From c3f100296606720d52282835c1b258a9191d0622 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 15 Nov 2024 15:21:24 -0600 Subject: [PATCH 1/2] scripts: pinctrl: gen_soc_headers.py: expand for additional families Expand the processor_to_controller() function in the gen_soc_headers.py implementation to support some additional SOC families the script can already handle. Signed-off-by: Daniel DeGrasse --- mcux/scripts/pinctrl/gen_soc_headers.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/mcux/scripts/pinctrl/gen_soc_headers.py b/mcux/scripts/pinctrl/gen_soc_headers.py index e16f35027..db5d9030a 100755 --- a/mcux/scripts/pinctrl/gen_soc_headers.py +++ b/mcux/scripts/pinctrl/gen_soc_headers.py @@ -69,12 +69,21 @@ def processor_to_controller(processor_name): if "IMXRT5" in processor_name: # LPC config tools return 'IOCON' - if "LPC55" in processor_name: + if "IMX8M" in processor_name: + # IMX config tools + return 'IOMUX' + if "IMX9" in processor_name: + # IMX config tools + return 'IOMUX' + if "LPC5" in processor_name: # LPC config tools return 'IOCON' if "MK" in processor_name: # Kinetis config tools return 'PORT' + if "K32" in processor_name: + # Kinetis config tools + return 'PORT' if "MCX" in processor_name: # Kinetis config tools return 'PORT' @@ -117,8 +126,8 @@ def main(): data_version = get_pack_version(temp_dir.name) print(f"Found data pack version {data_version}") - if round(data_version) != 14: - print("Warning: This tool is only verified for data pack version 14, " + if round(data_version) != 16: + print("Warning: This tool is only verified for data pack version 16, " "other versions may not work") # Attempt to locate the signal XML files we will generate from From 240116dd6a87348dc10b2caabcb5d89e0b2182f2 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 15 Nov 2024 15:32:00 -0600 Subject: [PATCH 2/2] dts: nxp: add pin control files for subset parts Add pin control files for subset parts within NXP HAL. Note that this does not add files for all parts supported by the NXP HAL, only for those that are already supported by the pin control tooling. This excludes a few part families: - MKE0* parts - LPC8* parts - LPC51* parts - MIMX8D*, MIMX8Q*, MIMX8U* parts Signed-off-by: Daniel DeGrasse --- dts/nxp/kinetis/K32L2A31VLH1A-pinctrl.h | 303 + dts/nxp/kinetis/K32L2A31VLL1A-pinctrl.h | 424 + dts/nxp/kinetis/K32L2A41VLH1A-pinctrl.h | 303 + dts/nxp/kinetis/K32L2A41VLL1A-pinctrl.h | 424 + dts/nxp/kinetis/K32L2B11VFM0A-pinctrl.h | 130 + dts/nxp/kinetis/K32L2B11VFT0A-pinctrl.h | 190 + dts/nxp/kinetis/K32L2B11VLH0A-pinctrl.h | 299 + dts/nxp/kinetis/K32L2B11VMP0A-pinctrl.h | 299 + dts/nxp/kinetis/K32L2B21VFM0A-pinctrl.h | 130 + dts/nxp/kinetis/K32L2B21VFT0A-pinctrl.h | 190 + dts/nxp/kinetis/K32L2B21VLH0A-pinctrl.h | 299 + dts/nxp/kinetis/K32L2B21VMP0A-pinctrl.h | 299 + dts/nxp/kinetis/K32L2B31VFM0A-pinctrl.h | 130 + dts/nxp/kinetis/K32L2B31VFT0A-pinctrl.h | 190 + dts/nxp/kinetis/K32L2B31VLH0A-pinctrl.h | 299 + dts/nxp/kinetis/K32L2B31VMP0A-pinctrl.h | 299 + dts/nxp/kinetis/K32L3A60VPJ1A-pinctrl.h | 561 ++ dts/nxp/kinetis/MK02FN128VFM10-pinctrl.h | 152 + dts/nxp/kinetis/MK02FN128VLF10-pinctrl.h | 187 + dts/nxp/kinetis/MK02FN128VLH10-pinctrl.h | 217 + dts/nxp/kinetis/MK22FN128VDC10-pinctrl.h | 320 + dts/nxp/kinetis/MK22FN128VLH10-pinctrl.h | 237 + dts/nxp/kinetis/MK22FN128VLL10-pinctrl.h | 318 + dts/nxp/kinetis/MK22FN128VMP10-pinctrl.h | 237 + dts/nxp/kinetis/MK22FN256CAH12-pinctrl.h | 236 + dts/nxp/kinetis/MK22FN256VDC12-pinctrl.h | 324 + dts/nxp/kinetis/MK22FN256VLH12-pinctrl.h | 236 + dts/nxp/kinetis/MK22FN256VLL12-pinctrl.h | 316 + dts/nxp/kinetis/MK22FN256VMP12-pinctrl.h | 236 + dts/nxp/kinetis/MK24FN1M0CAJ12-pinctrl.h | 463 ++ dts/nxp/kinetis/MK24FN1M0VDC12-pinctrl.h | 415 + dts/nxp/kinetis/MK24FN1M0VLL12-pinctrl.h | 363 + dts/nxp/kinetis/MK24FN1M0VLQ12-pinctrl.h | 461 ++ dts/nxp/kinetis/MK24FN256VDC12-pinctrl.h | 386 + dts/nxp/kinetis/MK26FN2M0CAC18-pinctrl.h | 631 ++ dts/nxp/kinetis/MK26FN2M0VLQ18-pinctrl.h | 556 ++ dts/nxp/kinetis/MK26FN2M0VMD18-pinctrl.h | 556 ++ dts/nxp/kinetis/MK26FN2M0VMI18-pinctrl.h | 631 ++ dts/nxp/kinetis/MK27FN2M0AVMI15-pinctrl.h | 716 ++ dts/nxp/kinetis/MK27FN2M0VMI15-pinctrl.h | 716 ++ dts/nxp/kinetis/MK28FN2M0ACAU15R-pinctrl.h | 716 ++ dts/nxp/kinetis/MK28FN2M0AVMI15-pinctrl.h | 716 ++ dts/nxp/kinetis/MK28FN2M0CAU15R-pinctrl.h | 716 ++ dts/nxp/kinetis/MK28FN2M0VMI15-pinctrl.h | 716 ++ dts/nxp/kinetis/MK63FN1M0VLQ12-pinctrl.h | 497 ++ dts/nxp/kinetis/MK63FN1M0VMD12-pinctrl.h | 479 ++ dts/nxp/kinetis/MK64FX512VDC12-pinctrl.h | 443 + dts/nxp/kinetis/MK64FX512VLL12-pinctrl.h | 387 + dts/nxp/kinetis/MK64FX512VLQ12-pinctrl.h | 497 ++ dts/nxp/kinetis/MK64FX512VMD12-pinctrl.h | 497 ++ dts/nxp/kinetis/MK65FN2M0CAC18-pinctrl.h | 675 ++ dts/nxp/kinetis/MK65FN2M0VMI18-pinctrl.h | 675 ++ dts/nxp/kinetis/MK65FX1M0CAC18-pinctrl.h | 675 ++ dts/nxp/kinetis/MK65FX1M0VMI18-pinctrl.h | 675 ++ dts/nxp/kinetis/MK66FX1M0VLQ18-pinctrl.h | 596 ++ dts/nxp/kinetis/MK66FX1M0VMD18-pinctrl.h | 596 ++ dts/nxp/kinetis/MK80FN256CAX15-pinctrl.h | 555 ++ dts/nxp/kinetis/MK80FN256VDC15-pinctrl.h | 555 ++ dts/nxp/kinetis/MK80FN256VLL15-pinctrl.h | 473 ++ dts/nxp/kinetis/MK80FN256VLQ15-pinctrl.h | 630 ++ dts/nxp/kinetis/MKE12Z128VLF7-pinctrl.h | 205 + dts/nxp/kinetis/MKE12Z128VLH7-pinctrl.h | 245 + dts/nxp/kinetis/MKE12Z128VLL7-pinctrl.h | 339 + dts/nxp/kinetis/MKE12Z256VLF7-pinctrl.h | 205 + dts/nxp/kinetis/MKE12Z256VLH7-pinctrl.h | 245 + dts/nxp/kinetis/MKE12Z256VLL7-pinctrl.h | 339 + dts/nxp/kinetis/MKE12Z512VLH9-pinctrl.h | 275 + dts/nxp/kinetis/MKE12Z512VLL9-pinctrl.h | 378 + dts/nxp/kinetis/MKE13Z128VLF7-pinctrl.h | 220 + dts/nxp/kinetis/MKE13Z128VLH7-pinctrl.h | 267 + dts/nxp/kinetis/MKE13Z128VLL7-pinctrl.h | 364 + dts/nxp/kinetis/MKE13Z256VLF7-pinctrl.h | 220 + dts/nxp/kinetis/MKE13Z256VLH7-pinctrl.h | 267 + dts/nxp/kinetis/MKE13Z256VLL7-pinctrl.h | 364 + dts/nxp/kinetis/MKE13Z512VLH9-pinctrl.h | 297 + dts/nxp/kinetis/MKE13Z512VLL9-pinctrl.h | 403 + dts/nxp/kinetis/MKE14Z128VLH7-pinctrl.h | 280 + dts/nxp/kinetis/MKE14Z128VLL7-pinctrl.h | 361 + dts/nxp/kinetis/MKE14Z256VLH7-pinctrl.h | 280 + dts/nxp/kinetis/MKE14Z256VLL7-pinctrl.h | 361 + dts/nxp/kinetis/MKE14Z32VFP4-pinctrl.h | 155 + dts/nxp/kinetis/MKE14Z32VLD4-pinctrl.h | 163 + dts/nxp/kinetis/MKE14Z32VLF4-pinctrl.h | 173 + dts/nxp/kinetis/MKE14Z64VFP4-pinctrl.h | 155 + dts/nxp/kinetis/MKE14Z64VLD4-pinctrl.h | 163 + dts/nxp/kinetis/MKE14Z64VLF4-pinctrl.h | 173 + dts/nxp/kinetis/MKE15Z128VLH7-pinctrl.h | 305 + dts/nxp/kinetis/MKE15Z128VLL7-pinctrl.h | 386 + dts/nxp/kinetis/MKL27Z256VFM4-pinctrl.h | 138 + dts/nxp/kinetis/MKL27Z256VFT4-pinctrl.h | 199 + dts/nxp/kinetis/MKL27Z256VLH4-pinctrl.h | 257 + dts/nxp/kinetis/MKL27Z256VMP4-pinctrl.h | 257 + dts/nxp/kinetis/MKL27Z64VDA4-pinctrl.h | 183 + dts/nxp/kinetis/MKL27Z64VFM4-pinctrl.h | 144 + dts/nxp/kinetis/MKL27Z64VFT4-pinctrl.h | 203 + dts/nxp/kinetis/MKL27Z64VLH4-pinctrl.h | 252 + dts/nxp/kinetis/MKL27Z64VMP4-pinctrl.h | 252 + dts/nxp/kinetis/MKM35Z512VLL7-pinctrl.h | 217 + dts/nxp/kinetis/MKV31F512VLH12-pinctrl.h | 278 + dts/nxp/kinetis/MKV31F512VLL12-pinctrl.h | 346 + dts/nxp/lpc/LPC54005JBD100-pinctrl.h | 3116 +++++++ dts/nxp/lpc/LPC54005JET100-pinctrl.h | 3116 +++++++ dts/nxp/lpc/LPC54016JBD100-pinctrl.h | 3143 ++++++++ dts/nxp/lpc/LPC54016JBD208-pinctrl.h | 3766 +++++++++ dts/nxp/lpc/LPC54016JET100-pinctrl.h | 3143 ++++++++ dts/nxp/lpc/LPC54016JET180-pinctrl.h | 3571 +++++++++ dts/nxp/lpc/LPC54018J2MET180-pinctrl.h | 3304 ++++++++ dts/nxp/lpc/LPC54018J4MET180-pinctrl.h | 3304 ++++++++ dts/nxp/lpc/LPC54018JBD208-pinctrl.h | 3801 +++++++++ dts/nxp/lpc/LPC54018JET180-pinctrl.h | 3606 +++++++++ dts/nxp/lpc/LPC54113J128BD64-pinctrl.h | 1694 ++++ dts/nxp/lpc/LPC54113J256BD64-pinctrl.h | 1694 ++++ dts/nxp/lpc/LPC54113J256UK49-pinctrl.h | 1316 +++ dts/nxp/lpc/LPC54605J256BD100-pinctrl.h | 3111 +++++++ dts/nxp/lpc/LPC54605J256ET100-pinctrl.h | 3111 +++++++ dts/nxp/lpc/LPC54605J256ET180-pinctrl.h | 3516 ++++++++ dts/nxp/lpc/LPC54605J512BD100-pinctrl.h | 3111 +++++++ dts/nxp/lpc/LPC54605J512ET100-pinctrl.h | 3111 +++++++ dts/nxp/lpc/LPC54605J512ET180-pinctrl.h | 3516 ++++++++ dts/nxp/lpc/LPC54606J256BD100-pinctrl.h | 3138 ++++++++ dts/nxp/lpc/LPC54606J256ET100-pinctrl.h | 3138 ++++++++ dts/nxp/lpc/LPC54606J256ET180-pinctrl.h | 3563 ++++++++ dts/nxp/lpc/LPC54606J512BD100-pinctrl.h | 3138 ++++++++ dts/nxp/lpc/LPC54606J512BD208-pinctrl.h | 3758 +++++++++ dts/nxp/lpc/LPC54606J512ET100-pinctrl.h | 3138 ++++++++ dts/nxp/lpc/LPC54607J256BD208-pinctrl.h | 3726 +++++++++ dts/nxp/lpc/LPC54607J256ET180-pinctrl.h | 3551 ++++++++ dts/nxp/lpc/LPC54607J512ET180-pinctrl.h | 3551 ++++++++ dts/nxp/lpc/LPC54608J512BD208-pinctrl.h | 3793 +++++++++ dts/nxp/lpc/LPC54608J512ET180-pinctrl.h | 3598 +++++++++ dts/nxp/lpc/LPC54616J256ET180-pinctrl.h | 3563 ++++++++ dts/nxp/lpc/LPC54616J512BD100-pinctrl.h | 3138 ++++++++ dts/nxp/lpc/LPC54616J512BD208-pinctrl.h | 3758 +++++++++ dts/nxp/lpc/LPC54616J512ET100-pinctrl.h | 3138 ++++++++ dts/nxp/lpc/LPC54618J512BD208-pinctrl.h | 3793 +++++++++ dts/nxp/lpc/LPC54618J512ET180-pinctrl.h | 3598 +++++++++ dts/nxp/lpc/LPC54628J512ET180-pinctrl.h | 3598 +++++++++ dts/nxp/lpc/LPC54S005JBD100-pinctrl.h | 3116 +++++++ dts/nxp/lpc/LPC54S005JET100-pinctrl.h | 3116 +++++++ dts/nxp/lpc/LPC54S016JBD100-pinctrl.h | 3143 ++++++++ dts/nxp/lpc/LPC54S016JBD208-pinctrl.h | 3766 +++++++++ dts/nxp/lpc/LPC54S016JET100-pinctrl.h | 3143 ++++++++ dts/nxp/lpc/LPC54S016JET180-pinctrl.h | 3571 +++++++++ dts/nxp/lpc/LPC54S018J2MET180-pinctrl.h | 3304 ++++++++ dts/nxp/lpc/LPC54S018J4MET180-pinctrl.h | 3304 ++++++++ dts/nxp/lpc/LPC54S018JBD208-pinctrl.h | 3801 +++++++++ dts/nxp/lpc/LPC54S018JET180-pinctrl.h | 3606 +++++++++ dts/nxp/lpc/LPC5502JBD64-pinctrl.h | 2691 +++++++ dts/nxp/lpc/LPC5502JHI48-pinctrl.h | 1849 +++++ dts/nxp/lpc/LPC5504JBD64-pinctrl.h | 2691 +++++++ dts/nxp/lpc/LPC5504JHI48-pinctrl.h | 1849 +++++ dts/nxp/lpc/LPC5506JBD64-pinctrl.h | 2691 +++++++ dts/nxp/lpc/LPC5506JHI48-pinctrl.h | 1849 +++++ dts/nxp/lpc/LPC5512JBD100-pinctrl.h | 3694 +++++++++ dts/nxp/lpc/LPC5512JBD64-pinctrl.h | 2237 ++++++ dts/nxp/lpc/LPC5514JBD100-pinctrl.h | 3700 +++++++++ dts/nxp/lpc/LPC5514JBD64-pinctrl.h | 2239 ++++++ dts/nxp/lpc/LPC5514JEV59-pinctrl.h | 2269 ++++++ dts/nxp/lpc/LPC5516JBD100-pinctrl.h | 3700 +++++++++ dts/nxp/lpc/LPC5516JBD64-pinctrl.h | 2239 ++++++ dts/nxp/lpc/LPC5516JEV59-pinctrl.h | 2269 ++++++ dts/nxp/lpc/LPC5516JEV98-pinctrl.h | 3700 +++++++++ dts/nxp/lpc/LPC5526JBD100-pinctrl.h | 3734 +++++++++ dts/nxp/lpc/LPC5526JBD64-pinctrl.h | 2254 ++++++ dts/nxp/lpc/LPC5526JEV98-pinctrl.h | 3734 +++++++++ dts/nxp/lpc/LPC5528JBD100-pinctrl.h | 3734 +++++++++ dts/nxp/lpc/LPC5528JBD64-pinctrl.h | 2254 ++++++ dts/nxp/lpc/LPC5528JEV59-pinctrl.h | 2285 ++++++ dts/nxp/lpc/LPC5528JEV98-pinctrl.h | 3734 +++++++++ dts/nxp/lpc/LPC5534JBD100-pinctrl.h | 7141 +++++++++++++++++ dts/nxp/lpc/LPC5534JBD64-pinctrl.h | 4538 +++++++++++ dts/nxp/lpc/LPC5534JHI48-pinctrl.h | 3714 +++++++++ dts/nxp/lpc/LPC5536JBD100-pinctrl.h | 7141 +++++++++++++++++ dts/nxp/lpc/LPC5536JBD64-pinctrl.h | 4538 +++++++++++ dts/nxp/lpc/LPC5536JHI48-pinctrl.h | 3714 +++++++++ dts/nxp/lpc/LPC55S04JBD64-pinctrl.h | 2691 +++++++ dts/nxp/lpc/LPC55S04JHI48-pinctrl.h | 1849 +++++ dts/nxp/lpc/LPC55S14JBD100-pinctrl.h | 3700 +++++++++ dts/nxp/lpc/LPC55S14JBD64-pinctrl.h | 2239 ++++++ dts/nxp/lpc/LPC55S14JEV59-pinctrl.h | 2269 ++++++ dts/nxp/lpc/LPC55S16JEV59-pinctrl.h | 2269 ++++++ dts/nxp/lpc/LPC55S26JBD100-pinctrl.h | 3734 +++++++++ dts/nxp/lpc/LPC55S26JBD64-pinctrl.h | 2254 ++++++ dts/nxp/lpc/LPC55S26JEV98-pinctrl.h | 3734 +++++++++ dts/nxp/lpc/LPC55S28JEV59-pinctrl.h | 2285 ++++++ dts/nxp/lpc/LPC55S66JBD100-pinctrl.h | 3734 +++++++++ dts/nxp/lpc/LPC55S66JBD64-pinctrl.h | 2254 ++++++ dts/nxp/lpc/LPC55S66JEV98-pinctrl.h | 3734 +++++++++ dts/nxp/lpc/LPC55S69JEV59-pinctrl.h | 2285 ++++++ dts/nxp/mcx/MCXA142VFM-pinctrl.h | 188 + dts/nxp/mcx/MCXA142VFT-pinctrl.h | 272 + dts/nxp/mcx/MCXA142VLF-pinctrl.h | 254 + dts/nxp/mcx/MCXA142VLH-pinctrl.h | 327 + dts/nxp/mcx/MCXA143VFM-pinctrl.h | 188 + dts/nxp/mcx/MCXA143VFT-pinctrl.h | 272 + dts/nxp/mcx/MCXA143VLF-pinctrl.h | 254 + dts/nxp/mcx/MCXA143VLH-pinctrl.h | 327 + dts/nxp/mcx/MCXA144VFT-pinctrl.h | 349 + dts/nxp/mcx/MCXA144VLH-pinctrl.h | 432 + dts/nxp/mcx/MCXA144VLL-pinctrl.h | 601 ++ dts/nxp/mcx/MCXA144VMP-pinctrl.h | 416 + dts/nxp/mcx/MCXA144VPJ-pinctrl.h | 605 ++ dts/nxp/mcx/MCXA145VFT-pinctrl.h | 349 + dts/nxp/mcx/MCXA145VLH-pinctrl.h | 432 + dts/nxp/mcx/MCXA145VLL-pinctrl.h | 601 ++ dts/nxp/mcx/MCXA145VMP-pinctrl.h | 416 + dts/nxp/mcx/MCXA145VPJ-pinctrl.h | 605 ++ dts/nxp/mcx/MCXA146VFT-pinctrl.h | 349 + dts/nxp/mcx/MCXA146VLH-pinctrl.h | 432 + dts/nxp/mcx/MCXA146VLL-pinctrl.h | 601 ++ dts/nxp/mcx/MCXA146VMP-pinctrl.h | 416 + dts/nxp/mcx/MCXA146VPJ-pinctrl.h | 605 ++ dts/nxp/mcx/MCXA152VFM-pinctrl.h | 188 + dts/nxp/mcx/MCXA152VFT-pinctrl.h | 272 + dts/nxp/mcx/MCXA152VLF-pinctrl.h | 254 + dts/nxp/mcx/MCXA152VLH-pinctrl.h | 327 + dts/nxp/mcx/MCXA153VFM-pinctrl.h | 188 + dts/nxp/mcx/MCXA153VFT-pinctrl.h | 272 + dts/nxp/mcx/MCXA153VLF-pinctrl.h | 254 + dts/nxp/mcx/MCXA153VLH-pinctrl.h | 327 + dts/nxp/mcx/MCXA154VFT-pinctrl.h | 359 + dts/nxp/mcx/MCXA154VLH-pinctrl.h | 445 + dts/nxp/mcx/MCXA154VLL-pinctrl.h | 619 ++ dts/nxp/mcx/MCXA154VMP-pinctrl.h | 429 + dts/nxp/mcx/MCXA154VPJ-pinctrl.h | 624 ++ dts/nxp/mcx/MCXA155VFT-pinctrl.h | 359 + dts/nxp/mcx/MCXA155VLH-pinctrl.h | 445 + dts/nxp/mcx/MCXA155VLL-pinctrl.h | 619 ++ dts/nxp/mcx/MCXA155VMP-pinctrl.h | 429 + dts/nxp/mcx/MCXA155VPJ-pinctrl.h | 624 ++ dts/nxp/mcx/MCXA156VFT-pinctrl.h | 359 + dts/nxp/mcx/MCXA156VLH-pinctrl.h | 445 + dts/nxp/mcx/MCXC041VFG-pinctrl.h | 79 + dts/nxp/mcx/MCXC041VFK-pinctrl.h | 110 + dts/nxp/mcx/MCXC143VFM-pinctrl.h | 171 + dts/nxp/mcx/MCXC143VFT-pinctrl.h | 226 + dts/nxp/mcx/MCXC144VFM-pinctrl.h | 171 + dts/nxp/mcx/MCXC144VFT-pinctrl.h | 226 + dts/nxp/mcx/MCXC243VFT-pinctrl.h | 199 + dts/nxp/mcx/MCXC244VFM-pinctrl.h | 138 + dts/nxp/mcx/MCXC244VFT-pinctrl.h | 199 + dts/nxp/mcx/MCXC443VLH-pinctrl.h | 313 + dts/nxp/mcx/MCXC443VMP-pinctrl.h | 313 + dts/nxp/mcx/MCXN235VDF-pinctrl.h | 759 ++ dts/nxp/mcx/MCXN235VNL-pinctrl.h | 579 ++ dts/nxp/mcx/MCXN235VPB-pinctrl.h | 742 ++ dts/nxp/mcx/MCXN236VPB-pinctrl.h | 742 ++ dts/nxp/mcx/MCXN546VDF-pinctrl.h | 1003 +++ dts/nxp/mcx/MCXN546VNL-pinctrl.h | 695 ++ dts/nxp/mcx/MCXN546VPB-pinctrl.h | 933 +++ dts/nxp/mcx/MCXN547VDF-pinctrl.h | 1003 +++ dts/nxp/mcx/MCXN547VNL-pinctrl.h | 695 ++ dts/nxp/mcx/MCXN547VPB-pinctrl.h | 933 +++ dts/nxp/mcx/MCXN946VDF-pinctrl.h | 1022 +++ dts/nxp/mcx/MCXN946VNL-pinctrl.h | 731 ++ dts/nxp/mcx/MCXN946VPB-pinctrl.h | 947 +++ dts/nxp/mcx/MCXN947VPB-pinctrl.h | 1003 +++ dts/nxp/mcx/MCXW716AMFPA-pinctrl.h | 179 + dts/nxp/mcx/MCXW716AMFTA-pinctrl.h | 225 + dts/nxp/nxp_imx/mimx8md6cvahz-pinctrl.dtsi | 1489 ++++ dts/nxp/nxp_imx/mimx8md6dvajz-pinctrl.dtsi | 1489 ++++ dts/nxp/nxp_imx/mimx8md7cvahz-pinctrl.dtsi | 1489 ++++ dts/nxp/nxp_imx/mimx8md7dvajz-pinctrl.dtsi | 1489 ++++ dts/nxp/nxp_imx/mimx8ml6cvnkz-pinctrl.dtsi | 2404 ++++++ dts/nxp/nxp_imx/mimx8ml6dvnlz-pinctrl.dtsi | 2404 ++++++ dts/nxp/nxp_imx/mimx8ml8cvnkz-pinctrl.dtsi | 2404 ++++++ dts/nxp/nxp_imx/mimx8mm1cvtkz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mm1dvtlz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mm2cvtkz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mm2dvtlz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mm3cvtkz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mm3dvtlz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mm4cvtkz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mm4dvtlz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mm5cvtkz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mm5dvtlz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mm6cvtkz-pinctrl.dtsi | 1648 ++++ dts/nxp/nxp_imx/mimx8mn1cvpiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn1cvtiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn1dvpiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn1dvtjz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn2cvtiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn2dvtjz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn3cvpiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn3cvtiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn3dvpiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn3dvtjz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn4cvtiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn4dvtjz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn5cvpiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn5cvtiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn5dvpiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn5dvtjz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mn6cvtiz-pinctrl.dtsi | 1894 +++++ dts/nxp/nxp_imx/mimx8mq5cvahz-pinctrl.dtsi | 1489 ++++ dts/nxp/nxp_imx/mimx8mq5dvajz-pinctrl.dtsi | 1489 ++++ dts/nxp/nxp_imx/mimx8mq6cvahz-pinctrl.dtsi | 1489 ++++ dts/nxp/nxp_imx/mimx8mq7cvahz-pinctrl.dtsi | 1489 ++++ dts/nxp/nxp_imx/mimx8mq7dvajz-pinctrl.dtsi | 1489 ++++ dts/nxp/nxp_imx/mimx9351avtxm-pinctrl.dtsi | 1831 +++++ dts/nxp/nxp_imx/mimx9351cvvxm-pinctrl.dtsi | 1831 +++++ dts/nxp/nxp_imx/mimx9351dvvxm-pinctrl.dtsi | 1831 +++++ dts/nxp/nxp_imx/mimx9351xvvxm-pinctrl.dtsi | 1831 +++++ dts/nxp/nxp_imx/mimx9352avtxm-pinctrl.dtsi | 1831 +++++ dts/nxp/nxp_imx/mimx9352cvvxm-pinctrl.dtsi | 1831 +++++ dts/nxp/nxp_imx/mimx9352dvvxm-pinctrl.dtsi | 1831 +++++ dts/nxp/nxp_imx/mimx9352xvvxm-pinctrl.dtsi | 1831 +++++ dts/nxp/nxp_imx/mimx9596cvtxn-pinctrl.dtsi | 2167 +++++ dts/nxp/nxp_imx/rt/MIMXRT533SFAWC-pinctrl.h | 4882 +++++++++++ dts/nxp/nxp_imx/rt/MIMXRT533SFFOC-pinctrl.h | 5843 ++++++++++++++ dts/nxp/nxp_imx/rt/MIMXRT555SFAWC-pinctrl.h | 4905 +++++++++++ dts/nxp/nxp_imx/rt/MIMXRT555SFFOC-pinctrl.h | 5893 ++++++++++++++ dts/nxp/nxp_imx/rt/MIMXRT633SFAWBR-pinctrl.h | 4290 ++++++++++ dts/nxp/nxp_imx/rt/MIMXRT633SFFOB-pinctrl.h | 5979 ++++++++++++++ dts/nxp/nxp_imx/rt/MIMXRT633SFVKB-pinctrl.h | 5790 +++++++++++++ .../nxp_imx/rt/mimxrt1015caf4b-pinctrl.dtsi | 860 ++ .../nxp_imx/rt/mimxrt1015daf5b-pinctrl.dtsi | 860 ++ .../nxp_imx/rt/mimxrt1021caf4b-pinctrl.dtsi | 1284 +++ .../nxp_imx/rt/mimxrt1021cag4b-pinctrl.dtsi | 2311 ++++++ .../nxp_imx/rt/mimxrt1021daf5b-pinctrl.dtsi | 1284 +++ .../nxp_imx/rt/mimxrt1021dag5b-pinctrl.dtsi | 2311 ++++++ .../nxp_imx/rt/mimxrt1024cag4b-pinctrl.dtsi | 2131 +++++ .../nxp_imx/rt/mimxrt1024dag5b-pinctrl.dtsi | 2131 +++++ .../nxp_imx/rt/mimxrt1041dfp6b-pinctrl.dtsi | 3116 +++++++ .../nxp_imx/rt/mimxrt1041djm6b-pinctrl.dtsi | 3116 +++++++ .../nxp_imx/rt/mimxrt1041xfp5b-pinctrl.dtsi | 3116 +++++++ .../nxp_imx/rt/mimxrt1041xjm5b-pinctrl.dtsi | 3116 +++++++ .../nxp_imx/rt/mimxrt1042djm6b-pinctrl.dtsi | 3200 ++++++++ .../nxp_imx/rt/mimxrt1064cvj5b-pinctrl.dtsi | 3925 +++++++++ .../nxp_imx/rt/mimxrt1064cvl5b-pinctrl.dtsi | 3925 +++++++++ .../nxp_imx/rt/mimxrt1064dvj6b-pinctrl.dtsi | 3925 +++++++++ .../nxp_imx/rt/mimxrt1064dvl6b-pinctrl.dtsi | 3925 +++++++++ .../nxp_imx/rt/mimxrt1165cvm5a-pinctrl.dtsi | 5984 ++++++++++++++ .../nxp_imx/rt/mimxrt1165dvm6a-pinctrl.dtsi | 5984 ++++++++++++++ .../nxp_imx/rt/mimxrt1165xvm5a-pinctrl.dtsi | 5984 ++++++++++++++ .../nxp_imx/rt/mimxrt1172avm8a-pinctrl.dtsi | 6212 ++++++++++++++ .../nxp_imx/rt/mimxrt1172cvm8a-pinctrl.dtsi | 6212 ++++++++++++++ .../nxp_imx/rt/mimxrt1172dvmaa-pinctrl.dtsi | 6212 ++++++++++++++ .../nxp_imx/rt/mimxrt1173cvm8a-pinctrl.dtsi | 6212 ++++++++++++++ 339 files changed, 565710 insertions(+) create mode 100644 dts/nxp/kinetis/K32L2A31VLH1A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2A31VLL1A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2A41VLH1A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2A41VLL1A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B11VFM0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B11VFT0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B11VLH0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B11VMP0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B21VFM0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B21VFT0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B21VLH0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B21VMP0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B31VFM0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B31VFT0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B31VLH0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L2B31VMP0A-pinctrl.h create mode 100644 dts/nxp/kinetis/K32L3A60VPJ1A-pinctrl.h create mode 100644 dts/nxp/kinetis/MK02FN128VFM10-pinctrl.h create mode 100644 dts/nxp/kinetis/MK02FN128VLF10-pinctrl.h create mode 100644 dts/nxp/kinetis/MK02FN128VLH10-pinctrl.h create mode 100644 dts/nxp/kinetis/MK22FN128VDC10-pinctrl.h create mode 100644 dts/nxp/kinetis/MK22FN128VLH10-pinctrl.h create mode 100644 dts/nxp/kinetis/MK22FN128VLL10-pinctrl.h create mode 100644 dts/nxp/kinetis/MK22FN128VMP10-pinctrl.h create mode 100644 dts/nxp/kinetis/MK22FN256CAH12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK22FN256VDC12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK22FN256VLH12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK22FN256VLL12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK22FN256VMP12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK24FN1M0CAJ12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK24FN1M0VDC12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK24FN1M0VLL12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK24FN1M0VLQ12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK24FN256VDC12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK26FN2M0CAC18-pinctrl.h create mode 100644 dts/nxp/kinetis/MK26FN2M0VLQ18-pinctrl.h create mode 100644 dts/nxp/kinetis/MK26FN2M0VMD18-pinctrl.h create mode 100644 dts/nxp/kinetis/MK26FN2M0VMI18-pinctrl.h create mode 100644 dts/nxp/kinetis/MK27FN2M0AVMI15-pinctrl.h create mode 100644 dts/nxp/kinetis/MK27FN2M0VMI15-pinctrl.h create mode 100644 dts/nxp/kinetis/MK28FN2M0ACAU15R-pinctrl.h create mode 100644 dts/nxp/kinetis/MK28FN2M0AVMI15-pinctrl.h create mode 100644 dts/nxp/kinetis/MK28FN2M0CAU15R-pinctrl.h create mode 100644 dts/nxp/kinetis/MK28FN2M0VMI15-pinctrl.h create mode 100644 dts/nxp/kinetis/MK63FN1M0VLQ12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK63FN1M0VMD12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK64FX512VDC12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK64FX512VLL12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK64FX512VLQ12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK64FX512VMD12-pinctrl.h create mode 100644 dts/nxp/kinetis/MK65FN2M0CAC18-pinctrl.h create mode 100644 dts/nxp/kinetis/MK65FN2M0VMI18-pinctrl.h create mode 100644 dts/nxp/kinetis/MK65FX1M0CAC18-pinctrl.h create mode 100644 dts/nxp/kinetis/MK65FX1M0VMI18-pinctrl.h create mode 100644 dts/nxp/kinetis/MK66FX1M0VLQ18-pinctrl.h create mode 100644 dts/nxp/kinetis/MK66FX1M0VMD18-pinctrl.h create mode 100644 dts/nxp/kinetis/MK80FN256CAX15-pinctrl.h create mode 100644 dts/nxp/kinetis/MK80FN256VDC15-pinctrl.h create mode 100644 dts/nxp/kinetis/MK80FN256VLL15-pinctrl.h create mode 100644 dts/nxp/kinetis/MK80FN256VLQ15-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE12Z128VLF7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE12Z128VLH7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE12Z128VLL7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE12Z256VLF7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE12Z256VLH7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE12Z256VLL7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE12Z512VLH9-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE12Z512VLL9-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE13Z128VLF7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE13Z128VLH7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE13Z128VLL7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE13Z256VLF7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE13Z256VLH7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE13Z256VLL7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE13Z512VLH9-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE13Z512VLL9-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE14Z128VLH7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE14Z128VLL7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE14Z256VLH7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE14Z256VLL7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE14Z32VFP4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE14Z32VLD4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE14Z32VLF4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE14Z64VFP4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE14Z64VLD4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE14Z64VLF4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE15Z128VLH7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKE15Z128VLL7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKL27Z256VFM4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKL27Z256VFT4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKL27Z256VLH4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKL27Z256VMP4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKL27Z64VDA4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKL27Z64VFM4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKL27Z64VFT4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKL27Z64VLH4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKL27Z64VMP4-pinctrl.h create mode 100644 dts/nxp/kinetis/MKM35Z512VLL7-pinctrl.h create mode 100644 dts/nxp/kinetis/MKV31F512VLH12-pinctrl.h create mode 100644 dts/nxp/kinetis/MKV31F512VLL12-pinctrl.h create mode 100644 dts/nxp/lpc/LPC54005JBD100-pinctrl.h create mode 100644 dts/nxp/lpc/LPC54005JET100-pinctrl.h create mode 100644 dts/nxp/lpc/LPC54016JBD100-pinctrl.h create mode 100644 dts/nxp/lpc/LPC54016JBD208-pinctrl.h create mode 100644 dts/nxp/lpc/LPC54016JET100-pinctrl.h create mode 100644 dts/nxp/lpc/LPC54016JET180-pinctrl.h create mode 100644 dts/nxp/lpc/LPC54018J2MET180-pinctrl.h create mode 100644 dts/nxp/lpc/LPC54018J4MET180-pinctrl.h create mode 100644 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dts/nxp/nxp_imx/rt/mimxrt1165cvm5a-pinctrl.dtsi create mode 100644 dts/nxp/nxp_imx/rt/mimxrt1165dvm6a-pinctrl.dtsi create mode 100644 dts/nxp/nxp_imx/rt/mimxrt1165xvm5a-pinctrl.dtsi create mode 100644 dts/nxp/nxp_imx/rt/mimxrt1172avm8a-pinctrl.dtsi create mode 100644 dts/nxp/nxp_imx/rt/mimxrt1172cvm8a-pinctrl.dtsi create mode 100644 dts/nxp/nxp_imx/rt/mimxrt1172dvmaa-pinctrl.dtsi create mode 100644 dts/nxp/nxp_imx/rt/mimxrt1173cvm8a-pinctrl.dtsi diff --git a/dts/nxp/kinetis/K32L2A31VLH1A-pinctrl.h b/dts/nxp/kinetis/K32L2A31VLH1A-pinctrl.h new file mode 100644 index 000000000..0b239504a --- /dev/null +++ b/dts/nxp/kinetis/K32L2A31VLH1A-pinctrl.h @@ -0,0 +1,303 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2A31VLH1A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2A31VLH1A_ +#define _ZEPHYR_DTS_BINDING_K32L2A31VLH1A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPI2C0_SDAS_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPI2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI0_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define LPI2C2_HREQ_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define LPI2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define LPI2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM0_CLKIN_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM1_CLKIN_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define LPI2C0_SCLS_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define TPM2_CLKIN_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPI2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FXIO0_D8_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPI2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FXIO0_D9_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define LPI2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FXIO0_D10_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define LPI2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LPSPI1_PCS3_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FXIO0_D11_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define LPSPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM0_CLKIN_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define LPSPI2_PCS3_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define FXIO0_D16_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define LPSPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM1_CLKIN_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define LPSPI2_PCS2_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define FXIO0_D17_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LPI2C1_HREQ_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FXIO0_D18_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define LPSPI2_PCS1_PTB19 KINETIS_MUX('B',19,5) /* PTB_19 */ +#define FXIO0_D19_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define LPSPI2_PCS1_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LPI2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define LPI2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LPSPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LPSPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LPSPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPSPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPSPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define FXIO0_D20_PTC7 KINETIS_MUX('C',7,6) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPI2C0_SCL_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define TPM0_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define FXIO0_D21_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPI2C0_SDA_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define TPM0_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define FXIO0_D22_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPI2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FXIO0_D23_PTC10 KINETIS_MUX('C',10,6) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPI2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LPSPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define LPSPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LPSPI1_PCS0_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPSPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPSPI1_SOUT_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPSPI1_SIN_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_SE16_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI1_SIN_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define ADC0_SE17_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define LPSPI2_SCK_PTE20 KINETIS_MUX('E',20,2) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define LPSPI2_SOUT_PTE21 KINETIS_MUX('E',21,2) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define LPSPI2_SIN_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define LPUART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define LPSPI2_PCS0_PTE23 KINETIS_MUX('E',23,2) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define LPUART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define ADC0_SE20_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define EMVSIM0_IO_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define LPI2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define ADC0_SE21_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define EMVSIM0_PD_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define LPI2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP1_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define EMVSIM0_CLK_PTE29 KINETIS_MUX('E',29,2) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM0_CLKIN_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP1_IN3_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define EMVSIM0_RST_PTE30 KINETIS_MUX('E',30,2) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM1_CLKIN_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define EMVSIM0_VCCEN_PTE31 KINETIS_MUX('E',31,2) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#define TPM2_CLKIN_PTE31 KINETIS_MUX('E',31,4) /* PTE_31 */ +#define LPI2C0_HREQ_PTE31 KINETIS_MUX('E',31,5) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/K32L2A31VLL1A-pinctrl.h b/dts/nxp/kinetis/K32L2A31VLL1A-pinctrl.h new file mode 100644 index 000000000..0303d9edf --- /dev/null +++ b/dts/nxp/kinetis/K32L2A31VLL1A-pinctrl.h @@ -0,0 +1,424 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2A31VLL1A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2A31VLL1A_ +#define _ZEPHYR_DTS_BINDING_K32L2A31VLL1A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPI2C0_SDAS_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPI2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI0_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define LPI2C2_HREQ_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define TPM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define TPM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPI2C2_SDAS_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define LPI2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define LPI2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define LPSPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define LPI2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define LPSPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define LPSPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define ADC0_SE22_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define LPSPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM0_CLKIN_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM1_CLKIN_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define LPI2C0_SCLS_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define TPM2_CLKIN_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPI2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FXIO0_D8_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPI2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FXIO0_D9_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define LPI2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FXIO0_D10_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define LPI2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LPSPI1_PCS3_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FXIO0_D11_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPSPI1_PCS1_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPSPI1_PCS0_PTB8 KINETIS_MUX('B',8,2) /* PTB_8 */ +#define FXIO0_D12_PTB8 KINETIS_MUX('B',8,6) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPSPI1_SCK_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define FXIO0_D13_PTB9 KINETIS_MUX('B',9,6) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define LPSPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define FXIO0_D14_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define LPSPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define TPM2_CLKIN_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define FXIO0_D15_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define LPSPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM0_CLKIN_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define LPSPI2_PCS3_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define FXIO0_D16_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define LPSPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM1_CLKIN_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define LPSPI2_PCS2_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define FXIO0_D17_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LPI2C1_HREQ_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FXIO0_D18_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define LPSPI2_PCS1_PTB19 KINETIS_MUX('B',19,5) /* PTB_19 */ +#define FXIO0_D19_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define LPSPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define LPSPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define LPSPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define LPSPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define LPSPI2_PCS1_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LPI2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define LPI2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LPSPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LPSPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LPSPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPSPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPSPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define FXIO0_D20_PTC7 KINETIS_MUX('C',7,6) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPI2C0_SCL_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define TPM0_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define FXIO0_D21_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPI2C0_SDA_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define TPM0_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define FXIO0_D22_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPI2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FXIO0_D23_PTC10 KINETIS_MUX('C',10,6) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPI2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPI2C1_SCLS_PTC12 KINETIS_MUX('C',12,2) /* PTC_12 */ +#define TPM0_CLKIN_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPI2C1_SDAS_PTC13 KINETIS_MUX('C',13,2) /* PTC_13 */ +#define TPM1_CLKIN_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define EMVSIM0_CLK_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define EMVSIM0_RST_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define EMVSIM0_VCCEN_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define EMVSIM0_IO_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define LPSPI0_PCS3_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define EMVSIM0_PD_PTC18 KINETIS_MUX('C',18,2) /* PTC_18 */ +#define LPSPI0_PCS2_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LPSPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define LPSPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LPSPI1_PCS0_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPSPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPSPI1_SOUT_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPSPI1_SIN_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_SE16_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI1_SIN_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define ADC0_SE17_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define ADC0_SE18_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define LPI2C1_SDAS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE19_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define LPSPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define LPI2C1_SCLS_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LPSPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define LPSPI1_PCS1_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI1_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define LPSPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define LPUART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM0_CLKIN_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define LPSPI1_PCS3_PTE16 KINETIS_MUX('E',16,5) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_DM1_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LPSPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define LPUART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define TPM1_CLKIN_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define LPTMR1_ALT3_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define FXIO0_D1_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_SE2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define ADC0_DP2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define LPSPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define LPUART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define LPI2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define FXIO0_D2_PTE18 KINETIS_MUX('E',18,6) /* PTE_18 */ +#define ADC0_SE6a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define ADC0_DM2_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define LPSPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define LPUART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define LPI2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define FXIO0_D3_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define LPSPI2_SCK_PTE20 KINETIS_MUX('E',20,2) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define LPSPI2_SOUT_PTE21 KINETIS_MUX('E',21,2) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define LPSPI2_SIN_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define LPUART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define LPSPI2_PCS0_PTE23 KINETIS_MUX('E',23,2) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define LPUART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define ADC0_SE20_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define EMVSIM0_IO_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define LPI2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define ADC0_SE21_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define EMVSIM0_PD_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define LPI2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define TPM0_CH5_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define LPI2C0_SCLS_PTE26 KINETIS_MUX('E',26,5) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP1_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define EMVSIM0_CLK_PTE29 KINETIS_MUX('E',29,2) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM0_CLKIN_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP1_IN3_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define EMVSIM0_RST_PTE30 KINETIS_MUX('E',30,2) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM1_CLKIN_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define EMVSIM0_VCCEN_PTE31 KINETIS_MUX('E',31,2) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#define TPM2_CLKIN_PTE31 KINETIS_MUX('E',31,4) /* PTE_31 */ +#define LPI2C0_HREQ_PTE31 KINETIS_MUX('E',31,5) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/K32L2A41VLH1A-pinctrl.h b/dts/nxp/kinetis/K32L2A41VLH1A-pinctrl.h new file mode 100644 index 000000000..e9f865288 --- /dev/null +++ b/dts/nxp/kinetis/K32L2A41VLH1A-pinctrl.h @@ -0,0 +1,303 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2A41VLH1A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2A41VLH1A_ +#define _ZEPHYR_DTS_BINDING_K32L2A41VLH1A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPI2C0_SDAS_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPI2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI0_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define LPI2C2_HREQ_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define LPI2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define LPI2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM0_CLKIN_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM1_CLKIN_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define LPI2C0_SCLS_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define TPM2_CLKIN_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPI2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FXIO0_D8_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPI2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FXIO0_D9_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define LPI2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FXIO0_D10_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define LPI2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LPSPI1_PCS3_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FXIO0_D11_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define LPSPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM0_CLKIN_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define LPSPI2_PCS3_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define FXIO0_D16_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define LPSPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM1_CLKIN_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define LPSPI2_PCS2_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define FXIO0_D17_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LPI2C1_HREQ_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FXIO0_D18_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define LPSPI2_PCS1_PTB19 KINETIS_MUX('B',19,5) /* PTB_19 */ +#define FXIO0_D19_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define LPSPI2_PCS1_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LPI2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define LPI2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LPSPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LPSPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LPSPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPSPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPSPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define FXIO0_D20_PTC7 KINETIS_MUX('C',7,6) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPI2C0_SCL_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define TPM0_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define FXIO0_D21_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPI2C0_SDA_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define TPM0_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define FXIO0_D22_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPI2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FXIO0_D23_PTC10 KINETIS_MUX('C',10,6) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPI2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LPSPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define LPSPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LPSPI1_PCS0_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPSPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPSPI1_SOUT_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPSPI1_SIN_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_SE16_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI1_SIN_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define ADC0_SE17_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define LPSPI2_SCK_PTE20 KINETIS_MUX('E',20,2) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define LPSPI2_SOUT_PTE21 KINETIS_MUX('E',21,2) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define LPSPI2_SIN_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define LPUART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define LPSPI2_PCS0_PTE23 KINETIS_MUX('E',23,2) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define LPUART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define ADC0_SE20_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define EMVSIM0_IO_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define LPI2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define ADC0_SE21_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define EMVSIM0_PD_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define LPI2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP1_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define EMVSIM0_CLK_PTE29 KINETIS_MUX('E',29,2) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM0_CLKIN_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP1_IN3_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define EMVSIM0_RST_PTE30 KINETIS_MUX('E',30,2) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM1_CLKIN_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define EMVSIM0_VCCEN_PTE31 KINETIS_MUX('E',31,2) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#define TPM2_CLKIN_PTE31 KINETIS_MUX('E',31,4) /* PTE_31 */ +#define LPI2C0_HREQ_PTE31 KINETIS_MUX('E',31,5) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/K32L2A41VLL1A-pinctrl.h b/dts/nxp/kinetis/K32L2A41VLL1A-pinctrl.h new file mode 100644 index 000000000..a54b8096e --- /dev/null +++ b/dts/nxp/kinetis/K32L2A41VLL1A-pinctrl.h @@ -0,0 +1,424 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2A41VLL1A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2A41VLL1A_ +#define _ZEPHYR_DTS_BINDING_K32L2A41VLL1A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPI2C0_SDAS_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPI2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI0_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define LPI2C2_HREQ_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define TPM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define TPM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPI2C2_SDAS_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define LPI2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define LPI2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define LPSPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define LPI2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define LPSPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define LPSPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define ADC0_SE22_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define LPSPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM0_CLKIN_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM1_CLKIN_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define LPI2C0_SCLS_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define TPM2_CLKIN_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPI2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FXIO0_D8_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPI2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FXIO0_D9_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define LPI2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FXIO0_D10_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define LPI2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LPSPI1_PCS3_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FXIO0_D11_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPSPI1_PCS1_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPSPI1_PCS0_PTB8 KINETIS_MUX('B',8,2) /* PTB_8 */ +#define FXIO0_D12_PTB8 KINETIS_MUX('B',8,6) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPSPI1_SCK_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define FXIO0_D13_PTB9 KINETIS_MUX('B',9,6) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define LPSPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define FXIO0_D14_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define LPSPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define TPM2_CLKIN_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define FXIO0_D15_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define LPSPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM0_CLKIN_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define LPSPI2_PCS3_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define FXIO0_D16_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define LPSPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM1_CLKIN_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define LPSPI2_PCS2_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define FXIO0_D17_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LPI2C1_HREQ_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FXIO0_D18_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define LPSPI2_PCS1_PTB19 KINETIS_MUX('B',19,5) /* PTB_19 */ +#define FXIO0_D19_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define LPSPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define LPSPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define LPSPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define LPSPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define LPSPI2_PCS1_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LPI2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define LPI2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LPSPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LPSPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LPSPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPSPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPSPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define FXIO0_D20_PTC7 KINETIS_MUX('C',7,6) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPI2C0_SCL_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define TPM0_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define FXIO0_D21_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPI2C0_SDA_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define TPM0_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define FXIO0_D22_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPI2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FXIO0_D23_PTC10 KINETIS_MUX('C',10,6) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPI2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPI2C1_SCLS_PTC12 KINETIS_MUX('C',12,2) /* PTC_12 */ +#define TPM0_CLKIN_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPI2C1_SDAS_PTC13 KINETIS_MUX('C',13,2) /* PTC_13 */ +#define TPM1_CLKIN_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define EMVSIM0_CLK_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define EMVSIM0_RST_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define EMVSIM0_VCCEN_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define EMVSIM0_IO_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define LPSPI0_PCS3_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define EMVSIM0_PD_PTC18 KINETIS_MUX('C',18,2) /* PTC_18 */ +#define LPSPI0_PCS2_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LPSPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define LPSPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LPSPI1_PCS0_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPSPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPSPI1_SOUT_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPSPI1_SIN_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_SE16_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI1_SIN_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define ADC0_SE17_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define ADC0_SE18_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define LPI2C1_SDAS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE19_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define LPSPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define LPI2C1_SCLS_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LPSPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define LPSPI1_PCS1_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI1_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define LPSPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define LPUART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM0_CLKIN_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define LPSPI1_PCS3_PTE16 KINETIS_MUX('E',16,5) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define ADC0_DM1_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LPSPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define LPUART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define TPM1_CLKIN_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR1_ALT3_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define FXIO0_D1_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_SE2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define ADC0_DP2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define LPSPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define LPUART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define LPI2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define FXIO0_D2_PTE18 KINETIS_MUX('E',18,6) /* PTE_18 */ +#define ADC0_DM2_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define ADC0_SE6a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define LPSPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define LPUART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define LPI2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define FXIO0_D3_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define LPSPI2_SCK_PTE20 KINETIS_MUX('E',20,2) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define LPSPI2_SOUT_PTE21 KINETIS_MUX('E',21,2) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define LPSPI2_SIN_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define LPUART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define LPSPI2_PCS0_PTE23 KINETIS_MUX('E',23,2) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define LPUART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define ADC0_SE20_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define EMVSIM0_IO_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define LPI2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define ADC0_SE21_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define EMVSIM0_PD_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define LPI2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define TPM0_CH5_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define LPI2C0_SCLS_PTE26 KINETIS_MUX('E',26,5) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP1_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define EMVSIM0_CLK_PTE29 KINETIS_MUX('E',29,2) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM0_CLKIN_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP1_IN3_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define EMVSIM0_RST_PTE30 KINETIS_MUX('E',30,2) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM1_CLKIN_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define EMVSIM0_VCCEN_PTE31 KINETIS_MUX('E',31,2) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#define TPM2_CLKIN_PTE31 KINETIS_MUX('E',31,4) /* PTE_31 */ +#define LPI2C0_HREQ_PTE31 KINETIS_MUX('E',31,5) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B11VFM0A-pinctrl.h b/dts/nxp/kinetis/K32L2B11VFM0A-pinctrl.h new file mode 100644 index 000000000..a0c12da73 --- /dev/null +++ b/dts/nxp/kinetis/K32L2B11VFM0A-pinctrl.h @@ -0,0 +1,130 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B11VFM0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B11VFM0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B11VFM0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B11VFT0A-pinctrl.h b/dts/nxp/kinetis/K32L2B11VFT0A-pinctrl.h new file mode 100644 index 000000000..c0a12e8ee --- /dev/null +++ b/dts/nxp/kinetis/K32L2B11VFT0A-pinctrl.h @@ -0,0 +1,190 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B11VFT0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B11VFT0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B11VFT0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B11VLH0A-pinctrl.h b/dts/nxp/kinetis/K32L2B11VLH0A-pinctrl.h new file mode 100644 index 000000000..9fcbeed24 --- /dev/null +++ b/dts/nxp/kinetis/K32L2B11VLH0A-pinctrl.h @@ -0,0 +1,299 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B11VLH0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B11VLH0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B11VLH0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define LCD_P0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LCD_P0_Fault_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define LCD_P1_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define LCD_P1_Fault_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define LCD_P2_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LCD_P2_Fault_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define LCD_P3_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LCD_P3_Fault_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define LCD_P12_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define LCD_P12_Fault_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define LCD_P13_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define LCD_P13_Fault_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define LCD_P14_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LCD_P14_Fault_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define LCD_P15_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define LCD_P15_Fault_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define LCD_P20_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define LCD_P20_Fault_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LCD_P21_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define LCD_P21_Fault_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define LCD_P22_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define LCD_P22_Fault_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define LCD_P23_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LCD_P23_Fault_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define LCD_P24_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define LCD_P24_Fault_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LCD_P25_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define LCD_P25_Fault_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define LCD_P26_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define LCD_P26_Fault_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define LCD_P27_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LCD_P27_Fault_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define VLL2_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define LCD_P4_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define PTC20 KINETIS_MUX('C',20,1) /* PTC_20 */ +#define LCD_P4_Fault_PTC20 KINETIS_MUX('C',20,7) /* PTC_20 */ +#define LCD_P5_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define VLL1_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define PTC21 KINETIS_MUX('C',21,1) /* PTC_21 */ +#define LCD_P5_Fault_PTC21 KINETIS_MUX('C',21,7) /* PTC_21 */ +#define VCAP2_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define LCD_P6_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define PTC22 KINETIS_MUX('C',22,1) /* PTC_22 */ +#define LCD_P6_Fault_PTC22 KINETIS_MUX('C',22,7) /* PTC_22 */ +#define LCD_P39_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define VCAP1_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define PTC23 KINETIS_MUX('C',23,1) /* PTC_23 */ +#define LCD_P39_Fault_PTC23 KINETIS_MUX('C',23,7) /* PTC_23 */ +#define LCD_P40_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define LCD_P40_Fault_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define LCD_P41_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LCD_P41_Fault_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LCD_P42_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define LCD_P42_Fault_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define LCD_P43_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LCD_P43_Fault_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LCD_P44_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define LCD_P44_Fault_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define LCD_P45_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LCD_P45_Fault_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define LCD_P46_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define LCD_P46_Fault_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define LCD_P47_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define LCD_P47_Fault_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LCD_P48_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define LCD_P48_Fault_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LCD_P49_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define LCD_P49_Fault_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define LCD_P59_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define LCD_P59_Fault_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define LCD_P60_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define LCD_P60_Fault_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B11VMP0A-pinctrl.h b/dts/nxp/kinetis/K32L2B11VMP0A-pinctrl.h new file mode 100644 index 000000000..f5d96584d --- /dev/null +++ b/dts/nxp/kinetis/K32L2B11VMP0A-pinctrl.h @@ -0,0 +1,299 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B11VMP0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B11VMP0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B11VMP0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define LCD_P0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LCD_P0_Fault_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define LCD_P1_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define LCD_P1_Fault_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define LCD_P2_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LCD_P2_Fault_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define LCD_P3_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LCD_P3_Fault_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define LCD_P12_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define LCD_P12_Fault_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define LCD_P13_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define LCD_P13_Fault_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define LCD_P14_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LCD_P14_Fault_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define LCD_P15_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define LCD_P15_Fault_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define LCD_P20_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define LCD_P20_Fault_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LCD_P21_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define LCD_P21_Fault_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define LCD_P22_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define LCD_P22_Fault_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define LCD_P23_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LCD_P23_Fault_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define LCD_P24_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define LCD_P24_Fault_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LCD_P25_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define LCD_P25_Fault_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define LCD_P26_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define LCD_P26_Fault_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define LCD_P27_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LCD_P27_Fault_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define VLL2_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define LCD_P4_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define PTC20 KINETIS_MUX('C',20,1) /* PTC_20 */ +#define LCD_P4_Fault_PTC20 KINETIS_MUX('C',20,7) /* PTC_20 */ +#define LCD_P5_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define VLL1_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define PTC21 KINETIS_MUX('C',21,1) /* PTC_21 */ +#define LCD_P5_Fault_PTC21 KINETIS_MUX('C',21,7) /* PTC_21 */ +#define VCAP2_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define LCD_P6_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define PTC22 KINETIS_MUX('C',22,1) /* PTC_22 */ +#define LCD_P6_Fault_PTC22 KINETIS_MUX('C',22,7) /* PTC_22 */ +#define LCD_P39_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define VCAP1_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define PTC23 KINETIS_MUX('C',23,1) /* PTC_23 */ +#define LCD_P39_Fault_PTC23 KINETIS_MUX('C',23,7) /* PTC_23 */ +#define LCD_P40_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define LCD_P40_Fault_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define LCD_P41_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LCD_P41_Fault_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LCD_P42_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define LCD_P42_Fault_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define LCD_P43_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LCD_P43_Fault_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LCD_P44_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define LCD_P44_Fault_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define LCD_P45_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LCD_P45_Fault_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define LCD_P46_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define LCD_P46_Fault_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define LCD_P47_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define LCD_P47_Fault_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LCD_P48_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define LCD_P48_Fault_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LCD_P49_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define LCD_P49_Fault_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define LCD_P59_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define LCD_P59_Fault_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define LCD_P60_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define LCD_P60_Fault_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B21VFM0A-pinctrl.h b/dts/nxp/kinetis/K32L2B21VFM0A-pinctrl.h new file mode 100644 index 000000000..325af7649 --- /dev/null +++ b/dts/nxp/kinetis/K32L2B21VFM0A-pinctrl.h @@ -0,0 +1,130 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B21VFM0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B21VFM0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B21VFM0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B21VFT0A-pinctrl.h b/dts/nxp/kinetis/K32L2B21VFT0A-pinctrl.h new file mode 100644 index 000000000..864e12a0c --- /dev/null +++ b/dts/nxp/kinetis/K32L2B21VFT0A-pinctrl.h @@ -0,0 +1,190 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B21VFT0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B21VFT0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B21VFT0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B21VLH0A-pinctrl.h b/dts/nxp/kinetis/K32L2B21VLH0A-pinctrl.h new file mode 100644 index 000000000..c2e14c51c --- /dev/null +++ b/dts/nxp/kinetis/K32L2B21VLH0A-pinctrl.h @@ -0,0 +1,299 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B21VLH0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B21VLH0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B21VLH0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LCD_P0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LCD_P0_Fault_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define LCD_P1_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define LCD_P1_Fault_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define LCD_P2_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LCD_P2_Fault_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define LCD_P3_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LCD_P3_Fault_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define LCD_P12_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define LCD_P12_Fault_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define LCD_P13_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define LCD_P13_Fault_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define LCD_P14_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LCD_P14_Fault_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define LCD_P15_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define LCD_P15_Fault_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define LCD_P20_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define LCD_P20_Fault_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define LCD_P21_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define LCD_P21_Fault_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define LCD_P22_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define LCD_P22_Fault_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define LCD_P23_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LCD_P23_Fault_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define LCD_P24_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define LCD_P24_Fault_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LCD_P25_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define LCD_P25_Fault_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LCD_P26_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define LCD_P26_Fault_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define LCD_P27_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LCD_P27_Fault_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define VLL2_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define LCD_P4_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define PTC20 KINETIS_MUX('C',20,1) /* PTC_20 */ +#define LCD_P4_Fault_PTC20 KINETIS_MUX('C',20,7) /* PTC_20 */ +#define VLL1_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define LCD_P5_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define PTC21 KINETIS_MUX('C',21,1) /* PTC_21 */ +#define LCD_P5_Fault_PTC21 KINETIS_MUX('C',21,7) /* PTC_21 */ +#define VCAP2_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define LCD_P6_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define PTC22 KINETIS_MUX('C',22,1) /* PTC_22 */ +#define LCD_P6_Fault_PTC22 KINETIS_MUX('C',22,7) /* PTC_22 */ +#define VCAP1_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define LCD_P39_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define PTC23 KINETIS_MUX('C',23,1) /* PTC_23 */ +#define LCD_P39_Fault_PTC23 KINETIS_MUX('C',23,7) /* PTC_23 */ +#define LCD_P40_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define LCD_P40_Fault_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define LCD_P41_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LCD_P41_Fault_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LCD_P42_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define LCD_P42_Fault_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define LCD_P43_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LCD_P43_Fault_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LCD_P44_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define LCD_P44_Fault_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define LCD_P45_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LCD_P45_Fault_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define LCD_P46_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define LCD_P46_Fault_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define LCD_P47_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define LCD_P47_Fault_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LCD_P48_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define LCD_P48_Fault_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LCD_P49_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define LCD_P49_Fault_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define LCD_P59_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define LCD_P59_Fault_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define LCD_P60_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define LCD_P60_Fault_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B21VMP0A-pinctrl.h b/dts/nxp/kinetis/K32L2B21VMP0A-pinctrl.h new file mode 100644 index 000000000..18be9f6e5 --- /dev/null +++ b/dts/nxp/kinetis/K32L2B21VMP0A-pinctrl.h @@ -0,0 +1,299 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B21VMP0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B21VMP0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B21VMP0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LCD_P0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LCD_P0_Fault_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define LCD_P1_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define LCD_P1_Fault_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define LCD_P2_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LCD_P2_Fault_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define LCD_P3_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LCD_P3_Fault_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define LCD_P12_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define LCD_P12_Fault_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define LCD_P13_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define LCD_P13_Fault_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define LCD_P14_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LCD_P14_Fault_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define LCD_P15_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define LCD_P15_Fault_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define LCD_P20_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define LCD_P20_Fault_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define LCD_P21_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define LCD_P21_Fault_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define LCD_P22_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define LCD_P22_Fault_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define LCD_P23_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LCD_P23_Fault_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define LCD_P24_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define LCD_P24_Fault_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LCD_P25_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define LCD_P25_Fault_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LCD_P26_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define LCD_P26_Fault_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define LCD_P27_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LCD_P27_Fault_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define VLL2_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define LCD_P4_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define PTC20 KINETIS_MUX('C',20,1) /* PTC_20 */ +#define LCD_P4_Fault_PTC20 KINETIS_MUX('C',20,7) /* PTC_20 */ +#define VLL1_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define LCD_P5_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define PTC21 KINETIS_MUX('C',21,1) /* PTC_21 */ +#define LCD_P5_Fault_PTC21 KINETIS_MUX('C',21,7) /* PTC_21 */ +#define VCAP2_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define LCD_P6_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define PTC22 KINETIS_MUX('C',22,1) /* PTC_22 */ +#define LCD_P6_Fault_PTC22 KINETIS_MUX('C',22,7) /* PTC_22 */ +#define VCAP1_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define LCD_P39_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define PTC23 KINETIS_MUX('C',23,1) /* PTC_23 */ +#define LCD_P39_Fault_PTC23 KINETIS_MUX('C',23,7) /* PTC_23 */ +#define LCD_P40_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define LCD_P40_Fault_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define LCD_P41_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LCD_P41_Fault_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LCD_P42_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define LCD_P42_Fault_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define LCD_P43_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LCD_P43_Fault_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LCD_P44_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define LCD_P44_Fault_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define LCD_P45_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LCD_P45_Fault_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define LCD_P46_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define LCD_P46_Fault_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define LCD_P47_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define LCD_P47_Fault_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LCD_P48_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define LCD_P48_Fault_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LCD_P49_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define LCD_P49_Fault_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define LCD_P59_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define LCD_P59_Fault_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define LCD_P60_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define LCD_P60_Fault_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B31VFM0A-pinctrl.h b/dts/nxp/kinetis/K32L2B31VFM0A-pinctrl.h new file mode 100644 index 000000000..eb6d02b81 --- /dev/null +++ b/dts/nxp/kinetis/K32L2B31VFM0A-pinctrl.h @@ -0,0 +1,130 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B31VFM0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B31VFM0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B31VFM0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B31VFT0A-pinctrl.h b/dts/nxp/kinetis/K32L2B31VFT0A-pinctrl.h new file mode 100644 index 000000000..25e13070b --- /dev/null +++ b/dts/nxp/kinetis/K32L2B31VFT0A-pinctrl.h @@ -0,0 +1,190 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B31VFT0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B31VFT0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B31VFT0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B31VLH0A-pinctrl.h b/dts/nxp/kinetis/K32L2B31VLH0A-pinctrl.h new file mode 100644 index 000000000..91ec688af --- /dev/null +++ b/dts/nxp/kinetis/K32L2B31VLH0A-pinctrl.h @@ -0,0 +1,299 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B31VLH0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B31VLH0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B31VLH0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LCD_P0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LCD_P0_Fault_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define LCD_P1_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define LCD_P1_Fault_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define LCD_P2_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LCD_P2_Fault_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define LCD_P3_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LCD_P3_Fault_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define LCD_P12_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define LCD_P12_Fault_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define LCD_P13_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define LCD_P13_Fault_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define LCD_P14_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LCD_P14_Fault_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define LCD_P15_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define LCD_P15_Fault_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define LCD_P20_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define LCD_P20_Fault_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LCD_P21_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define LCD_P21_Fault_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define LCD_P22_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define LCD_P22_Fault_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define LCD_P23_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LCD_P23_Fault_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define LCD_P24_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define LCD_P24_Fault_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LCD_P25_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define LCD_P25_Fault_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define LCD_P26_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define LCD_P26_Fault_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define LCD_P27_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LCD_P27_Fault_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define LCD_P4_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define VLL2_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define PTC20 KINETIS_MUX('C',20,1) /* PTC_20 */ +#define LCD_P4_Fault_PTC20 KINETIS_MUX('C',20,7) /* PTC_20 */ +#define LCD_P5_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define VLL1_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define PTC21 KINETIS_MUX('C',21,1) /* PTC_21 */ +#define LCD_P5_Fault_PTC21 KINETIS_MUX('C',21,7) /* PTC_21 */ +#define VCAP2_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define LCD_P6_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define PTC22 KINETIS_MUX('C',22,1) /* PTC_22 */ +#define LCD_P6_Fault_PTC22 KINETIS_MUX('C',22,7) /* PTC_22 */ +#define VCAP1_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define LCD_P39_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define PTC23 KINETIS_MUX('C',23,1) /* PTC_23 */ +#define LCD_P39_Fault_PTC23 KINETIS_MUX('C',23,7) /* PTC_23 */ +#define LCD_P40_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define LCD_P40_Fault_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define LCD_P41_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LCD_P41_Fault_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LCD_P42_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define LCD_P42_Fault_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define LCD_P43_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LCD_P43_Fault_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LCD_P44_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define LCD_P44_Fault_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define LCD_P45_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LCD_P45_Fault_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LCD_P46_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define LCD_P46_Fault_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define LCD_P47_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define LCD_P47_Fault_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LCD_P48_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define LCD_P48_Fault_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LCD_P49_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define LCD_P49_Fault_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LCD_P59_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define LCD_P59_Fault_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define LCD_P60_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define LCD_P60_Fault_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/K32L2B31VMP0A-pinctrl.h b/dts/nxp/kinetis/K32L2B31VMP0A-pinctrl.h new file mode 100644 index 000000000..0733c0701 --- /dev/null +++ b/dts/nxp/kinetis/K32L2B31VMP0A-pinctrl.h @@ -0,0 +1,299 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L2B31VMP0A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L2B31VMP0A_ +#define _ZEPHYR_DTS_BINDING_K32L2B31VMP0A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LCD_P0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LCD_P0_Fault_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define LCD_P1_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define LCD_P1_Fault_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define LCD_P2_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LCD_P2_Fault_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define LCD_P3_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LCD_P3_Fault_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define LCD_P12_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define LCD_P12_Fault_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define LCD_P13_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define LCD_P13_Fault_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define LCD_P14_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LCD_P14_Fault_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define LCD_P15_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define LCD_P15_Fault_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define LCD_P20_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define LCD_P20_Fault_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LCD_P21_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define LCD_P21_Fault_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define LCD_P22_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define LCD_P22_Fault_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define LCD_P23_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LCD_P23_Fault_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define LCD_P24_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define LCD_P24_Fault_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LCD_P25_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define LCD_P25_Fault_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define LCD_P26_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define LCD_P26_Fault_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define LCD_P27_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LCD_P27_Fault_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define LCD_P4_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define VLL2_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define PTC20 KINETIS_MUX('C',20,1) /* PTC_20 */ +#define LCD_P4_Fault_PTC20 KINETIS_MUX('C',20,7) /* PTC_20 */ +#define LCD_P5_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define VLL1_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define PTC21 KINETIS_MUX('C',21,1) /* PTC_21 */ +#define LCD_P5_Fault_PTC21 KINETIS_MUX('C',21,7) /* PTC_21 */ +#define VCAP2_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define LCD_P6_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define PTC22 KINETIS_MUX('C',22,1) /* PTC_22 */ +#define LCD_P6_Fault_PTC22 KINETIS_MUX('C',22,7) /* PTC_22 */ +#define VCAP1_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define LCD_P39_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define PTC23 KINETIS_MUX('C',23,1) /* PTC_23 */ +#define LCD_P39_Fault_PTC23 KINETIS_MUX('C',23,7) /* PTC_23 */ +#define LCD_P40_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define LCD_P40_Fault_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define LCD_P41_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LCD_P41_Fault_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LCD_P42_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define LCD_P42_Fault_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define LCD_P43_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LCD_P43_Fault_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LCD_P44_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define LCD_P44_Fault_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define LCD_P45_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LCD_P45_Fault_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LCD_P46_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define LCD_P46_Fault_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define LCD_P47_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define LCD_P47_Fault_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LCD_P48_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define LCD_P48_Fault_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LCD_P49_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define LCD_P49_Fault_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LCD_P59_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define LCD_P59_Fault_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define LCD_P60_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define LCD_P60_Fault_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/K32L3A60VPJ1A-pinctrl.h b/dts/nxp/kinetis/K32L3A60VPJ1A-pinctrl.h new file mode 100644 index 000000000..5027c4ff2 --- /dev/null +++ b/dts/nxp/kinetis/K32L3A60VPJ1A-pinctrl.h @@ -0,0 +1,561 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for K32L3A60VPJ1A/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_K32L3A60VPJ1A_ +#define _ZEPHYR_DTS_BINDING_K32L3A60VPJ1A_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LLWU_P0_PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_CTS_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define LPUART1_CTS_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define JTAG_TCLK_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define SWD_CLK_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define LLWU_P1_PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define LPUART1_RX_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define JTAG_TDI_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART1_TX_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define TPM0_CLKIN_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define JTAG_TDO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define SWD_SWO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART0_RTS_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define LPI2C0_SCLS_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define LPUART1_RTS_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define LPCMP0_OUT_PTA4 KINETIS_MUX('A',4,6) /* PTA_4 */ +#define JTAG_TMS_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define LPI2C2_SDAS_PTA9 KINETIS_MUX('A',9,2) /* PTA_9 */ +#define LPSPI3_SCK_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPI2C2_SCLS_PTA10 KINETIS_MUX('A',10,2) /* PTA_10 */ +#define LPSPI3_SOUT_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define LPI2C2_SDA_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPCMP0_OUT_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define LPI2C2_SCL_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define LPI2C2_HREQ_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPSPI3_PCS1_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define EMVSIM0_CLK_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPSPI2_PCS1_PTA18 KINETIS_MUX('A',18,2) /* PTA_18 */ +#define LPSPI3_PCS3_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define EMVSIM0_RST_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPSPI2_PCS3_PTA19 KINETIS_MUX('A',19,2) /* PTA_19 */ +#define LPSPI3_SCK_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define EMVSIM0_VCCEN_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define TPM2_CH5_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define LPSPI2_SCK_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPSPI1_PCS1_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define EMVSIM0_IO_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define TPM2_CH4_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LPSPI2_SOUT_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define EMVSIM0_PD_PTA21 KINETIS_MUX('A',21,4) /* PTA_21 */ +#define TPM2_CH3_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define PTA22 KINETIS_MUX('A',22,1) /* PTA_22 */ +#define LLWU_P2_PTA22 KINETIS_MUX('A',22,1) /* PTA_22 */ +#define LPSPI2_PCS2_PTA22 KINETIS_MUX('A',22,2) /* PTA_22 */ +#define LPI2C2_HREQ_PTA22 KINETIS_MUX('A',22,4) /* PTA_22 */ +#define TPM2_CH2_PTA22 KINETIS_MUX('A',22,6) /* PTA_22 */ +#define PTA23 KINETIS_MUX('A',23,1) /* PTA_23 */ +#define LPSPI2_SIN_PTA23 KINETIS_MUX('A',23,2) /* PTA_23 */ +#define LPSPI1_PCS3_PTA23 KINETIS_MUX('A',23,3) /* PTA_23 */ +#define LPI2C2_SDA_PTA23 KINETIS_MUX('A',23,4) /* PTA_23 */ +#define TPM2_CH1_PTA23 KINETIS_MUX('A',23,6) /* PTA_23 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define LPSPI2_PCS0_PTA24 KINETIS_MUX('A',24,2) /* PTA_24 */ +#define LPSPI1_SCK_PTA24 KINETIS_MUX('A',24,3) /* PTA_24 */ +#define LPI2C2_SCL_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define TPM2_CH0_PTA24 KINETIS_MUX('A',24,6) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define LPUART1_RX_PTA25 KINETIS_MUX('A',25,2) /* PTA_25 */ +#define LPSPI3_SOUT_PTA25 KINETIS_MUX('A',25,3) /* PTA_25 */ +#define LPI2C2_SDAS_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define LPUART1_TX_PTA26 KINETIS_MUX('A',26,2) /* PTA_26 */ +#define LPSPI3_PCS2_PTA26 KINETIS_MUX('A',26,3) /* PTA_26 */ +#define LPI2C2_SCLS_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define LPUART1_CTS_PTA27 KINETIS_MUX('A',27,2) /* PTA_27 */ +#define LPSPI3_SIN_PTA27 KINETIS_MUX('A',27,3) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define LPUART1_RTS_PTA28 KINETIS_MUX('A',28,2) /* PTA_28 */ +#define LPSPI3_PCS0_PTA28 KINETIS_MUX('A',28,3) /* PTA_28 */ +#define LLWU_P3_0_PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define PTA30_0 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define LLWU_P3_1_PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define PTA30_1 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define LPUART2_CTS_0_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define LPUART2_CTS_1_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define LPSPI1_SOUT_0_PTA30 KINETIS_MUX('A',30,3) /* PTA_30 */ +#define LPSPI1_SOUT_1_PTA30 KINETIS_MUX('A',30,3) /* PTA_30 */ +#define TPM1_CH0_0_PTA30 KINETIS_MUX('A',30,6) /* PTA_30 */ +#define TPM1_CH0_1_PTA30 KINETIS_MUX('A',30,6) /* PTA_30 */ +#define LPTMR2_ALT2_0_PTA30 KINETIS_MUX('A',30,7) /* PTA_30 */ +#define LPTMR2_ALT2_1_PTA30 KINETIS_MUX('A',30,7) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define LPUART2_RTS_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define LPSPI1_PCS2_PTA31 KINETIS_MUX('A',31,3) /* PTA_31 */ +#define TPM1_CH1_PTA31 KINETIS_MUX('A',31,6) /* PTA_31 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART2_TX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI1_SIN_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define USB0_SOF_OUT_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define CLKOUT_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CLKIN_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define LLWU_P4_PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART2_RX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI1_PCS0_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define I2S0_TX_D1_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define LPTMR1_ALT3_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define LLWU_P5_PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define LPSPI0_PCS1_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART1_RX_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define I2S0_TX_D0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TPM0_CH0_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define LPADC0_SE0_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define LPSPI0_PCS3_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART1_TX_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define I2S0_TX_FS_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TPM0_CH1_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define LPADC0_SE1_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define LLWU_P6_PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define LPSPI0_SCK_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPUART1_CTS_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define I2S0_TX_BCLK_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define TPM0_CH2_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define LPSPI0_SOUT_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPUART1_RTS_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define I2S0_MCLK_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define TPM0_CH3_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define LLWU_P7_PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPSPI0_PCS2_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPI2C1_SDA_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define I2S0_RX_BCLK_PTB6 KINETIS_MUX('B',6,4) /* PTB_6 */ +#define TPM0_CH4_PTB6 KINETIS_MUX('B',6,6) /* PTB_6 */ +#define LPADC0_SE2_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define LLWU_P8_PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPSPI0_SIN_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPI2C1_SDAS_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define I2S0_RX_FS_PTB7 KINETIS_MUX('B',7,4) /* PTB_7 */ +#define TPM0_CH5_PTB7 KINETIS_MUX('B',7,6) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LLWU_P9_PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPSPI0_PCS0_PTB8 KINETIS_MUX('B',8,2) /* PTB_8 */ +#define LPI2C1_SCLS_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define I2S0_RX_D0_PTB8 KINETIS_MUX('B',8,4) /* PTB_8 */ +#define LPTMR0_ALT1_PTB8 KINETIS_MUX('B',8,7) /* PTB_8 */ +#define LPADC0_SE3_PTB9 KINETIS_MUX('B',9,0) /* PTB_9 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPM_LPREQ_PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPSPI0_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPI2C1_SCL_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define I2S0_RX_D1_PTB9 KINETIS_MUX('B',9,4) /* PTB_9 */ +#define FXIO0_D0_PTB9 KINETIS_MUX('B',9,7) /* PTB_9 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define LPUART2_RX_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPI2C1_SDAS_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define LPI2C0_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define FXIO0_D1_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define LPUART2_TX_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define LPI2C1_SCLS_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define LPI2C0_SCL_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define TPM3_CLKIN_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define FXIO0_D2_PTB12 KINETIS_MUX('B',12,7) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define LPUART2_CTS_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define LPI2C1_SDA_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define LPI2C0_SDAS_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define TPM3_CH0_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define FXIO0_D3_PTB13 KINETIS_MUX('B',13,7) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define LPUART2_RTS_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define LPI2C1_SCL_PTB14 KINETIS_MUX('B',14,3) /* PTB_14 */ +#define LPI2C0_SCLS_PTB14 KINETIS_MUX('B',14,4) /* PTB_14 */ +#define TPM3_CH1_PTB14 KINETIS_MUX('B',14,6) /* PTB_14 */ +#define FXIO0_D4_PTB14 KINETIS_MUX('B',14,7) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define LPI2C1_HREQ_PTB15 KINETIS_MUX('B',15,3) /* PTB_15 */ +#define LPI2C3_SCL_PTB15 KINETIS_MUX('B',15,4) /* PTB_15 */ +#define TPM0_CLKIN_PTB15 KINETIS_MUX('B',15,6) /* PTB_15 */ +#define FXIO0_D5_PTB15 KINETIS_MUX('B',15,7) /* PTB_15 */ +#define LLWU_P10_PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define LPUART3_CTS_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define LPI2C3_SDA_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define FXIO0_D6_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define LPUART3_RTS_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define LPI2C3_SCLS_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define FXIO0_D7_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define LPSPI1_PCS1_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define LPUART2_RX_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define LPI2C3_SDAS_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FXIO0_D8_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define LPSPI1_PCS3_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define LPUART2_TX_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define TPM1_CLKIN_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D9_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define LLWU_P11_PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define LPSPI1_SCK_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define LPUART2_CTS_PTB20 KINETIS_MUX('B',20,3) /* PTB_20 */ +#define TPM1_CH0_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D10_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define LPSPI1_SOUT_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define LPUART2_RTS_PTB21 KINETIS_MUX('B',21,3) /* PTB_21 */ +#define LPI2C2_HREQ_PTB21 KINETIS_MUX('B',21,4) /* PTB_21 */ +#define TPM1_CH1_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D11_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define LLWU_P12_PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define LPSPI1_PCS2_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define LPUART0_CTS_PTB22 KINETIS_MUX('B',22,3) /* PTB_22 */ +#define LPI2C2_SDA_PTB22 KINETIS_MUX('B',22,4) /* PTB_22 */ +#define TPM2_CLKIN_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define FXIO0_D12_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB24 KINETIS_MUX('B',24,1) /* PTB_24 */ +#define LPSPI1_SIN_PTB24 KINETIS_MUX('B',24,2) /* PTB_24 */ +#define LPUART0_RTS_PTB24 KINETIS_MUX('B',24,3) /* PTB_24 */ +#define LPI2C2_SCL_PTB24 KINETIS_MUX('B',24,4) /* PTB_24 */ +#define EWM_IN_PTB24 KINETIS_MUX('B',24,6) /* PTB_24 */ +#define FXIO0_D13_PTB24 KINETIS_MUX('B',24,7) /* PTB_24 */ +#define LLWU_P13_PTB25 KINETIS_MUX('B',25,1) /* PTB_25 */ +#define PTB25 KINETIS_MUX('B',25,1) /* PTB_25 */ +#define LPSPI1_PCS0_PTB25 KINETIS_MUX('B',25,2) /* PTB_25 */ +#define LPUART0_RX_PTB25 KINETIS_MUX('B',25,3) /* PTB_25 */ +#define LPI2C2_SDAS_PTB25 KINETIS_MUX('B',25,4) /* PTB_25 */ +#define EWM_OUT_b_PTB25 KINETIS_MUX('B',25,6) /* PTB_25 */ +#define FXIO0_D14_PTB25 KINETIS_MUX('B',25,7) /* PTB_25 */ +#define PTB26 KINETIS_MUX('B',26,1) /* PTB_26 */ +#define USB0_SOF_OUT_PTB26 KINETIS_MUX('B',26,2) /* PTB_26 */ +#define LPUART0_TX_PTB26 KINETIS_MUX('B',26,3) /* PTB_26 */ +#define LPI2C2_SCLS_PTB26 KINETIS_MUX('B',26,4) /* PTB_26 */ +#define LPCMP0_OUT_PTB26 KINETIS_MUX('B',26,6) /* PTB_26 */ +#define PTB28 KINETIS_MUX('B',28,1) /* PTB_28 */ +#define LLWU_P14_PTB28 KINETIS_MUX('B',28,1) /* PTB_28 */ +#define LPUART3_RX_PTB28 KINETIS_MUX('B',28,3) /* PTB_28 */ +#define I2S0_TX_D0_PTB28 KINETIS_MUX('B',28,4) /* PTB_28 */ +#define FXIO0_D15_PTB28 KINETIS_MUX('B',28,7) /* PTB_28 */ +#define PTB29 KINETIS_MUX('B',29,1) /* PTB_29 */ +#define LPUART3_TX_PTB29 KINETIS_MUX('B',29,3) /* PTB_29 */ +#define I2S0_TX_FS_PTB29 KINETIS_MUX('B',29,4) /* PTB_29 */ +#define FXIO0_D16_PTB29 KINETIS_MUX('B',29,7) /* PTB_29 */ +#define PTB30 KINETIS_MUX('B',30,1) /* PTB_30 */ +#define I2S0_TX_BCLK_PTB30 KINETIS_MUX('B',30,4) /* PTB_30 */ +#define PTB31 KINETIS_MUX('B',31,1) /* PTB_31 */ +#define I2S0_RX_D0_PTB31 KINETIS_MUX('B',31,4) /* PTB_31 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define I2S0_RX_FS_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2S0_RX_BCLK_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define LPCMP0_IN0_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define LLWU_P15_PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPSPI0_PCS3_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define LPUART0_RX_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define LPI2C1_HREQ_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define TPM0_CH0_PTC7 KINETIS_MUX('C',7,6) /* PTC_7 */ +#define LPTMR1_ALT1_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define LPCMP0_IN1_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPSPI0_SCK_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_TX_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define LPI2C0_HREQ_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define TPM0_CH1_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define LPCMP0_IN2_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define LPADC0_SE4_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define LLWU_P16_PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPSPI0_SOUT_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_CTS_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define LPI2C0_SDA_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define TPM0_CH2_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define LPTMR0_ALT2_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define LPADC0_SE5_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPSPI0_PCS2_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define LPUART0_RTS_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define LPI2C0_SCL_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define TPM0_CH3_PTC10 KINETIS_MUX('C',10,6) /* PTC_10 */ +#define LPADC0_SE6_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P17_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPSPI0_SIN_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define LPI2C1_SDA_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define LPI2C0_SDAS_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define TPM0_CH4_PTC11 KINETIS_MUX('C',11,6) /* PTC_11 */ +#define EWM_IN_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define LPADC0_SE7_PTC12 KINETIS_MUX('C',12,0) /* PTC_12 */ +#define LLWU_P18_PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPSPI0_PCS0_PTC12 KINETIS_MUX('C',12,2) /* PTC_12 */ +#define LPI2C1_SCL_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define LPI2C0_SCLS_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define TPM0_CH5_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define EWM_OUT_b_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define TPM0_CH4_PTC27 KINETIS_MUX('C',27,6) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define LPSPI0_PCS1_PTC28 KINETIS_MUX('C',28,3) /* PTC_28 */ +#define TPM0_CH3_PTC28 KINETIS_MUX('C',28,6) /* PTC_28 */ +#define FXIO0_D17_PTC28 KINETIS_MUX('C',28,7) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define LPUART1_RX_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define LPSPI0_PCS3_PTC29 KINETIS_MUX('C',29,3) /* PTC_29 */ +#define TPM0_CH2_PTC29 KINETIS_MUX('C',29,6) /* PTC_29 */ +#define FXIO0_D18_PTC29 KINETIS_MUX('C',29,7) /* PTC_29 */ +#define PTC30 KINETIS_MUX('C',30,1) /* PTC_30 */ +#define LPUART1_TX_PTC30 KINETIS_MUX('C',30,2) /* PTC_30 */ +#define LPSPI0_SCK_PTC30 KINETIS_MUX('C',30,3) /* PTC_30 */ +#define TPM0_CH1_PTC30 KINETIS_MUX('C',30,6) /* PTC_30 */ +#define FXIO0_D19_PTC30 KINETIS_MUX('C',30,7) /* PTC_30 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LPUART1_CTS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI0_SOUT_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define FXIO0_D20_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define LPUART1_RTS_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI0_PCS2_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define EWM_IN_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define FXIO0_D21_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SDHC0_D7_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPSPI0_SIN_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define EWM_OUT_b_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define FXIO0_D22_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SDHC0_D6_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPSPI0_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define EMVSIM0_CLK_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define TPM2_CLKIN_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define FXIO0_D23_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SDHC0_D5_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPSPI2_PCS1_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define EMVSIM0_RST_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D24_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define LPADC0_SE8_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SDHC0_D4_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPSPI2_PCS3_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define EMVSIM0_VCCEN_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D25_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define LPADC0_SE9_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SDHC0_D1_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPSPI2_SCK_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define EMVSIM0_IO_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define TRACE_D3_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define TPM2_CH5_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define FXIO0_D26_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define LPADC0_SE10_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SDHC0_D0_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPSPI2_SOUT_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define EMVSIM0_PD_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define TRACE_D2_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define TPM2_CH4_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define FXIO0_D27_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LPADC0_SE11_PTD8 KINETIS_MUX('D',8,0) /* PTD_8 */ +#define LLWU_P19_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define SDHC0_DCLK_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPSPI2_PCS2_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define LPI2C1_SDAS_PTD8 KINETIS_MUX('D',8,4) /* PTD_8 */ +#define TRACE_D1_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define TPM2_CH3_PTD8 KINETIS_MUX('D',8,6) /* PTD_8 */ +#define FXIO0_D28_PTD8 KINETIS_MUX('D',8,7) /* PTD_8 */ +#define LPADC0_SE12_PTD9 KINETIS_MUX('D',9,0) /* PTD_9 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define SDHC0_CMD_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPSPI2_SIN_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define LPI2C1_SCLS_PTD9 KINETIS_MUX('D',9,4) /* PTD_9 */ +#define TRACE_D0_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define TPM2_CH2_PTD9 KINETIS_MUX('D',9,6) /* PTD_9 */ +#define FXIO0_D29_PTD9 KINETIS_MUX('D',9,7) /* PTD_9 */ +#define LPADC0_SE13_PTD10 KINETIS_MUX('D',10,0) /* PTD_10 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LLWU_P20_PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define SDHC0_D3_PTD10 KINETIS_MUX('D',10,2) /* PTD_10 */ +#define LPSPI2_PCS0_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define LPI2C1_SDA_PTD10 KINETIS_MUX('D',10,4) /* PTD_10 */ +#define TRACE_CLKOUT_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define TPM2_CH1_PTD10 KINETIS_MUX('D',10,6) /* PTD_10 */ +#define FXIO0_D30_PTD10 KINETIS_MUX('D',10,7) /* PTD_10 */ +#define LPADC0_SE14_PTD11 KINETIS_MUX('D',11,0) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SDHC0_D2_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define USB0_SOF_OUT_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define LPI2C1_SCL_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define CLKOUT_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define TPM2_CH0_PTD11 KINETIS_MUX('D',11,6) /* PTD_11 */ +#define FXIO0_D31_PTD11 KINETIS_MUX('D',11,7) /* PTD_11 */ +#define LPCMP1_IN4_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define EWM_IN_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define LPADC0_SE18_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P21_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SDHC0_D1_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_SDAS_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPSPI3_PCS1_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define EWM_OUT_b_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define LPTMR1_ALT2_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LPADC0_SE19_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SDHC0_D0_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPI2C0_SCLS_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define LPSPI3_PCS3_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define LPCMP1_OUT_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define LPADC0_SE20_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define LPCMP1_IN0_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define LLWU_P22_PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SDHC0_D7_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPI2C0_SDA_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define LPSPI3_SCK_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TPM0_CLKIN_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define LPTMR0_ALT3_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LPCMP1_IN1_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define LPADC0_SE21_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SDHC0_D6_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPI2C0_SCL_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define LPSPI3_SOUT_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define CLKOUT_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define TPM1_CLKIN_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define LPCMP1_IN2_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SDHC0_DCLK_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPI2C0_HREQ_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define LPSPI3_PCS2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define LPCMP1_OUT_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define LPADC0_SE22_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define LLWU_P23_PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define LPUART3_RX_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define LPSPI3_SIN_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define TPM1_CH0_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define LPTMR2_ALT1_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define LPADC0_SE23_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define LLWU_P24_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define SDHC0_CMD_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART3_TX_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define LPSPI3_PCS0_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define TPM1_CH1_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define FXIO0_D0_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define LLWU_P25_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define SDHC0_D4_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define LPUART3_CTS_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define LPI2C3_SDA_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define TPM3_CH0_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define LPTMR2_ALT3_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define SDHC0_D3_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPUART3_RTS_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define LPI2C3_SCL_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define TPM3_CH1_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define FXIO0_D1_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define LLWU_P26_PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define SDHC0_D2_PTE12 KINETIS_MUX('E',12,2) /* PTE_12 */ +#define LPI2C3_SDAS_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define TPM3_CLKIN_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define FXIO0_D2_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define I2S0_TX_BCLK_PTE13 KINETIS_MUX('E',13,2) /* PTE_13 */ +#define LPI2C3_SCLS_PTE13 KINETIS_MUX('E',13,4) /* PTE_13 */ +#define TPM3_CH0_PTE13 KINETIS_MUX('E',13,6) /* PTE_13 */ +#define FXIO0_D3_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define PTE14 KINETIS_MUX('E',14,1) /* PTE_14 */ +#define I2S0_TX_FS_PTE14 KINETIS_MUX('E',14,2) /* PTE_14 */ +#define LPI2C3_HREQ_PTE14 KINETIS_MUX('E',14,4) /* PTE_14 */ +#define TPM3_CH1_PTE14 KINETIS_MUX('E',14,6) /* PTE_14 */ +#define FXIO0_D4_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define PTE15 KINETIS_MUX('E',15,1) /* PTE_15 */ +#define I2S0_TX_D0_PTE15 KINETIS_MUX('E',15,2) /* PTE_15 */ +#define TPM3_CLKIN_PTE15 KINETIS_MUX('E',15,6) /* PTE_15 */ +#define FXIO0_D5_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define I2S0_RX_BCLK_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define TPM2_CH0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define FXIO0_D6_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define I2S0_RX_FS_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define TPM2_CH1_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define FXIO0_D7_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define I2S0_RX_D0_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define TPM2_CH2_PTE18 KINETIS_MUX('E',18,6) /* PTE_18 */ +#define FXIO0_D8_PTE18 KINETIS_MUX('E',18,7) /* PTE_18 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define I2S0_MCLK_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define TPM2_CH3_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define FXIO0_D9_PTE19 KINETIS_MUX('E',19,7) /* PTE_19 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define I2S0_TX_D1_PTE21 KINETIS_MUX('E',21,2) /* PTE_21 */ +#define USB0_SOF_OUT_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define TPM2_CH4_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define FXIO0_D10_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define I2S0_RX_D1_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define LPI2C3_HREQ_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define TPM2_CH5_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define FXIO0_D11_PTE22 KINETIS_MUX('E',22,7) /* PTE_22 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define LPUART3_CTS_PTE27 KINETIS_MUX('E',27,2) /* PTE_27 */ +#define LPI2C3_SDAS_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define FXIO0_D28_PTE27 KINETIS_MUX('E',27,7) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#define LPUART3_RTS_PTE28 KINETIS_MUX('E',28,2) /* PTE_28 */ +#define LPI2C3_SCLS_PTE28 KINETIS_MUX('E',28,3) /* PTE_28 */ +#define FXIO0_D29_PTE28 KINETIS_MUX('E',28,7) /* PTE_28 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define LPUART3_RX_PTE29 KINETIS_MUX('E',29,2) /* PTE_29 */ +#define LPI2C3_SDA_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define FXIO0_D30_PTE29 KINETIS_MUX('E',29,7) /* PTE_29 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define LPUART3_TX_PTE30 KINETIS_MUX('E',30,2) /* PTE_30 */ +#define LPI2C3_SCL_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM2_CLKIN_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define FXIO0_D31_PTE30 KINETIS_MUX('E',30,7) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/MK02FN128VFM10-pinctrl.h b/dts/nxp/kinetis/MK02FN128VFM10-pinctrl.h new file mode 100644 index 000000000..5517f10b4 --- /dev/null +++ b/dts/nxp/kinetis/MK02FN128VFM10-pinctrl.h @@ -0,0 +1,152 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK02FN128VFM10/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK02FN128VFM10_ +#define _ZEPHYR_DTS_BINDING_MK02FN128VFM10_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH0_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH1_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART1_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_DM1_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART1_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_DP2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART1_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_DM2_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART1_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#endif diff --git a/dts/nxp/kinetis/MK02FN128VLF10-pinctrl.h b/dts/nxp/kinetis/MK02FN128VLF10-pinctrl.h new file mode 100644 index 000000000..2d8bb3c84 --- /dev/null +++ b/dts/nxp/kinetis/MK02FN128VLF10-pinctrl.h @@ -0,0 +1,187 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK02FN128VLF10/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK02FN128VLF10_ +#define _ZEPHYR_DTS_BINDING_MK02FN128VLF10_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH0_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH1_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART1_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_DM1_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART1_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_DP2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART1_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_DM2_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART1_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#endif diff --git a/dts/nxp/kinetis/MK02FN128VLH10-pinctrl.h b/dts/nxp/kinetis/MK02FN128VLH10-pinctrl.h new file mode 100644 index 000000000..874c5b37d --- /dev/null +++ b/dts/nxp/kinetis/MK02FN128VLH10-pinctrl.h @@ -0,0 +1,217 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK02FN128VLH10/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK02FN128VLH10_ +#define _ZEPHYR_DTS_BINDING_MK02FN128VLH10_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH0_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH1_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART1_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_DM1_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART1_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_DP2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART1_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_DM2_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART1_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#endif diff --git a/dts/nxp/kinetis/MK22FN128VDC10-pinctrl.h b/dts/nxp/kinetis/MK22FN128VDC10-pinctrl.h new file mode 100644 index 000000000..edb745b1f --- /dev/null +++ b/dts/nxp/kinetis/MK22FN128VDC10-pinctrl.h @@ -0,0 +1,320 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK22FN128VDC10/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK22FN128VDC10_ +#define _ZEPHYR_DTS_BINDING_MK22FN128VDC10_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPUART0_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART0_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART0_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART0_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART0_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART0_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART0_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART0_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART0_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART0_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define CLKOUT32K_PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#endif diff --git a/dts/nxp/kinetis/MK22FN128VLH10-pinctrl.h b/dts/nxp/kinetis/MK22FN128VLH10-pinctrl.h new file mode 100644 index 000000000..cd16d1542 --- /dev/null +++ b/dts/nxp/kinetis/MK22FN128VLH10-pinctrl.h @@ -0,0 +1,237 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK22FN128VLH10/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK22FN128VLH10_ +#define _ZEPHYR_DTS_BINDING_MK22FN128VLH10_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#endif diff --git a/dts/nxp/kinetis/MK22FN128VLL10-pinctrl.h b/dts/nxp/kinetis/MK22FN128VLL10-pinctrl.h new file mode 100644 index 000000000..aa9d74bd3 --- /dev/null +++ b/dts/nxp/kinetis/MK22FN128VLL10-pinctrl.h @@ -0,0 +1,318 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK22FN128VLL10/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK22FN128VLL10_ +#define _ZEPHYR_DTS_BINDING_MK22FN128VLL10_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART0_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART0_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART0_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART0_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART0_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART0_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART0_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART0_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART0_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define CLKOUT32K_PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#endif diff --git a/dts/nxp/kinetis/MK22FN128VMP10-pinctrl.h b/dts/nxp/kinetis/MK22FN128VMP10-pinctrl.h new file mode 100644 index 000000000..073ca0294 --- /dev/null +++ b/dts/nxp/kinetis/MK22FN128VMP10-pinctrl.h @@ -0,0 +1,237 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK22FN128VMP10/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK22FN128VMP10_ +#define _ZEPHYR_DTS_BINDING_MK22FN128VMP10_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#endif diff --git a/dts/nxp/kinetis/MK22FN256CAH12-pinctrl.h b/dts/nxp/kinetis/MK22FN256CAH12-pinctrl.h new file mode 100644 index 000000000..800ff5248 --- /dev/null +++ b/dts/nxp/kinetis/MK22FN256CAH12-pinctrl.h @@ -0,0 +1,236 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK22FN256CAH12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK22FN256CAH12_ +#define _ZEPHYR_DTS_BINDING_MK22FN256CAH12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#endif diff --git a/dts/nxp/kinetis/MK22FN256VDC12-pinctrl.h b/dts/nxp/kinetis/MK22FN256VDC12-pinctrl.h new file mode 100644 index 000000000..f53d44880 --- /dev/null +++ b/dts/nxp/kinetis/MK22FN256VDC12-pinctrl.h @@ -0,0 +1,324 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK22FN256VDC12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK22FN256VDC12_ +#define _ZEPHYR_DTS_BINDING_MK22FN256VDC12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPUART0_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART0_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART0_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART0_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART0_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART0_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART0_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define LPUART0_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART0_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART0_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART0_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#endif diff --git a/dts/nxp/kinetis/MK22FN256VLH12-pinctrl.h b/dts/nxp/kinetis/MK22FN256VLH12-pinctrl.h new file mode 100644 index 000000000..ed7678e31 --- /dev/null +++ b/dts/nxp/kinetis/MK22FN256VLH12-pinctrl.h @@ -0,0 +1,236 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK22FN256VLH12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK22FN256VLH12_ +#define _ZEPHYR_DTS_BINDING_MK22FN256VLH12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#endif diff --git a/dts/nxp/kinetis/MK22FN256VLL12-pinctrl.h b/dts/nxp/kinetis/MK22FN256VLL12-pinctrl.h new file mode 100644 index 000000000..fa2dfa928 --- /dev/null +++ b/dts/nxp/kinetis/MK22FN256VLL12-pinctrl.h @@ -0,0 +1,316 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK22FN256VLL12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK22FN256VLL12_ +#define _ZEPHYR_DTS_BINDING_MK22FN256VLL12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART0_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART0_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART0_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART0_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART0_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART0_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART0_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART0_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART0_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#endif diff --git a/dts/nxp/kinetis/MK22FN256VMP12-pinctrl.h b/dts/nxp/kinetis/MK22FN256VMP12-pinctrl.h new file mode 100644 index 000000000..fd83845e7 --- /dev/null +++ b/dts/nxp/kinetis/MK22FN256VMP12-pinctrl.h @@ -0,0 +1,236 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK22FN256VMP12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK22FN256VMP12_ +#define _ZEPHYR_DTS_BINDING_MK22FN256VMP12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#endif diff --git a/dts/nxp/kinetis/MK24FN1M0CAJ12-pinctrl.h b/dts/nxp/kinetis/MK24FN1M0CAJ12-pinctrl.h new file mode 100644 index 000000000..a54a8efbc --- /dev/null +++ b/dts/nxp/kinetis/MK24FN1M0CAJ12-pinctrl.h @@ -0,0 +1,463 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK24FN1M0CAJ12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK24FN1M0CAJ12_ +#define _ZEPHYR_DTS_BINDING_MK24FN1M0CAJ12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_COL_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define UART0_COL_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_COL_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define UART5_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define UART5_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define UART5_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define UART5_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_DP2_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC0_DM2_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define UART5_TX_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define UART5_RX_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define UART5_CTS_b_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define UART5_RTS_b_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK24FN1M0VDC12-pinctrl.h b/dts/nxp/kinetis/MK24FN1M0VDC12-pinctrl.h new file mode 100644 index 000000000..430739cdb --- /dev/null +++ b/dts/nxp/kinetis/MK24FN1M0VDC12-pinctrl.h @@ -0,0 +1,415 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK24FN1M0VDC12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK24FN1M0VDC12_ +#define _ZEPHYR_DTS_BINDING_MK24FN1M0VDC12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_COL_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define UART0_COL_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define UART3_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define UART3_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_COL_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define UART5_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define UART5_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define UART5_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define UART5_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_DP2_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC0_DM2_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#endif diff --git a/dts/nxp/kinetis/MK24FN1M0VLL12-pinctrl.h b/dts/nxp/kinetis/MK24FN1M0VLL12-pinctrl.h new file mode 100644 index 000000000..bbc0882ba --- /dev/null +++ b/dts/nxp/kinetis/MK24FN1M0VLL12-pinctrl.h @@ -0,0 +1,363 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK24FN1M0VLL12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK24FN1M0VLL12_ +#define _ZEPHYR_DTS_BINDING_MK24FN1M0VLL12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_COL_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define UART0_COL_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_COL_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_DP2_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC0_DM2_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#endif diff --git a/dts/nxp/kinetis/MK24FN1M0VLQ12-pinctrl.h b/dts/nxp/kinetis/MK24FN1M0VLQ12-pinctrl.h new file mode 100644 index 000000000..5e6eefccd --- /dev/null +++ b/dts/nxp/kinetis/MK24FN1M0VLQ12-pinctrl.h @@ -0,0 +1,461 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK24FN1M0VLQ12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK24FN1M0VLQ12_ +#define _ZEPHYR_DTS_BINDING_MK24FN1M0VLQ12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_COL_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define UART0_COL_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_COL_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define UART5_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define UART5_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define UART5_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define UART5_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_DP2_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC0_DM2_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define UART5_TX_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define UART5_RX_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define UART5_CTS_b_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define UART5_RTS_b_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK24FN256VDC12-pinctrl.h b/dts/nxp/kinetis/MK24FN256VDC12-pinctrl.h new file mode 100644 index 000000000..11c7b6afb --- /dev/null +++ b/dts/nxp/kinetis/MK24FN256VDC12-pinctrl.h @@ -0,0 +1,386 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK24FN256VDC12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK24FN256VDC12_ +#define _ZEPHYR_DTS_BINDING_MK24FN256VDC12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define UART3_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define UART3_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define UART5_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define UART5_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define UART5_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define UART5_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#endif diff --git a/dts/nxp/kinetis/MK26FN2M0CAC18-pinctrl.h b/dts/nxp/kinetis/MK26FN2M0CAC18-pinctrl.h new file mode 100644 index 000000000..db2f2424b --- /dev/null +++ b/dts/nxp/kinetis/MK26FN2M0CAC18-pinctrl.h @@ -0,0 +1,631 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK26FN2M0CAC18/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK26FN2M0CAC18_ +#define _ZEPHYR_DTS_BINDING_MK26FN2M0CAC18_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define CMP3_IN1_PTA15 KINETIS_MUX('A',15,0) /* PTA_15 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define CMP3_IN2_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define CMP3_IN4_PTA24 KINETIS_MUX('A',24,0) /* PTA_24 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define CMP3_IN5_PTA25 KINETIS_MUX('A',25,0) /* PTA_25 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define CAN0_TX_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define CAN0_RX_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define UART3_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define UART3_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define CAN1_TX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define CAN1_RX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define CMP3_OUT_PTB23 KINETIS_MUX('B',23,6) /* PTB_23 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define CAN1_RX_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define CAN1_TX_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART0_RX_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART0_TX_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART0_RTS_b_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define LPUART0_CTS_b_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB0_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define LPUART0_TX_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define LPUART0_RX_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define LPUART0_CTS_b_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define USB1_ID_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define LPUART0_RTS_b_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define CMP3_OUT_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define CAN1_TX_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define CAN1_RX_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB0_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK26FN2M0VLQ18-pinctrl.h b/dts/nxp/kinetis/MK26FN2M0VLQ18-pinctrl.h new file mode 100644 index 000000000..be3f85cb4 --- /dev/null +++ b/dts/nxp/kinetis/MK26FN2M0VLQ18-pinctrl.h @@ -0,0 +1,556 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK26FN2M0VLQ18/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK26FN2M0VLQ18_ +#define _ZEPHYR_DTS_BINDING_MK26FN2M0VLQ18_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define CMP3_IN1_PTA15 KINETIS_MUX('A',15,0) /* PTA_15 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define CMP3_IN2_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define CMP3_IN4_PTA24 KINETIS_MUX('A',24,0) /* PTA_24 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define CMP3_IN5_PTA25 KINETIS_MUX('A',25,0) /* PTA_25 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define CMP3_OUT_PTB23 KINETIS_MUX('B',23,6) /* PTB_23 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define CAN1_RX_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define CAN1_TX_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART0_RX_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART0_TX_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART0_RTS_b_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define LPUART0_CTS_b_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB0_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define LPUART0_TX_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define LPUART0_RX_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define LPUART0_CTS_b_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define USB1_ID_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define LPUART0_RTS_b_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define CAN1_TX_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define CAN1_RX_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB0_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK26FN2M0VMD18-pinctrl.h b/dts/nxp/kinetis/MK26FN2M0VMD18-pinctrl.h new file mode 100644 index 000000000..ed425fd61 --- /dev/null +++ b/dts/nxp/kinetis/MK26FN2M0VMD18-pinctrl.h @@ -0,0 +1,556 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK26FN2M0VMD18/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK26FN2M0VMD18_ +#define _ZEPHYR_DTS_BINDING_MK26FN2M0VMD18_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define CMP3_IN1_PTA15 KINETIS_MUX('A',15,0) /* PTA_15 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define CMP3_IN2_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define CMP3_IN4_PTA24 KINETIS_MUX('A',24,0) /* PTA_24 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define CMP3_IN5_PTA25 KINETIS_MUX('A',25,0) /* PTA_25 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define CMP3_OUT_PTB23 KINETIS_MUX('B',23,6) /* PTB_23 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define CAN1_RX_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define CAN1_TX_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART0_RX_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART0_TX_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART0_RTS_b_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define LPUART0_CTS_b_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB0_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define LPUART0_TX_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define LPUART0_RX_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define LPUART0_CTS_b_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define USB1_ID_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define LPUART0_RTS_b_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define CAN1_TX_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define CAN1_RX_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB0_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK26FN2M0VMI18-pinctrl.h b/dts/nxp/kinetis/MK26FN2M0VMI18-pinctrl.h new file mode 100644 index 000000000..67e1dcd22 --- /dev/null +++ b/dts/nxp/kinetis/MK26FN2M0VMI18-pinctrl.h @@ -0,0 +1,631 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK26FN2M0VMI18/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK26FN2M0VMI18_ +#define _ZEPHYR_DTS_BINDING_MK26FN2M0VMI18_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define CMP3_IN1_PTA15 KINETIS_MUX('A',15,0) /* PTA_15 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define CMP3_IN2_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define CMP3_IN4_PTA24 KINETIS_MUX('A',24,0) /* PTA_24 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define CMP3_IN5_PTA25 KINETIS_MUX('A',25,0) /* PTA_25 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define CAN0_TX_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define CAN0_RX_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define UART3_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define UART3_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define CAN1_TX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define CAN1_RX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define CMP3_OUT_PTB23 KINETIS_MUX('B',23,6) /* PTB_23 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define CAN1_RX_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define CAN1_TX_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART0_RX_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART0_TX_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART0_RTS_b_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define LPUART0_CTS_b_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB0_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define LPUART0_TX_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define LPUART0_RX_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define LPUART0_CTS_b_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define USB1_ID_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define LPUART0_RTS_b_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define CMP3_OUT_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define CAN1_TX_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define CAN1_RX_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB0_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK27FN2M0AVMI15-pinctrl.h b/dts/nxp/kinetis/MK27FN2M0AVMI15-pinctrl.h new file mode 100644 index 000000000..54f032275 --- /dev/null +++ b/dts/nxp/kinetis/MK27FN2M0AVMI15-pinctrl.h @@ -0,0 +1,716 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK27FN2M0AVMI15/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK27FN2M0AVMI15_ +#define _ZEPHYR_DTS_BINDING_MK27FN2M0AVMI15_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FXIO0_D11_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FXIO0_D12_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FXIO0_D13_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FXIO0_D14_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define FXIO0_D15_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define I2C2_SCL_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define I2C2_SDA_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define I2C1_SCL_PTA8 KINETIS_MUX('A',8,2) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define I2C1_SDA_PTA9 KINETIS_MUX('A',9,2) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define I2C2_SDA_PTA10 KINETIS_MUX('A',10,2) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO0_D16_PTA10 KINETIS_MUX('A',10,5) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define I2C2_SCL_PTA11 KINETIS_MUX('A',11,2) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO0_D17_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define USB1_ID_PTA11 KINETIS_MUX('A',11,7) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define TRACE_CLKOUT_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define FXIO0_D18_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define TRACE_D3_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define FXIO0_D19_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define TRACE_D2_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define FXIO0_D20_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define TRACE_D1_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define FXIO0_D21_PTA15 KINETIS_MUX('A',15,5) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define TRACE_D0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define FXIO0_D22_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define FXIO0_D23_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define I2S1_MCLK_PTA17 KINETIS_MUX('A',17,7) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define I2C0_SCL_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART4_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define FTM_CLKIN1_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define FXIO0_D8_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define EWM_OUT_b_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define TPM_CLKIN1_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LLWU_P21_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define I2C0_SDA_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART4_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define FXIO0_D9_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define EWM_IN_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define PTA22 KINETIS_MUX('A',22,1) /* PTA_22 */ +#define LPUART4_CTS_b_PTA22 KINETIS_MUX('A',22,3) /* PTA_22 */ +#define FXIO0_D6_PTA22 KINETIS_MUX('A',22,5) /* PTA_22 */ +#define RTC_CLKOUT_PTA22 KINETIS_MUX('A',22,6) /* PTA_22 */ +#define USB0_CLKIN_PTA22 KINETIS_MUX('A',22,7) /* PTA_22 */ +#define PTA23 KINETIS_MUX('A',23,1) /* PTA_23 */ +#define LPUART4_RTS_b_PTA23 KINETIS_MUX('A',23,3) /* PTA_23 */ +#define FXIO0_D7_PTA23 KINETIS_MUX('A',23,5) /* PTA_23 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define LPUART2_TX_PTA24 KINETIS_MUX('A',24,3) /* PTA_24 */ +#define SDHC0_D1_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define I2S1_TX_BCLK_PTA24 KINETIS_MUX('A',24,7) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define LPUART2_RX_PTA25 KINETIS_MUX('A',25,3) /* PTA_25 */ +#define SDHC0_D0_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define I2S1_TX_FS_PTA25 KINETIS_MUX('A',25,7) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define LPUART2_CTS_b_PTA26 KINETIS_MUX('A',26,3) /* PTA_26 */ +#define SDHC0_DCLK_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define I2S1_TXD0_PTA26 KINETIS_MUX('A',26,7) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define LPUART2_RTS_b_PTA27 KINETIS_MUX('A',27,3) /* PTA_27 */ +#define SDHC0_CMD_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define I2S1_TXD1_PTA27 KINETIS_MUX('A',27,7) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define LPUART3_TX_PTA28 KINETIS_MUX('A',28,3) /* PTA_28 */ +#define SDHC0_D3_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define I2S1_RXD1_PTA28 KINETIS_MUX('A',28,7) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define LPUART3_RX_PTA29 KINETIS_MUX('A',29,3) /* PTA_29 */ +#define SDHC0_D2_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define I2S1_RXD0_PTA29 KINETIS_MUX('A',29,7) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define I2C3_SDA_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define LPUART3_CTS_b_PTA30 KINETIS_MUX('A',30,3) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define I2S1_RX_FS_PTA30 KINETIS_MUX('A',30,7) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define I2C3_SCL_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define LPUART3_RTS_b_PTA31 KINETIS_MUX('A',31,3) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define I2S1_RX_BCLK_PTA31 KINETIS_MUX('A',31,7) /* PTA_31 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FXIO0_D0_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FXIO0_D1_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_b_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define FXIO0_D2_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define FXIO0_D3_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPUART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define I2C2_SCL_PTB10 KINETIS_MUX('B',10,4) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define FXIO0_D4_PTB10 KINETIS_MUX('B',10,7) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define I2C2_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define FXIO0_D5_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define LPUART0_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define LPUART0_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define LPUART0_RX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define LPUART0_TX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FXIO0_D6_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define SDRAM_CKE_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D7_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D8_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D9_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define FXIO0_D10_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define FXIO0_D11_PTB23 KINETIS_MUX('B',23,7) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define FXIO0_D12_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define FXIO0_D13_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define FXIO0_D14_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define FXIO0_D15_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define FXIO0_D16_PTC8 KINETIS_MUX('C',8,7) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define FXIO0_D17_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define FXIO0_D18_PTC10 KINETIS_MUX('C',10,7) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define FXIO0_D19_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPUART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPUART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define LPUART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define FXIO0_D20_PTC14 KINETIS_MUX('C',14,7) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define LPUART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define FXIO0_D21_PTC15 KINETIS_MUX('C',15,7) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define LPUART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define QSPI0A_SS1_B_PTC19 KINETIS_MUX('C',19,7) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define QSPI0A_DATA3_PTC24 KINETIS_MUX('C',24,7) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define QSPI0A_SCLK_PTC25 KINETIS_MUX('C',25,7) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define QSPI0A_DATA0_PTC26 KINETIS_MUX('C',26,7) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define QSPI0A_DATA2_PTC27 KINETIS_MUX('C',27,7) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define QSPI0A_DATA1_PTC28 KINETIS_MUX('C',28,7) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define QSPI0A_SS0_B_PTC29 KINETIS_MUX('C',29,7) /* PTC_29 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D22_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D23_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART1_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define FXIO0_D24_PTD8 KINETIS_MUX('D',8,7) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART1_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define FXIO0_D25_PTD9 KINETIS_MUX('D',9,7) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART1_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define FXIO0_D26_PTD10 KINETIS_MUX('D',10,7) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART1_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define FXIO0_D27_PTD11 KINETIS_MUX('D',11,7) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define FXIO0_D28_PTD12 KINETIS_MUX('D',12,7) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define FXIO0_D29_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define FXIO0_D30_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define FXIO0_D31_PTD15 KINETIS_MUX('D',15,7) /* PTD_15 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define QSPI0A_DATA3_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SCK_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define QSPI0A_SCLK_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define QSPI0A_DATA0_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define FXIO0_D0_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,7) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_PCS2_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define QSPI0A_DATA2_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define FXIO0_D1_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_SIN_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define QSPI0A_DATA1_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS0_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define QSPI0A_SS0_B_PTE5 KINETIS_MUX('E',5,5) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define USB0_SOF_OUT_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define FXIO0_D12_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define QSPI0B_DATA3_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define SDHC0_D4_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FXIO0_D13_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define LPUART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define QSPI0B_SCLK_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define QSPI0A_SS1_B_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define FXIO0_D14_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define QSPI0B_DATA0_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define FXIO0_D15_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define QSPI0B_DATA2_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define SDHC0_D6_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO0_D16_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define QSPI0B_DATA1_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define SDHC0_D7_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define FXIO0_D17_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define QSPI0B_SS0_B_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define QSPI0A_DQS_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define QSPI0B_DQS_PTE12 KINETIS_MUX('E',12,5) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define FXIO0_D2_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define LPUART2_RX_PTE13 KINETIS_MUX('E',13,3) /* PTE_13 */ +#define I2S1_MCLK_PTE13 KINETIS_MUX('E',13,4) /* PTE_13 */ +#define QSPI0B_SS1_B_PTE13 KINETIS_MUX('E',13,5) /* PTE_13 */ +#define SDHC0_CLKIN_PTE13 KINETIS_MUX('E',13,6) /* PTE_13 */ +#define FXIO0_D3_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define LPUART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define I2S1_TX_BCLK_PTE16 KINETIS_MUX('E',16,5) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define FXIO0_D4_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define LPUART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define I2S1_TX_FS_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define FXIO0_D5_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define LPUART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define I2S1_TXD0_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D6_PTE18 KINETIS_MUX('E',18,7) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define LPUART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define I2S1_TXD1_PTE19 KINETIS_MUX('E',19,5) /* PTE_19 */ +#define FXIO0_D7_PTE19 KINETIS_MUX('E',19,7) /* PTE_19 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define LPUART4_TX_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define SPI3_PCS0_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define I2S1_RXD1_PTE20 KINETIS_MUX('E',20,5) /* PTE_20 */ +#define FXIO0_D8_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define LPUART4_RX_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define SPI3_SCK_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define I2S1_RXD0_PTE21 KINETIS_MUX('E',21,5) /* PTE_21 */ +#define FXIO0_D9_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define I2C2_SDA_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define LPUART4_CTS_b_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define SPI3_SOUT_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define I2S1_RX_FS_PTE22 KINETIS_MUX('E',22,5) /* PTE_22 */ +#define FXIO0_D10_PTE22 KINETIS_MUX('E',22,7) /* PTE_22 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define I2C2_SCL_PTE23 KINETIS_MUX('E',23,2) /* PTE_23 */ +#define LPUART4_RTS_b_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define SPI3_SIN_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define I2S1_RX_BCLK_PTE23 KINETIS_MUX('E',23,5) /* PTE_23 */ +#define FXIO0_D11_PTE23 KINETIS_MUX('E',23,7) /* PTE_23 */ +#endif diff --git a/dts/nxp/kinetis/MK27FN2M0VMI15-pinctrl.h b/dts/nxp/kinetis/MK27FN2M0VMI15-pinctrl.h new file mode 100644 index 000000000..a0e9f41bd --- /dev/null +++ b/dts/nxp/kinetis/MK27FN2M0VMI15-pinctrl.h @@ -0,0 +1,716 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK27FN2M0VMI15/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK27FN2M0VMI15_ +#define _ZEPHYR_DTS_BINDING_MK27FN2M0VMI15_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FXIO0_D11_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FXIO0_D12_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FXIO0_D13_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FXIO0_D14_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define FXIO0_D15_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define I2C2_SCL_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define I2C2_SDA_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define I2C1_SCL_PTA8 KINETIS_MUX('A',8,2) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define I2C1_SDA_PTA9 KINETIS_MUX('A',9,2) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define I2C2_SDA_PTA10 KINETIS_MUX('A',10,2) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO0_D16_PTA10 KINETIS_MUX('A',10,5) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define I2C2_SCL_PTA11 KINETIS_MUX('A',11,2) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO0_D17_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define USB1_ID_PTA11 KINETIS_MUX('A',11,7) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define TRACE_CLKOUT_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define FXIO0_D18_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define TRACE_D3_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define FXIO0_D19_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define TRACE_D2_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define FXIO0_D20_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define TRACE_D1_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define FXIO0_D21_PTA15 KINETIS_MUX('A',15,5) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define TRACE_D0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define FXIO0_D22_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define FXIO0_D23_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define I2S1_MCLK_PTA17 KINETIS_MUX('A',17,7) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define I2C0_SCL_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART4_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define FTM_CLKIN1_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define FXIO0_D8_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define EWM_OUT_b_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define TPM_CLKIN1_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LLWU_P21_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define I2C0_SDA_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART4_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define FXIO0_D9_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define EWM_IN_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define PTA22 KINETIS_MUX('A',22,1) /* PTA_22 */ +#define LPUART4_CTS_b_PTA22 KINETIS_MUX('A',22,3) /* PTA_22 */ +#define FXIO0_D6_PTA22 KINETIS_MUX('A',22,5) /* PTA_22 */ +#define RTC_CLKOUT_PTA22 KINETIS_MUX('A',22,6) /* PTA_22 */ +#define USB0_CLKIN_PTA22 KINETIS_MUX('A',22,7) /* PTA_22 */ +#define PTA23 KINETIS_MUX('A',23,1) /* PTA_23 */ +#define LPUART4_RTS_b_PTA23 KINETIS_MUX('A',23,3) /* PTA_23 */ +#define FXIO0_D7_PTA23 KINETIS_MUX('A',23,5) /* PTA_23 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define LPUART2_TX_PTA24 KINETIS_MUX('A',24,3) /* PTA_24 */ +#define SDHC0_D1_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define I2S1_TX_BCLK_PTA24 KINETIS_MUX('A',24,7) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define LPUART2_RX_PTA25 KINETIS_MUX('A',25,3) /* PTA_25 */ +#define SDHC0_D0_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define I2S1_TX_FS_PTA25 KINETIS_MUX('A',25,7) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define LPUART2_CTS_b_PTA26 KINETIS_MUX('A',26,3) /* PTA_26 */ +#define SDHC0_DCLK_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define I2S1_TXD0_PTA26 KINETIS_MUX('A',26,7) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define LPUART2_RTS_b_PTA27 KINETIS_MUX('A',27,3) /* PTA_27 */ +#define SDHC0_CMD_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define I2S1_TXD1_PTA27 KINETIS_MUX('A',27,7) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define LPUART3_TX_PTA28 KINETIS_MUX('A',28,3) /* PTA_28 */ +#define SDHC0_D3_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define I2S1_RXD1_PTA28 KINETIS_MUX('A',28,7) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define LPUART3_RX_PTA29 KINETIS_MUX('A',29,3) /* PTA_29 */ +#define SDHC0_D2_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define I2S1_RXD0_PTA29 KINETIS_MUX('A',29,7) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define I2C3_SDA_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define LPUART3_CTS_b_PTA30 KINETIS_MUX('A',30,3) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define I2S1_RX_FS_PTA30 KINETIS_MUX('A',30,7) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define I2C3_SCL_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define LPUART3_RTS_b_PTA31 KINETIS_MUX('A',31,3) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define I2S1_RX_BCLK_PTA31 KINETIS_MUX('A',31,7) /* PTA_31 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FXIO0_D0_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FXIO0_D1_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_b_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define FXIO0_D2_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define FXIO0_D3_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPUART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define I2C2_SCL_PTB10 KINETIS_MUX('B',10,4) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define FXIO0_D4_PTB10 KINETIS_MUX('B',10,7) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define I2C2_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define FXIO0_D5_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define LPUART0_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define LPUART0_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define LPUART0_RX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define LPUART0_TX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FXIO0_D6_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define SDRAM_CKE_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D7_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D8_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D9_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define FXIO0_D10_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define FXIO0_D11_PTB23 KINETIS_MUX('B',23,7) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define FXIO0_D12_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define FXIO0_D13_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define FXIO0_D14_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define FXIO0_D15_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define FXIO0_D16_PTC8 KINETIS_MUX('C',8,7) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define FXIO0_D17_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define FXIO0_D18_PTC10 KINETIS_MUX('C',10,7) /* PTC_10 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define FXIO0_D19_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPUART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPUART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define LPUART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define FXIO0_D20_PTC14 KINETIS_MUX('C',14,7) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define LPUART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define FXIO0_D21_PTC15 KINETIS_MUX('C',15,7) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define LPUART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define QSPI0A_SS1_B_PTC19 KINETIS_MUX('C',19,7) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define QSPI0A_DATA3_PTC24 KINETIS_MUX('C',24,7) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define QSPI0A_SCLK_PTC25 KINETIS_MUX('C',25,7) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define QSPI0A_DATA0_PTC26 KINETIS_MUX('C',26,7) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define QSPI0A_DATA2_PTC27 KINETIS_MUX('C',27,7) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define QSPI0A_DATA1_PTC28 KINETIS_MUX('C',28,7) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define QSPI0A_SS0_B_PTC29 KINETIS_MUX('C',29,7) /* PTC_29 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D22_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D23_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART1_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define FXIO0_D24_PTD8 KINETIS_MUX('D',8,7) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART1_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define FXIO0_D25_PTD9 KINETIS_MUX('D',9,7) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART1_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define FXIO0_D26_PTD10 KINETIS_MUX('D',10,7) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART1_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define FXIO0_D27_PTD11 KINETIS_MUX('D',11,7) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define FXIO0_D28_PTD12 KINETIS_MUX('D',12,7) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define FXIO0_D29_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define FXIO0_D30_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define FXIO0_D31_PTD15 KINETIS_MUX('D',15,7) /* PTD_15 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define QSPI0A_DATA3_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SCK_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define QSPI0A_SCLK_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define QSPI0A_DATA0_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define FXIO0_D0_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,7) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_PCS2_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define QSPI0A_DATA2_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define FXIO0_D1_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_SIN_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define QSPI0A_DATA1_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS0_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define QSPI0A_SS0_B_PTE5 KINETIS_MUX('E',5,5) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define USB0_SOF_OUT_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define FXIO0_D12_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define QSPI0B_DATA3_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define SDHC0_D4_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FXIO0_D13_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define LPUART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define QSPI0B_SCLK_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define QSPI0A_SS1_B_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define FXIO0_D14_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define QSPI0B_DATA0_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define FXIO0_D15_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define QSPI0B_DATA2_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define SDHC0_D6_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO0_D16_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define QSPI0B_DATA1_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define SDHC0_D7_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define FXIO0_D17_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define QSPI0B_SS0_B_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define QSPI0A_DQS_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define QSPI0B_DQS_PTE12 KINETIS_MUX('E',12,5) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define FXIO0_D2_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define LPUART2_RX_PTE13 KINETIS_MUX('E',13,3) /* PTE_13 */ +#define I2S1_MCLK_PTE13 KINETIS_MUX('E',13,4) /* PTE_13 */ +#define QSPI0B_SS1_B_PTE13 KINETIS_MUX('E',13,5) /* PTE_13 */ +#define SDHC0_CLKIN_PTE13 KINETIS_MUX('E',13,6) /* PTE_13 */ +#define FXIO0_D3_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define LPUART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define I2S1_TX_BCLK_PTE16 KINETIS_MUX('E',16,5) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define FXIO0_D4_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define LPUART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define I2S1_TX_FS_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define FXIO0_D5_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define LPUART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define I2S1_TXD0_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D6_PTE18 KINETIS_MUX('E',18,7) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define LPUART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define I2S1_TXD1_PTE19 KINETIS_MUX('E',19,5) /* PTE_19 */ +#define FXIO0_D7_PTE19 KINETIS_MUX('E',19,7) /* PTE_19 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define LPUART4_TX_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define SPI3_PCS0_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define I2S1_RXD1_PTE20 KINETIS_MUX('E',20,5) /* PTE_20 */ +#define FXIO0_D8_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define LPUART4_RX_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define SPI3_SCK_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define I2S1_RXD0_PTE21 KINETIS_MUX('E',21,5) /* PTE_21 */ +#define FXIO0_D9_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define I2C2_SDA_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define LPUART4_CTS_b_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define SPI3_SOUT_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define I2S1_RX_FS_PTE22 KINETIS_MUX('E',22,5) /* PTE_22 */ +#define FXIO0_D10_PTE22 KINETIS_MUX('E',22,7) /* PTE_22 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define I2C2_SCL_PTE23 KINETIS_MUX('E',23,2) /* PTE_23 */ +#define LPUART4_RTS_b_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define SPI3_SIN_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define I2S1_RX_BCLK_PTE23 KINETIS_MUX('E',23,5) /* PTE_23 */ +#define FXIO0_D11_PTE23 KINETIS_MUX('E',23,7) /* PTE_23 */ +#endif diff --git a/dts/nxp/kinetis/MK28FN2M0ACAU15R-pinctrl.h b/dts/nxp/kinetis/MK28FN2M0ACAU15R-pinctrl.h new file mode 100644 index 000000000..1980a3202 --- /dev/null +++ b/dts/nxp/kinetis/MK28FN2M0ACAU15R-pinctrl.h @@ -0,0 +1,716 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK28FN2M0ACAU15R/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK28FN2M0ACAU15R_ +#define _ZEPHYR_DTS_BINDING_MK28FN2M0ACAU15R_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FXIO0_D11_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FXIO0_D12_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FXIO0_D13_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FXIO0_D14_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define FXIO0_D15_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define I2C2_SCL_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define I2C2_SDA_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define I2C1_SCL_PTA8 KINETIS_MUX('A',8,2) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define I2C1_SDA_PTA9 KINETIS_MUX('A',9,2) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define I2C2_SDA_PTA10 KINETIS_MUX('A',10,2) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO0_D16_PTA10 KINETIS_MUX('A',10,5) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define I2C2_SCL_PTA11 KINETIS_MUX('A',11,2) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO0_D17_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define USB1_ID_PTA11 KINETIS_MUX('A',11,7) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define TRACE_CLKOUT_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define FXIO0_D18_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define TRACE_D3_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define FXIO0_D19_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define TRACE_D2_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define FXIO0_D20_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define TRACE_D1_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define FXIO0_D21_PTA15 KINETIS_MUX('A',15,5) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define TRACE_D0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define FXIO0_D22_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define FXIO0_D23_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define I2S1_MCLK_PTA17 KINETIS_MUX('A',17,7) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define I2C0_SCL_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART4_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define FTM_CLKIN1_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define FXIO0_D8_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define EWM_OUT_b_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define TPM_CLKIN1_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LLWU_P21_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define I2C0_SDA_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART4_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define FXIO0_D9_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define EWM_IN_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define PTA22 KINETIS_MUX('A',22,1) /* PTA_22 */ +#define LPUART4_CTS_b_PTA22 KINETIS_MUX('A',22,3) /* PTA_22 */ +#define FXIO0_D6_PTA22 KINETIS_MUX('A',22,5) /* PTA_22 */ +#define RTC_CLKOUT_PTA22 KINETIS_MUX('A',22,6) /* PTA_22 */ +#define USB0_CLKIN_PTA22 KINETIS_MUX('A',22,7) /* PTA_22 */ +#define PTA23 KINETIS_MUX('A',23,1) /* PTA_23 */ +#define LPUART4_RTS_b_PTA23 KINETIS_MUX('A',23,3) /* PTA_23 */ +#define FXIO0_D7_PTA23 KINETIS_MUX('A',23,5) /* PTA_23 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define LPUART2_TX_PTA24 KINETIS_MUX('A',24,3) /* PTA_24 */ +#define SDHC0_D1_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define I2S1_TX_BCLK_PTA24 KINETIS_MUX('A',24,7) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define LPUART2_RX_PTA25 KINETIS_MUX('A',25,3) /* PTA_25 */ +#define SDHC0_D0_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define I2S1_TX_FS_PTA25 KINETIS_MUX('A',25,7) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define LPUART2_CTS_b_PTA26 KINETIS_MUX('A',26,3) /* PTA_26 */ +#define SDHC0_DCLK_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define I2S1_TXD0_PTA26 KINETIS_MUX('A',26,7) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define LPUART2_RTS_b_PTA27 KINETIS_MUX('A',27,3) /* PTA_27 */ +#define SDHC0_CMD_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define I2S1_TXD1_PTA27 KINETIS_MUX('A',27,7) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define LPUART3_TX_PTA28 KINETIS_MUX('A',28,3) /* PTA_28 */ +#define SDHC0_D3_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define I2S1_RXD1_PTA28 KINETIS_MUX('A',28,7) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define LPUART3_RX_PTA29 KINETIS_MUX('A',29,3) /* PTA_29 */ +#define SDHC0_D2_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define I2S1_RXD0_PTA29 KINETIS_MUX('A',29,7) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define I2C3_SDA_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define LPUART3_CTS_b_PTA30 KINETIS_MUX('A',30,3) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define I2S1_RX_FS_PTA30 KINETIS_MUX('A',30,7) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define I2C3_SCL_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define LPUART3_RTS_b_PTA31 KINETIS_MUX('A',31,3) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define I2S1_RX_BCLK_PTA31 KINETIS_MUX('A',31,7) /* PTA_31 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FXIO0_D0_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FXIO0_D1_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_b_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define FXIO0_D2_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define FXIO0_D3_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPUART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define I2C2_SCL_PTB10 KINETIS_MUX('B',10,4) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define FXIO0_D4_PTB10 KINETIS_MUX('B',10,7) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define I2C2_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define FXIO0_D5_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define LPUART0_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define LPUART0_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define LPUART0_RX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define LPUART0_TX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FXIO0_D6_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define SDRAM_CKE_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D7_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D8_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D9_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define FXIO0_D10_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define FXIO0_D11_PTB23 KINETIS_MUX('B',23,7) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define FXIO0_D12_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define FXIO0_D13_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define FXIO0_D14_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define FXIO0_D15_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define FXIO0_D16_PTC8 KINETIS_MUX('C',8,7) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define FXIO0_D17_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define FXIO0_D18_PTC10 KINETIS_MUX('C',10,7) /* PTC_10 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define FXIO0_D19_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPUART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPUART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define LPUART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define FXIO0_D20_PTC14 KINETIS_MUX('C',14,7) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define LPUART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define FXIO0_D21_PTC15 KINETIS_MUX('C',15,7) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define LPUART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define QSPI0A_SS1_B_PTC19 KINETIS_MUX('C',19,7) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define QSPI0A_DATA3_PTC24 KINETIS_MUX('C',24,7) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define QSPI0A_SCLK_PTC25 KINETIS_MUX('C',25,7) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define QSPI0A_DATA0_PTC26 KINETIS_MUX('C',26,7) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define QSPI0A_DATA2_PTC27 KINETIS_MUX('C',27,7) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define QSPI0A_DATA1_PTC28 KINETIS_MUX('C',28,7) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define QSPI0A_SS0_B_PTC29 KINETIS_MUX('C',29,7) /* PTC_29 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D22_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D23_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART1_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define FXIO0_D24_PTD8 KINETIS_MUX('D',8,7) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART1_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define FXIO0_D25_PTD9 KINETIS_MUX('D',9,7) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART1_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define FXIO0_D26_PTD10 KINETIS_MUX('D',10,7) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART1_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define FXIO0_D27_PTD11 KINETIS_MUX('D',11,7) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define FXIO0_D28_PTD12 KINETIS_MUX('D',12,7) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define FXIO0_D29_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define FXIO0_D30_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define FXIO0_D31_PTD15 KINETIS_MUX('D',15,7) /* PTD_15 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define QSPI0A_DATA3_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SCK_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define QSPI0A_SCLK_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define QSPI0A_DATA0_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define FXIO0_D0_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,7) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_PCS2_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define QSPI0A_DATA2_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define FXIO0_D1_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_SIN_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define QSPI0A_DATA1_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS0_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define QSPI0A_SS0_B_PTE5 KINETIS_MUX('E',5,5) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define USB0_SOF_OUT_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define FXIO0_D12_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define QSPI0B_DATA3_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define SDHC0_D4_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FXIO0_D13_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define LPUART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define QSPI0B_SCLK_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define QSPI0A_SS1_B_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define FXIO0_D14_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define QSPI0B_DATA0_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define FXIO0_D15_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define QSPI0B_DATA2_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define SDHC0_D6_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO0_D16_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define QSPI0B_DATA1_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define SDHC0_D7_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define FXIO0_D17_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define QSPI0B_SS0_B_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define QSPI0A_DQS_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define QSPI0B_DQS_PTE12 KINETIS_MUX('E',12,5) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define FXIO0_D2_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define LPUART2_RX_PTE13 KINETIS_MUX('E',13,3) /* PTE_13 */ +#define I2S1_MCLK_PTE13 KINETIS_MUX('E',13,4) /* PTE_13 */ +#define QSPI0B_SS1_B_PTE13 KINETIS_MUX('E',13,5) /* PTE_13 */ +#define SDHC0_CLKIN_PTE13 KINETIS_MUX('E',13,6) /* PTE_13 */ +#define FXIO0_D3_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define LPUART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define I2S1_TX_BCLK_PTE16 KINETIS_MUX('E',16,5) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define FXIO0_D4_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define LPUART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define I2S1_TX_FS_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define FXIO0_D5_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define LPUART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define I2S1_TXD0_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D6_PTE18 KINETIS_MUX('E',18,7) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define LPUART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define I2S1_TXD1_PTE19 KINETIS_MUX('E',19,5) /* PTE_19 */ +#define FXIO0_D7_PTE19 KINETIS_MUX('E',19,7) /* PTE_19 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define LPUART4_TX_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define SPI3_PCS0_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define I2S1_RXD1_PTE20 KINETIS_MUX('E',20,5) /* PTE_20 */ +#define FXIO0_D8_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define LPUART4_RX_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define SPI3_SCK_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define I2S1_RXD0_PTE21 KINETIS_MUX('E',21,5) /* PTE_21 */ +#define FXIO0_D9_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define I2C2_SDA_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define LPUART4_CTS_b_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define SPI3_SOUT_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define I2S1_RX_FS_PTE22 KINETIS_MUX('E',22,5) /* PTE_22 */ +#define FXIO0_D10_PTE22 KINETIS_MUX('E',22,7) /* PTE_22 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define I2C2_SCL_PTE23 KINETIS_MUX('E',23,2) /* PTE_23 */ +#define LPUART4_RTS_b_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define SPI3_SIN_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define I2S1_RX_BCLK_PTE23 KINETIS_MUX('E',23,5) /* PTE_23 */ +#define FXIO0_D11_PTE23 KINETIS_MUX('E',23,7) /* PTE_23 */ +#endif diff --git a/dts/nxp/kinetis/MK28FN2M0AVMI15-pinctrl.h b/dts/nxp/kinetis/MK28FN2M0AVMI15-pinctrl.h new file mode 100644 index 000000000..993c4cc20 --- /dev/null +++ b/dts/nxp/kinetis/MK28FN2M0AVMI15-pinctrl.h @@ -0,0 +1,716 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK28FN2M0AVMI15/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK28FN2M0AVMI15_ +#define _ZEPHYR_DTS_BINDING_MK28FN2M0AVMI15_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FXIO0_D11_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FXIO0_D12_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FXIO0_D13_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FXIO0_D14_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define FXIO0_D15_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define I2C2_SCL_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define I2C2_SDA_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define I2C1_SCL_PTA8 KINETIS_MUX('A',8,2) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define I2C1_SDA_PTA9 KINETIS_MUX('A',9,2) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define I2C2_SDA_PTA10 KINETIS_MUX('A',10,2) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO0_D16_PTA10 KINETIS_MUX('A',10,5) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define I2C2_SCL_PTA11 KINETIS_MUX('A',11,2) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO0_D17_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define USB1_ID_PTA11 KINETIS_MUX('A',11,7) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define TRACE_CLKOUT_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define FXIO0_D18_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define TRACE_D3_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define FXIO0_D19_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define TRACE_D2_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define FXIO0_D20_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define TRACE_D1_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define FXIO0_D21_PTA15 KINETIS_MUX('A',15,5) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define TRACE_D0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define FXIO0_D22_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define FXIO0_D23_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define I2S1_MCLK_PTA17 KINETIS_MUX('A',17,7) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define I2C0_SCL_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART4_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define FTM_CLKIN1_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define FXIO0_D8_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define EWM_OUT_b_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define TPM_CLKIN1_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LLWU_P21_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define I2C0_SDA_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART4_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define FXIO0_D9_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define EWM_IN_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define PTA22 KINETIS_MUX('A',22,1) /* PTA_22 */ +#define LPUART4_CTS_b_PTA22 KINETIS_MUX('A',22,3) /* PTA_22 */ +#define FXIO0_D6_PTA22 KINETIS_MUX('A',22,5) /* PTA_22 */ +#define RTC_CLKOUT_PTA22 KINETIS_MUX('A',22,6) /* PTA_22 */ +#define USB0_CLKIN_PTA22 KINETIS_MUX('A',22,7) /* PTA_22 */ +#define PTA23 KINETIS_MUX('A',23,1) /* PTA_23 */ +#define LPUART4_RTS_b_PTA23 KINETIS_MUX('A',23,3) /* PTA_23 */ +#define FXIO0_D7_PTA23 KINETIS_MUX('A',23,5) /* PTA_23 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define LPUART2_TX_PTA24 KINETIS_MUX('A',24,3) /* PTA_24 */ +#define SDHC0_D1_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define I2S1_TX_BCLK_PTA24 KINETIS_MUX('A',24,7) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define LPUART2_RX_PTA25 KINETIS_MUX('A',25,3) /* PTA_25 */ +#define SDHC0_D0_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define I2S1_TX_FS_PTA25 KINETIS_MUX('A',25,7) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define LPUART2_CTS_b_PTA26 KINETIS_MUX('A',26,3) /* PTA_26 */ +#define SDHC0_DCLK_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define I2S1_TXD0_PTA26 KINETIS_MUX('A',26,7) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define LPUART2_RTS_b_PTA27 KINETIS_MUX('A',27,3) /* PTA_27 */ +#define SDHC0_CMD_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define I2S1_TXD1_PTA27 KINETIS_MUX('A',27,7) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define LPUART3_TX_PTA28 KINETIS_MUX('A',28,3) /* PTA_28 */ +#define SDHC0_D3_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define I2S1_RXD1_PTA28 KINETIS_MUX('A',28,7) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define LPUART3_RX_PTA29 KINETIS_MUX('A',29,3) /* PTA_29 */ +#define SDHC0_D2_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define I2S1_RXD0_PTA29 KINETIS_MUX('A',29,7) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define I2C3_SDA_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define LPUART3_CTS_b_PTA30 KINETIS_MUX('A',30,3) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define I2S1_RX_FS_PTA30 KINETIS_MUX('A',30,7) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define I2C3_SCL_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define LPUART3_RTS_b_PTA31 KINETIS_MUX('A',31,3) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define I2S1_RX_BCLK_PTA31 KINETIS_MUX('A',31,7) /* PTA_31 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FXIO0_D0_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FXIO0_D1_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_b_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define FXIO0_D2_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define FXIO0_D3_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPUART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define I2C2_SCL_PTB10 KINETIS_MUX('B',10,4) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define FXIO0_D4_PTB10 KINETIS_MUX('B',10,7) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define I2C2_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define FXIO0_D5_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define LPUART0_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define LPUART0_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define LPUART0_RX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define LPUART0_TX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FXIO0_D6_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define SDRAM_CKE_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D7_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D8_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D9_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define FXIO0_D10_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define FXIO0_D11_PTB23 KINETIS_MUX('B',23,7) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define FXIO0_D12_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define FXIO0_D13_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define FXIO0_D14_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define FXIO0_D15_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define FXIO0_D16_PTC8 KINETIS_MUX('C',8,7) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define FXIO0_D17_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define FXIO0_D18_PTC10 KINETIS_MUX('C',10,7) /* PTC_10 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define FXIO0_D19_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPUART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPUART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define LPUART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define FXIO0_D20_PTC14 KINETIS_MUX('C',14,7) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define LPUART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define FXIO0_D21_PTC15 KINETIS_MUX('C',15,7) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define LPUART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define QSPI0A_SS1_B_PTC19 KINETIS_MUX('C',19,7) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define QSPI0A_DATA3_PTC24 KINETIS_MUX('C',24,7) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define QSPI0A_SCLK_PTC25 KINETIS_MUX('C',25,7) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define QSPI0A_DATA0_PTC26 KINETIS_MUX('C',26,7) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define QSPI0A_DATA2_PTC27 KINETIS_MUX('C',27,7) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define QSPI0A_DATA1_PTC28 KINETIS_MUX('C',28,7) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define QSPI0A_SS0_B_PTC29 KINETIS_MUX('C',29,7) /* PTC_29 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D22_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D23_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART1_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define FXIO0_D24_PTD8 KINETIS_MUX('D',8,7) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART1_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define FXIO0_D25_PTD9 KINETIS_MUX('D',9,7) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART1_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define FXIO0_D26_PTD10 KINETIS_MUX('D',10,7) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART1_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define FXIO0_D27_PTD11 KINETIS_MUX('D',11,7) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define FXIO0_D28_PTD12 KINETIS_MUX('D',12,7) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define FXIO0_D29_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define FXIO0_D30_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define FXIO0_D31_PTD15 KINETIS_MUX('D',15,7) /* PTD_15 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define QSPI0A_DATA3_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SCK_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define QSPI0A_SCLK_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define QSPI0A_DATA0_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define FXIO0_D0_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,7) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_PCS2_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define QSPI0A_DATA2_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define FXIO0_D1_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_SIN_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define QSPI0A_DATA1_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS0_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define QSPI0A_SS0_B_PTE5 KINETIS_MUX('E',5,5) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define USB0_SOF_OUT_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define FXIO0_D12_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define QSPI0B_DATA3_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define SDHC0_D4_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FXIO0_D13_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define LPUART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define QSPI0B_SCLK_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define QSPI0A_SS1_B_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define FXIO0_D14_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define QSPI0B_DATA0_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define FXIO0_D15_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define QSPI0B_DATA2_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define SDHC0_D6_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO0_D16_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define QSPI0B_DATA1_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define SDHC0_D7_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define FXIO0_D17_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define QSPI0B_SS0_B_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define QSPI0A_DQS_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define QSPI0B_DQS_PTE12 KINETIS_MUX('E',12,5) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define FXIO0_D2_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define LPUART2_RX_PTE13 KINETIS_MUX('E',13,3) /* PTE_13 */ +#define I2S1_MCLK_PTE13 KINETIS_MUX('E',13,4) /* PTE_13 */ +#define QSPI0B_SS1_B_PTE13 KINETIS_MUX('E',13,5) /* PTE_13 */ +#define SDHC0_CLKIN_PTE13 KINETIS_MUX('E',13,6) /* PTE_13 */ +#define FXIO0_D3_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define LPUART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define I2S1_TX_BCLK_PTE16 KINETIS_MUX('E',16,5) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define FXIO0_D4_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define LPUART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define I2S1_TX_FS_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define FXIO0_D5_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define LPUART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define I2S1_TXD0_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D6_PTE18 KINETIS_MUX('E',18,7) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define LPUART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define I2S1_TXD1_PTE19 KINETIS_MUX('E',19,5) /* PTE_19 */ +#define FXIO0_D7_PTE19 KINETIS_MUX('E',19,7) /* PTE_19 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define LPUART4_TX_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define SPI3_PCS0_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define I2S1_RXD1_PTE20 KINETIS_MUX('E',20,5) /* PTE_20 */ +#define FXIO0_D8_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define LPUART4_RX_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define SPI3_SCK_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define I2S1_RXD0_PTE21 KINETIS_MUX('E',21,5) /* PTE_21 */ +#define FXIO0_D9_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define I2C2_SDA_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define LPUART4_CTS_b_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define SPI3_SOUT_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define I2S1_RX_FS_PTE22 KINETIS_MUX('E',22,5) /* PTE_22 */ +#define FXIO0_D10_PTE22 KINETIS_MUX('E',22,7) /* PTE_22 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define I2C2_SCL_PTE23 KINETIS_MUX('E',23,2) /* PTE_23 */ +#define LPUART4_RTS_b_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define SPI3_SIN_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define I2S1_RX_BCLK_PTE23 KINETIS_MUX('E',23,5) /* PTE_23 */ +#define FXIO0_D11_PTE23 KINETIS_MUX('E',23,7) /* PTE_23 */ +#endif diff --git a/dts/nxp/kinetis/MK28FN2M0CAU15R-pinctrl.h b/dts/nxp/kinetis/MK28FN2M0CAU15R-pinctrl.h new file mode 100644 index 000000000..485ffc97e --- /dev/null +++ b/dts/nxp/kinetis/MK28FN2M0CAU15R-pinctrl.h @@ -0,0 +1,716 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK28FN2M0CAU15R/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK28FN2M0CAU15R_ +#define _ZEPHYR_DTS_BINDING_MK28FN2M0CAU15R_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FXIO0_D11_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FXIO0_D12_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FXIO0_D13_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FXIO0_D14_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define FXIO0_D15_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define I2C2_SCL_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define I2C2_SDA_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define I2C1_SCL_PTA8 KINETIS_MUX('A',8,2) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define I2C1_SDA_PTA9 KINETIS_MUX('A',9,2) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define I2C2_SDA_PTA10 KINETIS_MUX('A',10,2) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO0_D16_PTA10 KINETIS_MUX('A',10,5) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define I2C2_SCL_PTA11 KINETIS_MUX('A',11,2) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO0_D17_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define USB1_ID_PTA11 KINETIS_MUX('A',11,7) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define TRACE_CLKOUT_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define FXIO0_D18_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define TRACE_D3_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define FXIO0_D19_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define TRACE_D2_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define FXIO0_D20_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define TRACE_D1_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define FXIO0_D21_PTA15 KINETIS_MUX('A',15,5) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define TRACE_D0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define FXIO0_D22_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define FXIO0_D23_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define I2S1_MCLK_PTA17 KINETIS_MUX('A',17,7) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define I2C0_SCL_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART4_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define FTM_CLKIN1_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define FXIO0_D8_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define EWM_OUT_b_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define TPM_CLKIN1_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LLWU_P21_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define I2C0_SDA_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART4_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define FXIO0_D9_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define EWM_IN_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define PTA22 KINETIS_MUX('A',22,1) /* PTA_22 */ +#define LPUART4_CTS_b_PTA22 KINETIS_MUX('A',22,3) /* PTA_22 */ +#define FXIO0_D6_PTA22 KINETIS_MUX('A',22,5) /* PTA_22 */ +#define RTC_CLKOUT_PTA22 KINETIS_MUX('A',22,6) /* PTA_22 */ +#define USB0_CLKIN_PTA22 KINETIS_MUX('A',22,7) /* PTA_22 */ +#define PTA23 KINETIS_MUX('A',23,1) /* PTA_23 */ +#define LPUART4_RTS_b_PTA23 KINETIS_MUX('A',23,3) /* PTA_23 */ +#define FXIO0_D7_PTA23 KINETIS_MUX('A',23,5) /* PTA_23 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define LPUART2_TX_PTA24 KINETIS_MUX('A',24,3) /* PTA_24 */ +#define SDHC0_D1_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define I2S1_TX_BCLK_PTA24 KINETIS_MUX('A',24,7) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define LPUART2_RX_PTA25 KINETIS_MUX('A',25,3) /* PTA_25 */ +#define SDHC0_D0_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define I2S1_TX_FS_PTA25 KINETIS_MUX('A',25,7) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define LPUART2_CTS_b_PTA26 KINETIS_MUX('A',26,3) /* PTA_26 */ +#define SDHC0_DCLK_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define I2S1_TXD0_PTA26 KINETIS_MUX('A',26,7) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define LPUART2_RTS_b_PTA27 KINETIS_MUX('A',27,3) /* PTA_27 */ +#define SDHC0_CMD_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define I2S1_TXD1_PTA27 KINETIS_MUX('A',27,7) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define LPUART3_TX_PTA28 KINETIS_MUX('A',28,3) /* PTA_28 */ +#define SDHC0_D3_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define I2S1_RXD1_PTA28 KINETIS_MUX('A',28,7) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define LPUART3_RX_PTA29 KINETIS_MUX('A',29,3) /* PTA_29 */ +#define SDHC0_D2_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define I2S1_RXD0_PTA29 KINETIS_MUX('A',29,7) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define I2C3_SDA_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define LPUART3_CTS_b_PTA30 KINETIS_MUX('A',30,3) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define I2S1_RX_FS_PTA30 KINETIS_MUX('A',30,7) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define I2C3_SCL_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define LPUART3_RTS_b_PTA31 KINETIS_MUX('A',31,3) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define I2S1_RX_BCLK_PTA31 KINETIS_MUX('A',31,7) /* PTA_31 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FXIO0_D0_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FXIO0_D1_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_b_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define FXIO0_D2_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define FXIO0_D3_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPUART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define I2C2_SCL_PTB10 KINETIS_MUX('B',10,4) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define FXIO0_D4_PTB10 KINETIS_MUX('B',10,7) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define I2C2_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define FXIO0_D5_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define LPUART0_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define LPUART0_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define LPUART0_RX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define LPUART0_TX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FXIO0_D6_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define SDRAM_CKE_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D7_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D8_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D9_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define FXIO0_D10_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define FXIO0_D11_PTB23 KINETIS_MUX('B',23,7) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define FXIO0_D12_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define FXIO0_D13_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define FXIO0_D14_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define FXIO0_D15_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define FXIO0_D16_PTC8 KINETIS_MUX('C',8,7) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define FXIO0_D17_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define FXIO0_D18_PTC10 KINETIS_MUX('C',10,7) /* PTC_10 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define FXIO0_D19_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPUART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPUART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define LPUART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define FXIO0_D20_PTC14 KINETIS_MUX('C',14,7) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define LPUART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define FXIO0_D21_PTC15 KINETIS_MUX('C',15,7) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define LPUART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define QSPI0A_SS1_B_PTC19 KINETIS_MUX('C',19,7) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define QSPI0A_DATA3_PTC24 KINETIS_MUX('C',24,7) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define QSPI0A_SCLK_PTC25 KINETIS_MUX('C',25,7) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define QSPI0A_DATA0_PTC26 KINETIS_MUX('C',26,7) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define QSPI0A_DATA2_PTC27 KINETIS_MUX('C',27,7) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define QSPI0A_DATA1_PTC28 KINETIS_MUX('C',28,7) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define QSPI0A_SS0_B_PTC29 KINETIS_MUX('C',29,7) /* PTC_29 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D22_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D23_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART1_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define FXIO0_D24_PTD8 KINETIS_MUX('D',8,7) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART1_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define FXIO0_D25_PTD9 KINETIS_MUX('D',9,7) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART1_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define FXIO0_D26_PTD10 KINETIS_MUX('D',10,7) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART1_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define FXIO0_D27_PTD11 KINETIS_MUX('D',11,7) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define FXIO0_D28_PTD12 KINETIS_MUX('D',12,7) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define FXIO0_D29_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define FXIO0_D30_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define FXIO0_D31_PTD15 KINETIS_MUX('D',15,7) /* PTD_15 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define QSPI0A_DATA3_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SCK_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define QSPI0A_SCLK_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define QSPI0A_DATA0_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define FXIO0_D0_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,7) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_PCS2_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define QSPI0A_DATA2_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define FXIO0_D1_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_SIN_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define QSPI0A_DATA1_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS0_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define QSPI0A_SS0_B_PTE5 KINETIS_MUX('E',5,5) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define USB0_SOF_OUT_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define FXIO0_D12_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define QSPI0B_DATA3_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define SDHC0_D4_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FXIO0_D13_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define LPUART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define QSPI0B_SCLK_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define QSPI0A_SS1_B_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define FXIO0_D14_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define QSPI0B_DATA0_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define FXIO0_D15_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define QSPI0B_DATA2_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define SDHC0_D6_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO0_D16_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define QSPI0B_DATA1_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define SDHC0_D7_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define FXIO0_D17_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define QSPI0B_SS0_B_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define QSPI0A_DQS_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define QSPI0B_DQS_PTE12 KINETIS_MUX('E',12,5) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define FXIO0_D2_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define LPUART2_RX_PTE13 KINETIS_MUX('E',13,3) /* PTE_13 */ +#define I2S1_MCLK_PTE13 KINETIS_MUX('E',13,4) /* PTE_13 */ +#define QSPI0B_SS1_B_PTE13 KINETIS_MUX('E',13,5) /* PTE_13 */ +#define SDHC0_CLKIN_PTE13 KINETIS_MUX('E',13,6) /* PTE_13 */ +#define FXIO0_D3_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define LPUART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define I2S1_TX_BCLK_PTE16 KINETIS_MUX('E',16,5) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define FXIO0_D4_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define LPUART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define I2S1_TX_FS_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define FXIO0_D5_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define LPUART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define I2S1_TXD0_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D6_PTE18 KINETIS_MUX('E',18,7) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define LPUART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define I2S1_TXD1_PTE19 KINETIS_MUX('E',19,5) /* PTE_19 */ +#define FXIO0_D7_PTE19 KINETIS_MUX('E',19,7) /* PTE_19 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define LPUART4_TX_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define SPI3_PCS0_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define I2S1_RXD1_PTE20 KINETIS_MUX('E',20,5) /* PTE_20 */ +#define FXIO0_D8_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define LPUART4_RX_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define SPI3_SCK_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define I2S1_RXD0_PTE21 KINETIS_MUX('E',21,5) /* PTE_21 */ +#define FXIO0_D9_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define I2C2_SDA_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define LPUART4_CTS_b_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define SPI3_SOUT_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define I2S1_RX_FS_PTE22 KINETIS_MUX('E',22,5) /* PTE_22 */ +#define FXIO0_D10_PTE22 KINETIS_MUX('E',22,7) /* PTE_22 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define I2C2_SCL_PTE23 KINETIS_MUX('E',23,2) /* PTE_23 */ +#define LPUART4_RTS_b_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define SPI3_SIN_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define I2S1_RX_BCLK_PTE23 KINETIS_MUX('E',23,5) /* PTE_23 */ +#define FXIO0_D11_PTE23 KINETIS_MUX('E',23,7) /* PTE_23 */ +#endif diff --git a/dts/nxp/kinetis/MK28FN2M0VMI15-pinctrl.h b/dts/nxp/kinetis/MK28FN2M0VMI15-pinctrl.h new file mode 100644 index 000000000..b7563464c --- /dev/null +++ b/dts/nxp/kinetis/MK28FN2M0VMI15-pinctrl.h @@ -0,0 +1,716 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK28FN2M0VMI15/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK28FN2M0VMI15_ +#define _ZEPHYR_DTS_BINDING_MK28FN2M0VMI15_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FXIO0_D11_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FXIO0_D12_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FXIO0_D13_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FXIO0_D14_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define FXIO0_D15_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define I2C2_SCL_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define I2C2_SDA_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define I2C1_SCL_PTA8 KINETIS_MUX('A',8,2) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define I2C1_SDA_PTA9 KINETIS_MUX('A',9,2) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define I2C2_SDA_PTA10 KINETIS_MUX('A',10,2) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO0_D16_PTA10 KINETIS_MUX('A',10,5) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define I2C2_SCL_PTA11 KINETIS_MUX('A',11,2) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO0_D17_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define USB1_ID_PTA11 KINETIS_MUX('A',11,7) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define TRACE_CLKOUT_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define FXIO0_D18_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define TRACE_D3_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define FXIO0_D19_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define TRACE_D2_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define FXIO0_D20_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define TRACE_D1_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define FXIO0_D21_PTA15 KINETIS_MUX('A',15,5) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define TRACE_D0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define FXIO0_D22_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define FXIO0_D23_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define I2S1_MCLK_PTA17 KINETIS_MUX('A',17,7) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define I2C0_SCL_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART4_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define FTM_CLKIN1_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define FXIO0_D8_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define EWM_OUT_b_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define TPM_CLKIN1_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LLWU_P21_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define I2C0_SDA_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART4_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define FXIO0_D9_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define EWM_IN_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define PTA22 KINETIS_MUX('A',22,1) /* PTA_22 */ +#define LPUART4_CTS_b_PTA22 KINETIS_MUX('A',22,3) /* PTA_22 */ +#define FXIO0_D6_PTA22 KINETIS_MUX('A',22,5) /* PTA_22 */ +#define RTC_CLKOUT_PTA22 KINETIS_MUX('A',22,6) /* PTA_22 */ +#define USB0_CLKIN_PTA22 KINETIS_MUX('A',22,7) /* PTA_22 */ +#define PTA23 KINETIS_MUX('A',23,1) /* PTA_23 */ +#define LPUART4_RTS_b_PTA23 KINETIS_MUX('A',23,3) /* PTA_23 */ +#define FXIO0_D7_PTA23 KINETIS_MUX('A',23,5) /* PTA_23 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define LPUART2_TX_PTA24 KINETIS_MUX('A',24,3) /* PTA_24 */ +#define SDHC0_D1_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define I2S1_TX_BCLK_PTA24 KINETIS_MUX('A',24,7) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define LPUART2_RX_PTA25 KINETIS_MUX('A',25,3) /* PTA_25 */ +#define SDHC0_D0_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define I2S1_TX_FS_PTA25 KINETIS_MUX('A',25,7) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define LPUART2_CTS_b_PTA26 KINETIS_MUX('A',26,3) /* PTA_26 */ +#define SDHC0_DCLK_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define I2S1_TXD0_PTA26 KINETIS_MUX('A',26,7) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define LPUART2_RTS_b_PTA27 KINETIS_MUX('A',27,3) /* PTA_27 */ +#define SDHC0_CMD_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define I2S1_TXD1_PTA27 KINETIS_MUX('A',27,7) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define LPUART3_TX_PTA28 KINETIS_MUX('A',28,3) /* PTA_28 */ +#define SDHC0_D3_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define I2S1_RXD1_PTA28 KINETIS_MUX('A',28,7) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define LPUART3_RX_PTA29 KINETIS_MUX('A',29,3) /* PTA_29 */ +#define SDHC0_D2_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define I2S1_RXD0_PTA29 KINETIS_MUX('A',29,7) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define I2C3_SDA_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define LPUART3_CTS_b_PTA30 KINETIS_MUX('A',30,3) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define I2S1_RX_FS_PTA30 KINETIS_MUX('A',30,7) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define I2C3_SCL_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define LPUART3_RTS_b_PTA31 KINETIS_MUX('A',31,3) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define I2S1_RX_BCLK_PTA31 KINETIS_MUX('A',31,7) /* PTA_31 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FXIO0_D0_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FXIO0_D1_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_b_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define FXIO0_D2_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define FXIO0_D3_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPUART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define I2C2_SCL_PTB10 KINETIS_MUX('B',10,4) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define FXIO0_D4_PTB10 KINETIS_MUX('B',10,7) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define I2C2_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define FXIO0_D5_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define LPUART0_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define LPUART0_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define LPUART0_RX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define LPUART0_TX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FXIO0_D6_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define SDRAM_CKE_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D7_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D8_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D9_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define FXIO0_D10_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define FXIO0_D11_PTB23 KINETIS_MUX('B',23,7) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define FXIO0_D12_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define FXIO0_D13_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define FXIO0_D14_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define FXIO0_D15_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define FXIO0_D16_PTC8 KINETIS_MUX('C',8,7) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define FXIO0_D17_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define FXIO0_D18_PTC10 KINETIS_MUX('C',10,7) /* PTC_10 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define FXIO0_D19_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPUART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPUART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define LPUART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define FXIO0_D20_PTC14 KINETIS_MUX('C',14,7) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define LPUART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define FXIO0_D21_PTC15 KINETIS_MUX('C',15,7) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define LPUART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define QSPI0A_SS1_B_PTC19 KINETIS_MUX('C',19,7) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define QSPI0A_DATA3_PTC24 KINETIS_MUX('C',24,7) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define QSPI0A_SCLK_PTC25 KINETIS_MUX('C',25,7) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define QSPI0A_DATA0_PTC26 KINETIS_MUX('C',26,7) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define QSPI0A_DATA2_PTC27 KINETIS_MUX('C',27,7) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define QSPI0A_DATA1_PTC28 KINETIS_MUX('C',28,7) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define QSPI0A_SS0_B_PTC29 KINETIS_MUX('C',29,7) /* PTC_29 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D22_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D23_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART1_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define FXIO0_D24_PTD8 KINETIS_MUX('D',8,7) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART1_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define FXIO0_D25_PTD9 KINETIS_MUX('D',9,7) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART1_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define FXIO0_D26_PTD10 KINETIS_MUX('D',10,7) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART1_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define FXIO0_D27_PTD11 KINETIS_MUX('D',11,7) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define FXIO0_D28_PTD12 KINETIS_MUX('D',12,7) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define FXIO0_D29_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define FXIO0_D30_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define FXIO0_D31_PTD15 KINETIS_MUX('D',15,7) /* PTD_15 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define QSPI0A_DATA3_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SCK_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define QSPI0A_SCLK_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define QSPI0A_DATA0_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define FXIO0_D0_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,7) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_PCS2_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define QSPI0A_DATA2_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define FXIO0_D1_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_SIN_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define QSPI0A_DATA1_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS0_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define QSPI0A_SS0_B_PTE5 KINETIS_MUX('E',5,5) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define USB0_SOF_OUT_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define FXIO0_D12_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define QSPI0B_DATA3_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define SDHC0_D4_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FXIO0_D13_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define LPUART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define QSPI0B_SCLK_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define QSPI0A_SS1_B_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define FXIO0_D14_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define QSPI0B_DATA0_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define FXIO0_D15_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define QSPI0B_DATA2_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define SDHC0_D6_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO0_D16_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define QSPI0B_DATA1_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define SDHC0_D7_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define FXIO0_D17_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define QSPI0B_SS0_B_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define QSPI0A_DQS_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define QSPI0B_DQS_PTE12 KINETIS_MUX('E',12,5) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define FXIO0_D2_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define LPUART2_RX_PTE13 KINETIS_MUX('E',13,3) /* PTE_13 */ +#define I2S1_MCLK_PTE13 KINETIS_MUX('E',13,4) /* PTE_13 */ +#define QSPI0B_SS1_B_PTE13 KINETIS_MUX('E',13,5) /* PTE_13 */ +#define SDHC0_CLKIN_PTE13 KINETIS_MUX('E',13,6) /* PTE_13 */ +#define FXIO0_D3_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define LPUART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define I2S1_TX_BCLK_PTE16 KINETIS_MUX('E',16,5) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define FXIO0_D4_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define LPUART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define I2S1_TX_FS_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define FXIO0_D5_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define LPUART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define I2S1_TXD0_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D6_PTE18 KINETIS_MUX('E',18,7) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define LPUART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define I2S1_TXD1_PTE19 KINETIS_MUX('E',19,5) /* PTE_19 */ +#define FXIO0_D7_PTE19 KINETIS_MUX('E',19,7) /* PTE_19 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define LPUART4_TX_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define SPI3_PCS0_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define I2S1_RXD1_PTE20 KINETIS_MUX('E',20,5) /* PTE_20 */ +#define FXIO0_D8_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define LPUART4_RX_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define SPI3_SCK_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define I2S1_RXD0_PTE21 KINETIS_MUX('E',21,5) /* PTE_21 */ +#define FXIO0_D9_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define I2C2_SDA_PTE22 KINETIS_MUX('E',22,2) /* PTE_22 */ +#define LPUART4_CTS_b_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define SPI3_SOUT_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define I2S1_RX_FS_PTE22 KINETIS_MUX('E',22,5) /* PTE_22 */ +#define FXIO0_D10_PTE22 KINETIS_MUX('E',22,7) /* PTE_22 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define I2C2_SCL_PTE23 KINETIS_MUX('E',23,2) /* PTE_23 */ +#define LPUART4_RTS_b_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define SPI3_SIN_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define I2S1_RX_BCLK_PTE23 KINETIS_MUX('E',23,5) /* PTE_23 */ +#define FXIO0_D11_PTE23 KINETIS_MUX('E',23,7) /* PTE_23 */ +#endif diff --git a/dts/nxp/kinetis/MK63FN1M0VLQ12-pinctrl.h b/dts/nxp/kinetis/MK63FN1M0VLQ12-pinctrl.h new file mode 100644 index 000000000..0c8314e38 --- /dev/null +++ b/dts/nxp/kinetis/MK63FN1M0VLQ12-pinctrl.h @@ -0,0 +1,497 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK63FN1M0VLQ12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK63FN1M0VLQ12_ +#define _ZEPHYR_DTS_BINDING_MK63FN1M0VLQ12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define MII0_RXD3_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define UART0_COL_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define MII0_TXD2_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define MII0_TXCLK_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define MII0_TXD3_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define MII0_CRS_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define MII0_TXER_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define UART0_COL_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define ENET0_1588_TMR2_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define ENET0_1588_TMR3_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_COL_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define UART5_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define UART5_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define UART5_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define UART5_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_DP2_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC0_DM2_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define UART5_TX_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define UART5_RX_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define UART5_CTS_b_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define UART5_RTS_b_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK63FN1M0VMD12-pinctrl.h b/dts/nxp/kinetis/MK63FN1M0VMD12-pinctrl.h new file mode 100644 index 000000000..e8183cb05 --- /dev/null +++ b/dts/nxp/kinetis/MK63FN1M0VMD12-pinctrl.h @@ -0,0 +1,479 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK63FN1M0VMD12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK63FN1M0VMD12_ +#define _ZEPHYR_DTS_BINDING_MK63FN1M0VMD12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define MII0_RXD3_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define UART0_COL_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define MII0_TXD2_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define MII0_TXCLK_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define MII0_TXD3_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define MII0_CRS_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define MII0_TXER_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define UART0_COL_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define ENET0_1588_TMR2_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define ENET0_1588_TMR3_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_COL_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define UART5_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define UART5_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define UART5_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define UART5_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_DP2_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC0_DM2_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define UART5_TX_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define UART5_RX_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define UART5_CTS_b_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define UART5_RTS_b_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#endif diff --git a/dts/nxp/kinetis/MK64FX512VDC12-pinctrl.h b/dts/nxp/kinetis/MK64FX512VDC12-pinctrl.h new file mode 100644 index 000000000..a970d8eb3 --- /dev/null +++ b/dts/nxp/kinetis/MK64FX512VDC12-pinctrl.h @@ -0,0 +1,443 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK64FX512VDC12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK64FX512VDC12_ +#define _ZEPHYR_DTS_BINDING_MK64FX512VDC12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define UART0_COL_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define UART0_COL_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define UART3_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define UART3_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_COL_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define UART5_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define UART5_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define UART5_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define UART5_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define ADC0_DP2_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC0_DM2_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#endif diff --git a/dts/nxp/kinetis/MK64FX512VLL12-pinctrl.h b/dts/nxp/kinetis/MK64FX512VLL12-pinctrl.h new file mode 100644 index 000000000..6581f1537 --- /dev/null +++ b/dts/nxp/kinetis/MK64FX512VLL12-pinctrl.h @@ -0,0 +1,387 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK64FX512VLL12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK64FX512VLL12_ +#define _ZEPHYR_DTS_BINDING_MK64FX512VLL12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define UART0_COL_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define UART0_COL_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_COL_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define ADC0_DP2_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC0_DM2_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#endif diff --git a/dts/nxp/kinetis/MK64FX512VLQ12-pinctrl.h b/dts/nxp/kinetis/MK64FX512VLQ12-pinctrl.h new file mode 100644 index 000000000..00602d1af --- /dev/null +++ b/dts/nxp/kinetis/MK64FX512VLQ12-pinctrl.h @@ -0,0 +1,497 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK64FX512VLQ12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK64FX512VLQ12_ +#define _ZEPHYR_DTS_BINDING_MK64FX512VLQ12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define MII0_RXD3_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define UART0_COL_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define MII0_TXD2_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define MII0_TXCLK_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define MII0_TXD3_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define MII0_CRS_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define MII0_TXER_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define UART0_COL_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define ENET0_1588_TMR2_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define ENET0_1588_TMR3_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_COL_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define UART5_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define UART5_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define UART5_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define UART5_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define ADC0_DP2_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC0_DM2_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define UART5_TX_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define UART5_RX_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define UART5_CTS_b_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define UART5_RTS_b_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK64FX512VMD12-pinctrl.h b/dts/nxp/kinetis/MK64FX512VMD12-pinctrl.h new file mode 100644 index 000000000..cf083f027 --- /dev/null +++ b/dts/nxp/kinetis/MK64FX512VMD12-pinctrl.h @@ -0,0 +1,497 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK64FX512VMD12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK64FX512VMD12_ +#define _ZEPHYR_DTS_BINDING_MK64FX512VMD12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_COL_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define MII0_RXD3_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define UART0_COL_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define MII0_TXD2_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define MII0_TXCLK_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define MII0_TXD3_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define MII0_CRS_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define MII0_TXER_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define UART0_COL_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define ENET0_1588_TMR2_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define ENET0_1588_TMR3_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_COL_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define UART5_RX_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define UART5_TX_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define UART5_RTS_b_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define UART5_CTS_b_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define ADC0_DP2_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC0_DM2_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define UART5_TX_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define UART5_RX_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define UART5_CTS_b_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define UART5_RTS_b_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK65FN2M0CAC18-pinctrl.h b/dts/nxp/kinetis/MK65FN2M0CAC18-pinctrl.h new file mode 100644 index 000000000..b2fac3fc2 --- /dev/null +++ b/dts/nxp/kinetis/MK65FN2M0CAC18-pinctrl.h @@ -0,0 +1,675 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK65FN2M0CAC18/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK65FN2M0CAC18_ +#define _ZEPHYR_DTS_BINDING_MK65FN2M0CAC18_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RMII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define MII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define MII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define RMII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define MII0_RXD3_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define CMP3_IN1_PTA15 KINETIS_MUX('A',15,0) /* PTA_15 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define CMP3_IN2_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define CMP3_IN4_PTA24 KINETIS_MUX('A',24,0) /* PTA_24 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define MII0_TXD2_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define CMP3_IN5_PTA25 KINETIS_MUX('A',25,0) /* PTA_25 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define MII0_TXCLK_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define MII0_TXD3_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define MII0_CRS_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define MII0_TXER_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define CAN0_TX_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define CAN0_RX_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define ENET0_1588_TMR2_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define ENET0_1588_TMR3_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define UART3_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define UART3_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define CAN1_TX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define CAN1_RX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define CMP3_OUT_PTB23 KINETIS_MUX('B',23,6) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define CAN1_RX_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define CAN1_TX_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define ENET0_1588_TMR0_PTC26 KINETIS_MUX('C',26,4) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define ENET0_1588_TMR1_PTC27 KINETIS_MUX('C',27,4) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define ENET0_1588_TMR2_PTC28 KINETIS_MUX('C',28,4) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define ENET0_1588_TMR3_PTC29 KINETIS_MUX('C',29,4) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART0_RX_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART0_TX_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART0_RTS_b_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define LPUART0_CTS_b_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB0_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define LPUART0_TX_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define LPUART0_RX_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define LPUART0_CTS_b_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define USB1_ID_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define LPUART0_RTS_b_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define CMP3_OUT_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define CAN1_TX_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define CAN1_RX_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB0_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK65FN2M0VMI18-pinctrl.h b/dts/nxp/kinetis/MK65FN2M0VMI18-pinctrl.h new file mode 100644 index 000000000..4de14b9fe --- /dev/null +++ b/dts/nxp/kinetis/MK65FN2M0VMI18-pinctrl.h @@ -0,0 +1,675 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK65FN2M0VMI18/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK65FN2M0VMI18_ +#define _ZEPHYR_DTS_BINDING_MK65FN2M0VMI18_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RMII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define MII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define MII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define RMII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define MII0_RXD3_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define CMP3_IN1_PTA15 KINETIS_MUX('A',15,0) /* PTA_15 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define CMP3_IN2_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define CMP3_IN4_PTA24 KINETIS_MUX('A',24,0) /* PTA_24 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define MII0_TXD2_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define CMP3_IN5_PTA25 KINETIS_MUX('A',25,0) /* PTA_25 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define MII0_TXCLK_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define MII0_TXD3_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define MII0_CRS_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define MII0_TXER_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define CAN0_TX_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define CAN0_RX_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define ENET0_1588_TMR2_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define ENET0_1588_TMR3_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define UART3_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define UART3_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define CAN1_TX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define CAN1_RX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define CMP3_OUT_PTB23 KINETIS_MUX('B',23,6) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define CAN1_RX_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define CAN1_TX_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define ENET0_1588_TMR0_PTC26 KINETIS_MUX('C',26,4) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define ENET0_1588_TMR1_PTC27 KINETIS_MUX('C',27,4) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define ENET0_1588_TMR2_PTC28 KINETIS_MUX('C',28,4) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define ENET0_1588_TMR3_PTC29 KINETIS_MUX('C',29,4) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART0_RX_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART0_TX_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART0_RTS_b_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define LPUART0_CTS_b_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB0_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define LPUART0_TX_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define LPUART0_RX_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define LPUART0_CTS_b_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define USB1_ID_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define LPUART0_RTS_b_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define CMP3_OUT_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define CAN1_TX_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define CAN1_RX_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB0_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK65FX1M0CAC18-pinctrl.h b/dts/nxp/kinetis/MK65FX1M0CAC18-pinctrl.h new file mode 100644 index 000000000..9b022ed2d --- /dev/null +++ b/dts/nxp/kinetis/MK65FX1M0CAC18-pinctrl.h @@ -0,0 +1,675 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK65FX1M0CAC18/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK65FX1M0CAC18_ +#define _ZEPHYR_DTS_BINDING_MK65FX1M0CAC18_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RMII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define MII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define MII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define RMII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define MII0_RXD3_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define CMP3_IN1_PTA15 KINETIS_MUX('A',15,0) /* PTA_15 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define CMP3_IN2_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define CMP3_IN4_PTA24 KINETIS_MUX('A',24,0) /* PTA_24 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define MII0_TXD2_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define CMP3_IN5_PTA25 KINETIS_MUX('A',25,0) /* PTA_25 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define MII0_TXCLK_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define MII0_TXD3_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define MII0_CRS_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define MII0_TXER_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define CAN0_TX_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define CAN0_RX_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define ENET0_1588_TMR2_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define ENET0_1588_TMR3_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define UART3_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define UART3_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define CAN1_TX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define CAN1_RX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define CMP3_OUT_PTB23 KINETIS_MUX('B',23,6) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define CAN1_RX_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define CAN1_TX_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define ENET0_1588_TMR0_PTC26 KINETIS_MUX('C',26,4) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define ENET0_1588_TMR1_PTC27 KINETIS_MUX('C',27,4) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define ENET0_1588_TMR2_PTC28 KINETIS_MUX('C',28,4) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define ENET0_1588_TMR3_PTC29 KINETIS_MUX('C',29,4) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART0_RX_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART0_TX_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART0_RTS_b_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define LPUART0_CTS_b_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB0_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define LPUART0_TX_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define LPUART0_RX_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define LPUART0_CTS_b_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define USB1_ID_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define LPUART0_RTS_b_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define CMP3_OUT_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define CAN1_TX_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define CAN1_RX_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB0_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK65FX1M0VMI18-pinctrl.h b/dts/nxp/kinetis/MK65FX1M0VMI18-pinctrl.h new file mode 100644 index 000000000..53f95b0fb --- /dev/null +++ b/dts/nxp/kinetis/MK65FX1M0VMI18-pinctrl.h @@ -0,0 +1,675 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK65FX1M0VMI18/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK65FX1M0VMI18_ +#define _ZEPHYR_DTS_BINDING_MK65FX1M0VMI18_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RMII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define MII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define MII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define RMII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define MII0_RXD3_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define CMP3_IN1_PTA15 KINETIS_MUX('A',15,0) /* PTA_15 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define CMP3_IN2_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define CMP3_IN4_PTA24 KINETIS_MUX('A',24,0) /* PTA_24 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define MII0_TXD2_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define SDRAM_D15_PTA24 KINETIS_MUX('A',24,5) /* PTA_24 */ +#define CMP3_IN5_PTA25 KINETIS_MUX('A',25,0) /* PTA_25 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define MII0_TXCLK_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define SDRAM_D14_PTA25 KINETIS_MUX('A',25,5) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define MII0_TXD3_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define SDRAM_D13_PTA26 KINETIS_MUX('A',26,5) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define MII0_CRS_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define SDRAM_D12_PTA27 KINETIS_MUX('A',27,5) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define MII0_TXER_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define PTA30 KINETIS_MUX('A',30,1) /* PTA_30 */ +#define CAN0_TX_PTA30 KINETIS_MUX('A',30,2) /* PTA_30 */ +#define SDRAM_D11_PTA30 KINETIS_MUX('A',30,5) /* PTA_30 */ +#define PTA31 KINETIS_MUX('A',31,1) /* PTA_31 */ +#define CAN0_RX_PTA31 KINETIS_MUX('A',31,2) /* PTA_31 */ +#define SDRAM_D10_PTA31 KINETIS_MUX('A',31,5) /* PTA_31 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define ENET0_1588_TMR2_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define ENET0_1588_TMR3_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define UART3_RTS_b_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define FTM1_CH0_PTB12 KINETIS_MUX('B',12,3) /* PTB_12 */ +#define FTM0_CH4_PTB12 KINETIS_MUX('B',12,4) /* PTB_12 */ +#define SDRAM_D9_PTB12 KINETIS_MUX('B',12,5) /* PTB_12 */ +#define FTM1_QD_PHA_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define TPM1_CH0_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define UART3_CTS_b_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define FTM1_CH1_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#define FTM0_CH5_PTB13 KINETIS_MUX('B',13,4) /* PTB_13 */ +#define SDRAM_D8_PTB13 KINETIS_MUX('B',13,5) /* PTB_13 */ +#define FTM1_QD_PHB_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define CAN1_TX_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define SDRAM_D7_PTB14 KINETIS_MUX('B',14,5) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define CAN1_RX_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define SDRAM_D6_PTB15 KINETIS_MUX('B',15,5) /* PTB_15 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define CMP3_OUT_PTB23 KINETIS_MUX('B',23,6) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define CAN1_RX_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define CAN1_TX_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTC24 KINETIS_MUX('C',24,1) /* PTC_24 */ +#define LPUART0_TX_PTC24 KINETIS_MUX('C',24,3) /* PTC_24 */ +#define SDRAM_D5_PTC24 KINETIS_MUX('C',24,5) /* PTC_24 */ +#define PTC25 KINETIS_MUX('C',25,1) /* PTC_25 */ +#define LPUART0_RX_PTC25 KINETIS_MUX('C',25,3) /* PTC_25 */ +#define SDRAM_D4_PTC25 KINETIS_MUX('C',25,5) /* PTC_25 */ +#define PTC26 KINETIS_MUX('C',26,1) /* PTC_26 */ +#define LPUART0_CTS_b_PTC26 KINETIS_MUX('C',26,3) /* PTC_26 */ +#define ENET0_1588_TMR0_PTC26 KINETIS_MUX('C',26,4) /* PTC_26 */ +#define SDRAM_D3_PTC26 KINETIS_MUX('C',26,5) /* PTC_26 */ +#define PTC27 KINETIS_MUX('C',27,1) /* PTC_27 */ +#define LPUART0_RTS_b_PTC27 KINETIS_MUX('C',27,3) /* PTC_27 */ +#define ENET0_1588_TMR1_PTC27 KINETIS_MUX('C',27,4) /* PTC_27 */ +#define SDRAM_D2_PTC27 KINETIS_MUX('C',27,5) /* PTC_27 */ +#define PTC28 KINETIS_MUX('C',28,1) /* PTC_28 */ +#define I2C3_SDA_PTC28 KINETIS_MUX('C',28,2) /* PTC_28 */ +#define ENET0_1588_TMR2_PTC28 KINETIS_MUX('C',28,4) /* PTC_28 */ +#define SDRAM_D1_PTC28 KINETIS_MUX('C',28,5) /* PTC_28 */ +#define PTC29 KINETIS_MUX('C',29,1) /* PTC_29 */ +#define I2C3_SCL_PTC29 KINETIS_MUX('C',29,2) /* PTC_29 */ +#define ENET0_1588_TMR3_PTC29 KINETIS_MUX('C',29,4) /* PTC_29 */ +#define SDRAM_D0_PTC29 KINETIS_MUX('C',29,5) /* PTC_29 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART0_RX_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART0_TX_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART0_RTS_b_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define LPUART0_CTS_b_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB0_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define LPUART0_TX_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define LPUART0_RX_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define LPUART0_CTS_b_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define USB1_ID_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define LPUART0_RTS_b_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define CMP3_OUT_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define CAN1_TX_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define CAN1_RX_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB0_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK66FX1M0VLQ18-pinctrl.h b/dts/nxp/kinetis/MK66FX1M0VLQ18-pinctrl.h new file mode 100644 index 000000000..4fdf27f7f --- /dev/null +++ b/dts/nxp/kinetis/MK66FX1M0VLQ18-pinctrl.h @@ -0,0 +1,596 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK66FX1M0VLQ18/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK66FX1M0VLQ18_ +#define _ZEPHYR_DTS_BINDING_MK66FX1M0VLQ18_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RMII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define MII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define RMII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define MII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define MII0_RXD3_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define CMP3_IN1_PTA15 KINETIS_MUX('A',15,0) /* PTA_15 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define CMP3_IN2_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define CMP3_IN4_PTA24 KINETIS_MUX('A',24,0) /* PTA_24 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define MII0_TXD2_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define CMP3_IN5_PTA25 KINETIS_MUX('A',25,0) /* PTA_25 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define MII0_TXCLK_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define MII0_TXD3_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define MII0_CRS_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define MII0_TXER_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define ENET0_1588_TMR2_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define ENET0_1588_TMR3_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define CMP3_OUT_PTB23 KINETIS_MUX('B',23,6) /* PTB_23 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define CAN1_RX_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define CAN1_TX_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART0_RX_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART0_TX_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART0_RTS_b_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define LPUART0_CTS_b_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB0_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define LPUART0_TX_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define LPUART0_RX_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define LPUART0_CTS_b_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define USB1_ID_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define LPUART0_RTS_b_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define CAN1_TX_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define CAN1_RX_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB0_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK66FX1M0VMD18-pinctrl.h b/dts/nxp/kinetis/MK66FX1M0VMD18-pinctrl.h new file mode 100644 index 000000000..effd9de51 --- /dev/null +++ b/dts/nxp/kinetis/MK66FX1M0VMD18-pinctrl.h @@ -0,0 +1,596 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK66FX1M0VMD18/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK66FX1M0VMD18_ +#define _ZEPHYR_DTS_BINDING_MK66FX1M0VMD18_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define MII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define RMII0_RXER_PTA5 KINETIS_MUX('A',5,4) /* PTA_5 */ +#define CMP2_OUT_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RMII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define MII0_MDIO_PTA7 KINETIS_MUX('A',7,5) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define RMII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define MII0_MDC_PTA8 KINETIS_MUX('A',8,5) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define MII0_RXD3_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define MII0_RXD2_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define MII0_RXCLK_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define I2C2_SDA_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define CMP2_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define CAN0_TX_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define MII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define RMII0_RXD1_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define I2C2_SCL_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define CMP2_IN1_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define CAN0_RX_PTA13 KINETIS_MUX('A',13,2) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define MII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define RMII0_RXD0_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define I2C2_SDA_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define MII0_RXDV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define RMII0_CRS_DV_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define I2C2_SCL_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define CMP3_IN1_PTA15 KINETIS_MUX('A',15,0) /* PTA_15 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define RMII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define MII0_TXEN_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define CMP3_IN2_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define MII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define RMII0_TXD0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define RMII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define MII0_TXD1_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define CMP3_IN4_PTA24 KINETIS_MUX('A',24,0) /* PTA_24 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define MII0_TXD2_PTA24 KINETIS_MUX('A',24,4) /* PTA_24 */ +#define CMP3_IN5_PTA25 KINETIS_MUX('A',25,0) /* PTA_25 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define MII0_TXCLK_PTA25 KINETIS_MUX('A',25,4) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define MII0_TXD3_PTA26 KINETIS_MUX('A',26,4) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define MII0_CRS_PTA27 KINETIS_MUX('A',27,4) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define MII0_TXER_PTA28 KINETIS_MUX('A',28,4) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define MII0_COL_PTA29 KINETIS_MUX('A',29,4) /* PTA_29 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define RMII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define MII0_MDIO_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define RMII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define MII0_MDC_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ENET0_1588_TMR0_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define ENET0_1588_TMR1_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC1_SE10_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define ENET0_1588_TMR2_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC1_SE11_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define ENET0_1588_TMR3_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ADC1_SE12_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define ADC1_SE13_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define UART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define UART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define UART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define UART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define CAN0_TX_PTB18 KINETIS_MUX('B',18,2) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define CAN0_RX_PTB19 KINETIS_MUX('B',19,2) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define CMP2_OUT_PTB22 KINETIS_MUX('B',22,6) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define CMP3_OUT_PTB23 KINETIS_MUX('B',23,6) /* PTB_23 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define UART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define UART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define UART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define UART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define CAN1_RX_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define UART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define ENET0_1588_TMR0_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define CAN1_TX_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define UART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define ENET0_1588_TMR1_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define UART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define ENET0_1588_TMR2_PTC18 KINETIS_MUX('C',18,4) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define UART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define ENET0_1588_TMR3_PTC19 KINETIS_MUX('C',19,4) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPUART0_RX_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define LPUART0_TX_PTD9 KINETIS_MUX('D',9,5) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define LPUART0_RTS_b_PTD10 KINETIS_MUX('D',10,5) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define SDHC0_CLKIN_PTD11 KINETIS_MUX('D',11,4) /* PTD_11 */ +#define LPUART0_CTS_b_PTD11 KINETIS_MUX('D',11,5) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define SDHC0_D4_PTD12 KINETIS_MUX('D',12,4) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define SDHC0_D5_PTD13 KINETIS_MUX('D',13,4) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define SDHC0_D6_PTD14 KINETIS_MUX('D',14,4) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define SDHC0_D7_PTD15 KINETIS_MUX('D',15,4) /* PTD_15 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TRACE_CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TRACE_D3_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define TRACE_D2_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define TRACE_D1_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define TRACE_D0_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define UART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define USB0_SOF_OUT_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define UART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define LPUART0_TX_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define LPUART0_RX_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define LPUART0_CTS_b_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define USB1_ID_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define LPUART0_RTS_b_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define CAN1_TX_PTE24 KINETIS_MUX('E',24,2) /* PTE_24 */ +#define UART4_TX_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define LLWU_P21_PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define CAN1_RX_PTE25 KINETIS_MUX('E',25,2) /* PTE_25 */ +#define UART4_RX_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define ENET_1588_CLKIN_PTE26 KINETIS_MUX('E',26,2) /* PTE_26 */ +#define UART4_CTS_b_PTE26 KINETIS_MUX('E',26,3) /* PTE_26 */ +#define RTC_CLKOUT_PTE26 KINETIS_MUX('E',26,6) /* PTE_26 */ +#define USB0_CLKIN_PTE26 KINETIS_MUX('E',26,7) /* PTE_26 */ +#define PTE27 KINETIS_MUX('E',27,1) /* PTE_27 */ +#define UART4_RTS_b_PTE27 KINETIS_MUX('E',27,3) /* PTE_27 */ +#define PTE28 KINETIS_MUX('E',28,1) /* PTE_28 */ +#endif diff --git a/dts/nxp/kinetis/MK80FN256CAX15-pinctrl.h b/dts/nxp/kinetis/MK80FN256CAX15-pinctrl.h new file mode 100644 index 000000000..0b0b2cbc7 --- /dev/null +++ b/dts/nxp/kinetis/MK80FN256CAX15-pinctrl.h @@ -0,0 +1,555 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK80FN256CAx15/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK80FN256CAX15_ +#define _ZEPHYR_DTS_BINDING_MK80FN256CAX15_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define EMVSIM0_CLK_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FXIO0_D11_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define EMVSIM0_IO_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FXIO0_D12_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define EMVSIM0_PD_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FXIO0_D13_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define EMVSIM0_RST_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FXIO0_D14_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define EMVSIM0_VCCEN_PTA4 KINETIS_MUX('A',4,6) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define FXIO0_D15_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define I2C2_SDA_PTA10 KINETIS_MUX('A',10,2) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define EMVSIM1_VCCEN_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define FXIO0_D16_PTA10 KINETIS_MUX('A',10,5) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define I2C2_SCL_PTA11 KINETIS_MUX('A',11,2) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO0_D17_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define TRACE_CLKOUT_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define FXIO0_D18_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define TRACE_D3_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define FXIO0_D19_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define TRACE_D2_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define FXIO0_D20_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define TRACE_D1_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define FXIO0_D21_PTA15 KINETIS_MUX('A',15,5) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define TRACE_D0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define FXIO0_D22_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define FXIO0_D23_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define I2C0_SCL_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART4_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define FTM_CLKIN1_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define FXIO0_D8_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define EWM_OUT_b_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define TPM_CLKIN1_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LLWU_P21_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define I2C0_SDA_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART4_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define FXIO0_D9_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define EWM_IN_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FXIO0_D0_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FXIO0_D1_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define FXIO0_D2_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define FXIO0_D3_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define EMVSIM1_IO_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define EMVSIM1_CLK_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define EMVSIM1_VCCEN_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define EMVSIM1_PD_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define EMVSIM1_RST_PTB8 KINETIS_MUX('B',8,2) /* PTB_8 */ +#define LPUART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define I2C2_SCL_PTB10 KINETIS_MUX('B',10,4) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define FXIO0_D4_PTB10 KINETIS_MUX('B',10,7) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define I2C2_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define FXIO0_D5_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FXIO0_D6_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D7_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D8_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D9_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define FXIO0_D10_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define FXIO0_D11_PTB23 KINETIS_MUX('B',23,7) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define FXIO0_D12_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define FXIO0_D13_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define FXIO0_D14_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define FXIO0_D15_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define FXIO0_D16_PTC8 KINETIS_MUX('C',8,7) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define FXIO0_D17_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define FXIO0_D18_PTC10 KINETIS_MUX('C',10,7) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define FXIO0_D19_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPUART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPUART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define LPUART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define FXIO0_D20_PTC14 KINETIS_MUX('C',14,7) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define LPUART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define FXIO0_D21_PTC15 KINETIS_MUX('C',15,7) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define LPUART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D22_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D23_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define FXIO0_D24_PTD8 KINETIS_MUX('D',8,7) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define FXIO0_D25_PTD9 KINETIS_MUX('D',9,7) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FXIO0_D26_PTD10 KINETIS_MUX('D',10,7) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define FXIO0_D27_PTD11 KINETIS_MUX('D',11,7) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define FXIO0_D28_PTD12 KINETIS_MUX('D',12,7) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define FXIO0_D29_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define FXIO0_D30_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define FXIO0_D31_PTD15 KINETIS_MUX('D',15,7) /* PTD_15 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define QSPI0A_DATA3_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SCK_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define QSPI0A_SCLK_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define QSPI0A_DATA0_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,7) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_PCS2_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define QSPI0A_DATA2_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_SIN_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define QSPI0A_DATA1_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS0_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define QSPI0A_SS0_B_PTE5 KINETIS_MUX('E',5,5) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define USB0_SOF_OUT_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define QSPI0B_DATA3_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define SDHC0_D4_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define SPI2_SCK_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define LPUART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define QSPI0B_SCLK_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define QSPI0A_SS1_B_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define SPI2_SOUT_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define QSPI0B_DATA0_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define SPI2_PCS1_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define QSPI0B_DATA2_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define SDHC0_D6_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define SPI2_SIN_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define QSPI0B_DATA1_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define SDHC0_D7_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define SPI2_PCS0_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define QSPI0B_SS0_B_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define QSPI0A_DQS_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MK80FN256VDC15-pinctrl.h b/dts/nxp/kinetis/MK80FN256VDC15-pinctrl.h new file mode 100644 index 000000000..28a5f26f1 --- /dev/null +++ b/dts/nxp/kinetis/MK80FN256VDC15-pinctrl.h @@ -0,0 +1,555 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK80FN256VDC15/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK80FN256VDC15_ +#define _ZEPHYR_DTS_BINDING_MK80FN256VDC15_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define EMVSIM0_CLK_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FXIO0_D11_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define EMVSIM0_IO_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FXIO0_D12_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define EMVSIM0_PD_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FXIO0_D13_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define EMVSIM0_RST_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FXIO0_D14_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define EMVSIM0_VCCEN_PTA4 KINETIS_MUX('A',4,6) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define FXIO0_D15_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define I2C2_SDA_PTA10 KINETIS_MUX('A',10,2) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define EMVSIM1_VCCEN_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define FXIO0_D16_PTA10 KINETIS_MUX('A',10,5) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define I2C2_SCL_PTA11 KINETIS_MUX('A',11,2) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO0_D17_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define TRACE_CLKOUT_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define FXIO0_D18_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define TRACE_D3_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define FXIO0_D19_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define TRACE_D2_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define FXIO0_D20_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define TRACE_D1_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define FXIO0_D21_PTA15 KINETIS_MUX('A',15,5) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define TRACE_D0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define FXIO0_D22_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define FXIO0_D23_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define I2C0_SCL_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART4_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define FTM_CLKIN1_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define FXIO0_D8_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define EWM_OUT_b_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define TPM_CLKIN1_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LLWU_P21_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define I2C0_SDA_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART4_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define FXIO0_D9_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define EWM_IN_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FXIO0_D0_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FXIO0_D1_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define FXIO0_D2_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define FXIO0_D3_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define EMVSIM1_IO_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define EMVSIM1_CLK_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define EMVSIM1_VCCEN_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define EMVSIM1_PD_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define EMVSIM1_RST_PTB8 KINETIS_MUX('B',8,2) /* PTB_8 */ +#define LPUART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define I2C2_SCL_PTB10 KINETIS_MUX('B',10,4) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define FXIO0_D4_PTB10 KINETIS_MUX('B',10,7) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define I2C2_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define FXIO0_D5_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FXIO0_D6_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D7_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D8_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D9_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define FXIO0_D10_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define FXIO0_D11_PTB23 KINETIS_MUX('B',23,7) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define FXIO0_D12_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define FXIO0_D13_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define FXIO0_D14_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define FXIO0_D15_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define FXIO0_D16_PTC8 KINETIS_MUX('C',8,7) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define FXIO0_D17_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define FXIO0_D18_PTC10 KINETIS_MUX('C',10,7) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define FXIO0_D19_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPUART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPUART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define LPUART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define FXIO0_D20_PTC14 KINETIS_MUX('C',14,7) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define LPUART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define FXIO0_D21_PTC15 KINETIS_MUX('C',15,7) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define LPUART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D22_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D23_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define FXIO0_D24_PTD8 KINETIS_MUX('D',8,7) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define FXIO0_D25_PTD9 KINETIS_MUX('D',9,7) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FXIO0_D26_PTD10 KINETIS_MUX('D',10,7) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define FXIO0_D27_PTD11 KINETIS_MUX('D',11,7) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define FXIO0_D28_PTD12 KINETIS_MUX('D',12,7) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define FXIO0_D29_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define FXIO0_D30_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define FXIO0_D31_PTD15 KINETIS_MUX('D',15,7) /* PTD_15 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define QSPI0A_DATA3_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SCK_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define QSPI0A_SCLK_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define QSPI0A_DATA0_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,7) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_PCS2_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define QSPI0A_DATA2_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_SIN_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define QSPI0A_DATA1_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS0_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define QSPI0A_SS0_B_PTE5 KINETIS_MUX('E',5,5) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define USB0_SOF_OUT_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define QSPI0B_DATA3_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define SDHC0_D4_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define SPI2_SCK_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define LPUART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define QSPI0B_SCLK_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define QSPI0A_SS1_B_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define SPI2_SOUT_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define QSPI0B_DATA0_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define SPI2_PCS1_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define QSPI0B_DATA2_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define SDHC0_D6_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define SPI2_SIN_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define QSPI0B_DATA1_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define SDHC0_D7_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define SPI2_PCS0_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define QSPI0B_SS0_B_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define QSPI0A_DQS_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MK80FN256VLL15-pinctrl.h b/dts/nxp/kinetis/MK80FN256VLL15-pinctrl.h new file mode 100644 index 000000000..03393d52c --- /dev/null +++ b/dts/nxp/kinetis/MK80FN256VLL15-pinctrl.h @@ -0,0 +1,473 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK80FN256VLL15/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK80FN256VLL15_ +#define _ZEPHYR_DTS_BINDING_MK80FN256VLL15_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define EMVSIM0_CLK_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FXIO0_D11_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define EMVSIM0_IO_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FXIO0_D12_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define EMVSIM0_PD_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FXIO0_D13_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define EMVSIM0_RST_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FXIO0_D14_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define EMVSIM0_VCCEN_PTA4 KINETIS_MUX('A',4,6) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define FXIO0_D15_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define TRACE_CLKOUT_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define FXIO0_D18_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define TRACE_D3_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define FXIO0_D19_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define TRACE_D2_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define FXIO0_D20_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define TRACE_D1_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define FXIO0_D21_PTA15 KINETIS_MUX('A',15,5) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define TRACE_D0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define FXIO0_D22_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define FXIO0_D23_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FXIO0_D0_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FXIO0_D1_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define FXIO0_D2_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define FXIO0_D3_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define I2C2_SCL_PTB10 KINETIS_MUX('B',10,4) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define FXIO0_D4_PTB10 KINETIS_MUX('B',10,7) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define I2C2_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define FXIO0_D5_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FXIO0_D6_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D7_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D8_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D9_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define FXIO0_D10_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define FXIO0_D11_PTB23 KINETIS_MUX('B',23,7) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define FXIO0_D12_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define FXIO0_D13_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define FXIO0_D14_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define FXIO0_D15_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define FXIO0_D16_PTC8 KINETIS_MUX('C',8,7) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define FXIO0_D17_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define FXIO0_D18_PTC10 KINETIS_MUX('C',10,7) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define FXIO0_D19_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPUART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPUART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define LPUART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define FXIO0_D20_PTC14 KINETIS_MUX('C',14,7) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define LPUART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define FXIO0_D21_PTC15 KINETIS_MUX('C',15,7) /* PTC_15 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D22_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D23_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define QSPI0A_DATA3_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SCK_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define QSPI0A_SCLK_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define QSPI0A_DATA0_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,7) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_PCS2_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define QSPI0A_DATA2_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_SIN_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define QSPI0A_DATA1_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS0_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define QSPI0A_SS0_B_PTE5 KINETIS_MUX('E',5,5) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define USB0_SOF_OUT_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define QSPI0B_DATA3_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define SDHC0_D4_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define SPI2_SCK_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define LPUART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define QSPI0B_SCLK_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define QSPI0A_SS1_B_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define SPI2_SOUT_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define QSPI0B_DATA0_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define SPI2_PCS1_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define QSPI0B_DATA2_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define SDHC0_D6_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define SPI2_SIN_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define QSPI0B_DATA1_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define SDHC0_D7_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define SPI2_PCS0_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define QSPI0B_SS0_B_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define QSPI0A_DQS_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MK80FN256VLQ15-pinctrl.h b/dts/nxp/kinetis/MK80FN256VLQ15-pinctrl.h new file mode 100644 index 000000000..68e0dfa31 --- /dev/null +++ b/dts/nxp/kinetis/MK80FN256VLQ15-pinctrl.h @@ -0,0 +1,630 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MK80FN256VLQ15/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MK80FN256VLQ15_ +#define _ZEPHYR_DTS_BINDING_MK80FN256VLQ15_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define TSI0_CH1_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO0_D10_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define EMVSIM0_CLK_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TSI0_CH2_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define I2C3_SDA_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FXIO0_D11_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define EMVSIM0_IO_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TSI0_CH3_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define I2C3_SCL_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FXIO0_D12_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define EMVSIM0_PD_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define TSI0_CH4_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPUART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FXIO0_D13_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define EMVSIM0_RST_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define TSI0_CH5_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FXIO0_D14_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define EMVSIM0_VCCEN_PTA4 KINETIS_MUX('A',4,6) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB0_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define FXIO0_D15_PTA5 KINETIS_MUX('A',5,5) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define I2C2_SCL_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define FTM0_CH3_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define EMVSIM1_CLK_PTA6 KINETIS_MUX('A',6,4) /* PTA_6 */ +#define CLKOUT_PTA6 KINETIS_MUX('A',6,5) /* PTA_6 */ +#define TRACE_CLKOUT_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define ADC0_SE10_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define I2C2_SDA_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define FTM0_CH4_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define EMVSIM1_IO_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define TRACE_D3_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define ADC0_SE11_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FTM1_CH0_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define EMVSIM1_PD_PTA8 KINETIS_MUX('A',8,4) /* PTA_8 */ +#define FTM1_QD_PHA_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TPM1_CH0_PTA8 KINETIS_MUX('A',8,6) /* PTA_8 */ +#define TRACE_D2_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FTM1_CH1_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define EMVSIM1_RST_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TPM1_CH1_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define FTM1_QD_PHB_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define TRACE_D1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LLWU_P22_PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define I2C2_SDA_PTA10 KINETIS_MUX('A',10,2) /* PTA_10 */ +#define FTM2_CH0_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define EMVSIM1_VCCEN_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define FXIO0_D16_PTA10 KINETIS_MUX('A',10,5) /* PTA_10 */ +#define FTM2_QD_PHA_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TPM2_CH0_PTA10 KINETIS_MUX('A',10,6) /* PTA_10 */ +#define TRACE_D0_PTA10 KINETIS_MUX('A',10,7) /* PTA_10 */ +#define LLWU_P23_PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define I2C2_SCL_PTA11 KINETIS_MUX('A',11,2) /* PTA_11 */ +#define FTM2_CH1_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO0_D17_PTA11 KINETIS_MUX('A',11,5) /* PTA_11 */ +#define FTM2_QD_PHB_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define TPM2_CH1_PTA11 KINETIS_MUX('A',11,6) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define TRACE_CLKOUT_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define FXIO0_D18_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define TRACE_D3_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define FXIO0_D19_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define LPUART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define TRACE_D2_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define FXIO0_D20_PTA14 KINETIS_MUX('A',14,5) /* PTA_14 */ +#define I2S0_RX_BCLK_PTA14 KINETIS_MUX('A',14,6) /* PTA_14 */ +#define I2S0_TXD1_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPUART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define TRACE_D1_PTA15 KINETIS_MUX('A',15,4) /* PTA_15 */ +#define FXIO0_D21_PTA15 KINETIS_MUX('A',15,5) /* PTA_15 */ +#define I2S0_RXD0_PTA15 KINETIS_MUX('A',15,6) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPUART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define TRACE_D0_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define FXIO0_D22_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define I2S0_RX_FS_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define I2S0_RXD1_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define LPUART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define FXIO0_D23_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define I2S0_MCLK_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,7) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define LPTMR1_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,7) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define I2C0_SCL_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART4_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define FTM_CLKIN1_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define FXIO0_D8_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define EWM_OUT_b_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define TPM_CLKIN1_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LLWU_P21_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define I2C0_SDA_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART4_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define FXIO0_D9_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define EWM_IN_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define PTA24 KINETIS_MUX('A',24,1) /* PTA_24 */ +#define EMVSIM0_CLK_PTA24 KINETIS_MUX('A',24,2) /* PTA_24 */ +#define PTA25 KINETIS_MUX('A',25,1) /* PTA_25 */ +#define EMVSIM0_IO_PTA25 KINETIS_MUX('A',25,2) /* PTA_25 */ +#define PTA26 KINETIS_MUX('A',26,1) /* PTA_26 */ +#define EMVSIM0_PD_PTA26 KINETIS_MUX('A',26,2) /* PTA_26 */ +#define PTA27 KINETIS_MUX('A',27,1) /* PTA_27 */ +#define EMVSIM0_RST_PTA27 KINETIS_MUX('A',27,2) /* PTA_27 */ +#define PTA28 KINETIS_MUX('A',28,1) /* PTA_28 */ +#define EMVSIM0_VCCEN_PTA28 KINETIS_MUX('A',28,2) /* PTA_28 */ +#define PTA29 KINETIS_MUX('A',29,1) /* PTA_29 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define TSI0_CH0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SDRAM_CAS_b_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define FXIO0_D0_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define TSI0_CH6_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SDRAM_RAS_b_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define FXIO0_D1_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define TSI0_CH7_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define SDRAM_WE_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define FXIO0_D2_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define TSI0_CH8_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define SDRAM_CS0_b_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define FXIO0_D3_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define EMVSIM1_IO_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define SDRAM_CS1_b_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define FTM1_FLT0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define EMVSIM1_CLK_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define FTM2_FLT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define EMVSIM1_VCCEN_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define SDRAM_D23_PTB6 KINETIS_MUX('B',6,5) /* PTB_6 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define EMVSIM1_PD_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define SDRAM_D22_PTB7 KINETIS_MUX('B',7,5) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define EMVSIM1_RST_PTB8 KINETIS_MUX('B',8,2) /* PTB_8 */ +#define LPUART3_RTS_b_PTB8 KINETIS_MUX('B',8,3) /* PTB_8 */ +#define SDRAM_D21_PTB8 KINETIS_MUX('B',8,5) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART3_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define SDRAM_D20_PTB9 KINETIS_MUX('B',9,5) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART3_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define I2C2_SCL_PTB10 KINETIS_MUX('B',10,4) /* PTB_10 */ +#define SDRAM_D19_PTB10 KINETIS_MUX('B',10,5) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define FXIO0_D4_PTB10 KINETIS_MUX('B',10,7) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART3_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define I2C2_SDA_PTB11 KINETIS_MUX('B',11,4) /* PTB_11 */ +#define SDRAM_D18_PTB11 KINETIS_MUX('B',11,5) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define FXIO0_D5_PTB11 KINETIS_MUX('B',11,7) /* PTB_11 */ +#define TSI0_CH9_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SDRAM_D17_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define TSI0_CH10_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SDRAM_D16_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define TSI0_CH11_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define SDRAM_A23_PTB18 KINETIS_MUX('B',18,5) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define FXIO0_D6_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define TSI0_CH12_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define FXIO0_D7_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define SPI2_PCS0_PTB20 KINETIS_MUX('B',20,2) /* PTB_20 */ +#define SDRAM_D31_PTB20 KINETIS_MUX('B',20,5) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define FXIO0_D8_PTB20 KINETIS_MUX('B',20,7) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define SPI2_SCK_PTB21 KINETIS_MUX('B',21,2) /* PTB_21 */ +#define SDRAM_D30_PTB21 KINETIS_MUX('B',21,5) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define FXIO0_D9_PTB21 KINETIS_MUX('B',21,7) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define SPI2_SOUT_PTB22 KINETIS_MUX('B',22,2) /* PTB_22 */ +#define SDRAM_D29_PTB22 KINETIS_MUX('B',22,5) /* PTB_22 */ +#define FXIO0_D10_PTB22 KINETIS_MUX('B',22,7) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI2_SIN_PTB23 KINETIS_MUX('B',23,2) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define SDRAM_D28_PTB23 KINETIS_MUX('B',23,5) /* PTB_23 */ +#define FXIO0_D11_PTB23 KINETIS_MUX('B',23,7) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH13_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB0_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define SDRAM_A22_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define FXIO0_D12_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define TSI0_CH14_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LPUART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define SDRAM_A21_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define FXIO0_D13_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define TSI0_CH15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define SDRAM_A20_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SDRAM_A19_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR1_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define SDRAM_A18_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SDRAM_A17_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define FXIO0_D14_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB0_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SDRAM_A16_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define FXIO0_D15_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define SDRAM_A15_PTC8 KINETIS_MUX('C',8,5) /* PTC_8 */ +#define FXIO0_D16_PTC8 KINETIS_MUX('C',8,7) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define SDRAM_A14_PTC9 KINETIS_MUX('C',9,5) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define FXIO0_D17_PTC9 KINETIS_MUX('C',9,7) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define SDRAM_A13_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define FXIO0_D18_PTC10 KINETIS_MUX('C',10,7) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define I2S0_RXD1_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define FXIO0_D19_PTC11 KINETIS_MUX('C',11,7) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPUART4_RTS_b_PTC12 KINETIS_MUX('C',12,3) /* PTC_12 */ +#define FTM_CLKIN0_PTC12 KINETIS_MUX('C',12,4) /* PTC_12 */ +#define SDRAM_D27_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define TPM_CLKIN0_PTC12 KINETIS_MUX('C',12,7) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPUART4_CTS_b_PTC13 KINETIS_MUX('C',13,3) /* PTC_13 */ +#define FTM_CLKIN1_PTC13 KINETIS_MUX('C',13,4) /* PTC_13 */ +#define SDRAM_D26_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define TPM_CLKIN1_PTC13 KINETIS_MUX('C',13,7) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define LPUART4_RX_PTC14 KINETIS_MUX('C',14,3) /* PTC_14 */ +#define SDRAM_D25_PTC14 KINETIS_MUX('C',14,5) /* PTC_14 */ +#define FXIO0_D20_PTC14 KINETIS_MUX('C',14,7) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define LPUART4_TX_PTC15 KINETIS_MUX('C',15,3) /* PTC_15 */ +#define SDRAM_D24_PTC15 KINETIS_MUX('C',15,5) /* PTC_15 */ +#define FXIO0_D21_PTC15 KINETIS_MUX('C',15,7) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART3_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define SDRAM_DQM2_PTC16 KINETIS_MUX('C',16,5) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART3_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define SDRAM_DQM3_PTC17 KINETIS_MUX('C',17,5) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART3_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define SDRAM_DQM1_PTC18 KINETIS_MUX('C',18,5) /* PTC_18 */ +#define PTC19 KINETIS_MUX('C',19,1) /* PTC_19 */ +#define LPUART3_CTS_b_PTC19 KINETIS_MUX('C',19,3) /* PTC_19 */ +#define SDRAM_DQM0_PTC19 KINETIS_MUX('C',19,5) /* PTC_19 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPUART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D22_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPUART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D23_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define LPUART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SDRAM_A12_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define LPUART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SDRAM_A11_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define LPUART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define SDRAM_A10_PTD4 KINETIS_MUX('D',4,5) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPUART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define SDRAM_A9_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define CMT_IRO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SDRAM_CKE_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LLWU_P24_PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define I2C0_SCL_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define FXIO0_D24_PTD8 KINETIS_MUX('D',8,7) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define I2C0_SDA_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define FXIO0_D25_PTD9 KINETIS_MUX('D',9,7) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FXIO0_D26_PTD10 KINETIS_MUX('D',10,7) /* PTD_10 */ +#define LLWU_P25_PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define SPI2_PCS0_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define FXIO0_D27_PTD11 KINETIS_MUX('D',11,7) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define SPI2_SCK_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define FTM3_FLT0_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define FXIO0_D28_PTD12 KINETIS_MUX('D',12,7) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define SPI2_SOUT_PTD13 KINETIS_MUX('D',13,2) /* PTD_13 */ +#define FXIO0_D29_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define SPI2_SIN_PTD14 KINETIS_MUX('D',14,2) /* PTD_14 */ +#define FXIO0_D30_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define SPI2_PCS1_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define FXIO0_D31_PTD15 KINETIS_MUX('D',15,7) /* PTD_15 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define SDHC0_D1_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define QSPI0A_DATA3_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SCK_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SDHC0_D0_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define QSPI0A_SCLK_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPUART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define SDHC0_DCLK_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define QSPI0A_DATA0_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,7) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_PCS2_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SDHC0_CMD_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define QSPI0A_DATA2_PTE3 KINETIS_MUX('E',3,5) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_SIN_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART3_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define SDHC0_D3_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define QSPI0A_DATA1_PTE4 KINETIS_MUX('E',4,5) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS0_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART3_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define SDHC0_D2_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define QSPI0A_SS0_B_PTE5 KINETIS_MUX('E',5,5) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define USB0_SOF_OUT_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P16_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART3_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define I2S0_MCLK_PTE6 KINETIS_MUX('E',6,4) /* PTE_6 */ +#define QSPI0B_DATA3_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define SDHC0_D4_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define SPI2_SCK_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define LPUART3_RTS_b_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2S0_RXD0_PTE7 KINETIS_MUX('E',7,4) /* PTE_7 */ +#define QSPI0B_SCLK_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define FTM3_CH2_PTE7 KINETIS_MUX('E',7,6) /* PTE_7 */ +#define QSPI0A_SS1_B_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define I2S0_RXD1_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define SPI2_SOUT_PTE8 KINETIS_MUX('E',8,3) /* PTE_8 */ +#define I2S0_RX_FS_PTE8 KINETIS_MUX('E',8,4) /* PTE_8 */ +#define QSPI0B_DATA0_PTE8 KINETIS_MUX('E',8,5) /* PTE_8 */ +#define FTM3_CH3_PTE8 KINETIS_MUX('E',8,6) /* PTE_8 */ +#define SDHC0_D5_PTE8 KINETIS_MUX('E',8,7) /* PTE_8 */ +#define LLWU_P17_PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define I2S0_TXD1_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define SPI2_PCS1_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define I2S0_RX_BCLK_PTE9 KINETIS_MUX('E',9,4) /* PTE_9 */ +#define QSPI0B_DATA2_PTE9 KINETIS_MUX('E',9,5) /* PTE_9 */ +#define FTM3_CH4_PTE9 KINETIS_MUX('E',9,6) /* PTE_9 */ +#define SDHC0_D6_PTE9 KINETIS_MUX('E',9,7) /* PTE_9 */ +#define LLWU_P18_PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define I2C3_SDA_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define SPI2_SIN_PTE10 KINETIS_MUX('E',10,3) /* PTE_10 */ +#define I2S0_TXD0_PTE10 KINETIS_MUX('E',10,4) /* PTE_10 */ +#define QSPI0B_DATA1_PTE10 KINETIS_MUX('E',10,5) /* PTE_10 */ +#define FTM3_CH5_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define SDHC0_D7_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define I2C3_SCL_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define SPI2_PCS0_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define I2S0_TX_FS_PTE11 KINETIS_MUX('E',11,4) /* PTE_11 */ +#define QSPI0B_SS0_B_PTE11 KINETIS_MUX('E',11,5) /* PTE_11 */ +#define FTM3_CH6_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define QSPI0A_DQS_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define I2S0_TX_BCLK_PTE12 KINETIS_MUX('E',12,4) /* PTE_12 */ +#define QSPI0B_DQS_PTE12 KINETIS_MUX('E',12,5) /* PTE_12 */ +#define FTM3_CH7_PTE12 KINETIS_MUX('E',12,6) /* PTE_12 */ +#define FXIO0_D2_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define LPUART2_RX_PTE13 KINETIS_MUX('E',13,3) /* PTE_13 */ +#define QSPI0B_SS1_B_PTE13 KINETIS_MUX('E',13,5) /* PTE_13 */ +#define SDHC0_CLKIN_PTE13 KINETIS_MUX('E',13,6) /* PTE_13 */ +#define FXIO0_D3_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define LPUART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define FXIO0_D4_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define LLWU_P19_PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define LPUART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define LPTMR1_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define FXIO0_D5_PTE17 KINETIS_MUX('E',17,7) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define LLWU_P20_PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define LPUART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define FXIO0_D6_PTE18 KINETIS_MUX('E',18,7) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define LPUART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define FXIO0_D7_PTE19 KINETIS_MUX('E',19,7) /* PTE_19 */ +#endif diff --git a/dts/nxp/kinetis/MKE12Z128VLF7-pinctrl.h b/dts/nxp/kinetis/MKE12Z128VLF7-pinctrl.h new file mode 100644 index 000000000..f02e3af2a --- /dev/null +++ b/dts/nxp/kinetis/MKE12Z128VLF7-pinctrl.h @@ -0,0 +1,205 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE12Z128VLF7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE12Z128VLF7_ +#define _ZEPHYR_DTS_BINDING_MKE12Z128VLF7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE12Z128VLH7-pinctrl.h b/dts/nxp/kinetis/MKE12Z128VLH7-pinctrl.h new file mode 100644 index 000000000..ff7b34226 --- /dev/null +++ b/dts/nxp/kinetis/MKE12Z128VLH7-pinctrl.h @@ -0,0 +1,245 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE12Z128VLH7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE12Z128VLH7_ +#define _ZEPHYR_DTS_BINDING_MKE12Z128VLH7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE12Z128VLL7-pinctrl.h b/dts/nxp/kinetis/MKE12Z128VLL7-pinctrl.h new file mode 100644 index 000000000..c77559257 --- /dev/null +++ b/dts/nxp/kinetis/MKE12Z128VLL7-pinctrl.h @@ -0,0 +1,339 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE12Z128VLL7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE12Z128VLL7_ +#define _ZEPHYR_DTS_BINDING_MKE12Z128VLL7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FXIO_D6_PTA8 KINETIS_MUX('A',8,4) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FXIO_D7_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define FTM0_FLT0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define EWM_IN_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define BUSOUT_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define FTM1_CH2_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPSPI0_PCS3_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define FTM1_CH3_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPI2C0_SDA_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define FTM0_CH6_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM_OUT_b_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPI2C0_SCL_PTB8 KINETIS_MUX('B',8,4) /* PTB_8 */ +#define FXIO_D4_PTB8 KINETIS_MUX('B',8,6) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPI2C0_SCLS_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define FXIO_D5_PTB9 KINETIS_MUX('B',9,6) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define FTM0_CH0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPI2C0_SDAS_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FXIO_D0_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define FTM0_CH1_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPI2C0_HREQ_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FXIO_D1_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define FTM0_CH2_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define FTM0_CH3_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define FTM0_CH4_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define FTM0_CH5_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPSPI0_SCK_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPSPI0_SIN_PTC11 KINETIS_MUX('C',11,5) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPSPI0_SOUT_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPSPI0_PCS0_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define FTM0_CH7_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPSPI0_PCS1_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define FXIO_D2_PTD9 KINETIS_MUX('D',9,6) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FTM2_CH0_PTD10 KINETIS_MUX('D',10,2) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define FTM2_CH1_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART2_CTS_PTD11 KINETIS_MUX('D',11,6) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define FTM2_CH2_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define LPUART2_RTS_PTD12 KINETIS_MUX('D',12,6) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define LPUART1_RX_PTD13 KINETIS_MUX('D',13,3) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define LPUART1_TX_PTD14 KINETIS_MUX('D',14,3) /* PTD_14 */ +#define CLKOUT_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTD17 KINETIS_MUX('D',17,1) /* PTD_17 */ +#define FTM0_FLT2_PTD17 KINETIS_MUX('D',17,2) /* PTD_17 */ +#define LPUART2_RX_PTD17 KINETIS_MUX('D',17,3) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define FTM0_FLT3_PTE12 KINETIS_MUX('E',12,2) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define PTE14 KINETIS_MUX('E',14,1) /* PTE_14 */ +#define FTM0_FLT1_PTE14 KINETIS_MUX('E',14,2) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define PTE15 KINETIS_MUX('E',15,1) /* PTE_15 */ +#define FXIO_D2_PTE15 KINETIS_MUX('E',15,6) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define FXIO_D3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#endif diff --git a/dts/nxp/kinetis/MKE12Z256VLF7-pinctrl.h b/dts/nxp/kinetis/MKE12Z256VLF7-pinctrl.h new file mode 100644 index 000000000..13300851e --- /dev/null +++ b/dts/nxp/kinetis/MKE12Z256VLF7-pinctrl.h @@ -0,0 +1,205 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE12Z256VLF7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE12Z256VLF7_ +#define _ZEPHYR_DTS_BINDING_MKE12Z256VLF7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE12Z256VLH7-pinctrl.h b/dts/nxp/kinetis/MKE12Z256VLH7-pinctrl.h new file mode 100644 index 000000000..f3b568a87 --- /dev/null +++ b/dts/nxp/kinetis/MKE12Z256VLH7-pinctrl.h @@ -0,0 +1,245 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE12Z256VLH7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE12Z256VLH7_ +#define _ZEPHYR_DTS_BINDING_MKE12Z256VLH7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE12Z256VLL7-pinctrl.h b/dts/nxp/kinetis/MKE12Z256VLL7-pinctrl.h new file mode 100644 index 000000000..0de7c8fea --- /dev/null +++ b/dts/nxp/kinetis/MKE12Z256VLL7-pinctrl.h @@ -0,0 +1,339 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE12Z256VLL7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE12Z256VLL7_ +#define _ZEPHYR_DTS_BINDING_MKE12Z256VLL7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FXIO_D6_PTA8 KINETIS_MUX('A',8,4) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FXIO_D7_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define FTM0_FLT0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define EWM_IN_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define BUSOUT_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define FTM1_CH2_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPSPI0_PCS3_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define FTM1_CH3_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPI2C0_SDA_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define FTM0_CH6_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM_OUT_b_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPI2C0_SCL_PTB8 KINETIS_MUX('B',8,4) /* PTB_8 */ +#define FXIO_D4_PTB8 KINETIS_MUX('B',8,6) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPI2C0_SCLS_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define FXIO_D5_PTB9 KINETIS_MUX('B',9,6) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define FTM0_CH0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPI2C0_SDAS_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FXIO_D0_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define FTM0_CH1_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPI2C0_HREQ_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FXIO_D1_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define FTM0_CH2_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define FTM0_CH3_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define FTM0_CH4_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define FTM0_CH5_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPSPI0_SCK_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPSPI0_SIN_PTC11 KINETIS_MUX('C',11,5) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPSPI0_SOUT_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPSPI0_PCS0_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define FTM0_CH7_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPSPI0_PCS1_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define FXIO_D2_PTD9 KINETIS_MUX('D',9,6) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FTM2_CH0_PTD10 KINETIS_MUX('D',10,2) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define FTM2_CH1_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART2_CTS_PTD11 KINETIS_MUX('D',11,6) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define FTM2_CH2_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define LPUART2_RTS_PTD12 KINETIS_MUX('D',12,6) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define LPUART1_RX_PTD13 KINETIS_MUX('D',13,3) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define LPUART1_TX_PTD14 KINETIS_MUX('D',14,3) /* PTD_14 */ +#define CLKOUT_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTD17 KINETIS_MUX('D',17,1) /* PTD_17 */ +#define FTM0_FLT2_PTD17 KINETIS_MUX('D',17,2) /* PTD_17 */ +#define LPUART2_RX_PTD17 KINETIS_MUX('D',17,3) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define FTM0_FLT3_PTE12 KINETIS_MUX('E',12,2) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define PTE14 KINETIS_MUX('E',14,1) /* PTE_14 */ +#define FTM0_FLT1_PTE14 KINETIS_MUX('E',14,2) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define PTE15 KINETIS_MUX('E',15,1) /* PTE_15 */ +#define FXIO_D2_PTE15 KINETIS_MUX('E',15,6) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define FXIO_D3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#endif diff --git a/dts/nxp/kinetis/MKE12Z512VLH9-pinctrl.h b/dts/nxp/kinetis/MKE12Z512VLH9-pinctrl.h new file mode 100644 index 000000000..f282398fd --- /dev/null +++ b/dts/nxp/kinetis/MKE12Z512VLH9-pinctrl.h @@ -0,0 +1,275 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE12Z512VLH9/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE12Z512VLH9_ +#define _ZEPHYR_DTS_BINDING_MKE12Z512VLH9_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPSPI1_PCS1_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPI2C1_SDAS_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPI2C1_SCLS_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define ADC0_SE21_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE20_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE19_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE18_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define SCI1_RX_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define SCI1_TX_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define SCI0_RX_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define SCI0_TX_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPI2C1_HREQ_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define ADC0_SE24_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define ADC0_SE22_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC0_SE17_PTC14 KINETIS_MUX('C',14,0) /* PTC_14 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define SCI0_RX_PTC14 KINETIS_MUX('C',14,4) /* PTC_14 */ +#define ADC0_SE16_PTC15 KINETIS_MUX('C',15,0) /* PTC_15 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define SCI0_TX_PTC15 KINETIS_MUX('C',15,4) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPI2C1_SDAS_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define SCI1_RX_PTC16 KINETIS_MUX('C',16,6) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPI2C1_SCLS_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define SCI1_TX_PTC17 KINETIS_MUX('C',17,6) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI1_SCK_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI1_SIN_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI1_SOUT_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI1_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE12Z512VLL9-pinctrl.h b/dts/nxp/kinetis/MKE12Z512VLL9-pinctrl.h new file mode 100644 index 000000000..eed907ce0 --- /dev/null +++ b/dts/nxp/kinetis/MKE12Z512VLL9-pinctrl.h @@ -0,0 +1,378 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE12Z512VLL9/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE12Z512VLL9_ +#define _ZEPHYR_DTS_BINDING_MKE12Z512VLL9_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPSPI1_PCS1_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FXIO_D6_PTA8 KINETIS_MUX('A',8,4) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FXIO_D7_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPI2C1_SDAS_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPI2C1_SCLS_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define FTM0_FLT0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define EWM_IN_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define BUSOUT_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define FTM1_CH2_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPSPI0_PCS3_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define FTM1_CH3_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPSPI1_PCS2_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define LPI2C0_SDA_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define FTM0_CH6_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM_OUT_b_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define ADC0_SE21_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE20_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE19_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE18_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPI2C0_SCL_PTB8 KINETIS_MUX('B',8,4) /* PTB_8 */ +#define FXIO_D4_PTB8 KINETIS_MUX('B',8,6) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPI2C0_SCLS_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define FXIO_D5_PTB9 KINETIS_MUX('B',9,6) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define FTM0_CH0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPI2C0_SDAS_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FXIO_D0_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define FTM0_CH1_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPI2C0_HREQ_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FXIO_D1_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define SCI1_RX_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define SCI1_TX_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define FTM0_CH2_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define LPSPI1_SCK_PTB14 KINETIS_MUX('B',14,3) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define FTM0_CH3_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define LPSPI1_SIN_PTB15 KINETIS_MUX('B',15,3) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define FTM0_CH4_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPSPI1_SOUT_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define FTM0_CH5_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPSPI1_PCS3_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define SCI0_RX_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define SCI0_TX_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPI2C1_HREQ_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define ADC0_SE24_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define ADC0_SE22_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPSPI0_SCK_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPSPI0_SIN_PTC11 KINETIS_MUX('C',11,5) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPSPI0_SOUT_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPSPI0_PCS0_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define ADC0_SE17_PTC14 KINETIS_MUX('C',14,0) /* PTC_14 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define SCI0_RX_PTC14 KINETIS_MUX('C',14,4) /* PTC_14 */ +#define ADC0_SE16_PTC15 KINETIS_MUX('C',15,0) /* PTC_15 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define SCI0_TX_PTC15 KINETIS_MUX('C',15,4) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPI2C1_SDAS_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define SCI1_RX_PTC16 KINETIS_MUX('C',16,6) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPI2C1_SCLS_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define SCI1_TX_PTC17 KINETIS_MUX('C',17,6) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI1_SCK_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI1_SIN_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI1_SOUT_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI1_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define FTM0_CH7_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPI2C1_SDA_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define LPSPI0_PCS1_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define LPI2C1_SCL_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define FXIO_D2_PTD9 KINETIS_MUX('D',9,6) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FTM2_CH0_PTD10 KINETIS_MUX('D',10,2) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define FTM2_CH1_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART2_CTS_PTD11 KINETIS_MUX('D',11,6) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define FTM2_CH2_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define LPI2C1_HREQ_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define LPUART2_RTS_PTD12 KINETIS_MUX('D',12,6) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define LPUART1_RX_PTD13 KINETIS_MUX('D',13,3) /* PTD_13 */ +#define RTC_CLKOUT_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define LPUART1_TX_PTD14 KINETIS_MUX('D',14,3) /* PTD_14 */ +#define CLKOUT_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTD17 KINETIS_MUX('D',17,1) /* PTD_17 */ +#define FTM0_FLT2_PTD17 KINETIS_MUX('D',17,2) /* PTD_17 */ +#define LPUART2_RX_PTD17 KINETIS_MUX('D',17,3) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define FTM0_FLT3_PTE12 KINETIS_MUX('E',12,2) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define PTE14 KINETIS_MUX('E',14,1) /* PTE_14 */ +#define FTM0_FLT1_PTE14 KINETIS_MUX('E',14,2) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define PTE15 KINETIS_MUX('E',15,1) /* PTE_15 */ +#define FXIO_D2_PTE15 KINETIS_MUX('E',15,6) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define FXIO_D3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#endif diff --git a/dts/nxp/kinetis/MKE13Z128VLF7-pinctrl.h b/dts/nxp/kinetis/MKE13Z128VLF7-pinctrl.h new file mode 100644 index 000000000..9743efc7f --- /dev/null +++ b/dts/nxp/kinetis/MKE13Z128VLF7-pinctrl.h @@ -0,0 +1,220 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE13Z128VLF7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE13Z128VLF7_ +#define _ZEPHYR_DTS_BINDING_MKE13Z128VLF7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define TSI0_CH24_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define TSI0_CH23_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define TSI0_CH8_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define TSI0_CH12_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TSI0_CH11_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define TSI0_CH7_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define TSI0_CH6_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define TSI0_CH1_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define TSI0_CH18_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TSI0_CH17_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define TSI0_CH16_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define TSI0_CH0_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define TSI0_CH22_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define TSI0_CH10_PTE10 KINETIS_MUX('E',10,0) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TSI0_CH9_PTE11 KINETIS_MUX('E',11,0) /* PTE_11 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE13Z128VLH7-pinctrl.h b/dts/nxp/kinetis/MKE13Z128VLH7-pinctrl.h new file mode 100644 index 000000000..a6c3159e9 --- /dev/null +++ b/dts/nxp/kinetis/MKE13Z128VLH7-pinctrl.h @@ -0,0 +1,267 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE13Z128VLH7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE13Z128VLH7_ +#define _ZEPHYR_DTS_BINDING_MKE13Z128VLH7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define TSI0_CH5_PTA10 KINETIS_MUX('A',10,0) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define TSI0_CH4_PTA11 KINETIS_MUX('A',11,0) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define TSI0_CH3_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define TSI0_CH2_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define TSI0_CH24_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define TSI0_CH23_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define TSI0_CH8_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define TSI0_CH12_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TSI0_CH11_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define TSI0_CH20_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define TSI0_CH19_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define TSI0_CH7_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define TSI0_CH6_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define TSI0_CH1_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define TSI0_CH18_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TSI0_CH17_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define TSI0_CH16_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define TSI0_CH0_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define TSI0_CH22_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define TSI0_CH21_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define TSI0_CH10_PTE10 KINETIS_MUX('E',10,0) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TSI0_CH9_PTE11 KINETIS_MUX('E',11,0) /* PTE_11 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE13Z128VLL7-pinctrl.h b/dts/nxp/kinetis/MKE13Z128VLL7-pinctrl.h new file mode 100644 index 000000000..bb243560e --- /dev/null +++ b/dts/nxp/kinetis/MKE13Z128VLL7-pinctrl.h @@ -0,0 +1,364 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE13Z128VLL7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE13Z128VLL7_ +#define _ZEPHYR_DTS_BINDING_MKE13Z128VLL7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FXIO_D6_PTA8 KINETIS_MUX('A',8,4) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FXIO_D7_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define TSI0_CH5_PTA10 KINETIS_MUX('A',10,0) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define TSI0_CH4_PTA11 KINETIS_MUX('A',11,0) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define TSI0_CH3_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define TSI0_CH2_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define FTM0_FLT0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define EWM_IN_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define BUSOUT_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define FTM1_CH2_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPSPI0_PCS3_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define FTM1_CH3_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPI2C0_SDA_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define FTM0_CH6_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM_OUT_b_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define TSI0_CH24_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define TSI0_CH23_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPI2C0_SCL_PTB8 KINETIS_MUX('B',8,4) /* PTB_8 */ +#define FXIO_D4_PTB8 KINETIS_MUX('B',8,6) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPI2C0_SCLS_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define FXIO_D5_PTB9 KINETIS_MUX('B',9,6) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define FTM0_CH0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPI2C0_SDAS_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FXIO_D0_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define FTM0_CH1_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPI2C0_HREQ_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FXIO_D1_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define FTM0_CH2_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define FTM0_CH3_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define FTM0_CH4_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define FTM0_CH5_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define TSI0_CH8_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPSPI0_SCK_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPSPI0_SIN_PTC11 KINETIS_MUX('C',11,5) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPSPI0_SOUT_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPSPI0_PCS0_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define TSI0_CH12_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TSI0_CH11_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define FTM0_CH7_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPSPI0_PCS1_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define FXIO_D2_PTD9 KINETIS_MUX('D',9,6) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FTM2_CH0_PTD10 KINETIS_MUX('D',10,2) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define FTM2_CH1_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART2_CTS_PTD11 KINETIS_MUX('D',11,6) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define FTM2_CH2_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define LPUART2_RTS_PTD12 KINETIS_MUX('D',12,6) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define LPUART1_RX_PTD13 KINETIS_MUX('D',13,3) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define LPUART1_TX_PTD14 KINETIS_MUX('D',14,3) /* PTD_14 */ +#define CLKOUT_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define TSI0_CH20_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define TSI0_CH19_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTD17 KINETIS_MUX('D',17,1) /* PTD_17 */ +#define FTM0_FLT2_PTD17 KINETIS_MUX('D',17,2) /* PTD_17 */ +#define LPUART2_RX_PTD17 KINETIS_MUX('D',17,3) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define TSI0_CH7_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define TSI0_CH6_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define TSI0_CH1_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define TSI0_CH18_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TSI0_CH17_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define TSI0_CH16_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define TSI0_CH0_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define TSI0_CH22_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define TSI0_CH21_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define TSI0_CH10_PTE10 KINETIS_MUX('E',10,0) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TSI0_CH9_PTE11 KINETIS_MUX('E',11,0) /* PTE_11 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define FTM0_FLT3_PTE12 KINETIS_MUX('E',12,2) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define TSI0_CH15_PTE13 KINETIS_MUX('E',13,0) /* PTE_13 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define PTE14 KINETIS_MUX('E',14,1) /* PTE_14 */ +#define FTM0_FLT1_PTE14 KINETIS_MUX('E',14,2) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define TSI0_CH14_PTE15 KINETIS_MUX('E',15,0) /* PTE_15 */ +#define PTE15 KINETIS_MUX('E',15,1) /* PTE_15 */ +#define FXIO_D2_PTE15 KINETIS_MUX('E',15,6) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TSI0_CH13_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define FXIO_D3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#endif diff --git a/dts/nxp/kinetis/MKE13Z256VLF7-pinctrl.h b/dts/nxp/kinetis/MKE13Z256VLF7-pinctrl.h new file mode 100644 index 000000000..2ca334c37 --- /dev/null +++ b/dts/nxp/kinetis/MKE13Z256VLF7-pinctrl.h @@ -0,0 +1,220 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE13Z256VLF7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE13Z256VLF7_ +#define _ZEPHYR_DTS_BINDING_MKE13Z256VLF7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define TSI0_CH24_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define TSI0_CH23_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define TSI0_CH8_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define TSI0_CH12_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TSI0_CH11_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define TSI0_CH7_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define TSI0_CH6_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define TSI0_CH1_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define TSI0_CH18_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TSI0_CH17_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define TSI0_CH16_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define TSI0_CH0_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define TSI0_CH22_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define TSI0_CH10_PTE10 KINETIS_MUX('E',10,0) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TSI0_CH9_PTE11 KINETIS_MUX('E',11,0) /* PTE_11 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE13Z256VLH7-pinctrl.h b/dts/nxp/kinetis/MKE13Z256VLH7-pinctrl.h new file mode 100644 index 000000000..9ee12b2fb --- /dev/null +++ b/dts/nxp/kinetis/MKE13Z256VLH7-pinctrl.h @@ -0,0 +1,267 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE13Z256VLH7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE13Z256VLH7_ +#define _ZEPHYR_DTS_BINDING_MKE13Z256VLH7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define TSI0_CH5_PTA10 KINETIS_MUX('A',10,0) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define TSI0_CH4_PTA11 KINETIS_MUX('A',11,0) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define TSI0_CH3_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define TSI0_CH2_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define TSI0_CH24_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define TSI0_CH23_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define TSI0_CH8_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define TSI0_CH12_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TSI0_CH11_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define TSI0_CH20_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define TSI0_CH19_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define TSI0_CH7_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define TSI0_CH6_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define TSI0_CH1_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define TSI0_CH18_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TSI0_CH17_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define TSI0_CH16_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define TSI0_CH0_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define TSI0_CH22_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define TSI0_CH21_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define TSI0_CH10_PTE10 KINETIS_MUX('E',10,0) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TSI0_CH9_PTE11 KINETIS_MUX('E',11,0) /* PTE_11 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE13Z256VLL7-pinctrl.h b/dts/nxp/kinetis/MKE13Z256VLL7-pinctrl.h new file mode 100644 index 000000000..218ed6301 --- /dev/null +++ b/dts/nxp/kinetis/MKE13Z256VLL7-pinctrl.h @@ -0,0 +1,364 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE13Z256VLL7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE13Z256VLL7_ +#define _ZEPHYR_DTS_BINDING_MKE13Z256VLL7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FXIO_D6_PTA8 KINETIS_MUX('A',8,4) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FXIO_D7_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define TSI0_CH5_PTA10 KINETIS_MUX('A',10,0) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define TSI0_CH4_PTA11 KINETIS_MUX('A',11,0) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define TSI0_CH3_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define TSI0_CH2_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define FTM0_FLT0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define EWM_IN_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define BUSOUT_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define FTM1_CH2_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPSPI0_PCS3_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define FTM1_CH3_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPI2C0_SDA_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define FTM0_CH6_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM_OUT_b_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define TSI0_CH24_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define TSI0_CH23_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPI2C0_SCL_PTB8 KINETIS_MUX('B',8,4) /* PTB_8 */ +#define FXIO_D4_PTB8 KINETIS_MUX('B',8,6) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPI2C0_SCLS_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define FXIO_D5_PTB9 KINETIS_MUX('B',9,6) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define FTM0_CH0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPI2C0_SDAS_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FXIO_D0_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define FTM0_CH1_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPI2C0_HREQ_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FXIO_D1_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define FTM0_CH2_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define FTM0_CH3_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define FTM0_CH4_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define FTM0_CH5_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define TSI0_CH8_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPSPI0_SCK_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPSPI0_SIN_PTC11 KINETIS_MUX('C',11,5) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPSPI0_SOUT_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPSPI0_PCS0_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define TSI0_CH12_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TSI0_CH11_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define FTM0_CH7_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPSPI0_PCS1_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define FXIO_D2_PTD9 KINETIS_MUX('D',9,6) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FTM2_CH0_PTD10 KINETIS_MUX('D',10,2) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define FTM2_CH1_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART2_CTS_PTD11 KINETIS_MUX('D',11,6) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define FTM2_CH2_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define LPUART2_RTS_PTD12 KINETIS_MUX('D',12,6) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define LPUART1_RX_PTD13 KINETIS_MUX('D',13,3) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define LPUART1_TX_PTD14 KINETIS_MUX('D',14,3) /* PTD_14 */ +#define CLKOUT_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define TSI0_CH20_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define TSI0_CH19_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTD17 KINETIS_MUX('D',17,1) /* PTD_17 */ +#define FTM0_FLT2_PTD17 KINETIS_MUX('D',17,2) /* PTD_17 */ +#define LPUART2_RX_PTD17 KINETIS_MUX('D',17,3) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define TSI0_CH7_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define TSI0_CH6_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define TSI0_CH1_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define TSI0_CH18_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TSI0_CH17_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define TSI0_CH16_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define TSI0_CH0_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define TSI0_CH22_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define TSI0_CH21_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define TSI0_CH10_PTE10 KINETIS_MUX('E',10,0) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TSI0_CH9_PTE11 KINETIS_MUX('E',11,0) /* PTE_11 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define FTM0_FLT3_PTE12 KINETIS_MUX('E',12,2) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define TSI0_CH15_PTE13 KINETIS_MUX('E',13,0) /* PTE_13 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define PTE14 KINETIS_MUX('E',14,1) /* PTE_14 */ +#define FTM0_FLT1_PTE14 KINETIS_MUX('E',14,2) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define TSI0_CH14_PTE15 KINETIS_MUX('E',15,0) /* PTE_15 */ +#define PTE15 KINETIS_MUX('E',15,1) /* PTE_15 */ +#define FXIO_D2_PTE15 KINETIS_MUX('E',15,6) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TSI0_CH13_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define FXIO_D3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#endif diff --git a/dts/nxp/kinetis/MKE13Z512VLH9-pinctrl.h b/dts/nxp/kinetis/MKE13Z512VLH9-pinctrl.h new file mode 100644 index 000000000..5174460ab --- /dev/null +++ b/dts/nxp/kinetis/MKE13Z512VLH9-pinctrl.h @@ -0,0 +1,297 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE13Z512VLH9/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE13Z512VLH9_ +#define _ZEPHYR_DTS_BINDING_MKE13Z512VLH9_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPSPI1_PCS1_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define TSI0_CH5_PTA10 KINETIS_MUX('A',10,0) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define TSI0_CH4_PTA11 KINETIS_MUX('A',11,0) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define TSI0_CH3_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPI2C1_SDAS_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define TSI0_CH2_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPI2C1_SCLS_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define ADC0_SE21_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE20_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE19_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE18_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define TSI0_CH24_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define TSI0_CH23_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define SCI1_RX_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define SCI1_TX_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define SCI0_RX_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define SCI0_TX_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define TSI0_CH8_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPI2C1_HREQ_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define ADC0_SE24_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define ADC0_SE22_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC0_SE17_PTC14 KINETIS_MUX('C',14,0) /* PTC_14 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define SCI0_RX_PTC14 KINETIS_MUX('C',14,4) /* PTC_14 */ +#define ADC0_SE16_PTC15 KINETIS_MUX('C',15,0) /* PTC_15 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define SCI0_TX_PTC15 KINETIS_MUX('C',15,4) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPI2C1_SDAS_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define SCI1_RX_PTC16 KINETIS_MUX('C',16,6) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPI2C1_SCLS_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define SCI1_TX_PTC17 KINETIS_MUX('C',17,6) /* PTC_17 */ +#define TSI0_CH12_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI1_SCK_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TSI0_CH11_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI1_SIN_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI1_SOUT_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI1_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define TSI0_CH20_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define TSI0_CH19_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define TSI0_CH7_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TSI0_CH6_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TSI0_CH1_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define TSI0_CH18_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TSI0_CH17_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define TSI0_CH16_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define TSI0_CH0_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define TSI0_CH22_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define TSI0_CH21_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define TSI0_CH10_PTE10 KINETIS_MUX('E',10,0) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TSI0_CH9_PTE11 KINETIS_MUX('E',11,0) /* PTE_11 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE13Z512VLL9-pinctrl.h b/dts/nxp/kinetis/MKE13Z512VLL9-pinctrl.h new file mode 100644 index 000000000..6d7892ecd --- /dev/null +++ b/dts/nxp/kinetis/MKE13Z512VLL9-pinctrl.h @@ -0,0 +1,403 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE13Z512VLL9/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE13Z512VLL9_ +#define _ZEPHYR_DTS_BINDING_MKE13Z512VLL9_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LPUART1_TX_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPSPI1_PCS1_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FXIO_D6_PTA8 KINETIS_MUX('A',8,4) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define TRGMUX_OUT0_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8_PTA8 KINETIS_MUX('A',8,7) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FXIO_D7_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define TRGMUX_OUT1_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9_PTA9 KINETIS_MUX('A',9,7) /* PTA_9 */ +#define TSI0_CH5_PTA10 KINETIS_MUX('A',10,0) /* PTA_10 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define TSI0_CH4_PTA11 KINETIS_MUX('A',11,0) /* PTA_11 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define TSI0_CH3_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPI2C1_SDAS_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define LPUART0_TX_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define TSI0_CH2_PTA13 KINETIS_MUX('A',13,0) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPI2C1_SCLS_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define LPUART0_RX_PTA13 KINETIS_MUX('A',13,5) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define FTM0_FLT0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define EWM_IN_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define BUSOUT_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define FTM1_CH2_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPSPI0_PCS3_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define FTM1_CH3_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPSPI1_PCS2_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define LPI2C0_SDA_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define FTM0_CH6_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM_OUT_b_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define ADC0_SE21_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE20_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE19_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE18_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ADC0_SE5_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define TSI0_CH24_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define TSI0_CH23_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define ADC0_SE3_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define LPUART0_RX_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LPUART0_TX_PTB7 KINETIS_MUX('B',7,3) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define LPI2C0_SCL_PTB8 KINETIS_MUX('B',8,4) /* PTB_8 */ +#define FXIO_D4_PTB8 KINETIS_MUX('B',8,6) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPI2C0_SCLS_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define FXIO_D5_PTB9 KINETIS_MUX('B',9,6) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define FTM0_CH0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPI2C0_SDAS_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FXIO_D0_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define FTM0_CH1_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPI2C0_HREQ_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FXIO_D1_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define SCI1_RX_PTB12 KINETIS_MUX('B',12,6) /* PTB_12 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define SCI1_TX_PTB13 KINETIS_MUX('B',13,6) /* PTB_13 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define FTM0_CH2_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define LPSPI1_SCK_PTB14 KINETIS_MUX('B',14,3) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define FTM0_CH3_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define LPSPI1_SIN_PTB15 KINETIS_MUX('B',15,3) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define FTM0_CH4_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPSPI1_SOUT_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define FTM0_CH5_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPSPI1_PCS3_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define ADC0_SE10_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define SCI0_RX_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define ADC0_SE8_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define SCI0_TX_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE15_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define FXIO_D6_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define ADC0_SE7_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define FXIO_D7_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_RX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define TSI0_CH8_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPI2C1_HREQ_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define ADC0_SE24_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define ADC0_SE22_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define LPSPI0_SCK_PTC10 KINETIS_MUX('C',10,5) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LPSPI0_SIN_PTC11 KINETIS_MUX('C',11,5) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define LPSPI0_SOUT_PTC12 KINETIS_MUX('C',12,5) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define LPSPI0_PCS0_PTC13 KINETIS_MUX('C',13,5) /* PTC_13 */ +#define ADC0_SE17_PTC14 KINETIS_MUX('C',14,0) /* PTC_14 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define SCI0_RX_PTC14 KINETIS_MUX('C',14,4) /* PTC_14 */ +#define ADC0_SE16_PTC15 KINETIS_MUX('C',15,0) /* PTC_15 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define SCI0_TX_PTC15 KINETIS_MUX('C',15,4) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPI2C1_SDAS_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define SCI1_RX_PTC16 KINETIS_MUX('C',16,6) /* PTC_16 */ +#define ADC0_SE12_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPI2C1_SCLS_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define SCI1_TX_PTC17 KINETIS_MUX('C',17,6) /* PTC_17 */ +#define TSI0_CH12_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI1_SCK_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TSI0_CH11_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI1_SIN_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI1_SOUT_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPI2C0_SDA_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI1_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPI2C0_SCL_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define ADC0_SE9_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FXIO_D3_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE11_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define ADC0_SE13_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define FTM0_CH7_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define LPI2C1_SDA_PTD8 KINETIS_MUX('D',8,3) /* PTD_8 */ +#define LPSPI0_PCS1_PTD8 KINETIS_MUX('D',8,5) /* PTD_8 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define LPI2C1_SCL_PTD9 KINETIS_MUX('D',9,3) /* PTD_9 */ +#define FXIO_D2_PTD9 KINETIS_MUX('D',9,6) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FTM2_CH0_PTD10 KINETIS_MUX('D',10,2) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define FTM2_CH1_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define LPUART2_CTS_PTD11 KINETIS_MUX('D',11,6) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define FTM2_CH2_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define LPI2C1_HREQ_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define LPUART2_RTS_PTD12 KINETIS_MUX('D',12,6) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define LPUART1_RX_PTD13 KINETIS_MUX('D',13,3) /* PTD_13 */ +#define RTC_CLKOUT_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define LPUART1_TX_PTD14 KINETIS_MUX('D',14,3) /* PTD_14 */ +#define CLKOUT_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define TSI0_CH20_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define ADC0_SE2_PTD15 KINETIS_MUX('D',15,0) /* PTD_15 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define TSI0_CH19_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define ADC0_SE4_PTD16 KINETIS_MUX('D',16,0) /* PTD_16 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTD17 KINETIS_MUX('D',17,1) /* PTD_17 */ +#define FTM0_FLT2_PTD17 KINETIS_MUX('D',17,2) /* PTD_17 */ +#define LPUART2_RX_PTD17 KINETIS_MUX('D',17,3) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define TRGMUX_OUT2_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17_PTD17 KINETIS_MUX('D',17,7) /* PTD_17 */ +#define TSI0_CH7_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define TSI0_CH6_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define TSI0_CH1_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define TSI0_CH18_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define ADC0_SE6_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TSI0_CH17_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define TSI0_CH16_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define TSI0_CH0_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ADC0_SE1_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define TSI0_CH22_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define TSI0_CH21_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define ADC0_SE0_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define TSI0_CH10_PTE10 KINETIS_MUX('E',10,0) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TSI0_CH9_PTE11 KINETIS_MUX('E',11,0) /* PTE_11 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define FTM0_FLT3_PTE12 KINETIS_MUX('E',12,2) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define TRGMUX_OUT3_PTE12 KINETIS_MUX('E',12,7) /* PTE_12 */ +#define TSI0_CH15_PTE13 KINETIS_MUX('E',13,0) /* PTE_13 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define TRGMUX_OUT5_PTE13 KINETIS_MUX('E',13,7) /* PTE_13 */ +#define PTE14 KINETIS_MUX('E',14,1) /* PTE_14 */ +#define FTM0_FLT1_PTE14 KINETIS_MUX('E',14,2) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define TRGMUX_OUT4_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14_PTE14 KINETIS_MUX('E',14,7) /* PTE_14 */ +#define TSI0_CH14_PTE15 KINETIS_MUX('E',15,0) /* PTE_15 */ +#define PTE15 KINETIS_MUX('E',15,1) /* PTE_15 */ +#define FXIO_D2_PTE15 KINETIS_MUX('E',15,6) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TSI0_CH13_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define FXIO_D3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#endif diff --git a/dts/nxp/kinetis/MKE14Z128VLH7-pinctrl.h b/dts/nxp/kinetis/MKE14Z128VLH7-pinctrl.h new file mode 100644 index 000000000..9572a0d63 --- /dev/null +++ b/dts/nxp/kinetis/MKE14Z128VLH7-pinctrl.h @@ -0,0 +1,280 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE14Z128VLH7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE14Z128VLH7_ +#define _ZEPHYR_DTS_BINDING_MKE14Z128VLH7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define ADC1_SE0_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define ADC1_SE1_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ACMP1_IN0_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define ADC0_SE2_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPSPI1_PCS1_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define ACMP1_IN1_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPI2C1_SDAS_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPI2C1_SCLS_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ACMP1_IN2_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ACMP1_OUT_PTB5 KINETIS_MUX('B',5,7) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define ADC1_SE7_PTB12 KINETIS_MUX('B',12,0) /* PTB_12 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define ADC1_SE8_PTB13 KINETIS_MUX('B',13,0) /* PTB_13 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define ACMP1_IN4_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ACMP1_IN3_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define XTAL32_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define EXTAL32_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPI2C1_HREQ_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define FTM2_QD_PHB_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define ADC1_SE4_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define ADC1_SE5_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC0_SE12_PTC14 KINETIS_MUX('C',14,0) /* PTC_14 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define ADC0_SE13_PTC15 KINETIS_MUX('C',15,0) /* PTC_15 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define FTM1_FLT2_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define LPI2C1_SDAS_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define ADC0_SE15_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define FTM1_FLT3_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define LPI2C1_SCLS_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI1_SCK_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI1_SIN_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define ADC1_SE2_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI1_SOUT_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define ADC1_SE3_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI1_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define ADC1_SE6_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define FTM2_FLT2_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define FTM2_FLT3_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define FTM1_FLT2_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define ADC1_SE10_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_QD_PHB_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_QD_PHA_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define ADC1_SE11_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define DAC0_OUT_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE14Z128VLL7-pinctrl.h b/dts/nxp/kinetis/MKE14Z128VLL7-pinctrl.h new file mode 100644 index 000000000..505f45af3 --- /dev/null +++ b/dts/nxp/kinetis/MKE14Z128VLL7-pinctrl.h @@ -0,0 +1,361 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE14Z128VLL7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE14Z128VLL7_ +#define _ZEPHYR_DTS_BINDING_MKE14Z128VLL7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define ADC1_SE0_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define ADC1_SE1_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ACMP1_IN0_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define ADC0_SE2_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPSPI1_PCS1_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define ACMP1_IN1_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FXIO_D6_PTA8 KINETIS_MUX('A',8,4) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FXIO_D7_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define FTM1_FLT3_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPI2C1_SDAS_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPI2C1_SCLS_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define FTM0_FLT0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define EWM_IN_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define BUSOUT_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define FTM1_CH2_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPSPI0_PCS3_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define FTM1_CH3_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPSPI1_PCS2_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define FTM0_CH6_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM_OUT_b_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ACMP1_IN2_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ACMP1_OUT_PTB5 KINETIS_MUX('B',5,7) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPI2C0_SCLS_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define LPI2C0_SDAS_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define LPI2C0_HREQ_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define ADC1_SE7_PTB12 KINETIS_MUX('B',12,0) /* PTB_12 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define ADC1_SE8_PTB13 KINETIS_MUX('B',13,0) /* PTB_13 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define ADC1_SE9_PTB14 KINETIS_MUX('B',14,0) /* PTB_14 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define FTM0_CH2_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define LPSPI1_SCK_PTB14 KINETIS_MUX('B',14,3) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define FTM0_CH3_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define LPSPI1_SIN_PTB15 KINETIS_MUX('B',15,3) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define FTM0_CH4_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPSPI1_SOUT_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define FTM0_CH5_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPSPI1_PCS3_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define ACMP1_IN4_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ACMP1_IN3_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define XTAL32_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define EXTAL32_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPI2C1_HREQ_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define FTM2_QD_PHB_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define ADC1_SE4_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define ADC1_SE5_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define ADC0_SE12_PTC14 KINETIS_MUX('C',14,0) /* PTC_14 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define ADC0_SE13_PTC15 KINETIS_MUX('C',15,0) /* PTC_15 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define FTM1_FLT2_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define LPI2C1_SDAS_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define ADC0_SE15_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define FTM1_FLT3_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define LPI2C1_SCLS_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI1_SCK_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI1_SIN_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define ADC1_SE2_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI1_SOUT_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define ADC1_SE3_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI1_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define ADC1_SE6_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define FTM2_FLT2_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define FTM2_FLT3_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define LPI2C1_SDA_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define FTM2_FLT2_PTD8 KINETIS_MUX('D',8,4) /* PTD_8 */ +#define ACMP1_IN5_PTD9 KINETIS_MUX('D',9,0) /* PTD_9 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define LPI2C1_SCL_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define FTM2_FLT3_PTD9 KINETIS_MUX('D',9,4) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FTM2_CH0_PTD10 KINETIS_MUX('D',10,2) /* PTD_10 */ +#define FTM2_QD_PHB_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define FTM2_CH1_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define FTM2_QD_PHA_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define LPUART2_CTS_PTD11 KINETIS_MUX('D',11,6) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define FTM2_CH2_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define LPI2C1_HREQ_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define LPUART2_RTS_PTD12 KINETIS_MUX('D',12,6) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define RTC_CLKOUT_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define CLKOUT_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTD17 KINETIS_MUX('D',17,1) /* PTD_17 */ +#define FTM0_FLT2_PTD17 KINETIS_MUX('D',17,2) /* PTD_17 */ +#define LPUART2_RX_PTD17 KINETIS_MUX('D',17,3) /* PTD_17 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define FTM1_FLT2_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define ADC1_SE10_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_QD_PHB_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_QD_PHA_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define ADC1_SE11_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define DAC0_OUT_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define FTM0_FLT3_PTE12 KINETIS_MUX('E',12,2) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define PTE14 KINETIS_MUX('E',14,1) /* PTE_14 */ +#define FTM0_FLT1_PTE14 KINETIS_MUX('E',14,2) /* PTE_14 */ +#define PTE15 KINETIS_MUX('E',15,1) /* PTE_15 */ +#define FXIO_D2_PTE15 KINETIS_MUX('E',15,6) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define FXIO_D3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#endif diff --git a/dts/nxp/kinetis/MKE14Z256VLH7-pinctrl.h b/dts/nxp/kinetis/MKE14Z256VLH7-pinctrl.h new file mode 100644 index 000000000..f973f13be --- /dev/null +++ b/dts/nxp/kinetis/MKE14Z256VLH7-pinctrl.h @@ -0,0 +1,280 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE14Z256VLH7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE14Z256VLH7_ +#define _ZEPHYR_DTS_BINDING_MKE14Z256VLH7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define ADC1_SE0_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define ADC1_SE1_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ACMP1_IN0_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define ADC0_SE2_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPSPI1_PCS1_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define ACMP1_IN1_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPI2C1_SDAS_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPI2C1_SCLS_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ACMP1_IN2_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ACMP1_OUT_PTB5 KINETIS_MUX('B',5,7) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define ADC1_SE7_PTB12 KINETIS_MUX('B',12,0) /* PTB_12 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define ADC1_SE8_PTB13 KINETIS_MUX('B',13,0) /* PTB_13 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ACMP1_IN4_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ACMP1_IN3_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define XTAL32_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define EXTAL32_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPI2C1_HREQ_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define FTM2_QD_PHB_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define ADC1_SE4_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define ADC1_SE5_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC0_SE12_PTC14 KINETIS_MUX('C',14,0) /* PTC_14 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define ADC0_SE13_PTC15 KINETIS_MUX('C',15,0) /* PTC_15 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define FTM1_FLT2_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define LPI2C1_SDAS_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define ADC0_SE15_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define FTM1_FLT3_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define LPI2C1_SCLS_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI1_SCK_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI1_SIN_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define ADC1_SE2_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI1_SOUT_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define ADC1_SE3_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI1_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define ADC1_SE6_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define FTM2_FLT2_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define FTM2_FLT3_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define FTM1_FLT2_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define ADC1_SE10_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_QD_PHB_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_QD_PHA_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define ADC1_SE11_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define DAC0_OUT_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE14Z256VLL7-pinctrl.h b/dts/nxp/kinetis/MKE14Z256VLL7-pinctrl.h new file mode 100644 index 000000000..4a3db6818 --- /dev/null +++ b/dts/nxp/kinetis/MKE14Z256VLL7-pinctrl.h @@ -0,0 +1,361 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE14Z256VLL7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE14Z256VLL7_ +#define _ZEPHYR_DTS_BINDING_MKE14Z256VLL7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define ADC1_SE0_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define ADC1_SE1_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ACMP1_IN0_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define ADC0_SE2_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPSPI1_PCS1_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define ACMP1_IN1_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FXIO_D6_PTA8 KINETIS_MUX('A',8,4) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FXIO_D7_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define FTM1_FLT3_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPI2C1_SDAS_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPI2C1_SCLS_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define FTM0_FLT0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define EWM_IN_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define BUSOUT_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define FTM1_CH2_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPSPI0_PCS3_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define FTM1_CH3_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPSPI1_PCS2_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define FTM0_CH6_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM_OUT_b_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ACMP1_IN2_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ACMP1_OUT_PTB5 KINETIS_MUX('B',5,7) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPI2C0_SCLS_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define LPI2C0_SDAS_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define LPI2C0_HREQ_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define ADC1_SE7_PTB12 KINETIS_MUX('B',12,0) /* PTB_12 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define ADC1_SE8_PTB13 KINETIS_MUX('B',13,0) /* PTB_13 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define ADC1_SE9_PTB14 KINETIS_MUX('B',14,0) /* PTB_14 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define FTM0_CH2_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define LPSPI1_SCK_PTB14 KINETIS_MUX('B',14,3) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define FTM0_CH3_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define LPSPI1_SIN_PTB15 KINETIS_MUX('B',15,3) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define FTM0_CH4_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPSPI1_SOUT_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define FTM0_CH5_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPSPI1_PCS3_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ACMP1_IN4_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ACMP1_IN3_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define XTAL32_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define EXTAL32_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPI2C1_HREQ_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define FTM2_QD_PHB_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define ADC1_SE4_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define ADC1_SE5_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define ADC0_SE12_PTC14 KINETIS_MUX('C',14,0) /* PTC_14 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define ADC0_SE13_PTC15 KINETIS_MUX('C',15,0) /* PTC_15 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define FTM1_FLT2_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define LPI2C1_SDAS_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define ADC0_SE15_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define FTM1_FLT3_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define LPI2C1_SCLS_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI1_SCK_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI1_SIN_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define ADC1_SE2_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI1_SOUT_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define ADC1_SE3_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI1_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define ADC1_SE6_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define FTM2_FLT2_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define FTM2_FLT3_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define LPI2C1_SDA_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define FTM2_FLT2_PTD8 KINETIS_MUX('D',8,4) /* PTD_8 */ +#define ACMP1_IN5_PTD9 KINETIS_MUX('D',9,0) /* PTD_9 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define LPI2C1_SCL_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define FTM2_FLT3_PTD9 KINETIS_MUX('D',9,4) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FTM2_CH0_PTD10 KINETIS_MUX('D',10,2) /* PTD_10 */ +#define FTM2_QD_PHB_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define FTM2_CH1_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define FTM2_QD_PHA_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define LPUART2_CTS_PTD11 KINETIS_MUX('D',11,6) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define FTM2_CH2_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define LPI2C1_HREQ_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define LPUART2_RTS_PTD12 KINETIS_MUX('D',12,6) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define RTC_CLKOUT_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define CLKOUT_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTD17 KINETIS_MUX('D',17,1) /* PTD_17 */ +#define FTM0_FLT2_PTD17 KINETIS_MUX('D',17,2) /* PTD_17 */ +#define LPUART2_RX_PTD17 KINETIS_MUX('D',17,3) /* PTD_17 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define FTM1_FLT2_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define ADC1_SE10_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_QD_PHB_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_QD_PHA_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define ADC1_SE11_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define DAC0_OUT_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define FTM0_FLT3_PTE12 KINETIS_MUX('E',12,2) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define PTE14 KINETIS_MUX('E',14,1) /* PTE_14 */ +#define FTM0_FLT1_PTE14 KINETIS_MUX('E',14,2) /* PTE_14 */ +#define PTE15 KINETIS_MUX('E',15,1) /* PTE_15 */ +#define FXIO_D2_PTE15 KINETIS_MUX('E',15,6) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define FXIO_D3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#endif diff --git a/dts/nxp/kinetis/MKE14Z32VFP4-pinctrl.h b/dts/nxp/kinetis/MKE14Z32VFP4-pinctrl.h new file mode 100644 index 000000000..457c461b5 --- /dev/null +++ b/dts/nxp/kinetis/MKE14Z32VFP4-pinctrl.h @@ -0,0 +1,155 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE14Z32VFP4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE14Z32VFP4_ +#define _ZEPHYR_DTS_BINDING_MKE14Z32VFP4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE14Z32VLD4-pinctrl.h b/dts/nxp/kinetis/MKE14Z32VLD4-pinctrl.h new file mode 100644 index 000000000..3fe95b26b --- /dev/null +++ b/dts/nxp/kinetis/MKE14Z32VLD4-pinctrl.h @@ -0,0 +1,163 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE14Z32VLD4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE14Z32VLD4_ +#define _ZEPHYR_DTS_BINDING_MKE14Z32VLD4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ADC0_SE2_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#endif diff --git a/dts/nxp/kinetis/MKE14Z32VLF4-pinctrl.h b/dts/nxp/kinetis/MKE14Z32VLF4-pinctrl.h new file mode 100644 index 000000000..600a80cb4 --- /dev/null +++ b/dts/nxp/kinetis/MKE14Z32VLF4-pinctrl.h @@ -0,0 +1,173 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE14Z32VLF4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE14Z32VLF4_ +#define _ZEPHYR_DTS_BINDING_MKE14Z32VLF4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ADC0_SE2_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE14Z64VFP4-pinctrl.h b/dts/nxp/kinetis/MKE14Z64VFP4-pinctrl.h new file mode 100644 index 000000000..4c46bf292 --- /dev/null +++ b/dts/nxp/kinetis/MKE14Z64VFP4-pinctrl.h @@ -0,0 +1,155 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE14Z64VFP4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE14Z64VFP4_ +#define _ZEPHYR_DTS_BINDING_MKE14Z64VFP4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE14Z64VLD4-pinctrl.h b/dts/nxp/kinetis/MKE14Z64VLD4-pinctrl.h new file mode 100644 index 000000000..2bb02ed1e --- /dev/null +++ b/dts/nxp/kinetis/MKE14Z64VLD4-pinctrl.h @@ -0,0 +1,163 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE14Z64VLD4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE14Z64VLD4_ +#define _ZEPHYR_DTS_BINDING_MKE14Z64VLD4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ADC0_SE2_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#endif diff --git a/dts/nxp/kinetis/MKE14Z64VLF4-pinctrl.h b/dts/nxp/kinetis/MKE14Z64VLF4-pinctrl.h new file mode 100644 index 000000000..51ce9da84 --- /dev/null +++ b/dts/nxp/kinetis/MKE14Z64VLF4-pinctrl.h @@ -0,0 +1,173 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE14Z64VLF4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE14Z64VLF4_ +#define _ZEPHYR_DTS_BINDING_MKE14Z64VLF4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ADC0_SE2_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LPSPI0_PCS3_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define LPUART2_CTS_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE15Z128VLH7-pinctrl.h b/dts/nxp/kinetis/MKE15Z128VLH7-pinctrl.h new file mode 100644 index 000000000..b686d869c --- /dev/null +++ b/dts/nxp/kinetis/MKE15Z128VLH7-pinctrl.h @@ -0,0 +1,305 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE15Z128VLH7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE15Z128VLH7_ +#define _ZEPHYR_DTS_BINDING_MKE15Z128VLH7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define TSI0_CH17_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define TSI0_CH18_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define ADC1_SE0_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define ADC1_SE1_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ACMP1_IN0_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define ADC0_SE2_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPSPI1_PCS1_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define ACMP1_IN1_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPI2C1_SDAS_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPI2C1_SCLS_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define TSI0_CH20_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define TSI0_CH21_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ACMP1_IN2_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define TSI0_CH8_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define TSI0_CH9_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ACMP1_OUT_PTB5 KINETIS_MUX('B',5,7) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define ADC1_SE7_PTB12 KINETIS_MUX('B',12,0) /* PTB_12 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define ADC1_SE8_PTB13 KINETIS_MUX('B',13,0) /* PTB_13 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH22_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ACMP1_IN4_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ACMP1_IN3_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define TSI0_CH23_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define XTAL32_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define EXTAL32_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define TSI0_CH12_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPI2C1_HREQ_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define FTM2_QD_PHB_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define ADC1_SE4_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define TSI0_CH15_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define ADC1_SE5_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define TSI0_CH16_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC0_SE12_PTC14 KINETIS_MUX('C',14,0) /* PTC_14 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define ADC0_SE13_PTC15 KINETIS_MUX('C',15,0) /* PTC_15 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define FTM1_FLT2_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define LPI2C1_SDAS_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define ADC0_SE15_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define FTM1_FLT3_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define LPI2C1_SCLS_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define TSI0_CH4_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI1_SCK_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TSI0_CH5_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI1_SIN_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define ADC1_SE2_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI1_SOUT_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define ADC1_SE3_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI1_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define ADC1_SE6_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define TSI0_CH6_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TSI0_CH7_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define FTM2_FLT2_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define TSI0_CH10_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define FTM2_FLT3_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define TSI0_CH13_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define FTM1_FLT2_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define TSI0_CH14_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define ADC1_SE10_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define TSI0_CH19_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define TSI0_CH24_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TSI0_CH1_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_QD_PHB_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define TSI0_CH0_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_QD_PHA_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define ADC1_SE11_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define TSI0_CH11_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define DAC0_OUT_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define TSI0_CH2_PTE10 KINETIS_MUX('E',10,0) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TSI0_CH3_PTE11 KINETIS_MUX('E',11,0) /* PTE_11 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#endif diff --git a/dts/nxp/kinetis/MKE15Z128VLL7-pinctrl.h b/dts/nxp/kinetis/MKE15Z128VLL7-pinctrl.h new file mode 100644 index 000000000..6fbacc7d1 --- /dev/null +++ b/dts/nxp/kinetis/MKE15Z128VLL7-pinctrl.h @@ -0,0 +1,386 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKE15Z128VLL7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKE15Z128VLL7_ +#define _ZEPHYR_DTS_BINDING_MKE15Z128VLL7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define ADC0_SE0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define TSI0_CH17_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ACMP0_IN0_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define FTM2_CH1_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPI2C0_SCLS_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define FXIO_D2_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define FTM2_QD_PHA_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define LPUART0_CTS_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define TRGMUX_OUT3_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define ACMP0_IN1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define ADC0_SE1_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define TSI0_CH18_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPI2C0_SDAS_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define FXIO_D3_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FTM1_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define LPUART0_RTS_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define TRGMUX_OUT0_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define ADC1_SE0_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPI2C0_SDA_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EWM_OUT_b_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define LPUART0_RX_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define ADC1_SE1_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LPI2C0_SCL_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define EWM_IN_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,6) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define ACMP0_OUT_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define EWM_OUT_b_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define SWD_DIO_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TCLK1_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define RESET_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define ACMP1_IN0_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define ADC0_SE2_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define FTM0_FLT1_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LPSPI1_PCS1_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define LPUART1_CTS_PTA6 KINETIS_MUX('A',6,6) /* PTA_6 */ +#define ADC0_SE3_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define ACMP1_IN1_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define FTM0_FLT2_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define RTC_CLKIN_PTA7 KINETIS_MUX('A',7,4) /* PTA_7 */ +#define LPUART1_RTS_PTA7 KINETIS_MUX('A',7,6) /* PTA_7 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define FXIO_D6_PTA8 KINETIS_MUX('A',8,4) /* PTA_8 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define FXIO_D7_PTA9 KINETIS_MUX('A',9,4) /* PTA_9 */ +#define FTM1_FLT3_PTA9 KINETIS_MUX('A',9,6) /* PTA_9 */ +#define PTA10 KINETIS_MUX('A',10,1) /* PTA_10 */ +#define LPUART0_TX_PTA10 KINETIS_MUX('A',10,3) /* PTA_10 */ +#define FXIO_D0_PTA10 KINETIS_MUX('A',10,4) /* PTA_10 */ +#define PTA11 KINETIS_MUX('A',11,1) /* PTA_11 */ +#define LPUART0_RX_PTA11 KINETIS_MUX('A',11,3) /* PTA_11 */ +#define FXIO_D1_PTA11 KINETIS_MUX('A',11,4) /* PTA_11 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPI2C1_SDAS_PTA12 KINETIS_MUX('A',12,4) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define LPI2C1_SCLS_PTA13 KINETIS_MUX('A',13,4) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define FTM0_FLT0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define EWM_IN_PTA14 KINETIS_MUX('A',14,4) /* PTA_14 */ +#define BUSOUT_PTA14 KINETIS_MUX('A',14,7) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define FTM1_CH2_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define LPSPI0_PCS3_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define FTM1_CH3_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define LPSPI1_PCS2_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define FTM0_CH6_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM_OUT_b_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define ADC0_SE4_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPUART0_RX_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define LPSPI0_PCS0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LPTMR0_ALT3_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define PWT_IN3_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE5_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPSPI0_SOUT_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define TCLK0_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define TSI0_CH20_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE6_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define FTM1_CH0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPSPI0_SCK_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM1_QD_PHB_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define TRGMUX_IN3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define TSI0_CH21_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define ADC0_SE7_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define FTM1_CH1_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPSPI0_SIN_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM1_QD_PHA_PTB3 KINETIS_MUX('B',3,4) /* PTB_3 */ +#define TRGMUX_IN2_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define ACMP1_IN2_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define TSI0_CH8_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define FTM0_CH4_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPSPI0_SOUT_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define TRGMUX_IN1_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define TSI0_CH9_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define FTM0_CH5_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPSPI0_PCS1_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define TRGMUX_IN0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define ACMP1_OUT_PTB5 KINETIS_MUX('B',5,7) /* PTB_5 */ +#define XTAL_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LPI2C0_SDA_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define EXTAL_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define LPI2C0_SCL_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define PTB8 KINETIS_MUX('B',8,1) /* PTB_8 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define LPI2C0_SCLS_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define LPI2C0_SDAS_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define LPI2C0_HREQ_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define ADC1_SE7_PTB12 KINETIS_MUX('B',12,0) /* PTB_12 */ +#define PTB12 KINETIS_MUX('B',12,1) /* PTB_12 */ +#define FTM0_CH0_PTB12 KINETIS_MUX('B',12,2) /* PTB_12 */ +#define ADC1_SE8_PTB13 KINETIS_MUX('B',13,0) /* PTB_13 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define FTM0_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define ADC1_SE9_PTB14 KINETIS_MUX('B',14,0) /* PTB_14 */ +#define PTB14 KINETIS_MUX('B',14,1) /* PTB_14 */ +#define FTM0_CH2_PTB14 KINETIS_MUX('B',14,2) /* PTB_14 */ +#define LPSPI1_SCK_PTB14 KINETIS_MUX('B',14,3) /* PTB_14 */ +#define PTB15 KINETIS_MUX('B',15,1) /* PTB_15 */ +#define FTM0_CH3_PTB15 KINETIS_MUX('B',15,2) /* PTB_15 */ +#define LPSPI1_SIN_PTB15 KINETIS_MUX('B',15,3) /* PTB_15 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define FTM0_CH4_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPSPI1_SOUT_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define FTM0_CH5_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPSPI1_PCS3_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define ADC0_SE8_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define TSI0_CH22_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ACMP1_IN4_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define FTM0_CH0_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define ACMP1_IN3_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE9_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define TSI0_CH23_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define FTM0_CH1_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define ACMP0_IN5_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define XTAL32_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE10_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define FTM0_CH2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define EXTAL32_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ACMP0_IN4_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define ADC0_SE11_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define FTM0_CH3_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define ACMP0_IN2_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define FTM1_CH0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define RTC_CLKOUT_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define EWM_IN_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define FTM1_QD_PHB_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define SWD_CLK_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define TSI0_CH12_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define FTM2_CH0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define RTC_CLKOUT_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define LPI2C1_HREQ_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define FTM2_QD_PHB_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define ADC1_SE4_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define TSI0_CH15_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPUART1_RX_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define ADC1_SE5_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define TSI0_CH16_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define LPUART1_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define LPUART1_RX_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define LPUART0_CTS_PTC8 KINETIS_MUX('C',8,6) /* PTC_8 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define LPUART1_TX_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define LPUART0_RTS_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define ADC0_SE12_PTC14 KINETIS_MUX('C',14,0) /* PTC_14 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define FTM1_CH2_PTC14 KINETIS_MUX('C',14,2) /* PTC_14 */ +#define ADC0_SE13_PTC15 KINETIS_MUX('C',15,0) /* PTC_15 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define FTM1_CH3_PTC15 KINETIS_MUX('C',15,2) /* PTC_15 */ +#define ADC0_SE14_PTC16 KINETIS_MUX('C',16,0) /* PTC_16 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define FTM1_FLT2_PTC16 KINETIS_MUX('C',16,2) /* PTC_16 */ +#define LPI2C1_SDAS_PTC16 KINETIS_MUX('C',16,4) /* PTC_16 */ +#define ADC0_SE15_PTC17 KINETIS_MUX('C',17,0) /* PTC_17 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define FTM1_FLT3_PTC17 KINETIS_MUX('C',17,2) /* PTC_17 */ +#define LPI2C1_SCLS_PTC17 KINETIS_MUX('C',17,4) /* PTC_17 */ +#define TSI0_CH4_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define FTM0_CH2_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define LPSPI1_SCK_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM2_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TRGMUX_OUT1_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define TSI0_CH5_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define FTM0_CH3_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define LPSPI1_SIN_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM2_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define TRGMUX_OUT2_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define ADC1_SE2_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPSPI1_SOUT_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FXIO_D4_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define TRGMUX_IN5_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define TRGMUX_IN5_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define ADC1_SE3_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPSPI1_PCS0_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FXIO_D5_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define TRGMUX_IN4_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define TRGMUX_IN4_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define NMI_b_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define ADC1_SE6_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define FTM0_FLT3_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define TSI0_CH6_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define FTM2_CH3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define LPTMR0_ALT2_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define PWT_IN2_PTD5 KINETIS_MUX('D',5,5) /* PTD_5 */ +#define TRGMUX_IN7_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TRGMUX_IN7_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define TSI0_CH7_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPUART2_RX_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define FTM2_FLT2_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define TSI0_CH10_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define LPUART2_TX_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define FTM2_FLT3_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define PTD8 KINETIS_MUX('D',8,1) /* PTD_8 */ +#define LPI2C1_SDA_PTD8 KINETIS_MUX('D',8,2) /* PTD_8 */ +#define FTM2_FLT2_PTD8 KINETIS_MUX('D',8,4) /* PTD_8 */ +#define ACMP1_IN5_PTD9 KINETIS_MUX('D',9,0) /* PTD_9 */ +#define PTD9 KINETIS_MUX('D',9,1) /* PTD_9 */ +#define LPI2C1_SCL_PTD9 KINETIS_MUX('D',9,2) /* PTD_9 */ +#define FTM2_FLT3_PTD9 KINETIS_MUX('D',9,4) /* PTD_9 */ +#define PTD10 KINETIS_MUX('D',10,1) /* PTD_10 */ +#define FTM2_CH0_PTD10 KINETIS_MUX('D',10,2) /* PTD_10 */ +#define FTM2_QD_PHB_PTD10 KINETIS_MUX('D',10,3) /* PTD_10 */ +#define PTD11 KINETIS_MUX('D',11,1) /* PTD_11 */ +#define FTM2_CH1_PTD11 KINETIS_MUX('D',11,2) /* PTD_11 */ +#define FTM2_QD_PHA_PTD11 KINETIS_MUX('D',11,3) /* PTD_11 */ +#define LPUART2_CTS_PTD11 KINETIS_MUX('D',11,6) /* PTD_11 */ +#define PTD12 KINETIS_MUX('D',12,1) /* PTD_12 */ +#define FTM2_CH2_PTD12 KINETIS_MUX('D',12,2) /* PTD_12 */ +#define LPI2C1_HREQ_PTD12 KINETIS_MUX('D',12,3) /* PTD_12 */ +#define LPUART2_RTS_PTD12 KINETIS_MUX('D',12,6) /* PTD_12 */ +#define PTD13 KINETIS_MUX('D',13,1) /* PTD_13 */ +#define RTC_CLKOUT_PTD13 KINETIS_MUX('D',13,7) /* PTD_13 */ +#define PTD14 KINETIS_MUX('D',14,1) /* PTD_14 */ +#define CLKOUT_PTD14 KINETIS_MUX('D',14,7) /* PTD_14 */ +#define PTD15 KINETIS_MUX('D',15,1) /* PTD_15 */ +#define FTM0_CH0_PTD15 KINETIS_MUX('D',15,2) /* PTD_15 */ +#define PTD16 KINETIS_MUX('D',16,1) /* PTD_16 */ +#define FTM0_CH1_PTD16 KINETIS_MUX('D',16,2) /* PTD_16 */ +#define PTD17 KINETIS_MUX('D',17,1) /* PTD_17 */ +#define FTM0_FLT2_PTD17 KINETIS_MUX('D',17,2) /* PTD_17 */ +#define LPUART2_RX_PTD17 KINETIS_MUX('D',17,3) /* PTD_17 */ +#define TSI0_CH13_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define LPSPI0_SCK_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define TCLK1_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define LPI2C1_SDA_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define FTM1_FLT2_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define TSI0_CH14_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LPSPI0_SIN_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPI2C0_HREQ_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define LPI2C1_SCL_PTE1 KINETIS_MUX('E',1,4) /* PTE_1 */ +#define ADC1_SE10_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define TSI0_CH19_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LPSPI0_SOUT_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define LPTMR0_ALT3_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define PWT_IN3_PTE2 KINETIS_MUX('E',2,5) /* PTE_2 */ +#define LPUART1_CTS_PTE2 KINETIS_MUX('E',2,6) /* PTE_2 */ +#define TSI0_CH24_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define FTM0_FLT0/TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define FTM0_FLT0_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define LPUART2_RTS_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define TRGMUX_IN6_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TRGMUX_IN6_PTE3 KINETIS_MUX('E',3,6) /* PTE_3 */ +#define TSI0_CH1_PTE4 KINETIS_MUX('E',4,0) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define BUSOUT_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define FTM2_QD_PHB_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define FTM2_CH2_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define FXIO_D6_PTE4 KINETIS_MUX('E',4,6) /* PTE_4 */ +#define EWM_OUT_b_PTE4 KINETIS_MUX('E',4,7) /* PTE_4 */ +#define TSI0_CH0_PTE5 KINETIS_MUX('E',5,0) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define TCLK2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define FTM2_QD_PHA_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define FTM2_CH3_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define FXIO_D7_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define EWM_IN_PTE5 KINETIS_MUX('E',5,7) /* PTE_5 */ +#define ADC1_SE11_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LPSPI0_PCS2_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART1_RTS_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define FTM0_CH7_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define TSI0_CH11_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define ACMP0_IN3_PTE8 KINETIS_MUX('E',8,0) /* PTE_8 */ +#define PTE8 KINETIS_MUX('E',8,1) /* PTE_8 */ +#define FTM0_CH6_PTE8 KINETIS_MUX('E',8,2) /* PTE_8 */ +#define DAC0_OUT_PTE9 KINETIS_MUX('E',9,0) /* PTE_9 */ +#define PTE9 KINETIS_MUX('E',9,1) /* PTE_9 */ +#define FTM0_CH7_PTE9 KINETIS_MUX('E',9,2) /* PTE_9 */ +#define LPUART2_CTS_PTE9 KINETIS_MUX('E',9,3) /* PTE_9 */ +#define TSI0_CH2_PTE10 KINETIS_MUX('E',10,0) /* PTE_10 */ +#define PTE10 KINETIS_MUX('E',10,1) /* PTE_10 */ +#define CLKOUT_PTE10 KINETIS_MUX('E',10,2) /* PTE_10 */ +#define FXIO_D4_PTE10 KINETIS_MUX('E',10,6) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TRGMUX_OUT4_PTE10 KINETIS_MUX('E',10,7) /* PTE_10 */ +#define TSI0_CH3_PTE11 KINETIS_MUX('E',11,0) /* PTE_11 */ +#define PTE11 KINETIS_MUX('E',11,1) /* PTE_11 */ +#define PWT_IN1_PTE11 KINETIS_MUX('E',11,2) /* PTE_11 */ +#define LPTMR0_ALT1_PTE11 KINETIS_MUX('E',11,3) /* PTE_11 */ +#define FXIO_D5_PTE11 KINETIS_MUX('E',11,6) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define TRGMUX_OUT5_PTE11 KINETIS_MUX('E',11,7) /* PTE_11 */ +#define PTE12 KINETIS_MUX('E',12,1) /* PTE_12 */ +#define FTM0_FLT3_PTE12 KINETIS_MUX('E',12,2) /* PTE_12 */ +#define LPUART2_TX_PTE12 KINETIS_MUX('E',12,3) /* PTE_12 */ +#define PTE13 KINETIS_MUX('E',13,1) /* PTE_13 */ +#define PTE14 KINETIS_MUX('E',14,1) /* PTE_14 */ +#define FTM0_FLT1_PTE14 KINETIS_MUX('E',14,2) /* PTE_14 */ +#define PTE15 KINETIS_MUX('E',15,1) /* PTE_15 */ +#define FXIO_D2_PTE15 KINETIS_MUX('E',15,6) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define TRGMUX_OUT6_PTE15 KINETIS_MUX('E',15,7) /* PTE_15 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define FXIO_D3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#define TRGMUX_OUT7_PTE16 KINETIS_MUX('E',16,7) /* PTE_16 */ +#endif diff --git a/dts/nxp/kinetis/MKL27Z256VFM4-pinctrl.h b/dts/nxp/kinetis/MKL27Z256VFM4-pinctrl.h new file mode 100644 index 000000000..00ac302d8 --- /dev/null +++ b/dts/nxp/kinetis/MKL27Z256VFM4-pinctrl.h @@ -0,0 +1,138 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKL27Z256VFM4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKL27Z256VFM4_ +#define _ZEPHYR_DTS_BINDING_MKL27Z256VFM4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/MKL27Z256VFT4-pinctrl.h b/dts/nxp/kinetis/MKL27Z256VFT4-pinctrl.h new file mode 100644 index 000000000..f17510eb3 --- /dev/null +++ b/dts/nxp/kinetis/MKL27Z256VFT4-pinctrl.h @@ -0,0 +1,199 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKL27Z256VFT4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKL27Z256VFT4_ +#define _ZEPHYR_DTS_BINDING_MKL27Z256VFT4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD0_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/MKL27Z256VLH4-pinctrl.h b/dts/nxp/kinetis/MKL27Z256VLH4-pinctrl.h new file mode 100644 index 000000000..be0fcd71e --- /dev/null +++ b/dts/nxp/kinetis/MKL27Z256VLH4-pinctrl.h @@ -0,0 +1,257 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKL27Z256VLH4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKL27Z256VLH4_ +#define _ZEPHYR_DTS_BINDING_MKL27Z256VLH4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD0_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2C0_SCL_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define TPM0_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2C0_SDA_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define TPM0_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define I2S0_RXD0_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/MKL27Z256VMP4-pinctrl.h b/dts/nxp/kinetis/MKL27Z256VMP4-pinctrl.h new file mode 100644 index 000000000..9fa28e62e --- /dev/null +++ b/dts/nxp/kinetis/MKL27Z256VMP4-pinctrl.h @@ -0,0 +1,257 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKL27Z256VMP4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKL27Z256VMP4_ +#define _ZEPHYR_DTS_BINDING_MKL27Z256VMP4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD0_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2C0_SCL_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define TPM0_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define I2S0_MCLK_PTC8 KINETIS_MUX('C',8,4) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2C0_SDA_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define TPM0_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define I2S0_RX_BCLK_PTC9 KINETIS_MUX('C',9,4) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define I2S0_RX_FS_PTC10 KINETIS_MUX('C',10,4) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define I2S0_RXD0_PTC11 KINETIS_MUX('C',11,4) /* PTC_11 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/MKL27Z64VDA4-pinctrl.h b/dts/nxp/kinetis/MKL27Z64VDA4-pinctrl.h new file mode 100644 index 000000000..0a1d544d1 --- /dev/null +++ b/dts/nxp/kinetis/MKL27Z64VDA4-pinctrl.h @@ -0,0 +1,183 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKL27Z64VDA4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKL27Z64VDA4_ +#define _ZEPHYR_DTS_BINDING_MKL27Z64VDA4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SPI1_MOSI_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SPI1_MISO_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SPI1_MISO_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SPI1_MOSI_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SPI1_PCS0_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define I2C1_SDA_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define I2C1_SCL_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define ADC0_DM1_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define FXIO0_D1_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_DP2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define ADC0_SE2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_MOSI_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define SPI0_MISO_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D2_PTE18 KINETIS_MUX('E',18,6) /* PTE_18 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define VREF_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/MKL27Z64VFM4-pinctrl.h b/dts/nxp/kinetis/MKL27Z64VFM4-pinctrl.h new file mode 100644 index 000000000..0b90cbef7 --- /dev/null +++ b/dts/nxp/kinetis/MKL27Z64VFM4-pinctrl.h @@ -0,0 +1,144 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKL27Z64VFM4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKL27Z64VFM4_ +#define _ZEPHYR_DTS_BINDING_MKL27Z64VFM4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SPI1_MOSI_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SPI1_MISO_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SPI1_MISO_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SPI1_MOSI_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SPI1_PCS0_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define I2C1_SDA_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define I2C1_SCL_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define VREF_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/MKL27Z64VFT4-pinctrl.h b/dts/nxp/kinetis/MKL27Z64VFT4-pinctrl.h new file mode 100644 index 000000000..b2b0d781c --- /dev/null +++ b/dts/nxp/kinetis/MKL27Z64VFT4-pinctrl.h @@ -0,0 +1,203 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKL27Z64VFT4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKL27Z64VFT4_ +#define _ZEPHYR_DTS_BINDING_MKL27Z64VFT4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SPI1_MOSI_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SPI1_MISO_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SPI1_MISO_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SPI1_MOSI_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SPI1_PCS0_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define I2C1_SDA_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define I2C1_SCL_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/kinetis/MKL27Z64VLH4-pinctrl.h b/dts/nxp/kinetis/MKL27Z64VLH4-pinctrl.h new file mode 100644 index 000000000..8a9456dba --- /dev/null +++ b/dts/nxp/kinetis/MKL27Z64VLH4-pinctrl.h @@ -0,0 +1,252 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKL27Z64VLH4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKL27Z64VLH4_ +#define _ZEPHYR_DTS_BINDING_MKL27Z64VLH4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SPI1_MOSI_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SPI1_MISO_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SPI1_MISO_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SPI1_MOSI_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SPI1_PCS0_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2C0_SCL_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define TPM0_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2C0_SDA_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define TPM0_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define I2C1_SDA_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define I2C1_SCL_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/MKL27Z64VMP4-pinctrl.h b/dts/nxp/kinetis/MKL27Z64VMP4-pinctrl.h new file mode 100644 index 000000000..90184c5e3 --- /dev/null +++ b/dts/nxp/kinetis/MKL27Z64VMP4-pinctrl.h @@ -0,0 +1,252 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKL27Z64VMP4/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKL27Z64VMP4_ +#define _ZEPHYR_DTS_BINDING_MKL27Z64VMP4_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define SPI1_MOSI_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define SPI1_MISO_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define SPI1_MISO_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define SPI1_MOSI_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define SPI1_PCS0_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define I2C0_SCL_PTC8 KINETIS_MUX('C',8,2) /* PTC_8 */ +#define TPM0_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define I2C0_SDA_PTC9 KINETIS_MUX('C',9,2) /* PTC_9 */ +#define TPM0_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define I2C1_SDA_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define I2C1_SCL_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/kinetis/MKM35Z512VLL7-pinctrl.h b/dts/nxp/kinetis/MKM35Z512VLL7-pinctrl.h new file mode 100644 index 000000000..ccc9e059d --- /dev/null +++ b/dts/nxp/kinetis/MKM35Z512VLL7-pinctrl.h @@ -0,0 +1,217 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKM35Z512VLL7/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKM35Z512VLL7_ +#define _ZEPHYR_DTS_BINDING_MKM35Z512VLL7_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define LCD_P23_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define LLWU_P16_PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LCD_P23_Fault_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define LCD_P24_PTA1 KINETIS_MUX('A',1,0) /* PTA_1 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LCD_P24_Fault_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define LCD_P25_PTA2 KINETIS_MUX('A',2,0) /* PTA_2 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LCD_P25_Fault_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define LCD_P26_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define LCD_P26_Fault_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define LCD_P27_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define LLWU_P15_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LCD_P27_Fault_PTA4 KINETIS_MUX('A',4,6) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define LCD_P28_PTA5 KINETIS_MUX('A',5,0) /* PTA_5 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define CMP0_OUT_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define LCD_P28_Fault_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define LCD_P29_PTA6 KINETIS_MUX('A',6,0) /* PTA_6 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define LLWU_P14_PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define XBAR_IN0_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define XBAR_IN0_PTA6_PTA6_PTA6_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define XBAR_IN0_PTA6_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define LCD_P29_Fault_PTA6 KINETIS_MUX('A',6,7) /* PTA_6 */ +#define LCD_P30_PTA7 KINETIS_MUX('A',7,0) /* PTA_7 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define XBAR_OUT0_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define LCD_P30_Fault_PTA7 KINETIS_MUX('A',7,7) /* PTA_7 */ +#define LCD_P31_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LCD_P31_Fault_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define LCD_P32_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LLWU_P17_PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LCD_P32_Fault_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define LCD_P33_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define SPI2_PCS0_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LCD_P33_Fault_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define LCD_P34_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define SPI2_SCK_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LCD_P34_Fault_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define LCD_P35_PTB4 KINETIS_MUX('B',4,0) /* PTB_4 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define SPI2_MISO_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LCD_P35_Fault_PTB4 KINETIS_MUX('B',4,7) /* PTB_4 */ +#define LCD_P36_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define SPI2_MOSI_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LCD_P36_Fault_PTB5 KINETIS_MUX('B',5,7) /* PTB_5 */ +#define LCD_P37_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define CMP1_IN0_PTB6 KINETIS_MUX('B',6,0) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define LCD_P37_Fault_PTB6 KINETIS_MUX('B',6,7) /* PTB_6 */ +#define LCD_P38_PTB7 KINETIS_MUX('B',7,0) /* PTB_7 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define AFE_CLK_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define LCD_P38_Fault_PTB7 KINETIS_MUX('B',7,7) /* PTB_7 */ +#define LCD_P39_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define UART3_RTS_b_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define XBAR_IN1_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define XBAR_IN1_PTC0_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define XBAR_IN1_PTC0_PTC0_PTC0_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define LCD_P39_Fault_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define CMP1_IN1_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LCD_P40_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define UART3_CTS_b_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define LCD_P40_Fault_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define LCD_P41_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define UART3_TX_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define XBAR_OUT1_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define LCD_P41_Fault_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP0_IN3_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LCD_P42_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define LLWU_P13_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define UART3_RX_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LCD_P42_Fault_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define LCD_P43_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LCD_P43_Fault_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define ADC0_SE0_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define CMP2_IN0_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P12_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define UART0_RTS_b_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR1_ALT1_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define ADC0_SE1_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define CMP2_IN1_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define UART0_CTS_b_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define QTMR0_TMR1_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define CMP2_IN2_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define ADC0_SE2_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define UART0_TX_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define XBAR_OUT2_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define CMP0_IN0_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define LLWU_P11_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define XBAR_IN2_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define XBAR_IN2_PTD0_PTD0_PTD0_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define XBAR_IN2_PTD0_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define UART0_RX/XBAR_IN2_PTD0_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define UART1_TX_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define SPI0_PCS0_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define XBAR_OUT3_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define QTMR0_TMR3_PTD1 KINETIS_MUX('D',1,5) /* PTD_1 */ +#define CMP0_IN1_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LLWU_P10_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SCK_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define XBAR_IN3_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define XBAR_IN3_PTD2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define XBAR_IN3_PTD2_PTD2_PTD2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define UART1_RX/XBAR_IN3_PTD2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define UART1_CTS_b_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define LPTMR1_ALT2_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define ADC0_SE3_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P9_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define UART1_RTS_b_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define SPI0_MISO_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define LPTMR1_ALT3_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define ADC0_SE4a_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPTMR0_ALT3_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define QTMR0_TMR0_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define UART3_CTS_b_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define ADC0_SE5a_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P8_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LPTMR0_ALT2_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define CMP1_OUT_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define UART3_RTS_b_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define CMP0_IN4_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define LLWU_P7_PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define I2C0_SCL_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define XBAR_IN4_PTD7_PTD7_PTD7_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define XBAR_IN4/UART3_RX_PTD7_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define XBAR_IN4_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define XBAR_IN4_PTD7_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define I2C0_SDA_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define XBAR_OUT4_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define UART3_TX_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CLKOUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define RESET_b_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define EXTAL_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define XBAR_IN6_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define XBAR_IN6_PTE2_PTE2_PTE2_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define EWM_IN/XBAR_IN6_PTE2_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define XBAR_IN6_PTE2_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define I2C1_SDA_PTE2 KINETIS_MUX('E',2,4) /* PTE_2 */ +#define XTAL_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define EWM_OUT_b_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define AFE_CLK_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define I2C1_SCL_PTE3 KINETIS_MUX('E',3,4) /* PTE_3 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define LPTMR0_ALT1_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define UART2_CTS_b_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define EWM_IN_PTE4 KINETIS_MUX('E',4,4) /* PTE_4 */ +#define LLWU_P6_PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define QTMR0_TMR3_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define UART2_RTS_b_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define EWM_OUT_b_PTE5 KINETIS_MUX('E',5,4) /* PTE_5 */ +#define CMP0_IN2_PTE6 KINETIS_MUX('E',6,0) /* PTE_6 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define LLWU_P5_PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define XBAR_IN5_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define XBAR_IN5/UART2_RX_PTE6_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define XBAR_IN5_PTE6_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define XBAR_IN5_PTE6_PTE6_PTE6_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define I2C0_SCL_PTE6 KINETIS_MUX('E',6,5) /* PTE_6 */ +#define SWD_DIO_PTE6 KINETIS_MUX('E',6,7) /* PTE_6 */ +#define ADC0_SE6a_PTE7 KINETIS_MUX('E',7,0) /* PTE_7 */ +#define PTE7 KINETIS_MUX('E',7,1) /* PTE_7 */ +#define XBAR_OUT5_PTE7 KINETIS_MUX('E',7,2) /* PTE_7 */ +#define UART2_TX_PTE7 KINETIS_MUX('E',7,3) /* PTE_7 */ +#define I2C0_SDA_PTE7 KINETIS_MUX('E',7,5) /* PTE_7 */ +#define SWD_CLK_PTE7 KINETIS_MUX('E',7,7) /* PTE_7 */ +#endif diff --git a/dts/nxp/kinetis/MKV31F512VLH12-pinctrl.h b/dts/nxp/kinetis/MKV31F512VLH12-pinctrl.h new file mode 100644 index 000000000..e7b302b8e --- /dev/null +++ b/dts/nxp/kinetis/MKV31F512VLH12-pinctrl.h @@ -0,0 +1,278 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKV31F512VLH12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKV31F512VLH12_ +#define _ZEPHYR_DTS_BINDING_MKV31F512VLH12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define EWM_IN_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define CMP0_OUT_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FTM2_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define CMP1_OUT_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FTM2_QD_PHB_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define FTM1_CH0_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FTM2_FLT0_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define EWM_OUT_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FTM0_FLT3_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM0_FLT0_PTA19 KINETIS_MUX('A',19,2) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define UART0_RX_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM0_FLT2_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define EWM_IN_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define UART0_TX_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT1_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define FTM0_FLT1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define SPI0_PCS0_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2C0_SCL_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define I2C0_SDA_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define FTM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define FTM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#endif diff --git a/dts/nxp/kinetis/MKV31F512VLL12-pinctrl.h b/dts/nxp/kinetis/MKV31F512VLL12-pinctrl.h new file mode 100644 index 000000000..3eefb27e4 --- /dev/null +++ b/dts/nxp/kinetis/MKV31F512VLL12-pinctrl.h @@ -0,0 +1,346 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MKV31F512VLL12/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MKV31F512VLL12_ +#define _ZEPHYR_DTS_BINDING_MKV31F512VLL12_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define UART0_CTS_b_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define FTM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define EWM_IN_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define JTAG_TCLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define UART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define FTM0_CH6_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define CMP0_OUT_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define FTM2_QD_PHA_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define FTM1_CH1_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define JTAG_TDI_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define UART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define FTM0_CH7_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define CMP1_OUT_PTA2 KINETIS_MUX('A',2,4) /* PTA_2 */ +#define FTM2_QD_PHB_PTA2 KINETIS_MUX('A',2,5) /* PTA_2 */ +#define FTM1_CH0_PTA2 KINETIS_MUX('A',2,6) /* PTA_2 */ +#define TRACE_SWO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define JTAG_TDO_PTA2 KINETIS_MUX('A',2,7) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define UART0_RTS_b_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define FTM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define FTM2_FLT0_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define EWM_OUT_b_PTA3 KINETIS_MUX('A',3,5) /* PTA_3 */ +#define JTAG_TMS_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define LLWU_P3_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define FTM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define FTM0_FLT3_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define FTM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define JTAG_TRST_b_PTA5 KINETIS_MUX('A',5,7) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define FTM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define FTM1_QD_PHA_PTA12 KINETIS_MUX('A',12,7) /* PTA_12 */ +#define LLWU_P4_PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define FTM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define FTM1_QD_PHB_PTA13 KINETIS_MUX('A',13,7) /* PTA_13 */ +#define PTA14 KINETIS_MUX('A',14,1) /* PTA_14 */ +#define SPI0_PCS0_PTA14 KINETIS_MUX('A',14,2) /* PTA_14 */ +#define UART0_TX_PTA14 KINETIS_MUX('A',14,3) /* PTA_14 */ +#define PTA15 KINETIS_MUX('A',15,1) /* PTA_15 */ +#define SPI0_SCK_PTA15 KINETIS_MUX('A',15,2) /* PTA_15 */ +#define UART0_RX_PTA15 KINETIS_MUX('A',15,3) /* PTA_15 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define SPI0_SOUT_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define UART0_CTS_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define ADC1_SE17_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define SPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define UART0_RTS_b_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define FTM0_FLT2_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define FTM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define FTM0_FLT0_PTA19 KINETIS_MUX('A',19,2) /* PTA_19 */ +#define FTM1_FLT0_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define FTM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define ADC1_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define FTM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define FTM1_QD_PHA_PTB0 KINETIS_MUX('B',0,6) /* PTB_0 */ +#define UART0_RX_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define ADC1_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define FTM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define FTM0_FLT2_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define EWM_IN_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FTM1_QD_PHB_PTB1 KINETIS_MUX('B',1,6) /* PTB_1 */ +#define UART0_TX_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define UART0_RTS_b_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define FTM0_FLT1_PTB2 KINETIS_MUX('B',2,4) /* PTB_2 */ +#define FTM0_FLT3_PTB2 KINETIS_MUX('B',2,6) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define UART0_CTS_b_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define FTM0_FLT0_PTB3 KINETIS_MUX('B',3,6) /* PTB_3 */ +#define PTB9 KINETIS_MUX('B',9,1) /* PTB_9 */ +#define SPI1_PCS1_PTB9 KINETIS_MUX('B',9,2) /* PTB_9 */ +#define LPUART0_CTS_b_PTB9 KINETIS_MUX('B',9,3) /* PTB_9 */ +#define ADC1_SE14_PTB10 KINETIS_MUX('B',10,0) /* PTB_10 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define SPI1_PCS0_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define LPUART0_RX_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define FTM0_FLT1_PTB10 KINETIS_MUX('B',10,6) /* PTB_10 */ +#define ADC1_SE15_PTB11 KINETIS_MUX('B',11,0) /* PTB_11 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define SPI1_SCK_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define LPUART0_TX_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define FTM0_FLT2_PTB11 KINETIS_MUX('B',11,6) /* PTB_11 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_SOUT_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define UART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define FTM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define EWM_IN_PTB16 KINETIS_MUX('B',16,6) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_SIN_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define UART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define FTM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define EWM_OUT_b_PTB17 KINETIS_MUX('B',17,6) /* PTB_17 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define FTM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define FTM2_QD_PHA_PTB18 KINETIS_MUX('B',18,6) /* PTB_18 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define FTM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define FTM2_QD_PHB_PTB19 KINETIS_MUX('B',19,6) /* PTB_19 */ +#define PTB20 KINETIS_MUX('B',20,1) /* PTB_20 */ +#define CMP0_OUT_PTB20 KINETIS_MUX('B',20,6) /* PTB_20 */ +#define PTB21 KINETIS_MUX('B',21,1) /* PTB_21 */ +#define CMP1_OUT_PTB21 KINETIS_MUX('B',21,6) /* PTB_21 */ +#define PTB22 KINETIS_MUX('B',22,1) /* PTB_22 */ +#define PTB23 KINETIS_MUX('B',23,1) /* PTB_23 */ +#define SPI0_PCS5_PTB23 KINETIS_MUX('B',23,3) /* PTB_23 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define SPI0_PCS4_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define PDB0_EXTRG_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define FTM0_FLT1_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define SPI0_PCS0_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define SPI0_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define UART1_RTS_b_PTC1 KINETIS_MUX('C',1,3) /* PTC_1 */ +#define FTM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define LPUART0_RTS_b_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define CMP1_IN0_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define ADC0_SE4b_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define SPI0_PCS2_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define UART1_CTS_b_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define FTM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define LPUART0_CTS_b_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define CMP1_IN1_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI0_PCS1_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define UART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define FTM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define LPUART0_RX_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_PCS0_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define UART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define FTM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define CMP1_OUT_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define LPUART0_TX_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FTM0_CH2_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_SOUT_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define PDB0_EXTRG_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2C0_SCL_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_SIN_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define I2C0_SDA_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define ADC1_SE4b_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define CMP0_IN2_PTC8 KINETIS_MUX('C',8,0) /* PTC_8 */ +#define PTC8 KINETIS_MUX('C',8,1) /* PTC_8 */ +#define FTM3_CH4_PTC8 KINETIS_MUX('C',8,3) /* PTC_8 */ +#define ADC1_SE5b_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define CMP0_IN3_PTC9 KINETIS_MUX('C',9,0) /* PTC_9 */ +#define PTC9 KINETIS_MUX('C',9,1) /* PTC_9 */ +#define FTM3_CH5_PTC9 KINETIS_MUX('C',9,3) /* PTC_9 */ +#define FTM2_FLT0_PTC9 KINETIS_MUX('C',9,6) /* PTC_9 */ +#define ADC1_SE6b_PTC10 KINETIS_MUX('C',10,0) /* PTC_10 */ +#define PTC10 KINETIS_MUX('C',10,1) /* PTC_10 */ +#define I2C1_SCL_PTC10 KINETIS_MUX('C',10,2) /* PTC_10 */ +#define FTM3_CH6_PTC10 KINETIS_MUX('C',10,3) /* PTC_10 */ +#define ADC1_SE7b_PTC11 KINETIS_MUX('C',11,0) /* PTC_11 */ +#define PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define LLWU_P11_PTC11 KINETIS_MUX('C',11,1) /* PTC_11 */ +#define I2C1_SDA_PTC11 KINETIS_MUX('C',11,2) /* PTC_11 */ +#define FTM3_CH7_PTC11 KINETIS_MUX('C',11,3) /* PTC_11 */ +#define PTC12 KINETIS_MUX('C',12,1) /* PTC_12 */ +#define FTM3_FLT0_PTC12 KINETIS_MUX('C',12,6) /* PTC_12 */ +#define PTC13 KINETIS_MUX('C',13,1) /* PTC_13 */ +#define PTC14 KINETIS_MUX('C',14,1) /* PTC_14 */ +#define PTC15 KINETIS_MUX('C',15,1) /* PTC_15 */ +#define PTC16 KINETIS_MUX('C',16,1) /* PTC_16 */ +#define LPUART0_RX_PTC16 KINETIS_MUX('C',16,3) /* PTC_16 */ +#define PTC17 KINETIS_MUX('C',17,1) /* PTC_17 */ +#define LPUART0_TX_PTC17 KINETIS_MUX('C',17,3) /* PTC_17 */ +#define PTC18 KINETIS_MUX('C',18,1) /* PTC_18 */ +#define LPUART0_RTS_b_PTC18 KINETIS_MUX('C',18,3) /* PTC_18 */ +#define LLWU_P12_PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_PCS0_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define UART2_RTS_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define FTM3_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define LPUART0_RTS_b_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define UART2_CTS_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define FTM3_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define LPUART0_CTS_b_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LLWU_P13_PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_SOUT_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define FTM3_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define LPUART0_RX_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define I2C0_SCL_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_SIN_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define FTM3_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define LPUART0_TX_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define I2C0_SDA_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI0_PCS1_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART0_RTS_b_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define FTM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define EWM_IN_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define SPI1_PCS0_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI0_PCS2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART0_CTS_b_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define FTM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define EWM_OUT_b_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI0_PCS3_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define UART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define FTM0_CH6_PTD6 KINETIS_MUX('D',6,4) /* PTD_6 */ +#define FTM0_FLT0_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define SPI1_SOUT_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define UART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define FTM0_CH7_PTD7 KINETIS_MUX('D',7,4) /* PTD_7 */ +#define FTM0_FLT1_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define SPI1_SIN_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define ADC1_SE4a_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_PCS1_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define UART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define ADC1_SE5a_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define LLWU_P0_PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_SOUT_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define UART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define SPI1_SIN_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define ADC1_SE6a_PTE2 KINETIS_MUX('E',2,0) /* PTE_2 */ +#define PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define LLWU_P1_PTE2 KINETIS_MUX('E',2,1) /* PTE_2 */ +#define SPI1_SCK_PTE2 KINETIS_MUX('E',2,2) /* PTE_2 */ +#define UART1_CTS_b_PTE2 KINETIS_MUX('E',2,3) /* PTE_2 */ +#define ADC1_SE7a_PTE3 KINETIS_MUX('E',3,0) /* PTE_3 */ +#define PTE3 KINETIS_MUX('E',3,1) /* PTE_3 */ +#define SPI1_SIN_PTE3 KINETIS_MUX('E',3,2) /* PTE_3 */ +#define UART1_RTS_b_PTE3 KINETIS_MUX('E',3,3) /* PTE_3 */ +#define SPI1_SOUT_PTE3 KINETIS_MUX('E',3,7) /* PTE_3 */ +#define LLWU_P2_PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define PTE4 KINETIS_MUX('E',4,1) /* PTE_4 */ +#define SPI1_PCS0_PTE4 KINETIS_MUX('E',4,2) /* PTE_4 */ +#define LPUART0_TX_PTE4 KINETIS_MUX('E',4,3) /* PTE_4 */ +#define PTE5 KINETIS_MUX('E',5,1) /* PTE_5 */ +#define SPI1_PCS2_PTE5 KINETIS_MUX('E',5,2) /* PTE_5 */ +#define LPUART0_RX_PTE5 KINETIS_MUX('E',5,3) /* PTE_5 */ +#define FTM3_CH0_PTE5 KINETIS_MUX('E',5,6) /* PTE_5 */ +#define PTE6 KINETIS_MUX('E',6,1) /* PTE_6 */ +#define SPI1_PCS3_PTE6 KINETIS_MUX('E',6,2) /* PTE_6 */ +#define LPUART0_CTS_b_PTE6 KINETIS_MUX('E',6,3) /* PTE_6 */ +#define FTM3_CH1_PTE6 KINETIS_MUX('E',6,6) /* PTE_6 */ +#define ADC0_SE4a_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_PCS0_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define FTM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FTM0_FLT3_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define FTM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_SE6a_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_SOUT_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define UART2_CTS_b_PTE18 KINETIS_MUX('E',18,3) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define ADC0_SE7a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_SIN_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define UART2_RTS_b_PTE19 KINETIS_MUX('E',19,3) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define ADC0_SE17_PTE24 KINETIS_MUX('E',24,0) /* PTE_24 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define FTM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define EWM_OUT_b_PTE24 KINETIS_MUX('E',24,6) /* PTE_24 */ +#define ADC0_SE18_PTE25 KINETIS_MUX('E',25,0) /* PTE_25 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define FTM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define EWM_IN_PTE25 KINETIS_MUX('E',25,6) /* PTE_25 */ +#define PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#define CLKOUT32K_PTE26 KINETIS_MUX('E',26,1) /* PTE_26 */ +#endif diff --git a/dts/nxp/lpc/LPC54005JBD100-pinctrl.h b/dts/nxp/lpc/LPC54005JBD100-pinctrl.h new file mode 100644 index 000000000..c4d5d85d8 --- /dev/null +++ b/dts/nxp/lpc/LPC54005JBD100-pinctrl.h @@ -0,0 +1,3116 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54005JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54005JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC54005JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54005JET100-pinctrl.h b/dts/nxp/lpc/LPC54005JET100-pinctrl.h new file mode 100644 index 000000000..a04ceb595 --- /dev/null +++ b/dts/nxp/lpc/LPC54005JET100-pinctrl.h @@ -0,0 +1,3116 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54005JET100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54005JET100_ +#define _ZEPHYR_DTS_BINDING_LPC54005JET100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54016JBD100-pinctrl.h b/dts/nxp/lpc/LPC54016JBD100-pinctrl.h new file mode 100644 index 000000000..1540d342f --- /dev/null +++ b/dts/nxp/lpc/LPC54016JBD100-pinctrl.h @@ -0,0 +1,3143 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54016JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54016JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC54016JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54016JBD208-pinctrl.h b/dts/nxp/lpc/LPC54016JBD208-pinctrl.h new file mode 100644 index 000000000..c6555522f --- /dev/null +++ b/dts/nxp/lpc/LPC54016JBD208-pinctrl.h @@ -0,0 +1,3766 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54016JBD208/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54016JBD208_ +#define _ZEPHYR_DTS_BINDING_LPC54016JBD208_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ +#define CAN1_TD_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 2) /* PIO4_17 */ +#define CTIMER1_CAPTURE2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 3) /* PIO4_17 */ +#define EMC_EMC_BLS2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 6) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 0) /* PIO4_17 */ +#define UTICK0_CAPTURE0_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 4) /* PIO4_17 */ +#define CAN1_RD_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 2) /* PIO4_18 */ +#define CTIMER1_CAPTURE3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 3) /* PIO4_18 */ +#define EMC_EMC_BLS3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 6) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 0) /* PIO4_18 */ +#define UTICK0_CAPTURE1_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 4) /* PIO4_18 */ +#define CTIMER4_CAPTURE2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 4) /* PIO4_19 */ +#define EMC_EMC_DQM2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 6) /* PIO4_19 */ +#define ENET_ENET_TXD0_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 1) /* PIO4_19 */ +#define FC2_SCK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 3) /* PIO4_19 */ +#define GPIO_PIO419_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 0) /* PIO4_19 */ +#define SD_CLK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 2) /* PIO4_19 */ +#define CTIMER4_CAPTURE3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 4) /* PIO4_20 */ +#define EMC_EMC_DQM3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 6) /* PIO4_20 */ +#define ENET_ENET_TXD1_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 1) /* PIO4_20 */ +#define FC2_RXD_SDA_MOSI_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 3) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 0) /* PIO4_20 */ +#define SD_CMD_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 2) /* PIO4_20 */ +#define CTIMER2_MATCH3_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 4) /* PIO4_21 */ +#define EMC_EMC_D16_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 6) /* PIO4_21 */ +#define ENET_ENET_TXD2_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 1) /* PIO4_21 */ +#define FC2_TXD_SCL_MISO_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 3) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 0) /* PIO4_21 */ +#define SD_POW_EN_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 2) /* PIO4_21 */ +#define CTIMER1_MATCH3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 4) /* PIO4_22 */ +#define EMC_EMC_D17_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 6) /* PIO4_22 */ +#define ENET_ENET_TXD3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 1) /* PIO4_22 */ +#define FC2_RTS_SCL_SSEL1_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 3) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 0) /* PIO4_22 */ +#define SD_CARD_DET_N_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 2) /* PIO4_22 */ +#define CTIMER1_MATCH0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 5) /* PIO4_23 */ +#define EMC_EMC_D18_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 6) /* PIO4_23 */ +#define ENET_ENET_RXD0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 1) /* PIO4_23 */ +#define FC2_CTS_SDA_SSEL0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 3) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 0) /* PIO4_23 */ +#define SD_WR_PRT_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 2) /* PIO4_23 */ +#define CTIMER1_MATCH1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 5) /* PIO4_24 */ +#define EMC_EMC_D19_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 6) /* PIO4_24 */ +#define ENET_ENET_RXD1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 1) /* PIO4_24 */ +#define FC7_RTS_SCL_SSEL1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 3) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 0) /* PIO4_24 */ +#define SD_CARD_INT_N_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 2) /* PIO4_24 */ +#define CTIMER1_MATCH2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 5) /* PIO4_25 */ +#define EMC_EMC_D20_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 6) /* PIO4_25 */ +#define ENET_ENET_RXD2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 1) /* PIO4_25 */ +#define FC7_CTS_SDA_SSEL0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 3) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 0) /* PIO4_25 */ +#define SDIF_SD_D0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 2) /* PIO4_25 */ +#define CTIMER1_MATCH3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 5) /* PIO4_26 */ +#define EMC_EMC_D21_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 6) /* PIO4_26 */ +#define ENET_ENET_RXD3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 1) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 0) /* PIO4_26 */ +#define SDIF_SD_D1_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 2) /* PIO4_26 */ +#define UTICK0_CAPTURE2_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 4) /* PIO4_26 */ +#define CTIMER1_CAPTURE0_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 5) /* PIO4_27 */ +#define EMC_EMC_D22_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 6) /* PIO4_27 */ +#define ENET_TX_EN_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 1) /* PIO4_27 */ +#define FC1_SCK_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 4) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 0) /* PIO4_27 */ +#define SDIF_SD_D2_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 2) /* PIO4_27 */ +#define CTIMER1_CAPTURE1_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 5) /* PIO4_28 */ +#define EMC_EMC_D23_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 6) /* PIO4_28 */ +#define ENET_TX_ER_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 1) /* PIO4_28 */ +#define FC1_RXD_SDA_MOSI_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 4) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 0) /* PIO4_28 */ +#define SDIF_SD_D3_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 2) /* PIO4_28 */ +#define CTIMER1_CAPTURE2_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 5) /* PIO4_29 */ +#define EMC_EMC_D24_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 6) /* PIO4_29 */ +#define ENET_RX_ER_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 1) /* PIO4_29 */ +#define FC1_TXD_SCL_MISO_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 4) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 0) /* PIO4_29 */ +#define SDIF_SD_D4_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 2) /* PIO4_29 */ +#define CTIMER1_CAPTURE3_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 5) /* PIO4_30 */ +#define CTIMER3_MATCH0_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 3) /* PIO4_30 */ +#define EMC_EMC_D25_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 6) /* PIO4_30 */ +#define ENET_TX_CLK_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 1) /* PIO4_30 */ +#define FC1_RTS_SCL_SSEL1_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 4) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 0) /* PIO4_30 */ +#define SDIF_SD_D5_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 2) /* PIO4_30 */ +#define CTIMER3_MATCH1_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 3) /* PIO4_31 */ +#define EMC_EMC_D26_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 6) /* PIO4_31 */ +#define ENET_RX_CLK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 1) /* PIO4_31 */ +#define FC4_SCK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 4) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 0) /* PIO4_31 */ +#define SDIF_SD_D6_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 2) /* PIO4_31 */ +#define CTIMER3_MATCH2_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 3) /* PIO5_0 */ +#define EMC_EMC_D27_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 6) /* PIO5_0 */ +#define ENET_RX_DV_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 1) /* PIO5_0 */ +#define FC4_RXD_SDA_MOSI_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 4) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 0) /* PIO5_0 */ +#define SDIF_SD_D7_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 2) /* PIO5_0 */ +#define CTIMER3_MATCH3_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 3) /* PIO5_1 */ +#define EMC_EMC_D28_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 6) /* PIO5_1 */ +#define ENET_CRS_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 1) /* PIO5_1 */ +#define FC4_TXD_SCL_MISO_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 4) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 0) /* PIO5_1 */ +#define SDIF_SD_VOLT0_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 2) /* PIO5_1 */ +#define CTIMER3_CAPTURE0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 3) /* PIO5_2 */ +#define EMC_EMC_D29_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 6) /* PIO5_2 */ +#define ENET_COL_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 1) /* PIO5_2 */ +#define FC4_CTS_SDA_SSEL0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 4) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 0) /* PIO5_2 */ +#define SDIF_SD_VOLT1_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 2) /* PIO5_2 */ +#define CTIMER3_CAPTURE1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 3) /* PIO5_3 */ +#define EMC_EMC_D30_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 6) /* PIO5_3 */ +#define ENET_MDC_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 1) /* PIO5_3 */ +#define FC4_RTS_SCL_SSEL1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 4) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 0) /* PIO5_3 */ +#define SDIF_SD_VOLT2_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 2) /* PIO5_3 */ +#define CTIMER3_CAPTURE2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 3) /* PIO5_4 */ +#define EMC_EMC_D31_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 6) /* PIO5_4 */ +#define ENET_MDIO_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 1) /* PIO5_4 */ +#define FC4_SSEL2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 0) /* PIO5_4 */ +#define SD_BACKEND_PWR_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 2) /* PIO5_4 */ +#define CTIMER3_CAPTURE3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 3) /* PIO5_5 */ +#define DMIC0_CLK1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 2) /* PIO5_5 */ +#define EMC_EMC_A21_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 6) /* PIO5_5 */ +#define FC4_SSEL3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 4) /* PIO5_5 */ +#define GPIO_PIO55_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 0) /* PIO5_5 */ +#define SCT0_IN0_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN2_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN4_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN5_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN6_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define TRACECLK_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 5) /* PIO5_5 */ +#define DMIC0_DATA1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 2) /* PIO5_6 */ +#define EMC_EMC_A22_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 6) /* PIO5_6 */ +#define FC5_SCK_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 3) /* PIO5_6 */ +#define GPIO_PIO56_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 0) /* PIO5_6 */ +#define SCT0_IN0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN2_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN3_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN4_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN6_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_OUT5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 4) /* PIO5_6 */ +#define SWD_TRACEDATA0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 5) /* PIO5_6 */ +#define EMC_EMC_A23_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 6) /* PIO5_7 */ +#define FC5_RXD_SDA_MOSI_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 3) /* PIO5_7 */ +#define GPIO_PIO57_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 0) /* PIO5_7 */ +#define MCLK_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 2) /* PIO5_7 */ +#define SCT0_IN0_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN2_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN3_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN4_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN5_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_OUT6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 4) /* PIO5_7 */ +#define SWD_TRACEDATA1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 5) /* PIO5_7 */ +#define DMIC0_CLK0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 2) /* PIO5_8 */ +#define EMC_EMC_A24_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 6) /* PIO5_8 */ +#define FC5_TXD_SCL_MISO_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 3) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 0) /* PIO5_8 */ +#define SCT0_IN0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN1_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN3_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN4_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN5_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN6_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_OUT7_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 4) /* PIO5_8 */ +#define SWD_TRACEDATA2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 5) /* PIO5_8 */ +#define DMIC0_DATA0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 2) /* PIO5_9 */ +#define EMC_EMC_A25_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 6) /* PIO5_9 */ +#define FC5_CTS_SDA_SSEL0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 3) /* PIO5_9 */ +#define GPIO_PIO59_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 0) /* PIO5_9 */ +#define SCT0_IN0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN1_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN2_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN4_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN5_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN6_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_OUT8_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 4) /* PIO5_9 */ +#define SWD_TRACEDATA3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 5) /* PIO5_9 */ +#define FC5_RTS_SCL_SSEL1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 3) /* PIO5_10 */ +#define GPIO_PIO510_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 0) /* PIO5_10 */ +#define SCT0_IN0_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN2_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN4_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN5_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN6_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_OUT9_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 4) /* PIO5_10 */ +#define UTICK0_CAPTURE3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 5) /* PIO5_10 */ + +#endif diff --git a/dts/nxp/lpc/LPC54016JET100-pinctrl.h b/dts/nxp/lpc/LPC54016JET100-pinctrl.h new file mode 100644 index 000000000..44ae0d92e --- /dev/null +++ b/dts/nxp/lpc/LPC54016JET100-pinctrl.h @@ -0,0 +1,3143 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54016JET100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54016JET100_ +#define _ZEPHYR_DTS_BINDING_LPC54016JET100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54016JET180-pinctrl.h b/dts/nxp/lpc/LPC54016JET180-pinctrl.h new file mode 100644 index 000000000..da62c4108 --- /dev/null +++ b/dts/nxp/lpc/LPC54016JET180-pinctrl.h @@ -0,0 +1,3571 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54016JET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54016JET180_ +#define _ZEPHYR_DTS_BINDING_LPC54016JET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54018J2MET180-pinctrl.h b/dts/nxp/lpc/LPC54018J2MET180-pinctrl.h new file mode 100644 index 000000000..c56bc2c0f --- /dev/null +++ b/dts/nxp/lpc/LPC54018J2MET180-pinctrl.h @@ -0,0 +1,3304 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54018J2MET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54018J2MET180_ +#define _ZEPHYR_DTS_BINDING_LPC54018J2MET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ + +#endif diff --git a/dts/nxp/lpc/LPC54018J4MET180-pinctrl.h b/dts/nxp/lpc/LPC54018J4MET180-pinctrl.h new file mode 100644 index 000000000..4e1298f20 --- /dev/null +++ b/dts/nxp/lpc/LPC54018J4MET180-pinctrl.h @@ -0,0 +1,3304 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54018J4MET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54018J4MET180_ +#define _ZEPHYR_DTS_BINDING_LPC54018J4MET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ + +#endif diff --git a/dts/nxp/lpc/LPC54018JBD208-pinctrl.h b/dts/nxp/lpc/LPC54018JBD208-pinctrl.h new file mode 100644 index 000000000..93a164208 --- /dev/null +++ b/dts/nxp/lpc/LPC54018JBD208-pinctrl.h @@ -0,0 +1,3801 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54018JBD208/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54018JBD208_ +#define _ZEPHYR_DTS_BINDING_LPC54018JBD208_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ +#define CAN1_TD_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 2) /* PIO4_17 */ +#define CTIMER1_CAPTURE2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 3) /* PIO4_17 */ +#define EMC_EMC_BLS2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 6) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 0) /* PIO4_17 */ +#define UTICK0_CAPTURE0_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 4) /* PIO4_17 */ +#define CAN1_RD_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 2) /* PIO4_18 */ +#define CTIMER1_CAPTURE3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 3) /* PIO4_18 */ +#define EMC_EMC_BLS3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 6) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 0) /* PIO4_18 */ +#define UTICK0_CAPTURE1_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 4) /* PIO4_18 */ +#define CTIMER4_CAPTURE2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 4) /* PIO4_19 */ +#define EMC_EMC_DQM2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 6) /* PIO4_19 */ +#define ENET_ENET_TXD0_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 1) /* PIO4_19 */ +#define FC2_SCK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 3) /* PIO4_19 */ +#define GPIO_PIO419_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 0) /* PIO4_19 */ +#define SD_CLK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 2) /* PIO4_19 */ +#define CTIMER4_CAPTURE3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 4) /* PIO4_20 */ +#define EMC_EMC_DQM3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 6) /* PIO4_20 */ +#define ENET_ENET_TXD1_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 1) /* PIO4_20 */ +#define FC2_RXD_SDA_MOSI_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 3) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 0) /* PIO4_20 */ +#define SD_CMD_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 2) /* PIO4_20 */ +#define CTIMER2_MATCH3_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 4) /* PIO4_21 */ +#define EMC_EMC_D16_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 6) /* PIO4_21 */ +#define ENET_ENET_TXD2_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 1) /* PIO4_21 */ +#define FC2_TXD_SCL_MISO_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 3) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 0) /* PIO4_21 */ +#define SD_POW_EN_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 2) /* PIO4_21 */ +#define CTIMER1_MATCH3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 4) /* PIO4_22 */ +#define EMC_EMC_D17_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 6) /* PIO4_22 */ +#define ENET_ENET_TXD3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 1) /* PIO4_22 */ +#define FC2_RTS_SCL_SSEL1_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 3) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 0) /* PIO4_22 */ +#define SD_CARD_DET_N_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 2) /* PIO4_22 */ +#define CTIMER1_MATCH0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 5) /* PIO4_23 */ +#define EMC_EMC_D18_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 6) /* PIO4_23 */ +#define ENET_ENET_RXD0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 1) /* PIO4_23 */ +#define FC2_CTS_SDA_SSEL0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 3) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 0) /* PIO4_23 */ +#define SD_WR_PRT_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 2) /* PIO4_23 */ +#define CTIMER1_MATCH1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 5) /* PIO4_24 */ +#define EMC_EMC_D19_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 6) /* PIO4_24 */ +#define ENET_ENET_RXD1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 1) /* PIO4_24 */ +#define FC7_RTS_SCL_SSEL1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 3) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 0) /* PIO4_24 */ +#define SD_CARD_INT_N_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 2) /* PIO4_24 */ +#define CTIMER1_MATCH2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 5) /* PIO4_25 */ +#define EMC_EMC_D20_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 6) /* PIO4_25 */ +#define ENET_ENET_RXD2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 1) /* PIO4_25 */ +#define FC7_CTS_SDA_SSEL0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 3) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 0) /* PIO4_25 */ +#define SDIF_SD_D0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 2) /* PIO4_25 */ +#define CTIMER1_MATCH3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 5) /* PIO4_26 */ +#define EMC_EMC_D21_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 6) /* PIO4_26 */ +#define ENET_ENET_RXD3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 1) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 0) /* PIO4_26 */ +#define SDIF_SD_D1_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 2) /* PIO4_26 */ +#define UTICK0_CAPTURE2_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 4) /* PIO4_26 */ +#define CTIMER1_CAPTURE0_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 5) /* PIO4_27 */ +#define EMC_EMC_D22_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 6) /* PIO4_27 */ +#define ENET_TX_EN_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 1) /* PIO4_27 */ +#define FC1_SCK_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 4) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 0) /* PIO4_27 */ +#define SDIF_SD_D2_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 2) /* PIO4_27 */ +#define CTIMER1_CAPTURE1_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 5) /* PIO4_28 */ +#define EMC_EMC_D23_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 6) /* PIO4_28 */ +#define ENET_TX_ER_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 1) /* PIO4_28 */ +#define FC1_RXD_SDA_MOSI_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 4) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 0) /* PIO4_28 */ +#define SDIF_SD_D3_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 2) /* PIO4_28 */ +#define CTIMER1_CAPTURE2_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 5) /* PIO4_29 */ +#define EMC_EMC_D24_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 6) /* PIO4_29 */ +#define ENET_RX_ER_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 1) /* PIO4_29 */ +#define FC1_TXD_SCL_MISO_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 4) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 0) /* PIO4_29 */ +#define SDIF_SD_D4_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 2) /* PIO4_29 */ +#define CTIMER1_CAPTURE3_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 5) /* PIO4_30 */ +#define CTIMER3_MATCH0_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 3) /* PIO4_30 */ +#define EMC_EMC_D25_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 6) /* PIO4_30 */ +#define ENET_TX_CLK_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 1) /* PIO4_30 */ +#define FC1_RTS_SCL_SSEL1_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 4) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 0) /* PIO4_30 */ +#define SDIF_SD_D5_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 2) /* PIO4_30 */ +#define CTIMER3_MATCH1_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 3) /* PIO4_31 */ +#define EMC_EMC_D26_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 6) /* PIO4_31 */ +#define ENET_RX_CLK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 1) /* PIO4_31 */ +#define FC4_SCK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 4) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 0) /* PIO4_31 */ +#define SDIF_SD_D6_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 2) /* PIO4_31 */ +#define CTIMER3_MATCH2_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 3) /* PIO5_0 */ +#define EMC_EMC_D27_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 6) /* PIO5_0 */ +#define ENET_RX_DV_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 1) /* PIO5_0 */ +#define FC4_RXD_SDA_MOSI_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 4) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 0) /* PIO5_0 */ +#define SDIF_SD_D7_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 2) /* PIO5_0 */ +#define CTIMER3_MATCH3_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 3) /* PIO5_1 */ +#define EMC_EMC_D28_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 6) /* PIO5_1 */ +#define ENET_CRS_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 1) /* PIO5_1 */ +#define FC4_TXD_SCL_MISO_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 4) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 0) /* PIO5_1 */ +#define SDIF_SD_VOLT0_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 2) /* PIO5_1 */ +#define CTIMER3_CAPTURE0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 3) /* PIO5_2 */ +#define EMC_EMC_D29_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 6) /* PIO5_2 */ +#define ENET_COL_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 1) /* PIO5_2 */ +#define FC4_CTS_SDA_SSEL0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 4) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 0) /* PIO5_2 */ +#define SDIF_SD_VOLT1_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 2) /* PIO5_2 */ +#define CTIMER3_CAPTURE1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 3) /* PIO5_3 */ +#define EMC_EMC_D30_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 6) /* PIO5_3 */ +#define ENET_MDC_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 1) /* PIO5_3 */ +#define FC4_RTS_SCL_SSEL1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 4) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 0) /* PIO5_3 */ +#define SDIF_SD_VOLT2_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 2) /* PIO5_3 */ +#define CTIMER3_CAPTURE2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 3) /* PIO5_4 */ +#define EMC_EMC_D31_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 6) /* PIO5_4 */ +#define ENET_MDIO_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 1) /* PIO5_4 */ +#define FC4_SSEL2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 0) /* PIO5_4 */ +#define SD_BACKEND_PWR_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 2) /* PIO5_4 */ +#define CTIMER3_CAPTURE3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 3) /* PIO5_5 */ +#define DMIC0_CLK1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 2) /* PIO5_5 */ +#define EMC_EMC_A21_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 6) /* PIO5_5 */ +#define FC4_SSEL3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 4) /* PIO5_5 */ +#define GPIO_PIO55_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 0) /* PIO5_5 */ +#define SCT0_IN0_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN2_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN4_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN5_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN6_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define TRACECLK_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 5) /* PIO5_5 */ +#define DMIC0_DATA1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 2) /* PIO5_6 */ +#define EMC_EMC_A22_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 6) /* PIO5_6 */ +#define FC5_SCK_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 3) /* PIO5_6 */ +#define GPIO_PIO56_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 0) /* PIO5_6 */ +#define SCT0_IN0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN2_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN3_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN4_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN6_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_OUT5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 4) /* PIO5_6 */ +#define SWD_TRACEDATA0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 5) /* PIO5_6 */ +#define EMC_EMC_A23_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 6) /* PIO5_7 */ +#define FC5_RXD_SDA_MOSI_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 3) /* PIO5_7 */ +#define GPIO_PIO57_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 0) /* PIO5_7 */ +#define MCLK_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 2) /* PIO5_7 */ +#define SCT0_IN0_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN2_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN3_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN4_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN5_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_OUT6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 4) /* PIO5_7 */ +#define SWD_TRACEDATA1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 5) /* PIO5_7 */ +#define DMIC0_CLK0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 2) /* PIO5_8 */ +#define EMC_EMC_A24_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 6) /* PIO5_8 */ +#define FC5_TXD_SCL_MISO_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 3) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 0) /* PIO5_8 */ +#define SCT0_IN0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN1_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN3_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN4_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN5_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN6_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_OUT7_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 4) /* PIO5_8 */ +#define SWD_TRACEDATA2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 5) /* PIO5_8 */ +#define DMIC0_DATA0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 2) /* PIO5_9 */ +#define EMC_EMC_A25_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 6) /* PIO5_9 */ +#define FC5_CTS_SDA_SSEL0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 3) /* PIO5_9 */ +#define GPIO_PIO59_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 0) /* PIO5_9 */ +#define SCT0_IN0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN1_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN2_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN4_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN5_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN6_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_OUT8_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 4) /* PIO5_9 */ +#define SWD_TRACEDATA3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 5) /* PIO5_9 */ +#define FC5_RTS_SCL_SSEL1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 3) /* PIO5_10 */ +#define GPIO_PIO510_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 0) /* PIO5_10 */ +#define SCT0_IN0_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN2_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN4_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN5_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN6_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_OUT9_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 4) /* PIO5_10 */ +#define UTICK0_CAPTURE3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 5) /* PIO5_10 */ + +#endif diff --git a/dts/nxp/lpc/LPC54018JET180-pinctrl.h b/dts/nxp/lpc/LPC54018JET180-pinctrl.h new file mode 100644 index 000000000..605f2ae9e --- /dev/null +++ b/dts/nxp/lpc/LPC54018JET180-pinctrl.h @@ -0,0 +1,3606 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54018JET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54018JET180_ +#define _ZEPHYR_DTS_BINDING_LPC54018JET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54113J128BD64-pinctrl.h b/dts/nxp/lpc/LPC54113J128BD64-pinctrl.h new file mode 100644 index 000000000..8e96cb8dd --- /dev/null +++ b/dts/nxp/lpc/LPC54113J128BD64-pinctrl.h @@ -0,0 +1,1694 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54113J128BD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54113J128BD64_ +#define _ZEPHYR_DTS_BINDING_LPC54113J128BD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_CAPTURE0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define FC0_RXD_SDA_MOSI_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define FC3_CTS_SDA_SSEL0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_OUT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC0_TXD_SCL_MISO_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define FC3_RTS_SCL_SSEL1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC0_CTS_SDA_SSEL0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define FC2_SSEL3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER1_MATCH3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC0_RTS_SCL_SSEL1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define FC2_SSEL2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC0_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define FC3_SSEL2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER0_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_OUT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER0_MATCH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define UTICK0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ +#define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define CTIMER0_CAPTURE2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define CTIMER0_MATCH2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC6_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SCT0_OUT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define CTIMER0_MATCH3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC2_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SCT0_OUT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define CTIMER3_CAPTURE0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define FC2_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC3_CTS_SDA_SSEL0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCT0_OUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER3_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC2_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SCT0_OUT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC3_SCK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define CTIMER2_MATCH3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_RXD_SDA_MOSI_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 2) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER2_MATCH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC3_TXD_SCL_MISO_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_OUT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER2_MATCH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_SCK_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 5) /* PIO0_14 */ +#define FC3_CTS_SDA_SSEL0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_OUT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER2_MATCH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define FC3_RTS_SCL_SSEL1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define FC4_SCK_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 5) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SWO_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CTIMER3_MATCH1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define FC3_SSEL2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define FC6_CTS_SDA_SSEL0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define SWCLK_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 5) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define CTIMER3_MATCH2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC3_SSEL3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define FC6_RTS_SCL_SSEL1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SWDIO_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 5) /* PIO0_17 */ +#define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER0_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define FC5_TXD_SCL_MISO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCT0_OUT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC5_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC0_SCK_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define FC5_RXD_SDA_MOSI_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CLKOUT_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define CTIMER3_MATCH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC0_TXD_SCL_MISO_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CLKIN_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define CTIMER3_MATCH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC0_RXD_SDA_MOSI_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC1_RTS_SCL_SSEL1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define UTICK0_CAPTURE1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_MATCH0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 5) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC1_CTS_SDA_SSEL0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 5) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC4_RTS_SCL_SSEL1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define FC6_CTS_SDA_SSEL0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC4_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER0_CAPTURE1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define CTIMER0_MATCH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER0_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC1_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define ADC0_CH1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_CAPTURE2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define CTIMER0_MATCH2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC1_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define ADC0_CH2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_CAPTURE3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define CTIMER0_MATCH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 6) /* PIO0_31 */ +#define CTIMER2_CAPTURE2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMIC0_CLK0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define FC2_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_CH3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define CTIMER3_MATCH1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMIC0_DATA0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define FC2_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_CH4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC4_TXD_SCL_MISO_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define FC5_SSEL2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define SWO_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 2) /* PIO1_1 */ +#define ADC0_CH5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define FC4_RXD_SDA_MOSI_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC5_SSEL3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define FC7_SSEL3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 2) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define MCLK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define ADC0_CH6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CTIMER0_CAPTURE1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define FC3_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC7_SSEL2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 2) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ +#define USB0_UP_LED_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_CH7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER0_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMIC0_CLK1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FC3_TXD_SCL_MISO_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define FC7_RTS_SCL_SSEL1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define ADC0_CH8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER1_CAPTURE0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define CTIMER1_MATCH3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 5) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMIC0_DATA1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define FC7_CTS_SDA_SSEL0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define USB0_FRAME_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 7) /* PIO1_5 */ +#define ADC0_CH9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER1_CAPTURE2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define CTIMER1_MATCH2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 5) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC7_SCK_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define USB0_VBUS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 7) /* PIO1_6 */ +#define ADC0_CH10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER1_CAPTURE2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 5) /* PIO1_7 */ +#define CTIMER1_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_CH11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define CTIMER1_CAPTURE3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define CTIMER1_MATCH3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 3) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define FC3_RXD_SDA_MOSI_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define USB0_UP_LED_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ADC0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_SCK_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define USB0_FRAME_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 7) /* PIO1_10 */ +#define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC4_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define FC6_RTS_SCL_SSEL1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */ +#define ADC0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC5_RXD_SDA_MOSI_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define FC7_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define UTICK0_CAPTURE2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define ADC0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_MATCH1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC5_TXD_SCL_MISO_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define FC2_RXD_SDA_MOSI_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define SCT0_OUT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define ADC0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMIC0_CLK0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC7_CTS_SDA_SSEL0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define SCT0_OUT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER0_CAPTURE0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define CTIMER0_MATCH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMIC0_DATA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC7_RTS_SCL_SSEL1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define MCLK_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define UTICK0_CAPTURE3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ + +#endif diff --git a/dts/nxp/lpc/LPC54113J256BD64-pinctrl.h b/dts/nxp/lpc/LPC54113J256BD64-pinctrl.h new file mode 100644 index 000000000..cd897aa99 --- /dev/null +++ b/dts/nxp/lpc/LPC54113J256BD64-pinctrl.h @@ -0,0 +1,1694 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54113J256BD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54113J256BD64_ +#define _ZEPHYR_DTS_BINDING_LPC54113J256BD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_CAPTURE0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define FC0_RXD_SDA_MOSI_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define FC3_CTS_SDA_SSEL0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_OUT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC0_TXD_SCL_MISO_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define FC3_RTS_SCL_SSEL1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC0_CTS_SDA_SSEL0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define FC2_SSEL3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER1_MATCH3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC0_RTS_SCL_SSEL1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define FC2_SSEL2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC0_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define FC3_SSEL2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER0_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_OUT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER0_MATCH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define UTICK0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ +#define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define CTIMER0_CAPTURE2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define CTIMER0_MATCH2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC6_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SCT0_OUT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define CTIMER0_MATCH3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC2_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SCT0_OUT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define CTIMER3_CAPTURE0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define FC2_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC3_CTS_SDA_SSEL0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCT0_OUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER3_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC2_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SCT0_OUT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC3_SCK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define CTIMER2_MATCH3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_RXD_SDA_MOSI_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 2) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER2_MATCH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC3_TXD_SCL_MISO_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_OUT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER2_MATCH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_SCK_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 5) /* PIO0_14 */ +#define FC3_CTS_SDA_SSEL0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_OUT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER2_MATCH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define FC3_RTS_SCL_SSEL1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define FC4_SCK_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 5) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SWO_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CTIMER3_MATCH1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define FC3_SSEL2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define FC6_CTS_SDA_SSEL0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define SWCLK_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 5) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define CTIMER3_MATCH2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC3_SSEL3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define FC6_RTS_SCL_SSEL1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SWDIO_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 5) /* PIO0_17 */ +#define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER0_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define FC5_TXD_SCL_MISO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCT0_OUT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC5_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC0_SCK_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define FC5_RXD_SDA_MOSI_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CLKOUT_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define CTIMER3_MATCH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC0_TXD_SCL_MISO_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CLKIN_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define CTIMER3_MATCH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC0_RXD_SDA_MOSI_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC1_RTS_SCL_SSEL1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define UTICK0_CAPTURE1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_MATCH0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 5) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC1_CTS_SDA_SSEL0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 5) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC4_RTS_SCL_SSEL1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define FC6_CTS_SDA_SSEL0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC4_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER0_CAPTURE1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define CTIMER0_MATCH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER0_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC1_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define ADC0_CH1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_CAPTURE2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define CTIMER0_MATCH2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC1_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define ADC0_CH2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_CAPTURE3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define CTIMER0_MATCH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 6) /* PIO0_31 */ +#define CTIMER2_CAPTURE2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMIC0_CLK0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define FC2_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_CH3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define CTIMER3_MATCH1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMIC0_DATA0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define FC2_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_CH4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC4_TXD_SCL_MISO_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define FC5_SSEL2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define SWO_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 2) /* PIO1_1 */ +#define ADC0_CH5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define FC4_RXD_SDA_MOSI_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC5_SSEL3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define FC7_SSEL3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 2) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define MCLK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define ADC0_CH6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CTIMER0_CAPTURE1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define FC3_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC7_SSEL2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 2) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ +#define USB0_UP_LED_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_CH7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER0_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMIC0_CLK1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FC3_TXD_SCL_MISO_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define FC7_RTS_SCL_SSEL1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define ADC0_CH8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER1_CAPTURE0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define CTIMER1_MATCH3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 5) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMIC0_DATA1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define FC7_CTS_SDA_SSEL0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define USB0_FRAME_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 7) /* PIO1_5 */ +#define ADC0_CH9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER1_CAPTURE2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define CTIMER1_MATCH2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 5) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC7_SCK_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define USB0_VBUS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 7) /* PIO1_6 */ +#define ADC0_CH10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER1_CAPTURE2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 5) /* PIO1_7 */ +#define CTIMER1_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_CH11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define CTIMER1_CAPTURE3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define CTIMER1_MATCH3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 3) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define FC3_RXD_SDA_MOSI_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define USB0_UP_LED_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ADC0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_SCK_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define USB0_FRAME_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 7) /* PIO1_10 */ +#define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC4_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define FC6_RTS_SCL_SSEL1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */ +#define ADC0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC5_RXD_SDA_MOSI_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define FC7_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define UTICK0_CAPTURE2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define ADC0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_MATCH1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC5_TXD_SCL_MISO_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define FC2_RXD_SDA_MOSI_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define SCT0_OUT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define ADC0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMIC0_CLK0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC7_CTS_SDA_SSEL0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define SCT0_OUT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER0_CAPTURE0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define CTIMER0_MATCH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMIC0_DATA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC7_RTS_SCL_SSEL1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define MCLK_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define UTICK0_CAPTURE3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ + +#endif diff --git a/dts/nxp/lpc/LPC54113J256UK49-pinctrl.h b/dts/nxp/lpc/LPC54113J256UK49-pinctrl.h new file mode 100644 index 000000000..e1c82a181 --- /dev/null +++ b/dts/nxp/lpc/LPC54113J256UK49-pinctrl.h @@ -0,0 +1,1316 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54113J256UK49/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54113J256UK49_ +#define _ZEPHYR_DTS_BINDING_LPC54113J256UK49_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_CAPTURE0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define FC0_RXD_SDA_MOSI_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define FC3_CTS_SDA_SSEL0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_OUT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC0_TXD_SCL_MISO_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define FC3_RTS_SCL_SSEL1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC0_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define FC3_SSEL2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER0_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_OUT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER0_MATCH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define UTICK0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ +#define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define CTIMER0_CAPTURE2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define CTIMER0_MATCH2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC6_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SCT0_OUT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define CTIMER0_MATCH3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC2_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SCT0_OUT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define CTIMER3_CAPTURE0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define FC2_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC3_CTS_SDA_SSEL0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCT0_OUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER3_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC2_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SCT0_OUT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC3_SCK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define CTIMER2_MATCH3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_RXD_SDA_MOSI_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 2) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER2_MATCH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC3_TXD_SCL_MISO_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_OUT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER2_MATCH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_SCK_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 5) /* PIO0_14 */ +#define FC3_CTS_SDA_SSEL0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_OUT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER2_MATCH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define FC3_RTS_SCL_SSEL1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define FC4_SCK_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 5) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SWO_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CTIMER3_MATCH1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define FC3_SSEL2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define FC6_CTS_SDA_SSEL0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define SWCLK_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 5) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define CTIMER3_MATCH2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC3_SSEL3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define FC6_RTS_SCL_SSEL1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SWDIO_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 5) /* PIO0_17 */ +#define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER0_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define FC5_TXD_SCL_MISO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCT0_OUT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC5_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC0_SCK_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define FC5_RXD_SDA_MOSI_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CLKOUT_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define CTIMER3_MATCH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC0_TXD_SCL_MISO_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CLKIN_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define CTIMER3_MATCH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC0_RXD_SDA_MOSI_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC1_RTS_SCL_SSEL1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define UTICK0_CAPTURE1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_MATCH0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 5) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC1_CTS_SDA_SSEL0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 5) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC4_RTS_SCL_SSEL1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define FC6_CTS_SDA_SSEL0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC4_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER0_CAPTURE1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define CTIMER0_MATCH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER0_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC1_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define ADC0_CH1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_CAPTURE2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define CTIMER0_MATCH2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC1_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define ADC0_CH2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_CAPTURE3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define CTIMER0_MATCH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 6) /* PIO0_31 */ +#define CTIMER2_CAPTURE2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMIC0_CLK0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define FC2_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_CH3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define CTIMER3_MATCH1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMIC0_DATA0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define FC2_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_CH4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC4_TXD_SCL_MISO_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define FC5_SSEL2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define SWO_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 2) /* PIO1_1 */ +#define ADC0_CH5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define FC4_RXD_SDA_MOSI_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC5_SSEL3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define FC7_SSEL3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 2) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define MCLK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define ADC0_CH6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CTIMER0_CAPTURE1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define FC3_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC7_SSEL2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 2) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ +#define USB0_UP_LED_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_CH7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER0_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMIC0_CLK1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FC3_TXD_SCL_MISO_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define FC7_RTS_SCL_SSEL1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define ADC0_CH8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER1_CAPTURE0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define CTIMER1_MATCH3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 5) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMIC0_DATA1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define FC7_CTS_SDA_SSEL0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define USB0_FRAME_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 7) /* PIO1_5 */ +#define ADC0_CH9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER1_CAPTURE2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define CTIMER1_MATCH2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 5) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC7_SCK_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define USB0_VBUS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 7) /* PIO1_6 */ +#define ADC0_CH10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER1_CAPTURE2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 5) /* PIO1_7 */ +#define CTIMER1_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_CH11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define CTIMER1_CAPTURE3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define CTIMER1_MATCH3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 3) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ + +#endif diff --git a/dts/nxp/lpc/LPC54605J256BD100-pinctrl.h b/dts/nxp/lpc/LPC54605J256BD100-pinctrl.h new file mode 100644 index 000000000..75c6ebef2 --- /dev/null +++ b/dts/nxp/lpc/LPC54605J256BD100-pinctrl.h @@ -0,0 +1,3111 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54605J256BD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54605J256BD100_ +#define _ZEPHYR_DTS_BINDING_LPC54605J256BD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54605J256ET100-pinctrl.h b/dts/nxp/lpc/LPC54605J256ET100-pinctrl.h new file mode 100644 index 000000000..2dce6303c --- /dev/null +++ b/dts/nxp/lpc/LPC54605J256ET100-pinctrl.h @@ -0,0 +1,3111 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54605J256ET100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54605J256ET100_ +#define _ZEPHYR_DTS_BINDING_LPC54605J256ET100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54605J256ET180-pinctrl.h b/dts/nxp/lpc/LPC54605J256ET180-pinctrl.h new file mode 100644 index 000000000..8f8d5218b --- /dev/null +++ b/dts/nxp/lpc/LPC54605J256ET180-pinctrl.h @@ -0,0 +1,3516 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54605J256ET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54605J256ET180_ +#define _ZEPHYR_DTS_BINDING_LPC54605J256ET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54605J512BD100-pinctrl.h b/dts/nxp/lpc/LPC54605J512BD100-pinctrl.h new file mode 100644 index 000000000..2b05064a3 --- /dev/null +++ b/dts/nxp/lpc/LPC54605J512BD100-pinctrl.h @@ -0,0 +1,3111 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54605J512BD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54605J512BD100_ +#define _ZEPHYR_DTS_BINDING_LPC54605J512BD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54605J512ET100-pinctrl.h b/dts/nxp/lpc/LPC54605J512ET100-pinctrl.h new file mode 100644 index 000000000..7e9ae7f9f --- /dev/null +++ b/dts/nxp/lpc/LPC54605J512ET100-pinctrl.h @@ -0,0 +1,3111 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54605J512ET100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54605J512ET100_ +#define _ZEPHYR_DTS_BINDING_LPC54605J512ET100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54605J512ET180-pinctrl.h b/dts/nxp/lpc/LPC54605J512ET180-pinctrl.h new file mode 100644 index 000000000..9274f8db1 --- /dev/null +++ b/dts/nxp/lpc/LPC54605J512ET180-pinctrl.h @@ -0,0 +1,3516 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54605J512ET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54605J512ET180_ +#define _ZEPHYR_DTS_BINDING_LPC54605J512ET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54606J256BD100-pinctrl.h b/dts/nxp/lpc/LPC54606J256BD100-pinctrl.h new file mode 100644 index 000000000..dc0f2e07c --- /dev/null +++ b/dts/nxp/lpc/LPC54606J256BD100-pinctrl.h @@ -0,0 +1,3138 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54606J256BD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54606J256BD100_ +#define _ZEPHYR_DTS_BINDING_LPC54606J256BD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54606J256ET100-pinctrl.h b/dts/nxp/lpc/LPC54606J256ET100-pinctrl.h new file mode 100644 index 000000000..4522a7c1a --- /dev/null +++ b/dts/nxp/lpc/LPC54606J256ET100-pinctrl.h @@ -0,0 +1,3138 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54606J256ET100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54606J256ET100_ +#define _ZEPHYR_DTS_BINDING_LPC54606J256ET100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54606J256ET180-pinctrl.h b/dts/nxp/lpc/LPC54606J256ET180-pinctrl.h new file mode 100644 index 000000000..61245a147 --- /dev/null +++ b/dts/nxp/lpc/LPC54606J256ET180-pinctrl.h @@ -0,0 +1,3563 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54606J256ET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54606J256ET180_ +#define _ZEPHYR_DTS_BINDING_LPC54606J256ET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54606J512BD100-pinctrl.h b/dts/nxp/lpc/LPC54606J512BD100-pinctrl.h new file mode 100644 index 000000000..5e7a0837a --- /dev/null +++ b/dts/nxp/lpc/LPC54606J512BD100-pinctrl.h @@ -0,0 +1,3138 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54606J512BD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54606J512BD100_ +#define _ZEPHYR_DTS_BINDING_LPC54606J512BD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54606J512BD208-pinctrl.h b/dts/nxp/lpc/LPC54606J512BD208-pinctrl.h new file mode 100644 index 000000000..be3280efc --- /dev/null +++ b/dts/nxp/lpc/LPC54606J512BD208-pinctrl.h @@ -0,0 +1,3758 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54606J512BD208/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54606J512BD208_ +#define _ZEPHYR_DTS_BINDING_LPC54606J512BD208_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ +#define CAN1_TD_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 2) /* PIO4_17 */ +#define CTIMER1_CAPTURE2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 3) /* PIO4_17 */ +#define EMC_EMC_BLS2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 6) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 0) /* PIO4_17 */ +#define UTICK0_CAPTURE0_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 4) /* PIO4_17 */ +#define CAN1_RD_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 2) /* PIO4_18 */ +#define CTIMER1_CAPTURE3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 3) /* PIO4_18 */ +#define EMC_EMC_BLS3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 6) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 0) /* PIO4_18 */ +#define UTICK0_CAPTURE1_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 4) /* PIO4_18 */ +#define CTIMER4_CAPTURE2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 4) /* PIO4_19 */ +#define EMC_EMC_DQM2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 6) /* PIO4_19 */ +#define ENET_ENET_TXD0_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 1) /* PIO4_19 */ +#define FC2_SCK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 3) /* PIO4_19 */ +#define GPIO_PIO419_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 0) /* PIO4_19 */ +#define SD_CLK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 2) /* PIO4_19 */ +#define CTIMER4_CAPTURE3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 4) /* PIO4_20 */ +#define EMC_EMC_DQM3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 6) /* PIO4_20 */ +#define ENET_ENET_TXD1_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 1) /* PIO4_20 */ +#define FC2_RXD_SDA_MOSI_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 3) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 0) /* PIO4_20 */ +#define SD_CMD_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 2) /* PIO4_20 */ +#define CTIMER2_MATCH3_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 4) /* PIO4_21 */ +#define EMC_EMC_D16_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 6) /* PIO4_21 */ +#define ENET_ENET_TXD2_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 1) /* PIO4_21 */ +#define FC2_TXD_SCL_MISO_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 3) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 0) /* PIO4_21 */ +#define SD_POW_EN_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 2) /* PIO4_21 */ +#define CTIMER1_MATCH3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 4) /* PIO4_22 */ +#define EMC_EMC_D17_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 6) /* PIO4_22 */ +#define ENET_ENET_TXD3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 1) /* PIO4_22 */ +#define FC2_RTS_SCL_SSEL1_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 3) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 0) /* PIO4_22 */ +#define SD_CARD_DET_N_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 2) /* PIO4_22 */ +#define CTIMER1_MATCH0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 5) /* PIO4_23 */ +#define EMC_EMC_D18_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 6) /* PIO4_23 */ +#define ENET_ENET_RXD0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 1) /* PIO4_23 */ +#define FC2_CTS_SDA_SSEL0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 3) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 0) /* PIO4_23 */ +#define SD_WR_PRT_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 2) /* PIO4_23 */ +#define CTIMER1_MATCH1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 5) /* PIO4_24 */ +#define EMC_EMC_D19_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 6) /* PIO4_24 */ +#define ENET_ENET_RXD1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 1) /* PIO4_24 */ +#define FC7_RTS_SCL_SSEL1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 3) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 0) /* PIO4_24 */ +#define SD_CARD_INT_N_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 2) /* PIO4_24 */ +#define CTIMER1_MATCH2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 5) /* PIO4_25 */ +#define EMC_EMC_D20_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 6) /* PIO4_25 */ +#define ENET_ENET_RXD2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 1) /* PIO4_25 */ +#define FC7_CTS_SDA_SSEL0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 3) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 0) /* PIO4_25 */ +#define SDIF_SD_D0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 2) /* PIO4_25 */ +#define CTIMER1_MATCH3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 5) /* PIO4_26 */ +#define EMC_EMC_D21_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 6) /* PIO4_26 */ +#define ENET_ENET_RXD3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 1) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 0) /* PIO4_26 */ +#define SDIF_SD_D1_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 2) /* PIO4_26 */ +#define UTICK0_CAPTURE2_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 4) /* PIO4_26 */ +#define CTIMER1_CAPTURE0_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 5) /* PIO4_27 */ +#define EMC_EMC_D22_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 6) /* PIO4_27 */ +#define ENET_TX_EN_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 1) /* PIO4_27 */ +#define FC1_SCK_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 4) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 0) /* PIO4_27 */ +#define SDIF_SD_D2_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 2) /* PIO4_27 */ +#define CTIMER1_CAPTURE1_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 5) /* PIO4_28 */ +#define EMC_EMC_D23_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 6) /* PIO4_28 */ +#define ENET_TX_ER_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 1) /* PIO4_28 */ +#define FC1_RXD_SDA_MOSI_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 4) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 0) /* PIO4_28 */ +#define SDIF_SD_D3_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 2) /* PIO4_28 */ +#define CTIMER1_CAPTURE2_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 5) /* PIO4_29 */ +#define EMC_EMC_D24_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 6) /* PIO4_29 */ +#define ENET_RX_ER_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 1) /* PIO4_29 */ +#define FC1_TXD_SCL_MISO_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 4) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 0) /* PIO4_29 */ +#define SDIF_SD_D4_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 2) /* PIO4_29 */ +#define CTIMER1_CAPTURE3_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 5) /* PIO4_30 */ +#define CTIMER3_MATCH0_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 3) /* PIO4_30 */ +#define EMC_EMC_D25_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 6) /* PIO4_30 */ +#define ENET_TX_CLK_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 1) /* PIO4_30 */ +#define FC1_RTS_SCL_SSEL1_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 4) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 0) /* PIO4_30 */ +#define SDIF_SD_D5_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 2) /* PIO4_30 */ +#define CTIMER3_MATCH1_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 3) /* PIO4_31 */ +#define EMC_EMC_D26_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 6) /* PIO4_31 */ +#define ENET_RX_CLK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 1) /* PIO4_31 */ +#define FC4_SCK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 4) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 0) /* PIO4_31 */ +#define SDIF_SD_D6_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 2) /* PIO4_31 */ +#define CTIMER3_MATCH2_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 3) /* PIO5_0 */ +#define EMC_EMC_D27_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 6) /* PIO5_0 */ +#define ENET_RX_DV_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 1) /* PIO5_0 */ +#define FC4_RXD_SDA_MOSI_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 4) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 0) /* PIO5_0 */ +#define SDIF_SD_D7_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 2) /* PIO5_0 */ +#define CTIMER3_MATCH3_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 3) /* PIO5_1 */ +#define EMC_EMC_D28_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 6) /* PIO5_1 */ +#define ENET_CRS_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 1) /* PIO5_1 */ +#define FC4_TXD_SCL_MISO_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 4) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 0) /* PIO5_1 */ +#define SDIF_SD_VOLT0_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 2) /* PIO5_1 */ +#define CTIMER3_CAPTURE0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 3) /* PIO5_2 */ +#define EMC_EMC_D29_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 6) /* PIO5_2 */ +#define ENET_COL_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 1) /* PIO5_2 */ +#define FC4_CTS_SDA_SSEL0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 4) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 0) /* PIO5_2 */ +#define SDIF_SD_VOLT1_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 2) /* PIO5_2 */ +#define CTIMER3_CAPTURE1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 3) /* PIO5_3 */ +#define EMC_EMC_D30_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 6) /* PIO5_3 */ +#define ENET_MDC_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 1) /* PIO5_3 */ +#define FC4_RTS_SCL_SSEL1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 4) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 0) /* PIO5_3 */ +#define SDIF_SD_VOLT2_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 2) /* PIO5_3 */ +#define CTIMER3_CAPTURE2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 3) /* PIO5_4 */ +#define EMC_EMC_D31_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 6) /* PIO5_4 */ +#define ENET_MDIO_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 1) /* PIO5_4 */ +#define FC4_SSEL2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 0) /* PIO5_4 */ +#define SD_BACKEND_PWR_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 2) /* PIO5_4 */ +#define CTIMER3_CAPTURE3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 3) /* PIO5_5 */ +#define DMIC0_CLK1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 2) /* PIO5_5 */ +#define EMC_EMC_A21_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 6) /* PIO5_5 */ +#define FC4_SSEL3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 4) /* PIO5_5 */ +#define GPIO_PIO55_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 0) /* PIO5_5 */ +#define SCT0_IN0_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN2_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN4_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN5_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN6_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define TRACECLK_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 5) /* PIO5_5 */ +#define DMIC0_DATA1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 2) /* PIO5_6 */ +#define EMC_EMC_A22_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 6) /* PIO5_6 */ +#define FC5_SCK_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 3) /* PIO5_6 */ +#define GPIO_PIO56_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 0) /* PIO5_6 */ +#define SCT0_IN0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN2_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN3_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN4_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN6_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_OUT5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 4) /* PIO5_6 */ +#define SWD_TRACEDATA0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 5) /* PIO5_6 */ +#define EMC_EMC_A23_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 6) /* PIO5_7 */ +#define FC5_RXD_SDA_MOSI_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 3) /* PIO5_7 */ +#define GPIO_PIO57_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 0) /* PIO5_7 */ +#define MCLK_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 2) /* PIO5_7 */ +#define SCT0_IN0_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN2_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN3_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN4_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN5_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_OUT6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 4) /* PIO5_7 */ +#define SWD_TRACEDATA1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 5) /* PIO5_7 */ +#define DMIC0_CLK0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 2) /* PIO5_8 */ +#define EMC_EMC_A24_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 6) /* PIO5_8 */ +#define FC5_TXD_SCL_MISO_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 3) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 0) /* PIO5_8 */ +#define SCT0_IN0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN1_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN3_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN4_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN5_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN6_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_OUT7_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 4) /* PIO5_8 */ +#define SWD_TRACEDATA2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 5) /* PIO5_8 */ +#define DMIC0_DATA0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 2) /* PIO5_9 */ +#define EMC_EMC_A25_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 6) /* PIO5_9 */ +#define FC5_CTS_SDA_SSEL0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 3) /* PIO5_9 */ +#define GPIO_PIO59_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 0) /* PIO5_9 */ +#define SCT0_IN0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN1_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN2_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN4_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN5_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN6_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_OUT8_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 4) /* PIO5_9 */ +#define SWD_TRACEDATA3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 5) /* PIO5_9 */ +#define FC5_RTS_SCL_SSEL1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 3) /* PIO5_10 */ +#define GPIO_PIO510_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 0) /* PIO5_10 */ +#define SCT0_IN0_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN2_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN4_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN5_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN6_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_OUT9_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 4) /* PIO5_10 */ +#define UTICK0_CAPTURE3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 5) /* PIO5_10 */ + +#endif diff --git a/dts/nxp/lpc/LPC54606J512ET100-pinctrl.h b/dts/nxp/lpc/LPC54606J512ET100-pinctrl.h new file mode 100644 index 000000000..b6643e6d1 --- /dev/null +++ b/dts/nxp/lpc/LPC54606J512ET100-pinctrl.h @@ -0,0 +1,3138 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54606J512ET100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54606J512ET100_ +#define _ZEPHYR_DTS_BINDING_LPC54606J512ET100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54607J256BD208-pinctrl.h b/dts/nxp/lpc/LPC54607J256BD208-pinctrl.h new file mode 100644 index 000000000..5e9bf2cb9 --- /dev/null +++ b/dts/nxp/lpc/LPC54607J256BD208-pinctrl.h @@ -0,0 +1,3726 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54607J256BD208/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54607J256BD208_ +#define _ZEPHYR_DTS_BINDING_LPC54607J256BD208_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ +#define CTIMER1_CAPTURE2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 3) /* PIO4_17 */ +#define EMC_EMC_BLS2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 6) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 0) /* PIO4_17 */ +#define UTICK0_CAPTURE0_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 4) /* PIO4_17 */ +#define CTIMER1_CAPTURE3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 3) /* PIO4_18 */ +#define EMC_EMC_BLS3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 6) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 0) /* PIO4_18 */ +#define UTICK0_CAPTURE1_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 4) /* PIO4_18 */ +#define CTIMER4_CAPTURE2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 4) /* PIO4_19 */ +#define EMC_EMC_DQM2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 6) /* PIO4_19 */ +#define FC2_SCK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 3) /* PIO4_19 */ +#define GPIO_PIO419_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 0) /* PIO4_19 */ +#define SD_CLK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 2) /* PIO4_19 */ +#define CTIMER4_CAPTURE3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 4) /* PIO4_20 */ +#define EMC_EMC_DQM3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 6) /* PIO4_20 */ +#define FC2_RXD_SDA_MOSI_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 3) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 0) /* PIO4_20 */ +#define SD_CMD_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 2) /* PIO4_20 */ +#define CTIMER2_MATCH3_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 4) /* PIO4_21 */ +#define EMC_EMC_D16_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 6) /* PIO4_21 */ +#define FC2_TXD_SCL_MISO_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 3) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 0) /* PIO4_21 */ +#define SD_POW_EN_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 2) /* PIO4_21 */ +#define CTIMER1_MATCH3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 4) /* PIO4_22 */ +#define EMC_EMC_D17_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 6) /* PIO4_22 */ +#define FC2_RTS_SCL_SSEL1_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 3) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 0) /* PIO4_22 */ +#define SD_CARD_DET_N_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 2) /* PIO4_22 */ +#define CTIMER1_MATCH0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 5) /* PIO4_23 */ +#define EMC_EMC_D18_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 6) /* PIO4_23 */ +#define FC2_CTS_SDA_SSEL0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 3) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 0) /* PIO4_23 */ +#define SD_WR_PRT_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 2) /* PIO4_23 */ +#define CTIMER1_MATCH1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 5) /* PIO4_24 */ +#define EMC_EMC_D19_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 6) /* PIO4_24 */ +#define FC7_RTS_SCL_SSEL1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 3) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 0) /* PIO4_24 */ +#define SD_CARD_INT_N_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 2) /* PIO4_24 */ +#define CTIMER1_MATCH2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 5) /* PIO4_25 */ +#define EMC_EMC_D20_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 6) /* PIO4_25 */ +#define FC7_CTS_SDA_SSEL0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 3) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 0) /* PIO4_25 */ +#define SDIF_SD_D0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 2) /* PIO4_25 */ +#define CTIMER1_MATCH3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 5) /* PIO4_26 */ +#define EMC_EMC_D21_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 6) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 0) /* PIO4_26 */ +#define SDIF_SD_D1_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 2) /* PIO4_26 */ +#define UTICK0_CAPTURE2_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 4) /* PIO4_26 */ +#define CTIMER1_CAPTURE0_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 5) /* PIO4_27 */ +#define EMC_EMC_D22_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 6) /* PIO4_27 */ +#define FC1_SCK_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 4) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 0) /* PIO4_27 */ +#define SDIF_SD_D2_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 2) /* PIO4_27 */ +#define CTIMER1_CAPTURE1_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 5) /* PIO4_28 */ +#define EMC_EMC_D23_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 6) /* PIO4_28 */ +#define FC1_RXD_SDA_MOSI_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 4) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 0) /* PIO4_28 */ +#define SDIF_SD_D3_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 2) /* PIO4_28 */ +#define CTIMER1_CAPTURE2_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 5) /* PIO4_29 */ +#define EMC_EMC_D24_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 6) /* PIO4_29 */ +#define FC1_TXD_SCL_MISO_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 4) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 0) /* PIO4_29 */ +#define SDIF_SD_D4_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 2) /* PIO4_29 */ +#define CTIMER1_CAPTURE3_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 5) /* PIO4_30 */ +#define CTIMER3_MATCH0_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 3) /* PIO4_30 */ +#define EMC_EMC_D25_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 6) /* PIO4_30 */ +#define FC1_RTS_SCL_SSEL1_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 4) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 0) /* PIO4_30 */ +#define SDIF_SD_D5_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 2) /* PIO4_30 */ +#define CTIMER3_MATCH1_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 3) /* PIO4_31 */ +#define EMC_EMC_D26_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 6) /* PIO4_31 */ +#define FC4_SCK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 4) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 0) /* PIO4_31 */ +#define SDIF_SD_D6_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 2) /* PIO4_31 */ +#define CTIMER3_MATCH2_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 3) /* PIO5_0 */ +#define EMC_EMC_D27_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 6) /* PIO5_0 */ +#define FC4_RXD_SDA_MOSI_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 4) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 0) /* PIO5_0 */ +#define SDIF_SD_D7_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 2) /* PIO5_0 */ +#define CTIMER3_MATCH3_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 3) /* PIO5_1 */ +#define EMC_EMC_D28_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 6) /* PIO5_1 */ +#define FC4_TXD_SCL_MISO_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 4) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 0) /* PIO5_1 */ +#define SDIF_SD_VOLT0_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 2) /* PIO5_1 */ +#define CTIMER3_CAPTURE0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 3) /* PIO5_2 */ +#define EMC_EMC_D29_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 6) /* PIO5_2 */ +#define FC4_CTS_SDA_SSEL0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 4) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 0) /* PIO5_2 */ +#define SDIF_SD_VOLT1_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 2) /* PIO5_2 */ +#define CTIMER3_CAPTURE1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 3) /* PIO5_3 */ +#define EMC_EMC_D30_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 6) /* PIO5_3 */ +#define FC4_RTS_SCL_SSEL1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 4) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 0) /* PIO5_3 */ +#define SDIF_SD_VOLT2_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 2) /* PIO5_3 */ +#define CTIMER3_CAPTURE2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 3) /* PIO5_4 */ +#define EMC_EMC_D31_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 6) /* PIO5_4 */ +#define FC4_SSEL2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 0) /* PIO5_4 */ +#define SD_BACKEND_PWR_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 2) /* PIO5_4 */ +#define CTIMER3_CAPTURE3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 3) /* PIO5_5 */ +#define DMIC0_CLK1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 2) /* PIO5_5 */ +#define EMC_EMC_A21_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 6) /* PIO5_5 */ +#define FC4_SSEL3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 4) /* PIO5_5 */ +#define GPIO_PIO55_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 0) /* PIO5_5 */ +#define SCT0_IN0_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN2_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN4_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN5_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN6_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define TRACECLK_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 5) /* PIO5_5 */ +#define DMIC0_DATA1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 2) /* PIO5_6 */ +#define EMC_EMC_A22_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 6) /* PIO5_6 */ +#define FC5_SCK_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 3) /* PIO5_6 */ +#define GPIO_PIO56_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 0) /* PIO5_6 */ +#define SCT0_IN0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN2_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN3_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN4_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN6_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_OUT5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 4) /* PIO5_6 */ +#define SWD_TRACEDATA0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 5) /* PIO5_6 */ +#define EMC_EMC_A23_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 6) /* PIO5_7 */ +#define FC5_RXD_SDA_MOSI_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 3) /* PIO5_7 */ +#define GPIO_PIO57_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 0) /* PIO5_7 */ +#define MCLK_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 2) /* PIO5_7 */ +#define SCT0_IN0_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN2_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN3_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN4_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN5_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_OUT6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 4) /* PIO5_7 */ +#define SWD_TRACEDATA1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 5) /* PIO5_7 */ +#define DMIC0_CLK0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 2) /* PIO5_8 */ +#define EMC_EMC_A24_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 6) /* PIO5_8 */ +#define FC5_TXD_SCL_MISO_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 3) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 0) /* PIO5_8 */ +#define SCT0_IN0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN1_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN3_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN4_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN5_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN6_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_OUT7_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 4) /* PIO5_8 */ +#define SWD_TRACEDATA2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 5) /* PIO5_8 */ +#define DMIC0_DATA0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 2) /* PIO5_9 */ +#define EMC_EMC_A25_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 6) /* PIO5_9 */ +#define FC5_CTS_SDA_SSEL0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 3) /* PIO5_9 */ +#define GPIO_PIO59_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 0) /* PIO5_9 */ +#define SCT0_IN0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN1_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN2_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN4_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN5_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN6_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_OUT8_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 4) /* PIO5_9 */ +#define SWD_TRACEDATA3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 5) /* PIO5_9 */ +#define FC5_RTS_SCL_SSEL1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 3) /* PIO5_10 */ +#define GPIO_PIO510_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 0) /* PIO5_10 */ +#define SCT0_IN0_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN2_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN4_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN5_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN6_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_OUT9_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 4) /* PIO5_10 */ +#define UTICK0_CAPTURE3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 5) /* PIO5_10 */ + +#endif diff --git a/dts/nxp/lpc/LPC54607J256ET180-pinctrl.h b/dts/nxp/lpc/LPC54607J256ET180-pinctrl.h new file mode 100644 index 000000000..e02ee1d66 --- /dev/null +++ b/dts/nxp/lpc/LPC54607J256ET180-pinctrl.h @@ -0,0 +1,3551 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54607J256ET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54607J256ET180_ +#define _ZEPHYR_DTS_BINDING_LPC54607J256ET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54607J512ET180-pinctrl.h b/dts/nxp/lpc/LPC54607J512ET180-pinctrl.h new file mode 100644 index 000000000..6d8a39df2 --- /dev/null +++ b/dts/nxp/lpc/LPC54607J512ET180-pinctrl.h @@ -0,0 +1,3551 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54607J512ET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54607J512ET180_ +#define _ZEPHYR_DTS_BINDING_LPC54607J512ET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54608J512BD208-pinctrl.h b/dts/nxp/lpc/LPC54608J512BD208-pinctrl.h new file mode 100644 index 000000000..0b017cd1c --- /dev/null +++ b/dts/nxp/lpc/LPC54608J512BD208-pinctrl.h @@ -0,0 +1,3793 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54608J512BD208/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54608J512BD208_ +#define _ZEPHYR_DTS_BINDING_LPC54608J512BD208_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ +#define CAN1_TD_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 2) /* PIO4_17 */ +#define CTIMER1_CAPTURE2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 3) /* PIO4_17 */ +#define EMC_EMC_BLS2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 6) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 0) /* PIO4_17 */ +#define UTICK0_CAPTURE0_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 4) /* PIO4_17 */ +#define CAN1_RD_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 2) /* PIO4_18 */ +#define CTIMER1_CAPTURE3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 3) /* PIO4_18 */ +#define EMC_EMC_BLS3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 6) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 0) /* PIO4_18 */ +#define UTICK0_CAPTURE1_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 4) /* PIO4_18 */ +#define CTIMER4_CAPTURE2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 4) /* PIO4_19 */ +#define EMC_EMC_DQM2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 6) /* PIO4_19 */ +#define ENET_ENET_TXD0_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 1) /* PIO4_19 */ +#define FC2_SCK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 3) /* PIO4_19 */ +#define GPIO_PIO419_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 0) /* PIO4_19 */ +#define SD_CLK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 2) /* PIO4_19 */ +#define CTIMER4_CAPTURE3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 4) /* PIO4_20 */ +#define EMC_EMC_DQM3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 6) /* PIO4_20 */ +#define ENET_ENET_TXD1_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 1) /* PIO4_20 */ +#define FC2_RXD_SDA_MOSI_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 3) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 0) /* PIO4_20 */ +#define SD_CMD_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 2) /* PIO4_20 */ +#define CTIMER2_MATCH3_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 4) /* PIO4_21 */ +#define EMC_EMC_D16_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 6) /* PIO4_21 */ +#define ENET_ENET_TXD2_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 1) /* PIO4_21 */ +#define FC2_TXD_SCL_MISO_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 3) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 0) /* PIO4_21 */ +#define SD_POW_EN_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 2) /* PIO4_21 */ +#define CTIMER1_MATCH3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 4) /* PIO4_22 */ +#define EMC_EMC_D17_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 6) /* PIO4_22 */ +#define ENET_ENET_TXD3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 1) /* PIO4_22 */ +#define FC2_RTS_SCL_SSEL1_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 3) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 0) /* PIO4_22 */ +#define SD_CARD_DET_N_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 2) /* PIO4_22 */ +#define CTIMER1_MATCH0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 5) /* PIO4_23 */ +#define EMC_EMC_D18_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 6) /* PIO4_23 */ +#define ENET_ENET_RXD0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 1) /* PIO4_23 */ +#define FC2_CTS_SDA_SSEL0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 3) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 0) /* PIO4_23 */ +#define SD_WR_PRT_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 2) /* PIO4_23 */ +#define CTIMER1_MATCH1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 5) /* PIO4_24 */ +#define EMC_EMC_D19_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 6) /* PIO4_24 */ +#define ENET_ENET_RXD1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 1) /* PIO4_24 */ +#define FC7_RTS_SCL_SSEL1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 3) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 0) /* PIO4_24 */ +#define SD_CARD_INT_N_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 2) /* PIO4_24 */ +#define CTIMER1_MATCH2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 5) /* PIO4_25 */ +#define EMC_EMC_D20_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 6) /* PIO4_25 */ +#define ENET_ENET_RXD2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 1) /* PIO4_25 */ +#define FC7_CTS_SDA_SSEL0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 3) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 0) /* PIO4_25 */ +#define SDIF_SD_D0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 2) /* PIO4_25 */ +#define CTIMER1_MATCH3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 5) /* PIO4_26 */ +#define EMC_EMC_D21_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 6) /* PIO4_26 */ +#define ENET_ENET_RXD3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 1) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 0) /* PIO4_26 */ +#define SDIF_SD_D1_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 2) /* PIO4_26 */ +#define UTICK0_CAPTURE2_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 4) /* PIO4_26 */ +#define CTIMER1_CAPTURE0_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 5) /* PIO4_27 */ +#define EMC_EMC_D22_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 6) /* PIO4_27 */ +#define ENET_TX_EN_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 1) /* PIO4_27 */ +#define FC1_SCK_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 4) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 0) /* PIO4_27 */ +#define SDIF_SD_D2_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 2) /* PIO4_27 */ +#define CTIMER1_CAPTURE1_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 5) /* PIO4_28 */ +#define EMC_EMC_D23_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 6) /* PIO4_28 */ +#define ENET_TX_ER_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 1) /* PIO4_28 */ +#define FC1_RXD_SDA_MOSI_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 4) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 0) /* PIO4_28 */ +#define SDIF_SD_D3_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 2) /* PIO4_28 */ +#define CTIMER1_CAPTURE2_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 5) /* PIO4_29 */ +#define EMC_EMC_D24_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 6) /* PIO4_29 */ +#define ENET_RX_ER_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 1) /* PIO4_29 */ +#define FC1_TXD_SCL_MISO_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 4) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 0) /* PIO4_29 */ +#define SDIF_SD_D4_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 2) /* PIO4_29 */ +#define CTIMER1_CAPTURE3_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 5) /* PIO4_30 */ +#define CTIMER3_MATCH0_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 3) /* PIO4_30 */ +#define EMC_EMC_D25_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 6) /* PIO4_30 */ +#define ENET_TX_CLK_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 1) /* PIO4_30 */ +#define FC1_RTS_SCL_SSEL1_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 4) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 0) /* PIO4_30 */ +#define SDIF_SD_D5_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 2) /* PIO4_30 */ +#define CTIMER3_MATCH1_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 3) /* PIO4_31 */ +#define EMC_EMC_D26_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 6) /* PIO4_31 */ +#define ENET_RX_CLK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 1) /* PIO4_31 */ +#define FC4_SCK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 4) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 0) /* PIO4_31 */ +#define SDIF_SD_D6_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 2) /* PIO4_31 */ +#define CTIMER3_MATCH2_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 3) /* PIO5_0 */ +#define EMC_EMC_D27_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 6) /* PIO5_0 */ +#define ENET_RX_DV_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 1) /* PIO5_0 */ +#define FC4_RXD_SDA_MOSI_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 4) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 0) /* PIO5_0 */ +#define SDIF_SD_D7_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 2) /* PIO5_0 */ +#define CTIMER3_MATCH3_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 3) /* PIO5_1 */ +#define EMC_EMC_D28_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 6) /* PIO5_1 */ +#define ENET_CRS_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 1) /* PIO5_1 */ +#define FC4_TXD_SCL_MISO_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 4) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 0) /* PIO5_1 */ +#define SDIF_SD_VOLT0_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 2) /* PIO5_1 */ +#define CTIMER3_CAPTURE0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 3) /* PIO5_2 */ +#define EMC_EMC_D29_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 6) /* PIO5_2 */ +#define ENET_COL_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 1) /* PIO5_2 */ +#define FC4_CTS_SDA_SSEL0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 4) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 0) /* PIO5_2 */ +#define SDIF_SD_VOLT1_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 2) /* PIO5_2 */ +#define CTIMER3_CAPTURE1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 3) /* PIO5_3 */ +#define EMC_EMC_D30_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 6) /* PIO5_3 */ +#define ENET_MDC_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 1) /* PIO5_3 */ +#define FC4_RTS_SCL_SSEL1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 4) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 0) /* PIO5_3 */ +#define SDIF_SD_VOLT2_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 2) /* PIO5_3 */ +#define CTIMER3_CAPTURE2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 3) /* PIO5_4 */ +#define EMC_EMC_D31_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 6) /* PIO5_4 */ +#define ENET_MDIO_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 1) /* PIO5_4 */ +#define FC4_SSEL2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 0) /* PIO5_4 */ +#define SD_BACKEND_PWR_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 2) /* PIO5_4 */ +#define CTIMER3_CAPTURE3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 3) /* PIO5_5 */ +#define DMIC0_CLK1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 2) /* PIO5_5 */ +#define EMC_EMC_A21_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 6) /* PIO5_5 */ +#define FC4_SSEL3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 4) /* PIO5_5 */ +#define GPIO_PIO55_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 0) /* PIO5_5 */ +#define SCT0_IN0_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN2_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN4_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN5_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN6_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define TRACECLK_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 5) /* PIO5_5 */ +#define DMIC0_DATA1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 2) /* PIO5_6 */ +#define EMC_EMC_A22_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 6) /* PIO5_6 */ +#define FC5_SCK_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 3) /* PIO5_6 */ +#define GPIO_PIO56_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 0) /* PIO5_6 */ +#define SCT0_IN0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN2_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN3_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN4_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN6_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_OUT5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 4) /* PIO5_6 */ +#define SWD_TRACEDATA0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 5) /* PIO5_6 */ +#define EMC_EMC_A23_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 6) /* PIO5_7 */ +#define FC5_RXD_SDA_MOSI_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 3) /* PIO5_7 */ +#define GPIO_PIO57_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 0) /* PIO5_7 */ +#define MCLK_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 2) /* PIO5_7 */ +#define SCT0_IN0_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN2_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN3_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN4_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN5_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_OUT6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 4) /* PIO5_7 */ +#define SWD_TRACEDATA1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 5) /* PIO5_7 */ +#define DMIC0_CLK0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 2) /* PIO5_8 */ +#define EMC_EMC_A24_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 6) /* PIO5_8 */ +#define FC5_TXD_SCL_MISO_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 3) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 0) /* PIO5_8 */ +#define SCT0_IN0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN1_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN3_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN4_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN5_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN6_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_OUT7_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 4) /* PIO5_8 */ +#define SWD_TRACEDATA2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 5) /* PIO5_8 */ +#define DMIC0_DATA0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 2) /* PIO5_9 */ +#define EMC_EMC_A25_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 6) /* PIO5_9 */ +#define FC5_CTS_SDA_SSEL0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 3) /* PIO5_9 */ +#define GPIO_PIO59_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 0) /* PIO5_9 */ +#define SCT0_IN0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN1_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN2_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN4_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN5_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN6_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_OUT8_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 4) /* PIO5_9 */ +#define SWD_TRACEDATA3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 5) /* PIO5_9 */ +#define FC5_RTS_SCL_SSEL1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 3) /* PIO5_10 */ +#define GPIO_PIO510_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 0) /* PIO5_10 */ +#define SCT0_IN0_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN2_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN4_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN5_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN6_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_OUT9_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 4) /* PIO5_10 */ +#define UTICK0_CAPTURE3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 5) /* PIO5_10 */ + +#endif diff --git a/dts/nxp/lpc/LPC54608J512ET180-pinctrl.h b/dts/nxp/lpc/LPC54608J512ET180-pinctrl.h new file mode 100644 index 000000000..b8766e578 --- /dev/null +++ b/dts/nxp/lpc/LPC54608J512ET180-pinctrl.h @@ -0,0 +1,3598 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54608J512ET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54608J512ET180_ +#define _ZEPHYR_DTS_BINDING_LPC54608J512ET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54616J256ET180-pinctrl.h b/dts/nxp/lpc/LPC54616J256ET180-pinctrl.h new file mode 100644 index 000000000..3c51cf47e --- /dev/null +++ b/dts/nxp/lpc/LPC54616J256ET180-pinctrl.h @@ -0,0 +1,3563 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54616J256ET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54616J256ET180_ +#define _ZEPHYR_DTS_BINDING_LPC54616J256ET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54616J512BD100-pinctrl.h b/dts/nxp/lpc/LPC54616J512BD100-pinctrl.h new file mode 100644 index 000000000..5c8b4408e --- /dev/null +++ b/dts/nxp/lpc/LPC54616J512BD100-pinctrl.h @@ -0,0 +1,3138 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54616J512BD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54616J512BD100_ +#define _ZEPHYR_DTS_BINDING_LPC54616J512BD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54616J512BD208-pinctrl.h b/dts/nxp/lpc/LPC54616J512BD208-pinctrl.h new file mode 100644 index 000000000..75a054443 --- /dev/null +++ b/dts/nxp/lpc/LPC54616J512BD208-pinctrl.h @@ -0,0 +1,3758 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54616J512BD208/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54616J512BD208_ +#define _ZEPHYR_DTS_BINDING_LPC54616J512BD208_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ +#define CAN1_TD_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 2) /* PIO4_17 */ +#define CTIMER1_CAPTURE2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 3) /* PIO4_17 */ +#define EMC_EMC_BLS2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 6) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 0) /* PIO4_17 */ +#define UTICK0_CAPTURE0_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 4) /* PIO4_17 */ +#define CAN1_RD_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 2) /* PIO4_18 */ +#define CTIMER1_CAPTURE3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 3) /* PIO4_18 */ +#define EMC_EMC_BLS3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 6) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 0) /* PIO4_18 */ +#define UTICK0_CAPTURE1_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 4) /* PIO4_18 */ +#define CTIMER4_CAPTURE2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 4) /* PIO4_19 */ +#define EMC_EMC_DQM2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 6) /* PIO4_19 */ +#define ENET_ENET_TXD0_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 1) /* PIO4_19 */ +#define FC2_SCK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 3) /* PIO4_19 */ +#define GPIO_PIO419_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 0) /* PIO4_19 */ +#define SD_CLK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 2) /* PIO4_19 */ +#define CTIMER4_CAPTURE3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 4) /* PIO4_20 */ +#define EMC_EMC_DQM3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 6) /* PIO4_20 */ +#define ENET_ENET_TXD1_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 1) /* PIO4_20 */ +#define FC2_RXD_SDA_MOSI_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 3) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 0) /* PIO4_20 */ +#define SD_CMD_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 2) /* PIO4_20 */ +#define CTIMER2_MATCH3_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 4) /* PIO4_21 */ +#define EMC_EMC_D16_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 6) /* PIO4_21 */ +#define ENET_ENET_TXD2_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 1) /* PIO4_21 */ +#define FC2_TXD_SCL_MISO_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 3) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 0) /* PIO4_21 */ +#define SD_POW_EN_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 2) /* PIO4_21 */ +#define CTIMER1_MATCH3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 4) /* PIO4_22 */ +#define EMC_EMC_D17_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 6) /* PIO4_22 */ +#define ENET_ENET_TXD3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 1) /* PIO4_22 */ +#define FC2_RTS_SCL_SSEL1_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 3) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 0) /* PIO4_22 */ +#define SD_CARD_DET_N_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 2) /* PIO4_22 */ +#define CTIMER1_MATCH0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 5) /* PIO4_23 */ +#define EMC_EMC_D18_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 6) /* PIO4_23 */ +#define ENET_ENET_RXD0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 1) /* PIO4_23 */ +#define FC2_CTS_SDA_SSEL0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 3) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 0) /* PIO4_23 */ +#define SD_WR_PRT_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 2) /* PIO4_23 */ +#define CTIMER1_MATCH1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 5) /* PIO4_24 */ +#define EMC_EMC_D19_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 6) /* PIO4_24 */ +#define ENET_ENET_RXD1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 1) /* PIO4_24 */ +#define FC7_RTS_SCL_SSEL1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 3) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 0) /* PIO4_24 */ +#define SD_CARD_INT_N_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 2) /* PIO4_24 */ +#define CTIMER1_MATCH2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 5) /* PIO4_25 */ +#define EMC_EMC_D20_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 6) /* PIO4_25 */ +#define ENET_ENET_RXD2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 1) /* PIO4_25 */ +#define FC7_CTS_SDA_SSEL0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 3) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 0) /* PIO4_25 */ +#define SDIF_SD_D0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 2) /* PIO4_25 */ +#define CTIMER1_MATCH3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 5) /* PIO4_26 */ +#define EMC_EMC_D21_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 6) /* PIO4_26 */ +#define ENET_ENET_RXD3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 1) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 0) /* PIO4_26 */ +#define SDIF_SD_D1_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 2) /* PIO4_26 */ +#define UTICK0_CAPTURE2_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 4) /* PIO4_26 */ +#define CTIMER1_CAPTURE0_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 5) /* PIO4_27 */ +#define EMC_EMC_D22_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 6) /* PIO4_27 */ +#define ENET_TX_EN_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 1) /* PIO4_27 */ +#define FC1_SCK_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 4) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 0) /* PIO4_27 */ +#define SDIF_SD_D2_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 2) /* PIO4_27 */ +#define CTIMER1_CAPTURE1_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 5) /* PIO4_28 */ +#define EMC_EMC_D23_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 6) /* PIO4_28 */ +#define ENET_TX_ER_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 1) /* PIO4_28 */ +#define FC1_RXD_SDA_MOSI_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 4) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 0) /* PIO4_28 */ +#define SDIF_SD_D3_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 2) /* PIO4_28 */ +#define CTIMER1_CAPTURE2_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 5) /* PIO4_29 */ +#define EMC_EMC_D24_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 6) /* PIO4_29 */ +#define ENET_RX_ER_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 1) /* PIO4_29 */ +#define FC1_TXD_SCL_MISO_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 4) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 0) /* PIO4_29 */ +#define SDIF_SD_D4_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 2) /* PIO4_29 */ +#define CTIMER1_CAPTURE3_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 5) /* PIO4_30 */ +#define CTIMER3_MATCH0_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 3) /* PIO4_30 */ +#define EMC_EMC_D25_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 6) /* PIO4_30 */ +#define ENET_TX_CLK_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 1) /* PIO4_30 */ +#define FC1_RTS_SCL_SSEL1_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 4) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 0) /* PIO4_30 */ +#define SDIF_SD_D5_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 2) /* PIO4_30 */ +#define CTIMER3_MATCH1_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 3) /* PIO4_31 */ +#define EMC_EMC_D26_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 6) /* PIO4_31 */ +#define ENET_RX_CLK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 1) /* PIO4_31 */ +#define FC4_SCK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 4) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 0) /* PIO4_31 */ +#define SDIF_SD_D6_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 2) /* PIO4_31 */ +#define CTIMER3_MATCH2_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 3) /* PIO5_0 */ +#define EMC_EMC_D27_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 6) /* PIO5_0 */ +#define ENET_RX_DV_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 1) /* PIO5_0 */ +#define FC4_RXD_SDA_MOSI_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 4) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 0) /* PIO5_0 */ +#define SDIF_SD_D7_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 2) /* PIO5_0 */ +#define CTIMER3_MATCH3_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 3) /* PIO5_1 */ +#define EMC_EMC_D28_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 6) /* PIO5_1 */ +#define ENET_CRS_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 1) /* PIO5_1 */ +#define FC4_TXD_SCL_MISO_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 4) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 0) /* PIO5_1 */ +#define SDIF_SD_VOLT0_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 2) /* PIO5_1 */ +#define CTIMER3_CAPTURE0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 3) /* PIO5_2 */ +#define EMC_EMC_D29_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 6) /* PIO5_2 */ +#define ENET_COL_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 1) /* PIO5_2 */ +#define FC4_CTS_SDA_SSEL0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 4) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 0) /* PIO5_2 */ +#define SDIF_SD_VOLT1_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 2) /* PIO5_2 */ +#define CTIMER3_CAPTURE1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 3) /* PIO5_3 */ +#define EMC_EMC_D30_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 6) /* PIO5_3 */ +#define ENET_MDC_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 1) /* PIO5_3 */ +#define FC4_RTS_SCL_SSEL1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 4) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 0) /* PIO5_3 */ +#define SDIF_SD_VOLT2_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 2) /* PIO5_3 */ +#define CTIMER3_CAPTURE2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 3) /* PIO5_4 */ +#define EMC_EMC_D31_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 6) /* PIO5_4 */ +#define ENET_MDIO_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 1) /* PIO5_4 */ +#define FC4_SSEL2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 0) /* PIO5_4 */ +#define SD_BACKEND_PWR_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 2) /* PIO5_4 */ +#define CTIMER3_CAPTURE3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 3) /* PIO5_5 */ +#define DMIC0_CLK1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 2) /* PIO5_5 */ +#define EMC_EMC_A21_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 6) /* PIO5_5 */ +#define FC4_SSEL3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 4) /* PIO5_5 */ +#define GPIO_PIO55_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 0) /* PIO5_5 */ +#define SCT0_IN0_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN2_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN4_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN5_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN6_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define TRACECLK_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 5) /* PIO5_5 */ +#define DMIC0_DATA1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 2) /* PIO5_6 */ +#define EMC_EMC_A22_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 6) /* PIO5_6 */ +#define FC5_SCK_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 3) /* PIO5_6 */ +#define GPIO_PIO56_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 0) /* PIO5_6 */ +#define SCT0_IN0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN2_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN3_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN4_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN6_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_OUT5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 4) /* PIO5_6 */ +#define SWD_TRACEDATA0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 5) /* PIO5_6 */ +#define EMC_EMC_A23_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 6) /* PIO5_7 */ +#define FC5_RXD_SDA_MOSI_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 3) /* PIO5_7 */ +#define GPIO_PIO57_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 0) /* PIO5_7 */ +#define MCLK_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 2) /* PIO5_7 */ +#define SCT0_IN0_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN2_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN3_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN4_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN5_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_OUT6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 4) /* PIO5_7 */ +#define SWD_TRACEDATA1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 5) /* PIO5_7 */ +#define DMIC0_CLK0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 2) /* PIO5_8 */ +#define EMC_EMC_A24_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 6) /* PIO5_8 */ +#define FC5_TXD_SCL_MISO_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 3) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 0) /* PIO5_8 */ +#define SCT0_IN0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN1_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN3_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN4_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN5_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN6_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_OUT7_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 4) /* PIO5_8 */ +#define SWD_TRACEDATA2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 5) /* PIO5_8 */ +#define DMIC0_DATA0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 2) /* PIO5_9 */ +#define EMC_EMC_A25_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 6) /* PIO5_9 */ +#define FC5_CTS_SDA_SSEL0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 3) /* PIO5_9 */ +#define GPIO_PIO59_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 0) /* PIO5_9 */ +#define SCT0_IN0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN1_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN2_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN4_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN5_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN6_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_OUT8_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 4) /* PIO5_9 */ +#define SWD_TRACEDATA3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 5) /* PIO5_9 */ +#define FC5_RTS_SCL_SSEL1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 3) /* PIO5_10 */ +#define GPIO_PIO510_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 0) /* PIO5_10 */ +#define SCT0_IN0_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN2_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN4_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN5_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN6_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_OUT9_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 4) /* PIO5_10 */ +#define UTICK0_CAPTURE3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 5) /* PIO5_10 */ + +#endif diff --git a/dts/nxp/lpc/LPC54616J512ET100-pinctrl.h b/dts/nxp/lpc/LPC54616J512ET100-pinctrl.h new file mode 100644 index 000000000..52d2706ea --- /dev/null +++ b/dts/nxp/lpc/LPC54616J512ET100-pinctrl.h @@ -0,0 +1,3138 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54616J512ET100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54616J512ET100_ +#define _ZEPHYR_DTS_BINDING_LPC54616J512ET100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54618J512BD208-pinctrl.h b/dts/nxp/lpc/LPC54618J512BD208-pinctrl.h new file mode 100644 index 000000000..e8dc4f363 --- /dev/null +++ b/dts/nxp/lpc/LPC54618J512BD208-pinctrl.h @@ -0,0 +1,3793 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54618J512BD208/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54618J512BD208_ +#define _ZEPHYR_DTS_BINDING_LPC54618J512BD208_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ +#define CAN1_TD_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 2) /* PIO4_17 */ +#define CTIMER1_CAPTURE2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 3) /* PIO4_17 */ +#define EMC_EMC_BLS2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 6) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 0) /* PIO4_17 */ +#define UTICK0_CAPTURE0_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 4) /* PIO4_17 */ +#define CAN1_RD_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 2) /* PIO4_18 */ +#define CTIMER1_CAPTURE3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 3) /* PIO4_18 */ +#define EMC_EMC_BLS3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 6) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 0) /* PIO4_18 */ +#define UTICK0_CAPTURE1_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 4) /* PIO4_18 */ +#define CTIMER4_CAPTURE2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 4) /* PIO4_19 */ +#define EMC_EMC_DQM2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 6) /* PIO4_19 */ +#define ENET_ENET_TXD0_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 1) /* PIO4_19 */ +#define FC2_SCK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 3) /* PIO4_19 */ +#define GPIO_PIO419_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 0) /* PIO4_19 */ +#define SD_CLK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 2) /* PIO4_19 */ +#define CTIMER4_CAPTURE3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 4) /* PIO4_20 */ +#define EMC_EMC_DQM3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 6) /* PIO4_20 */ +#define ENET_ENET_TXD1_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 1) /* PIO4_20 */ +#define FC2_RXD_SDA_MOSI_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 3) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 0) /* PIO4_20 */ +#define SD_CMD_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 2) /* PIO4_20 */ +#define CTIMER2_MATCH3_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 4) /* PIO4_21 */ +#define EMC_EMC_D16_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 6) /* PIO4_21 */ +#define ENET_ENET_TXD2_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 1) /* PIO4_21 */ +#define FC2_TXD_SCL_MISO_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 3) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 0) /* PIO4_21 */ +#define SD_POW_EN_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 2) /* PIO4_21 */ +#define CTIMER1_MATCH3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 4) /* PIO4_22 */ +#define EMC_EMC_D17_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 6) /* PIO4_22 */ +#define ENET_ENET_TXD3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 1) /* PIO4_22 */ +#define FC2_RTS_SCL_SSEL1_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 3) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 0) /* PIO4_22 */ +#define SD_CARD_DET_N_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 2) /* PIO4_22 */ +#define CTIMER1_MATCH0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 5) /* PIO4_23 */ +#define EMC_EMC_D18_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 6) /* PIO4_23 */ +#define ENET_ENET_RXD0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 1) /* PIO4_23 */ +#define FC2_CTS_SDA_SSEL0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 3) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 0) /* PIO4_23 */ +#define SD_WR_PRT_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 2) /* PIO4_23 */ +#define CTIMER1_MATCH1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 5) /* PIO4_24 */ +#define EMC_EMC_D19_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 6) /* PIO4_24 */ +#define ENET_ENET_RXD1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 1) /* PIO4_24 */ +#define FC7_RTS_SCL_SSEL1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 3) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 0) /* PIO4_24 */ +#define SD_CARD_INT_N_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 2) /* PIO4_24 */ +#define CTIMER1_MATCH2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 5) /* PIO4_25 */ +#define EMC_EMC_D20_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 6) /* PIO4_25 */ +#define ENET_ENET_RXD2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 1) /* PIO4_25 */ +#define FC7_CTS_SDA_SSEL0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 3) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 0) /* PIO4_25 */ +#define SDIF_SD_D0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 2) /* PIO4_25 */ +#define CTIMER1_MATCH3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 5) /* PIO4_26 */ +#define EMC_EMC_D21_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 6) /* PIO4_26 */ +#define ENET_ENET_RXD3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 1) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 0) /* PIO4_26 */ +#define SDIF_SD_D1_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 2) /* PIO4_26 */ +#define UTICK0_CAPTURE2_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 4) /* PIO4_26 */ +#define CTIMER1_CAPTURE0_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 5) /* PIO4_27 */ +#define EMC_EMC_D22_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 6) /* PIO4_27 */ +#define ENET_TX_EN_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 1) /* PIO4_27 */ +#define FC1_SCK_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 4) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 0) /* PIO4_27 */ +#define SDIF_SD_D2_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 2) /* PIO4_27 */ +#define CTIMER1_CAPTURE1_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 5) /* PIO4_28 */ +#define EMC_EMC_D23_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 6) /* PIO4_28 */ +#define ENET_TX_ER_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 1) /* PIO4_28 */ +#define FC1_RXD_SDA_MOSI_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 4) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 0) /* PIO4_28 */ +#define SDIF_SD_D3_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 2) /* PIO4_28 */ +#define CTIMER1_CAPTURE2_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 5) /* PIO4_29 */ +#define EMC_EMC_D24_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 6) /* PIO4_29 */ +#define ENET_RX_ER_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 1) /* PIO4_29 */ +#define FC1_TXD_SCL_MISO_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 4) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 0) /* PIO4_29 */ +#define SDIF_SD_D4_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 2) /* PIO4_29 */ +#define CTIMER1_CAPTURE3_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 5) /* PIO4_30 */ +#define CTIMER3_MATCH0_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 3) /* PIO4_30 */ +#define EMC_EMC_D25_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 6) /* PIO4_30 */ +#define ENET_TX_CLK_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 1) /* PIO4_30 */ +#define FC1_RTS_SCL_SSEL1_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 4) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 0) /* PIO4_30 */ +#define SDIF_SD_D5_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 2) /* PIO4_30 */ +#define CTIMER3_MATCH1_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 3) /* PIO4_31 */ +#define EMC_EMC_D26_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 6) /* PIO4_31 */ +#define ENET_RX_CLK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 1) /* PIO4_31 */ +#define FC4_SCK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 4) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 0) /* PIO4_31 */ +#define SDIF_SD_D6_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 2) /* PIO4_31 */ +#define CTIMER3_MATCH2_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 3) /* PIO5_0 */ +#define EMC_EMC_D27_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 6) /* PIO5_0 */ +#define ENET_RX_DV_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 1) /* PIO5_0 */ +#define FC4_RXD_SDA_MOSI_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 4) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 0) /* PIO5_0 */ +#define SDIF_SD_D7_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 2) /* PIO5_0 */ +#define CTIMER3_MATCH3_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 3) /* PIO5_1 */ +#define EMC_EMC_D28_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 6) /* PIO5_1 */ +#define ENET_CRS_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 1) /* PIO5_1 */ +#define FC4_TXD_SCL_MISO_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 4) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 0) /* PIO5_1 */ +#define SDIF_SD_VOLT0_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 2) /* PIO5_1 */ +#define CTIMER3_CAPTURE0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 3) /* PIO5_2 */ +#define EMC_EMC_D29_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 6) /* PIO5_2 */ +#define ENET_COL_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 1) /* PIO5_2 */ +#define FC4_CTS_SDA_SSEL0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 4) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 0) /* PIO5_2 */ +#define SDIF_SD_VOLT1_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 2) /* PIO5_2 */ +#define CTIMER3_CAPTURE1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 3) /* PIO5_3 */ +#define EMC_EMC_D30_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 6) /* PIO5_3 */ +#define ENET_MDC_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 1) /* PIO5_3 */ +#define FC4_RTS_SCL_SSEL1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 4) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 0) /* PIO5_3 */ +#define SDIF_SD_VOLT2_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 2) /* PIO5_3 */ +#define CTIMER3_CAPTURE2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 3) /* PIO5_4 */ +#define EMC_EMC_D31_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 6) /* PIO5_4 */ +#define ENET_MDIO_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 1) /* PIO5_4 */ +#define FC4_SSEL2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 0) /* PIO5_4 */ +#define SD_BACKEND_PWR_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 2) /* PIO5_4 */ +#define CTIMER3_CAPTURE3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 3) /* PIO5_5 */ +#define DMIC0_CLK1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 2) /* PIO5_5 */ +#define EMC_EMC_A21_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 6) /* PIO5_5 */ +#define FC4_SSEL3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 4) /* PIO5_5 */ +#define GPIO_PIO55_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 0) /* PIO5_5 */ +#define SCT0_IN0_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN2_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN4_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN5_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN6_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define TRACECLK_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 5) /* PIO5_5 */ +#define DMIC0_DATA1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 2) /* PIO5_6 */ +#define EMC_EMC_A22_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 6) /* PIO5_6 */ +#define FC5_SCK_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 3) /* PIO5_6 */ +#define GPIO_PIO56_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 0) /* PIO5_6 */ +#define SCT0_IN0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN2_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN3_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN4_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN6_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_OUT5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 4) /* PIO5_6 */ +#define SWD_TRACEDATA0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 5) /* PIO5_6 */ +#define EMC_EMC_A23_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 6) /* PIO5_7 */ +#define FC5_RXD_SDA_MOSI_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 3) /* PIO5_7 */ +#define GPIO_PIO57_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 0) /* PIO5_7 */ +#define MCLK_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 2) /* PIO5_7 */ +#define SCT0_IN0_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN2_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN3_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN4_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN5_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_OUT6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 4) /* PIO5_7 */ +#define SWD_TRACEDATA1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 5) /* PIO5_7 */ +#define DMIC0_CLK0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 2) /* PIO5_8 */ +#define EMC_EMC_A24_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 6) /* PIO5_8 */ +#define FC5_TXD_SCL_MISO_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 3) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 0) /* PIO5_8 */ +#define SCT0_IN0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN1_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN3_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN4_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN5_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN6_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_OUT7_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 4) /* PIO5_8 */ +#define SWD_TRACEDATA2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 5) /* PIO5_8 */ +#define DMIC0_DATA0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 2) /* PIO5_9 */ +#define EMC_EMC_A25_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 6) /* PIO5_9 */ +#define FC5_CTS_SDA_SSEL0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 3) /* PIO5_9 */ +#define GPIO_PIO59_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 0) /* PIO5_9 */ +#define SCT0_IN0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN1_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN2_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN4_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN5_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN6_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_OUT8_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 4) /* PIO5_9 */ +#define SWD_TRACEDATA3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 5) /* PIO5_9 */ +#define FC5_RTS_SCL_SSEL1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 3) /* PIO5_10 */ +#define GPIO_PIO510_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 0) /* PIO5_10 */ +#define SCT0_IN0_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN2_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN4_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN5_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN6_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_OUT9_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 4) /* PIO5_10 */ +#define UTICK0_CAPTURE3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 5) /* PIO5_10 */ + +#endif diff --git a/dts/nxp/lpc/LPC54618J512ET180-pinctrl.h b/dts/nxp/lpc/LPC54618J512ET180-pinctrl.h new file mode 100644 index 000000000..e741d4e10 --- /dev/null +++ b/dts/nxp/lpc/LPC54618J512ET180-pinctrl.h @@ -0,0 +1,3598 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54618J512ET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54618J512ET180_ +#define _ZEPHYR_DTS_BINDING_LPC54618J512ET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54628J512ET180-pinctrl.h b/dts/nxp/lpc/LPC54628J512ET180-pinctrl.h new file mode 100644 index 000000000..19a7db3c4 --- /dev/null +++ b/dts/nxp/lpc/LPC54628J512ET180-pinctrl.h @@ -0,0 +1,3598 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54628J512ET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54628J512ET180_ +#define _ZEPHYR_DTS_BINDING_LPC54628J512ET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_UP_LED_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define USB1_UP_LED_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define SYSCON_FREQMEB_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define USB0_UP_LED_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define USB1_UP_LED_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define USB0_UP_LED_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define USB1_UP_LED_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54S005JBD100-pinctrl.h b/dts/nxp/lpc/LPC54S005JBD100-pinctrl.h new file mode 100644 index 000000000..27be54363 --- /dev/null +++ b/dts/nxp/lpc/LPC54S005JBD100-pinctrl.h @@ -0,0 +1,3116 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54S005JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54S005JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC54S005JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54S005JET100-pinctrl.h b/dts/nxp/lpc/LPC54S005JET100-pinctrl.h new file mode 100644 index 000000000..7ff9a897d --- /dev/null +++ b/dts/nxp/lpc/LPC54S005JET100-pinctrl.h @@ -0,0 +1,3116 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54S005JET100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54S005JET100_ +#define _ZEPHYR_DTS_BINDING_LPC54S005JET100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54S016JBD100-pinctrl.h b/dts/nxp/lpc/LPC54S016JBD100-pinctrl.h new file mode 100644 index 000000000..9f26c564b --- /dev/null +++ b/dts/nxp/lpc/LPC54S016JBD100-pinctrl.h @@ -0,0 +1,3143 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54S016JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54S016JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC54S016JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54S016JBD208-pinctrl.h b/dts/nxp/lpc/LPC54S016JBD208-pinctrl.h new file mode 100644 index 000000000..ea81b4a2c --- /dev/null +++ b/dts/nxp/lpc/LPC54S016JBD208-pinctrl.h @@ -0,0 +1,3766 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54S016JBD208/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54S016JBD208_ +#define _ZEPHYR_DTS_BINDING_LPC54S016JBD208_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ +#define CAN1_TD_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 2) /* PIO4_17 */ +#define CTIMER1_CAPTURE2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 3) /* PIO4_17 */ +#define EMC_EMC_BLS2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 6) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 0) /* PIO4_17 */ +#define UTICK0_CAPTURE0_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 4) /* PIO4_17 */ +#define CAN1_RD_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 2) /* PIO4_18 */ +#define CTIMER1_CAPTURE3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 3) /* PIO4_18 */ +#define EMC_EMC_BLS3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 6) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 0) /* PIO4_18 */ +#define UTICK0_CAPTURE1_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 4) /* PIO4_18 */ +#define CTIMER4_CAPTURE2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 4) /* PIO4_19 */ +#define EMC_EMC_DQM2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 6) /* PIO4_19 */ +#define ENET_ENET_TXD0_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 1) /* PIO4_19 */ +#define FC2_SCK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 3) /* PIO4_19 */ +#define GPIO_PIO419_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 0) /* PIO4_19 */ +#define SD_CLK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 2) /* PIO4_19 */ +#define CTIMER4_CAPTURE3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 4) /* PIO4_20 */ +#define EMC_EMC_DQM3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 6) /* PIO4_20 */ +#define ENET_ENET_TXD1_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 1) /* PIO4_20 */ +#define FC2_RXD_SDA_MOSI_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 3) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 0) /* PIO4_20 */ +#define SD_CMD_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 2) /* PIO4_20 */ +#define CTIMER2_MATCH3_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 4) /* PIO4_21 */ +#define EMC_EMC_D16_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 6) /* PIO4_21 */ +#define ENET_ENET_TXD2_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 1) /* PIO4_21 */ +#define FC2_TXD_SCL_MISO_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 3) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 0) /* PIO4_21 */ +#define SD_POW_EN_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 2) /* PIO4_21 */ +#define CTIMER1_MATCH3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 4) /* PIO4_22 */ +#define EMC_EMC_D17_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 6) /* PIO4_22 */ +#define ENET_ENET_TXD3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 1) /* PIO4_22 */ +#define FC2_RTS_SCL_SSEL1_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 3) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 0) /* PIO4_22 */ +#define SD_CARD_DET_N_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 2) /* PIO4_22 */ +#define CTIMER1_MATCH0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 5) /* PIO4_23 */ +#define EMC_EMC_D18_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 6) /* PIO4_23 */ +#define ENET_ENET_RXD0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 1) /* PIO4_23 */ +#define FC2_CTS_SDA_SSEL0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 3) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 0) /* PIO4_23 */ +#define SD_WR_PRT_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 2) /* PIO4_23 */ +#define CTIMER1_MATCH1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 5) /* PIO4_24 */ +#define EMC_EMC_D19_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 6) /* PIO4_24 */ +#define ENET_ENET_RXD1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 1) /* PIO4_24 */ +#define FC7_RTS_SCL_SSEL1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 3) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 0) /* PIO4_24 */ +#define SD_CARD_INT_N_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 2) /* PIO4_24 */ +#define CTIMER1_MATCH2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 5) /* PIO4_25 */ +#define EMC_EMC_D20_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 6) /* PIO4_25 */ +#define ENET_ENET_RXD2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 1) /* PIO4_25 */ +#define FC7_CTS_SDA_SSEL0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 3) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 0) /* PIO4_25 */ +#define SDIF_SD_D0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 2) /* PIO4_25 */ +#define CTIMER1_MATCH3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 5) /* PIO4_26 */ +#define EMC_EMC_D21_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 6) /* PIO4_26 */ +#define ENET_ENET_RXD3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 1) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 0) /* PIO4_26 */ +#define SDIF_SD_D1_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 2) /* PIO4_26 */ +#define UTICK0_CAPTURE2_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 4) /* PIO4_26 */ +#define CTIMER1_CAPTURE0_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 5) /* PIO4_27 */ +#define EMC_EMC_D22_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 6) /* PIO4_27 */ +#define ENET_TX_EN_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 1) /* PIO4_27 */ +#define FC1_SCK_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 4) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 0) /* PIO4_27 */ +#define SDIF_SD_D2_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 2) /* PIO4_27 */ +#define CTIMER1_CAPTURE1_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 5) /* PIO4_28 */ +#define EMC_EMC_D23_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 6) /* PIO4_28 */ +#define ENET_TX_ER_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 1) /* PIO4_28 */ +#define FC1_RXD_SDA_MOSI_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 4) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 0) /* PIO4_28 */ +#define SDIF_SD_D3_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 2) /* PIO4_28 */ +#define CTIMER1_CAPTURE2_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 5) /* PIO4_29 */ +#define EMC_EMC_D24_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 6) /* PIO4_29 */ +#define ENET_RX_ER_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 1) /* PIO4_29 */ +#define FC1_TXD_SCL_MISO_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 4) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 0) /* PIO4_29 */ +#define SDIF_SD_D4_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 2) /* PIO4_29 */ +#define CTIMER1_CAPTURE3_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 5) /* PIO4_30 */ +#define CTIMER3_MATCH0_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 3) /* PIO4_30 */ +#define EMC_EMC_D25_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 6) /* PIO4_30 */ +#define ENET_TX_CLK_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 1) /* PIO4_30 */ +#define FC1_RTS_SCL_SSEL1_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 4) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 0) /* PIO4_30 */ +#define SDIF_SD_D5_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 2) /* PIO4_30 */ +#define CTIMER3_MATCH1_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 3) /* PIO4_31 */ +#define EMC_EMC_D26_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 6) /* PIO4_31 */ +#define ENET_RX_CLK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 1) /* PIO4_31 */ +#define FC4_SCK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 4) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 0) /* PIO4_31 */ +#define SDIF_SD_D6_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 2) /* PIO4_31 */ +#define CTIMER3_MATCH2_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 3) /* PIO5_0 */ +#define EMC_EMC_D27_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 6) /* PIO5_0 */ +#define ENET_RX_DV_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 1) /* PIO5_0 */ +#define FC4_RXD_SDA_MOSI_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 4) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 0) /* PIO5_0 */ +#define SDIF_SD_D7_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 2) /* PIO5_0 */ +#define CTIMER3_MATCH3_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 3) /* PIO5_1 */ +#define EMC_EMC_D28_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 6) /* PIO5_1 */ +#define ENET_CRS_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 1) /* PIO5_1 */ +#define FC4_TXD_SCL_MISO_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 4) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 0) /* PIO5_1 */ +#define SDIF_SD_VOLT0_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 2) /* PIO5_1 */ +#define CTIMER3_CAPTURE0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 3) /* PIO5_2 */ +#define EMC_EMC_D29_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 6) /* PIO5_2 */ +#define ENET_COL_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 1) /* PIO5_2 */ +#define FC4_CTS_SDA_SSEL0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 4) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 0) /* PIO5_2 */ +#define SDIF_SD_VOLT1_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 2) /* PIO5_2 */ +#define CTIMER3_CAPTURE1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 3) /* PIO5_3 */ +#define EMC_EMC_D30_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 6) /* PIO5_3 */ +#define ENET_MDC_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 1) /* PIO5_3 */ +#define FC4_RTS_SCL_SSEL1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 4) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 0) /* PIO5_3 */ +#define SDIF_SD_VOLT2_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 2) /* PIO5_3 */ +#define CTIMER3_CAPTURE2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 3) /* PIO5_4 */ +#define EMC_EMC_D31_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 6) /* PIO5_4 */ +#define ENET_MDIO_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 1) /* PIO5_4 */ +#define FC4_SSEL2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 0) /* PIO5_4 */ +#define SD_BACKEND_PWR_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 2) /* PIO5_4 */ +#define CTIMER3_CAPTURE3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 3) /* PIO5_5 */ +#define DMIC0_CLK1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 2) /* PIO5_5 */ +#define EMC_EMC_A21_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 6) /* PIO5_5 */ +#define FC4_SSEL3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 4) /* PIO5_5 */ +#define GPIO_PIO55_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 0) /* PIO5_5 */ +#define SCT0_IN0_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN2_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN4_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN5_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN6_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define TRACECLK_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 5) /* PIO5_5 */ +#define DMIC0_DATA1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 2) /* PIO5_6 */ +#define EMC_EMC_A22_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 6) /* PIO5_6 */ +#define FC5_SCK_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 3) /* PIO5_6 */ +#define GPIO_PIO56_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 0) /* PIO5_6 */ +#define SCT0_IN0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN2_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN3_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN4_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN6_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_OUT5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 4) /* PIO5_6 */ +#define SWD_TRACEDATA0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 5) /* PIO5_6 */ +#define EMC_EMC_A23_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 6) /* PIO5_7 */ +#define FC5_RXD_SDA_MOSI_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 3) /* PIO5_7 */ +#define GPIO_PIO57_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 0) /* PIO5_7 */ +#define MCLK_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 2) /* PIO5_7 */ +#define SCT0_IN0_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN2_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN3_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN4_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN5_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_OUT6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 4) /* PIO5_7 */ +#define SWD_TRACEDATA1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 5) /* PIO5_7 */ +#define DMIC0_CLK0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 2) /* PIO5_8 */ +#define EMC_EMC_A24_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 6) /* PIO5_8 */ +#define FC5_TXD_SCL_MISO_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 3) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 0) /* PIO5_8 */ +#define SCT0_IN0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN1_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN3_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN4_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN5_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN6_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_OUT7_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 4) /* PIO5_8 */ +#define SWD_TRACEDATA2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 5) /* PIO5_8 */ +#define DMIC0_DATA0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 2) /* PIO5_9 */ +#define EMC_EMC_A25_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 6) /* PIO5_9 */ +#define FC5_CTS_SDA_SSEL0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 3) /* PIO5_9 */ +#define GPIO_PIO59_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 0) /* PIO5_9 */ +#define SCT0_IN0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN1_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN2_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN4_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN5_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN6_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_OUT8_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 4) /* PIO5_9 */ +#define SWD_TRACEDATA3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 5) /* PIO5_9 */ +#define FC5_RTS_SCL_SSEL1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 3) /* PIO5_10 */ +#define GPIO_PIO510_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 0) /* PIO5_10 */ +#define SCT0_IN0_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN2_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN4_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN5_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN6_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_OUT9_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 4) /* PIO5_10 */ +#define UTICK0_CAPTURE3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 5) /* PIO5_10 */ + +#endif diff --git a/dts/nxp/lpc/LPC54S016JET100-pinctrl.h b/dts/nxp/lpc/LPC54S016JET100-pinctrl.h new file mode 100644 index 000000000..de5611cff --- /dev/null +++ b/dts/nxp/lpc/LPC54S016JET100-pinctrl.h @@ -0,0 +1,3143 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54S016JET100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54S016JET100_ +#define _ZEPHYR_DTS_BINDING_LPC54S016JET100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC54S016JET180-pinctrl.h b/dts/nxp/lpc/LPC54S016JET180-pinctrl.h new file mode 100644 index 000000000..d53759cdf --- /dev/null +++ b/dts/nxp/lpc/LPC54S016JET180-pinctrl.h @@ -0,0 +1,3571 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54S016JET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54S016JET180_ +#define _ZEPHYR_DTS_BINDING_LPC54S016JET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC54S018J2MET180-pinctrl.h b/dts/nxp/lpc/LPC54S018J2MET180-pinctrl.h new file mode 100644 index 000000000..db75da62f --- /dev/null +++ b/dts/nxp/lpc/LPC54S018J2MET180-pinctrl.h @@ -0,0 +1,3304 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54S018J2MET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54S018J2MET180_ +#define _ZEPHYR_DTS_BINDING_LPC54S018J2MET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ + +#endif diff --git a/dts/nxp/lpc/LPC54S018J4MET180-pinctrl.h b/dts/nxp/lpc/LPC54S018J4MET180-pinctrl.h new file mode 100644 index 000000000..5d886143e --- /dev/null +++ b/dts/nxp/lpc/LPC54S018J4MET180-pinctrl.h @@ -0,0 +1,3304 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54S018J4MET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54S018J4MET180_ +#define _ZEPHYR_DTS_BINDING_LPC54S018J4MET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ + +#endif diff --git a/dts/nxp/lpc/LPC54S018JBD208-pinctrl.h b/dts/nxp/lpc/LPC54S018JBD208-pinctrl.h new file mode 100644 index 000000000..c9e111674 --- /dev/null +++ b/dts/nxp/lpc/LPC54S018JBD208-pinctrl.h @@ -0,0 +1,3801 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54S018JBD208/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54S018JBD208_ +#define _ZEPHYR_DTS_BINDING_LPC54S018JBD208_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ +#define CAN1_TD_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 2) /* PIO4_17 */ +#define CTIMER1_CAPTURE2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 3) /* PIO4_17 */ +#define EMC_EMC_BLS2_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 6) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 0) /* PIO4_17 */ +#define UTICK0_CAPTURE0_PIO4_17 IOCON_MUX(145, IOCON_TYPE_D, 4) /* PIO4_17 */ +#define CAN1_RD_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 2) /* PIO4_18 */ +#define CTIMER1_CAPTURE3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 3) /* PIO4_18 */ +#define EMC_EMC_BLS3_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 6) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 0) /* PIO4_18 */ +#define UTICK0_CAPTURE1_PIO4_18 IOCON_MUX(146, IOCON_TYPE_D, 4) /* PIO4_18 */ +#define CTIMER4_CAPTURE2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 4) /* PIO4_19 */ +#define EMC_EMC_DQM2_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 6) /* PIO4_19 */ +#define ENET_ENET_TXD0_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 1) /* PIO4_19 */ +#define FC2_SCK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 3) /* PIO4_19 */ +#define GPIO_PIO419_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 0) /* PIO4_19 */ +#define SD_CLK_PIO4_19 IOCON_MUX(147, IOCON_TYPE_D, 2) /* PIO4_19 */ +#define CTIMER4_CAPTURE3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 4) /* PIO4_20 */ +#define EMC_EMC_DQM3_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 6) /* PIO4_20 */ +#define ENET_ENET_TXD1_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 1) /* PIO4_20 */ +#define FC2_RXD_SDA_MOSI_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 3) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 0) /* PIO4_20 */ +#define SD_CMD_PIO4_20 IOCON_MUX(148, IOCON_TYPE_D, 2) /* PIO4_20 */ +#define CTIMER2_MATCH3_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 4) /* PIO4_21 */ +#define EMC_EMC_D16_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 6) /* PIO4_21 */ +#define ENET_ENET_TXD2_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 1) /* PIO4_21 */ +#define FC2_TXD_SCL_MISO_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 3) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 0) /* PIO4_21 */ +#define SD_POW_EN_PIO4_21 IOCON_MUX(149, IOCON_TYPE_D, 2) /* PIO4_21 */ +#define CTIMER1_MATCH3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 4) /* PIO4_22 */ +#define EMC_EMC_D17_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 6) /* PIO4_22 */ +#define ENET_ENET_TXD3_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 1) /* PIO4_22 */ +#define FC2_RTS_SCL_SSEL1_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 3) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 0) /* PIO4_22 */ +#define SD_CARD_DET_N_PIO4_22 IOCON_MUX(150, IOCON_TYPE_D, 2) /* PIO4_22 */ +#define CTIMER1_MATCH0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 5) /* PIO4_23 */ +#define EMC_EMC_D18_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 6) /* PIO4_23 */ +#define ENET_ENET_RXD0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 1) /* PIO4_23 */ +#define FC2_CTS_SDA_SSEL0_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 3) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 0) /* PIO4_23 */ +#define SD_WR_PRT_PIO4_23 IOCON_MUX(151, IOCON_TYPE_D, 2) /* PIO4_23 */ +#define CTIMER1_MATCH1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 5) /* PIO4_24 */ +#define EMC_EMC_D19_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 6) /* PIO4_24 */ +#define ENET_ENET_RXD1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 1) /* PIO4_24 */ +#define FC7_RTS_SCL_SSEL1_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 3) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 0) /* PIO4_24 */ +#define SD_CARD_INT_N_PIO4_24 IOCON_MUX(152, IOCON_TYPE_D, 2) /* PIO4_24 */ +#define CTIMER1_MATCH2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 5) /* PIO4_25 */ +#define EMC_EMC_D20_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 6) /* PIO4_25 */ +#define ENET_ENET_RXD2_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 1) /* PIO4_25 */ +#define FC7_CTS_SDA_SSEL0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 3) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 0) /* PIO4_25 */ +#define SDIF_SD_D0_PIO4_25 IOCON_MUX(153, IOCON_TYPE_D, 2) /* PIO4_25 */ +#define CTIMER1_MATCH3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 5) /* PIO4_26 */ +#define EMC_EMC_D21_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 6) /* PIO4_26 */ +#define ENET_ENET_RXD3_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 1) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 0) /* PIO4_26 */ +#define SDIF_SD_D1_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 2) /* PIO4_26 */ +#define UTICK0_CAPTURE2_PIO4_26 IOCON_MUX(154, IOCON_TYPE_D, 4) /* PIO4_26 */ +#define CTIMER1_CAPTURE0_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 5) /* PIO4_27 */ +#define EMC_EMC_D22_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 6) /* PIO4_27 */ +#define ENET_TX_EN_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 1) /* PIO4_27 */ +#define FC1_SCK_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 4) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 0) /* PIO4_27 */ +#define SDIF_SD_D2_PIO4_27 IOCON_MUX(155, IOCON_TYPE_D, 2) /* PIO4_27 */ +#define CTIMER1_CAPTURE1_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 5) /* PIO4_28 */ +#define EMC_EMC_D23_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 6) /* PIO4_28 */ +#define ENET_TX_ER_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 1) /* PIO4_28 */ +#define FC1_RXD_SDA_MOSI_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 4) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 0) /* PIO4_28 */ +#define SDIF_SD_D3_PIO4_28 IOCON_MUX(156, IOCON_TYPE_D, 2) /* PIO4_28 */ +#define CTIMER1_CAPTURE2_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 5) /* PIO4_29 */ +#define EMC_EMC_D24_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 6) /* PIO4_29 */ +#define ENET_RX_ER_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 1) /* PIO4_29 */ +#define FC1_TXD_SCL_MISO_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 4) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 0) /* PIO4_29 */ +#define SDIF_SD_D4_PIO4_29 IOCON_MUX(157, IOCON_TYPE_D, 2) /* PIO4_29 */ +#define CTIMER1_CAPTURE3_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 5) /* PIO4_30 */ +#define CTIMER3_MATCH0_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 3) /* PIO4_30 */ +#define EMC_EMC_D25_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 6) /* PIO4_30 */ +#define ENET_TX_CLK_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 1) /* PIO4_30 */ +#define FC1_RTS_SCL_SSEL1_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 4) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 0) /* PIO4_30 */ +#define SDIF_SD_D5_PIO4_30 IOCON_MUX(158, IOCON_TYPE_D, 2) /* PIO4_30 */ +#define CTIMER3_MATCH1_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 3) /* PIO4_31 */ +#define EMC_EMC_D26_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 6) /* PIO4_31 */ +#define ENET_RX_CLK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 1) /* PIO4_31 */ +#define FC4_SCK_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 4) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 0) /* PIO4_31 */ +#define SDIF_SD_D6_PIO4_31 IOCON_MUX(159, IOCON_TYPE_D, 2) /* PIO4_31 */ +#define CTIMER3_MATCH2_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 3) /* PIO5_0 */ +#define EMC_EMC_D27_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 6) /* PIO5_0 */ +#define ENET_RX_DV_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 1) /* PIO5_0 */ +#define FC4_RXD_SDA_MOSI_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 4) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 0) /* PIO5_0 */ +#define SDIF_SD_D7_PIO5_0 IOCON_MUX(160, IOCON_TYPE_D, 2) /* PIO5_0 */ +#define CTIMER3_MATCH3_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 3) /* PIO5_1 */ +#define EMC_EMC_D28_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 6) /* PIO5_1 */ +#define ENET_CRS_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 1) /* PIO5_1 */ +#define FC4_TXD_SCL_MISO_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 4) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 0) /* PIO5_1 */ +#define SDIF_SD_VOLT0_PIO5_1 IOCON_MUX(161, IOCON_TYPE_D, 2) /* PIO5_1 */ +#define CTIMER3_CAPTURE0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 3) /* PIO5_2 */ +#define EMC_EMC_D29_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 6) /* PIO5_2 */ +#define ENET_COL_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 1) /* PIO5_2 */ +#define FC4_CTS_SDA_SSEL0_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 4) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 0) /* PIO5_2 */ +#define SDIF_SD_VOLT1_PIO5_2 IOCON_MUX(162, IOCON_TYPE_D, 2) /* PIO5_2 */ +#define CTIMER3_CAPTURE1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 3) /* PIO5_3 */ +#define EMC_EMC_D30_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 6) /* PIO5_3 */ +#define ENET_MDC_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 1) /* PIO5_3 */ +#define FC4_RTS_SCL_SSEL1_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 4) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 0) /* PIO5_3 */ +#define SDIF_SD_VOLT2_PIO5_3 IOCON_MUX(163, IOCON_TYPE_D, 2) /* PIO5_3 */ +#define CTIMER3_CAPTURE2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 3) /* PIO5_4 */ +#define EMC_EMC_D31_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 6) /* PIO5_4 */ +#define ENET_MDIO_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 1) /* PIO5_4 */ +#define FC4_SSEL2_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 0) /* PIO5_4 */ +#define SD_BACKEND_PWR_PIO5_4 IOCON_MUX(164, IOCON_TYPE_D, 2) /* PIO5_4 */ +#define CTIMER3_CAPTURE3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 3) /* PIO5_5 */ +#define DMIC0_CLK1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 2) /* PIO5_5 */ +#define EMC_EMC_A21_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 6) /* PIO5_5 */ +#define FC4_SSEL3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 4) /* PIO5_5 */ +#define GPIO_PIO55_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 0) /* PIO5_5 */ +#define SCT0_IN0_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN1_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN2_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN3_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN4_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN5_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define SCT0_IN6_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 1) /* PIO5_5 */ +#define TRACECLK_PIO5_5 IOCON_MUX(165, IOCON_TYPE_D, 5) /* PIO5_5 */ +#define DMIC0_DATA1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 2) /* PIO5_6 */ +#define EMC_EMC_A22_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 6) /* PIO5_6 */ +#define FC5_SCK_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 3) /* PIO5_6 */ +#define GPIO_PIO56_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 0) /* PIO5_6 */ +#define SCT0_IN0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN1_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN2_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN3_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN4_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_IN6_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 1) /* PIO5_6 */ +#define SCT0_OUT5_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 4) /* PIO5_6 */ +#define SWD_TRACEDATA0_PIO5_6 IOCON_MUX(166, IOCON_TYPE_D, 5) /* PIO5_6 */ +#define EMC_EMC_A23_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 6) /* PIO5_7 */ +#define FC5_RXD_SDA_MOSI_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 3) /* PIO5_7 */ +#define GPIO_PIO57_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 0) /* PIO5_7 */ +#define MCLK_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 2) /* PIO5_7 */ +#define SCT0_IN0_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN2_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN3_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN4_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN5_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_IN6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 1) /* PIO5_7 */ +#define SCT0_OUT6_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 4) /* PIO5_7 */ +#define SWD_TRACEDATA1_PIO5_7 IOCON_MUX(167, IOCON_TYPE_D, 5) /* PIO5_7 */ +#define DMIC0_CLK0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 2) /* PIO5_8 */ +#define EMC_EMC_A24_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 6) /* PIO5_8 */ +#define FC5_TXD_SCL_MISO_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 3) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 0) /* PIO5_8 */ +#define SCT0_IN0_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN1_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN3_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN4_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN5_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_IN6_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 1) /* PIO5_8 */ +#define SCT0_OUT7_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 4) /* PIO5_8 */ +#define SWD_TRACEDATA2_PIO5_8 IOCON_MUX(168, IOCON_TYPE_D, 5) /* PIO5_8 */ +#define DMIC0_DATA0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 2) /* PIO5_9 */ +#define EMC_EMC_A25_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 6) /* PIO5_9 */ +#define FC5_CTS_SDA_SSEL0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 3) /* PIO5_9 */ +#define GPIO_PIO59_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 0) /* PIO5_9 */ +#define SCT0_IN0_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN1_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN2_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN4_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN5_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_IN6_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 1) /* PIO5_9 */ +#define SCT0_OUT8_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 4) /* PIO5_9 */ +#define SWD_TRACEDATA3_PIO5_9 IOCON_MUX(169, IOCON_TYPE_D, 5) /* PIO5_9 */ +#define FC5_RTS_SCL_SSEL1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 3) /* PIO5_10 */ +#define GPIO_PIO510_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 0) /* PIO5_10 */ +#define SCT0_IN0_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN1_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN2_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN4_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN5_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_IN6_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 1) /* PIO5_10 */ +#define SCT0_OUT9_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 4) /* PIO5_10 */ +#define UTICK0_CAPTURE3_PIO5_10 IOCON_MUX(170, IOCON_TYPE_D, 5) /* PIO5_10 */ + +#endif diff --git a/dts/nxp/lpc/LPC54S018JET180-pinctrl.h b/dts/nxp/lpc/LPC54S018JET180-pinctrl.h new file mode 100644 index 000000000..93eac6283 --- /dev/null +++ b/dts/nxp/lpc/LPC54S018JET180-pinctrl.h @@ -0,0 +1,3606 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC54S018JET180/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC54S018JET180_ +#define _ZEPHYR_DTS_BINDING_LPC54S018JET180_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define CAN1_RD_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define DMIC0_CLK0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 4) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define CAN1_TD_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_DATA0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define EMC_EMC_D0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 6) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define EMC_EMC_D1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 6) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define EMC_EMC_D2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 6) /* PIO0_4 */ +#define ENET_MDC_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 7) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define EMC_EMC_D3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 6) /* PIO0_5 */ +#define ENET_MDIO_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 7) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define EMC_EMC_D4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 6) /* PIO0_6 */ +#define ENET_RX_DV_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 7) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMIC0_CLK1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ +#define EMC_EMC_D5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 6) /* PIO0_7 */ +#define ENET_RX_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 7) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define EMC_EMC_D6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 6) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define EMC_EMC_D7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 6) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ +#define SCI1_IO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ +#define SD_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ +#define ADC0_CH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 6) /* PIO0_10 */ +#define ADC0_CH1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_GPIO_CLK_A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 6) /* PIO0_11 */ +#define ADC0_CH2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FREQME_GPIO_CLK_B_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 6) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 3) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define ENET_ENET_RXD0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 7) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 4) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 3) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define ENET_ENET_RXD1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 7) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 4) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ +#define ADC0_CH3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define EMC_WEN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 6) /* PIO0_15 */ +#define ENET_TX_EN_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 7) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define EMC_EMC_CS0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 6) /* PIO0_16 */ +#define ENET_ENET_TXD0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 7) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define EMC_OEN_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 6) /* PIO0_17 */ +#define ENET_ENET_TXD1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 7) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define EMC_EMC_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 6) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ +#define SCI1_SCLK_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 5) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 4) /* PIO0_18 */ +#define SD_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define EMC_EMC_A1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 6) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define EMC_EMC_A2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 6) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define SCI0_IO_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 5) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define EMC_EMC_A3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define SCI0_SCLK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 4) /* PIO0_23 */ +#define SPIFI_CSN_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 6) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SPIFI_IO(0)_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 6) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SPIFI_IO(1)_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC10_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SPIFI_CLK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 6) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SPIFI0_SPIFI_IO3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 6) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SPIFI0_SPIFI_IO2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 6) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 4) /* PIO0_31 */ +#define SDIF_SD_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ +#define SWD_TRACEDATA0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ +#define ADC0_CH6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SDIF_SD_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ +#define TRACECLK_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC10_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define FC10_TXD_SCL_MISO_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC10_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 8) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define EMC_EMC_D11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FREQME_GPIO_CLK_A_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define EMC_EMC_A4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 6) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define EMC_EMC_A5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 6) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define EMC_EMC_A6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 6) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define EMC_EMC_A7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 6) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define SD_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define EMC_CASN_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 6) /* PIO1_9 */ +#define ENET_ENET_TXD0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_D, 4) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define EMC_RASN_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 6) /* PIO1_10 */ +#define ENET_ENET_TXD1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define EMC_EMC_CLK0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 6) /* PIO1_11 */ +#define ENET_TX_EN_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define EMC_EMC_DYCS0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 6) /* PIO1_12 */ +#define ENET_ENET_RXD0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define EMC_EMC_DQM0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 6) /* PIO1_13 */ +#define ENET_ENET_RXD1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 3) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define EMC_EMC_DQM1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 6) /* PIO1_14 */ +#define ENET_RX_DV_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 1) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_D, 2) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define EMC_EMC_CKE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 6) /* PIO1_15 */ +#define ENET_RX_CLK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define EMC_EMC_A10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 6) /* PIO1_16 */ +#define ENET_MDC_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define CAN1_TD_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 5) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define EMC_EMC_BLS0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 6) /* PIO1_17 */ +#define ENET_MDIO_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_17 */ +#define FC8_RXD_SDA_MOSI_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define CAN1_RD_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 5) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define EMC_EMC_BLS1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 6) /* PIO1_18 */ +#define FC8_TXD_SCL_MISO_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define EMC_EMC_D8_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 6) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define FC8_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define EMC_EMC_D9_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 6) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define EMC_EMC_D10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 6) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define EMC_EMC_CKE1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 6) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define FC8_RTS_SCL_SSEL1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define EMC_EMC_A11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 6) /* PIO1_23 */ +#define ENET_MDIO_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 4) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define EMC_EMC_A12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 6) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define EMC_EMC_A13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 6) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define EMC_EMC_A8_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 6) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define EMC_EMC_A9_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 6) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define SDIF_SD_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define EMC_EMC_D12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 6) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define SDIF_SD_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define EMC_EMC_D13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 6) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define EMC_EMC_D14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 6) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define EMC_EMC_D15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 6) /* PIO1_31 */ +#define FC8_CTS_SDA_SSEL0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 5) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define ADC0_CH7_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_0 */ +#define ADC0_CH8_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define CTIMER1_MATCH1_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 4) /* PIO2_2 */ +#define ENET_CRS_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_2 */ +#define FC3_SSEL3_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_2 */ +#define GPIO_PIO22_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_2 */ +#define SCT0_OUT6_PIO2_2 IOCON_MUX(66, IOCON_TYPE_D, 3) /* PIO2_2 */ +#define CTIMER2_MATCH0_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 4) /* PIO2_3 */ +#define ENET_ENET_TXD2_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_3 */ +#define FC1_RXD_SDA_MOSI_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_3 */ +#define GPIO_PIO23_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_3 */ +#define SD_CLK_PIO2_3 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_3 */ +#define CTIMER2_MATCH1_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 4) /* PIO2_4 */ +#define ENET_ENET_TXD3_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_4 */ +#define FC1_TXD_SCL_MISO_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 3) /* PIO2_4 */ +#define GPIO_PIO24_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_4 */ +#define SD_CMD_PIO2_4 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_4 */ +#define CTIMER1_MATCH2_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 4) /* PIO2_5 */ +#define ENET_TX_ER_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_5 */ +#define FC1_CTS_SDA_SSEL0_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 3) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_5 */ +#define SD_POW_EN_PIO2_5 IOCON_MUX(69, IOCON_TYPE_D, 2) /* PIO2_5 */ +#define CTIMER0_CAPTURE0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 4) /* PIO2_6 */ +#define ENET_TX_CLK_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_6 */ +#define FC1_RTS_SCL_SSEL1_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 3) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_6 */ +#define SDIF_SD_D0_PIO2_6 IOCON_MUX(70, IOCON_TYPE_D, 2) /* PIO2_6 */ +#define CTIMER0_CAPTURE1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 4) /* PIO2_7 */ +#define ENET_COL_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_7 */ +#define FREQME_GPIO_CLK_B_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 3) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_7 */ +#define SDIF_SD_D1_PIO2_7 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_7 */ +#define CTIMER0_MATCH0_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 4) /* PIO2_8 */ +#define ENET_ENET_RXD2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_8 */ +#define SDIF_SD_D2_PIO2_8 IOCON_MUX(72, IOCON_TYPE_D, 2) /* PIO2_8 */ +#define CTIMER0_MATCH1_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 4) /* PIO2_9 */ +#define ENET_ENET_RXD3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_9 */ +#define SDIF_SD_D3_PIO2_9 IOCON_MUX(73, IOCON_TYPE_D, 2) /* PIO2_9 */ +#define ENET_RX_ER_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_10 */ +#define SD_CARD_DET_N_PIO2_10 IOCON_MUX(74, IOCON_TYPE_D, 2) /* PIO2_10 */ +#define FC5_SCK_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_11 */ +#define LCD_PWR_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_11 */ +#define SDIF_SD_VOLT0_PIO2_11 IOCON_MUX(75, IOCON_TYPE_D, 2) /* PIO2_11 */ +#define FC5_RXD_SDA_MOSI_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 5) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_12 */ +#define LCD_LE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_12 */ +#define SDIF_SD_VOLT1_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 2) /* PIO2_12 */ +#define USB0_IDVALUE_PIO2_12 IOCON_MUX(76, IOCON_TYPE_D, 3) /* PIO2_12 */ +#define FC5_TXD_SCL_MISO_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 5) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_13 */ +#define LCD_DCLK_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_13 */ +#define SDIF_SD_VOLT2_PIO2_13 IOCON_MUX(77, IOCON_TYPE_D, 2) /* PIO2_13 */ +#define CTIMER0_MATCH2_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 4) /* PIO2_14 */ +#define FC5_CTS_SDA_SSEL0_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 5) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_14 */ +#define LCD_FP_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_14 */ +#define USB0_FRAME_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 2) /* PIO2_14 */ +#define USB0_PORTPWRN_PIO2_14 IOCON_MUX(78, IOCON_TYPE_D, 3) /* PIO2_14 */ +#define CTIMER0_MATCH3_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 4) /* PIO2_15 */ +#define FC5_RTS_SCL_SSEL1_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 5) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_15 */ +#define LCD_AC_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_15 */ +#define USB0_LEDN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 2) /* PIO2_15 */ +#define USB0_OVERCURRENTN_PIO2_15 IOCON_MUX(79, IOCON_TYPE_D, 3) /* PIO2_15 */ +#define CTIMER1_MATCH3_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 4) /* PIO2_16 */ +#define FC8_SCK_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 5) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_16 */ +#define LCD_LP_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_16 */ +#define USB1_FRAME_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 2) /* PIO2_16 */ +#define USB1_PORTPWRN_PIO2_16 IOCON_MUX(80, IOCON_TYPE_D, 3) /* PIO2_16 */ +#define CTIMER1_CAPTURE1_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 4) /* PIO2_17 */ +#define FC8_RXD_SDA_MOSI_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 5) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_17 */ +#define LCD_CLKIN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 1) /* PIO2_17 */ +#define USB1_LEDN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 2) /* PIO2_17 */ +#define USB1_OVERCURRENTN_PIO2_17 IOCON_MUX(81, IOCON_TYPE_D, 3) /* PIO2_17 */ +#define CTIMER3_MATCH0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 4) /* PIO2_18 */ +#define FC3_RXD_SDA_MOSI_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 2) /* PIO2_18 */ +#define FC7_SCK_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 3) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_18 */ +#define LCD_LCD_VD0_PIO2_18 IOCON_MUX(82, IOCON_TYPE_D, 1) /* PIO2_18 */ +#define CTIMER3_MATCH1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 4) /* PIO2_19 */ +#define FC3_TXD_SCL_MISO_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 2) /* PIO2_19 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 3) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_19 */ +#define LCD_LCD_VD1_PIO2_19 IOCON_MUX(83, IOCON_TYPE_D, 1) /* PIO2_19 */ +#define CTIMER3_MATCH2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 4) /* PIO2_20 */ +#define CTIMER4_CAPTURE0_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 5) /* PIO2_20 */ +#define FC3_RTS_SCL_SSEL1_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 2) /* PIO2_20 */ +#define FC7_TXD_SCL_MISO_WS_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 3) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_20 */ +#define LCD_LCD_VD2_PIO2_20 IOCON_MUX(84, IOCON_TYPE_D, 1) /* PIO2_20 */ +#define CTIMER3_MATCH3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 4) /* PIO2_21 */ +#define FC3_CTS_SDA_SSEL0_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 2) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 0) /* PIO2_21 */ +#define LCD_LCD_VD3_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 1) /* PIO2_21 */ +#define MCLK_PIO2_21 IOCON_MUX(85, IOCON_TYPE_D, 3) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 4) /* PIO2_22 */ +#define FC10_RTS_SCL_SSEL1_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 0) /* PIO2_22 */ +#define LCD_LCD_VD4_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 1) /* PIO2_22 */ +#define SCT0_OUT7_PIO2_22 IOCON_MUX(86, IOCON_TYPE_D, 2) /* PIO2_22 */ +#define FC10_SSEL2_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 0) /* PIO2_23 */ +#define LCD_LCD_VD5_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 1) /* PIO2_23 */ +#define SCT0_OUT8_PIO2_23 IOCON_MUX(87, IOCON_TYPE_D, 2) /* PIO2_23 */ +#define FC10_SSEL3_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 0) /* PIO2_24 */ +#define LCD_LCD_VD6_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 1) /* PIO2_24 */ +#define SCT0_OUT9_PIO2_24 IOCON_MUX(88, IOCON_TYPE_D, 2) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 0) /* PIO2_25 */ +#define LCD_LCD_VD7_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 1) /* PIO2_25 */ +#define USB0_VBUS_PIO2_25 IOCON_MUX(89, IOCON_TYPE_D, 2) /* PIO2_25 */ +#define CTIMER2_CAPTURE1_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 4) /* PIO2_26 */ +#define FC3_SCK_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 3) /* PIO2_26 */ +#define GPIO_PIO226_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 0) /* PIO2_26 */ +#define LCD_LCD_VD8_PIO2_26 IOCON_MUX(90, IOCON_TYPE_D, 1) /* PIO2_26 */ +#define FC3_SSEL2_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 3) /* PIO2_27 */ +#define FC9_SCK_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 2) /* PIO2_27 */ +#define GPIO_PIO227_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 0) /* PIO2_27 */ +#define LCD_LCD_VD9_PIO2_27 IOCON_MUX(91, IOCON_TYPE_D, 1) /* PIO2_27 */ +#define CTIMER2_CAPTURE2_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 4) /* PIO2_28 */ +#define FC7_CTS_SDA_SSEL0_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 2) /* PIO2_28 */ +#define GPIO_PIO228_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 0) /* PIO2_28 */ +#define LCD_LCD_VD10_PIO2_28 IOCON_MUX(92, IOCON_TYPE_D, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 5) /* PIO2_29 */ +#define CTIMER2_CAPTURE3_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 4) /* PIO2_29 */ +#define FC7_RTS_SCL_SSEL1_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 2) /* PIO2_29 */ +#define FC8_TXD_SCL_MISO_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 3) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 0) /* PIO2_29 */ +#define LCD_LCD_VD11_PIO2_29 IOCON_MUX(93, IOCON_TYPE_D, 1) /* PIO2_29 */ +#define CTIMER2_MATCH2_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 4) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 0) /* PIO2_30 */ +#define LCD_LCD_VD12_PIO2_30 IOCON_MUX(94, IOCON_TYPE_D, 1) /* PIO2_30 */ +#define GPIO_PIO231_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 0) /* PIO2_31 */ +#define LCD_LCD_VD13_PIO2_31 IOCON_MUX(95, IOCON_TYPE_D, 1) /* PIO2_31 */ +#define CTIMER1_MATCH0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 4) /* PIO3_0 */ +#define DMIC0_CLK0_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 2) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 0) /* PIO3_0 */ +#define LCD_LCD_VD14_PIO3_0 IOCON_MUX(96, IOCON_TYPE_D, 1) /* PIO3_0 */ +#define CTIMER1_MATCH1_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 4) /* PIO3_1 */ +#define DMIC0_DATA0_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 2) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 0) /* PIO3_1 */ +#define LCD_LCD_VD15_PIO3_1 IOCON_MUX(97, IOCON_TYPE_D, 1) /* PIO3_1 */ +#define CTIMER1_MATCH2_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 4) /* PIO3_2 */ +#define FC9_RXD_SDA_MOSI_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 2) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 0) /* PIO3_2 */ +#define LCD_LCD_VD16_PIO3_2 IOCON_MUX(98, IOCON_TYPE_D, 1) /* PIO3_2 */ +#define FC9_TXD_SCL_MISO_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 2) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 0) /* PIO3_3 */ +#define LCD_LCD_VD17_PIO3_3 IOCON_MUX(99, IOCON_TYPE_D, 1) /* PIO3_3 */ +#define CTIMER4_CAPTURE1_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 4) /* PIO3_4 */ +#define FC8_CTS_SDA_SSEL0_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 3) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 0) /* PIO3_4 */ +#define LCD_LCD_VD18_PIO3_4 IOCON_MUX(100, IOCON_TYPE_D, 1) /* PIO3_4 */ +#define CTIMER4_MATCH1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 4) /* PIO3_5 */ +#define FC8_RTS_SCL_SSEL1_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 3) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 0) /* PIO3_5 */ +#define LCD_LCD_VD19_PIO3_5 IOCON_MUX(101, IOCON_TYPE_D, 1) /* PIO3_5 */ +#define CTIMER4_MATCH2_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 4) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 0) /* PIO3_6 */ +#define LCD_LCD_VD0_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 2) /* PIO3_6 */ +#define LCD_LCD_VD20_PIO3_6 IOCON_MUX(102, IOCON_TYPE_D, 1) /* PIO3_6 */ +#define CTIMER4_CAPTURE2_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 4) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 0) /* PIO3_7 */ +#define LCD_LCD_VD1_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 2) /* PIO3_7 */ +#define LCD_LCD_VD21_PIO3_7 IOCON_MUX(103, IOCON_TYPE_D, 1) /* PIO3_7 */ +#define CTIMER4_CAPTURE3_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 0) /* PIO3_8 */ +#define LCD_LCD_VD22_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 1) /* PIO3_8 */ +#define LCD_LCD_VD2_PIO3_8 IOCON_MUX(104, IOCON_TYPE_D, 2) /* PIO3_8 */ +#define CTIMER0_CAPTURE2_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 0) /* PIO3_9 */ +#define LCD_LCD_VD23_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 1) /* PIO3_9 */ +#define LCD_LCD_VD3_PIO3_9 IOCON_MUX(105, IOCON_TYPE_D, 2) /* PIO3_9 */ +#define CTIMER3_MATCH0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 3) /* PIO3_10 */ +#define EMC_EMC_DYCS1_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 0) /* PIO3_10 */ +#define SCT0_OUT3_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 1) /* PIO3_10 */ +#define SWD_TRACEDATA0_PIO3_10 IOCON_MUX(106, IOCON_TYPE_D, 7) /* PIO3_10 */ +#define FC0_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 2) /* PIO3_11 */ +#define FC1_SCK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 3) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 0) /* PIO3_11 */ +#define MCLK_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 1) /* PIO3_11 */ +#define SWD_TRACEDATA3_PIO3_11 IOCON_MUX(107, IOCON_TYPE_D, 7) /* PIO3_11 */ +#define CLKOUT_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 5) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 3) /* PIO3_12 */ +#define EMC_EMC_CLK1_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 6) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 0) /* PIO3_12 */ +#define SCT0_OUT8_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 1) /* PIO3_12 */ +#define TRACECLK_PIO3_12 IOCON_MUX(108, IOCON_TYPE_D, 7) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 3) /* PIO3_13 */ +#define EMC_FBCK_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 6) /* PIO3_13 */ +#define FC9_CTS_SDA_SSEL0_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 2) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 0) /* PIO3_13 */ +#define SCT0_OUT9_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 1) /* PIO3_13 */ +#define SWD_TRACEDATA1_PIO3_13 IOCON_MUX(109, IOCON_TYPE_D, 7) /* PIO3_13 */ +#define CTIMER3_MATCH1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 3) /* PIO3_14 */ +#define FC9_RTS_SCL_SSEL1_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 2) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 0) /* PIO3_14 */ +#define SCT0_OUT4_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 1) /* PIO3_14 */ +#define SWD_TRACEDATA2_PIO3_14 IOCON_MUX(110, IOCON_TYPE_D, 7) /* PIO3_14 */ +#define FC8_SCK_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 1) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 0) /* PIO3_15 */ +#define SD_WR_PRT_PIO3_15 IOCON_MUX(111, IOCON_TYPE_D, 2) /* PIO3_15 */ +#define FC8_RXD_SDA_MOSI_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 1) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 0) /* PIO3_16 */ +#define SDIF_SD_D4_PIO3_16 IOCON_MUX(112, IOCON_TYPE_D, 2) /* PIO3_16 */ +#define FC8_TXD_SCL_MISO_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 1) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 0) /* PIO3_17 */ +#define SDIF_SD_D5_PIO3_17 IOCON_MUX(113, IOCON_TYPE_D, 2) /* PIO3_17 */ +#define CAN0_TD_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 4) /* PIO3_18 */ +#define CTIMER4_MATCH0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 3) /* PIO3_18 */ +#define FC8_CTS_SDA_SSEL0_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 1) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 0) /* PIO3_18 */ +#define SCT0_OUT5_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 5) /* PIO3_18 */ +#define SDIF_SD_D6_PIO3_18 IOCON_MUX(114, IOCON_TYPE_D, 2) /* PIO3_18 */ +#define CAN0_RD_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 4) /* PIO3_19 */ +#define CTIMER4_MATCH1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 3) /* PIO3_19 */ +#define FC8_RTS_SCL_SSEL1_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 1) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 0) /* PIO3_19 */ +#define SCT0_OUT6_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 5) /* PIO3_19 */ +#define SDIF_SD_D7_PIO3_19 IOCON_MUX(115, IOCON_TYPE_D, 2) /* PIO3_19 */ +#define CLKOUT_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 3) /* PIO3_20 */ +#define FC9_SCK_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 1) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 0) /* PIO3_20 */ +#define SCT0_OUT7_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 5) /* PIO3_20 */ +#define SD_CARD_INT_N_PIO3_20 IOCON_MUX(116, IOCON_TYPE_D, 2) /* PIO3_20 */ +#define ADC0_CH9_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define CTIMER4_MATCH3_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 3) /* PIO3_21 */ +#define FC9_RXD_SDA_MOSI_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 1) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 0) /* PIO3_21 */ +#define SD_BACKEND_PWR_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 2) /* PIO3_21 */ +#define UTICK0_CAPTURE2_PIO3_21 IOCON_MUX(117, IOCON_TYPE_D, 4) /* PIO3_21 */ +#define ADC0_CH10_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC9_TXD_SCL_MISO_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 1) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOCON_MUX(118, IOCON_TYPE_D, 0) /* PIO3_22 */ +#define FC2_CTS_SDA_SSEL0_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 1) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 0) /* PIO3_23 */ +#define UTICK0_CAPTURE3_PIO3_23 IOCON_MUX(119, IOCON_TYPE_D, 3) /* PIO3_23 */ +#define CTIMER4_CAPTURE0_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 2) /* PIO3_24 */ +#define FC2_RTS_SCL_SSEL1_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 1) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 0) /* PIO3_24 */ +#define USB0_VBUS_PIO3_24 IOCON_MUX(120, IOCON_TYPE_D, 3) /* PIO3_24 */ +#define CTIMER4_CAPTURE2_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 2) /* PIO3_25 */ +#define EMC_EMC_A14_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 6) /* PIO3_25 */ +#define FC4_SCK_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 3) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOCON_MUX(121, IOCON_TYPE_D, 0) /* PIO3_25 */ +#define EMC_EMC_A15_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 6) /* PIO3_26 */ +#define FC4_RXD_SDA_MOSI_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 3) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 0) /* PIO3_26 */ +#define SCT0_OUT0_PIO3_26 IOCON_MUX(122, IOCON_TYPE_D, 2) /* PIO3_26 */ +#define EMC_EMC_A16_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 6) /* PIO3_27 */ +#define FC4_TXD_SCL_MISO_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 3) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 0) /* PIO3_27 */ +#define SCT0_OUT1_PIO3_27 IOCON_MUX(123, IOCON_TYPE_D, 2) /* PIO3_27 */ +#define EMC_EMC_A17_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 6) /* PIO3_28 */ +#define FC4_CTS_SDA_SSEL0_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 3) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 0) /* PIO3_28 */ +#define SCT0_OUT2_PIO3_28 IOCON_MUX(124, IOCON_TYPE_D, 2) /* PIO3_28 */ +#define EMC_EMC_A18_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 6) /* PIO3_29 */ +#define FC4_RTS_SCL_SSEL1_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 3) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 0) /* PIO3_29 */ +#define SCT0_OUT3_PIO3_29 IOCON_MUX(125, IOCON_TYPE_D, 2) /* PIO3_29 */ +#define EMC_EMC_A19_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 6) /* PIO3_30 */ +#define FC4_SSEL2_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 3) /* PIO3_30 */ +#define FC9_CTS_SDA_SSEL0_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 0) /* PIO3_30 */ +#define SCT0_OUT4_PIO3_30 IOCON_MUX(126, IOCON_TYPE_D, 2) /* PIO3_30 */ +#define CTIMER4_MATCH2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 3) /* PIO3_31 */ +#define EMC_EMC_A20_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 6) /* PIO3_31 */ +#define FC9_RTS_SCL_SSEL1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 0) /* PIO3_31 */ +#define SCT0_IN0_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN1_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN2_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN3_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN4_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_IN6_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 5) /* PIO3_31 */ +#define SCT0_OUT5_PIO3_31 IOCON_MUX(127, IOCON_TYPE_D, 2) /* PIO3_31 */ +#define CTIMER4_CAPTURE1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 3) /* PIO4_0 */ +#define EMC_EMC_CS1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 6) /* PIO4_0 */ +#define FC6_CTS_SDA_SSEL0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 2) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 0) /* PIO4_0 */ +#define SCT0_IN0_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN1_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN2_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN3_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN4_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN5_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define SCT0_IN6_PIO4_0 IOCON_MUX(128, IOCON_TYPE_D, 5) /* PIO4_0 */ +#define EMC_EMC_CS2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 6) /* PIO4_1 */ +#define FC6_SCK_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 2) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 0) /* PIO4_1 */ +#define SCT0_IN0_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN1_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN2_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN3_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN4_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN5_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define SCT0_IN6_PIO4_1 IOCON_MUX(129, IOCON_TYPE_D, 5) /* PIO4_1 */ +#define EMC_EMC_CS3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 6) /* PIO4_2 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 2) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 0) /* PIO4_2 */ +#define SCT0_IN0_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN1_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN2_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN3_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN4_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN5_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define SCT0_IN6_PIO4_2 IOCON_MUX(130, IOCON_TYPE_D, 5) /* PIO4_2 */ +#define CTIMER0_CAPTURE3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 3) /* PIO4_3 */ +#define EMC_EMC_DYCS2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 6) /* PIO4_3 */ +#define FC6_TXD_SCL_MISO_WS_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 2) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 0) /* PIO4_3 */ +#define SCT0_IN0_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN1_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN2_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN3_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN4_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN5_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define SCT0_IN6_PIO4_3 IOCON_MUX(131, IOCON_TYPE_D, 5) /* PIO4_3 */ +#define EMC_EMC_DYCS3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 6) /* PIO4_4 */ +#define FC0_RTS_SCL_SSEL1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 3) /* PIO4_4 */ +#define FC4_SSEL3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 2) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 0) /* PIO4_4 */ +#define SCT0_IN0_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN1_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN2_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN3_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN4_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN5_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define SCT0_IN6_PIO4_4 IOCON_MUX(132, IOCON_TYPE_D, 5) /* PIO4_4 */ +#define CTIMER4_MATCH3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 4) /* PIO4_5 */ +#define EMC_EMC_CKE2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 6) /* PIO4_5 */ +#define FC0_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 3) /* PIO4_5 */ +#define FC9_CTS_SDA_SSEL0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 2) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 0) /* PIO4_5 */ +#define SCT0_IN0_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN1_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN2_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN3_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN4_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN5_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define SCT0_IN6_PIO4_5 IOCON_MUX(133, IOCON_TYPE_D, 5) /* PIO4_5 */ +#define EMC_EMC_CKE3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 6) /* PIO4_6 */ +#define FC9_RTS_SCL_SSEL1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 2) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 0) /* PIO4_6 */ +#define SCT0_IN0_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN1_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN2_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN3_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN4_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN5_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define SCT0_IN6_PIO4_6 IOCON_MUX(134, IOCON_TYPE_D, 5) /* PIO4_6 */ +#define CTIMER4_CAPTURE3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 2) /* PIO4_7 */ +#define GPIO_PIO47_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 0) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 5) /* PIO4_7 */ +#define USB0_FRAME_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 4) /* PIO4_7 */ +#define USB0_PORTPWRN_PIO4_7 IOCON_MUX(135, IOCON_TYPE_D, 3) /* PIO4_7 */ +#define ENET_ENET_TXD0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 1) /* PIO4_8 */ +#define FC2_SCK_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 2) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 0) /* PIO4_8 */ +#define SCT0_IN0_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN1_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN2_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN3_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN4_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN5_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define SCT0_IN6_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 5) /* PIO4_8 */ +#define USB0_LEDN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 4) /* PIO4_8 */ +#define USB0_OVERCURRENTN_PIO4_8 IOCON_MUX(136, IOCON_TYPE_D, 3) /* PIO4_8 */ +#define ENET_ENET_TXD1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 1) /* PIO4_9 */ +#define FC2_RXD_SDA_MOSI_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 2) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 0) /* PIO4_9 */ +#define SCT0_IN0_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN1_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN2_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN3_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN4_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN5_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define SCT0_IN6_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 5) /* PIO4_9 */ +#define USB1_FRAME_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 4) /* PIO4_9 */ +#define USB1_PORTPWRN_PIO4_9 IOCON_MUX(137, IOCON_TYPE_D, 3) /* PIO4_9 */ +#define ENET_RX_DV_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 1) /* PIO4_10 */ +#define FC2_TXD_SCL_MISO_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 2) /* PIO4_10 */ +#define GPIO_PIO410_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 0) /* PIO4_10 */ +#define SCT0_IN0_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN1_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN2_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN3_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN4_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN5_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define SCT0_IN6_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 5) /* PIO4_10 */ +#define USB1_LEDN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 4) /* PIO4_10 */ +#define USB1_OVERCURRENTN_PIO4_10 IOCON_MUX(138, IOCON_TYPE_D, 3) /* PIO4_10 */ +#define ENET_ENET_RXD0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 1) /* PIO4_11 */ +#define FC2_CTS_SDA_SSEL0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 0) /* PIO4_11 */ +#define SCT0_IN0_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN1_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN2_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN3_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN4_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN5_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define SCT0_IN6_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 5) /* PIO4_11 */ +#define USB0_IDVALUE_PIO4_11 IOCON_MUX(139, IOCON_TYPE_D, 3) /* PIO4_11 */ +#define ENET_ENET_RXD1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 1) /* PIO4_12 */ +#define FC2_RTS_SCL_SSEL1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 0) /* PIO4_12 */ +#define SCT0_IN0_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN1_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN2_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN3_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN4_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN5_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define SCT0_IN6_PIO4_12 IOCON_MUX(140, IOCON_TYPE_D, 5) /* PIO4_12 */ +#define CTIMER4_MATCH0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 2) /* PIO4_13 */ +#define ENET_TX_EN_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 1) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 0) /* PIO4_13 */ +#define SCT0_IN0_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN1_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN2_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN3_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN4_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN5_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define SCT0_IN6_PIO4_13 IOCON_MUX(141, IOCON_TYPE_D, 5) /* PIO4_13 */ +#define CTIMER4_MATCH1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 2) /* PIO4_14 */ +#define ENET_RX_CLK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 1) /* PIO4_14 */ +#define FC9_SCK_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 3) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 0) /* PIO4_14 */ +#define SCT0_IN0_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN1_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN2_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN3_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN4_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN5_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define SCT0_IN6_PIO4_14 IOCON_MUX(142, IOCON_TYPE_D, 5) /* PIO4_14 */ +#define CTIMER4_MATCH2_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 2) /* PIO4_15 */ +#define ENET_MDC_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 1) /* PIO4_15 */ +#define FC9_RXD_SDA_MOSI_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 3) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOCON_MUX(143, IOCON_TYPE_D, 0) /* PIO4_15 */ +#define CTIMER4_MATCH3_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 2) /* PIO4_16 */ +#define ENET_MDIO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 1) /* PIO4_16 */ +#define FC9_TXD_SCL_MISO_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 3) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOCON_MUX(144, IOCON_TYPE_D, 0) /* PIO4_16 */ + +#endif diff --git a/dts/nxp/lpc/LPC5502JBD64-pinctrl.h b/dts/nxp/lpc/LPC5502JBD64-pinctrl.h new file mode 100644 index 000000000..67bf5604e --- /dev/null +++ b/dts/nxp/lpc/LPC5502JBD64-pinctrl.h @@ -0,0 +1,2691 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5502JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5502JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC5502JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ + +#endif diff --git a/dts/nxp/lpc/LPC5502JHI48-pinctrl.h b/dts/nxp/lpc/LPC5502JHI48-pinctrl.h new file mode 100644 index 000000000..dab4d7779 --- /dev/null +++ b/dts/nxp/lpc/LPC5502JHI48-pinctrl.h @@ -0,0 +1,1849 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5502JHI48/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5502JHI48_ +#define _ZEPHYR_DTS_BINDING_LPC5502JHI48_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ + +#endif diff --git a/dts/nxp/lpc/LPC5504JBD64-pinctrl.h b/dts/nxp/lpc/LPC5504JBD64-pinctrl.h new file mode 100644 index 000000000..bc10a0359 --- /dev/null +++ b/dts/nxp/lpc/LPC5504JBD64-pinctrl.h @@ -0,0 +1,2691 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5504JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5504JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC5504JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ + +#endif diff --git a/dts/nxp/lpc/LPC5504JHI48-pinctrl.h b/dts/nxp/lpc/LPC5504JHI48-pinctrl.h new file mode 100644 index 000000000..357cc86e5 --- /dev/null +++ b/dts/nxp/lpc/LPC5504JHI48-pinctrl.h @@ -0,0 +1,1849 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5504JHI48/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5504JHI48_ +#define _ZEPHYR_DTS_BINDING_LPC5504JHI48_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ + +#endif diff --git a/dts/nxp/lpc/LPC5506JBD64-pinctrl.h b/dts/nxp/lpc/LPC5506JBD64-pinctrl.h new file mode 100644 index 000000000..8589f0dcd --- /dev/null +++ b/dts/nxp/lpc/LPC5506JBD64-pinctrl.h @@ -0,0 +1,2691 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5506JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5506JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC5506JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ + +#endif diff --git a/dts/nxp/lpc/LPC5506JHI48-pinctrl.h b/dts/nxp/lpc/LPC5506JHI48-pinctrl.h new file mode 100644 index 000000000..b93092ccb --- /dev/null +++ b/dts/nxp/lpc/LPC5506JHI48-pinctrl.h @@ -0,0 +1,1849 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5506JHI48/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5506JHI48_ +#define _ZEPHYR_DTS_BINDING_LPC5506JHI48_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ + +#endif diff --git a/dts/nxp/lpc/LPC5512JBD100-pinctrl.h b/dts/nxp/lpc/LPC5512JBD100-pinctrl.h new file mode 100644 index 000000000..a0edd3e47 --- /dev/null +++ b/dts/nxp/lpc/LPC5512JBD100-pinctrl.h @@ -0,0 +1,3694 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5512JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5512JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC5512JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CAN0_TD_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 9) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC5512JBD64-pinctrl.h b/dts/nxp/lpc/LPC5512JBD64-pinctrl.h new file mode 100644 index 000000000..772028c80 --- /dev/null +++ b/dts/nxp/lpc/LPC5512JBD64-pinctrl.h @@ -0,0 +1,2237 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5512JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5512JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC5512JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ + +#endif diff --git a/dts/nxp/lpc/LPC5514JBD100-pinctrl.h b/dts/nxp/lpc/LPC5514JBD100-pinctrl.h new file mode 100644 index 000000000..e0b06abde --- /dev/null +++ b/dts/nxp/lpc/LPC5514JBD100-pinctrl.h @@ -0,0 +1,3700 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5514JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5514JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC5514JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CAN0_TD_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 9) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC5514JBD64-pinctrl.h b/dts/nxp/lpc/LPC5514JBD64-pinctrl.h new file mode 100644 index 000000000..06bed5270 --- /dev/null +++ b/dts/nxp/lpc/LPC5514JBD64-pinctrl.h @@ -0,0 +1,2239 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5514JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5514JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC5514JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ + +#endif diff --git a/dts/nxp/lpc/LPC5514JEV59-pinctrl.h b/dts/nxp/lpc/LPC5514JEV59-pinctrl.h new file mode 100644 index 000000000..9e0419998 --- /dev/null +++ b/dts/nxp/lpc/LPC5514JEV59-pinctrl.h @@ -0,0 +1,2269 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5514JEV59/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5514JEV59_ +#define _ZEPHYR_DTS_BINDING_LPC5514JEV59_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ + +#endif diff --git a/dts/nxp/lpc/LPC5516JBD100-pinctrl.h b/dts/nxp/lpc/LPC5516JBD100-pinctrl.h new file mode 100644 index 000000000..ede3efd59 --- /dev/null +++ b/dts/nxp/lpc/LPC5516JBD100-pinctrl.h @@ -0,0 +1,3700 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5516JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5516JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC5516JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CAN0_TD_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 9) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC5516JBD64-pinctrl.h b/dts/nxp/lpc/LPC5516JBD64-pinctrl.h new file mode 100644 index 000000000..82dbcbe8e --- /dev/null +++ b/dts/nxp/lpc/LPC5516JBD64-pinctrl.h @@ -0,0 +1,2239 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5516JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5516JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC5516JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ + +#endif diff --git a/dts/nxp/lpc/LPC5516JEV59-pinctrl.h b/dts/nxp/lpc/LPC5516JEV59-pinctrl.h new file mode 100644 index 000000000..27a43b097 --- /dev/null +++ b/dts/nxp/lpc/LPC5516JEV59-pinctrl.h @@ -0,0 +1,2269 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5516JEV59/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5516JEV59_ +#define _ZEPHYR_DTS_BINDING_LPC5516JEV59_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ + +#endif diff --git a/dts/nxp/lpc/LPC5516JEV98-pinctrl.h b/dts/nxp/lpc/LPC5516JEV98-pinctrl.h new file mode 100644 index 000000000..d250e8adf --- /dev/null +++ b/dts/nxp/lpc/LPC5516JEV98-pinctrl.h @@ -0,0 +1,3700 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5516JEV98/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5516JEV98_ +#define _ZEPHYR_DTS_BINDING_LPC5516JEV98_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CAN0_TD_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 9) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC5526JBD100-pinctrl.h b/dts/nxp/lpc/LPC5526JBD100-pinctrl.h new file mode 100644 index 000000000..b5b9a9930 --- /dev/null +++ b/dts/nxp/lpc/LPC5526JBD100-pinctrl.h @@ -0,0 +1,3734 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5526JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5526JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC5526JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD0_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD0_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD0_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define SD0_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define SD0_CARD_DET_N_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 7) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define SD1_CMD_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 7) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define SDIF_SD1_D2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 7) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD0_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define SD1_CARD_DET_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 9) /* PIO1_17 */ +#define SD1_CARD_INT_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 7) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define SD1_POW_EN_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 1) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD0_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define SDIF_SD1_D3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 3) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define SDIF_SD1_D1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 3) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define SDIF_SD1_D0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 3) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define SDIF_SD0_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define SDIF_SD0_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define SD1_CLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 2) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC5526JBD64-pinctrl.h b/dts/nxp/lpc/LPC5526JBD64-pinctrl.h new file mode 100644 index 000000000..0d1ff2e48 --- /dev/null +++ b/dts/nxp/lpc/LPC5526JBD64-pinctrl.h @@ -0,0 +1,2254 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5526JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5526JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC5526JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ + +#endif diff --git a/dts/nxp/lpc/LPC5526JEV98-pinctrl.h b/dts/nxp/lpc/LPC5526JEV98-pinctrl.h new file mode 100644 index 000000000..dde7a3c09 --- /dev/null +++ b/dts/nxp/lpc/LPC5526JEV98-pinctrl.h @@ -0,0 +1,3734 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5526JEV98/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5526JEV98_ +#define _ZEPHYR_DTS_BINDING_LPC5526JEV98_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD0_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD0_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD0_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define SD0_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define SD0_CARD_DET_N_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 7) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define SD1_CMD_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 7) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define SDIF_SD1_D2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 7) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD0_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define SD1_CARD_DET_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 9) /* PIO1_17 */ +#define SD1_CARD_INT_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 7) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define SD1_POW_EN_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 1) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD0_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define SDIF_SD1_D3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 3) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define SDIF_SD1_D1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 3) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define SDIF_SD1_D0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 3) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define SDIF_SD0_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define SDIF_SD0_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define SD1_CLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 2) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC5528JBD100-pinctrl.h b/dts/nxp/lpc/LPC5528JBD100-pinctrl.h new file mode 100644 index 000000000..a762f61fe --- /dev/null +++ b/dts/nxp/lpc/LPC5528JBD100-pinctrl.h @@ -0,0 +1,3734 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5528JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5528JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC5528JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD0_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD0_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD0_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define SD0_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define SD0_CARD_DET_N_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 7) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define SD1_CMD_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 7) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define SDIF_SD1_D2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 7) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD0_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define SD1_CARD_DET_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 9) /* PIO1_17 */ +#define SD1_CARD_INT_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 7) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define SD1_POW_EN_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 1) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD0_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define SDIF_SD1_D3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 3) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define SDIF_SD1_D1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 3) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define SDIF_SD1_D0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 3) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define SDIF_SD0_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define SDIF_SD0_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define SD1_CLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 2) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC5528JBD64-pinctrl.h b/dts/nxp/lpc/LPC5528JBD64-pinctrl.h new file mode 100644 index 000000000..efa9f1f69 --- /dev/null +++ b/dts/nxp/lpc/LPC5528JBD64-pinctrl.h @@ -0,0 +1,2254 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5528JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5528JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC5528JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ + +#endif diff --git a/dts/nxp/lpc/LPC5528JEV59-pinctrl.h b/dts/nxp/lpc/LPC5528JEV59-pinctrl.h new file mode 100644 index 000000000..29a528286 --- /dev/null +++ b/dts/nxp/lpc/LPC5528JEV59-pinctrl.h @@ -0,0 +1,2285 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5528JEV59/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5528JEV59_ +#define _ZEPHYR_DTS_BINDING_LPC5528JEV59_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ + +#endif diff --git a/dts/nxp/lpc/LPC5528JEV98-pinctrl.h b/dts/nxp/lpc/LPC5528JEV98-pinctrl.h new file mode 100644 index 000000000..265bb4104 --- /dev/null +++ b/dts/nxp/lpc/LPC5528JEV98-pinctrl.h @@ -0,0 +1,3734 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5528JEV98/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5528JEV98_ +#define _ZEPHYR_DTS_BINDING_LPC5528JEV98_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD0_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD0_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD0_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define SD0_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define SD0_CARD_DET_N_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 7) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define SD1_CMD_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 7) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define SDIF_SD1_D2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 7) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD0_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define SD1_CARD_DET_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 9) /* PIO1_17 */ +#define SD1_CARD_INT_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 7) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define SD1_POW_EN_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 1) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD0_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define SDIF_SD1_D3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 3) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define SDIF_SD1_D1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 3) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define SDIF_SD1_D0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 3) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define SDIF_SD0_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define SDIF_SD0_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define SD1_CLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 2) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC5534JBD100-pinctrl.h b/dts/nxp/lpc/LPC5534JBD100-pinctrl.h new file mode 100644 index 000000000..0c080a61f --- /dev/null +++ b/dts/nxp/lpc/LPC5534JBD100-pinctrl.h @@ -0,0 +1,7141 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5534JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5534JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC5534JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG023_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG024_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG025_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG026_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG027_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG028_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG029_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG030_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG031_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG032_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG033_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG034_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG035_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG036_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG037_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG038_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG039_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG040_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG041_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG042_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG043_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG044_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG045_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG046_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG047_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG048_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG049_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG050_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG051_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMIC0_DATA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 5) /* PIO0_0 */ +#define ENC0_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC0_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define EXTTRIG_IN8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PIO0_0_PIO0_0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PWM0_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_B2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 11) /* PIO0_0 */ +#define PWM1_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SWCLK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 9) /* PIO0_0 */ +#define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_CH2B_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define AOI0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 12) /* PIO0_1 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CT_INP0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG023_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG024_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG025_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG026_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG027_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG028_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG029_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG030_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG031_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG032_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG033_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG034_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG035_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG036_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG037_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG038_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG039_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG040_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG041_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG042_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG043_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG044_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG045_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG046_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG047_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG048_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG049_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG050_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG051_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_CLK0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PIO0_1_PIO0_1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define AOI0_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define AOI1_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CT_INP1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG023_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG024_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG025_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG026_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG027_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG028_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG029_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG030_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG031_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG032_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG033_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG034_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG035_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG036_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG037_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG038_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG039_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG040_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG041_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG042_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG043_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG044_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG045_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG046_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG047_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG048_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG049_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG050_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG051_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ENC0_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC0_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define EXTTRIG_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define FLEXSPI0_DATA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 5) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PIO0_2_PIO0_2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PWM0_A2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 11) /* PIO0_2 */ +#define PWM0_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG023_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG024_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG025_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG026_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG027_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG028_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG029_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG030_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG031_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG032_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG033_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG034_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG035_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG036_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG037_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG038_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG039_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG040_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG041_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG042_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG043_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG044_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG045_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG046_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG047_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG048_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG049_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG050_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG051_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define FLEXSPI0_DATA2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PIO0_3_PIO0_3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PWM1_B0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 11) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define AOI0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CT_INP12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG023_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG024_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG025_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG026_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG027_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG028_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG029_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG030_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG031_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG032_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG033_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG034_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG035_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG036_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG037_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG038_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG039_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG040_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG041_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG042_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG043_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG044_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG045_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG046_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG047_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG048_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG049_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG050_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG051_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ENC0_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC0_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define EXTTRIG_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 9) /* PIO0_4 */ +#define FLEXSPI0_DATA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 5) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PIO0_4_PIO0_4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PWM0_B3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 11) /* PIO0_4 */ +#define PWM0_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG023_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG024_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG025_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG026_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG027_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG028_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG029_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG030_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG031_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG032_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG033_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG034_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG035_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG036_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG037_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG038_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG039_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG040_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG041_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG042_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG043_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG044_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG045_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG046_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG047_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG048_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG049_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG050_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG051_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ENC0_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC0_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define EXTTRIG_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PIO0_5_PIO0_5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PWM0_A0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 11) /* PIO0_5 */ +#define PWM0_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define AOI0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define CT_INP13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG023_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG024_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG025_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG026_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG027_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG028_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG029_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG030_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG031_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG032_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG033_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG034_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG035_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG036_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG037_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG038_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG039_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG040_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG041_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG042_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG043_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG044_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG045_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG046_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG047_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG048_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG049_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG050_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG051_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ENC0_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC0_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define EXTTRIG_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 9) /* PIO0_6 */ +#define FLEXSPI0_DATA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PIO0_6_PIO0_6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PWM0_B0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 11) /* PIO0_6 */ +#define PWM0_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_OUT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 8) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define AOI0_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define AOI1_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG023_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG024_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG025_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG026_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG027_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG028_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG029_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG030_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG031_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG032_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG033_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG034_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG035_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG036_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG037_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG038_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG039_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG040_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG041_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG042_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG043_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG044_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG045_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG046_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG047_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG048_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG049_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG050_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG051_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMIC0_CLK0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 5) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP1_IN0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP2_OUT_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 13) /* PIO0_7 */ +#define MCLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 8) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PIO0_7_PIO0_7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PWM0_B0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 11) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG023_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG024_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG025_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG026_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG027_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG028_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG029_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG030_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG031_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG032_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG033_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG034_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG035_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG036_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG037_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG038_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG039_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG040_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG041_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG042_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG043_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG044_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG045_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG046_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG047_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG048_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG049_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG050_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG051_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define OPAMP0_DP0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PIO0_8_PIO0_8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define AOI0_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define AOI1_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG023_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG024_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG025_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG026_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG027_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG028_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG029_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG030_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG031_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG032_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG033_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG034_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG035_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG036_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG037_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG038_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG039_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG040_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG041_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG042_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG043_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG044_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG045_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG046_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG047_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG048_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG049_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG050_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG051_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define I3C0_SCL_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 7) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PIO0_9_PIO0_9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PWM1_A2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 11) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SWDIO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 9) /* PIO0_9 */ +#define ADC0_CH1A_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CT_INP10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG023_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG024_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG025_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG026_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG027_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG028_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG029_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG030_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG031_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG032_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG033_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG034_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG035_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG036_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG037_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG038_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG039_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG040_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG041_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG042_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG043_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG044_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG045_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG046_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG047_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG048_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG049_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG050_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG051_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PIO0_10_PIO0_10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_CH2A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define AOI1_OUT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 12) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG023_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG024_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG025_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG026_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG027_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG028_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG029_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG030_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG031_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG032_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG033_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG034_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG035_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG036_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG037_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG038_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG039_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG040_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG041_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG042_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG043_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG044_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG045_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG046_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG047_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG048_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG049_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG050_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG051_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PIO0_11_PIO0_11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define ADC0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC1_CH3A_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC1_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC1_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC1_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC1_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define AOI1_OUT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 12) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG023_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG024_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG025_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG026_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG027_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG028_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG029_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG030_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG031_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG032_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG033_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG034_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG035_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG036_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG037_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG038_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG039_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG040_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG041_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG042_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG043_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG044_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG045_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG046_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG047_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG048_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG049_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG050_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG051_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 7) /* PIO0_12 */ +#define FREQME_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PIO0_12_PIO0_12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */ +#define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define AOI0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CT_INP0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG023_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG024_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG025_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG026_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG027_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG028_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG029_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG030_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG031_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG032_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG033_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG034_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG035_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG036_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG037_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG038_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG039_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG040_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG041_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG042_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG043_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG044_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG045_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG046_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG047_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG048_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG049_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG050_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG051_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ENC0_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC0_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define EXTTRIG_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PIO0_13_PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PWM0_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define AOI0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CT_INP1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG023_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG024_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG025_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG026_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG027_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG028_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG029_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG030_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG031_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG032_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG033_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG034_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG035_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG036_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG037_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG038_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG039_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG040_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG041_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG042_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG043_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG044_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG045_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG046_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG047_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG048_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG049_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG050_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG051_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ENC0_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC0_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define EXTTRIG_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PIO0_14_PIO0_14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PWM0_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH3A_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CT_INP16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG023_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG024_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG025_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG026_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG027_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG028_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG029_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG030_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG031_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG032_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG033_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG034_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG035_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG036_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG037_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG038_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG039_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG040_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG041_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG042_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG043_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG044_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG045_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG046_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG047_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG048_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG049_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG050_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG051_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PIO0_15_PIO0_15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH3B_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define AOI0_OUT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 12) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CT_INP4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG023_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG024_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG025_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG026_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG027_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG028_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG029_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG030_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG031_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG032_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG033_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG034_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG035_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG036_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG037_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG038_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG039_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG040_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG041_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG042_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG043_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG044_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG045_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG046_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG047_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG048_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG049_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG050_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG051_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PIO0_16_PIO0_16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define AOI0_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define AOI1_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG023_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG024_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG025_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG026_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG027_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG028_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG029_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG030_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG031_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG032_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG033_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG034_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG035_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG036_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG037_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG038_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG039_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG040_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG041_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG042_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG043_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG044_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG045_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG046_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG047_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG048_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG049_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG050_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG051_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 1) /* PIO0_17 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 8) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define HSCMP1_OUT_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 13) /* PIO0_17 */ +#define HSCMP2_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PIO0_17_PIO0_17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define AOI0_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define AOI1_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG023_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG024_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG025_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG026_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG027_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG028_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG029_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG030_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG031_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG032_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG033_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG034_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG035_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG036_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG037_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG038_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG039_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG040_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG041_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG042_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG043_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG044_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG045_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG046_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG047_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG048_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG049_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG050_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG051_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PIO0_18_PIO0_18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PWM1_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 11) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SWO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 8) /* PIO0_18 */ +#define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define AOI0_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define AOI1_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG023_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG024_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG025_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG026_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG027_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG028_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG029_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG030_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG031_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG032_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG033_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG034_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG035_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG036_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG037_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG038_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG039_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG040_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG041_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG042_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG043_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG044_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG045_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG046_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG047_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG048_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG049_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG050_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG051_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ENC0_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC0_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define EXTTRIG_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define FLEXSPI0_SCLK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 5) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PIO0_19_PIO0_19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PWM0_B1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 11) /* PIO0_19 */ +#define PWM0_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CT_INP15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG023_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG024_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG025_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG026_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG027_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG028_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG029_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG030_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG031_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG032_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG033_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG034_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG035_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG036_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG037_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG038_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG039_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG040_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG041_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG042_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG043_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG044_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG045_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG046_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG047_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG048_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG049_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG050_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG051_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PIO0_20_PIO0_20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PWM1_X2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 13) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define AOI0_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define AOI1_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG023_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG024_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG025_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG026_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG027_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG028_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG029_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG030_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG031_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG032_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG033_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG034_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG035_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG036_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG037_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG038_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG039_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG040_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG041_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG042_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG043_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG044_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG045_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG046_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG047_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG048_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG049_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG050_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG051_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ENC0_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC0_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define EXTTRIG_IN7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_CTS_SDA_SSEL0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define FLEXSPI0_SS0_N_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PIO0_21_PIO0_21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PWM0_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_B1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 11) /* PIO0_21 */ +#define PWM1_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_OUT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CT_INP15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG023_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG024_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG025_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG026_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG027_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG028_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG029_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG030_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG031_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG032_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG033_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG034_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG035_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG036_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG037_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG038_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG039_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG040_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG041_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG042_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG043_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG044_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG045_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG046_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG047_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG048_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG049_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG050_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG051_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ENC0_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC0_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC1_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC1_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define EXTTRIG_IN5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define FC7_RTS_SCL_SSEL1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define FLEXSPI0_SCLK_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 5) /* PIO0_22 */ +#define FLEXSPI0_SS1_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 6) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PIO0_22_PIO0_22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PWM0_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_X0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 11) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH8B_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC1_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC1_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC1_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC1_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG024_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG025_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG026_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG027_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG028_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG029_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG030_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG031_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG032_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG033_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG034_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG035_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG036_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG037_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG038_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG039_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG040_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG041_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG042_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG043_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG044_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG045_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG046_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG047_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG048_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG049_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG050_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG051_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PIO0_23_PIO0_23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CT_INP8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG023_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG025_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG026_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG027_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG028_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG029_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG030_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG031_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG032_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG033_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG034_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG035_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG036_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG037_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG038_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG039_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG040_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG041_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG042_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG043_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG044_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG045_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG046_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG047_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG048_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG049_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG050_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG051_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define HSCMP0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define I3C0_SDA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 5) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PIO0_24_PIO0_24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PWM0_A1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 11) /* PIO0_24 */ +#define PWM0_X0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 13) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SWD_TRACEDATA0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 6) /* PIO0_24 */ +#define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CT_INP9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG023_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG024_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG026_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG027_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG028_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG029_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG030_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG031_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG032_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG033_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG034_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG035_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG036_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG037_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG038_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG039_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG040_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG041_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG042_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG043_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG044_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG045_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG046_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG047_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG048_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG049_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG050_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG051_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ENC0_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC0_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC1_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC1_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define EXTTRIG_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define FLEXSPI0_DQS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define HSCMP0_OUT_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 7) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PIO0_25_PIO0_25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PWM0_A0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 11) /* PIO0_25 */ +#define PWM0_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CT_INP14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG023_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG024_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG025_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG027_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG028_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG029_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG030_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG031_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG032_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG033_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG034_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG035_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG036_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG037_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG038_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG039_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG040_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG041_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG042_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG043_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG044_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG045_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG046_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG047_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG048_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG049_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG050_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG051_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PIO0_26_PIO0_26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PWM0_B1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 11) /* PIO0_26 */ +#define RTC_TAMPER2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG023_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG024_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG025_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG026_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG028_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG029_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG030_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG031_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG032_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG033_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG034_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG035_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG036_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG037_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG038_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG039_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG040_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG041_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG042_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG043_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG044_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG045_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG046_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG047_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG048_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG049_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG050_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG051_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define OPAMP1_DP0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PIO0_27_PIO0_27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define ADC0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC1_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC1_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC1_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC1_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CT_INP11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG023_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG024_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG025_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG026_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG027_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG029_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG030_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG031_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG032_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG033_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG034_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG035_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG036_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG037_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG038_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG039_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG040_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG041_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG042_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG043_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG044_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG045_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG046_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG047_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG048_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG049_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG050_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG051_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define I3C0_PUR_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 8) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PIO0_28_PIO0_28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PWM0_A2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 11) /* PIO0_28 */ +#define RTC_TAMPER1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define AOI0_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG023_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG024_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG025_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG026_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG027_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG028_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG030_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG031_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG032_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG033_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG034_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG035_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG036_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG037_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG038_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG039_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG040_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG041_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG042_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG043_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG044_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG045_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG046_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG047_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG048_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG049_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG050_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG051_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ENC0_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC0_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define EXTTRIG_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 6) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PIO0_29_PIO0_29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PWM0_A1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 11) /* PIO0_29 */ +#define PWM0_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define AOI1_OUT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 12) /* PIO0_30 */ +#define CAN0_TD_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 6) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG023_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG024_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG025_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG026_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG027_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG028_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG029_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG031_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG032_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG033_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG034_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG035_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG036_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG037_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG038_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG039_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG040_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG041_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG042_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG043_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG044_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG045_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG046_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG047_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG048_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG049_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG050_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG051_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 9) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PIO0_30_PIO0_30_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PWM1_A1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 11) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH8A_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define AOI0_OUT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 12) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG023_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG024_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG025_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG026_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG027_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG028_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG029_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG030_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG032_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG033_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG034_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG035_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG036_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG037_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG038_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG039_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG040_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG041_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG042_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG043_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG044_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG045_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG046_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG047_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG048_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG049_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG050_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG051_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define I3C0_SCL_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 15) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PIO0_31_PIO0_31_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_CH0B_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define AOI1_OUT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 12) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CT_INP2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG023_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG024_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG025_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG026_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG027_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG028_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG029_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG030_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG031_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG032_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG033_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG034_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG035_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG036_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG037_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG038_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG039_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG040_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG041_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG042_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG043_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG044_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG045_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG046_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG047_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG048_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG049_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG050_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG051_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PIO1_0_PIO1_0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CT_INP3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG023_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG024_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG025_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG026_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG027_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG028_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG029_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG030_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG031_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG032_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG033_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG034_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG035_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG036_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG037_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG038_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG039_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG040_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG041_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG042_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG043_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG044_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG045_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG046_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG047_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG048_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG049_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG050_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG051_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PIO1_1_PIO1_1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PWM0_B2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 11) /* PIO1_1 */ +#define RTC_ALARMOUT_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 10) /* PIO1_1 */ +#define RTC_TAMPER0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define TRACECLK_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define AOI0_OUT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 12) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG023_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG024_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG025_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG026_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG027_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG028_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG029_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG030_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG031_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG032_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG033_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG034_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG035_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG036_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG037_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG038_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG039_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG040_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG041_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG042_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG043_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG044_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG045_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG046_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG047_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG048_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG049_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG050_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG051_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PIO1_2_PIO1_2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PWM0_B0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 11) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG023_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG024_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG025_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG026_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG027_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG028_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG029_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG030_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG031_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG032_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG033_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG034_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG035_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG036_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG037_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG038_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG039_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG040_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG041_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG042_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG043_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG044_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG045_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG046_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG047_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG048_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG049_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG050_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG051_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PIO1_3_PIO1_3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PWM0_A3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 11) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC1_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC1_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC1_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC1_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define AOI0_TRIGOUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 12) /* PIO1_4 */ +#define AOI1_TRIGOUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 12) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG023_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG024_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG025_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG026_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG027_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG028_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG029_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG030_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG031_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG032_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG033_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG034_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG035_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG036_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG037_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG038_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG039_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG040_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG041_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG042_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG043_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG044_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG045_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG046_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG047_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG048_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG049_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG050_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG051_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ENC0_PHASEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define ENC0_PHASEB_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define ENC1_PHASEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define ENC1_PHASEB_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define EXTTRIG_IN8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 7) /* PIO1_4 */ +#define FREQME_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PIO1_4_PIO1_4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PWM0_B2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 11) /* PIO1_4 */ +#define PWM0_EXTA0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_EXTA1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_EXTA2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_EXTA3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_EXTA0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_EXTA1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_EXTA2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_EXTA3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define ADC0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC1_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC1_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC1_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC1_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define AOI0_TRIGOUT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 12) /* PIO1_5 */ +#define AOI1_TRIGOUT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 12) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG023_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG024_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG025_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG026_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG027_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG028_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG029_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG030_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG031_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG032_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG033_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG034_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG035_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG036_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG037_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG038_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG039_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG040_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG041_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG042_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG043_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG044_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG045_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG046_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG047_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG048_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG049_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG050_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG051_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define HSCMP0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PIO1_5_PIO1_5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PWM1_A3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 11) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define ADC0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC1_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC1_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC1_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC1_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define AOI0_TRIGOUT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 12) /* PIO1_6 */ +#define AOI1_TRIGOUT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 12) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG023_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG024_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG025_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG026_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG027_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG028_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG029_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG030_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG031_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG032_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG033_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG034_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG035_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG036_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG037_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG038_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG039_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG040_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG041_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG042_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG043_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG044_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG045_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG046_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG047_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG048_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG049_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG050_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG051_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define HSCMP0_OUT_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 13) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PIO1_6_PIO1_6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PWM0_A1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 11) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define ADC0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC1_CH3B_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC1_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC1_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC1_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC1_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define AOI1_OUT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 12) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG023_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG024_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG025_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG026_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG027_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG028_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG029_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG030_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG031_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG032_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG033_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG034_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG035_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG036_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG037_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG038_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG039_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG040_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG041_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG042_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG043_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG044_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG045_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG046_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG047_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG048_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG049_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG050_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG051_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PIO1_7_PIO1_7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define ADC0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC1_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC1_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC1_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC1_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define AOI0_TRIGOUT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 13) /* PIO1_8 */ +#define AOI1_OUT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 12) /* PIO1_8 */ +#define AOI1_TRIGOUT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 13) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG023_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG024_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG025_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG026_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG027_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG028_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG029_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG030_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG031_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG032_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG033_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG034_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG035_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG036_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG037_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG038_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG039_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG040_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG041_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG042_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG043_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG044_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG045_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG046_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG047_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG048_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG049_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG050_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG051_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC1_SCK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 7) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PIO1_8_PIO1_8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PWM0_A2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 11) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define ADC0_CH0A_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC1_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC1_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC1_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC1_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define AOI1_OUT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 12) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CT_INP4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG023_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG024_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG025_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG026_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG027_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG028_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG029_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG030_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG031_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG032_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG033_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG034_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG035_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG036_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG037_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG038_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG039_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG040_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG041_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG042_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG043_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG044_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG045_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG046_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG047_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG048_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG049_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG050_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG051_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define HSCMP0_IN4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define OPAMP0_OUT_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PIO1_9_PIO1_9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define ADC0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC1_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC1_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC1_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC1_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define AOI0_TRIGOUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 12) /* PIO1_10 */ +#define AOI1_TRIGOUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 12) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG023_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG024_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG025_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG026_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG027_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG028_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG029_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG030_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG031_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG032_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG033_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG034_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG035_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG036_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG037_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG038_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG039_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG040_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG041_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG042_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG043_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG044_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG045_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG046_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG047_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG048_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG049_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG050_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG051_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define HSCMP1_IN3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define HSCMP2_OUT_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 13) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PIO1_10_PIO1_10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PWM0_X1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 11) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 4) /* PIO1_10 */ +#define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CT_INP5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG023_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG024_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG025_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG026_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG027_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG028_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG029_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG030_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG031_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG032_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG033_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG034_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG035_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG036_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG037_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG038_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG039_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG040_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG041_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG042_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG043_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG044_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG045_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG046_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG047_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG048_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG049_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG050_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG051_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ENC0_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC0_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define EXTTRIG_IN8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define FC6_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 10) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define HS_SPI_SSEL0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PIO1_11_PIO1_11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PWM0_A0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 11) /* PIO1_11 */ +#define PWM0_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC1_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC1_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC1_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC1_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define AOI0_OUT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 12) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG023_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG024_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG025_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG026_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG027_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG028_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG029_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG030_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG031_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG032_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG033_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG034_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG035_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG036_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG037_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG038_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG039_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG040_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG041_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG042_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG043_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG044_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG045_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG046_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG047_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG048_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG049_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG050_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG051_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ENC0_PHASEA_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define ENC0_PHASEB_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define ENC1_PHASEA_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define ENC1_PHASEB_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define EXTTRIG_IN9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define HSCMP0_IN1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PIO1_12_PIO1_12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PWM0_A3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 11) /* PIO1_12 */ +#define PWM0_EXTA0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_EXTA1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_EXTA2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_EXTA3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_EXTA0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_EXTA1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_EXTA2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_EXTA3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 4) /* PIO1_12 */ +#define ACMP0VREF_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define AOI0_OUT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 12) /* PIO1_13 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CT_INP6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG023_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG024_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG025_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG026_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG027_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG028_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG029_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG030_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG031_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG032_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG033_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG034_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG035_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG036_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG037_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG038_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG039_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG040_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG041_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG042_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG043_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG044_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG045_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG046_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG047_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG048_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG049_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG050_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG051_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PIO1_13_PIO1_13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PWM1_X1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 11) /* PIO1_13 */ +#define SCT0_OUT8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 8) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 4) /* PIO1_13 */ +#define ADC0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC1_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC1_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC1_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC1_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG023_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG024_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG025_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG026_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG027_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG028_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG029_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG030_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG031_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG032_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG033_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG034_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG035_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG036_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG037_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG038_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG039_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG040_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG041_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG042_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG043_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG044_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG045_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG046_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG047_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG048_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG049_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG050_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG051_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ENC0_PHASEA_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define ENC0_PHASEB_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define ENC1_PHASEA_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define ENC1_PHASEB_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define EXTTRIG_IN9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PIO1_14_PIO1_14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PWM0_B3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 11) /* PIO1_14 */ +#define PWM0_EXTA0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_EXTA1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_EXTA2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_EXTA3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_EXTA0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_EXTA1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_EXTA2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_EXTA3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define ADC0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CT_INP7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG023_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG024_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG025_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG026_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG027_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG028_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG029_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG030_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG031_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG032_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG033_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG034_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG035_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG036_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG037_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG038_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG039_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG040_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG041_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG042_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG043_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG044_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG045_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG046_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG047_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG048_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG049_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG050_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG051_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ENC0_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC0_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC1_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC1_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define EXTTRIG_IN8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define FC1_SCK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 9) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define FLEXSPI0_DATA5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 8) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PIO1_15_PIO1_15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PWM0_B0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 11) /* PIO1_15 */ +#define PWM0_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG023_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG024_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG025_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG026_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG027_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG028_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG029_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG030_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG031_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG032_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG033_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG034_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG035_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG036_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG037_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG038_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG039_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG040_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG041_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG042_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG043_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG044_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG045_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG046_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG047_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG048_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG049_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG050_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG051_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ENC0_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC0_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC1_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC1_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define EXTTRIG_IN7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 9) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define FLEXSPI0_DATA4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 8) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PIO1_16_PIO1_16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PWM0_B2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 11) /* PIO1_16 */ +#define PWM0_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ADC0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC1_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC1_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC1_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC1_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define AOI1_OUT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 12) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG023_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG024_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG025_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG026_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG027_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG028_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG029_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG030_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG031_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG032_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG033_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG034_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG035_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG036_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG037_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG038_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG039_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG040_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG041_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG042_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG043_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG044_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG045_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG046_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG047_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG048_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG049_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG050_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG051_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PIO1_17_PIO1_17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PWM0_B0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 11) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC1_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC1_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC1_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC1_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG023_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG024_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG025_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG026_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG027_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG028_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG029_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG030_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG031_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG032_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG033_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG034_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG035_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG036_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG037_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG038_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG039_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG040_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG041_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG042_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG043_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG044_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG045_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG046_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG047_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG048_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG049_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG050_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG051_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define HSCMP2_OUT_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 13) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PIO1_18_PIO1_18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PWM0_A2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 11) /* PIO1_18 */ +#define RTC_ALARMOUT_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 8) /* PIO1_18 */ +#define RTC_TAMPER3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_CH4B_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC1_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC1_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC1_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC1_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define AOI1_OUT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 13) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DAC1_OUT_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG023_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG024_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG025_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG026_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG027_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG028_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG029_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG030_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG031_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG032_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG033_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG034_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG035_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG036_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG037_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG038_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG039_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG040_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG041_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG042_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG043_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG044_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG045_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG046_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG047_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG048_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG049_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG050_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG051_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define HSCMP1_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PIO1_19_PIO1_19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC1_CH8A_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC1_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC1_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC1_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC1_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define AOI0_OUT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 12) /* PIO1_20 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CT_INP14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG023_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG024_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG025_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG026_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG027_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG028_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG029_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG030_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG031_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG032_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG033_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG034_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG035_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG036_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG037_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG038_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG039_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG040_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG041_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG042_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG043_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG044_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG045_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG046_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG047_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG048_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG049_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG050_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG051_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PIO1_20_PIO1_20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PWM0_A0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 11) /* PIO1_20 */ +#define ADC0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC1_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC1_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC1_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC1_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define AOI0_TRIGOUT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 12) /* PIO1_21 */ +#define AOI1_TRIGOUT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 12) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG023_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG024_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG025_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG026_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG027_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG028_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG029_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG030_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG031_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG032_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG033_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG034_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG035_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG036_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG037_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG038_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG039_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG040_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG041_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG042_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG043_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG044_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG045_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG046_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG047_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG048_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG049_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG050_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG051_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PIO1_21_PIO1_21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PWM1_A0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 11) /* PIO1_21 */ +#define ADC0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define AOI0_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */ +#define AOI1_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 3) /* PIO1_22 */ +#define DAC0_OUT_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG023_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG024_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG025_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG026_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG027_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG028_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG029_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG030_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG031_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG032_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG033_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG034_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG035_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG036_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG037_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG038_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG039_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG040_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG041_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG042_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG043_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG044_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG045_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG046_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG047_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG048_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG049_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG050_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG051_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define HSCMP1_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PIO1_22_PIO1_22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PWM0_B1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 11) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define ADC0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC1_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC1_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC1_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC1_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define AOI0_TRIGOUT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 12) /* PIO1_23 */ +#define AOI1_TRIGOUT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 12) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG023_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG024_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG025_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG026_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG027_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG028_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG029_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG030_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG031_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG032_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG033_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG034_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG035_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG036_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG037_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG038_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG039_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG040_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG041_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG042_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG043_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG044_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG045_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG046_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG047_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG048_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG049_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG050_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG051_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define HSCMP2_IN1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PIO1_23_PIO1_23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PWM1_A1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 11) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 2) /* PIO1_23 */ +#define ADC0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC1_CH8B_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC1_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC1_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC1_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC1_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define AOI0_OUT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 12) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG023_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG024_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG025_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG026_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG027_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG028_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG029_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG030_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG031_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG032_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG033_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG034_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG035_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG036_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG037_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG038_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG039_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG040_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG041_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG042_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG043_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG044_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG045_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG046_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG047_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG048_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG049_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG050_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG051_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PIO1_24_PIO1_24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 2) /* PIO1_24 */ +#define ADC0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC1_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC1_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC1_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC1_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define AOI0_OUT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 13) /* PIO1_25 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG023_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG024_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG025_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG026_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG027_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG028_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG029_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG030_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG031_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG032_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG033_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG034_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG035_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG036_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG037_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG038_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG039_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG040_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG041_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG042_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG043_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG044_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG045_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG046_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG047_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG048_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG049_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG050_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG051_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PIO1_25_PIO1_25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PWM1_A2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 11) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC1_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC1_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC1_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC1_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define AOI1_OUT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 13) /* PIO1_26 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CT_INP3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG023_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG024_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG025_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG026_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG027_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG028_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG029_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG030_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG031_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG032_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG033_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG034_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG035_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG036_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG037_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG038_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG039_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG040_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG041_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG042_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG043_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG044_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG045_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG046_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG047_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG048_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG049_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG050_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG051_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PIO1_26_PIO1_26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PWM0_A1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 11) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC1_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC1_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC1_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC1_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CAN0_TD_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 9) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG023_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG024_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG025_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG026_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG027_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG028_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG029_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG030_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG031_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG032_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG033_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG034_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG035_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG036_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG037_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG038_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG039_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG040_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG041_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG042_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG043_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG044_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG045_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG046_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG047_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG048_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG049_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG050_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG051_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define FLEXSPI0_DATA6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 8) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PIO1_27_PIO1_27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PWM1_B2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 11) /* PIO1_27 */ +#define ADC0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC1_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC1_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC1_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC1_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define AOI0_TRIGOUT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 10) /* PIO1_28 */ +#define AOI1_TRIGOUT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 10) /* PIO1_28 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CT_INP2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG023_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG024_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG025_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG026_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG027_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG028_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG029_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG030_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG031_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG032_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG033_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG034_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG035_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG036_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG037_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG038_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG039_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG040_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG041_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG042_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG043_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG044_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG045_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG046_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG047_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG048_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG049_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG050_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG051_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define HSCMP1_OUT_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 13) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PIO1_28_PIO1_28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PWM1_X3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 11) /* PIO1_28 */ +#define ADC0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC1_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC1_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC1_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC1_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG023_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG024_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG025_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG026_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG027_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG028_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG029_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG030_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG031_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG032_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG033_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG034_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG035_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG036_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG037_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG038_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG039_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG040_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG041_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG042_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG043_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG044_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG045_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG046_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG047_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG048_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG049_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG050_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG051_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ENC0_PHASEA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define ENC0_PHASEB_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define ENC1_PHASEA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define ENC1_PHASEB_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define EXTTRIG_IN9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define FLEXSPI0_DATA7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 8) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PIO1_29_PIO1_29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PWM0_EXTA0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_EXTA1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_EXTA2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_EXTA3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_X2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 11) /* PIO1_29 */ +#define PWM1_EXTA0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_EXTA1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_EXTA2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_EXTA3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define ADC0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC1_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC1_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC1_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC1_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define AOI1_OUT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 12) /* PIO1_30 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG023_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG024_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG025_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG026_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG027_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG028_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG029_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG030_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG031_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG032_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG033_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG034_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG035_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG036_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG037_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG038_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG039_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG040_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG041_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG042_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG043_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG044_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG045_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG046_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG047_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG048_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG049_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG050_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG051_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define HSCMP0_OUT_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 13) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PIO1_30_PIO1_30_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PWM0_X3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 11) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define ADC0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC1_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC1_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC1_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC1_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define AOI0_IN0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG023_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG024_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG025_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG026_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG027_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG028_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG029_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG030_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG031_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG032_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG033_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG034_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG035_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG036_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG037_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG038_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG039_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG040_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG041_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG042_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG043_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG044_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG045_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG046_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG047_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG048_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG049_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG050_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG051_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ENC0_PHASEA_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define ENC0_PHASEB_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define ENC1_PHASEA_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define ENC1_PHASEB_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define EXTTRIG_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PIO1_31_PIO1_31_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PWM0_EXTA0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_EXTA1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_EXTA2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_EXTA3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_B2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 11) /* PIO1_31 */ +#define PWM1_EXTA0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_EXTA1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_EXTA2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_EXTA3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define USB0_VBUS_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define ADC0_CH9A_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 0) /* PIO2_0 */ +#define AOI0_OUT0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 12) /* PIO2_0 */ +#define CTIMER0_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER0_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER0_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER0_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER1_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER1_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER1_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER2_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER2_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER2_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER2_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER3_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER3_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER3_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER3_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER4_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER4_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER4_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER4_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CT_INP4_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 0) /* PIO2_0 */ +#define I3C0_PUR_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 5) /* PIO2_0 */ +#define AOI0_OUT2_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 12) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define I3C0_SDA_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 5) /* PIO2_1 */ +#define OPAMP2_DP0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ + +#endif diff --git a/dts/nxp/lpc/LPC5534JBD64-pinctrl.h b/dts/nxp/lpc/LPC5534JBD64-pinctrl.h new file mode 100644 index 000000000..ac699d582 --- /dev/null +++ b/dts/nxp/lpc/LPC5534JBD64-pinctrl.h @@ -0,0 +1,4538 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5534JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5534JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC5534JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG023_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG024_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG025_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG026_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG027_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG028_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG029_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG030_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG031_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG032_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG033_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG034_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG035_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG036_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG037_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG038_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG039_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG040_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG041_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG042_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG043_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG044_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG045_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG046_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG047_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG048_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG049_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG050_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG051_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMIC0_DATA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 5) /* PIO0_0 */ +#define ENC0_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC0_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define EXTTRIG_IN8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PIO0_0_PIO0_0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PWM0_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_B2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 11) /* PIO0_0 */ +#define PWM1_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SWCLK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 9) /* PIO0_0 */ +#define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_CH2B_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define AOI0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 12) /* PIO0_1 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CT_INP0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG023_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG024_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG025_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG026_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG027_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG028_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG029_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG030_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG031_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG032_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG033_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG034_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG035_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG036_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG037_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG038_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG039_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG040_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG041_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG042_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG043_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG044_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG045_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG046_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG047_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG048_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG049_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG050_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG051_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_CLK0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PIO0_1_PIO0_1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define AOI0_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define AOI1_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CT_INP1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG023_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG024_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG025_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG026_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG027_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG028_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG029_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG030_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG031_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG032_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG033_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG034_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG035_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG036_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG037_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG038_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG039_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG040_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG041_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG042_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG043_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG044_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG045_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG046_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG047_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG048_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG049_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG050_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG051_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ENC0_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC0_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define EXTTRIG_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define FLEXSPI0_DATA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 5) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PIO0_2_PIO0_2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PWM0_A2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 11) /* PIO0_2 */ +#define PWM0_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG023_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG024_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG025_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG026_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG027_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG028_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG029_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG030_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG031_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG032_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG033_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG034_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG035_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG036_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG037_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG038_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG039_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG040_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG041_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG042_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG043_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG044_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG045_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG046_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG047_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG048_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG049_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG050_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG051_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define FLEXSPI0_DATA2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PIO0_3_PIO0_3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PWM1_B0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 11) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define AOI0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CT_INP12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG023_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG024_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG025_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG026_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG027_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG028_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG029_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG030_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG031_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG032_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG033_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG034_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG035_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG036_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG037_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG038_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG039_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG040_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG041_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG042_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG043_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG044_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG045_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG046_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG047_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG048_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG049_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG050_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG051_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ENC0_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC0_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define EXTTRIG_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 9) /* PIO0_4 */ +#define FLEXSPI0_DATA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 5) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PIO0_4_PIO0_4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PWM0_B3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 11) /* PIO0_4 */ +#define PWM0_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG023_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG024_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG025_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG026_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG027_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG028_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG029_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG030_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG031_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG032_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG033_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG034_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG035_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG036_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG037_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG038_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG039_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG040_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG041_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG042_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG043_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG044_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG045_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG046_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG047_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG048_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG049_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG050_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG051_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ENC0_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC0_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define EXTTRIG_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PIO0_5_PIO0_5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PWM0_A0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 11) /* PIO0_5 */ +#define PWM0_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define AOI0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define CT_INP13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG023_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG024_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG025_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG026_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG027_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG028_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG029_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG030_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG031_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG032_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG033_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG034_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG035_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG036_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG037_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG038_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG039_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG040_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG041_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG042_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG043_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG044_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG045_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG046_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG047_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG048_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG049_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG050_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG051_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ENC0_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC0_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define EXTTRIG_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 9) /* PIO0_6 */ +#define FLEXSPI0_DATA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PIO0_6_PIO0_6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PWM0_B0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 11) /* PIO0_6 */ +#define PWM0_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_OUT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 8) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define AOI0_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define AOI1_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG023_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG024_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG025_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG026_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG027_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG028_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG029_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG030_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG031_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG032_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG033_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG034_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG035_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG036_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG037_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG038_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG039_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG040_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG041_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG042_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG043_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG044_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG045_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG046_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG047_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG048_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG049_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG050_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG051_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMIC0_CLK0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 5) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP1_IN0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP2_OUT_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 13) /* PIO0_7 */ +#define MCLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 8) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PIO0_7_PIO0_7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PWM0_B0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 11) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG023_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG024_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG025_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG026_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG027_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG028_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG029_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG030_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG031_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG032_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG033_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG034_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG035_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG036_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG037_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG038_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG039_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG040_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG041_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG042_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG043_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG044_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG045_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG046_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG047_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG048_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG049_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG050_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG051_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define OPAMP0_DP0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PIO0_8_PIO0_8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define AOI0_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define AOI1_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG023_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG024_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG025_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG026_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG027_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG028_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG029_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG030_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG031_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG032_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG033_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG034_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG035_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG036_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG037_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG038_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG039_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG040_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG041_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG042_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG043_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG044_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG045_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG046_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG047_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG048_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG049_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG050_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG051_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define I3C0_SCL_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 7) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PIO0_9_PIO0_9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PWM1_A2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 11) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SWDIO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 9) /* PIO0_9 */ +#define ADC0_CH1A_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CT_INP10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG023_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG024_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG025_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG026_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG027_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG028_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG029_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG030_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG031_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG032_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG033_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG034_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG035_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG036_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG037_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG038_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG039_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG040_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG041_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG042_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG043_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG044_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG045_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG046_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG047_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG048_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG049_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG050_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG051_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PIO0_10_PIO0_10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_CH2A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define AOI1_OUT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 12) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG023_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG024_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG025_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG026_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG027_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG028_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG029_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG030_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG031_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG032_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG033_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG034_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG035_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG036_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG037_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG038_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG039_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG040_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG041_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG042_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG043_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG044_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG045_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG046_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG047_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG048_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG049_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG050_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG051_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PIO0_11_PIO0_11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define AOI0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CT_INP0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG023_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG024_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG025_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG026_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG027_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG028_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG029_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG030_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG031_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG032_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG033_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG034_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG035_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG036_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG037_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG038_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG039_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG040_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG041_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG042_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG043_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG044_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG045_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG046_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG047_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG048_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG049_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG050_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG051_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ENC0_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC0_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define EXTTRIG_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PIO0_13_PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PWM0_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define AOI0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CT_INP1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG023_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG024_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG025_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG026_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG027_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG028_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG029_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG030_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG031_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG032_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG033_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG034_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG035_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG036_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG037_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG038_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG039_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG040_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG041_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG042_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG043_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG044_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG045_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG046_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG047_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG048_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG049_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG050_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG051_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ENC0_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC0_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define EXTTRIG_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PIO0_14_PIO0_14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PWM0_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH3A_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CT_INP16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG023_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG024_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG025_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG026_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG027_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG028_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG029_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG030_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG031_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG032_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG033_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG034_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG035_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG036_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG037_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG038_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG039_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG040_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG041_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG042_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG043_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG044_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG045_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG046_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG047_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG048_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG049_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG050_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG051_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PIO0_15_PIO0_15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH3B_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define AOI0_OUT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 12) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CT_INP4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG023_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG024_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG025_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG026_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG027_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG028_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG029_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG030_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG031_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG032_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG033_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG034_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG035_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG036_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG037_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG038_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG039_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG040_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG041_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG042_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG043_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG044_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG045_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG046_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG047_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG048_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG049_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG050_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG051_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PIO0_16_PIO0_16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define AOI0_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define AOI1_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG023_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG024_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG025_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG026_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG027_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG028_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG029_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG030_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG031_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG032_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG033_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG034_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG035_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG036_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG037_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG038_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG039_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG040_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG041_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG042_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG043_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG044_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG045_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG046_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG047_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG048_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG049_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG050_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG051_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 1) /* PIO0_17 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 8) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define HSCMP1_OUT_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 13) /* PIO0_17 */ +#define HSCMP2_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PIO0_17_PIO0_17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define AOI0_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define AOI1_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG023_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG024_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG025_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG026_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG027_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG028_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG029_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG030_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG031_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG032_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG033_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG034_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG035_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG036_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG037_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG038_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG039_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG040_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG041_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG042_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG043_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG044_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG045_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG046_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG047_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG048_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG049_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG050_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG051_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PIO0_18_PIO0_18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PWM1_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 11) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SWO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 8) /* PIO0_18 */ +#define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define AOI0_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define AOI1_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG023_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG024_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG025_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG026_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG027_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG028_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG029_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG030_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG031_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG032_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG033_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG034_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG035_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG036_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG037_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG038_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG039_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG040_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG041_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG042_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG043_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG044_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG045_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG046_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG047_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG048_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG049_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG050_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG051_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ENC0_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC0_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define EXTTRIG_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define FLEXSPI0_SCLK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 5) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PIO0_19_PIO0_19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PWM0_B1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 11) /* PIO0_19 */ +#define PWM0_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CT_INP15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG023_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG024_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG025_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG026_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG027_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG028_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG029_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG030_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG031_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG032_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG033_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG034_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG035_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG036_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG037_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG038_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG039_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG040_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG041_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG042_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG043_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG044_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG045_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG046_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG047_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG048_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG049_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG050_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG051_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PIO0_20_PIO0_20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PWM1_X2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 13) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define AOI0_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define AOI1_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG023_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG024_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG025_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG026_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG027_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG028_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG029_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG030_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG031_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG032_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG033_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG034_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG035_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG036_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG037_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG038_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG039_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG040_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG041_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG042_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG043_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG044_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG045_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG046_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG047_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG048_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG049_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG050_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG051_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ENC0_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC0_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define EXTTRIG_IN7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_CTS_SDA_SSEL0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define FLEXSPI0_SS0_N_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PIO0_21_PIO0_21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PWM0_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_B1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 11) /* PIO0_21 */ +#define PWM1_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_OUT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CT_INP15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG023_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG024_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG025_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG026_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG027_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG028_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG029_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG030_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG031_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG032_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG033_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG034_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG035_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG036_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG037_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG038_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG039_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG040_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG041_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG042_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG043_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG044_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG045_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG046_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG047_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG048_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG049_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG050_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG051_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ENC0_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC0_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC1_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC1_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define EXTTRIG_IN5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define FC7_RTS_SCL_SSEL1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define FLEXSPI0_SCLK_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 5) /* PIO0_22 */ +#define FLEXSPI0_SS1_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 6) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PIO0_22_PIO0_22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PWM0_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_X0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 11) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CT_INP8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG023_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG025_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG026_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG027_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG028_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG029_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG030_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG031_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG032_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG033_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG034_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG035_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG036_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG037_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG038_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG039_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG040_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG041_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG042_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG043_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG044_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG045_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG046_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG047_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG048_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG049_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG050_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG051_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define HSCMP0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define I3C0_SDA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 5) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PIO0_24_PIO0_24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PWM0_A1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 11) /* PIO0_24 */ +#define PWM0_X0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 13) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SWD_TRACEDATA0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 6) /* PIO0_24 */ +#define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CT_INP9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG023_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG024_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG026_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG027_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG028_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG029_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG030_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG031_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG032_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG033_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG034_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG035_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG036_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG037_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG038_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG039_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG040_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG041_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG042_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG043_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG044_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG045_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG046_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG047_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG048_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG049_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG050_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG051_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ENC0_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC0_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC1_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC1_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define EXTTRIG_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define FLEXSPI0_DQS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define HSCMP0_OUT_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 7) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PIO0_25_PIO0_25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PWM0_A0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 11) /* PIO0_25 */ +#define PWM0_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CT_INP14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG023_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG024_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG025_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG027_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG028_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG029_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG030_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG031_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG032_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG033_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG034_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG035_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG036_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG037_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG038_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG039_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG040_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG041_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG042_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG043_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG044_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG045_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG046_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG047_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG048_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG049_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG050_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG051_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PIO0_26_PIO0_26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PWM0_B1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 11) /* PIO0_26 */ +#define RTC_TAMPER2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define ADC0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG023_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG024_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG025_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG026_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG028_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG029_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG030_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG031_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG032_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG033_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG034_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG035_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG036_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG037_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG038_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG039_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG040_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG041_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG042_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG043_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG044_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG045_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG046_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG047_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG048_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG049_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG050_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG051_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define OPAMP1_DP0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PIO0_27_PIO0_27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define AOI0_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG023_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG024_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG025_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG026_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG027_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG028_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG030_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG031_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG032_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG033_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG034_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG035_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG036_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG037_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG038_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG039_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG040_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG041_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG042_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG043_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG044_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG045_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG046_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG047_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG048_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG049_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG050_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG051_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ENC0_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC0_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define EXTTRIG_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 6) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PIO0_29_PIO0_29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PWM0_A1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 11) /* PIO0_29 */ +#define PWM0_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define AOI1_OUT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 12) /* PIO0_30 */ +#define CAN0_TD_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 6) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG023_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG024_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG025_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG026_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG027_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG028_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG029_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG031_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG032_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG033_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG034_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG035_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG036_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG037_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG038_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG039_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG040_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG041_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG042_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG043_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG044_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG045_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG046_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG047_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG048_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG049_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG050_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG051_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 9) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PIO0_30_PIO0_30_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PWM1_A1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 11) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH8A_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define AOI0_OUT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 12) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG023_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG024_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG025_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG026_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG027_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG028_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG029_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG030_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG032_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG033_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG034_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG035_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG036_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG037_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG038_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG039_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG040_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG041_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG042_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG043_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG044_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG045_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG046_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG047_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG048_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG049_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG050_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG051_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define I3C0_SCL_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 15) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PIO0_31_PIO0_31_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_CH0B_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define AOI1_OUT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 12) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CT_INP2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG023_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG024_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG025_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG026_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG027_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG028_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG029_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG030_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG031_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG032_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG033_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG034_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG035_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG036_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG037_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG038_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG039_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG040_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG041_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG042_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG043_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG044_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG045_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG046_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG047_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG048_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG049_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG050_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG051_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PIO1_0_PIO1_0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CT_INP3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG023_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG024_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG025_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG026_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG027_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG028_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG029_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG030_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG031_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG032_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG033_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG034_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG035_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG036_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG037_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG038_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG039_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG040_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG041_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG042_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG043_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG044_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG045_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG046_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG047_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG048_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG049_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG050_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG051_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PIO1_1_PIO1_1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PWM0_B2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 11) /* PIO1_1 */ +#define RTC_ALARMOUT_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 10) /* PIO1_1 */ +#define RTC_TAMPER0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define TRACECLK_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define AOI0_OUT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 12) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG023_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG024_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG025_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG026_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG027_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG028_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG029_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG030_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG031_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG032_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG033_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG034_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG035_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG036_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG037_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG038_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG039_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG040_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG041_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG042_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG043_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG044_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG045_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG046_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG047_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG048_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG049_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG050_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG051_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PIO1_2_PIO1_2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PWM0_B0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 11) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG023_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG024_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG025_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG026_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG027_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG028_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG029_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG030_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG031_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG032_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG033_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG034_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG035_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG036_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG037_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG038_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG039_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG040_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG041_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG042_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG043_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG044_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG045_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG046_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG047_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG048_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG049_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG050_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG051_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PIO1_3_PIO1_3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PWM0_A3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 11) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CT_INP5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG023_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG024_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG025_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG026_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG027_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG028_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG029_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG030_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG031_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG032_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG033_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG034_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG035_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG036_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG037_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG038_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG039_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG040_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG041_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG042_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG043_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG044_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG045_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG046_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG047_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG048_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG049_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG050_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG051_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ENC0_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC0_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define EXTTRIG_IN8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define FC6_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 10) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define HS_SPI_SSEL0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PIO1_11_PIO1_11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PWM0_A0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 11) /* PIO1_11 */ +#define PWM0_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ACMP0VREF_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define AOI0_OUT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 12) /* PIO1_13 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CT_INP6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG023_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG024_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG025_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG026_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG027_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG028_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG029_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG030_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG031_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG032_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG033_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG034_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG035_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG036_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG037_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG038_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG039_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG040_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG041_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG042_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG043_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG044_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG045_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG046_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG047_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG048_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG049_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG050_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG051_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PIO1_13_PIO1_13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PWM1_X1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 11) /* PIO1_13 */ +#define SCT0_OUT8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 8) /* PIO1_13 */ +#define ADC0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CT_INP7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG023_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG024_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG025_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG026_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG027_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG028_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG029_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG030_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG031_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG032_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG033_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG034_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG035_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG036_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG037_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG038_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG039_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG040_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG041_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG042_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG043_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG044_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG045_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG046_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG047_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG048_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG049_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG050_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG051_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ENC0_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC0_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC1_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC1_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define EXTTRIG_IN8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define FC1_SCK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 9) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define FLEXSPI0_DATA5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 8) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PIO1_15_PIO1_15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PWM0_B0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 11) /* PIO1_15 */ +#define PWM0_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG023_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG024_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG025_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG026_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG027_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG028_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG029_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG030_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG031_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG032_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG033_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG034_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG035_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG036_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG037_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG038_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG039_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG040_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG041_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG042_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG043_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG044_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG045_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG046_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG047_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG048_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG049_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG050_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG051_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ENC0_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC0_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC1_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC1_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define EXTTRIG_IN7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 9) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define FLEXSPI0_DATA4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 8) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PIO1_16_PIO1_16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PWM0_B2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 11) /* PIO1_16 */ +#define PWM0_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ADC0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define AOI0_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */ +#define AOI1_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 3) /* PIO1_22 */ +#define DAC0_OUT_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG023_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG024_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG025_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG026_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG027_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG028_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG029_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG030_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG031_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG032_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG033_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG034_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG035_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG036_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG037_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG038_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG039_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG040_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG041_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG042_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG043_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG044_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG045_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG046_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG047_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG048_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG049_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG050_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG051_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define HSCMP1_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PIO1_22_PIO1_22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PWM0_B1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 11) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define AOI0_OUT2_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 12) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define I3C0_SDA_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 5) /* PIO2_1 */ +#define OPAMP2_DP0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ + +#endif diff --git a/dts/nxp/lpc/LPC5534JHI48-pinctrl.h b/dts/nxp/lpc/LPC5534JHI48-pinctrl.h new file mode 100644 index 000000000..9b3a915e2 --- /dev/null +++ b/dts/nxp/lpc/LPC5534JHI48-pinctrl.h @@ -0,0 +1,3714 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5534JHI48/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5534JHI48_ +#define _ZEPHYR_DTS_BINDING_LPC5534JHI48_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG023_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG024_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG025_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG026_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG027_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG028_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG029_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG030_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG031_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG032_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG033_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG034_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG035_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG036_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG037_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG038_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG039_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG040_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG041_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG042_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG043_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG044_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG045_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG046_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG047_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG048_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG049_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG050_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG051_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMIC0_DATA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 5) /* PIO0_0 */ +#define ENC0_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC0_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define EXTTRIG_IN8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PIO0_0_PIO0_0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PWM0_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_B2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 11) /* PIO0_0 */ +#define PWM1_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SWCLK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 9) /* PIO0_0 */ +#define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_CH2B_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define AOI0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 12) /* PIO0_1 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CT_INP0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG023_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG024_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG025_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG026_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG027_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG028_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG029_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG030_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG031_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG032_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG033_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG034_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG035_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG036_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG037_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG038_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG039_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG040_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG041_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG042_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG043_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG044_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG045_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG046_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG047_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG048_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG049_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG050_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG051_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_CLK0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PIO0_1_PIO0_1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define AOI0_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define AOI1_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CT_INP1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG023_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG024_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG025_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG026_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG027_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG028_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG029_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG030_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG031_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG032_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG033_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG034_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG035_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG036_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG037_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG038_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG039_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG040_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG041_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG042_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG043_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG044_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG045_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG046_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG047_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG048_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG049_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG050_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG051_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ENC0_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC0_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define EXTTRIG_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define FLEXSPI0_DATA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 5) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PIO0_2_PIO0_2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PWM0_A2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 11) /* PIO0_2 */ +#define PWM0_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG023_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG024_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG025_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG026_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG027_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG028_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG029_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG030_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG031_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG032_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG033_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG034_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG035_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG036_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG037_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG038_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG039_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG040_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG041_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG042_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG043_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG044_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG045_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG046_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG047_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG048_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG049_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG050_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG051_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define FLEXSPI0_DATA2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PIO0_3_PIO0_3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PWM1_B0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 11) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define AOI0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CT_INP12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG023_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG024_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG025_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG026_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG027_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG028_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG029_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG030_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG031_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG032_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG033_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG034_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG035_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG036_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG037_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG038_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG039_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG040_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG041_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG042_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG043_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG044_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG045_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG046_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG047_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG048_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG049_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG050_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG051_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ENC0_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC0_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define EXTTRIG_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 9) /* PIO0_4 */ +#define FLEXSPI0_DATA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 5) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PIO0_4_PIO0_4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PWM0_B3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 11) /* PIO0_4 */ +#define PWM0_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG023_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG024_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG025_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG026_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG027_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG028_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG029_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG030_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG031_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG032_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG033_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG034_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG035_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG036_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG037_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG038_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG039_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG040_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG041_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG042_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG043_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG044_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG045_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG046_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG047_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG048_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG049_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG050_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG051_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ENC0_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC0_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define EXTTRIG_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PIO0_5_PIO0_5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PWM0_A0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 11) /* PIO0_5 */ +#define PWM0_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define AOI0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define CT_INP13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG023_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG024_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG025_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG026_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG027_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG028_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG029_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG030_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG031_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG032_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG033_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG034_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG035_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG036_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG037_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG038_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG039_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG040_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG041_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG042_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG043_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG044_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG045_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG046_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG047_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG048_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG049_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG050_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG051_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ENC0_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC0_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define EXTTRIG_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 9) /* PIO0_6 */ +#define FLEXSPI0_DATA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PIO0_6_PIO0_6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PWM0_B0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 11) /* PIO0_6 */ +#define PWM0_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_OUT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 8) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define AOI0_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define AOI1_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG023_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG024_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG025_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG026_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG027_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG028_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG029_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG030_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG031_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG032_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG033_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG034_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG035_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG036_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG037_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG038_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG039_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG040_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG041_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG042_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG043_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG044_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG045_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG046_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG047_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG048_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG049_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG050_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG051_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMIC0_CLK0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 5) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP1_IN0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP2_OUT_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 13) /* PIO0_7 */ +#define MCLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 8) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PIO0_7_PIO0_7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PWM0_B0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 11) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG023_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG024_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG025_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG026_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG027_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG028_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG029_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG030_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG031_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG032_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG033_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG034_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG035_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG036_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG037_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG038_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG039_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG040_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG041_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG042_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG043_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG044_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG045_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG046_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG047_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG048_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG049_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG050_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG051_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define OPAMP0_DP0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PIO0_8_PIO0_8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define AOI0_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define AOI1_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG023_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG024_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG025_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG026_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG027_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG028_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG029_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG030_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG031_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG032_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG033_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG034_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG035_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG036_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG037_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG038_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG039_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG040_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG041_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG042_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG043_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG044_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG045_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG046_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG047_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG048_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG049_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG050_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG051_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define I3C0_SCL_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 7) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PIO0_9_PIO0_9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PWM1_A2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 11) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SWDIO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 9) /* PIO0_9 */ +#define ADC0_CH1A_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CT_INP10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG023_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG024_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG025_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG026_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG027_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG028_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG029_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG030_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG031_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG032_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG033_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG034_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG035_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG036_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG037_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG038_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG039_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG040_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG041_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG042_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG043_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG044_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG045_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG046_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG047_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG048_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG049_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG050_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG051_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PIO0_10_PIO0_10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_CH2A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define AOI1_OUT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 12) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG023_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG024_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG025_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG026_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG027_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG028_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG029_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG030_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG031_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG032_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG033_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG034_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG035_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG036_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG037_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG038_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG039_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG040_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG041_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG042_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG043_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG044_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG045_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG046_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG047_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG048_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG049_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG050_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG051_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PIO0_11_PIO0_11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define AOI0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CT_INP0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG023_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG024_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG025_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG026_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG027_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG028_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG029_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG030_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG031_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG032_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG033_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG034_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG035_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG036_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG037_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG038_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG039_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG040_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG041_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG042_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG043_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG044_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG045_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG046_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG047_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG048_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG049_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG050_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG051_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ENC0_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC0_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define EXTTRIG_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PIO0_13_PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PWM0_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define AOI0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CT_INP1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG023_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG024_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG025_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG026_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG027_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG028_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG029_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG030_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG031_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG032_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG033_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG034_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG035_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG036_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG037_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG038_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG039_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG040_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG041_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG042_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG043_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG044_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG045_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG046_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG047_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG048_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG049_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG050_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG051_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ENC0_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC0_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define EXTTRIG_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PIO0_14_PIO0_14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PWM0_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH3A_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CT_INP16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG023_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG024_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG025_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG026_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG027_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG028_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG029_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG030_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG031_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG032_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG033_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG034_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG035_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG036_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG037_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG038_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG039_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG040_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG041_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG042_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG043_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG044_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG045_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG046_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG047_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG048_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG049_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG050_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG051_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PIO0_15_PIO0_15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH3B_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define AOI0_OUT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 12) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CT_INP4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG023_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG024_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG025_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG026_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG027_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG028_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG029_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG030_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG031_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG032_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG033_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG034_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG035_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG036_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG037_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG038_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG039_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG040_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG041_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG042_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG043_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG044_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG045_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG046_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG047_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG048_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG049_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG050_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG051_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PIO0_16_PIO0_16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define AOI0_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define AOI1_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG023_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG024_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG025_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG026_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG027_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG028_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG029_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG030_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG031_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG032_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG033_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG034_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG035_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG036_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG037_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG038_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG039_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG040_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG041_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG042_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG043_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG044_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG045_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG046_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG047_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG048_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG049_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG050_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG051_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 1) /* PIO0_17 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 8) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define HSCMP1_OUT_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 13) /* PIO0_17 */ +#define HSCMP2_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PIO0_17_PIO0_17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define AOI0_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define AOI1_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG023_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG024_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG025_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG026_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG027_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG028_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG029_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG030_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG031_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG032_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG033_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG034_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG035_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG036_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG037_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG038_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG039_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG040_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG041_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG042_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG043_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG044_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG045_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG046_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG047_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG048_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG049_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG050_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG051_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PIO0_18_PIO0_18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PWM1_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 11) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SWO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 8) /* PIO0_18 */ +#define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define AOI0_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define AOI1_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG023_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG024_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG025_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG026_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG027_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG028_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG029_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG030_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG031_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG032_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG033_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG034_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG035_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG036_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG037_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG038_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG039_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG040_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG041_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG042_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG043_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG044_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG045_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG046_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG047_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG048_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG049_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG050_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG051_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ENC0_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC0_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define EXTTRIG_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define FLEXSPI0_SCLK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 5) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PIO0_19_PIO0_19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PWM0_B1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 11) /* PIO0_19 */ +#define PWM0_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CT_INP15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG023_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG024_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG025_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG026_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG027_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG028_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG029_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG030_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG031_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG032_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG033_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG034_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG035_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG036_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG037_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG038_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG039_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG040_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG041_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG042_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG043_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG044_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG045_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG046_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG047_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG048_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG049_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG050_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG051_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PIO0_20_PIO0_20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PWM1_X2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 13) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define AOI0_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define AOI1_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG023_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG024_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG025_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG026_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG027_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG028_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG029_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG030_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG031_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG032_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG033_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG034_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG035_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG036_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG037_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG038_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG039_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG040_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG041_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG042_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG043_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG044_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG045_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG046_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG047_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG048_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG049_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG050_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG051_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ENC0_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC0_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define EXTTRIG_IN7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_CTS_SDA_SSEL0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define FLEXSPI0_SS0_N_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PIO0_21_PIO0_21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PWM0_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_B1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 11) /* PIO0_21 */ +#define PWM1_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_OUT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CT_INP8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG023_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG025_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG026_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG027_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG028_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG029_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG030_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG031_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG032_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG033_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG034_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG035_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG036_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG037_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG038_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG039_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG040_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG041_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG042_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG043_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG044_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG045_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG046_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG047_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG048_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG049_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG050_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG051_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define HSCMP0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define I3C0_SDA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 5) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PIO0_24_PIO0_24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PWM0_A1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 11) /* PIO0_24 */ +#define PWM0_X0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 13) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SWD_TRACEDATA0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 6) /* PIO0_24 */ +#define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CT_INP14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG023_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG024_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG025_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG027_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG028_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG029_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG030_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG031_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG032_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG033_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG034_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG035_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG036_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG037_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG038_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG039_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG040_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG041_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG042_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG043_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG044_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG045_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG046_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG047_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG048_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG049_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG050_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG051_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PIO0_26_PIO0_26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PWM0_B1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 11) /* PIO0_26 */ +#define RTC_TAMPER2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define ADC0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG023_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG024_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG025_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG026_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG028_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG029_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG030_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG031_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG032_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG033_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG034_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG035_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG036_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG037_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG038_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG039_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG040_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG041_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG042_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG043_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG044_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG045_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG046_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG047_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG048_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG049_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG050_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG051_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define OPAMP1_DP0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PIO0_27_PIO0_27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define AOI0_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG023_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG024_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG025_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG026_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG027_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG028_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG030_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG031_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG032_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG033_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG034_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG035_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG036_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG037_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG038_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG039_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG040_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG041_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG042_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG043_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG044_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG045_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG046_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG047_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG048_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG049_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG050_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG051_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ENC0_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC0_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define EXTTRIG_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 6) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PIO0_29_PIO0_29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PWM0_A1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 11) /* PIO0_29 */ +#define PWM0_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define AOI1_OUT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 12) /* PIO0_30 */ +#define CAN0_TD_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 6) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG023_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG024_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG025_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG026_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG027_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG028_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG029_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG031_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG032_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG033_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG034_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG035_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG036_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG037_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG038_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG039_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG040_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG041_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG042_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG043_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG044_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG045_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG046_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG047_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG048_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG049_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG050_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG051_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 9) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PIO0_30_PIO0_30_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PWM1_A1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 11) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_CH0B_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define AOI1_OUT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 12) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CT_INP2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG023_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG024_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG025_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG026_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG027_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG028_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG029_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG030_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG031_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG032_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG033_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG034_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG035_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG036_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG037_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG038_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG039_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG040_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG041_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG042_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG043_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG044_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG045_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG046_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG047_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG048_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG049_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG050_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG051_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PIO1_0_PIO1_0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CT_INP3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG023_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG024_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG025_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG026_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG027_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG028_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG029_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG030_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG031_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG032_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG033_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG034_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG035_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG036_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG037_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG038_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG039_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG040_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG041_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG042_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG043_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG044_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG045_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG046_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG047_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG048_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG049_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG050_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG051_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PIO1_1_PIO1_1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PWM0_B2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 11) /* PIO1_1 */ +#define RTC_ALARMOUT_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 10) /* PIO1_1 */ +#define RTC_TAMPER0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define TRACECLK_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define AOI0_OUT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 12) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG023_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG024_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG025_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG026_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG027_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG028_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG029_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG030_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG031_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG032_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG033_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG034_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG035_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG036_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG037_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG038_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG039_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG040_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG041_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG042_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG043_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG044_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG045_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG046_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG047_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG048_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG049_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG050_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG051_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PIO1_2_PIO1_2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PWM0_B0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 11) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG023_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG024_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG025_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG026_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG027_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG028_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG029_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG030_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG031_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG032_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG033_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG034_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG035_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG036_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG037_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG038_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG039_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG040_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG041_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG042_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG043_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG044_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG045_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG046_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG047_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG048_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG049_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG050_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG051_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PIO1_3_PIO1_3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PWM0_A3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 11) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CT_INP5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG023_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG024_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG025_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG026_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG027_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG028_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG029_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG030_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG031_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG032_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG033_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG034_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG035_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG036_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG037_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG038_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG039_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG040_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG041_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG042_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG043_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG044_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG045_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG046_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG047_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG048_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG049_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG050_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG051_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ENC0_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC0_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define EXTTRIG_IN8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define FC6_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 10) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define HS_SPI_SSEL0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PIO1_11_PIO1_11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PWM0_A0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 11) /* PIO1_11 */ +#define PWM0_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define AOI0_OUT2_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 12) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define I3C0_SDA_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 5) /* PIO2_1 */ +#define OPAMP2_DP0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ + +#endif diff --git a/dts/nxp/lpc/LPC5536JBD100-pinctrl.h b/dts/nxp/lpc/LPC5536JBD100-pinctrl.h new file mode 100644 index 000000000..d37828a75 --- /dev/null +++ b/dts/nxp/lpc/LPC5536JBD100-pinctrl.h @@ -0,0 +1,7141 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5536JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5536JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC5536JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG023_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG024_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG025_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG026_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG027_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG028_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG029_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG030_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG031_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG032_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG033_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG034_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG035_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG036_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG037_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG038_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG039_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG040_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG041_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG042_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG043_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG044_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG045_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG046_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG047_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG048_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG049_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG050_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG051_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMIC0_DATA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 5) /* PIO0_0 */ +#define ENC0_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC0_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define EXTTRIG_IN8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PIO0_0_PIO0_0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PWM0_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_B2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 11) /* PIO0_0 */ +#define PWM1_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SWCLK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 9) /* PIO0_0 */ +#define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_CH2B_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define AOI0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 12) /* PIO0_1 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CT_INP0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG023_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG024_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG025_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG026_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG027_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG028_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG029_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG030_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG031_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG032_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG033_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG034_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG035_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG036_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG037_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG038_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG039_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG040_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG041_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG042_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG043_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG044_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG045_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG046_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG047_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG048_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG049_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG050_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG051_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_CLK0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PIO0_1_PIO0_1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define AOI0_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define AOI1_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CT_INP1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG023_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG024_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG025_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG026_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG027_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG028_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG029_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG030_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG031_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG032_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG033_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG034_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG035_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG036_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG037_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG038_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG039_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG040_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG041_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG042_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG043_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG044_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG045_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG046_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG047_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG048_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG049_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG050_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG051_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ENC0_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC0_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define EXTTRIG_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define FLEXSPI0_DATA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 5) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PIO0_2_PIO0_2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PWM0_A2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 11) /* PIO0_2 */ +#define PWM0_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG023_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG024_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG025_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG026_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG027_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG028_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG029_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG030_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG031_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG032_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG033_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG034_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG035_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG036_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG037_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG038_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG039_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG040_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG041_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG042_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG043_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG044_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG045_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG046_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG047_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG048_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG049_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG050_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG051_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define FLEXSPI0_DATA2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PIO0_3_PIO0_3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PWM1_B0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 11) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define AOI0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CT_INP12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG023_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG024_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG025_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG026_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG027_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG028_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG029_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG030_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG031_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG032_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG033_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG034_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG035_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG036_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG037_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG038_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG039_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG040_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG041_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG042_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG043_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG044_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG045_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG046_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG047_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG048_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG049_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG050_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG051_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ENC0_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC0_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define EXTTRIG_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 9) /* PIO0_4 */ +#define FLEXSPI0_DATA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 5) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PIO0_4_PIO0_4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PWM0_B3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 11) /* PIO0_4 */ +#define PWM0_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG023_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG024_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG025_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG026_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG027_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG028_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG029_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG030_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG031_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG032_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG033_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG034_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG035_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG036_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG037_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG038_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG039_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG040_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG041_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG042_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG043_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG044_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG045_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG046_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG047_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG048_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG049_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG050_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG051_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ENC0_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC0_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define EXTTRIG_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PIO0_5_PIO0_5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PWM0_A0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 11) /* PIO0_5 */ +#define PWM0_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define AOI0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define CT_INP13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG023_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG024_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG025_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG026_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG027_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG028_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG029_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG030_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG031_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG032_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG033_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG034_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG035_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG036_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG037_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG038_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG039_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG040_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG041_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG042_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG043_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG044_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG045_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG046_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG047_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG048_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG049_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG050_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG051_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ENC0_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC0_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define EXTTRIG_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 9) /* PIO0_6 */ +#define FLEXSPI0_DATA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PIO0_6_PIO0_6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PWM0_B0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 11) /* PIO0_6 */ +#define PWM0_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_OUT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 8) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define AOI0_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define AOI1_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG023_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG024_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG025_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG026_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG027_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG028_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG029_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG030_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG031_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG032_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG033_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG034_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG035_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG036_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG037_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG038_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG039_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG040_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG041_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG042_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG043_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG044_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG045_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG046_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG047_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG048_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG049_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG050_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG051_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMIC0_CLK0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 5) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP1_IN0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP2_OUT_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 13) /* PIO0_7 */ +#define MCLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 8) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PIO0_7_PIO0_7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PWM0_B0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 11) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG023_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG024_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG025_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG026_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG027_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG028_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG029_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG030_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG031_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG032_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG033_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG034_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG035_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG036_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG037_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG038_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG039_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG040_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG041_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG042_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG043_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG044_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG045_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG046_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG047_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG048_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG049_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG050_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG051_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define OPAMP0_DP0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PIO0_8_PIO0_8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define AOI0_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define AOI1_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG023_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG024_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG025_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG026_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG027_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG028_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG029_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG030_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG031_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG032_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG033_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG034_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG035_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG036_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG037_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG038_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG039_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG040_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG041_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG042_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG043_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG044_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG045_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG046_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG047_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG048_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG049_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG050_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG051_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define I3C0_SCL_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 7) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PIO0_9_PIO0_9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PWM1_A2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 11) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SWDIO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 9) /* PIO0_9 */ +#define ADC0_CH1A_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CT_INP10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG023_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG024_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG025_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG026_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG027_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG028_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG029_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG030_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG031_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG032_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG033_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG034_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG035_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG036_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG037_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG038_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG039_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG040_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG041_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG042_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG043_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG044_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG045_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG046_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG047_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG048_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG049_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG050_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG051_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PIO0_10_PIO0_10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_CH2A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define AOI1_OUT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 12) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG023_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG024_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG025_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG026_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG027_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG028_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG029_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG030_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG031_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG032_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG033_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG034_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG035_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG036_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG037_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG038_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG039_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG040_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG041_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG042_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG043_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG044_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG045_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG046_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG047_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG048_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG049_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG050_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG051_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PIO0_11_PIO0_11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define ADC0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC1_CH3A_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC1_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC1_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC1_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define ADC1_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define AOI1_OUT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 12) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG023_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG024_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG025_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG026_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG027_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG028_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG029_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG030_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG031_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG032_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG033_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG034_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG035_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG036_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG037_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG038_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG039_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG040_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG041_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG042_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG043_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG044_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG045_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG046_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG047_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG048_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG049_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG050_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG051_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 7) /* PIO0_12 */ +#define FREQME_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define PIO0_12_PIO0_12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */ +#define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define AOI0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CT_INP0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG023_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG024_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG025_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG026_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG027_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG028_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG029_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG030_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG031_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG032_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG033_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG034_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG035_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG036_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG037_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG038_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG039_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG040_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG041_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG042_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG043_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG044_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG045_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG046_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG047_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG048_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG049_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG050_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG051_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ENC0_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC0_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define EXTTRIG_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PIO0_13_PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PWM0_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define AOI0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CT_INP1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG023_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG024_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG025_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG026_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG027_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG028_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG029_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG030_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG031_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG032_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG033_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG034_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG035_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG036_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG037_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG038_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG039_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG040_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG041_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG042_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG043_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG044_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG045_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG046_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG047_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG048_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG049_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG050_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG051_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ENC0_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC0_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define EXTTRIG_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PIO0_14_PIO0_14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PWM0_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH3A_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CT_INP16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG023_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG024_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG025_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG026_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG027_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG028_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG029_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG030_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG031_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG032_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG033_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG034_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG035_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG036_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG037_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG038_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG039_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG040_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG041_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG042_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG043_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG044_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG045_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG046_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG047_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG048_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG049_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG050_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG051_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PIO0_15_PIO0_15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH3B_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define AOI0_OUT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 12) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CT_INP4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG023_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG024_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG025_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG026_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG027_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG028_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG029_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG030_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG031_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG032_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG033_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG034_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG035_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG036_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG037_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG038_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG039_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG040_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG041_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG042_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG043_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG044_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG045_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG046_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG047_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG048_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG049_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG050_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG051_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PIO0_16_PIO0_16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define AOI0_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define AOI1_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG023_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG024_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG025_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG026_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG027_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG028_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG029_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG030_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG031_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG032_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG033_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG034_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG035_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG036_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG037_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG038_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG039_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG040_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG041_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG042_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG043_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG044_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG045_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG046_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG047_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG048_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG049_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG050_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG051_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 1) /* PIO0_17 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 8) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define HSCMP1_OUT_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 13) /* PIO0_17 */ +#define HSCMP2_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PIO0_17_PIO0_17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define AOI0_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define AOI1_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG023_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG024_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG025_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG026_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG027_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG028_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG029_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG030_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG031_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG032_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG033_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG034_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG035_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG036_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG037_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG038_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG039_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG040_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG041_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG042_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG043_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG044_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG045_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG046_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG047_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG048_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG049_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG050_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG051_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PIO0_18_PIO0_18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PWM1_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 11) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SWO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 8) /* PIO0_18 */ +#define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define AOI0_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define AOI1_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG023_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG024_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG025_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG026_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG027_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG028_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG029_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG030_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG031_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG032_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG033_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG034_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG035_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG036_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG037_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG038_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG039_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG040_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG041_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG042_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG043_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG044_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG045_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG046_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG047_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG048_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG049_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG050_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG051_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ENC0_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC0_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define EXTTRIG_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define FLEXSPI0_SCLK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 5) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PIO0_19_PIO0_19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PWM0_B1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 11) /* PIO0_19 */ +#define PWM0_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CT_INP15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG023_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG024_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG025_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG026_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG027_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG028_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG029_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG030_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG031_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG032_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG033_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG034_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG035_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG036_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG037_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG038_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG039_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG040_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG041_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG042_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG043_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG044_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG045_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG046_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG047_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG048_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG049_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG050_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG051_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PIO0_20_PIO0_20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PWM1_X2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 13) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define AOI0_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define AOI1_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG023_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG024_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG025_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG026_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG027_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG028_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG029_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG030_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG031_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG032_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG033_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG034_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG035_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG036_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG037_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG038_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG039_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG040_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG041_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG042_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG043_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG044_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG045_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG046_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG047_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG048_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG049_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG050_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG051_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ENC0_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC0_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define EXTTRIG_IN7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_CTS_SDA_SSEL0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define FLEXSPI0_SS0_N_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PIO0_21_PIO0_21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PWM0_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_B1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 11) /* PIO0_21 */ +#define PWM1_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_OUT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CT_INP15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG023_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG024_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG025_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG026_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG027_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG028_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG029_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG030_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG031_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG032_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG033_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG034_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG035_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG036_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG037_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG038_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG039_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG040_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG041_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG042_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG043_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG044_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG045_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG046_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG047_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG048_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG049_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG050_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG051_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ENC0_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC0_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC1_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC1_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define EXTTRIG_IN5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define FC7_RTS_SCL_SSEL1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define FLEXSPI0_SCLK_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 5) /* PIO0_22 */ +#define FLEXSPI0_SS1_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 6) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PIO0_22_PIO0_22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PWM0_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_X0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 11) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH8B_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC1_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC1_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC1_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define ADC1_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG024_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG025_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG026_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG027_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG028_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG029_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG030_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG031_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG032_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG033_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG034_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG035_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG036_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG037_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG038_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG039_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG040_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG041_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG042_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG043_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG044_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG045_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG046_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG047_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG048_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG049_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG050_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG051_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PIO0_23_PIO0_23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CT_INP8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG023_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG025_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG026_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG027_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG028_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG029_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG030_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG031_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG032_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG033_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG034_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG035_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG036_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG037_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG038_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG039_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG040_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG041_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG042_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG043_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG044_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG045_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG046_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG047_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG048_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG049_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG050_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG051_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define HSCMP0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define I3C0_SDA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 5) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PIO0_24_PIO0_24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PWM0_A1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 11) /* PIO0_24 */ +#define PWM0_X0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 13) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SWD_TRACEDATA0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 6) /* PIO0_24 */ +#define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CT_INP9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG023_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG024_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG026_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG027_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG028_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG029_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG030_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG031_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG032_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG033_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG034_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG035_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG036_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG037_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG038_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG039_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG040_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG041_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG042_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG043_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG044_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG045_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG046_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG047_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG048_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG049_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG050_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG051_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ENC0_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC0_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC1_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC1_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define EXTTRIG_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define FLEXSPI0_DQS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define HSCMP0_OUT_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 7) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PIO0_25_PIO0_25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PWM0_A0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 11) /* PIO0_25 */ +#define PWM0_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CT_INP14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG023_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG024_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG025_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG027_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG028_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG029_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG030_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG031_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG032_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG033_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG034_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG035_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG036_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG037_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG038_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG039_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG040_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG041_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG042_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG043_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG044_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG045_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG046_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG047_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG048_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG049_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG050_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG051_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PIO0_26_PIO0_26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PWM0_B1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 11) /* PIO0_26 */ +#define RTC_TAMPER2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define ADC0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG023_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG024_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG025_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG026_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG028_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG029_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG030_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG031_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG032_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG033_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG034_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG035_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG036_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG037_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG038_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG039_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG040_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG041_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG042_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG043_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG044_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG045_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG046_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG047_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG048_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG049_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG050_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG051_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define OPAMP1_DP0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PIO0_27_PIO0_27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define ADC0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC1_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC1_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC1_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define ADC1_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CT_INP11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG023_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG024_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG025_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG026_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG027_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG029_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG030_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG031_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG032_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG033_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG034_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG035_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG036_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG037_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG038_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG039_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG040_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG041_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG042_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG043_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG044_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG045_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG046_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG047_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG048_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG049_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG050_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG051_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define I3C0_PUR_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 8) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PIO0_28_PIO0_28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PWM0_A2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 11) /* PIO0_28 */ +#define RTC_TAMPER1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define AOI0_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG023_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG024_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG025_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG026_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG027_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG028_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG030_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG031_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG032_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG033_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG034_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG035_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG036_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG037_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG038_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG039_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG040_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG041_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG042_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG043_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG044_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG045_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG046_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG047_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG048_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG049_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG050_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG051_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ENC0_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC0_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define EXTTRIG_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 6) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PIO0_29_PIO0_29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PWM0_A1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 11) /* PIO0_29 */ +#define PWM0_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define AOI1_OUT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 12) /* PIO0_30 */ +#define CAN0_TD_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 6) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG023_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG024_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG025_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG026_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG027_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG028_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG029_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG031_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG032_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG033_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG034_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG035_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG036_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG037_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG038_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG039_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG040_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG041_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG042_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG043_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG044_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG045_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG046_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG047_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG048_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG049_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG050_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG051_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 9) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PIO0_30_PIO0_30_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PWM1_A1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 11) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH8A_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define AOI0_OUT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 12) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG023_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG024_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG025_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG026_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG027_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG028_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG029_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG030_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG032_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG033_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG034_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG035_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG036_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG037_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG038_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG039_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG040_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG041_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG042_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG043_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG044_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG045_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG046_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG047_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG048_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG049_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG050_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG051_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define I3C0_SCL_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 15) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PIO0_31_PIO0_31_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_CH0B_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define AOI1_OUT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 12) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CT_INP2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG023_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG024_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG025_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG026_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG027_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG028_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG029_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG030_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG031_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG032_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG033_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG034_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG035_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG036_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG037_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG038_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG039_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG040_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG041_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG042_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG043_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG044_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG045_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG046_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG047_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG048_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG049_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG050_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG051_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PIO1_0_PIO1_0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CT_INP3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG023_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG024_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG025_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG026_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG027_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG028_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG029_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG030_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG031_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG032_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG033_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG034_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG035_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG036_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG037_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG038_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG039_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG040_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG041_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG042_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG043_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG044_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG045_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG046_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG047_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG048_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG049_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG050_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG051_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PIO1_1_PIO1_1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PWM0_B2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 11) /* PIO1_1 */ +#define RTC_ALARMOUT_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 10) /* PIO1_1 */ +#define RTC_TAMPER0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define TRACECLK_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define AOI0_OUT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 12) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG023_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG024_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG025_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG026_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG027_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG028_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG029_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG030_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG031_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG032_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG033_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG034_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG035_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG036_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG037_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG038_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG039_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG040_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG041_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG042_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG043_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG044_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG045_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG046_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG047_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG048_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG049_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG050_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG051_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PIO1_2_PIO1_2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PWM0_B0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 11) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG023_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG024_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG025_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG026_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG027_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG028_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG029_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG030_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG031_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG032_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG033_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG034_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG035_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG036_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG037_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG038_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG039_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG040_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG041_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG042_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG043_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG044_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG045_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG046_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG047_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG048_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG049_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG050_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG051_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PIO1_3_PIO1_3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PWM0_A3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 11) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define ADC0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC1_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC1_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC1_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ADC1_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define AOI0_TRIGOUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 12) /* PIO1_4 */ +#define AOI1_TRIGOUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 12) /* PIO1_4 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG023_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG024_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG025_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG026_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG027_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG028_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG029_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG030_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG031_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG032_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG033_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG034_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG035_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG036_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG037_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG038_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG039_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG040_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG041_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG042_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG043_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG044_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG045_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG046_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG047_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG048_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG049_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG050_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG051_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define ENC0_PHASEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define ENC0_PHASEB_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define ENC1_PHASEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define ENC1_PHASEB_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define EXTTRIG_IN8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 7) /* PIO1_4 */ +#define FREQME_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PIO1_4_PIO1_4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PWM0_B2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 11) /* PIO1_4 */ +#define PWM0_EXTA0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_EXTA1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_EXTA2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_EXTA3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_EXTA0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_EXTA1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_EXTA2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_EXTA3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define ADC0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC1_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC1_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC1_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define ADC1_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define AOI0_TRIGOUT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 12) /* PIO1_5 */ +#define AOI1_TRIGOUT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 12) /* PIO1_5 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG023_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG024_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG025_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG026_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG027_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG028_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG029_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG030_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG031_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG032_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG033_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG034_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG035_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG036_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG037_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG038_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG039_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG040_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG041_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG042_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG043_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG044_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG045_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG046_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG047_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG048_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG049_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG050_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG051_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define HSCMP0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PIO1_5_PIO1_5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */ +#define PWM1_A3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 11) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */ +#define ADC0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC1_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC1_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC1_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define ADC1_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define AOI0_TRIGOUT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 12) /* PIO1_6 */ +#define AOI1_TRIGOUT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 12) /* PIO1_6 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG023_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG024_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG025_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG026_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG027_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG028_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG029_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG030_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG031_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG032_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG033_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG034_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG035_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG036_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG037_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG038_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG039_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG040_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG041_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG042_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG043_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG044_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG045_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG046_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG047_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG048_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG049_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG050_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG051_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define HSCMP0_OUT_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 13) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PIO1_6_PIO1_6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PWM0_A1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 11) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define ADC0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC1_CH3B_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC1_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC1_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC1_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define ADC1_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define AOI1_OUT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 12) /* PIO1_7 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG023_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG024_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG025_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG026_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG027_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG028_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG029_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG030_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG031_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG032_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG033_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG034_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG035_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG036_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG037_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG038_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG039_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG040_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG041_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG042_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG043_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG044_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG045_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG046_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG047_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG048_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG049_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG050_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG051_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PIO1_7_PIO1_7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define ADC0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC1_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC1_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC1_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define ADC1_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define AOI0_TRIGOUT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 13) /* PIO1_8 */ +#define AOI1_OUT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 12) /* PIO1_8 */ +#define AOI1_TRIGOUT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 13) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG023_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG024_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG025_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG026_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG027_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG028_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG029_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG030_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG031_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG032_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG033_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG034_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG035_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG036_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG037_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG038_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG039_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG040_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG041_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG042_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG043_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG044_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG045_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG046_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG047_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG048_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG049_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG050_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG051_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */ +#define FC1_SCK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 7) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PIO1_8_PIO1_8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ +#define PWM0_A2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 11) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */ +#define ADC0_CH0A_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC1_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC1_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC1_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define ADC1_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define AOI1_OUT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 12) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CT_INP4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG023_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG024_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG025_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG026_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG027_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG028_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG029_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG030_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG031_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG032_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG033_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG034_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG035_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG036_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG037_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG038_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG039_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG040_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG041_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG042_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG043_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG044_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG045_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG046_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG047_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG048_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG049_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG050_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG051_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define HSCMP0_IN4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define OPAMP0_OUT_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PIO1_9_PIO1_9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define ADC0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC1_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC1_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC1_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define ADC1_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define AOI0_TRIGOUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 12) /* PIO1_10 */ +#define AOI1_TRIGOUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 12) /* PIO1_10 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG023_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG024_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG025_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG026_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG027_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG028_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG029_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG030_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG031_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG032_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG033_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG034_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG035_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG036_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG037_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG038_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG039_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG040_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG041_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG042_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG043_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG044_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG045_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG046_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG047_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG048_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG049_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG050_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG051_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define HSCMP1_IN3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define HSCMP2_OUT_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 13) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PIO1_10_PIO1_10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */ +#define PWM0_X1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 11) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 4) /* PIO1_10 */ +#define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CT_INP5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG023_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG024_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG025_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG026_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG027_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG028_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG029_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG030_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG031_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG032_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG033_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG034_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG035_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG036_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG037_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG038_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG039_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG040_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG041_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG042_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG043_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG044_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG045_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG046_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG047_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG048_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG049_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG050_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG051_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ENC0_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC0_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define EXTTRIG_IN8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define FC6_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 10) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define HS_SPI_SSEL0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PIO1_11_PIO1_11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PWM0_A0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 11) /* PIO1_11 */ +#define PWM0_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define ADC0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC1_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC1_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC1_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ADC1_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define AOI0_OUT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 12) /* PIO1_12 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG023_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG024_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG025_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG026_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG027_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG028_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG029_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG030_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG031_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG032_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG033_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG034_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG035_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG036_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG037_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG038_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG039_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG040_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG041_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG042_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG043_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG044_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG045_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG046_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG047_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG048_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG049_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG050_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG051_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define ENC0_PHASEA_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define ENC0_PHASEB_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define ENC1_PHASEA_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define ENC1_PHASEB_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define EXTTRIG_IN9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define HSCMP0_IN1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PIO1_12_PIO1_12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */ +#define PWM0_A3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 11) /* PIO1_12 */ +#define PWM0_EXTA0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_EXTA1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_EXTA2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_EXTA3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_EXTA0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_EXTA1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_EXTA2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_EXTA3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 4) /* PIO1_12 */ +#define ACMP0VREF_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define AOI0_OUT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 12) /* PIO1_13 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CT_INP6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG023_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG024_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG025_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG026_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG027_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG028_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG029_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG030_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG031_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG032_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG033_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG034_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG035_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG036_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG037_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG038_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG039_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG040_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG041_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG042_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG043_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG044_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG045_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG046_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG047_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG048_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG049_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG050_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG051_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PIO1_13_PIO1_13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PWM1_X1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 11) /* PIO1_13 */ +#define SCT0_OUT8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 8) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 4) /* PIO1_13 */ +#define ADC0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC1_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC1_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC1_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ADC1_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG023_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG024_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG025_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG026_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG027_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG028_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG029_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG030_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG031_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG032_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG033_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG034_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG035_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG036_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG037_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG038_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG039_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG040_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG041_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG042_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG043_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG044_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG045_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG046_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG047_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG048_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG049_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG050_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG051_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define ENC0_PHASEA_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define ENC0_PHASEB_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define ENC1_PHASEA_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define ENC1_PHASEB_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define EXTTRIG_IN9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PIO1_14_PIO1_14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PWM0_B3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 11) /* PIO1_14 */ +#define PWM0_EXTA0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_EXTA1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_EXTA2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_EXTA3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_EXTA0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_EXTA1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_EXTA2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_EXTA3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define ADC0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CT_INP7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG023_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG024_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG025_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG026_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG027_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG028_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG029_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG030_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG031_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG032_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG033_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG034_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG035_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG036_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG037_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG038_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG039_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG040_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG041_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG042_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG043_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG044_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG045_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG046_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG047_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG048_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG049_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG050_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG051_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ENC0_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC0_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC1_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC1_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define EXTTRIG_IN8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define FC1_SCK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 9) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define FLEXSPI0_DATA5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 8) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PIO1_15_PIO1_15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PWM0_B0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 11) /* PIO1_15 */ +#define PWM0_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG023_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG024_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG025_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG026_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG027_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG028_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG029_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG030_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG031_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG032_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG033_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG034_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG035_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG036_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG037_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG038_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG039_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG040_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG041_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG042_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG043_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG044_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG045_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG046_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG047_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG048_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG049_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG050_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG051_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ENC0_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC0_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC1_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC1_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define EXTTRIG_IN7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 9) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define FLEXSPI0_DATA4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 8) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PIO1_16_PIO1_16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PWM0_B2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 11) /* PIO1_16 */ +#define PWM0_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ADC0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC1_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC1_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC1_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define ADC1_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define AOI1_OUT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 12) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG023_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG024_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG025_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG026_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG027_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG028_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG029_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG030_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG031_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG032_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG033_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG034_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG035_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG036_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG037_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG038_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG039_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG040_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG041_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG042_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG043_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG044_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG045_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG046_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG047_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG048_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG049_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG050_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG051_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PIO1_17_PIO1_17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PWM0_B0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 11) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define ADC0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC1_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC1_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC1_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define ADC1_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG023_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG024_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG025_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG026_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG027_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG028_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG029_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG030_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG031_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG032_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG033_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG034_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG035_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG036_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG037_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG038_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG039_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG040_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG041_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG042_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG043_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG044_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG045_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG046_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG047_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG048_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG049_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG050_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG051_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define HSCMP2_OUT_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 13) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PIO1_18_PIO1_18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PWM0_A2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 11) /* PIO1_18 */ +#define RTC_ALARMOUT_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 8) /* PIO1_18 */ +#define RTC_TAMPER3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ADC0_CH4B_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC1_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC1_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC1_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define ADC1_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define AOI1_OUT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 13) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */ +#define DAC1_OUT_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG023_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG024_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG025_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG026_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG027_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG028_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG029_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG030_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG031_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG032_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG033_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG034_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG035_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG036_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG037_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG038_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG039_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG040_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG041_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG042_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG043_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG044_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG045_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG046_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG047_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG048_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG049_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG050_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG051_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define HSCMP1_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define PIO1_19_PIO1_19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */ +#define ADC0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC1_CH8A_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC1_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC1_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC1_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define ADC1_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define AOI0_OUT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 12) /* PIO1_20 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define CT_INP14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG023_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG024_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG025_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG026_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG027_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG028_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG029_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG030_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG031_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG032_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG033_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG034_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG035_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG036_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG037_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG038_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG039_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG040_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG041_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG042_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG043_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG044_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG045_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG046_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG047_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG048_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG049_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG050_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG051_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PIO1_20_PIO1_20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */ +#define PWM0_A0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 11) /* PIO1_20 */ +#define ADC0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC1_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC1_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC1_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define ADC1_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define AOI0_TRIGOUT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 12) /* PIO1_21 */ +#define AOI1_TRIGOUT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 12) /* PIO1_21 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG023_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG024_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG025_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG026_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG027_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG028_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG029_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG030_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG031_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG032_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG033_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG034_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG035_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG036_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG037_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG038_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG039_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG040_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG041_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG042_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG043_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG044_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG045_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG046_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG047_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG048_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG049_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG050_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG051_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PIO1_21_PIO1_21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PWM1_A0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 11) /* PIO1_21 */ +#define ADC0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define AOI0_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */ +#define AOI1_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 3) /* PIO1_22 */ +#define DAC0_OUT_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG023_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG024_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG025_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG026_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG027_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG028_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG029_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG030_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG031_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG032_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG033_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG034_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG035_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG036_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG037_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG038_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG039_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG040_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG041_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG042_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG043_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG044_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG045_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG046_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG047_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG048_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG049_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG050_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG051_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define HSCMP1_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PIO1_22_PIO1_22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PWM0_B1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 11) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define ADC0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC1_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC1_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC1_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define ADC1_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define AOI0_TRIGOUT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 12) /* PIO1_23 */ +#define AOI1_TRIGOUT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 12) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG023_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG024_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG025_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG026_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG027_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG028_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG029_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG030_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG031_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG032_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG033_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG034_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG035_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG036_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG037_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG038_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG039_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG040_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG041_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG042_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG043_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG044_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG045_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG046_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG047_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG048_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG049_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG050_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG051_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define HSCMP2_IN1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PIO1_23_PIO1_23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */ +#define PWM1_A1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 11) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 2) /* PIO1_23 */ +#define ADC0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC1_CH8B_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC1_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC1_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC1_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define ADC1_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define AOI0_OUT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 12) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG023_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG024_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG025_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG026_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG027_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG028_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG029_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG030_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG031_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG032_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG033_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG034_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG035_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG036_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG037_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG038_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG039_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG040_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG041_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG042_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG043_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG044_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG045_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG046_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG047_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG048_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG049_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG050_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG051_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define PIO1_24_PIO1_24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 2) /* PIO1_24 */ +#define ADC0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC1_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC1_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC1_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define ADC1_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define AOI0_OUT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 13) /* PIO1_25 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG023_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG024_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG025_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG026_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG027_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG028_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG029_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG030_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG031_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG032_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG033_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG034_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG035_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG036_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG037_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG038_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG039_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG040_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG041_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG042_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG043_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG044_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG045_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG046_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG047_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG048_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG049_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG050_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG051_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PIO1_25_PIO1_25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PWM1_A2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 11) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define ADC0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC1_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC1_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC1_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define ADC1_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define AOI1_OUT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 13) /* PIO1_26 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CT_INP3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG023_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG024_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG025_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG026_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG027_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG028_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG029_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG030_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG031_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG032_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG033_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG034_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG035_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG036_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG037_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG038_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG039_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG040_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG041_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG042_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG043_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG044_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG045_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG046_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG047_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG048_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG049_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG050_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG051_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PIO1_26_PIO1_26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PWM0_A1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 11) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define ADC0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC1_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC1_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC1_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define ADC1_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define CAN0_TD_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 9) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG023_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG024_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG025_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG026_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG027_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG028_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG029_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG030_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG031_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG032_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG033_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG034_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG035_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG036_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG037_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG038_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG039_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG040_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG041_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG042_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG043_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG044_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG045_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG046_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG047_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG048_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG049_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG050_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG051_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define FLEXSPI0_DATA6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 8) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PIO1_27_PIO1_27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PWM1_B2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 11) /* PIO1_27 */ +#define ADC0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC1_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC1_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC1_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define ADC1_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define AOI0_TRIGOUT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 10) /* PIO1_28 */ +#define AOI1_TRIGOUT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 10) /* PIO1_28 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CT_INP2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG023_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG024_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG025_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG026_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG027_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG028_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG029_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG030_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG031_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG032_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG033_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG034_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG035_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG036_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG037_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG038_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG039_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG040_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG041_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG042_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG043_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG044_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG045_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG046_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG047_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG048_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG049_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG050_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG051_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define HSCMP1_OUT_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 13) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PIO1_28_PIO1_28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PWM1_X3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 11) /* PIO1_28 */ +#define ADC0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC1_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC1_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC1_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ADC1_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG023_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG024_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG025_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG026_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG027_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG028_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG029_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG030_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG031_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG032_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG033_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG034_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG035_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG036_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG037_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG038_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG039_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG040_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG041_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG042_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG043_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG044_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG045_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG046_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG047_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG048_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG049_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG050_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG051_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define ENC0_PHASEA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define ENC0_PHASEB_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define ENC1_PHASEA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define ENC1_PHASEB_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define EXTTRIG_IN9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define FLEXSPI0_DATA7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 8) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PIO1_29_PIO1_29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PWM0_EXTA0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_EXTA1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_EXTA2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_EXTA3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM0_X2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 11) /* PIO1_29 */ +#define PWM1_EXTA0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_EXTA1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_EXTA2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_EXTA3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define ADC0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC1_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC1_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC1_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define ADC1_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define AOI1_OUT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 12) /* PIO1_30 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG023_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG024_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG025_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG026_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG027_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG028_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG029_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG030_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG031_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG032_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG033_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG034_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG035_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG036_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG037_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG038_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG039_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG040_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG041_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG042_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG043_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG044_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG045_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG046_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG047_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG048_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG049_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG050_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG051_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define HSCMP0_OUT_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 13) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PIO1_30_PIO1_30_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PWM0_X3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 11) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define ADC0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC1_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC1_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC1_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ADC1_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define AOI0_IN0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI0_IN9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define AOI1_IN9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG023_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG024_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG025_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG026_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG027_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG028_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG029_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG030_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG031_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG032_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG033_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG034_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG035_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG036_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG037_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG038_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG039_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG040_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG041_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG042_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG043_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG044_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG045_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG046_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG047_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG048_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG049_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG050_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG051_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define ENC0_PHASEA_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define ENC0_PHASEB_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define ENC1_PHASEA_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define ENC1_PHASEB_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define EXTTRIG_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PIO1_31_PIO1_31_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PWM0_EXTA0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_EXTA1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_EXTA2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_EXTA3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_B2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 11) /* PIO1_31 */ +#define PWM1_EXTA0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_EXTA1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_EXTA2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_EXTA3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define USB0_VBUS_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define ADC0_CH9A_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 0) /* PIO2_0 */ +#define AOI0_OUT0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 12) /* PIO2_0 */ +#define CTIMER0_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER0_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER0_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER0_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER1_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER1_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER1_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER2_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER2_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER2_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER2_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER3_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER3_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER3_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER3_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER4_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER4_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER4_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CTIMER4_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define CT_INP4_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 2) /* PIO2_0 */ +#define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 0) /* PIO2_0 */ +#define I3C0_PUR_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 5) /* PIO2_0 */ +#define AOI0_OUT2_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 12) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define I3C0_SDA_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 5) /* PIO2_1 */ +#define OPAMP2_DP0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ + +#endif diff --git a/dts/nxp/lpc/LPC5536JBD64-pinctrl.h b/dts/nxp/lpc/LPC5536JBD64-pinctrl.h new file mode 100644 index 000000000..7cc7abbbd --- /dev/null +++ b/dts/nxp/lpc/LPC5536JBD64-pinctrl.h @@ -0,0 +1,4538 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5536JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5536JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC5536JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG023_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG024_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG025_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG026_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG027_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG028_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG029_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG030_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG031_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG032_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG033_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG034_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG035_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG036_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG037_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG038_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG039_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG040_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG041_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG042_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG043_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG044_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG045_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG046_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG047_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG048_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG049_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG050_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG051_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMIC0_DATA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 5) /* PIO0_0 */ +#define ENC0_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC0_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define EXTTRIG_IN8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PIO0_0_PIO0_0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PWM0_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_B2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 11) /* PIO0_0 */ +#define PWM1_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SWCLK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 9) /* PIO0_0 */ +#define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_CH2B_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define AOI0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 12) /* PIO0_1 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CT_INP0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG023_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG024_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG025_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG026_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG027_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG028_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG029_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG030_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG031_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG032_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG033_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG034_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG035_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG036_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG037_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG038_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG039_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG040_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG041_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG042_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG043_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG044_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG045_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG046_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG047_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG048_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG049_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG050_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG051_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_CLK0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PIO0_1_PIO0_1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define AOI0_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define AOI1_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CT_INP1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG023_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG024_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG025_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG026_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG027_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG028_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG029_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG030_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG031_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG032_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG033_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG034_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG035_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG036_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG037_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG038_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG039_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG040_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG041_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG042_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG043_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG044_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG045_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG046_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG047_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG048_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG049_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG050_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG051_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ENC0_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC0_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define EXTTRIG_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define FLEXSPI0_DATA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 5) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PIO0_2_PIO0_2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PWM0_A2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 11) /* PIO0_2 */ +#define PWM0_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG023_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG024_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG025_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG026_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG027_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG028_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG029_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG030_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG031_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG032_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG033_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG034_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG035_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG036_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG037_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG038_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG039_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG040_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG041_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG042_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG043_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG044_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG045_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG046_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG047_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG048_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG049_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG050_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG051_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define FLEXSPI0_DATA2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PIO0_3_PIO0_3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PWM1_B0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 11) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define AOI0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CT_INP12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG023_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG024_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG025_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG026_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG027_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG028_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG029_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG030_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG031_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG032_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG033_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG034_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG035_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG036_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG037_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG038_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG039_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG040_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG041_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG042_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG043_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG044_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG045_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG046_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG047_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG048_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG049_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG050_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG051_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ENC0_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC0_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define EXTTRIG_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 9) /* PIO0_4 */ +#define FLEXSPI0_DATA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 5) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PIO0_4_PIO0_4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PWM0_B3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 11) /* PIO0_4 */ +#define PWM0_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG023_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG024_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG025_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG026_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG027_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG028_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG029_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG030_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG031_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG032_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG033_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG034_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG035_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG036_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG037_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG038_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG039_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG040_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG041_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG042_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG043_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG044_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG045_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG046_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG047_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG048_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG049_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG050_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG051_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ENC0_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC0_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define EXTTRIG_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PIO0_5_PIO0_5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PWM0_A0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 11) /* PIO0_5 */ +#define PWM0_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define AOI0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define CT_INP13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG023_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG024_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG025_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG026_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG027_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG028_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG029_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG030_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG031_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG032_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG033_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG034_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG035_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG036_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG037_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG038_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG039_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG040_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG041_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG042_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG043_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG044_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG045_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG046_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG047_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG048_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG049_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG050_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG051_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ENC0_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC0_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define EXTTRIG_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 9) /* PIO0_6 */ +#define FLEXSPI0_DATA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PIO0_6_PIO0_6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PWM0_B0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 11) /* PIO0_6 */ +#define PWM0_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_OUT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 8) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define AOI0_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define AOI1_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG023_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG024_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG025_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG026_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG027_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG028_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG029_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG030_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG031_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG032_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG033_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG034_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG035_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG036_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG037_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG038_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG039_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG040_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG041_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG042_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG043_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG044_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG045_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG046_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG047_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG048_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG049_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG050_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG051_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMIC0_CLK0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 5) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP1_IN0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP2_OUT_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 13) /* PIO0_7 */ +#define MCLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 8) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PIO0_7_PIO0_7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PWM0_B0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 11) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG023_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG024_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG025_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG026_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG027_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG028_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG029_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG030_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG031_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG032_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG033_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG034_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG035_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG036_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG037_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG038_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG039_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG040_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG041_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG042_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG043_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG044_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG045_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG046_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG047_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG048_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG049_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG050_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG051_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define OPAMP0_DP0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PIO0_8_PIO0_8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define AOI0_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define AOI1_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG023_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG024_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG025_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG026_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG027_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG028_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG029_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG030_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG031_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG032_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG033_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG034_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG035_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG036_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG037_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG038_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG039_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG040_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG041_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG042_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG043_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG044_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG045_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG046_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG047_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG048_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG049_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG050_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG051_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define I3C0_SCL_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 7) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PIO0_9_PIO0_9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PWM1_A2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 11) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SWDIO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 9) /* PIO0_9 */ +#define ADC0_CH1A_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CT_INP10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG023_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG024_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG025_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG026_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG027_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG028_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG029_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG030_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG031_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG032_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG033_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG034_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG035_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG036_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG037_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG038_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG039_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG040_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG041_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG042_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG043_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG044_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG045_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG046_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG047_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG048_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG049_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG050_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG051_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PIO0_10_PIO0_10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_CH2A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define AOI1_OUT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 12) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG023_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG024_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG025_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG026_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG027_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG028_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG029_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG030_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG031_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG032_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG033_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG034_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG035_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG036_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG037_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG038_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG039_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG040_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG041_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG042_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG043_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG044_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG045_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG046_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG047_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG048_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG049_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG050_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG051_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PIO0_11_PIO0_11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define AOI0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CT_INP0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG023_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG024_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG025_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG026_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG027_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG028_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG029_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG030_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG031_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG032_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG033_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG034_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG035_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG036_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG037_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG038_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG039_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG040_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG041_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG042_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG043_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG044_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG045_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG046_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG047_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG048_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG049_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG050_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG051_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ENC0_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC0_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define EXTTRIG_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PIO0_13_PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PWM0_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define AOI0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CT_INP1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG023_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG024_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG025_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG026_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG027_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG028_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG029_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG030_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG031_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG032_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG033_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG034_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG035_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG036_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG037_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG038_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG039_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG040_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG041_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG042_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG043_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG044_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG045_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG046_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG047_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG048_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG049_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG050_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG051_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ENC0_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC0_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define EXTTRIG_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PIO0_14_PIO0_14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PWM0_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH3A_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CT_INP16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG023_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG024_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG025_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG026_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG027_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG028_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG029_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG030_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG031_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG032_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG033_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG034_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG035_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG036_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG037_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG038_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG039_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG040_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG041_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG042_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG043_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG044_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG045_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG046_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG047_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG048_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG049_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG050_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG051_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PIO0_15_PIO0_15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH3B_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define AOI0_OUT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 12) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CT_INP4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG023_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG024_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG025_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG026_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG027_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG028_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG029_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG030_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG031_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG032_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG033_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG034_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG035_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG036_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG037_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG038_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG039_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG040_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG041_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG042_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG043_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG044_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG045_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG046_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG047_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG048_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG049_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG050_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG051_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PIO0_16_PIO0_16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define AOI0_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define AOI1_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG023_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG024_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG025_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG026_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG027_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG028_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG029_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG030_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG031_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG032_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG033_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG034_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG035_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG036_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG037_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG038_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG039_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG040_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG041_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG042_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG043_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG044_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG045_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG046_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG047_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG048_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG049_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG050_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG051_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 1) /* PIO0_17 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 8) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define HSCMP1_OUT_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 13) /* PIO0_17 */ +#define HSCMP2_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PIO0_17_PIO0_17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define AOI0_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define AOI1_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG023_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG024_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG025_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG026_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG027_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG028_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG029_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG030_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG031_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG032_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG033_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG034_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG035_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG036_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG037_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG038_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG039_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG040_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG041_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG042_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG043_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG044_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG045_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG046_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG047_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG048_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG049_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG050_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG051_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PIO0_18_PIO0_18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PWM1_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 11) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SWO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 8) /* PIO0_18 */ +#define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define AOI0_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define AOI1_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG023_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG024_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG025_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG026_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG027_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG028_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG029_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG030_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG031_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG032_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG033_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG034_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG035_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG036_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG037_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG038_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG039_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG040_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG041_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG042_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG043_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG044_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG045_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG046_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG047_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG048_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG049_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG050_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG051_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ENC0_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC0_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define EXTTRIG_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define FLEXSPI0_SCLK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 5) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PIO0_19_PIO0_19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PWM0_B1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 11) /* PIO0_19 */ +#define PWM0_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CT_INP15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG023_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG024_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG025_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG026_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG027_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG028_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG029_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG030_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG031_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG032_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG033_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG034_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG035_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG036_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG037_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG038_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG039_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG040_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG041_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG042_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG043_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG044_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG045_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG046_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG047_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG048_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG049_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG050_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG051_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PIO0_20_PIO0_20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PWM1_X2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 13) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define AOI0_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define AOI1_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG023_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG024_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG025_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG026_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG027_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG028_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG029_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG030_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG031_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG032_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG033_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG034_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG035_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG036_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG037_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG038_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG039_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG040_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG041_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG042_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG043_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG044_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG045_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG046_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG047_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG048_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG049_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG050_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG051_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ENC0_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC0_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define EXTTRIG_IN7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_CTS_SDA_SSEL0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define FLEXSPI0_SS0_N_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PIO0_21_PIO0_21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PWM0_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_B1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 11) /* PIO0_21 */ +#define PWM1_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_OUT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ADC1_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CT_INP15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG023_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG024_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG025_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG026_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG027_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG028_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG029_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG030_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG031_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG032_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG033_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG034_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG035_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG036_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG037_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG038_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG039_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG040_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG041_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG042_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG043_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG044_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG045_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG046_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG047_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG048_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG049_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG050_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG051_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define ENC0_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC0_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC1_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define ENC1_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define EXTTRIG_IN5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define FC7_RTS_SCL_SSEL1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define FLEXSPI0_SCLK_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 5) /* PIO0_22 */ +#define FLEXSPI0_SS1_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 6) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PIO0_22_PIO0_22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PWM0_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */ +#define PWM1_X0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 11) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CT_INP8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG023_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG025_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG026_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG027_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG028_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG029_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG030_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG031_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG032_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG033_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG034_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG035_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG036_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG037_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG038_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG039_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG040_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG041_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG042_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG043_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG044_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG045_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG046_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG047_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG048_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG049_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG050_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG051_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define HSCMP0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define I3C0_SDA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 5) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PIO0_24_PIO0_24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PWM0_A1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 11) /* PIO0_24 */ +#define PWM0_X0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 13) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SWD_TRACEDATA0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 6) /* PIO0_24 */ +#define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ADC1_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CT_INP9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG023_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG024_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG026_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG027_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG028_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG029_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG030_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG031_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG032_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG033_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG034_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG035_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG036_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG037_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG038_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG039_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG040_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG041_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG042_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG043_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG044_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG045_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG046_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG047_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG048_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG049_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG050_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG051_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define ENC0_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC0_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC1_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define ENC1_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define EXTTRIG_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define FLEXSPI0_DQS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define HSCMP0_OUT_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 7) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PIO0_25_PIO0_25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PWM0_A0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 11) /* PIO0_25 */ +#define PWM0_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CT_INP14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG023_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG024_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG025_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG027_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG028_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG029_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG030_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG031_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG032_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG033_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG034_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG035_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG036_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG037_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG038_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG039_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG040_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG041_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG042_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG043_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG044_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG045_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG046_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG047_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG048_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG049_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG050_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG051_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PIO0_26_PIO0_26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PWM0_B1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 11) /* PIO0_26 */ +#define RTC_TAMPER2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define ADC0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG023_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG024_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG025_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG026_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG028_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG029_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG030_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG031_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG032_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG033_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG034_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG035_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG036_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG037_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG038_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG039_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG040_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG041_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG042_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG043_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG044_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG045_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG046_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG047_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG048_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG049_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG050_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG051_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define OPAMP1_DP0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PIO0_27_PIO0_27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define AOI0_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG023_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG024_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG025_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG026_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG027_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG028_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG030_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG031_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG032_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG033_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG034_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG035_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG036_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG037_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG038_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG039_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG040_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG041_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG042_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG043_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG044_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG045_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG046_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG047_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG048_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG049_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG050_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG051_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ENC0_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC0_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define EXTTRIG_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 6) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PIO0_29_PIO0_29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PWM0_A1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 11) /* PIO0_29 */ +#define PWM0_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define AOI1_OUT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 12) /* PIO0_30 */ +#define CAN0_TD_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 6) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG023_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG024_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG025_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG026_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG027_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG028_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG029_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG031_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG032_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG033_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG034_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG035_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG036_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG037_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG038_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG039_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG040_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG041_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG042_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG043_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG044_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG045_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG046_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG047_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG048_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG049_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG050_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG051_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 9) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PIO0_30_PIO0_30_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PWM1_A1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 11) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_CH8A_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define ADC1_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define AOI0_OUT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 12) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG023_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG024_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG025_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG026_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG027_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG028_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG029_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG030_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG032_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG033_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG034_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG035_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG036_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG037_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG038_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG039_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG040_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG041_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG042_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG043_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG044_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG045_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG046_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG047_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG048_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG049_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG050_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG051_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define I3C0_SCL_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 15) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PIO0_31_PIO0_31_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_CH0B_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define AOI1_OUT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 12) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CT_INP2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG023_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG024_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG025_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG026_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG027_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG028_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG029_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG030_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG031_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG032_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG033_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG034_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG035_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG036_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG037_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG038_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG039_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG040_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG041_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG042_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG043_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG044_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG045_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG046_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG047_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG048_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG049_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG050_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG051_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PIO1_0_PIO1_0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CT_INP3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG023_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG024_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG025_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG026_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG027_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG028_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG029_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG030_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG031_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG032_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG033_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG034_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG035_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG036_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG037_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG038_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG039_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG040_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG041_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG042_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG043_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG044_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG045_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG046_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG047_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG048_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG049_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG050_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG051_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PIO1_1_PIO1_1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PWM0_B2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 11) /* PIO1_1 */ +#define RTC_ALARMOUT_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 10) /* PIO1_1 */ +#define RTC_TAMPER0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define TRACECLK_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define AOI0_OUT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 12) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG023_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG024_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG025_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG026_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG027_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG028_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG029_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG030_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG031_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG032_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG033_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG034_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG035_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG036_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG037_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG038_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG039_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG040_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG041_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG042_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG043_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG044_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG045_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG046_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG047_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG048_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG049_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG050_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG051_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PIO1_2_PIO1_2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PWM0_B0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 11) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG023_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG024_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG025_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG026_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG027_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG028_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG029_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG030_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG031_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG032_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG033_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG034_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG035_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG036_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG037_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG038_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG039_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG040_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG041_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG042_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG043_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG044_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG045_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG046_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG047_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG048_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG049_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG050_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG051_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PIO1_3_PIO1_3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PWM0_A3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 11) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CT_INP5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG023_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG024_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG025_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG026_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG027_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG028_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG029_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG030_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG031_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG032_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG033_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG034_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG035_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG036_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG037_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG038_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG039_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG040_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG041_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG042_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG043_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG044_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG045_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG046_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG047_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG048_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG049_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG050_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG051_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ENC0_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC0_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define EXTTRIG_IN8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define FC6_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 10) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define HS_SPI_SSEL0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PIO1_11_PIO1_11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PWM0_A0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 11) /* PIO1_11 */ +#define PWM0_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ACMP0VREF_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define ADC1_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define AOI0_OUT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 12) /* PIO1_13 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define CT_INP6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG023_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG024_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG025_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG026_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG027_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG028_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG029_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG030_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG031_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG032_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG033_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG034_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG035_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG036_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG037_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG038_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG039_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG040_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG041_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG042_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG043_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG044_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG045_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG046_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG047_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG048_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG049_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG050_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG051_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PIO1_13_PIO1_13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */ +#define PWM1_X1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 11) /* PIO1_13 */ +#define SCT0_OUT8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 8) /* PIO1_13 */ +#define ADC0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ADC1_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CT_INP7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG023_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG024_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG025_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG026_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG027_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG028_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG029_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG030_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG031_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG032_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG033_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG034_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG035_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG036_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG037_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG038_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG039_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG040_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG041_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG042_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG043_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG044_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG045_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG046_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG047_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG048_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG049_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG050_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG051_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define ENC0_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC0_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC1_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define ENC1_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define EXTTRIG_IN8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define FC1_SCK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 9) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define FLEXSPI0_DATA5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 8) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PIO1_15_PIO1_15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PWM0_B0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 11) /* PIO1_15 */ +#define PWM0_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define ADC0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ADC1_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG023_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG024_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG025_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG026_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG027_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG028_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG029_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG030_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG031_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG032_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG033_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG034_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG035_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG036_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG037_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG038_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG039_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG040_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG041_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG042_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG043_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG044_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG045_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG046_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG047_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG048_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG049_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG050_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG051_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define ENC0_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC0_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC1_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ENC1_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define EXTTRIG_IN7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 9) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define FLEXSPI0_DATA4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 8) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PIO1_16_PIO1_16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PWM0_B2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 11) /* PIO1_16 */ +#define PWM0_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */ +#define ADC0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define ADC1_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define AOI0_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */ +#define AOI1_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 3) /* PIO1_22 */ +#define DAC0_OUT_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG023_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG024_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG025_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG026_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG027_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG028_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG029_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG030_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG031_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG032_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG033_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG034_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG035_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG036_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG037_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG038_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG039_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG040_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG041_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG042_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG043_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG044_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG045_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG046_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG047_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG048_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG049_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG050_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG051_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define HSCMP1_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PIO1_22_PIO1_22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */ +#define PWM0_B1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 11) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */ +#define AOI0_OUT2_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 12) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define I3C0_SDA_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 5) /* PIO2_1 */ +#define OPAMP2_DP0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ + +#endif diff --git a/dts/nxp/lpc/LPC5536JHI48-pinctrl.h b/dts/nxp/lpc/LPC5536JHI48-pinctrl.h new file mode 100644 index 000000000..0e299b6a7 --- /dev/null +++ b/dts/nxp/lpc/LPC5536JHI48-pinctrl.h @@ -0,0 +1,3714 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC5536JHI48/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC5536JHI48_ +#define _ZEPHYR_DTS_BINDING_LPC5536JHI48_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define ADC1_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG023_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG024_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG025_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG026_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG027_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG028_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG029_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG030_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG031_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG032_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG033_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG034_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG035_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG036_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG037_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG038_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG039_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG040_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG041_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG042_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG043_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG044_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG045_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG046_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG047_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG048_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG049_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG050_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG051_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMIC0_DATA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 5) /* PIO0_0 */ +#define ENC0_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC0_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define ENC1_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define EXTTRIG_IN8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PIO0_0_PIO0_0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PWM0_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_B2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 11) /* PIO0_0 */ +#define PWM1_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SWCLK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 9) /* PIO0_0 */ +#define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_CH2B_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define ADC1_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define AOI0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 12) /* PIO0_1 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CT_INP0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG023_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG024_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG025_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG026_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG027_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG028_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG029_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG030_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG031_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG032_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG033_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG034_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG035_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG036_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG037_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG038_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG039_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG040_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG041_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG042_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG043_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG044_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG045_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG046_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG047_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG048_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG049_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG050_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG051_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMIC0_CLK0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PIO0_1_PIO0_1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ADC1_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define AOI0_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define AOI1_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CT_INP1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG023_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG024_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG025_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG026_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG027_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG028_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG029_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG030_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG031_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG032_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG033_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG034_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG035_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG036_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG037_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG038_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG039_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG040_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG041_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG042_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG043_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG044_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG045_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG046_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG047_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG048_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG049_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG050_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG051_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define ENC0_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC0_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define ENC1_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define EXTTRIG_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define FLEXSPI0_DATA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 5) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PIO0_2_PIO0_2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PWM0_A2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 11) /* PIO0_2 */ +#define PWM0_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define ADC1_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG023_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG024_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG025_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG026_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG027_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG028_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG029_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG030_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG031_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG032_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG033_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG034_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG035_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG036_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG037_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG038_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG039_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG040_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG041_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG042_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG043_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG044_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG045_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG046_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG047_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG048_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG049_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG050_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG051_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define FLEXSPI0_DATA2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PIO0_3_PIO0_3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PWM1_B0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 11) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ADC1_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define AOI0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI0_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define AOI1_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CT_INP12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG023_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG024_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG025_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG026_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG027_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG028_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG029_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG030_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG031_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG032_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG033_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG034_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG035_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG036_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG037_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG038_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG039_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG040_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG041_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG042_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG043_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG044_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG045_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG046_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG047_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG048_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG049_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG050_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG051_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define ENC0_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC0_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define ENC1_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define EXTTRIG_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 9) /* PIO0_4 */ +#define FLEXSPI0_DATA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 5) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PIO0_4_PIO0_4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PWM0_B3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 11) /* PIO0_4 */ +#define PWM0_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ADC1_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG023_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG024_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG025_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG026_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG027_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG028_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG029_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG030_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG031_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG032_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG033_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG034_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG035_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG036_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG037_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG038_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG039_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG040_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG041_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG042_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG043_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG044_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG045_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG046_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG047_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG048_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG049_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG050_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG051_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define ENC0_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC0_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define ENC1_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define EXTTRIG_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PIO0_5_PIO0_5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PWM0_A0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 11) /* PIO0_5 */ +#define PWM0_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ADC1_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define AOI0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI0_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define AOI1_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define CT_INP13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG023_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG024_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG025_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG026_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG027_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG028_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG029_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG030_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG031_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG032_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG033_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG034_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG035_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG036_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG037_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG038_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG039_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG040_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG041_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG042_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG043_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG044_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG045_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG046_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG047_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG048_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG049_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG050_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG051_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define ENC0_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC0_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define ENC1_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define EXTTRIG_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 9) /* PIO0_6 */ +#define FLEXSPI0_DATA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PIO0_6_PIO0_6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PWM0_B0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 11) /* PIO0_6 */ +#define PWM0_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_OUT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 8) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define ADC1_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define AOI0_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define AOI1_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG023_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG024_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG025_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG026_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG027_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG028_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG029_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG030_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG031_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG032_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG033_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG034_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG035_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG036_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG037_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG038_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG039_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG040_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG041_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG042_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG043_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG044_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG045_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG046_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG047_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG048_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG049_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG050_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG051_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define DMIC0_CLK0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 5) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP1_IN0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define HSCMP2_OUT_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 13) /* PIO0_7 */ +#define MCLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 8) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PIO0_7_PIO0_7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ +#define PWM0_B0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 11) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ +#define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define ADC1_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG023_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG024_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG025_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG026_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG027_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG028_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG029_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG030_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG031_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG032_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG033_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG034_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG035_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG036_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG037_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG038_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG039_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG040_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG041_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG042_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG043_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG044_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG045_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG046_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG047_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG048_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG049_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG050_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG051_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define OPAMP0_DP0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PIO0_8_PIO0_8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define ADC1_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define AOI0_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define AOI1_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG023_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG024_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG025_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG026_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG027_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG028_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG029_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG030_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG031_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG032_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG033_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG034_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG035_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG036_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG037_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG038_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG039_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG040_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG041_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG042_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG043_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG044_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG045_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG046_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG047_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG048_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG049_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG050_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG051_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define I3C0_SCL_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 7) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PIO0_9_PIO0_9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PWM1_A2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 11) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SWDIO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 9) /* PIO0_9 */ +#define ADC0_CH1A_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define ADC1_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define CT_INP10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG023_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG024_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG025_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG026_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG027_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG028_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG029_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG030_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG031_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG032_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG033_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG034_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG035_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG036_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG037_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG038_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG039_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG040_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG041_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG042_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG043_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG044_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG045_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG046_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG047_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG048_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG049_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG050_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG051_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define PIO0_10_PIO0_10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ +#define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_CH2A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define ADC1_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define AOI1_OUT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 12) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG023_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG024_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG025_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG026_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG027_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG028_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG029_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG030_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG031_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG032_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG033_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG034_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG035_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG036_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG037_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG038_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG039_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG040_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG041_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG042_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG043_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG044_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG045_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG046_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG047_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG048_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG049_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG050_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG051_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ +#define FREQME_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define PIO0_11_PIO0_11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ +#define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ADC1_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define AOI0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI0_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define AOI1_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CT_INP0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG023_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG024_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG025_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG026_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG027_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG028_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG029_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG030_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG031_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG032_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG033_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG034_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG035_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG036_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG037_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG038_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG039_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG040_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG041_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG042_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG043_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG044_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG045_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG046_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG047_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG048_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG049_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG050_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG051_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define ENC0_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC0_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define ENC1_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define EXTTRIG_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PIO0_13_PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PWM0_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ADC1_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define AOI0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI0_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define AOI1_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CT_INP1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG023_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG024_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG025_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG026_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG027_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG028_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG029_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG030_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG031_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG032_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG033_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG034_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG035_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG036_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG037_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG038_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG039_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG040_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG041_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG042_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG043_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG044_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG045_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG046_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG047_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG048_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG049_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG050_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG051_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define ENC0_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC0_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define ENC1_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define EXTTRIG_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PIO0_14_PIO0_14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PWM0_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH3A_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define ADC1_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define CT_INP16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG023_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG024_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG025_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG026_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG027_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG028_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG029_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG030_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG031_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG032_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG033_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG034_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG035_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG036_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG037_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG038_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG039_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG040_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG041_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG042_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG043_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG044_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG045_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG046_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG047_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG048_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG049_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG050_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG051_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define PIO0_15_PIO0_15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ +#define ADC0_CH3B_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define ADC1_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define AOI0_OUT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 12) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define CT_INP4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG023_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG024_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG025_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG026_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG027_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG028_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG029_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG030_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG031_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG032_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG033_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG034_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG035_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG036_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG037_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG038_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG039_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG040_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG041_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG042_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG043_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG044_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG045_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG046_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG047_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG048_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG049_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG050_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG051_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define PIO0_16_PIO0_16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ +#define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define ADC1_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define AOI0_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define AOI1_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG023_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG024_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG025_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG026_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG027_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG028_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG029_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG030_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG031_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG032_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG033_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG034_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG035_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG036_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG037_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG038_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG039_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG040_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG041_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG042_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG043_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG044_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG045_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG046_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG047_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG048_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG049_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG050_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG051_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 1) /* PIO0_17 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 8) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define HSCMP1_OUT_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 13) /* PIO0_17 */ +#define HSCMP2_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define PIO0_17_PIO0_17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ +#define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define ADC1_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define AOI0_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define AOI1_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG023_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG024_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG025_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG026_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG027_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG028_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG029_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG030_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG031_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG032_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG033_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG034_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG035_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG036_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG037_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG038_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG039_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG040_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG041_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG042_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG043_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG044_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG045_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG046_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG047_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG048_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG049_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG050_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG051_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PIO0_18_PIO0_18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PWM1_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 11) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SWO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 8) /* PIO0_18 */ +#define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ADC1_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define AOI0_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI0_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define AOI1_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define AOI1_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG023_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG024_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG025_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG026_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG027_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG028_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG029_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG030_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG031_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG032_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG033_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG034_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG035_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG036_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG037_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG038_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG039_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG040_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG041_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG042_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG043_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG044_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG045_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG046_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG047_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG048_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG049_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG050_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG051_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define ENC0_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC0_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define ENC1_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define EXTTRIG_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define FLEXSPI0_SCLK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 5) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PIO0_19_PIO0_19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PWM0_B1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 11) /* PIO0_19 */ +#define PWM0_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define ADC1_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CT_INP15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG023_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG024_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG025_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG026_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG027_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG028_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG029_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG030_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG031_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG032_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG033_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG034_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG035_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG036_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG037_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG038_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG039_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG040_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG041_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG042_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG043_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG044_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG045_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG046_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG047_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG048_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG049_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG050_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG051_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PIO0_20_PIO0_20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PWM1_X2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 13) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ADC1_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define AOI0_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define AOI1_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG023_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG024_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG025_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG026_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG027_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG028_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG029_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG030_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG031_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG032_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG033_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG034_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG035_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG036_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG037_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG038_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG039_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG040_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG041_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG042_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG043_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG044_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG045_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG046_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG047_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG048_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG049_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG050_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG051_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define ENC0_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC0_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define ENC1_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define EXTTRIG_IN7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_CTS_SDA_SSEL0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define FLEXSPI0_SS0_N_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PIO0_21_PIO0_21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PWM0_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_B1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 11) /* PIO0_21 */ +#define PWM1_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_OUT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define ADC1_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define CT_INP8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG023_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG025_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG026_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG027_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG028_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG029_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG030_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG031_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG032_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG033_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG034_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG035_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG036_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG037_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG038_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG039_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG040_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG041_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG042_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG043_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG044_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG045_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG046_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG047_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG048_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG049_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG050_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG051_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define HSCMP0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define I3C0_SDA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 5) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PIO0_24_PIO0_24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ +#define PWM0_A1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 11) /* PIO0_24 */ +#define PWM0_X0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 13) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ +#define SWD_TRACEDATA0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 6) /* PIO0_24 */ +#define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define ADC1_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CT_INP14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG023_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG024_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG025_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG027_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG028_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG029_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG030_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG031_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG032_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG033_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG034_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG035_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG036_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG037_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG038_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG039_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG040_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG041_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG042_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG043_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG044_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG045_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG046_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG047_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG048_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG049_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG050_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG051_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PIO0_26_PIO0_26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PWM0_B1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 11) /* PIO0_26 */ +#define RTC_TAMPER2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define ADC0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define ADC1_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG023_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG024_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG025_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG026_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG028_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG029_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG030_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG031_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG032_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG033_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG034_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG035_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG036_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG037_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG038_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG039_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG040_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG041_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG042_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG043_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG044_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG045_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG046_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG047_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG048_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG049_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG050_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG051_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define OPAMP1_DP0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PIO0_27_PIO0_27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ADC1_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define AOI0_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI0_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define AOI1_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG023_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG024_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG025_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG026_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG027_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG028_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG030_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG031_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG032_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG033_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG034_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG035_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG036_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG037_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG038_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG039_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG040_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG041_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG042_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG043_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG044_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG045_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG046_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG047_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG048_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG049_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG050_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG051_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define ENC0_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC0_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define ENC1_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define EXTTRIG_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 6) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PIO0_29_PIO0_29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PWM0_A1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 11) /* PIO0_29 */ +#define PWM0_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ +#define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define ADC1_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define AOI1_OUT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 12) /* PIO0_30 */ +#define CAN0_TD_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 6) /* PIO0_30 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG023_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG024_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG025_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG026_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG027_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG028_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG029_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG031_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG032_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG033_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG034_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG035_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG036_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG037_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG038_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG039_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG040_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG041_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG042_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG043_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG044_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG045_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG046_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG047_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG048_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG049_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG050_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG051_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 9) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PIO0_30_PIO0_30_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PWM1_A1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 11) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ +#define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_CH0B_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define ADC1_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define AOI1_OUT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 12) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define CT_INP2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG023_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG024_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG025_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG026_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG027_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG028_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG029_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG030_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG031_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG032_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG033_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG034_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG035_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG036_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG037_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG038_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG039_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG040_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG041_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG042_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG043_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG044_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG045_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG046_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG047_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG048_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG049_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG050_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG051_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define PIO1_0_PIO1_0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ +#define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define ADC1_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CT_INP3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG023_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG024_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG025_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG026_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG027_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG028_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG029_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG030_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG031_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG032_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG033_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG034_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG035_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG036_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG037_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG038_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG039_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG040_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG041_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG042_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG043_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG044_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG045_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG046_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG047_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG048_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG049_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG050_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG051_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PIO1_1_PIO1_1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PWM0_B2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 11) /* PIO1_1 */ +#define RTC_ALARMOUT_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 10) /* PIO1_1 */ +#define RTC_TAMPER0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define TRACECLK_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ +#define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define ADC1_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define AOI0_OUT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 12) /* PIO1_2 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG023_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG024_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG025_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG026_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG027_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG028_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG029_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG030_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG031_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG032_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG033_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG034_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG035_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG036_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG037_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG038_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG039_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG040_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG041_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG042_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG043_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG044_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG045_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG046_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG047_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG048_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG049_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG050_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG051_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PIO1_2_PIO1_2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PWM0_B0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 11) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define ADC1_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG023_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG024_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG025_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG026_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG027_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG028_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG029_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG030_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG031_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG032_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG033_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG034_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG035_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG036_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG037_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG038_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG039_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG040_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG041_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG042_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG043_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG044_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG045_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG046_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG047_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG048_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG049_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG050_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG051_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PIO1_3_PIO1_3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PWM0_A3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 11) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ADC1_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CT_INP5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG023_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG024_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG025_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG026_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG027_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG028_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG029_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG030_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG031_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG032_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG033_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG034_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG035_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG036_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG037_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG038_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG039_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG040_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG041_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG042_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG043_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG044_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG045_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG046_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG047_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG048_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG049_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG050_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG051_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define ENC0_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC0_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define ENC1_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define EXTTRIG_IN8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define FC6_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 10) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define HS_SPI_SSEL0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PIO1_11_PIO1_11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PWM0_A0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 11) /* PIO1_11 */ +#define PWM0_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM0_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define PWM1_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ +#define AOI0_OUT2_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 12) /* PIO2_1 */ +#define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ +#define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ +#define I3C0_SDA_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 5) /* PIO2_1 */ +#define OPAMP2_DP0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S04JBD64-pinctrl.h b/dts/nxp/lpc/LPC55S04JBD64-pinctrl.h new file mode 100644 index 000000000..1c2a57a30 --- /dev/null +++ b/dts/nxp/lpc/LPC55S04JBD64-pinctrl.h @@ -0,0 +1,2691 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S04JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S04JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC55S04JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S04JHI48-pinctrl.h b/dts/nxp/lpc/LPC55S04JHI48-pinctrl.h new file mode 100644 index 000000000..f348fdb50 --- /dev/null +++ b/dts/nxp/lpc/LPC55S04JHI48-pinctrl.h @@ -0,0 +1,1849 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S04JHI48/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S04JHI48_ +#define _ZEPHYR_DTS_BINDING_LPC55S04JHI48_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S14JBD100-pinctrl.h b/dts/nxp/lpc/LPC55S14JBD100-pinctrl.h new file mode 100644 index 000000000..0dbcd22e2 --- /dev/null +++ b/dts/nxp/lpc/LPC55S14JBD100-pinctrl.h @@ -0,0 +1,3700 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S14JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S14JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC55S14JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 9) /* PIO1_22 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CAN0_TD_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 9) /* PIO1_27 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S14JBD64-pinctrl.h b/dts/nxp/lpc/LPC55S14JBD64-pinctrl.h new file mode 100644 index 000000000..409e19cc2 --- /dev/null +++ b/dts/nxp/lpc/LPC55S14JBD64-pinctrl.h @@ -0,0 +1,2239 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S14JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S14JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC55S14JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S14JEV59-pinctrl.h b/dts/nxp/lpc/LPC55S14JEV59-pinctrl.h new file mode 100644 index 000000000..a509d1804 --- /dev/null +++ b/dts/nxp/lpc/LPC55S14JEV59-pinctrl.h @@ -0,0 +1,2269 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S14JEV59/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S14JEV59_ +#define _ZEPHYR_DTS_BINDING_LPC55S14JEV59_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S16JEV59-pinctrl.h b/dts/nxp/lpc/LPC55S16JEV59-pinctrl.h new file mode 100644 index 000000000..4b596a43f --- /dev/null +++ b/dts/nxp/lpc/LPC55S16JEV59-pinctrl.h @@ -0,0 +1,2269 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S16JEV59/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S16JEV59_ +#define _ZEPHYR_DTS_BINDING_LPC55S16JEV59_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S26JBD100-pinctrl.h b/dts/nxp/lpc/LPC55S26JBD100-pinctrl.h new file mode 100644 index 000000000..8b65d3902 --- /dev/null +++ b/dts/nxp/lpc/LPC55S26JBD100-pinctrl.h @@ -0,0 +1,3734 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S26JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S26JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC55S26JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD0_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD0_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD0_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define SD0_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define SD0_CARD_DET_N_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 7) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define SD1_CMD_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 7) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define SDIF_SD1_D2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 7) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD0_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define SD1_CARD_DET_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 9) /* PIO1_17 */ +#define SD1_CARD_INT_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 7) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define SD1_POW_EN_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 1) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD0_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define SDIF_SD1_D3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 3) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define SDIF_SD1_D1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 3) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define SDIF_SD1_D0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 3) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define SDIF_SD0_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define SDIF_SD0_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define SD1_CLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 2) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S26JBD64-pinctrl.h b/dts/nxp/lpc/LPC55S26JBD64-pinctrl.h new file mode 100644 index 000000000..7c0eacf3c --- /dev/null +++ b/dts/nxp/lpc/LPC55S26JBD64-pinctrl.h @@ -0,0 +1,2254 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S26JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S26JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC55S26JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S26JEV98-pinctrl.h b/dts/nxp/lpc/LPC55S26JEV98-pinctrl.h new file mode 100644 index 000000000..1b171c793 --- /dev/null +++ b/dts/nxp/lpc/LPC55S26JEV98-pinctrl.h @@ -0,0 +1,3734 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S26JEV98/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S26JEV98_ +#define _ZEPHYR_DTS_BINDING_LPC55S26JEV98_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD0_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD0_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD0_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define SD0_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define SD0_CARD_DET_N_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 7) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define SD1_CMD_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 7) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define SDIF_SD1_D2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 7) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD0_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define SD1_CARD_DET_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 9) /* PIO1_17 */ +#define SD1_CARD_INT_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 7) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define SD1_POW_EN_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 1) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD0_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define SDIF_SD1_D3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 3) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define SDIF_SD1_D1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 3) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define SDIF_SD1_D0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 3) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define SDIF_SD0_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define SDIF_SD0_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define SD1_CLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 2) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S28JEV59-pinctrl.h b/dts/nxp/lpc/LPC55S28JEV59-pinctrl.h new file mode 100644 index 000000000..d9b603cad --- /dev/null +++ b/dts/nxp/lpc/LPC55S28JEV59-pinctrl.h @@ -0,0 +1,2285 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S28JEV59/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S28JEV59_ +#define _ZEPHYR_DTS_BINDING_LPC55S28JEV59_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S66JBD100-pinctrl.h b/dts/nxp/lpc/LPC55S66JBD100-pinctrl.h new file mode 100644 index 000000000..491a5363b --- /dev/null +++ b/dts/nxp/lpc/LPC55S66JBD100-pinctrl.h @@ -0,0 +1,3734 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S66JBD100/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S66JBD100_ +#define _ZEPHYR_DTS_BINDING_LPC55S66JBD100_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD0_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD0_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD0_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define SD0_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define SD0_CARD_DET_N_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 7) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define SD1_CMD_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 7) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define SDIF_SD1_D2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 7) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD0_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define SD1_CARD_DET_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 9) /* PIO1_17 */ +#define SD1_CARD_INT_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 7) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define SD1_POW_EN_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 1) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD0_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define SDIF_SD1_D3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 3) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define SDIF_SD1_D1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 3) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define SDIF_SD1_D0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 3) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define SDIF_SD0_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define SDIF_SD0_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define SD1_CLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 2) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S66JBD64-pinctrl.h b/dts/nxp/lpc/LPC55S66JBD64-pinctrl.h new file mode 100644 index 000000000..0a2ae9dfd --- /dev/null +++ b/dts/nxp/lpc/LPC55S66JBD64-pinctrl.h @@ -0,0 +1,2254 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S66JBD64/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S66JBD64_ +#define _ZEPHYR_DTS_BINDING_LPC55S66JBD64_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S66JEV98-pinctrl.h b/dts/nxp/lpc/LPC55S66JEV98-pinctrl.h new file mode 100644 index 000000000..43b553be2 --- /dev/null +++ b/dts/nxp/lpc/LPC55S66JEV98-pinctrl.h @@ -0,0 +1,3734 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S66JEV98/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S66JEV98_ +#define _ZEPHYR_DTS_BINDING_LPC55S66JEV98_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ +#define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ +#define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ +#define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ +#define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ +#define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ +#define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ +#define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 4) /* PIO1_5 */ +#define SDIF_SD0_D2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ +#define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ +#define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */ +#define SDIF_SD0_D3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ +#define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ +#define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */ +#define SDIF_SD0_D1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 1) /* PIO1_8 */ +#define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 5) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 0) /* PIO1_8 */ +#define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 4) /* PIO1_8 */ +#define SD0_CLK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_A, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */ +#define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */ +#define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */ +#define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */ +#define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_10 */ +#define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_10 */ +#define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_D, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ +#define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ +#define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */ +#define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_12 */ +#define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 5) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_12 */ +#define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_D, 4) /* PIO1_12 */ +#define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_13 */ +#define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_13 */ +#define SD0_CARD_DET_N_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 7) /* PIO1_13 */ +#define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 5) /* PIO1_13 */ +#define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_D, 4) /* PIO1_13 */ +#define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */ +#define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */ +#define SD1_CMD_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 7) /* PIO1_14 */ +#define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */ +#define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */ +#define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */ +#define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */ +#define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */ +#define SDIF_SD1_D2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 7) /* PIO1_15 */ +#define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */ +#define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */ +#define SD0_CMD_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 4) /* PIO1_16 */ +#define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */ +#define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */ +#define SD1_CARD_DET_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 9) /* PIO1_17 */ +#define SD1_CARD_INT_N_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 7) /* PIO1_17 */ +#define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */ +#define PLU_OUT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 7) /* PIO1_18 */ +#define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */ +#define SD1_POW_EN_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 1) /* PIO1_18 */ +#define ACMPVREF_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 3) /* PIO1_19 */ +#define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 5) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 0) /* PIO1_19 */ +#define PLU_OUT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 7) /* PIO1_19 */ +#define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 4) /* PIO1_19 */ +#define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_A, 2) /* PIO1_19 */ +#define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_20 */ +#define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 5) /* PIO1_20 */ +#define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_20 */ +#define PLU_OUT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_D, 7) /* PIO1_20 */ +#define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */ +#define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */ +#define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */ +#define PLU_OUT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 7) /* PIO1_21 */ +#define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 5) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_22 */ +#define PLU_OUT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 7) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 4) /* PIO1_22 */ +#define SD0_CMD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_22 */ +#define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 1) /* PIO1_23 */ +#define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 5) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_23 */ +#define PLU_OUT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 7) /* PIO1_23 */ +#define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 2) /* PIO1_23 */ +#define SDIF_SD1_D3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_D, 3) /* PIO1_23 */ +#define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 1) /* PIO1_24 */ +#define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 5) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 0) /* PIO1_24 */ +#define PLU_OUT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 7) /* PIO1_24 */ +#define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 2) /* PIO1_24 */ +#define SDIF_SD1_D1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_D, 3) /* PIO1_24 */ +#define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */ +#define PLU_CLKIN_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 7) /* PIO1_25 */ +#define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */ +#define SDIF_SD1_D0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 3) /* PIO1_25 */ +#define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */ +#define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */ +#define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */ +#define PLU_INPUT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 7) /* PIO1_26 */ +#define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */ +#define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */ +#define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */ +#define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */ +#define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */ +#define PLU_INPUT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 7) /* PIO1_27 */ +#define SDIF_SD0_D4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 2) /* PIO1_27 */ +#define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */ +#define PLU_INPUT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 7) /* PIO1_28 */ +#define SDIF_SD0_D5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 2) /* PIO1_28 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ +#define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */ +#define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */ +#define PLU_INPUT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */ +#define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */ +#define SD1_CLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 2) /* PIO1_31 */ + +#endif diff --git a/dts/nxp/lpc/LPC55S69JEV59-pinctrl.h b/dts/nxp/lpc/LPC55S69JEV59-pinctrl.h new file mode 100644 index 000000000..f7ea01eb1 --- /dev/null +++ b/dts/nxp/lpc/LPC55S69JEV59-pinctrl.h @@ -0,0 +1,2285 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from LPC55S69JEV59/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_LPC55S69JEV59_ +#define _ZEPHYR_DTS_BINDING_LPC55S69JEV59_ + +#define IOCON_MUX(offset, type, mux) \ + (((offset & 0xFFF) << 20) | \ + (((type) & 0x3) << 18) | \ + (((mux) & 0xF) << 0)) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +#define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ +#define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ +#define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ +#define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ +#define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ +#define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ +#define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ +#define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ +#define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ +#define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ +#define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ +#define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ +#define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ +#define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ +#define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ +#define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ +#define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ +#define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ +#define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ +#define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ +#define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ +#define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ +#define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ +#define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ +#define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ +#define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ +#define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ +#define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ +#define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ +#define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ +#define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ +#define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ +#define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ +#define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ +#define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ +#define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ +#define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ +#define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ +#define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ +#define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ +#define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ +#define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ +#define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ +#define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ +#define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ +#define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ +#define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ +#define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ +#define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ +#define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ +#define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ +#define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ +#define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ +#define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ +#define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ +#define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ +#define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ +#define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ +#define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ +#define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ +#define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ +#define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ +#define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ +#define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ +#define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ +#define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ +#define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ +#define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ +#define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ +#define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ +#define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ +#define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ +#define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ +#define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ +#define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ +#define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ +#define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ +#define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ +#define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ +#define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ +#define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ +#define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ +#define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ +#define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ +#define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ +#define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ +#define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ +#define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ +#define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ +#define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ +#define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ +#define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ +#define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ +#define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ +#define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ +#define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ +#define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ +#define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ +#define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ +#define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ +#define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ +#define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ +#define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ +#define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ +#define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ +#define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ +#define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ +#define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ +#define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ +#define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ +#define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ +#define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ +#define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ +#define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ +#define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ +#define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ +#define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ +#define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ +#define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ +#define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ +#define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ +#define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ +#define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ +#define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ +#define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ +#define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ +#define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ +#define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ +#define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ +#define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ +#define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ +#define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ +#define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ +#define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ +#define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ +#define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ +#define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ +#define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */ +#define SDIF_SD0_D0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ +#define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ +#define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */ +#define PLU_INPUT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 7) /* PIO1_29 */ +#define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */ +#define SDIF_SD0_D6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 2) /* PIO1_29 */ +#define USB1_FRAME_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 5) /* PIO1_29 */ +#define USB1_PORTPWRN_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 4) /* PIO1_29 */ +#define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */ +#define PLU_INPUT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 7) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */ +#define SDIF_SD0_D7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 2) /* PIO1_30 */ +#define USB1_LEDN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 5) /* PIO1_30 */ +#define USB1_OVERCURRENTN_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 4) /* PIO1_30 */ + +#endif diff --git a/dts/nxp/mcx/MCXA142VFM-pinctrl.h b/dts/nxp/mcx/MCXA142VFM-pinctrl.h new file mode 100644 index 000000000..f15f8dc6d --- /dev/null +++ b/dts/nxp/mcx/MCXA142VFM-pinctrl.h @@ -0,0 +1,188 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA142VFM/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA142VFM_ +#define _ZEPHYR_DTS_BINDING_MCXA142VFM_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#endif diff --git a/dts/nxp/mcx/MCXA142VFT-pinctrl.h b/dts/nxp/mcx/MCXA142VFT-pinctrl.h new file mode 100644 index 000000000..cea034d6e --- /dev/null +++ b/dts/nxp/mcx/MCXA142VFT-pinctrl.h @@ -0,0 +1,272 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA142VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA142VFT_ +#define _ZEPHYR_DTS_BINDING_MCXA142VFT_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define ADC0_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define ADC0_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA142VLF-pinctrl.h b/dts/nxp/mcx/MCXA142VLF-pinctrl.h new file mode 100644 index 000000000..b35a3d287 --- /dev/null +++ b/dts/nxp/mcx/MCXA142VLF-pinctrl.h @@ -0,0 +1,254 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA142VLF/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA142VLF_ +#define _ZEPHYR_DTS_BINDING_MCXA142VLF_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA142VLH-pinctrl.h b/dts/nxp/mcx/MCXA142VLH-pinctrl.h new file mode 100644 index 000000000..aa60f7244 --- /dev/null +++ b/dts/nxp/mcx/MCXA142VLH-pinctrl.h @@ -0,0 +1,327 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA142VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA142VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA142VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define ADC0_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define ADC0_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define ADC0_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define ADC0_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA143VFM-pinctrl.h b/dts/nxp/mcx/MCXA143VFM-pinctrl.h new file mode 100644 index 000000000..c7803ac9d --- /dev/null +++ b/dts/nxp/mcx/MCXA143VFM-pinctrl.h @@ -0,0 +1,188 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA143VFM/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA143VFM_ +#define _ZEPHYR_DTS_BINDING_MCXA143VFM_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#endif diff --git a/dts/nxp/mcx/MCXA143VFT-pinctrl.h b/dts/nxp/mcx/MCXA143VFT-pinctrl.h new file mode 100644 index 000000000..88dd06c5f --- /dev/null +++ b/dts/nxp/mcx/MCXA143VFT-pinctrl.h @@ -0,0 +1,272 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA143VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA143VFT_ +#define _ZEPHYR_DTS_BINDING_MCXA143VFT_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC0_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC0_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA143VLF-pinctrl.h b/dts/nxp/mcx/MCXA143VLF-pinctrl.h new file mode 100644 index 000000000..ffd2381cf --- /dev/null +++ b/dts/nxp/mcx/MCXA143VLF-pinctrl.h @@ -0,0 +1,254 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA143VLF/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA143VLF_ +#define _ZEPHYR_DTS_BINDING_MCXA143VLF_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA143VLH-pinctrl.h b/dts/nxp/mcx/MCXA143VLH-pinctrl.h new file mode 100644 index 000000000..592e5832f --- /dev/null +++ b/dts/nxp/mcx/MCXA143VLH-pinctrl.h @@ -0,0 +1,327 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA143VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA143VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA143VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC0_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC0_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define ADC0_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define ADC0_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA144VFT-pinctrl.h b/dts/nxp/mcx/MCXA144VFT-pinctrl.h new file mode 100644 index 000000000..86992eaf4 --- /dev/null +++ b/dts/nxp/mcx/MCXA144VFT-pinctrl.h @@ -0,0 +1,349 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA144VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA144VFT_ +#define _ZEPHYR_DTS_BINDING_MCXA144VFT_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA144VLH-pinctrl.h b/dts/nxp/mcx/MCXA144VLH-pinctrl.h new file mode 100644 index 000000000..d9da340c1 --- /dev/null +++ b/dts/nxp/mcx/MCXA144VLH-pinctrl.h @@ -0,0 +1,432 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA144VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA144VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA144VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA144VLL-pinctrl.h b/dts/nxp/mcx/MCXA144VLL-pinctrl.h new file mode 100644 index 000000000..eef51872e --- /dev/null +++ b/dts/nxp/mcx/MCXA144VLL-pinctrl.h @@ -0,0 +1,601 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA144VLL/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA144VLL_ +#define _ZEPHYR_DTS_BINDING_MCXA144VLL_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_P0_18 A15X_MUX('0',18,6) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_P0_19 A15X_MUX('0',19,6) /* PT0_19 */ +#define WUU0_IN31_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_P0_20 A15X_MUX('0',20,6) /* PT0_20 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_P0_21 A15X_MUX('0',21,6) /* PT0_21 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define FLEXIO0_D6_P0_22 A15X_MUX('0',22,6) /* PT0_22 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define FLEXIO0_D7_P0_23 A15X_MUX('0',23,6) /* PT0_23 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_P1_14 A15X_MUX('1',14,4) /* PT1_14 */ +#define CT3_MAT0_P1_14 A15X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_P1_14 A15X_MUX('1',14,6) /* PT1_14 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_P1_15 A15X_MUX('1',15,4) /* PT1_15 */ +#define CT3_MAT1_P1_15 A15X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_P1_15 A15X_MUX('1',15,6) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define CT3_MAT2_P2_10 A15X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_P2_10 A15X_MUX('2',10,6) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define CT3_MAT3_P2_11 A15X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_P2_11 A15X_MUX('2',11,6) /* PT2_11 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT3_MAT0_P2_16 A15X_MUX('2',16,4) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define FLEXIO0_D24_P2_16 A15X_MUX('2',16,6) /* PT2_16 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT3_MAT1_P2_17 A15X_MUX('2',17,4) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define FLEXIO0_D25_P2_17 A15X_MUX('2',17,6) /* PT2_17 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define CT3_MAT3_P2_19 A15X_MUX('2',19,4) /* PT2_19 */ +#define FLEXIO0_D27_P2_19 A15X_MUX('2',19,6) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define FLEXIO0_D28_P2_20 A15X_MUX('2',20,6) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define FLEXIO0_D29_P2_21 A15X_MUX('2',21,6) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define FLEXIO0_D31_P2_23 A15X_MUX('2',23,6) /* PT2_23 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define LPUART4_RTS_B_P3_16 A15X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_P3_16 A15X_MUX('3',16,6) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define LPUART4_CTS_B_P3_17 A15X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_P3_17 A15X_MUX('3',17,6) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define LPUART4_RXD_P3_18 A15X_MUX('3',18,2) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_P3_18 A15X_MUX('3',18,6) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define LPUART4_TXD_P3_19 A15X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_P3_19 A15X_MUX('3',19,6) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPI2C3_SDA_P3_20 A15X_MUX('3',20,2) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_P3_20 A15X_MUX('3',20,6) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPI2C3_SCL_P3_21 A15X_MUX('3',21,2) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_P3_21 A15X_MUX('3',21,6) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_P3_22 A15X_MUX('3',22,6) /* PT3_22 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPI2C2_SDAS_P4_2 A15X_MUX('4',2,2) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define CT4_MAT0_P4_2 A15X_MUX('4',2,4) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define FLEXIO0_D10_P4_2 A15X_MUX('4',2,6) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define LPI2C2_SCL_P4_3 A15X_MUX('4',3,2) /* PT4_3 */ +#define LPUART4_TXD_P4_3 A15X_MUX('4',3,3) /* PT4_3 */ +#define CT4_MAT1_P4_3 A15X_MUX('4',3,4) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define FLEXIO0_D11_P4_3 A15X_MUX('4',3,6) /* PT4_3 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define LPI2C2_SDA_P4_4 A15X_MUX('4',4,2) /* PT4_4 */ +#define LPUART4_RXD_P4_4 A15X_MUX('4',4,3) /* PT4_4 */ +#define CT4_MAT2_P4_4 A15X_MUX('4',4,4) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define FLEXIO0_D12_P4_4 A15X_MUX('4',4,6) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPI2C2_SCLS_P4_5 A15X_MUX('4',5,2) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define CT4_MAT3_P4_5 A15X_MUX('4',5,4) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define FLEXIO0_D13_P4_5 A15X_MUX('4',5,6) /* PT4_5 */ +#define WUU0_IN17_P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPI2C2_HREQ_P4_6 A15X_MUX('4',6,2) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define FLEXIO0_D14_P4_6 A15X_MUX('4',6,6) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define FLEXIO0_D15_P4_7 A15X_MUX('4',7,6) /* PT4_7 */ +#endif diff --git a/dts/nxp/mcx/MCXA144VMP-pinctrl.h b/dts/nxp/mcx/MCXA144VMP-pinctrl.h new file mode 100644 index 000000000..e3977507b --- /dev/null +++ b/dts/nxp/mcx/MCXA144VMP-pinctrl.h @@ -0,0 +1,416 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA144VMP/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA144VMP_ +#define _ZEPHYR_DTS_BINDING_MCXA144VMP_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA144VPJ-pinctrl.h b/dts/nxp/mcx/MCXA144VPJ-pinctrl.h new file mode 100644 index 000000000..932cfbfff --- /dev/null +++ b/dts/nxp/mcx/MCXA144VPJ-pinctrl.h @@ -0,0 +1,605 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA144VPJ/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA144VPJ_ +#define _ZEPHYR_DTS_BINDING_MCXA144VPJ_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_P0_18 A15X_MUX('0',18,6) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_P0_19 A15X_MUX('0',19,6) /* PT0_19 */ +#define WUU0_IN31_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_P0_20 A15X_MUX('0',20,6) /* PT0_20 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_P0_21 A15X_MUX('0',21,6) /* PT0_21 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define FLEXIO0_D6_P0_22 A15X_MUX('0',22,6) /* PT0_22 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define FLEXIO0_D7_P0_23 A15X_MUX('0',23,6) /* PT0_23 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_P1_14 A15X_MUX('1',14,4) /* PT1_14 */ +#define CT3_MAT0_P1_14 A15X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_P1_14 A15X_MUX('1',14,6) /* PT1_14 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_P1_15 A15X_MUX('1',15,4) /* PT1_15 */ +#define CT3_MAT1_P1_15 A15X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_P1_15 A15X_MUX('1',15,6) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define CT3_MAT2_P2_10 A15X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_P2_10 A15X_MUX('2',10,6) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define CT3_MAT3_P2_11 A15X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_P2_11 A15X_MUX('2',11,6) /* PT2_11 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT3_MAT0_P2_16 A15X_MUX('2',16,4) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define FLEXIO0_D24_P2_16 A15X_MUX('2',16,6) /* PT2_16 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT3_MAT1_P2_17 A15X_MUX('2',17,4) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define FLEXIO0_D25_P2_17 A15X_MUX('2',17,6) /* PT2_17 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define CT3_MAT3_P2_19 A15X_MUX('2',19,4) /* PT2_19 */ +#define FLEXIO0_D27_P2_19 A15X_MUX('2',19,6) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define FLEXIO0_D28_P2_20 A15X_MUX('2',20,6) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define FLEXIO0_D29_P2_21 A15X_MUX('2',21,6) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define FLEXIO0_D31_P2_23 A15X_MUX('2',23,6) /* PT2_23 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_2 A15X_MUX('3',2,0) /* PT3_2 */ +#define LPSPI1_PCS1_P3_2 A15X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_P3_2 A15X_MUX('3',2,4) /* PT3_2 */ +#define FLEXIO0_D10_P3_2 A15X_MUX('3',2,6) /* PT3_2 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define LPUART4_RTS_B_P3_16 A15X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_P3_16 A15X_MUX('3',16,6) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define LPUART4_CTS_B_P3_17 A15X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_P3_17 A15X_MUX('3',17,6) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define LPUART4_RXD_P3_18 A15X_MUX('3',18,2) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_P3_18 A15X_MUX('3',18,6) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define LPUART4_TXD_P3_19 A15X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_P3_19 A15X_MUX('3',19,6) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPI2C3_SDA_P3_20 A15X_MUX('3',20,2) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_P3_20 A15X_MUX('3',20,6) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPI2C3_SCL_P3_21 A15X_MUX('3',21,2) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_P3_21 A15X_MUX('3',21,6) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_P3_22 A15X_MUX('3',22,6) /* PT3_22 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPI2C2_SDAS_P4_2 A15X_MUX('4',2,2) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define CT4_MAT0_P4_2 A15X_MUX('4',2,4) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define FLEXIO0_D10_P4_2 A15X_MUX('4',2,6) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define LPI2C2_SCL_P4_3 A15X_MUX('4',3,2) /* PT4_3 */ +#define LPUART4_TXD_P4_3 A15X_MUX('4',3,3) /* PT4_3 */ +#define CT4_MAT1_P4_3 A15X_MUX('4',3,4) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define FLEXIO0_D11_P4_3 A15X_MUX('4',3,6) /* PT4_3 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define LPI2C2_SDA_P4_4 A15X_MUX('4',4,2) /* PT4_4 */ +#define LPUART4_RXD_P4_4 A15X_MUX('4',4,3) /* PT4_4 */ +#define CT4_MAT2_P4_4 A15X_MUX('4',4,4) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define FLEXIO0_D12_P4_4 A15X_MUX('4',4,6) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPI2C2_SCLS_P4_5 A15X_MUX('4',5,2) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define CT4_MAT3_P4_5 A15X_MUX('4',5,4) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define FLEXIO0_D13_P4_5 A15X_MUX('4',5,6) /* PT4_5 */ +#define WUU0_IN17_P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPI2C2_HREQ_P4_6 A15X_MUX('4',6,2) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define FLEXIO0_D14_P4_6 A15X_MUX('4',6,6) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define FLEXIO0_D15_P4_7 A15X_MUX('4',7,6) /* PT4_7 */ +#endif diff --git a/dts/nxp/mcx/MCXA145VFT-pinctrl.h b/dts/nxp/mcx/MCXA145VFT-pinctrl.h new file mode 100644 index 000000000..49a059256 --- /dev/null +++ b/dts/nxp/mcx/MCXA145VFT-pinctrl.h @@ -0,0 +1,349 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA145VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA145VFT_ +#define _ZEPHYR_DTS_BINDING_MCXA145VFT_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA145VLH-pinctrl.h b/dts/nxp/mcx/MCXA145VLH-pinctrl.h new file mode 100644 index 000000000..cdbf2f8eb --- /dev/null +++ b/dts/nxp/mcx/MCXA145VLH-pinctrl.h @@ -0,0 +1,432 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA145VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA145VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA145VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA145VLL-pinctrl.h b/dts/nxp/mcx/MCXA145VLL-pinctrl.h new file mode 100644 index 000000000..82149acb9 --- /dev/null +++ b/dts/nxp/mcx/MCXA145VLL-pinctrl.h @@ -0,0 +1,601 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA145VLL/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA145VLL_ +#define _ZEPHYR_DTS_BINDING_MCXA145VLL_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_P0_18 A15X_MUX('0',18,6) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_P0_19 A15X_MUX('0',19,6) /* PT0_19 */ +#define WUU0_IN31_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_P0_20 A15X_MUX('0',20,6) /* PT0_20 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_P0_21 A15X_MUX('0',21,6) /* PT0_21 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define FLEXIO0_D6_P0_22 A15X_MUX('0',22,6) /* PT0_22 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define FLEXIO0_D7_P0_23 A15X_MUX('0',23,6) /* PT0_23 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_P1_14 A15X_MUX('1',14,4) /* PT1_14 */ +#define CT3_MAT0_P1_14 A15X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_P1_14 A15X_MUX('1',14,6) /* PT1_14 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_P1_15 A15X_MUX('1',15,4) /* PT1_15 */ +#define CT3_MAT1_P1_15 A15X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_P1_15 A15X_MUX('1',15,6) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define CT3_MAT2_P2_10 A15X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_P2_10 A15X_MUX('2',10,6) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define CT3_MAT3_P2_11 A15X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_P2_11 A15X_MUX('2',11,6) /* PT2_11 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT3_MAT0_P2_16 A15X_MUX('2',16,4) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define FLEXIO0_D24_P2_16 A15X_MUX('2',16,6) /* PT2_16 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT3_MAT1_P2_17 A15X_MUX('2',17,4) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define FLEXIO0_D25_P2_17 A15X_MUX('2',17,6) /* PT2_17 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define CT3_MAT3_P2_19 A15X_MUX('2',19,4) /* PT2_19 */ +#define FLEXIO0_D27_P2_19 A15X_MUX('2',19,6) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define FLEXIO0_D28_P2_20 A15X_MUX('2',20,6) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define FLEXIO0_D29_P2_21 A15X_MUX('2',21,6) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define FLEXIO0_D31_P2_23 A15X_MUX('2',23,6) /* PT2_23 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define LPUART4_RTS_B_P3_16 A15X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_P3_16 A15X_MUX('3',16,6) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define LPUART4_CTS_B_P3_17 A15X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_P3_17 A15X_MUX('3',17,6) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define LPUART4_RXD_P3_18 A15X_MUX('3',18,2) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_P3_18 A15X_MUX('3',18,6) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define LPUART4_TXD_P3_19 A15X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_P3_19 A15X_MUX('3',19,6) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPI2C3_SDA_P3_20 A15X_MUX('3',20,2) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_P3_20 A15X_MUX('3',20,6) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPI2C3_SCL_P3_21 A15X_MUX('3',21,2) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_P3_21 A15X_MUX('3',21,6) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_P3_22 A15X_MUX('3',22,6) /* PT3_22 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPI2C2_SDAS_P4_2 A15X_MUX('4',2,2) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define CT4_MAT0_P4_2 A15X_MUX('4',2,4) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define FLEXIO0_D10_P4_2 A15X_MUX('4',2,6) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define LPI2C2_SCL_P4_3 A15X_MUX('4',3,2) /* PT4_3 */ +#define LPUART4_TXD_P4_3 A15X_MUX('4',3,3) /* PT4_3 */ +#define CT4_MAT1_P4_3 A15X_MUX('4',3,4) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define FLEXIO0_D11_P4_3 A15X_MUX('4',3,6) /* PT4_3 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define LPI2C2_SDA_P4_4 A15X_MUX('4',4,2) /* PT4_4 */ +#define LPUART4_RXD_P4_4 A15X_MUX('4',4,3) /* PT4_4 */ +#define CT4_MAT2_P4_4 A15X_MUX('4',4,4) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define FLEXIO0_D12_P4_4 A15X_MUX('4',4,6) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPI2C2_SCLS_P4_5 A15X_MUX('4',5,2) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define CT4_MAT3_P4_5 A15X_MUX('4',5,4) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define FLEXIO0_D13_P4_5 A15X_MUX('4',5,6) /* PT4_5 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define WUU0_IN17_P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPI2C2_HREQ_P4_6 A15X_MUX('4',6,2) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define FLEXIO0_D14_P4_6 A15X_MUX('4',6,6) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define FLEXIO0_D15_P4_7 A15X_MUX('4',7,6) /* PT4_7 */ +#endif diff --git a/dts/nxp/mcx/MCXA145VMP-pinctrl.h b/dts/nxp/mcx/MCXA145VMP-pinctrl.h new file mode 100644 index 000000000..7518eb1ba --- /dev/null +++ b/dts/nxp/mcx/MCXA145VMP-pinctrl.h @@ -0,0 +1,416 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA145VMP/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA145VMP_ +#define _ZEPHYR_DTS_BINDING_MCXA145VMP_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA145VPJ-pinctrl.h b/dts/nxp/mcx/MCXA145VPJ-pinctrl.h new file mode 100644 index 000000000..b2c2f2fd8 --- /dev/null +++ b/dts/nxp/mcx/MCXA145VPJ-pinctrl.h @@ -0,0 +1,605 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA145VPJ/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA145VPJ_ +#define _ZEPHYR_DTS_BINDING_MCXA145VPJ_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_P0_18 A15X_MUX('0',18,6) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_P0_19 A15X_MUX('0',19,6) /* PT0_19 */ +#define WUU0_IN31_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_P0_20 A15X_MUX('0',20,6) /* PT0_20 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_P0_21 A15X_MUX('0',21,6) /* PT0_21 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define FLEXIO0_D6_P0_22 A15X_MUX('0',22,6) /* PT0_22 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define FLEXIO0_D7_P0_23 A15X_MUX('0',23,6) /* PT0_23 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_P1_14 A15X_MUX('1',14,4) /* PT1_14 */ +#define CT3_MAT0_P1_14 A15X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_P1_14 A15X_MUX('1',14,6) /* PT1_14 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_P1_15 A15X_MUX('1',15,4) /* PT1_15 */ +#define CT3_MAT1_P1_15 A15X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_P1_15 A15X_MUX('1',15,6) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define CT3_MAT2_P2_10 A15X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_P2_10 A15X_MUX('2',10,6) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define CT3_MAT3_P2_11 A15X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_P2_11 A15X_MUX('2',11,6) /* PT2_11 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT3_MAT0_P2_16 A15X_MUX('2',16,4) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define FLEXIO0_D24_P2_16 A15X_MUX('2',16,6) /* PT2_16 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT3_MAT1_P2_17 A15X_MUX('2',17,4) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define FLEXIO0_D25_P2_17 A15X_MUX('2',17,6) /* PT2_17 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define CT3_MAT3_P2_19 A15X_MUX('2',19,4) /* PT2_19 */ +#define FLEXIO0_D27_P2_19 A15X_MUX('2',19,6) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define FLEXIO0_D28_P2_20 A15X_MUX('2',20,6) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define FLEXIO0_D29_P2_21 A15X_MUX('2',21,6) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define FLEXIO0_D31_P2_23 A15X_MUX('2',23,6) /* PT2_23 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_2 A15X_MUX('3',2,0) /* PT3_2 */ +#define LPSPI1_PCS1_P3_2 A15X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_P3_2 A15X_MUX('3',2,4) /* PT3_2 */ +#define FLEXIO0_D10_P3_2 A15X_MUX('3',2,6) /* PT3_2 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define LPUART4_RTS_B_P3_16 A15X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_P3_16 A15X_MUX('3',16,6) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define LPUART4_CTS_B_P3_17 A15X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_P3_17 A15X_MUX('3',17,6) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define LPUART4_RXD_P3_18 A15X_MUX('3',18,2) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_P3_18 A15X_MUX('3',18,6) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define LPUART4_TXD_P3_19 A15X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_P3_19 A15X_MUX('3',19,6) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPI2C3_SDA_P3_20 A15X_MUX('3',20,2) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_P3_20 A15X_MUX('3',20,6) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPI2C3_SCL_P3_21 A15X_MUX('3',21,2) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_P3_21 A15X_MUX('3',21,6) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_P3_22 A15X_MUX('3',22,6) /* PT3_22 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPI2C2_SDAS_P4_2 A15X_MUX('4',2,2) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define CT4_MAT0_P4_2 A15X_MUX('4',2,4) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define FLEXIO0_D10_P4_2 A15X_MUX('4',2,6) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define LPI2C2_SCL_P4_3 A15X_MUX('4',3,2) /* PT4_3 */ +#define LPUART4_TXD_P4_3 A15X_MUX('4',3,3) /* PT4_3 */ +#define CT4_MAT1_P4_3 A15X_MUX('4',3,4) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define FLEXIO0_D11_P4_3 A15X_MUX('4',3,6) /* PT4_3 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define LPI2C2_SDA_P4_4 A15X_MUX('4',4,2) /* PT4_4 */ +#define LPUART4_RXD_P4_4 A15X_MUX('4',4,3) /* PT4_4 */ +#define CT4_MAT2_P4_4 A15X_MUX('4',4,4) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define FLEXIO0_D12_P4_4 A15X_MUX('4',4,6) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPI2C2_SCLS_P4_5 A15X_MUX('4',5,2) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define CT4_MAT3_P4_5 A15X_MUX('4',5,4) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define FLEXIO0_D13_P4_5 A15X_MUX('4',5,6) /* PT4_5 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define WUU0_IN17_P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPI2C2_HREQ_P4_6 A15X_MUX('4',6,2) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define FLEXIO0_D14_P4_6 A15X_MUX('4',6,6) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define FLEXIO0_D15_P4_7 A15X_MUX('4',7,6) /* PT4_7 */ +#endif diff --git a/dts/nxp/mcx/MCXA146VFT-pinctrl.h b/dts/nxp/mcx/MCXA146VFT-pinctrl.h new file mode 100644 index 000000000..11cda9684 --- /dev/null +++ b/dts/nxp/mcx/MCXA146VFT-pinctrl.h @@ -0,0 +1,349 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA146VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA146VFT_ +#define _ZEPHYR_DTS_BINDING_MCXA146VFT_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA146VLH-pinctrl.h b/dts/nxp/mcx/MCXA146VLH-pinctrl.h new file mode 100644 index 000000000..6eb7d60f2 --- /dev/null +++ b/dts/nxp/mcx/MCXA146VLH-pinctrl.h @@ -0,0 +1,432 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA146VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA146VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA146VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA146VLL-pinctrl.h b/dts/nxp/mcx/MCXA146VLL-pinctrl.h new file mode 100644 index 000000000..cf4197572 --- /dev/null +++ b/dts/nxp/mcx/MCXA146VLL-pinctrl.h @@ -0,0 +1,601 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA146VLL/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA146VLL_ +#define _ZEPHYR_DTS_BINDING_MCXA146VLL_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_P0_18 A15X_MUX('0',18,6) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_P0_19 A15X_MUX('0',19,6) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define WUU0_IN31_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_P0_20 A15X_MUX('0',20,6) /* PT0_20 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_P0_21 A15X_MUX('0',21,6) /* PT0_21 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define FLEXIO0_D6_P0_22 A15X_MUX('0',22,6) /* PT0_22 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define FLEXIO0_D7_P0_23 A15X_MUX('0',23,6) /* PT0_23 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_P1_14 A15X_MUX('1',14,4) /* PT1_14 */ +#define CT3_MAT0_P1_14 A15X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_P1_14 A15X_MUX('1',14,6) /* PT1_14 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_P1_15 A15X_MUX('1',15,4) /* PT1_15 */ +#define CT3_MAT1_P1_15 A15X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_P1_15 A15X_MUX('1',15,6) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define CT3_MAT2_P2_10 A15X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_P2_10 A15X_MUX('2',10,6) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define CT3_MAT3_P2_11 A15X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_P2_11 A15X_MUX('2',11,6) /* PT2_11 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT3_MAT0_P2_16 A15X_MUX('2',16,4) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define FLEXIO0_D24_P2_16 A15X_MUX('2',16,6) /* PT2_16 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT3_MAT1_P2_17 A15X_MUX('2',17,4) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define FLEXIO0_D25_P2_17 A15X_MUX('2',17,6) /* PT2_17 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define CT3_MAT3_P2_19 A15X_MUX('2',19,4) /* PT2_19 */ +#define FLEXIO0_D27_P2_19 A15X_MUX('2',19,6) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define FLEXIO0_D28_P2_20 A15X_MUX('2',20,6) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define FLEXIO0_D29_P2_21 A15X_MUX('2',21,6) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define FLEXIO0_D31_P2_23 A15X_MUX('2',23,6) /* PT2_23 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define LPUART4_RTS_B_P3_16 A15X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_P3_16 A15X_MUX('3',16,6) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define LPUART4_CTS_B_P3_17 A15X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_P3_17 A15X_MUX('3',17,6) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define LPUART4_RXD_P3_18 A15X_MUX('3',18,2) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_P3_18 A15X_MUX('3',18,6) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define LPUART4_TXD_P3_19 A15X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_P3_19 A15X_MUX('3',19,6) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPI2C3_SDA_P3_20 A15X_MUX('3',20,2) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_P3_20 A15X_MUX('3',20,6) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPI2C3_SCL_P3_21 A15X_MUX('3',21,2) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_P3_21 A15X_MUX('3',21,6) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_P3_22 A15X_MUX('3',22,6) /* PT3_22 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPI2C2_SDAS_P4_2 A15X_MUX('4',2,2) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define CT4_MAT0_P4_2 A15X_MUX('4',2,4) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define FLEXIO0_D10_P4_2 A15X_MUX('4',2,6) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define LPI2C2_SCL_P4_3 A15X_MUX('4',3,2) /* PT4_3 */ +#define LPUART4_TXD_P4_3 A15X_MUX('4',3,3) /* PT4_3 */ +#define CT4_MAT1_P4_3 A15X_MUX('4',3,4) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define FLEXIO0_D11_P4_3 A15X_MUX('4',3,6) /* PT4_3 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define LPI2C2_SDA_P4_4 A15X_MUX('4',4,2) /* PT4_4 */ +#define LPUART4_RXD_P4_4 A15X_MUX('4',4,3) /* PT4_4 */ +#define CT4_MAT2_P4_4 A15X_MUX('4',4,4) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define FLEXIO0_D12_P4_4 A15X_MUX('4',4,6) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPI2C2_SCLS_P4_5 A15X_MUX('4',5,2) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define CT4_MAT3_P4_5 A15X_MUX('4',5,4) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define FLEXIO0_D13_P4_5 A15X_MUX('4',5,6) /* PT4_5 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define WUU0_IN17_P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPI2C2_HREQ_P4_6 A15X_MUX('4',6,2) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define FLEXIO0_D14_P4_6 A15X_MUX('4',6,6) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define FLEXIO0_D15_P4_7 A15X_MUX('4',7,6) /* PT4_7 */ +#endif diff --git a/dts/nxp/mcx/MCXA146VMP-pinctrl.h b/dts/nxp/mcx/MCXA146VMP-pinctrl.h new file mode 100644 index 000000000..7e2483789 --- /dev/null +++ b/dts/nxp/mcx/MCXA146VMP-pinctrl.h @@ -0,0 +1,416 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA146VMP/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA146VMP_ +#define _ZEPHYR_DTS_BINDING_MCXA146VMP_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA146VPJ-pinctrl.h b/dts/nxp/mcx/MCXA146VPJ-pinctrl.h new file mode 100644 index 000000000..115ffd40b --- /dev/null +++ b/dts/nxp/mcx/MCXA146VPJ-pinctrl.h @@ -0,0 +1,605 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA146VPJ/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA146VPJ_ +#define _ZEPHYR_DTS_BINDING_MCXA146VPJ_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_P0_18 A15X_MUX('0',18,6) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_P0_19 A15X_MUX('0',19,6) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define WUU0_IN31_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_P0_20 A15X_MUX('0',20,6) /* PT0_20 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_P0_21 A15X_MUX('0',21,6) /* PT0_21 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define FLEXIO0_D6_P0_22 A15X_MUX('0',22,6) /* PT0_22 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define FLEXIO0_D7_P0_23 A15X_MUX('0',23,6) /* PT0_23 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_P1_14 A15X_MUX('1',14,4) /* PT1_14 */ +#define CT3_MAT0_P1_14 A15X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_P1_14 A15X_MUX('1',14,6) /* PT1_14 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_P1_15 A15X_MUX('1',15,4) /* PT1_15 */ +#define CT3_MAT1_P1_15 A15X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_P1_15 A15X_MUX('1',15,6) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define CT3_MAT2_P2_10 A15X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_P2_10 A15X_MUX('2',10,6) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define CT3_MAT3_P2_11 A15X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_P2_11 A15X_MUX('2',11,6) /* PT2_11 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT3_MAT0_P2_16 A15X_MUX('2',16,4) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define FLEXIO0_D24_P2_16 A15X_MUX('2',16,6) /* PT2_16 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT3_MAT1_P2_17 A15X_MUX('2',17,4) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define FLEXIO0_D25_P2_17 A15X_MUX('2',17,6) /* PT2_17 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define CT3_MAT3_P2_19 A15X_MUX('2',19,4) /* PT2_19 */ +#define FLEXIO0_D27_P2_19 A15X_MUX('2',19,6) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define FLEXIO0_D28_P2_20 A15X_MUX('2',20,6) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define FLEXIO0_D29_P2_21 A15X_MUX('2',21,6) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define FLEXIO0_D31_P2_23 A15X_MUX('2',23,6) /* PT2_23 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_2 A15X_MUX('3',2,0) /* PT3_2 */ +#define LPSPI1_PCS1_P3_2 A15X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_P3_2 A15X_MUX('3',2,4) /* PT3_2 */ +#define FLEXIO0_D10_P3_2 A15X_MUX('3',2,6) /* PT3_2 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define LPUART4_RTS_B_P3_16 A15X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_P3_16 A15X_MUX('3',16,6) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define LPUART4_CTS_B_P3_17 A15X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_P3_17 A15X_MUX('3',17,6) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define LPUART4_RXD_P3_18 A15X_MUX('3',18,2) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_P3_18 A15X_MUX('3',18,6) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define LPUART4_TXD_P3_19 A15X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_P3_19 A15X_MUX('3',19,6) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPI2C3_SDA_P3_20 A15X_MUX('3',20,2) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_P3_20 A15X_MUX('3',20,6) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPI2C3_SCL_P3_21 A15X_MUX('3',21,2) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_P3_21 A15X_MUX('3',21,6) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_P3_22 A15X_MUX('3',22,6) /* PT3_22 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPI2C2_SDAS_P4_2 A15X_MUX('4',2,2) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define CT4_MAT0_P4_2 A15X_MUX('4',2,4) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define FLEXIO0_D10_P4_2 A15X_MUX('4',2,6) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define LPI2C2_SCL_P4_3 A15X_MUX('4',3,2) /* PT4_3 */ +#define LPUART4_TXD_P4_3 A15X_MUX('4',3,3) /* PT4_3 */ +#define CT4_MAT1_P4_3 A15X_MUX('4',3,4) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define FLEXIO0_D11_P4_3 A15X_MUX('4',3,6) /* PT4_3 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define LPI2C2_SDA_P4_4 A15X_MUX('4',4,2) /* PT4_4 */ +#define LPUART4_RXD_P4_4 A15X_MUX('4',4,3) /* PT4_4 */ +#define CT4_MAT2_P4_4 A15X_MUX('4',4,4) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define FLEXIO0_D12_P4_4 A15X_MUX('4',4,6) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPI2C2_SCLS_P4_5 A15X_MUX('4',5,2) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define CT4_MAT3_P4_5 A15X_MUX('4',5,4) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define FLEXIO0_D13_P4_5 A15X_MUX('4',5,6) /* PT4_5 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define WUU0_IN17_P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPI2C2_HREQ_P4_6 A15X_MUX('4',6,2) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define FLEXIO0_D14_P4_6 A15X_MUX('4',6,6) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define FLEXIO0_D15_P4_7 A15X_MUX('4',7,6) /* PT4_7 */ +#endif diff --git a/dts/nxp/mcx/MCXA152VFM-pinctrl.h b/dts/nxp/mcx/MCXA152VFM-pinctrl.h new file mode 100644 index 000000000..e185980b1 --- /dev/null +++ b/dts/nxp/mcx/MCXA152VFM-pinctrl.h @@ -0,0 +1,188 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA152VFM/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA152VFM_ +#define _ZEPHYR_DTS_BINDING_MCXA152VFM_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#endif diff --git a/dts/nxp/mcx/MCXA152VFT-pinctrl.h b/dts/nxp/mcx/MCXA152VFT-pinctrl.h new file mode 100644 index 000000000..8bf76ac49 --- /dev/null +++ b/dts/nxp/mcx/MCXA152VFT-pinctrl.h @@ -0,0 +1,272 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA152VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA152VFT_ +#define _ZEPHYR_DTS_BINDING_MCXA152VFT_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC0_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define ADC0_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA152VLF-pinctrl.h b/dts/nxp/mcx/MCXA152VLF-pinctrl.h new file mode 100644 index 000000000..14a7901f1 --- /dev/null +++ b/dts/nxp/mcx/MCXA152VLF-pinctrl.h @@ -0,0 +1,254 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA152VLF/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA152VLF_ +#define _ZEPHYR_DTS_BINDING_MCXA152VLF_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA152VLH-pinctrl.h b/dts/nxp/mcx/MCXA152VLH-pinctrl.h new file mode 100644 index 000000000..f88cb4b9d --- /dev/null +++ b/dts/nxp/mcx/MCXA152VLH-pinctrl.h @@ -0,0 +1,327 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA152VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA152VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA152VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC0_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define ADC0_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define ADC0_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define ADC0_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA153VFM-pinctrl.h b/dts/nxp/mcx/MCXA153VFM-pinctrl.h new file mode 100644 index 000000000..7250da1be --- /dev/null +++ b/dts/nxp/mcx/MCXA153VFM-pinctrl.h @@ -0,0 +1,188 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA153VFM/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA153VFM_ +#define _ZEPHYR_DTS_BINDING_MCXA153VFM_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#endif diff --git a/dts/nxp/mcx/MCXA153VFT-pinctrl.h b/dts/nxp/mcx/MCXA153VFT-pinctrl.h new file mode 100644 index 000000000..e88f79cfe --- /dev/null +++ b/dts/nxp/mcx/MCXA153VFT-pinctrl.h @@ -0,0 +1,272 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA153VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA153VFT_ +#define _ZEPHYR_DTS_BINDING_MCXA153VFT_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC0_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define ADC0_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA153VLF-pinctrl.h b/dts/nxp/mcx/MCXA153VLF-pinctrl.h new file mode 100644 index 000000000..d0325e321 --- /dev/null +++ b/dts/nxp/mcx/MCXA153VLF-pinctrl.h @@ -0,0 +1,254 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA153VLF/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA153VLF_ +#define _ZEPHYR_DTS_BINDING_MCXA153VLF_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA153VLH-pinctrl.h b/dts/nxp/mcx/MCXA153VLH-pinctrl.h new file mode 100644 index 000000000..809e94b93 --- /dev/null +++ b/dts/nxp/mcx/MCXA153VLH-pinctrl.h @@ -0,0 +1,327 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA153VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA153VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA153VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C0_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C0_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C0_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C0_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C0_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C0_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC0_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C0_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define ADC0_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C0_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC0_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define ADC0_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC0_A2_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC0_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C0_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C0_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define ADC0_A14_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define ADC0_A13_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC0_A12_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA154VFT-pinctrl.h b/dts/nxp/mcx/MCXA154VFT-pinctrl.h new file mode 100644 index 000000000..0948398d4 --- /dev/null +++ b/dts/nxp/mcx/MCXA154VFT-pinctrl.h @@ -0,0 +1,359 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA154VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA154VFT_ +#define _ZEPHYR_DTS_BINDING_MCXA154VFT_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA154VLH-pinctrl.h b/dts/nxp/mcx/MCXA154VLH-pinctrl.h new file mode 100644 index 000000000..7646109a4 --- /dev/null +++ b/dts/nxp/mcx/MCXA154VLH-pinctrl.h @@ -0,0 +1,445 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA154VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA154VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA154VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA154VLL-pinctrl.h b/dts/nxp/mcx/MCXA154VLL-pinctrl.h new file mode 100644 index 000000000..893187fb0 --- /dev/null +++ b/dts/nxp/mcx/MCXA154VLL-pinctrl.h @@ -0,0 +1,619 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA154VLL/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA154VLL_ +#define _ZEPHYR_DTS_BINDING_MCXA154VLL_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_P0_18 A15X_MUX('0',18,6) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_P0_19 A15X_MUX('0',19,6) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define WUU0_IN31_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_P0_20 A15X_MUX('0',20,6) /* PT0_20 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_P0_21 A15X_MUX('0',21,6) /* PT0_21 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define FLEXIO0_D6_P0_22 A15X_MUX('0',22,6) /* PT0_22 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define FLEXIO0_D7_P0_23 A15X_MUX('0',23,6) /* PT0_23 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_P1_14 A15X_MUX('1',14,4) /* PT1_14 */ +#define CT3_MAT0_P1_14 A15X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_P1_14 A15X_MUX('1',14,6) /* PT1_14 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_P1_15 A15X_MUX('1',15,4) /* PT1_15 */ +#define CT3_MAT1_P1_15 A15X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_P1_15 A15X_MUX('1',15,6) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define CT3_MAT2_P2_10 A15X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_P2_10 A15X_MUX('2',10,6) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define CT3_MAT3_P2_11 A15X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_P2_11 A15X_MUX('2',11,6) /* PT2_11 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT3_MAT0_P2_16 A15X_MUX('2',16,4) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define FLEXIO0_D24_P2_16 A15X_MUX('2',16,6) /* PT2_16 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT3_MAT1_P2_17 A15X_MUX('2',17,4) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define FLEXIO0_D25_P2_17 A15X_MUX('2',17,6) /* PT2_17 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define CT3_MAT3_P2_19 A15X_MUX('2',19,4) /* PT2_19 */ +#define FLEXIO0_D27_P2_19 A15X_MUX('2',19,6) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define FLEXIO0_D28_P2_20 A15X_MUX('2',20,6) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define FLEXIO0_D29_P2_21 A15X_MUX('2',21,6) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define FLEXIO0_D31_P2_23 A15X_MUX('2',23,6) /* PT2_23 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define LPUART4_RTS_B_P3_16 A15X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_P3_16 A15X_MUX('3',16,6) /* PT3_16 */ +#define PWM1_A0_P3_16 A15X_MUX('3',16,7) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define LPUART4_CTS_B_P3_17 A15X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_P3_17 A15X_MUX('3',17,6) /* PT3_17 */ +#define PWM1_B0_P3_17 A15X_MUX('3',17,7) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define LPUART4_RXD_P3_18 A15X_MUX('3',18,2) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_P3_18 A15X_MUX('3',18,6) /* PT3_18 */ +#define PWM1_X0_P3_18 A15X_MUX('3',18,7) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define LPUART4_TXD_P3_19 A15X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_P3_19 A15X_MUX('3',19,6) /* PT3_19 */ +#define PWM1_X1_P3_19 A15X_MUX('3',19,7) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPI2C3_SDA_P3_20 A15X_MUX('3',20,2) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_P3_20 A15X_MUX('3',20,6) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPI2C3_SCL_P3_21 A15X_MUX('3',21,2) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_P3_21 A15X_MUX('3',21,6) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_P3_22 A15X_MUX('3',22,6) /* PT3_22 */ +#define PWM1_X2_P3_22 A15X_MUX('3',22,7) /* PT3_22 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPI2C2_SDAS_P4_2 A15X_MUX('4',2,2) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define CT4_MAT0_P4_2 A15X_MUX('4',2,4) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define FLEXIO0_D10_P4_2 A15X_MUX('4',2,6) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define LPI2C2_SCL_P4_3 A15X_MUX('4',3,2) /* PT4_3 */ +#define LPUART4_TXD_P4_3 A15X_MUX('4',3,3) /* PT4_3 */ +#define CT4_MAT1_P4_3 A15X_MUX('4',3,4) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define FLEXIO0_D11_P4_3 A15X_MUX('4',3,6) /* PT4_3 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define LPI2C2_SDA_P4_4 A15X_MUX('4',4,2) /* PT4_4 */ +#define LPUART4_RXD_P4_4 A15X_MUX('4',4,3) /* PT4_4 */ +#define CT4_MAT2_P4_4 A15X_MUX('4',4,4) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define FLEXIO0_D12_P4_4 A15X_MUX('4',4,6) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPI2C2_SCLS_P4_5 A15X_MUX('4',5,2) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define CT4_MAT3_P4_5 A15X_MUX('4',5,4) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define FLEXIO0_D13_P4_5 A15X_MUX('4',5,6) /* PT4_5 */ +#define WUU0_IN17_P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPI2C2_HREQ_P4_6 A15X_MUX('4',6,2) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define FLEXIO0_D14_P4_6 A15X_MUX('4',6,6) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define FLEXIO0_D15_P4_7 A15X_MUX('4',7,6) /* PT4_7 */ +#endif diff --git a/dts/nxp/mcx/MCXA154VMP-pinctrl.h b/dts/nxp/mcx/MCXA154VMP-pinctrl.h new file mode 100644 index 000000000..8a032ce23 --- /dev/null +++ b/dts/nxp/mcx/MCXA154VMP-pinctrl.h @@ -0,0 +1,429 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA154VMP/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA154VMP_ +#define _ZEPHYR_DTS_BINDING_MCXA154VMP_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA154VPJ-pinctrl.h b/dts/nxp/mcx/MCXA154VPJ-pinctrl.h new file mode 100644 index 000000000..b392fd260 --- /dev/null +++ b/dts/nxp/mcx/MCXA154VPJ-pinctrl.h @@ -0,0 +1,624 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA154VPJ/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA154VPJ_ +#define _ZEPHYR_DTS_BINDING_MCXA154VPJ_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_P0_18 A15X_MUX('0',18,6) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_P0_19 A15X_MUX('0',19,6) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define WUU0_IN31_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_P0_20 A15X_MUX('0',20,6) /* PT0_20 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_P0_21 A15X_MUX('0',21,6) /* PT0_21 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define FLEXIO0_D6_P0_22 A15X_MUX('0',22,6) /* PT0_22 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define FLEXIO0_D7_P0_23 A15X_MUX('0',23,6) /* PT0_23 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_P1_14 A15X_MUX('1',14,4) /* PT1_14 */ +#define CT3_MAT0_P1_14 A15X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_P1_14 A15X_MUX('1',14,6) /* PT1_14 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_P1_15 A15X_MUX('1',15,4) /* PT1_15 */ +#define CT3_MAT1_P1_15 A15X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_P1_15 A15X_MUX('1',15,6) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define CT3_MAT2_P2_10 A15X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_P2_10 A15X_MUX('2',10,6) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define CT3_MAT3_P2_11 A15X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_P2_11 A15X_MUX('2',11,6) /* PT2_11 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT3_MAT0_P2_16 A15X_MUX('2',16,4) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define FLEXIO0_D24_P2_16 A15X_MUX('2',16,6) /* PT2_16 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT3_MAT1_P2_17 A15X_MUX('2',17,4) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define FLEXIO0_D25_P2_17 A15X_MUX('2',17,6) /* PT2_17 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define CT3_MAT3_P2_19 A15X_MUX('2',19,4) /* PT2_19 */ +#define FLEXIO0_D27_P2_19 A15X_MUX('2',19,6) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define FLEXIO0_D28_P2_20 A15X_MUX('2',20,6) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define FLEXIO0_D29_P2_21 A15X_MUX('2',21,6) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define FLEXIO0_D31_P2_23 A15X_MUX('2',23,6) /* PT2_23 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_2 A15X_MUX('3',2,0) /* PT3_2 */ +#define LPSPI1_PCS1_P3_2 A15X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_P3_2 A15X_MUX('3',2,4) /* PT3_2 */ +#define FLEXIO0_D10_P3_2 A15X_MUX('3',2,6) /* PT3_2 */ +#define PWM1_X2_P3_2 A15X_MUX('3',2,7) /* PT3_2 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define LPUART4_RTS_B_P3_16 A15X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_P3_16 A15X_MUX('3',16,6) /* PT3_16 */ +#define PWM1_A0_P3_16 A15X_MUX('3',16,7) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define LPUART4_CTS_B_P3_17 A15X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_P3_17 A15X_MUX('3',17,6) /* PT3_17 */ +#define PWM1_B0_P3_17 A15X_MUX('3',17,7) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define LPUART4_RXD_P3_18 A15X_MUX('3',18,2) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_P3_18 A15X_MUX('3',18,6) /* PT3_18 */ +#define PWM1_X0_P3_18 A15X_MUX('3',18,7) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define LPUART4_TXD_P3_19 A15X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_P3_19 A15X_MUX('3',19,6) /* PT3_19 */ +#define PWM1_X1_P3_19 A15X_MUX('3',19,7) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPI2C3_SDA_P3_20 A15X_MUX('3',20,2) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_P3_20 A15X_MUX('3',20,6) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPI2C3_SCL_P3_21 A15X_MUX('3',21,2) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_P3_21 A15X_MUX('3',21,6) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_P3_22 A15X_MUX('3',22,6) /* PT3_22 */ +#define PWM1_X2_P3_22 A15X_MUX('3',22,7) /* PT3_22 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPI2C2_SDAS_P4_2 A15X_MUX('4',2,2) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define CT4_MAT0_P4_2 A15X_MUX('4',2,4) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define FLEXIO0_D10_P4_2 A15X_MUX('4',2,6) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define LPI2C2_SCL_P4_3 A15X_MUX('4',3,2) /* PT4_3 */ +#define LPUART4_TXD_P4_3 A15X_MUX('4',3,3) /* PT4_3 */ +#define CT4_MAT1_P4_3 A15X_MUX('4',3,4) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define FLEXIO0_D11_P4_3 A15X_MUX('4',3,6) /* PT4_3 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define LPI2C2_SDA_P4_4 A15X_MUX('4',4,2) /* PT4_4 */ +#define LPUART4_RXD_P4_4 A15X_MUX('4',4,3) /* PT4_4 */ +#define CT4_MAT2_P4_4 A15X_MUX('4',4,4) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define FLEXIO0_D12_P4_4 A15X_MUX('4',4,6) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPI2C2_SCLS_P4_5 A15X_MUX('4',5,2) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define CT4_MAT3_P4_5 A15X_MUX('4',5,4) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define FLEXIO0_D13_P4_5 A15X_MUX('4',5,6) /* PT4_5 */ +#define WUU0_IN17_P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPI2C2_HREQ_P4_6 A15X_MUX('4',6,2) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define FLEXIO0_D14_P4_6 A15X_MUX('4',6,6) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define FLEXIO0_D15_P4_7 A15X_MUX('4',7,6) /* PT4_7 */ +#endif diff --git a/dts/nxp/mcx/MCXA155VFT-pinctrl.h b/dts/nxp/mcx/MCXA155VFT-pinctrl.h new file mode 100644 index 000000000..2f1b3d216 --- /dev/null +++ b/dts/nxp/mcx/MCXA155VFT-pinctrl.h @@ -0,0 +1,359 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA155VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA155VFT_ +#define _ZEPHYR_DTS_BINDING_MCXA155VFT_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA155VLH-pinctrl.h b/dts/nxp/mcx/MCXA155VLH-pinctrl.h new file mode 100644 index 000000000..6bc10d8da --- /dev/null +++ b/dts/nxp/mcx/MCXA155VLH-pinctrl.h @@ -0,0 +1,445 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA155VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA155VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA155VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA155VLL-pinctrl.h b/dts/nxp/mcx/MCXA155VLL-pinctrl.h new file mode 100644 index 000000000..7817b59c1 --- /dev/null +++ b/dts/nxp/mcx/MCXA155VLL-pinctrl.h @@ -0,0 +1,619 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA155VLL/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA155VLL_ +#define _ZEPHYR_DTS_BINDING_MCXA155VLL_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_P0_18 A15X_MUX('0',18,6) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_P0_19 A15X_MUX('0',19,6) /* PT0_19 */ +#define WUU0_IN31_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_P0_20 A15X_MUX('0',20,6) /* PT0_20 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_P0_21 A15X_MUX('0',21,6) /* PT0_21 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define FLEXIO0_D6_P0_22 A15X_MUX('0',22,6) /* PT0_22 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define FLEXIO0_D7_P0_23 A15X_MUX('0',23,6) /* PT0_23 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_P1_14 A15X_MUX('1',14,4) /* PT1_14 */ +#define CT3_MAT0_P1_14 A15X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_P1_14 A15X_MUX('1',14,6) /* PT1_14 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_P1_15 A15X_MUX('1',15,4) /* PT1_15 */ +#define CT3_MAT1_P1_15 A15X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_P1_15 A15X_MUX('1',15,6) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define CT3_MAT2_P2_10 A15X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_P2_10 A15X_MUX('2',10,6) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define CT3_MAT3_P2_11 A15X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_P2_11 A15X_MUX('2',11,6) /* PT2_11 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT3_MAT0_P2_16 A15X_MUX('2',16,4) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define FLEXIO0_D24_P2_16 A15X_MUX('2',16,6) /* PT2_16 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT3_MAT1_P2_17 A15X_MUX('2',17,4) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define FLEXIO0_D25_P2_17 A15X_MUX('2',17,6) /* PT2_17 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define CT3_MAT3_P2_19 A15X_MUX('2',19,4) /* PT2_19 */ +#define FLEXIO0_D27_P2_19 A15X_MUX('2',19,6) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define FLEXIO0_D28_P2_20 A15X_MUX('2',20,6) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define FLEXIO0_D29_P2_21 A15X_MUX('2',21,6) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define FLEXIO0_D31_P2_23 A15X_MUX('2',23,6) /* PT2_23 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define LPUART4_RTS_B_P3_16 A15X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_P3_16 A15X_MUX('3',16,6) /* PT3_16 */ +#define PWM1_A0_P3_16 A15X_MUX('3',16,7) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define LPUART4_CTS_B_P3_17 A15X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_P3_17 A15X_MUX('3',17,6) /* PT3_17 */ +#define PWM1_B0_P3_17 A15X_MUX('3',17,7) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define LPUART4_RXD_P3_18 A15X_MUX('3',18,2) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_P3_18 A15X_MUX('3',18,6) /* PT3_18 */ +#define PWM1_X0_P3_18 A15X_MUX('3',18,7) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define LPUART4_TXD_P3_19 A15X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_P3_19 A15X_MUX('3',19,6) /* PT3_19 */ +#define PWM1_X1_P3_19 A15X_MUX('3',19,7) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPI2C3_SDA_P3_20 A15X_MUX('3',20,2) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_P3_20 A15X_MUX('3',20,6) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPI2C3_SCL_P3_21 A15X_MUX('3',21,2) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_P3_21 A15X_MUX('3',21,6) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_P3_22 A15X_MUX('3',22,6) /* PT3_22 */ +#define PWM1_X2_P3_22 A15X_MUX('3',22,7) /* PT3_22 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPI2C2_SDAS_P4_2 A15X_MUX('4',2,2) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define CT4_MAT0_P4_2 A15X_MUX('4',2,4) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define FLEXIO0_D10_P4_2 A15X_MUX('4',2,6) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define LPI2C2_SCL_P4_3 A15X_MUX('4',3,2) /* PT4_3 */ +#define LPUART4_TXD_P4_3 A15X_MUX('4',3,3) /* PT4_3 */ +#define CT4_MAT1_P4_3 A15X_MUX('4',3,4) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define FLEXIO0_D11_P4_3 A15X_MUX('4',3,6) /* PT4_3 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define LPI2C2_SDA_P4_4 A15X_MUX('4',4,2) /* PT4_4 */ +#define LPUART4_RXD_P4_4 A15X_MUX('4',4,3) /* PT4_4 */ +#define CT4_MAT2_P4_4 A15X_MUX('4',4,4) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define FLEXIO0_D12_P4_4 A15X_MUX('4',4,6) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPI2C2_SCLS_P4_5 A15X_MUX('4',5,2) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define CT4_MAT3_P4_5 A15X_MUX('4',5,4) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define FLEXIO0_D13_P4_5 A15X_MUX('4',5,6) /* PT4_5 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define WUU0_IN17_P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPI2C2_HREQ_P4_6 A15X_MUX('4',6,2) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define FLEXIO0_D14_P4_6 A15X_MUX('4',6,6) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define FLEXIO0_D15_P4_7 A15X_MUX('4',7,6) /* PT4_7 */ +#endif diff --git a/dts/nxp/mcx/MCXA155VMP-pinctrl.h b/dts/nxp/mcx/MCXA155VMP-pinctrl.h new file mode 100644 index 000000000..d3e06fc95 --- /dev/null +++ b/dts/nxp/mcx/MCXA155VMP-pinctrl.h @@ -0,0 +1,429 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA155VMP/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA155VMP_ +#define _ZEPHYR_DTS_BINDING_MCXA155VMP_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA155VPJ-pinctrl.h b/dts/nxp/mcx/MCXA155VPJ-pinctrl.h new file mode 100644 index 000000000..68d17aa18 --- /dev/null +++ b/dts/nxp/mcx/MCXA155VPJ-pinctrl.h @@ -0,0 +1,624 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA155VPJ/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA155VPJ_ +#define _ZEPHYR_DTS_BINDING_MCXA155VPJ_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A8_P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define P0_18 A15X_MUX('0',18,0) /* PT0_18 */ +#define LPI2C0_SCLS_P0_18 A15X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_P0_18 A15X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_P0_18 A15X_MUX('0',18,6) /* PT0_18 */ +#define CMP0_OUT_P0_18 A15X_MUX('0',18,8) /* PT0_18 */ +#define P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A9_P0_19 A15X_MUX('0',19,0) /* PT0_19 */ +#define LPI2C0_SDAS_P0_19 A15X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_P0_19 A15X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_P0_19 A15X_MUX('0',19,6) /* PT0_19 */ +#define WUU0_IN31_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define CMP1_OUT_P0_19 A15X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A10_P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define P0_20 A15X_MUX('0',20,0) /* PT0_20 */ +#define LPUART0_RXD_P0_20 A15X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_P0_20 A15X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_P0_20 A15X_MUX('0',20,6) /* PT0_20 */ +#define P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A11_P0_21 A15X_MUX('0',21,0) /* PT0_21 */ +#define LPUART0_TXD_P0_21 A15X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_P0_21 A15X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_P0_21 A15X_MUX('0',21,6) /* PT0_21 */ +#define P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A12_P0_22 A15X_MUX('0',22,0) /* PT0_22 */ +#define LPUART0_RTS_B_P0_22 A15X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_P0_22 A15X_MUX('0',22,4) /* PT0_22 */ +#define CT0_MAT0_P0_22 A15X_MUX('0',22,5) /* PT0_22 */ +#define FLEXIO0_D6_P0_22 A15X_MUX('0',22,6) /* PT0_22 */ +#define ADC0_A13_P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define P0_23 A15X_MUX('0',23,0) /* PT0_23 */ +#define LPUART0_CTS_B_P0_23 A15X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_P0_23 A15X_MUX('0',23,4) /* PT0_23 */ +#define CT0_MAT1_P0_23 A15X_MUX('0',23,5) /* PT0_23 */ +#define FLEXIO0_D7_P0_23 A15X_MUX('0',23,6) /* PT0_23 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define ADC1_A12_P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define P1_14 A15X_MUX('1',14,0) /* PT1_14 */ +#define LPI2C1_SCLS_P1_14 A15X_MUX('1',14,2) /* PT1_14 */ +#define LPUART2_RTS_B_P1_14 A15X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_P1_14 A15X_MUX('1',14,4) /* PT1_14 */ +#define CT3_MAT0_P1_14 A15X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_P1_14 A15X_MUX('1',14,6) /* PT1_14 */ +#define P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A13_P1_15 A15X_MUX('1',15,0) /* PT1_15 */ +#define LPI2C1_SDAS_P1_15 A15X_MUX('1',15,2) /* PT1_15 */ +#define LPUART2_CTS_B_P1_15 A15X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_P1_15 A15X_MUX('1',15,4) /* PT1_15 */ +#define CT3_MAT1_P1_15 A15X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_P1_15 A15X_MUX('1',15,6) /* PT1_15 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_10 A15X_MUX('2',10,0) /* PT2_10 */ +#define TRIG_OUT5_P2_10 A15X_MUX('2',10,1) /* PT2_10 */ +#define LPUART2_TXD_P2_10 A15X_MUX('2',10,3) /* PT2_10 */ +#define CT3_MAT2_P2_10 A15X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_P2_10 A15X_MUX('2',10,6) /* PT2_10 */ +#define P2_11 A15X_MUX('2',11,0) /* PT2_11 */ +#define TRIG_IN4_P2_11 A15X_MUX('2',11,1) /* PT2_11 */ +#define LPUART2_RXD_P2_11 A15X_MUX('2',11,3) /* PT2_11 */ +#define CT3_MAT3_P2_11 A15X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_P2_11 A15X_MUX('2',11,6) /* PT2_11 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define ADC0_A6_P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define P2_16 A15X_MUX('2',16,0) /* PT2_16 */ +#define LPSPI1_SDI_P2_16 A15X_MUX('2',16,2) /* PT2_16 */ +#define LPUART1_RTS_B_P2_16 A15X_MUX('2',16,3) /* PT2_16 */ +#define CT3_MAT0_P2_16 A15X_MUX('2',16,4) /* PT2_16 */ +#define CT0_MAT2_P2_16 A15X_MUX('2',16,5) /* PT2_16 */ +#define FLEXIO0_D24_P2_16 A15X_MUX('2',16,6) /* PT2_16 */ +#define ADC1_A6_P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define P2_17 A15X_MUX('2',17,0) /* PT2_17 */ +#define TRIG_IN9_P2_17 A15X_MUX('2',17,1) /* PT2_17 */ +#define LPSPI1_PCS0_P2_17 A15X_MUX('2',17,2) /* PT2_17 */ +#define LPUART1_CTS_B_P2_17 A15X_MUX('2',17,3) /* PT2_17 */ +#define CT3_MAT1_P2_17 A15X_MUX('2',17,4) /* PT2_17 */ +#define CT0_MAT3_P2_17 A15X_MUX('2',17,5) /* PT2_17 */ +#define FLEXIO0_D25_P2_17 A15X_MUX('2',17,6) /* PT2_17 */ +#define P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define ADC1_A2_P2_19 A15X_MUX('2',19,0) /* PT2_19 */ +#define TRIG_OUT5_P2_19 A15X_MUX('2',19,1) /* PT2_19 */ +#define CT3_MAT3_P2_19 A15X_MUX('2',19,4) /* PT2_19 */ +#define FLEXIO0_D27_P2_19 A15X_MUX('2',19,6) /* PT2_19 */ +#define P2_20 A15X_MUX('2',20,0) /* PT2_20 */ +#define TRIG_IN8_P2_20 A15X_MUX('2',20,1) /* PT2_20 */ +#define LPSPI1_PCS2_P2_20 A15X_MUX('2',20,2) /* PT2_20 */ +#define CT2_MAT0_P2_20 A15X_MUX('2',20,4) /* PT2_20 */ +#define FLEXIO0_D28_P2_20 A15X_MUX('2',20,6) /* PT2_20 */ +#define P2_21 A15X_MUX('2',21,0) /* PT2_21 */ +#define TRIG_IN9_P2_21 A15X_MUX('2',21,1) /* PT2_21 */ +#define LPSPI1_PCS3_P2_21 A15X_MUX('2',21,2) /* PT2_21 */ +#define CT2_MAT1_P2_21 A15X_MUX('2',21,4) /* PT2_21 */ +#define FLEXIO0_D29_P2_21 A15X_MUX('2',21,6) /* PT2_21 */ +#define P2_23 A15X_MUX('2',23,0) /* PT2_23 */ +#define TRIG_OUT5_P2_23 A15X_MUX('2',23,1) /* PT2_23 */ +#define CT2_MAT3_P2_23 A15X_MUX('2',23,4) /* PT2_23 */ +#define FLEXIO0_D31_P2_23 A15X_MUX('2',23,6) /* PT2_23 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_2 A15X_MUX('3',2,0) /* PT3_2 */ +#define LPSPI1_PCS1_P3_2 A15X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_P3_2 A15X_MUX('3',2,4) /* PT3_2 */ +#define FLEXIO0_D10_P3_2 A15X_MUX('3',2,6) /* PT3_2 */ +#define PWM1_X2_P3_2 A15X_MUX('3',2,7) /* PT3_2 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define P3_16 A15X_MUX('3',16,0) /* PT3_16 */ +#define LPUART4_RTS_B_P3_16 A15X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_P3_16 A15X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_P3_16 A15X_MUX('3',16,6) /* PT3_16 */ +#define PWM1_A0_P3_16 A15X_MUX('3',16,7) /* PT3_16 */ +#define P3_17 A15X_MUX('3',17,0) /* PT3_17 */ +#define LPUART4_CTS_B_P3_17 A15X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_P3_17 A15X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_P3_17 A15X_MUX('3',17,6) /* PT3_17 */ +#define PWM1_B0_P3_17 A15X_MUX('3',17,7) /* PT3_17 */ +#define P3_18 A15X_MUX('3',18,0) /* PT3_18 */ +#define LPUART4_RXD_P3_18 A15X_MUX('3',18,2) /* PT3_18 */ +#define CT2_MAT0_P3_18 A15X_MUX('3',18,4) /* PT3_18 */ +#define PWM0_X0_P3_18 A15X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_P3_18 A15X_MUX('3',18,6) /* PT3_18 */ +#define PWM1_X0_P3_18 A15X_MUX('3',18,7) /* PT3_18 */ +#define P3_19 A15X_MUX('3',19,0) /* PT3_19 */ +#define LPUART4_TXD_P3_19 A15X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_P3_19 A15X_MUX('3',19,4) /* PT3_19 */ +#define PWM0_X1_P3_19 A15X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_P3_19 A15X_MUX('3',19,6) /* PT3_19 */ +#define PWM1_X1_P3_19 A15X_MUX('3',19,7) /* PT3_19 */ +#define P3_20 A15X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_P3_20 A15X_MUX('3',20,1) /* PT3_20 */ +#define LPI2C3_SDA_P3_20 A15X_MUX('3',20,2) /* PT3_20 */ +#define LPUART1_RXD_P3_20 A15X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_P3_20 A15X_MUX('3',20,4) /* PT3_20 */ +#define PWM0_X2_P3_20 A15X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_P3_20 A15X_MUX('3',20,6) /* PT3_20 */ +#define P3_21 A15X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_P3_21 A15X_MUX('3',21,1) /* PT3_21 */ +#define LPI2C3_SCL_P3_21 A15X_MUX('3',21,2) /* PT3_21 */ +#define LPUART1_TXD_P3_21 A15X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_P3_21 A15X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_P3_21 A15X_MUX('3',21,6) /* PT3_21 */ +#define P3_22 A15X_MUX('3',22,0) /* PT3_22 */ +#define LPUART1_RTS_B_P3_22 A15X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_P3_22 A15X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_P3_22 A15X_MUX('3',22,6) /* PT3_22 */ +#define PWM1_X2_P3_22 A15X_MUX('3',22,7) /* PT3_22 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#define P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define WUU0_IN16_P4_2 A15X_MUX('4',2,0) /* PT4_2 */ +#define CLKOUT_P4_2 A15X_MUX('4',2,1) /* PT4_2 */ +#define LPI2C2_SDAS_P4_2 A15X_MUX('4',2,2) /* PT4_2 */ +#define LPUART3_RXD_P4_2 A15X_MUX('4',2,3) /* PT4_2 */ +#define CT4_MAT0_P4_2 A15X_MUX('4',2,4) /* PT4_2 */ +#define PWM0_A2_P4_2 A15X_MUX('4',2,5) /* PT4_2 */ +#define FLEXIO0_D10_P4_2 A15X_MUX('4',2,6) /* PT4_2 */ +#define P4_3 A15X_MUX('4',3,0) /* PT4_3 */ +#define LPI2C2_SCL_P4_3 A15X_MUX('4',3,2) /* PT4_3 */ +#define LPUART4_TXD_P4_3 A15X_MUX('4',3,3) /* PT4_3 */ +#define CT4_MAT1_P4_3 A15X_MUX('4',3,4) /* PT4_3 */ +#define PWM0_B2_P4_3 A15X_MUX('4',3,5) /* PT4_3 */ +#define FLEXIO0_D11_P4_3 A15X_MUX('4',3,6) /* PT4_3 */ +#define P4_4 A15X_MUX('4',4,0) /* PT4_4 */ +#define LPI2C2_SDA_P4_4 A15X_MUX('4',4,2) /* PT4_4 */ +#define LPUART4_RXD_P4_4 A15X_MUX('4',4,3) /* PT4_4 */ +#define CT4_MAT2_P4_4 A15X_MUX('4',4,4) /* PT4_4 */ +#define PWM0_A1_P4_4 A15X_MUX('4',4,5) /* PT4_4 */ +#define FLEXIO0_D12_P4_4 A15X_MUX('4',4,6) /* PT4_4 */ +#define P4_5 A15X_MUX('4',5,0) /* PT4_5 */ +#define TRIG_OUT3_P4_5 A15X_MUX('4',5,1) /* PT4_5 */ +#define LPI2C2_SCLS_P4_5 A15X_MUX('4',5,2) /* PT4_5 */ +#define LPUART3_TXD_P4_5 A15X_MUX('4',5,3) /* PT4_5 */ +#define CT4_MAT3_P4_5 A15X_MUX('4',5,4) /* PT4_5 */ +#define PWM0_B1_P4_5 A15X_MUX('4',5,5) /* PT4_5 */ +#define FLEXIO0_D13_P4_5 A15X_MUX('4',5,6) /* PT4_5 */ +#define P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define WUU0_IN17_P4_6 A15X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_IN4_P4_6 A15X_MUX('4',6,1) /* PT4_6 */ +#define LPI2C2_HREQ_P4_6 A15X_MUX('4',6,2) /* PT4_6 */ +#define LPUART3_CTS_B_P4_6 A15X_MUX('4',6,3) /* PT4_6 */ +#define CT_INP6_P4_6 A15X_MUX('4',6,4) /* PT4_6 */ +#define PWM0_A0_P4_6 A15X_MUX('4',6,5) /* PT4_6 */ +#define FLEXIO0_D14_P4_6 A15X_MUX('4',6,6) /* PT4_6 */ +#define P4_7 A15X_MUX('4',7,0) /* PT4_7 */ +#define TRIG_IN5_P4_7 A15X_MUX('4',7,1) /* PT4_7 */ +#define LPUART3_RTS_B_P4_7 A15X_MUX('4',7,3) /* PT4_7 */ +#define CT_INP7_P4_7 A15X_MUX('4',7,4) /* PT4_7 */ +#define PWM0_B0_P4_7 A15X_MUX('4',7,5) /* PT4_7 */ +#define FLEXIO0_D15_P4_7 A15X_MUX('4',7,6) /* PT4_7 */ +#endif diff --git a/dts/nxp/mcx/MCXA156VFT-pinctrl.h b/dts/nxp/mcx/MCXA156VFT-pinctrl.h new file mode 100644 index 000000000..53a75d076 --- /dev/null +++ b/dts/nxp/mcx/MCXA156VFT-pinctrl.h @@ -0,0 +1,359 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA156VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA156VFT_ +#define _ZEPHYR_DTS_BINDING_MCXA156VFT_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXA156VLH-pinctrl.h b/dts/nxp/mcx/MCXA156VLH-pinctrl.h new file mode 100644 index 000000000..3ead3d7e5 --- /dev/null +++ b/dts/nxp/mcx/MCXA156VLH-pinctrl.h @@ -0,0 +1,445 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXA156VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXA156VLH_ +#define _ZEPHYR_DTS_BINDING_MCXA156VLH_ + +#define A15X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ +#define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ +#define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ +#define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ +#define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ +#define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ +#define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ +#define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ +#define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ +#define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ +#define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ +#define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ +#define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ +#define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ +#define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ +#define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ +#define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ +#define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ +#define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ +#define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ +#define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ +#define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ +#define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ +#define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ +#define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ +#define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ +#define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ +#define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ +#define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ +#define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ +#define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ +#define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ +#define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ +#define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ +#define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ +#define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ +#define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ +#define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ +#define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ +#define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ +#define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ +#define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ +#define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ +#define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ +#define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ +#define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ +#define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ +#define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ +#define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ +#define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ +#define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ +#define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ +#define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ +#define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ +#define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ +#define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ +#define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ +#define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ +#define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ +#define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ +#define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ +#define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ +#define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ +#define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ +#define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ +#define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ +#define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ +#define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ +#define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ +#define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ +#define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ +#define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ +#define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ +#define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ +#define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ +#define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ +#define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ +#define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ +#define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ +#define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ +#define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ +#define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ +#define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ +#define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ +#define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ +#define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ +#define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ +#define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ +#define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ +#define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ +#define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ +#define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ +#define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ +#define WUU0_IN12_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A10_P1_12 A15X_MUX('1',12,0) /* PT1_12 */ +#define LPI2C1_SDA_P1_12 A15X_MUX('1',12,2) /* PT1_12 */ +#define LPUART2_RXD_P1_12 A15X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_P1_12 A15X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_P1_12 A15X_MUX('1',12,6) /* PT1_12 */ +#define CAN0_RXD_P1_12 A15X_MUX('1',12,11) /* PT1_12 */ +#define ADC1_A11_P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define P1_13 A15X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_P1_13 A15X_MUX('1',13,1) /* PT1_13 */ +#define LPI2C1_SCL_P1_13 A15X_MUX('1',13,2) /* PT1_13 */ +#define LPUART2_TXD_P1_13 A15X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_P1_13 A15X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_P1_13 A15X_MUX('1',13,6) /* PT1_13 */ +#define CAN0_TXD_P1_13 A15X_MUX('1',13,11) /* PT1_13 */ +#define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ +#define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ +#define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ +#define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ +#define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ +#define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ +#define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ +#define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ +#define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ +#define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ +#define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ +#define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ +#define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ +#define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ +#define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ +#define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ +#define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ +#define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ +#define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ +#define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ +#define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ +#define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ +#define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ +#define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ +#define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ +#define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ +#define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ +#define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ +#define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ +#define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ +#define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ +#define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ +#define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ +#define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ +#define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ +#define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ +#define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ +#define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ +#define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ +#define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ +#define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ +#define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ +#define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ +#define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ +#define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ +#define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ +#define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ +#define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ +#define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ +#define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ +#define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ +#define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ +#define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ +#define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ +#define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ +#define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ +#define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ +#define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ +#define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ +#define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ +#define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ +#define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ +#define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ +#define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ +#define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ +#define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ +#define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ +#define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ +#define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ +#define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ +#define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ +#define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ +#define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ +#define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ +#define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ +#define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ +#define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ +#define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ +#define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ +#define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ +#define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ +#define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ +#define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ +#define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ +#define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ +#define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ +#define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ +#define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ +#define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ +#define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ +#define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ +#define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ +#define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ +#define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ +#define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ +#define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ +#define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ +#define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ +#define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ +#define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ +#define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ +#define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ +#define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ +#define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ +#define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ +#define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ +#define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ +#define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ +#define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ +#define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ +#define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ +#define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ +#define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ +#define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ +#define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ +#define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ +#define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ +#define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ +#define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ +#define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ +#define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ +#define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ +#define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ +#define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ +#define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ +#define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ +#define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ +#define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ +#define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ +#define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ +#define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ +#define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ +#define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ +#define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ +#define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ +#define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ +#define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ +#define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ +#define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ +#define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ +#define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ +#define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ +#define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ +#define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ +#define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ +#define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ +#define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ +#define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ +#define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ +#define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ +#define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ +#define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ +#define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ +#define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ +#define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ +#define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ +#define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ +#define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ +#define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ +#define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ +#define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ +#define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ +#define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ +#endif diff --git a/dts/nxp/mcx/MCXC041VFG-pinctrl.h b/dts/nxp/mcx/MCXC041VFG-pinctrl.h new file mode 100644 index 000000000..36970d193 --- /dev/null +++ b/dts/nxp/mcx/MCXC041VFG-pinctrl.h @@ -0,0 +1,79 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC041VFG/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC041VFG_ +#define _ZEPHYR_DTS_BINDING_MCXC041VFG_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define CMP0_IN2_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ADC0_SE15_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LLWU_P7_PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM1_CH0_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPTMR0_ALT1_PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define TPM_CLKIN0_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define RESET_b_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define CMP0_OUT_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define SWD_DIO_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EXTAL0_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C0_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define I2C0_SDA_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define XTAL0_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C0_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define I2C0_SCL_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define LPUART0_RX_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define CLKOUT_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define RTC_CLKIN_PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TPM0_CH1_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define SPI0_SS_b_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define TPM0_CH0_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define SPI0_MISO_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define SPI0_MISO_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define SPI0_MOSI_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define ADC0_SE9_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P4_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define EXTRG_IN_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define SPI0_SCK_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define CMP0_IN3_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE8_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPUART0_RX_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define VREF_OUT_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define CMP0_IN5_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define LPUART0_RX_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_TX_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SCL_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_TX_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define I2C0_SDA_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPUART0_RX_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define ADC0_SE1_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define CMP0_IN1_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define TPM1_CH1_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define NMI_b_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#endif diff --git a/dts/nxp/mcx/MCXC041VFK-pinctrl.h b/dts/nxp/mcx/MCXC041VFK-pinctrl.h new file mode 100644 index 000000000..0596a883f --- /dev/null +++ b/dts/nxp/mcx/MCXC041VFK-pinctrl.h @@ -0,0 +1,110 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC041VFK/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC041VFK_ +#define _ZEPHYR_DTS_BINDING_MCXC041VFK_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define CMP0_IN2_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define ADC0_SE15_PTA0 KINETIS_MUX('A',0,0) /* PTA_0 */ +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define LLWU_P7_PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM1_CH0_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPTMR0_ALT1_PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define TPM_CLKIN0_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define RESET_b_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define CMP0_OUT_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define SWD_DIO_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define EXTAL0_PTA3 KINETIS_MUX('A',3,0) /* PTA_3 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C0_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define I2C0_SDA_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define LPUART0_TX_PTA3 KINETIS_MUX('A',3,4) /* PTA_3 */ +#define XTAL0_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C0_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define I2C0_SCL_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define LPUART0_RX_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define CLKOUT_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define RTC_CLKIN_PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define TPM0_CH1_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define SPI0_SS_b_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define PTA6 KINETIS_MUX('A',6,1) /* PTA_6 */ +#define TPM0_CH0_PTA6 KINETIS_MUX('A',6,2) /* PTA_6 */ +#define SPI0_MISO_PTA6 KINETIS_MUX('A',6,3) /* PTA_6 */ +#define PTA7 KINETIS_MUX('A',7,1) /* PTA_7 */ +#define SPI0_MISO_PTA7 KINETIS_MUX('A',7,2) /* PTA_7 */ +#define SPI0_MOSI_PTA7 KINETIS_MUX('A',7,3) /* PTA_7 */ +#define ADC0_SE3_PTA8 KINETIS_MUX('A',8,0) /* PTA_8 */ +#define PTA8 KINETIS_MUX('A',8,1) /* PTA_8 */ +#define I2C0_SCL_PTA8 KINETIS_MUX('A',8,2) /* PTA_8 */ +#define SPI0_MOSI_PTA8 KINETIS_MUX('A',8,3) /* PTA_8 */ +#define ADC0_SE2_PTA9 KINETIS_MUX('A',9,0) /* PTA_9 */ +#define PTA9 KINETIS_MUX('A',9,1) /* PTA_9 */ +#define I2C0_SDA_PTA9 KINETIS_MUX('A',9,2) /* PTA_9 */ +#define SPI0_SCK_PTA9 KINETIS_MUX('A',9,3) /* PTA_9 */ +#define ADC0_SE0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define CMP0_IN0_PTA12 KINETIS_MUX('A',12,0) /* PTA_12 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define LPTMR0_ALT2_PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,2) /* PTA_12 */ +#define TPM_CLKIN0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define CLKOUT_PTA12 KINETIS_MUX('A',12,5) /* PTA_12 */ +#define ADC0_SE9_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P4_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define EXTRG_IN_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define SPI0_SCK_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,4) /* PTB_0 */ +#define CMP0_IN3_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE8_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPUART0_TX_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define LPUART0_RX_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,4) /* PTB_1 */ +#define VREF_OUT_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define CMP0_IN5_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define LPUART0_RX_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART0_TX_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SCL_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART0_TX_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define I2C0_SDA_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPUART0_RX_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define ADC0_SE1_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define CMP0_IN1_PTB5 KINETIS_MUX('B',5,0) /* PTB_5 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define TPM1_CH1_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define NMI_b_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define LPTMR0_ALT3_PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define PTB6 KINETIS_MUX('B',6,1) /* PTB_6 */ +#define TPM1_CH1_PTB6 KINETIS_MUX('B',6,2) /* PTB_6 */ +#define TPM_CLKIN1_PTB6 KINETIS_MUX('B',6,3) /* PTB_6 */ +#define PTB7 KINETIS_MUX('B',7,1) /* PTB_7 */ +#define TPM1_CH0_PTB7 KINETIS_MUX('B',7,2) /* PTB_7 */ +#define PTB10 KINETIS_MUX('B',10,1) /* PTB_10 */ +#define TPM0_CH1_PTB10 KINETIS_MUX('B',10,2) /* PTB_10 */ +#define SPI0_SS_b_PTB10 KINETIS_MUX('B',10,3) /* PTB_10 */ +#define PTB11 KINETIS_MUX('B',11,1) /* PTB_11 */ +#define TPM0_CH0_PTB11 KINETIS_MUX('B',11,2) /* PTB_11 */ +#define SPI0_MISO_PTB11 KINETIS_MUX('B',11,3) /* PTB_11 */ +#define CLKOUT32K_PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define PTB13 KINETIS_MUX('B',13,1) /* PTB_13 */ +#define TPM1_CH1_PTB13 KINETIS_MUX('B',13,2) /* PTB_13 */ +#define RTC_CLKOUT_PTB13 KINETIS_MUX('B',13,3) /* PTB_13 */ +#endif diff --git a/dts/nxp/mcx/MCXC143VFM-pinctrl.h b/dts/nxp/mcx/MCXC143VFM-pinctrl.h new file mode 100644 index 000000000..62c02cea1 --- /dev/null +++ b/dts/nxp/mcx/MCXC143VFM-pinctrl.h @@ -0,0 +1,171 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC143VFM/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC143VFM_ +#define _ZEPHYR_DTS_BINDING_MCXC143VFM_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_SS_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define ADC0_DM1_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define FXIO0_D1_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_DP2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define ADC0_SE2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_MOSI_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define SPI0_MISO_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D2_PTE18 KINETIS_MUX('E',18,6) /* PTE_18 */ +#define ADC0_DM2_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define ADC0_SE6a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_MISO_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define SPI0_MOSI_PTE19 KINETIS_MUX('E',19,5) /* PTE_19 */ +#define FXIO0_D3_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/mcx/MCXC143VFT-pinctrl.h b/dts/nxp/mcx/MCXC143VFT-pinctrl.h new file mode 100644 index 000000000..f44df632e --- /dev/null +++ b/dts/nxp/mcx/MCXC143VFT-pinctrl.h @@ -0,0 +1,226 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC143VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC143VFT_ +#define _ZEPHYR_DTS_BINDING_MCXC143VFT_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD0_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_SS_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define ADC0_DM1_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define FXIO0_D1_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_DP2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define ADC0_SE2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_MOSI_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define SPI0_MISO_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D2_PTE18 KINETIS_MUX('E',18,6) /* PTE_18 */ +#define ADC0_DM2_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define ADC0_SE6a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_MISO_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define SPI0_MOSI_PTE19 KINETIS_MUX('E',19,5) /* PTE_19 */ +#define FXIO0_D3_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/mcx/MCXC144VFM-pinctrl.h b/dts/nxp/mcx/MCXC144VFM-pinctrl.h new file mode 100644 index 000000000..c3e4036b4 --- /dev/null +++ b/dts/nxp/mcx/MCXC144VFM-pinctrl.h @@ -0,0 +1,171 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC144VFM/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC144VFM_ +#define _ZEPHYR_DTS_BINDING_MCXC144VFM_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_SS_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_DM1_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define FXIO0_D1_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_SE2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define ADC0_DP2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_MOSI_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define SPI0_MISO_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D2_PTE18 KINETIS_MUX('E',18,6) /* PTE_18 */ +#define ADC0_DM2_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define ADC0_SE6a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_MISO_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define SPI0_MOSI_PTE19 KINETIS_MUX('E',19,5) /* PTE_19 */ +#define FXIO0_D3_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/mcx/MCXC144VFT-pinctrl.h b/dts/nxp/mcx/MCXC144VFT-pinctrl.h new file mode 100644 index 000000000..9ad66760a --- /dev/null +++ b/dts/nxp/mcx/MCXC144VFT-pinctrl.h @@ -0,0 +1,226 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC144VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC144VFT_ +#define _ZEPHYR_DTS_BINDING_MCXC144VFT_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD0_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_DP1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define ADC0_SE1_PTE16 KINETIS_MUX('E',16,0) /* PTE_16 */ +#define PTE16 KINETIS_MUX('E',16,1) /* PTE_16 */ +#define SPI0_SS_PTE16 KINETIS_MUX('E',16,2) /* PTE_16 */ +#define UART2_TX_PTE16 KINETIS_MUX('E',16,3) /* PTE_16 */ +#define TPM_CLKIN0_PTE16 KINETIS_MUX('E',16,4) /* PTE_16 */ +#define FXIO0_D0_PTE16 KINETIS_MUX('E',16,6) /* PTE_16 */ +#define ADC0_DM1_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define ADC0_SE5a_PTE17 KINETIS_MUX('E',17,0) /* PTE_17 */ +#define PTE17 KINETIS_MUX('E',17,1) /* PTE_17 */ +#define SPI0_SCK_PTE17 KINETIS_MUX('E',17,2) /* PTE_17 */ +#define UART2_RX_PTE17 KINETIS_MUX('E',17,3) /* PTE_17 */ +#define TPM_CLKIN1_PTE17 KINETIS_MUX('E',17,4) /* PTE_17 */ +#define LPTMR0_ALT3_PTE17 KINETIS_MUX('E',17,5) /* PTE_17 */ +#define FXIO0_D1_PTE17 KINETIS_MUX('E',17,6) /* PTE_17 */ +#define ADC0_SE2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define ADC0_DP2_PTE18 KINETIS_MUX('E',18,0) /* PTE_18 */ +#define PTE18 KINETIS_MUX('E',18,1) /* PTE_18 */ +#define SPI0_MOSI_PTE18 KINETIS_MUX('E',18,2) /* PTE_18 */ +#define I2C0_SDA_PTE18 KINETIS_MUX('E',18,4) /* PTE_18 */ +#define SPI0_MISO_PTE18 KINETIS_MUX('E',18,5) /* PTE_18 */ +#define FXIO0_D2_PTE18 KINETIS_MUX('E',18,6) /* PTE_18 */ +#define ADC0_DM2_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define ADC0_SE6a_PTE19 KINETIS_MUX('E',19,0) /* PTE_19 */ +#define PTE19 KINETIS_MUX('E',19,1) /* PTE_19 */ +#define SPI0_MISO_PTE19 KINETIS_MUX('E',19,2) /* PTE_19 */ +#define I2C0_SCL_PTE19 KINETIS_MUX('E',19,4) /* PTE_19 */ +#define SPI0_MOSI_PTE19 KINETIS_MUX('E',19,5) /* PTE_19 */ +#define FXIO0_D3_PTE19 KINETIS_MUX('E',19,6) /* PTE_19 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/mcx/MCXC243VFT-pinctrl.h b/dts/nxp/mcx/MCXC243VFT-pinctrl.h new file mode 100644 index 000000000..461702e3f --- /dev/null +++ b/dts/nxp/mcx/MCXC243VFT-pinctrl.h @@ -0,0 +1,199 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC243VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC243VFT_ +#define _ZEPHYR_DTS_BINDING_MCXC243VFT_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD0_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/mcx/MCXC244VFM-pinctrl.h b/dts/nxp/mcx/MCXC244VFM-pinctrl.h new file mode 100644 index 000000000..6926d559c --- /dev/null +++ b/dts/nxp/mcx/MCXC244VFM-pinctrl.h @@ -0,0 +1,138 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC244VFM/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC244VFM_ +#define _ZEPHYR_DTS_BINDING_MCXC244VFM_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/mcx/MCXC244VFT-pinctrl.h b/dts/nxp/mcx/MCXC244VFT-pinctrl.h new file mode 100644 index 000000000..12dddeed1 --- /dev/null +++ b/dts/nxp/mcx/MCXC244VFT-pinctrl.h @@ -0,0 +1,199 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC244VFT/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC244VFT_ +#define _ZEPHYR_DTS_BINDING_MCXC244VFT_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD0_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#endif diff --git a/dts/nxp/mcx/MCXC443VLH-pinctrl.h b/dts/nxp/mcx/MCXC443VLH-pinctrl.h new file mode 100644 index 000000000..79c70bd86 --- /dev/null +++ b/dts/nxp/mcx/MCXC443VLH-pinctrl.h @@ -0,0 +1,313 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC443VLH/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC443VLH_ +#define _ZEPHYR_DTS_BINDING_MCXC443VLH_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LCD_P0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LCD_P0_Fault_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define LCD_P1_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define LCD_P1_Fault_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define LCD_P2_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LCD_P2_Fault_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define LCD_P3_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LCD_P3_Fault_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define LCD_P12_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define LCD_P12_Fault_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define LCD_P13_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define LCD_P13_Fault_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define LCD_P14_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define LCD_P14_Fault_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define LCD_P15_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define LCD_P15_Fault_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define LCD_P20_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD0_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define LCD_P20_Fault_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define LCD_P21_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LCD_P21_Fault_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define LCD_P22_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LCD_P22_Fault_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define LCD_P23_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LCD_P23_Fault_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define LCD_P24_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define LCD_P24_Fault_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LCD_P25_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define LCD_P25_Fault_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define LCD_P26_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define LCD_P26_Fault_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define LCD_P27_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LCD_P27_Fault_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define LCD_P4_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define VLL2_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define PTC20 KINETIS_MUX('C',20,1) /* PTC_20 */ +#define LCD_P4_Fault_PTC20 KINETIS_MUX('C',20,7) /* PTC_20 */ +#define VLL1_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define LCD_P5_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define PTC21 KINETIS_MUX('C',21,1) /* PTC_21 */ +#define LCD_P5_Fault_PTC21 KINETIS_MUX('C',21,7) /* PTC_21 */ +#define LCD_P6_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define VCAP2_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define PTC22 KINETIS_MUX('C',22,1) /* PTC_22 */ +#define LCD_P6_Fault_PTC22 KINETIS_MUX('C',22,7) /* PTC_22 */ +#define LCD_P39_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define VCAP1_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define PTC23 KINETIS_MUX('C',23,1) /* PTC_23 */ +#define LCD_P39_Fault_PTC23 KINETIS_MUX('C',23,7) /* PTC_23 */ +#define LCD_P40_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define LCD_P40_Fault_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define LCD_P41_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LCD_P41_Fault_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LCD_P42_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define LCD_P42_Fault_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define LCD_P43_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LCD_P43_Fault_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LCD_P44_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define LCD_P44_Fault_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define LCD_P45_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LCD_P45_Fault_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LCD_P46_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define LCD_P46_Fault_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define LCD_P47_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define LCD_P47_Fault_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LCD_P48_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define LCD_P48_Fault_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LCD_P49_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define LCD_P49_Fault_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LCD_P59_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define LCD_P59_Fault_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define LCD_P60_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define LCD_P60_Fault_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/mcx/MCXC443VMP-pinctrl.h b/dts/nxp/mcx/MCXC443VMP-pinctrl.h new file mode 100644 index 000000000..e50cf246d --- /dev/null +++ b/dts/nxp/mcx/MCXC443VMP-pinctrl.h @@ -0,0 +1,313 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXC443VMP/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXC443VMP_ +#define _ZEPHYR_DTS_BINDING_MCXC443VMP_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define TPM0_CH5_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define SWD_CLK_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define LPUART0_RX_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define TPM2_CH0_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define PTA2 KINETIS_MUX('A',2,1) /* PTA_2 */ +#define LPUART0_TX_PTA2 KINETIS_MUX('A',2,2) /* PTA_2 */ +#define TPM2_CH1_PTA2 KINETIS_MUX('A',2,3) /* PTA_2 */ +#define PTA3 KINETIS_MUX('A',3,1) /* PTA_3 */ +#define I2C1_SCL_PTA3 KINETIS_MUX('A',3,2) /* PTA_3 */ +#define TPM0_CH0_PTA3 KINETIS_MUX('A',3,3) /* PTA_3 */ +#define SWD_DIO_PTA3 KINETIS_MUX('A',3,7) /* PTA_3 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define I2C1_SDA_PTA4 KINETIS_MUX('A',4,2) /* PTA_4 */ +#define TPM0_CH1_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define NMI_b_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define PTA5 KINETIS_MUX('A',5,1) /* PTA_5 */ +#define USB_CLKIN_PTA5 KINETIS_MUX('A',5,2) /* PTA_5 */ +#define TPM0_CH2_PTA5 KINETIS_MUX('A',5,3) /* PTA_5 */ +#define I2S0_TX_BCLK_PTA5 KINETIS_MUX('A',5,6) /* PTA_5 */ +#define PTA12 KINETIS_MUX('A',12,1) /* PTA_12 */ +#define TPM1_CH0_PTA12 KINETIS_MUX('A',12,3) /* PTA_12 */ +#define I2S0_TXD0_PTA12 KINETIS_MUX('A',12,6) /* PTA_12 */ +#define PTA13 KINETIS_MUX('A',13,1) /* PTA_13 */ +#define TPM1_CH1_PTA13 KINETIS_MUX('A',13,3) /* PTA_13 */ +#define I2S0_TX_FS_PTA13 KINETIS_MUX('A',13,6) /* PTA_13 */ +#define EXTAL0_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPUART1_RX_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define TPM_CLKIN0_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define XTAL0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPUART1_TX_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define TPM_CLKIN1_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define LPTMR0_ALT1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define RESET_b_PTA20 KINETIS_MUX('A',20,7) /* PTA_20 */ +#define ADC0_SE8_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LCD_P0_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define LLWU_P5_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define I2C0_SCL_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,3) /* PTB_0 */ +#define LCD_P0_Fault_PTB0 KINETIS_MUX('B',0,7) /* PTB_0 */ +#define LCD_P1_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define ADC0_SE9_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define I2C0_SDA_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,3) /* PTB_1 */ +#define LCD_P1_Fault_PTB1 KINETIS_MUX('B',1,7) /* PTB_1 */ +#define LCD_P2_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define ADC0_SE12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define I2C0_SCL_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define TPM2_CH0_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define LCD_P2_Fault_PTB2 KINETIS_MUX('B',2,7) /* PTB_2 */ +#define ADC0_SE13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define LCD_P3_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define I2C0_SDA_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define TPM2_CH1_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define LCD_P3_Fault_PTB3 KINETIS_MUX('B',3,7) /* PTB_3 */ +#define LCD_P12_PTB16 KINETIS_MUX('B',16,0) /* PTB_16 */ +#define PTB16 KINETIS_MUX('B',16,1) /* PTB_16 */ +#define SPI1_MOSI_PTB16 KINETIS_MUX('B',16,2) /* PTB_16 */ +#define LPUART0_RX_PTB16 KINETIS_MUX('B',16,3) /* PTB_16 */ +#define TPM_CLKIN0_PTB16 KINETIS_MUX('B',16,4) /* PTB_16 */ +#define SPI1_MISO_PTB16 KINETIS_MUX('B',16,5) /* PTB_16 */ +#define LCD_P12_Fault_PTB16 KINETIS_MUX('B',16,7) /* PTB_16 */ +#define LCD_P13_PTB17 KINETIS_MUX('B',17,0) /* PTB_17 */ +#define PTB17 KINETIS_MUX('B',17,1) /* PTB_17 */ +#define SPI1_MISO_PTB17 KINETIS_MUX('B',17,2) /* PTB_17 */ +#define LPUART0_TX_PTB17 KINETIS_MUX('B',17,3) /* PTB_17 */ +#define TPM_CLKIN1_PTB17 KINETIS_MUX('B',17,4) /* PTB_17 */ +#define SPI1_MOSI_PTB17 KINETIS_MUX('B',17,5) /* PTB_17 */ +#define LCD_P13_Fault_PTB17 KINETIS_MUX('B',17,7) /* PTB_17 */ +#define LCD_P14_PTB18 KINETIS_MUX('B',18,0) /* PTB_18 */ +#define PTB18 KINETIS_MUX('B',18,1) /* PTB_18 */ +#define TPM2_CH0_PTB18 KINETIS_MUX('B',18,3) /* PTB_18 */ +#define I2S0_TX_BCLK_PTB18 KINETIS_MUX('B',18,4) /* PTB_18 */ +#define LCD_P14_Fault_PTB18 KINETIS_MUX('B',18,7) /* PTB_18 */ +#define LCD_P15_PTB19 KINETIS_MUX('B',19,0) /* PTB_19 */ +#define PTB19 KINETIS_MUX('B',19,1) /* PTB_19 */ +#define TPM2_CH1_PTB19 KINETIS_MUX('B',19,3) /* PTB_19 */ +#define I2S0_TX_FS_PTB19 KINETIS_MUX('B',19,4) /* PTB_19 */ +#define LCD_P15_Fault_PTB19 KINETIS_MUX('B',19,7) /* PTB_19 */ +#define LCD_P20_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define ADC0_SE14_PTC0 KINETIS_MUX('C',0,0) /* PTC_0 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define EXTRG_IN_PTC0 KINETIS_MUX('C',0,3) /* PTC_0 */ +#define USB_SOF_OUT_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define CMP0_OUT_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define I2S0_TXD0_PTC0 KINETIS_MUX('C',0,6) /* PTC_0 */ +#define LCD_P20_Fault_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define LCD_P21_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define ADC0_SE15_PTC1 KINETIS_MUX('C',1,0) /* PTC_1 */ +#define LLWU_P6_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define RTC_CLKIN_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define I2C1_SCL_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define TPM0_CH0_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define I2S0_TXD0_PTC1 KINETIS_MUX('C',1,6) /* PTC_1 */ +#define LCD_P21_Fault_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define ADC0_SE11_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define LCD_P22_PTC2 KINETIS_MUX('C',2,0) /* PTC_2 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define I2C1_SDA_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define TPM0_CH1_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define I2S0_TX_FS_PTC2 KINETIS_MUX('C',2,6) /* PTC_2 */ +#define LCD_P22_Fault_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define LCD_P23_PTC3 KINETIS_MUX('C',3,0) /* PTC_3 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LLWU_P7_PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define SPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_RX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define TPM0_CH2_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define CLKOUT_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define I2S0_TX_BCLK_PTC3 KINETIS_MUX('C',3,6) /* PTC_3 */ +#define LCD_P23_Fault_PTC3 KINETIS_MUX('C',3,7) /* PTC_3 */ +#define LCD_P24_PTC4 KINETIS_MUX('C',4,0) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LLWU_P8_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define SPI0_SS_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPUART1_TX_PTC4 KINETIS_MUX('C',4,3) /* PTC_4 */ +#define TPM0_CH3_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define I2S0_MCLK_PTC4 KINETIS_MUX('C',4,5) /* PTC_4 */ +#define LCD_P24_Fault_PTC4 KINETIS_MUX('C',4,7) /* PTC_4 */ +#define LCD_P25_PTC5 KINETIS_MUX('C',5,0) /* PTC_5 */ +#define LLWU_P9_PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define SPI0_SCK_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPTMR0_ALT2_PTC5 KINETIS_MUX('C',5,3) /* PTC_5 */ +#define I2S0_RXD0_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define CMP0_OUT_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define LCD_P25_Fault_PTC5 KINETIS_MUX('C',5,7) /* PTC_5 */ +#define LCD_P26_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define CMP0_IN0_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LLWU_P10_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define SPI0_MOSI_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define EXTRG_IN_PTC6 KINETIS_MUX('C',6,3) /* PTC_6 */ +#define I2S0_RX_BCLK_PTC6 KINETIS_MUX('C',6,4) /* PTC_6 */ +#define SPI0_MISO_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define I2S0_MCLK_PTC6 KINETIS_MUX('C',6,6) /* PTC_6 */ +#define LCD_P26_Fault_PTC6 KINETIS_MUX('C',6,7) /* PTC_6 */ +#define CMP0_IN1_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define LCD_P27_PTC7 KINETIS_MUX('C',7,0) /* PTC_7 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define SPI0_MISO_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define USB_SOF_OUT_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define I2S0_RX_FS_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define SPI0_MOSI_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define LCD_P27_Fault_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define LCD_P4_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define VLL2_PTC20 KINETIS_MUX('C',20,0) /* PTC_20 */ +#define PTC20 KINETIS_MUX('C',20,1) /* PTC_20 */ +#define LCD_P4_Fault_PTC20 KINETIS_MUX('C',20,7) /* PTC_20 */ +#define VLL1_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define LCD_P5_PTC21 KINETIS_MUX('C',21,0) /* PTC_21 */ +#define PTC21 KINETIS_MUX('C',21,1) /* PTC_21 */ +#define LCD_P5_Fault_PTC21 KINETIS_MUX('C',21,7) /* PTC_21 */ +#define LCD_P6_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define VCAP2_PTC22 KINETIS_MUX('C',22,0) /* PTC_22 */ +#define PTC22 KINETIS_MUX('C',22,1) /* PTC_22 */ +#define LCD_P6_Fault_PTC22 KINETIS_MUX('C',22,7) /* PTC_22 */ +#define LCD_P39_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define VCAP1_PTC23 KINETIS_MUX('C',23,0) /* PTC_23 */ +#define PTC23 KINETIS_MUX('C',23,1) /* PTC_23 */ +#define LCD_P39_Fault_PTC23 KINETIS_MUX('C',23,7) /* PTC_23 */ +#define LCD_P40_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define SPI0_SS_PTD0 KINETIS_MUX('D',0,2) /* PTD_0 */ +#define TPM0_CH0_PTD0 KINETIS_MUX('D',0,4) /* PTD_0 */ +#define FXIO0_D0_PTD0 KINETIS_MUX('D',0,6) /* PTD_0 */ +#define LCD_P40_Fault_PTD0 KINETIS_MUX('D',0,7) /* PTD_0 */ +#define LCD_P41_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define ADC0_SE5b_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPI0_SCK_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define TPM0_CH1_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define FXIO0_D1_PTD1 KINETIS_MUX('D',1,6) /* PTD_1 */ +#define LCD_P41_Fault_PTD1 KINETIS_MUX('D',1,7) /* PTD_1 */ +#define LCD_P42_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define SPI0_MOSI_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define UART2_RX_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define TPM0_CH2_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define SPI0_MISO_PTD2 KINETIS_MUX('D',2,5) /* PTD_2 */ +#define FXIO0_D2_PTD2 KINETIS_MUX('D',2,6) /* PTD_2 */ +#define LCD_P42_Fault_PTD2 KINETIS_MUX('D',2,7) /* PTD_2 */ +#define LCD_P43_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define SPI0_MISO_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define UART2_TX_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define TPM0_CH3_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define SPI0_MOSI_PTD3 KINETIS_MUX('D',3,5) /* PTD_3 */ +#define FXIO0_D3_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define LCD_P43_Fault_PTD3 KINETIS_MUX('D',3,7) /* PTD_3 */ +#define LCD_P44_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define LLWU_P14_PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define SPI1_SS_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define UART2_RX_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define TPM0_CH4_PTD4 KINETIS_MUX('D',4,4) /* PTD_4 */ +#define FXIO0_D4_PTD4 KINETIS_MUX('D',4,6) /* PTD_4 */ +#define LCD_P44_Fault_PTD4 KINETIS_MUX('D',4,7) /* PTD_4 */ +#define ADC0_SE6b_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define LCD_P45_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define SPI1_SCK_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#define UART2_TX_PTD5 KINETIS_MUX('D',5,3) /* PTD_5 */ +#define TPM0_CH5_PTD5 KINETIS_MUX('D',5,4) /* PTD_5 */ +#define FXIO0_D5_PTD5 KINETIS_MUX('D',5,6) /* PTD_5 */ +#define LCD_P45_Fault_PTD5 KINETIS_MUX('D',5,7) /* PTD_5 */ +#define ADC0_SE7b_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LCD_P46_PTD6 KINETIS_MUX('D',6,0) /* PTD_6 */ +#define LLWU_P15_PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define PTD6 KINETIS_MUX('D',6,1) /* PTD_6 */ +#define SPI1_MOSI_PTD6 KINETIS_MUX('D',6,2) /* PTD_6 */ +#define LPUART0_RX_PTD6 KINETIS_MUX('D',6,3) /* PTD_6 */ +#define SPI1_MISO_PTD6 KINETIS_MUX('D',6,5) /* PTD_6 */ +#define FXIO0_D6_PTD6 KINETIS_MUX('D',6,6) /* PTD_6 */ +#define LCD_P46_Fault_PTD6 KINETIS_MUX('D',6,7) /* PTD_6 */ +#define LCD_P47_PTD7 KINETIS_MUX('D',7,0) /* PTD_7 */ +#define PTD7 KINETIS_MUX('D',7,1) /* PTD_7 */ +#define SPI1_MISO_PTD7 KINETIS_MUX('D',7,2) /* PTD_7 */ +#define LPUART0_TX_PTD7 KINETIS_MUX('D',7,3) /* PTD_7 */ +#define SPI1_MOSI_PTD7 KINETIS_MUX('D',7,5) /* PTD_7 */ +#define FXIO0_D7_PTD7 KINETIS_MUX('D',7,6) /* PTD_7 */ +#define LCD_P47_Fault_PTD7 KINETIS_MUX('D',7,7) /* PTD_7 */ +#define LCD_P48_PTE0 KINETIS_MUX('E',0,0) /* PTE_0 */ +#define CLKOUT32K_PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define PTE0 KINETIS_MUX('E',0,1) /* PTE_0 */ +#define SPI1_MISO_PTE0 KINETIS_MUX('E',0,2) /* PTE_0 */ +#define LPUART1_TX_PTE0 KINETIS_MUX('E',0,3) /* PTE_0 */ +#define RTC_CLKOUT_PTE0 KINETIS_MUX('E',0,4) /* PTE_0 */ +#define CMP0_OUT_PTE0 KINETIS_MUX('E',0,5) /* PTE_0 */ +#define I2C1_SDA_PTE0 KINETIS_MUX('E',0,6) /* PTE_0 */ +#define LCD_P48_Fault_PTE0 KINETIS_MUX('E',0,7) /* PTE_0 */ +#define LCD_P49_PTE1 KINETIS_MUX('E',1,0) /* PTE_1 */ +#define PTE1 KINETIS_MUX('E',1,1) /* PTE_1 */ +#define SPI1_MOSI_PTE1 KINETIS_MUX('E',1,2) /* PTE_1 */ +#define LPUART1_RX_PTE1 KINETIS_MUX('E',1,3) /* PTE_1 */ +#define SPI1_MISO_PTE1 KINETIS_MUX('E',1,5) /* PTE_1 */ +#define I2C1_SCL_PTE1 KINETIS_MUX('E',1,6) /* PTE_1 */ +#define LCD_P49_Fault_PTE1 KINETIS_MUX('E',1,7) /* PTE_1 */ +#define LCD_P59_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_DP0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define ADC0_SE0_PTE20 KINETIS_MUX('E',20,0) /* PTE_20 */ +#define PTE20 KINETIS_MUX('E',20,1) /* PTE_20 */ +#define TPM1_CH0_PTE20 KINETIS_MUX('E',20,3) /* PTE_20 */ +#define LPUART0_TX_PTE20 KINETIS_MUX('E',20,4) /* PTE_20 */ +#define FXIO0_D4_PTE20 KINETIS_MUX('E',20,6) /* PTE_20 */ +#define LCD_P59_Fault_PTE20 KINETIS_MUX('E',20,7) /* PTE_20 */ +#define ADC0_SE4a_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define LCD_P60_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define ADC0_DM0_PTE21 KINETIS_MUX('E',21,0) /* PTE_21 */ +#define PTE21 KINETIS_MUX('E',21,1) /* PTE_21 */ +#define TPM1_CH1_PTE21 KINETIS_MUX('E',21,3) /* PTE_21 */ +#define LPUART0_RX_PTE21 KINETIS_MUX('E',21,4) /* PTE_21 */ +#define FXIO0_D5_PTE21 KINETIS_MUX('E',21,6) /* PTE_21 */ +#define LCD_P60_Fault_PTE21 KINETIS_MUX('E',21,7) /* PTE_21 */ +#define ADC0_DP3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define ADC0_SE3_PTE22 KINETIS_MUX('E',22,0) /* PTE_22 */ +#define PTE22 KINETIS_MUX('E',22,1) /* PTE_22 */ +#define TPM2_CH0_PTE22 KINETIS_MUX('E',22,3) /* PTE_22 */ +#define UART2_TX_PTE22 KINETIS_MUX('E',22,4) /* PTE_22 */ +#define FXIO0_D6_PTE22 KINETIS_MUX('E',22,6) /* PTE_22 */ +#define ADC0_DM3_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define ADC0_SE7a_PTE23 KINETIS_MUX('E',23,0) /* PTE_23 */ +#define PTE23 KINETIS_MUX('E',23,1) /* PTE_23 */ +#define TPM2_CH1_PTE23 KINETIS_MUX('E',23,3) /* PTE_23 */ +#define UART2_RX_PTE23 KINETIS_MUX('E',23,4) /* PTE_23 */ +#define FXIO0_D7_PTE23 KINETIS_MUX('E',23,6) /* PTE_23 */ +#define PTE24 KINETIS_MUX('E',24,1) /* PTE_24 */ +#define TPM0_CH0_PTE24 KINETIS_MUX('E',24,3) /* PTE_24 */ +#define I2C0_SCL_PTE24 KINETIS_MUX('E',24,5) /* PTE_24 */ +#define PTE25 KINETIS_MUX('E',25,1) /* PTE_25 */ +#define TPM0_CH1_PTE25 KINETIS_MUX('E',25,3) /* PTE_25 */ +#define I2C0_SDA_PTE25 KINETIS_MUX('E',25,5) /* PTE_25 */ +#define ADC0_SE4b_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define CMP0_IN5_PTE29 KINETIS_MUX('E',29,0) /* PTE_29 */ +#define PTE29 KINETIS_MUX('E',29,1) /* PTE_29 */ +#define TPM0_CH2_PTE29 KINETIS_MUX('E',29,3) /* PTE_29 */ +#define TPM_CLKIN0_PTE29 KINETIS_MUX('E',29,4) /* PTE_29 */ +#define DAC0_OUT_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define CMP0_IN4_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define ADC0_SE23_PTE30 KINETIS_MUX('E',30,0) /* PTE_30 */ +#define PTE30 KINETIS_MUX('E',30,1) /* PTE_30 */ +#define TPM0_CH3_PTE30 KINETIS_MUX('E',30,3) /* PTE_30 */ +#define TPM_CLKIN1_PTE30 KINETIS_MUX('E',30,4) /* PTE_30 */ +#define LPUART1_TX_PTE30 KINETIS_MUX('E',30,5) /* PTE_30 */ +#define LPTMR0_ALT1_PTE30 KINETIS_MUX('E',30,6) /* PTE_30 */ +#define PTE31 KINETIS_MUX('E',31,1) /* PTE_31 */ +#define TPM0_CH4_PTE31 KINETIS_MUX('E',31,3) /* PTE_31 */ +#endif diff --git a/dts/nxp/mcx/MCXN235VDF-pinctrl.h b/dts/nxp/mcx/MCXN235VDF-pinctrl.h new file mode 100644 index 000000000..cd94080da --- /dev/null +++ b/dts/nxp/mcx/MCXN235VDF-pinctrl.h @@ -0,0 +1,759 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN235VDF/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN235VDF_ +#define _ZEPHYR_DTS_BINDING_MCXN235VDF_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define WUU0_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define FC0_P3_PIO0_7 N9X_MUX('0',7,2) /* PT0_7 */ +#define CT_INP3_PIO0_7 N9X_MUX('0',7,4) /* PT0_7 */ +#define PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define ADC0_B14_PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define FC1_P6_PIO0_14 N9X_MUX('0',14,2) /* PT0_14 */ +#define FC0_P2_PIO0_14 N9X_MUX('0',14,3) /* PT0_14 */ +#define CT_INP2_PIO0_14 N9X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_PIO0_14 N9X_MUX('0',14,5) /* PT0_14 */ +#define FLEXIO0_D6_PIO0_14 N9X_MUX('0',14,6) /* PT0_14 */ +#define PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define ADC0_B15_PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define FC0_P3_PIO0_15 N9X_MUX('0',15,3) /* PT0_15 */ +#define CT_INP3_PIO0_15 N9X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_PIO0_15 N9X_MUX('0',15,5) /* PT0_15 */ +#define FLEXIO0_D7_PIO0_15 N9X_MUX('0',15,6) /* PT0_15 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define ADC0_B16_PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define FC1_P0_PIO0_24 N9X_MUX('0',24,2) /* PT0_24 */ +#define CT0_MAT0_PIO0_24 N9X_MUX('0',24,4) /* PT0_24 */ +#define PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define ADC0_B17_PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define FC1_P1_PIO0_25 N9X_MUX('0',25,2) /* PT0_25 */ +#define CT0_MAT1_PIO0_25 N9X_MUX('0',25,4) /* PT0_25 */ +#define PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define ADC0_B18_PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define FC1_P2_PIO0_26 N9X_MUX('0',26,2) /* PT0_26 */ +#define CT0_MAT2_PIO0_26 N9X_MUX('0',26,4) /* PT0_26 */ +#define PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define ADC0_B19_PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define FC1_P3_PIO0_27 N9X_MUX('0',27,2) /* PT0_27 */ +#define CT0_MAT3_PIO0_27 N9X_MUX('0',27,4) /* PT0_27 */ +#define PIO0_28 N9X_MUX('0',28,0) /* PT0_28 */ +#define ADC0_B20_PIO0_28 N9X_MUX('0',28,0) /* PT0_28 */ +#define FC1_P4_PIO0_28 N9X_MUX('0',28,2) /* PT0_28 */ +#define FC0_P4_PIO0_28 N9X_MUX('0',28,3) /* PT0_28 */ +#define CT_INP0_PIO0_28 N9X_MUX('0',28,4) /* PT0_28 */ +#define PIO0_29 N9X_MUX('0',29,0) /* PT0_29 */ +#define ADC0_B21_PIO0_29 N9X_MUX('0',29,0) /* PT0_29 */ +#define FC1_P5_PIO0_29 N9X_MUX('0',29,2) /* PT0_29 */ +#define FC0_P5_PIO0_29 N9X_MUX('0',29,3) /* PT0_29 */ +#define CT_INP1_PIO0_29 N9X_MUX('0',29,4) /* PT0_29 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define CAN1_TXD_PIO1_6 N9X_MUX('1',6,11) /* PT1_6 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define CAN1_RXD_PIO1_7 N9X_MUX('1',7,11) /* PT1_7 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define CAN1_RXD_PIO1_12 N9X_MUX('1',12,11) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define CAN1_TXD_PIO1_13 N9X_MUX('1',13,11) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define ADC1_A16_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define WUU0_IN14_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define FC5_P0_PIO1_16 N9X_MUX('1',16,2) /* PT1_16 */ +#define FC3_P4_PIO1_16 N9X_MUX('1',16,3) /* PT1_16 */ +#define CT_INP12_PIO1_16 N9X_MUX('1',16,4) /* PT1_16 */ +#define FLEXIO0_D24_PIO1_16 N9X_MUX('1',16,6) /* PT1_16 */ +#define EZH_PIO12_PIO1_16 N9X_MUX('1',16,7) /* PT1_16 */ +#define I3C1_SDA_PIO1_16 N9X_MUX('1',16,10) /* PT1_16 */ +#define PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define ADC1_A17_PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define FC5_P1_PIO1_17 N9X_MUX('1',17,2) /* PT1_17 */ +#define FC3_P5_PIO1_17 N9X_MUX('1',17,3) /* PT1_17 */ +#define CT_INP13_PIO1_17 N9X_MUX('1',17,4) /* PT1_17 */ +#define FLEXIO0_D25_PIO1_17 N9X_MUX('1',17,6) /* PT1_17 */ +#define EZH_PIO13_PIO1_17 N9X_MUX('1',17,7) /* PT1_17 */ +#define I3C1_SCL_PIO1_17 N9X_MUX('1',17,10) /* PT1_17 */ +#define ADC1_A18_PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define FREQME_CLK_IN0_PIO1_18 N9X_MUX('1',18,1) /* PT1_18 */ +#define FC5_P2_PIO1_18 N9X_MUX('1',18,2) /* PT1_18 */ +#define FC3_P6_PIO1_18 N9X_MUX('1',18,3) /* PT1_18 */ +#define CT3_MAT0_PIO1_18 N9X_MUX('1',18,4) /* PT1_18 */ +#define FLEXIO0_D26_PIO1_18 N9X_MUX('1',18,6) /* PT1_18 */ +#define EZH_PIO14_PIO1_18 N9X_MUX('1',18,7) /* PT1_18 */ +#define CAN0_TXD_PIO1_18 N9X_MUX('1',18,11) /* PT1_18 */ +#define PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define ADC1_A19_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define WUU0_IN15_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define FREQME_CLK_IN1_PIO1_19 N9X_MUX('1',19,1) /* PT1_19 */ +#define FC5_P3_PIO1_19 N9X_MUX('1',19,2) /* PT1_19 */ +#define CT3_MAT1_PIO1_19 N9X_MUX('1',19,4) /* PT1_19 */ +#define FLEXIO0_D27_PIO1_19 N9X_MUX('1',19,6) /* PT1_19 */ +#define EZH_PIO15_PIO1_19 N9X_MUX('1',19,7) /* PT1_19 */ +#define CAN0_RXD_PIO1_19 N9X_MUX('1',19,11) /* PT1_19 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define PWM1_A3_PIO2_0 N9X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define PWM1_B3_PIO2_1 N9X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define PWM1_A2_PIO2_2 N9X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define PWM1_B2_PIO2_3 N9X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PWM1_A1_PIO2_4 N9X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define PWM1_B1_PIO2_5 N9X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define PWM1_A0_PIO2_6 N9X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define PWM1_B0_PIO2_7 N9X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO2_8 N9X_MUX('2',8,0) /* PT2_8 */ +#define TRACE_DATA0_PIO2_8 N9X_MUX('2',8,1) /* PT2_8 */ +#define PWM1_X0_PIO2_8 N9X_MUX('2',8,5) /* PT2_8 */ +#define FLEXIO0_D16_PIO2_8 N9X_MUX('2',8,6) /* PT2_8 */ +#define EZH_PIO28_PIO2_8 N9X_MUX('2',8,7) /* PT2_8 */ +#define SAI1_TXD0_PIO2_8 N9X_MUX('2',8,10) /* PT2_8 */ +#define PIO2_9 N9X_MUX('2',9,0) /* PT2_9 */ +#define TRACE_DATA1_PIO2_9 N9X_MUX('2',9,1) /* PT2_9 */ +#define PWM1_X1_PIO2_9 N9X_MUX('2',9,5) /* PT2_9 */ +#define FLEXIO0_D17_PIO2_9 N9X_MUX('2',9,6) /* PT2_9 */ +#define EZH_PIO29_PIO2_9 N9X_MUX('2',9,7) /* PT2_9 */ +#define SAI1_RXD0_PIO2_9 N9X_MUX('2',9,10) /* PT2_9 */ +#define PIO2_10 N9X_MUX('2',10,0) /* PT2_10 */ +#define TRACE_DATA2_PIO2_10 N9X_MUX('2',10,1) /* PT2_10 */ +#define PWM1_X2_PIO2_10 N9X_MUX('2',10,5) /* PT2_10 */ +#define FLEXIO0_D18_PIO2_10 N9X_MUX('2',10,6) /* PT2_10 */ +#define EZH_PIO31_PIO2_10 N9X_MUX('2',10,7) /* PT2_10 */ +#define SAI1_RXD1_PIO2_10 N9X_MUX('2',10,10) /* PT2_10 */ +#define PIO2_11 N9X_MUX('2',11,0) /* PT2_11 */ +#define TRACE_DATA3_PIO2_11 N9X_MUX('2',11,1) /* PT2_11 */ +#define PWM1_X3_PIO2_11 N9X_MUX('2',11,5) /* PT2_11 */ +#define FLEXIO0_D19_PIO2_11 N9X_MUX('2',11,6) /* PT2_11 */ +#define EZH_PIO30_PIO2_11 N9X_MUX('2',11,7) /* PT2_11 */ +#define SAI1_TXD1_PIO2_11 N9X_MUX('2',11,10) /* PT2_11 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_2 N9X_MUX('3',2,0) /* PT3_2 */ +#define FC7_P0_PIO3_2 N9X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_PIO3_2 N9X_MUX('3',2,4) /* PT3_2 */ +#define PWM0_X0_PIO3_2 N9X_MUX('3',2,5) /* PT3_2 */ +#define FLEXIO0_D10_PIO3_2 N9X_MUX('3',2,6) /* PT3_2 */ +#define EZH_PIO2_PIO3_2 N9X_MUX('3',2,7) /* PT3_2 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define PWM1_A0_PIO3_12 N9X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define PWM1_B0_PIO3_13 N9X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define PWM1_A1_PIO3_14 N9X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define PWM1_B1_PIO3_15 N9X_MUX('3',15,5) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define PWM1_A2_PIO3_16 N9X_MUX('3',16,5) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define PWM1_B2_PIO3_17 N9X_MUX('3',17,5) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define PIO3_18 N9X_MUX('3',18,0) /* PT3_18 */ +#define FC6_P6_PIO3_18 N9X_MUX('3',18,3) /* PT3_18 */ +#define CT2_MAT0_PIO3_18 N9X_MUX('3',18,4) /* PT3_18 */ +#define PWM1_X0_PIO3_18 N9X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_PIO3_18 N9X_MUX('3',18,6) /* PT3_18 */ +#define EZH_PIO18_PIO3_18 N9X_MUX('3',18,7) /* PT3_18 */ +#define SAI1_RX_BCLK_PIO3_18 N9X_MUX('3',18,10) /* PT3_18 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define PWM1_A3_PIO3_20 N9X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define PWM1_B3_PIO3_21 N9X_MUX('3',21,5) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO3_22 N9X_MUX('3',22,0) /* PT3_22 */ +#define FC6_P2_PIO3_22 N9X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_PIO3_22 N9X_MUX('3',22,4) /* PT3_22 */ +#define PWM1_X2_PIO3_22 N9X_MUX('3',22,5) /* PT3_22 */ +#define FLEXIO0_D30_PIO3_22 N9X_MUX('3',22,6) /* PT3_22 */ +#define EZH_PIO22_PIO3_22 N9X_MUX('3',22,7) /* PT3_22 */ +#define SAI1_RXD1_PIO3_22 N9X_MUX('3',22,10) /* PT3_22 */ +#define PIO3_23 N9X_MUX('3',23,0) /* PT3_23 */ +#define FC6_P3_PIO3_23 N9X_MUX('3',23,3) /* PT3_23 */ +#define CT_INP11_PIO3_23 N9X_MUX('3',23,4) /* PT3_23 */ +#define PWM1_X3_PIO3_23 N9X_MUX('3',23,5) /* PT3_23 */ +#define FLEXIO0_D31_PIO3_23 N9X_MUX('3',23,6) /* PT3_23 */ +#define EZH_PIO23_PIO3_23 N9X_MUX('3',23,7) /* PT3_23 */ +#define SAI1_TXD1_PIO3_23 N9X_MUX('3',23,10) /* PT3_23 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define ADC0_A0_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define ADC0_B0_PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define ADC1_A0_PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define ADC1_B0_PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define ADC0_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define ADC1_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define USB1_OTG_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_14 N9X_MUX('4',14,0) /* PT4_14 */ +#define CT4_MAT2_PIO4_14 N9X_MUX('4',14,4) /* PT4_14 */ +#define FLEXIO0_D22_PIO4_14 N9X_MUX('4',14,6) /* PT4_14 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define CAN1_RXD_PIO4_15 N9X_MUX('4',15,11) /* PT4_15 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define CAN1_TXD_PIO4_16 N9X_MUX('4',16,11) /* PT4_16 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PIO4_18 N9X_MUX('4',18,0) /* PT4_18 */ +#define CT3_MAT2_PIO4_18 N9X_MUX('4',18,4) /* PT4_18 */ +#define FLEXIO0_D26_PIO4_18 N9X_MUX('4',18,6) /* PT4_18 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define PIO4_22 N9X_MUX('4',22,0) /* PT4_22 */ +#define CT2_MAT2_PIO4_22 N9X_MUX('4',22,4) /* PT4_22 */ +#define FLEXIO0_D30_PIO4_22 N9X_MUX('4',22,6) /* PT4_22 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#define ADC1_B12_PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define TRIG_OUT7_PIO5_4 N9X_MUX('5',4,1) /* PT5_4 */ +#define SPC_LPREQ_PIO5_4 N9X_MUX('5',4,2) /* PT5_4 */ +#define TAMPER2_PIO5_4 N9X_MUX('5',4,3) /* PT5_4 */ +#define PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define ADC1_B13_PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define TRIG_IN10_PIO5_5 N9X_MUX('5',5,1) /* PT5_5 */ +#define LPTMR0_ALT2_PIO5_5 N9X_MUX('5',5,2) /* PT5_5 */ +#define TAMPER3_PIO5_5 N9X_MUX('5',5,3) /* PT5_5 */ +#define PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define ADC1_B14_PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define TRIG_OUT6_PIO5_6 N9X_MUX('5',6,1) /* PT5_6 */ +#define LPTMR1_ALT2_PIO5_6 N9X_MUX('5',6,2) /* PT5_6 */ +#define TAMPER4_PIO5_6 N9X_MUX('5',6,3) /* PT5_6 */ +#define PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define ADC1_B15_PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define TRIG_IN11_PIO5_7 N9X_MUX('5',7,1) /* PT5_7 */ +#define TAMPER5_PIO5_7 N9X_MUX('5',7,3) /* PT5_7 */ +#endif diff --git a/dts/nxp/mcx/MCXN235VNL-pinctrl.h b/dts/nxp/mcx/MCXN235VNL-pinctrl.h new file mode 100644 index 000000000..7f7587789 --- /dev/null +++ b/dts/nxp/mcx/MCXN235VNL-pinctrl.h @@ -0,0 +1,579 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN235VNL/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN235VNL_ +#define _ZEPHYR_DTS_BINDING_MCXN235VNL_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define CAN1_TXD_PIO1_6 N9X_MUX('1',6,11) /* PT1_6 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define CAN1_RXD_PIO1_7 N9X_MUX('1',7,11) /* PT1_7 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define CAN1_RXD_PIO1_12 N9X_MUX('1',12,11) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define CAN1_TXD_PIO1_13 N9X_MUX('1',13,11) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define PWM1_A3_PIO2_0 N9X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define PWM1_B3_PIO2_1 N9X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define PWM1_A2_PIO2_2 N9X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define PWM1_B2_PIO2_3 N9X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PWM1_A1_PIO2_4 N9X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define PWM1_B1_PIO2_5 N9X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define PWM1_A0_PIO2_6 N9X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define PWM1_B0_PIO2_7 N9X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define PWM1_A0_PIO3_12 N9X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define PWM1_B0_PIO3_13 N9X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define PWM1_A1_PIO3_14 N9X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define PWM1_B1_PIO3_15 N9X_MUX('3',15,5) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define PWM1_A2_PIO3_16 N9X_MUX('3',16,5) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define PWM1_B2_PIO3_17 N9X_MUX('3',17,5) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define PWM1_A3_PIO3_20 N9X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define PWM1_B3_PIO3_21 N9X_MUX('3',21,5) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define ADC0_A0_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define ADC0_B0_PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define ADC1_A0_PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define ADC1_B0_PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define ADC0_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define ADC1_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define ADC1_A7_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define ADC0_A7_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define VREFO_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define USB1_OTG_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define CAN1_RXD_PIO4_15 N9X_MUX('4',15,11) /* PT4_15 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define CAN1_TXD_PIO4_16 N9X_MUX('4',16,11) /* PT4_16 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#endif diff --git a/dts/nxp/mcx/MCXN235VPB-pinctrl.h b/dts/nxp/mcx/MCXN235VPB-pinctrl.h new file mode 100644 index 000000000..3b81ff46e --- /dev/null +++ b/dts/nxp/mcx/MCXN235VPB-pinctrl.h @@ -0,0 +1,742 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN235VPB/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN235VPB_ +#define _ZEPHYR_DTS_BINDING_MCXN235VPB_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define WUU0_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define FC0_P3_PIO0_7 N9X_MUX('0',7,2) /* PT0_7 */ +#define CT_INP3_PIO0_7 N9X_MUX('0',7,4) /* PT0_7 */ +#define PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define ADC0_B14_PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define FC1_P6_PIO0_14 N9X_MUX('0',14,2) /* PT0_14 */ +#define FC0_P2_PIO0_14 N9X_MUX('0',14,3) /* PT0_14 */ +#define CT_INP2_PIO0_14 N9X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_PIO0_14 N9X_MUX('0',14,5) /* PT0_14 */ +#define FLEXIO0_D6_PIO0_14 N9X_MUX('0',14,6) /* PT0_14 */ +#define PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define ADC0_B15_PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define FC0_P3_PIO0_15 N9X_MUX('0',15,3) /* PT0_15 */ +#define CT_INP3_PIO0_15 N9X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_PIO0_15 N9X_MUX('0',15,5) /* PT0_15 */ +#define FLEXIO0_D7_PIO0_15 N9X_MUX('0',15,6) /* PT0_15 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define ADC0_B16_PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define FC1_P0_PIO0_24 N9X_MUX('0',24,2) /* PT0_24 */ +#define CT0_MAT0_PIO0_24 N9X_MUX('0',24,4) /* PT0_24 */ +#define PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define ADC0_B17_PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define FC1_P1_PIO0_25 N9X_MUX('0',25,2) /* PT0_25 */ +#define CT0_MAT1_PIO0_25 N9X_MUX('0',25,4) /* PT0_25 */ +#define PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define ADC0_B18_PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define FC1_P2_PIO0_26 N9X_MUX('0',26,2) /* PT0_26 */ +#define CT0_MAT2_PIO0_26 N9X_MUX('0',26,4) /* PT0_26 */ +#define PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define ADC0_B19_PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define FC1_P3_PIO0_27 N9X_MUX('0',27,2) /* PT0_27 */ +#define CT0_MAT3_PIO0_27 N9X_MUX('0',27,4) /* PT0_27 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define CAN1_TXD_PIO1_6 N9X_MUX('1',6,11) /* PT1_6 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define CAN1_RXD_PIO1_7 N9X_MUX('1',7,11) /* PT1_7 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define CAN1_RXD_PIO1_12 N9X_MUX('1',12,11) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define CAN1_TXD_PIO1_13 N9X_MUX('1',13,11) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define ADC1_A16_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define WUU0_IN14_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define FC5_P0_PIO1_16 N9X_MUX('1',16,2) /* PT1_16 */ +#define FC3_P4_PIO1_16 N9X_MUX('1',16,3) /* PT1_16 */ +#define CT_INP12_PIO1_16 N9X_MUX('1',16,4) /* PT1_16 */ +#define FLEXIO0_D24_PIO1_16 N9X_MUX('1',16,6) /* PT1_16 */ +#define EZH_PIO12_PIO1_16 N9X_MUX('1',16,7) /* PT1_16 */ +#define I3C1_SDA_PIO1_16 N9X_MUX('1',16,10) /* PT1_16 */ +#define PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define ADC1_A17_PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define FC5_P1_PIO1_17 N9X_MUX('1',17,2) /* PT1_17 */ +#define FC3_P5_PIO1_17 N9X_MUX('1',17,3) /* PT1_17 */ +#define CT_INP13_PIO1_17 N9X_MUX('1',17,4) /* PT1_17 */ +#define FLEXIO0_D25_PIO1_17 N9X_MUX('1',17,6) /* PT1_17 */ +#define EZH_PIO13_PIO1_17 N9X_MUX('1',17,7) /* PT1_17 */ +#define I3C1_SCL_PIO1_17 N9X_MUX('1',17,10) /* PT1_17 */ +#define ADC1_A18_PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define FREQME_CLK_IN0_PIO1_18 N9X_MUX('1',18,1) /* PT1_18 */ +#define FC5_P2_PIO1_18 N9X_MUX('1',18,2) /* PT1_18 */ +#define FC3_P6_PIO1_18 N9X_MUX('1',18,3) /* PT1_18 */ +#define CT3_MAT0_PIO1_18 N9X_MUX('1',18,4) /* PT1_18 */ +#define FLEXIO0_D26_PIO1_18 N9X_MUX('1',18,6) /* PT1_18 */ +#define EZH_PIO14_PIO1_18 N9X_MUX('1',18,7) /* PT1_18 */ +#define CAN0_TXD_PIO1_18 N9X_MUX('1',18,11) /* PT1_18 */ +#define PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define ADC1_A19_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define WUU0_IN15_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define FREQME_CLK_IN1_PIO1_19 N9X_MUX('1',19,1) /* PT1_19 */ +#define FC5_P3_PIO1_19 N9X_MUX('1',19,2) /* PT1_19 */ +#define CT3_MAT1_PIO1_19 N9X_MUX('1',19,4) /* PT1_19 */ +#define FLEXIO0_D27_PIO1_19 N9X_MUX('1',19,6) /* PT1_19 */ +#define EZH_PIO15_PIO1_19 N9X_MUX('1',19,7) /* PT1_19 */ +#define CAN0_RXD_PIO1_19 N9X_MUX('1',19,11) /* PT1_19 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define PWM1_A3_PIO2_0 N9X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define PWM1_B3_PIO2_1 N9X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define PWM1_A2_PIO2_2 N9X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define PWM1_B2_PIO2_3 N9X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PWM1_A1_PIO2_4 N9X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define PWM1_B1_PIO2_5 N9X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define PWM1_A0_PIO2_6 N9X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define PWM1_B0_PIO2_7 N9X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO2_8 N9X_MUX('2',8,0) /* PT2_8 */ +#define TRACE_DATA0_PIO2_8 N9X_MUX('2',8,1) /* PT2_8 */ +#define PWM1_X0_PIO2_8 N9X_MUX('2',8,5) /* PT2_8 */ +#define FLEXIO0_D16_PIO2_8 N9X_MUX('2',8,6) /* PT2_8 */ +#define EZH_PIO28_PIO2_8 N9X_MUX('2',8,7) /* PT2_8 */ +#define SAI1_TXD0_PIO2_8 N9X_MUX('2',8,10) /* PT2_8 */ +#define PIO2_9 N9X_MUX('2',9,0) /* PT2_9 */ +#define TRACE_DATA1_PIO2_9 N9X_MUX('2',9,1) /* PT2_9 */ +#define PWM1_X1_PIO2_9 N9X_MUX('2',9,5) /* PT2_9 */ +#define FLEXIO0_D17_PIO2_9 N9X_MUX('2',9,6) /* PT2_9 */ +#define EZH_PIO29_PIO2_9 N9X_MUX('2',9,7) /* PT2_9 */ +#define SAI1_RXD0_PIO2_9 N9X_MUX('2',9,10) /* PT2_9 */ +#define PIO2_10 N9X_MUX('2',10,0) /* PT2_10 */ +#define TRACE_DATA2_PIO2_10 N9X_MUX('2',10,1) /* PT2_10 */ +#define PWM1_X2_PIO2_10 N9X_MUX('2',10,5) /* PT2_10 */ +#define FLEXIO0_D18_PIO2_10 N9X_MUX('2',10,6) /* PT2_10 */ +#define EZH_PIO31_PIO2_10 N9X_MUX('2',10,7) /* PT2_10 */ +#define SAI1_RXD1_PIO2_10 N9X_MUX('2',10,10) /* PT2_10 */ +#define PIO2_11 N9X_MUX('2',11,0) /* PT2_11 */ +#define TRACE_DATA3_PIO2_11 N9X_MUX('2',11,1) /* PT2_11 */ +#define PWM1_X3_PIO2_11 N9X_MUX('2',11,5) /* PT2_11 */ +#define FLEXIO0_D19_PIO2_11 N9X_MUX('2',11,6) /* PT2_11 */ +#define EZH_PIO30_PIO2_11 N9X_MUX('2',11,7) /* PT2_11 */ +#define SAI1_TXD1_PIO2_11 N9X_MUX('2',11,10) /* PT2_11 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_2 N9X_MUX('3',2,0) /* PT3_2 */ +#define FC7_P0_PIO3_2 N9X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_PIO3_2 N9X_MUX('3',2,4) /* PT3_2 */ +#define PWM0_X0_PIO3_2 N9X_MUX('3',2,5) /* PT3_2 */ +#define FLEXIO0_D10_PIO3_2 N9X_MUX('3',2,6) /* PT3_2 */ +#define EZH_PIO2_PIO3_2 N9X_MUX('3',2,7) /* PT3_2 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define PWM1_A0_PIO3_12 N9X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define PWM1_B0_PIO3_13 N9X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define PWM1_A1_PIO3_14 N9X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define PWM1_B1_PIO3_15 N9X_MUX('3',15,5) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define PWM1_A2_PIO3_16 N9X_MUX('3',16,5) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define PWM1_B2_PIO3_17 N9X_MUX('3',17,5) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define PWM1_A3_PIO3_20 N9X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define PWM1_B3_PIO3_21 N9X_MUX('3',21,5) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO3_22 N9X_MUX('3',22,0) /* PT3_22 */ +#define FC6_P2_PIO3_22 N9X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_PIO3_22 N9X_MUX('3',22,4) /* PT3_22 */ +#define PWM1_X2_PIO3_22 N9X_MUX('3',22,5) /* PT3_22 */ +#define FLEXIO0_D30_PIO3_22 N9X_MUX('3',22,6) /* PT3_22 */ +#define EZH_PIO22_PIO3_22 N9X_MUX('3',22,7) /* PT3_22 */ +#define SAI1_RXD1_PIO3_22 N9X_MUX('3',22,10) /* PT3_22 */ +#define PIO3_23 N9X_MUX('3',23,0) /* PT3_23 */ +#define FC6_P3_PIO3_23 N9X_MUX('3',23,3) /* PT3_23 */ +#define CT_INP11_PIO3_23 N9X_MUX('3',23,4) /* PT3_23 */ +#define PWM1_X3_PIO3_23 N9X_MUX('3',23,5) /* PT3_23 */ +#define FLEXIO0_D31_PIO3_23 N9X_MUX('3',23,6) /* PT3_23 */ +#define EZH_PIO23_PIO3_23 N9X_MUX('3',23,7) /* PT3_23 */ +#define SAI1_TXD1_PIO3_23 N9X_MUX('3',23,10) /* PT3_23 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define ADC0_A0_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define ADC0_B0_PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define ADC1_A0_PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define ADC1_B0_PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define ADC0_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define ADC1_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define USB1_OTG_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_14 N9X_MUX('4',14,0) /* PT4_14 */ +#define CT4_MAT2_PIO4_14 N9X_MUX('4',14,4) /* PT4_14 */ +#define FLEXIO0_D22_PIO4_14 N9X_MUX('4',14,6) /* PT4_14 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define CAN1_RXD_PIO4_15 N9X_MUX('4',15,11) /* PT4_15 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define CAN1_TXD_PIO4_16 N9X_MUX('4',16,11) /* PT4_16 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PIO4_18 N9X_MUX('4',18,0) /* PT4_18 */ +#define CT3_MAT2_PIO4_18 N9X_MUX('4',18,4) /* PT4_18 */ +#define FLEXIO0_D26_PIO4_18 N9X_MUX('4',18,6) /* PT4_18 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define PIO4_22 N9X_MUX('4',22,0) /* PT4_22 */ +#define CT2_MAT2_PIO4_22 N9X_MUX('4',22,4) /* PT4_22 */ +#define FLEXIO0_D30_PIO4_22 N9X_MUX('4',22,6) /* PT4_22 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#define ADC1_B12_PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define TRIG_OUT7_PIO5_4 N9X_MUX('5',4,1) /* PT5_4 */ +#define SPC_LPREQ_PIO5_4 N9X_MUX('5',4,2) /* PT5_4 */ +#define TAMPER2_PIO5_4 N9X_MUX('5',4,3) /* PT5_4 */ +#define PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define ADC1_B13_PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define TRIG_IN10_PIO5_5 N9X_MUX('5',5,1) /* PT5_5 */ +#define LPTMR0_ALT2_PIO5_5 N9X_MUX('5',5,2) /* PT5_5 */ +#define TAMPER3_PIO5_5 N9X_MUX('5',5,3) /* PT5_5 */ +#define PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define ADC1_B14_PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define TRIG_OUT6_PIO5_6 N9X_MUX('5',6,1) /* PT5_6 */ +#define LPTMR1_ALT2_PIO5_6 N9X_MUX('5',6,2) /* PT5_6 */ +#define TAMPER4_PIO5_6 N9X_MUX('5',6,3) /* PT5_6 */ +#define PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define ADC1_B15_PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define TRIG_IN11_PIO5_7 N9X_MUX('5',7,1) /* PT5_7 */ +#define TAMPER5_PIO5_7 N9X_MUX('5',7,3) /* PT5_7 */ +#endif diff --git a/dts/nxp/mcx/MCXN236VPB-pinctrl.h b/dts/nxp/mcx/MCXN236VPB-pinctrl.h new file mode 100644 index 000000000..0e3f49d3c --- /dev/null +++ b/dts/nxp/mcx/MCXN236VPB-pinctrl.h @@ -0,0 +1,742 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN236VPB/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN236VPB_ +#define _ZEPHYR_DTS_BINDING_MCXN236VPB_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define WUU0_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define FC0_P3_PIO0_7 N9X_MUX('0',7,2) /* PT0_7 */ +#define CT_INP3_PIO0_7 N9X_MUX('0',7,4) /* PT0_7 */ +#define PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define ADC0_B14_PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define FC1_P6_PIO0_14 N9X_MUX('0',14,2) /* PT0_14 */ +#define FC0_P2_PIO0_14 N9X_MUX('0',14,3) /* PT0_14 */ +#define CT_INP2_PIO0_14 N9X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_PIO0_14 N9X_MUX('0',14,5) /* PT0_14 */ +#define FLEXIO0_D6_PIO0_14 N9X_MUX('0',14,6) /* PT0_14 */ +#define PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define ADC0_B15_PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define FC0_P3_PIO0_15 N9X_MUX('0',15,3) /* PT0_15 */ +#define CT_INP3_PIO0_15 N9X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_PIO0_15 N9X_MUX('0',15,5) /* PT0_15 */ +#define FLEXIO0_D7_PIO0_15 N9X_MUX('0',15,6) /* PT0_15 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define ADC0_B16_PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define FC1_P0_PIO0_24 N9X_MUX('0',24,2) /* PT0_24 */ +#define CT0_MAT0_PIO0_24 N9X_MUX('0',24,4) /* PT0_24 */ +#define PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define ADC0_B17_PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define FC1_P1_PIO0_25 N9X_MUX('0',25,2) /* PT0_25 */ +#define CT0_MAT1_PIO0_25 N9X_MUX('0',25,4) /* PT0_25 */ +#define ADC0_B18_PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define FC1_P2_PIO0_26 N9X_MUX('0',26,2) /* PT0_26 */ +#define CT0_MAT2_PIO0_26 N9X_MUX('0',26,4) /* PT0_26 */ +#define PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define ADC0_B19_PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define FC1_P3_PIO0_27 N9X_MUX('0',27,2) /* PT0_27 */ +#define CT0_MAT3_PIO0_27 N9X_MUX('0',27,4) /* PT0_27 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define CAN1_TXD_PIO1_6 N9X_MUX('1',6,11) /* PT1_6 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define CAN1_RXD_PIO1_7 N9X_MUX('1',7,11) /* PT1_7 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define CAN1_RXD_PIO1_12 N9X_MUX('1',12,11) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define CAN1_TXD_PIO1_13 N9X_MUX('1',13,11) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define WUU0_IN14_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define ADC1_A16_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define FC5_P0_PIO1_16 N9X_MUX('1',16,2) /* PT1_16 */ +#define FC3_P4_PIO1_16 N9X_MUX('1',16,3) /* PT1_16 */ +#define CT_INP12_PIO1_16 N9X_MUX('1',16,4) /* PT1_16 */ +#define FLEXIO0_D24_PIO1_16 N9X_MUX('1',16,6) /* PT1_16 */ +#define EZH_PIO12_PIO1_16 N9X_MUX('1',16,7) /* PT1_16 */ +#define I3C1_SDA_PIO1_16 N9X_MUX('1',16,10) /* PT1_16 */ +#define PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define ADC1_A17_PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define FC5_P1_PIO1_17 N9X_MUX('1',17,2) /* PT1_17 */ +#define FC3_P5_PIO1_17 N9X_MUX('1',17,3) /* PT1_17 */ +#define CT_INP13_PIO1_17 N9X_MUX('1',17,4) /* PT1_17 */ +#define FLEXIO0_D25_PIO1_17 N9X_MUX('1',17,6) /* PT1_17 */ +#define EZH_PIO13_PIO1_17 N9X_MUX('1',17,7) /* PT1_17 */ +#define I3C1_SCL_PIO1_17 N9X_MUX('1',17,10) /* PT1_17 */ +#define PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define ADC1_A18_PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define FREQME_CLK_IN0_PIO1_18 N9X_MUX('1',18,1) /* PT1_18 */ +#define FC5_P2_PIO1_18 N9X_MUX('1',18,2) /* PT1_18 */ +#define FC3_P6_PIO1_18 N9X_MUX('1',18,3) /* PT1_18 */ +#define CT3_MAT0_PIO1_18 N9X_MUX('1',18,4) /* PT1_18 */ +#define FLEXIO0_D26_PIO1_18 N9X_MUX('1',18,6) /* PT1_18 */ +#define EZH_PIO14_PIO1_18 N9X_MUX('1',18,7) /* PT1_18 */ +#define CAN0_TXD_PIO1_18 N9X_MUX('1',18,11) /* PT1_18 */ +#define PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define ADC1_A19_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define WUU0_IN15_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define FREQME_CLK_IN1_PIO1_19 N9X_MUX('1',19,1) /* PT1_19 */ +#define FC5_P3_PIO1_19 N9X_MUX('1',19,2) /* PT1_19 */ +#define CT3_MAT1_PIO1_19 N9X_MUX('1',19,4) /* PT1_19 */ +#define FLEXIO0_D27_PIO1_19 N9X_MUX('1',19,6) /* PT1_19 */ +#define EZH_PIO15_PIO1_19 N9X_MUX('1',19,7) /* PT1_19 */ +#define CAN0_RXD_PIO1_19 N9X_MUX('1',19,11) /* PT1_19 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define PWM1_A3_PIO2_0 N9X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define PWM1_B3_PIO2_1 N9X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define PWM1_A2_PIO2_2 N9X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define PWM1_B2_PIO2_3 N9X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PWM1_A1_PIO2_4 N9X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define PWM1_B1_PIO2_5 N9X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define PWM1_A0_PIO2_6 N9X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define PWM1_B0_PIO2_7 N9X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO2_8 N9X_MUX('2',8,0) /* PT2_8 */ +#define TRACE_DATA0_PIO2_8 N9X_MUX('2',8,1) /* PT2_8 */ +#define PWM1_X0_PIO2_8 N9X_MUX('2',8,5) /* PT2_8 */ +#define FLEXIO0_D16_PIO2_8 N9X_MUX('2',8,6) /* PT2_8 */ +#define EZH_PIO28_PIO2_8 N9X_MUX('2',8,7) /* PT2_8 */ +#define SAI1_TXD0_PIO2_8 N9X_MUX('2',8,10) /* PT2_8 */ +#define PIO2_9 N9X_MUX('2',9,0) /* PT2_9 */ +#define TRACE_DATA1_PIO2_9 N9X_MUX('2',9,1) /* PT2_9 */ +#define PWM1_X1_PIO2_9 N9X_MUX('2',9,5) /* PT2_9 */ +#define FLEXIO0_D17_PIO2_9 N9X_MUX('2',9,6) /* PT2_9 */ +#define EZH_PIO29_PIO2_9 N9X_MUX('2',9,7) /* PT2_9 */ +#define SAI1_RXD0_PIO2_9 N9X_MUX('2',9,10) /* PT2_9 */ +#define PIO2_10 N9X_MUX('2',10,0) /* PT2_10 */ +#define TRACE_DATA2_PIO2_10 N9X_MUX('2',10,1) /* PT2_10 */ +#define PWM1_X2_PIO2_10 N9X_MUX('2',10,5) /* PT2_10 */ +#define FLEXIO0_D18_PIO2_10 N9X_MUX('2',10,6) /* PT2_10 */ +#define EZH_PIO31_PIO2_10 N9X_MUX('2',10,7) /* PT2_10 */ +#define SAI1_RXD1_PIO2_10 N9X_MUX('2',10,10) /* PT2_10 */ +#define PIO2_11 N9X_MUX('2',11,0) /* PT2_11 */ +#define TRACE_DATA3_PIO2_11 N9X_MUX('2',11,1) /* PT2_11 */ +#define PWM1_X3_PIO2_11 N9X_MUX('2',11,5) /* PT2_11 */ +#define FLEXIO0_D19_PIO2_11 N9X_MUX('2',11,6) /* PT2_11 */ +#define EZH_PIO30_PIO2_11 N9X_MUX('2',11,7) /* PT2_11 */ +#define SAI1_TXD1_PIO2_11 N9X_MUX('2',11,10) /* PT2_11 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_2 N9X_MUX('3',2,0) /* PT3_2 */ +#define FC7_P0_PIO3_2 N9X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_PIO3_2 N9X_MUX('3',2,4) /* PT3_2 */ +#define PWM0_X0_PIO3_2 N9X_MUX('3',2,5) /* PT3_2 */ +#define FLEXIO0_D10_PIO3_2 N9X_MUX('3',2,6) /* PT3_2 */ +#define EZH_PIO2_PIO3_2 N9X_MUX('3',2,7) /* PT3_2 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define PWM1_A0_PIO3_12 N9X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define PWM1_B0_PIO3_13 N9X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define PWM1_A1_PIO3_14 N9X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define PWM1_B1_PIO3_15 N9X_MUX('3',15,5) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define PWM1_A2_PIO3_16 N9X_MUX('3',16,5) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define PWM1_B2_PIO3_17 N9X_MUX('3',17,5) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define PWM1_A3_PIO3_20 N9X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define PWM1_B3_PIO3_21 N9X_MUX('3',21,5) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO3_22 N9X_MUX('3',22,0) /* PT3_22 */ +#define FC6_P2_PIO3_22 N9X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_PIO3_22 N9X_MUX('3',22,4) /* PT3_22 */ +#define PWM1_X2_PIO3_22 N9X_MUX('3',22,5) /* PT3_22 */ +#define FLEXIO0_D30_PIO3_22 N9X_MUX('3',22,6) /* PT3_22 */ +#define EZH_PIO22_PIO3_22 N9X_MUX('3',22,7) /* PT3_22 */ +#define SAI1_RXD1_PIO3_22 N9X_MUX('3',22,10) /* PT3_22 */ +#define PIO3_23 N9X_MUX('3',23,0) /* PT3_23 */ +#define FC6_P3_PIO3_23 N9X_MUX('3',23,3) /* PT3_23 */ +#define CT_INP11_PIO3_23 N9X_MUX('3',23,4) /* PT3_23 */ +#define PWM1_X3_PIO3_23 N9X_MUX('3',23,5) /* PT3_23 */ +#define FLEXIO0_D31_PIO3_23 N9X_MUX('3',23,6) /* PT3_23 */ +#define EZH_PIO23_PIO3_23 N9X_MUX('3',23,7) /* PT3_23 */ +#define SAI1_TXD1_PIO3_23 N9X_MUX('3',23,10) /* PT3_23 */ +#define ADC0_A0_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define ADC0_B0_PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define ADC1_A0_PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define ADC1_B0_PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define ADC1_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define ADC0_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_OTG_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_14 N9X_MUX('4',14,0) /* PT4_14 */ +#define CT4_MAT2_PIO4_14 N9X_MUX('4',14,4) /* PT4_14 */ +#define FLEXIO0_D22_PIO4_14 N9X_MUX('4',14,6) /* PT4_14 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define CAN1_RXD_PIO4_15 N9X_MUX('4',15,11) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define CAN1_TXD_PIO4_16 N9X_MUX('4',16,11) /* PT4_16 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PIO4_18 N9X_MUX('4',18,0) /* PT4_18 */ +#define CT3_MAT2_PIO4_18 N9X_MUX('4',18,4) /* PT4_18 */ +#define FLEXIO0_D26_PIO4_18 N9X_MUX('4',18,6) /* PT4_18 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define PIO4_22 N9X_MUX('4',22,0) /* PT4_22 */ +#define CT2_MAT2_PIO4_22 N9X_MUX('4',22,4) /* PT4_22 */ +#define FLEXIO0_D30_PIO4_22 N9X_MUX('4',22,6) /* PT4_22 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#define PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define ADC1_B12_PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define TRIG_OUT7_PIO5_4 N9X_MUX('5',4,1) /* PT5_4 */ +#define SPC_LPREQ_PIO5_4 N9X_MUX('5',4,2) /* PT5_4 */ +#define TAMPER2_PIO5_4 N9X_MUX('5',4,3) /* PT5_4 */ +#define PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define ADC1_B13_PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define TRIG_IN10_PIO5_5 N9X_MUX('5',5,1) /* PT5_5 */ +#define LPTMR0_ALT2_PIO5_5 N9X_MUX('5',5,2) /* PT5_5 */ +#define TAMPER3_PIO5_5 N9X_MUX('5',5,3) /* PT5_5 */ +#define PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define ADC1_B14_PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define TRIG_OUT6_PIO5_6 N9X_MUX('5',6,1) /* PT5_6 */ +#define LPTMR1_ALT2_PIO5_6 N9X_MUX('5',6,2) /* PT5_6 */ +#define TAMPER4_PIO5_6 N9X_MUX('5',6,3) /* PT5_6 */ +#define ADC1_B15_PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define TRIG_IN11_PIO5_7 N9X_MUX('5',7,1) /* PT5_7 */ +#define TAMPER5_PIO5_7 N9X_MUX('5',7,3) /* PT5_7 */ +#endif diff --git a/dts/nxp/mcx/MCXN546VDF-pinctrl.h b/dts/nxp/mcx/MCXN546VDF-pinctrl.h new file mode 100644 index 000000000..f8fe3a2cf --- /dev/null +++ b/dts/nxp/mcx/MCXN546VDF-pinctrl.h @@ -0,0 +1,1003 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN546VDF/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN546VDF_ +#define _ZEPHYR_DTS_BINDING_MCXN546VDF_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define TSI0_CH8_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define TSI0_CH9_PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define TSI0_CH10_PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define WUU0_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define FC0_P3_PIO0_7 N9X_MUX('0',7,2) /* PT0_7 */ +#define CT_INP3_PIO0_7 N9X_MUX('0',7,4) /* PT0_7 */ +#define PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define ADC0_B8_PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define FC0_P4_PIO0_8 N9X_MUX('0',8,2) /* PT0_8 */ +#define CT_INP0_PIO0_8 N9X_MUX('0',8,4) /* PT0_8 */ +#define FLEXIO0_D0_PIO0_8 N9X_MUX('0',8,6) /* PT0_8 */ +#define PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define ADC0_B9_PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define FC0_P5_PIO0_9 N9X_MUX('0',9,2) /* PT0_9 */ +#define CT_INP1_PIO0_9 N9X_MUX('0',9,4) /* PT0_9 */ +#define FLEXIO0_D1_PIO0_9 N9X_MUX('0',9,6) /* PT0_9 */ +#define PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define ADC0_B10_PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define FC0_P6_PIO0_10 N9X_MUX('0',10,2) /* PT0_10 */ +#define CT0_MAT0_PIO0_10 N9X_MUX('0',10,4) /* PT0_10 */ +#define FLEXIO0_D2_PIO0_10 N9X_MUX('0',10,6) /* PT0_10 */ +#define PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define ADC0_B11_PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define CT0_MAT1_PIO0_11 N9X_MUX('0',11,4) /* PT0_11 */ +#define FLEXIO0_D3_PIO0_11 N9X_MUX('0',11,6) /* PT0_11 */ +#define PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define ADC0_B12_PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define FC1_P4_PIO0_12 N9X_MUX('0',12,2) /* PT0_12 */ +#define FC0_P0_PIO0_12 N9X_MUX('0',12,3) /* PT0_12 */ +#define CT0_MAT2_PIO0_12 N9X_MUX('0',12,4) /* PT0_12 */ +#define FLEXIO0_D4_PIO0_12 N9X_MUX('0',12,6) /* PT0_12 */ +#define PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define ADC0_B13_PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define FC1_P5_PIO0_13 N9X_MUX('0',13,2) /* PT0_13 */ +#define FC0_P1_PIO0_13 N9X_MUX('0',13,3) /* PT0_13 */ +#define CT0_MAT3_PIO0_13 N9X_MUX('0',13,4) /* PT0_13 */ +#define FLEXIO0_D5_PIO0_13 N9X_MUX('0',13,6) /* PT0_13 */ +#define ADC0_B14_PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define FC1_P6_PIO0_14 N9X_MUX('0',14,2) /* PT0_14 */ +#define FC0_P2_PIO0_14 N9X_MUX('0',14,3) /* PT0_14 */ +#define CT_INP2_PIO0_14 N9X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_PIO0_14 N9X_MUX('0',14,5) /* PT0_14 */ +#define FLEXIO0_D6_PIO0_14 N9X_MUX('0',14,6) /* PT0_14 */ +#define PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define ADC0_B15_PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define FC0_P3_PIO0_15 N9X_MUX('0',15,3) /* PT0_15 */ +#define CT_INP3_PIO0_15 N9X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_PIO0_15 N9X_MUX('0',15,5) /* PT0_15 */ +#define FLEXIO0_D7_PIO0_15 N9X_MUX('0',15,6) /* PT0_15 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define TSI0_CH11_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define TSI0_CH12_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define TSI0_CH13_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define TSI0_CH14_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define TSI0_CH15_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define TSI0_CH16_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define ADC0_B16_PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define FC1_P0_PIO0_24 N9X_MUX('0',24,2) /* PT0_24 */ +#define CT0_MAT0_PIO0_24 N9X_MUX('0',24,4) /* PT0_24 */ +#define PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define ADC0_B17_PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define FC1_P1_PIO0_25 N9X_MUX('0',25,2) /* PT0_25 */ +#define CT0_MAT1_PIO0_25 N9X_MUX('0',25,4) /* PT0_25 */ +#define PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define ADC0_B18_PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define FC1_P2_PIO0_26 N9X_MUX('0',26,2) /* PT0_26 */ +#define CT0_MAT2_PIO0_26 N9X_MUX('0',26,4) /* PT0_26 */ +#define PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define ADC0_B19_PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define FC1_P3_PIO0_27 N9X_MUX('0',27,2) /* PT0_27 */ +#define CT0_MAT3_PIO0_27 N9X_MUX('0',27,4) /* PT0_27 */ +#define PIO0_28 N9X_MUX('0',28,0) /* PT0_28 */ +#define ADC0_B20_PIO0_28 N9X_MUX('0',28,0) /* PT0_28 */ +#define FC1_P4_PIO0_28 N9X_MUX('0',28,2) /* PT0_28 */ +#define FC0_P4_PIO0_28 N9X_MUX('0',28,3) /* PT0_28 */ +#define CT_INP0_PIO0_28 N9X_MUX('0',28,4) /* PT0_28 */ +#define PIO0_29 N9X_MUX('0',29,0) /* PT0_29 */ +#define ADC0_B21_PIO0_29 N9X_MUX('0',29,0) /* PT0_29 */ +#define FC1_P5_PIO0_29 N9X_MUX('0',29,2) /* PT0_29 */ +#define FC0_P5_PIO0_29 N9X_MUX('0',29,3) /* PT0_29 */ +#define CT_INP1_PIO0_29 N9X_MUX('0',29,4) /* PT0_29 */ +#define PIO0_30 N9X_MUX('0',30,0) /* PT0_30 */ +#define ADC0_B22_PIO0_30 N9X_MUX('0',30,0) /* PT0_30 */ +#define FC1_P6_PIO0_30 N9X_MUX('0',30,2) /* PT0_30 */ +#define FC0_P6_PIO0_30 N9X_MUX('0',30,3) /* PT0_30 */ +#define CT_INP2_PIO0_30 N9X_MUX('0',30,4) /* PT0_30 */ +#define ADC0_B23_PIO0_31 N9X_MUX('0',31,0) /* PT0_31 */ +#define PIO0_31 N9X_MUX('0',31,0) /* PT0_31 */ +#define CT_INP3_PIO0_31 N9X_MUX('0',31,4) /* PT0_31 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TSI0_CH0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define SCT0_OUT6_PIO1_0 N9X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define TSI0_CH1_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define SCT0_OUT7_PIO1_1 N9X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TSI0_CH2_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define SCT0_IN6_PIO1_2 N9X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define ENET0_MDC_PIO1_2 N9X_MUX('1',2,9) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TSI0_CH3_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define SCT0_IN7_PIO1_3 N9X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define ENET0_MDIO_PIO1_3 N9X_MUX('1',3,9) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define TSI0_CH4_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define SCT0_OUT0_PIO1_4 N9X_MUX('1',4,5) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define ENET0_TX_CLK_PIO1_4 N9X_MUX('1',4,9) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define TSI0_CH5_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define SCT0_OUT1_PIO1_5 N9X_MUX('1',5,5) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define ENET0_TXEN_PIO1_5 N9X_MUX('1',5,9) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TSI0_CH6_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define SCT0_IN0_PIO1_6 N9X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define ENET0_TXD0_PIO1_6 N9X_MUX('1',6,9) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define TSI0_CH7_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define SCT0_IN1_PIO1_7 N9X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define PLU_CLK_PIO1_7 N9X_MUX('1',7,8) /* PT1_7 */ +#define ENET0_TXD1_PIO1_7 N9X_MUX('1',7,9) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TSI0_CH17_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define SCT0_OUT2_PIO1_8 N9X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define PLU_OUT0_PIO1_8 N9X_MUX('1',8,8) /* PT1_8 */ +#define ENET0_TXD2_PIO1_8 N9X_MUX('1',8,9) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TSI0_CH18_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define SCT0_OUT3_PIO1_9 N9X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define PLU_OUT1_PIO1_9 N9X_MUX('1',9,8) /* PT1_9 */ +#define ENET0_TXD3_PIO1_9 N9X_MUX('1',9,9) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TSI0_CH19_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define SCT0_IN2_PIO1_10 N9X_MUX('1',10,5) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define PLU_IN0_PIO1_10 N9X_MUX('1',10,8) /* PT1_10 */ +#define ENET0_TXER_PIO1_10 N9X_MUX('1',10,9) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TSI0_CH20_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define SCT0_IN3_PIO1_11 N9X_MUX('1',11,5) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define PLU_IN1_PIO1_11 N9X_MUX('1',11,8) /* PT1_11 */ +#define ENET0_RX_CLK_PIO1_11 N9X_MUX('1',11,9) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TSI0_CH21_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define SCT0_OUT4_PIO1_12 N9X_MUX('1',12,5) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define PLU_OUT2_PIO1_12 N9X_MUX('1',12,8) /* PT1_12 */ +#define ENET0_RXER_PIO1_12 N9X_MUX('1',12,9) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TSI0_CH22_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define SCT0_OUT5_PIO1_13 N9X_MUX('1',13,5) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define PLU_OUT3_PIO1_13 N9X_MUX('1',13,8) /* PT1_13 */ +#define ENET0_RXDV_PIO1_13 N9X_MUX('1',13,9) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define TSI0_CH23_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define SCT0_IN4_PIO1_14 N9X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PLU_IN2_PIO1_14 N9X_MUX('1',14,8) /* PT1_14 */ +#define ENET0_RXD0_PIO1_14 N9X_MUX('1',14,9) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define TSI0_CH24_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define SCT0_IN5_PIO1_15 N9X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define PLU_IN3_PIO1_15 N9X_MUX('1',15,8) /* PT1_15 */ +#define ENET0_RXD1_PIO1_15 N9X_MUX('1',15,9) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define WUU0_IN14_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define ADC1_A16_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define FC5_P0_PIO1_16 N9X_MUX('1',16,2) /* PT1_16 */ +#define FC3_P4_PIO1_16 N9X_MUX('1',16,3) /* PT1_16 */ +#define CT_INP12_PIO1_16 N9X_MUX('1',16,4) /* PT1_16 */ +#define SCT0_OUT6_PIO1_16 N9X_MUX('1',16,5) /* PT1_16 */ +#define FLEXIO0_D24_PIO1_16 N9X_MUX('1',16,6) /* PT1_16 */ +#define EZH_PIO12_PIO1_16 N9X_MUX('1',16,7) /* PT1_16 */ +#define PLU_OUT4_PIO1_16 N9X_MUX('1',16,8) /* PT1_16 */ +#define ENET0_RXD2_PIO1_16 N9X_MUX('1',16,9) /* PT1_16 */ +#define I3C1_SDA_PIO1_16 N9X_MUX('1',16,10) /* PT1_16 */ +#define PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define ADC1_A17_PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define FC5_P1_PIO1_17 N9X_MUX('1',17,2) /* PT1_17 */ +#define FC3_P5_PIO1_17 N9X_MUX('1',17,3) /* PT1_17 */ +#define CT_INP13_PIO1_17 N9X_MUX('1',17,4) /* PT1_17 */ +#define SCT0_OUT7_PIO1_17 N9X_MUX('1',17,5) /* PT1_17 */ +#define FLEXIO0_D25_PIO1_17 N9X_MUX('1',17,6) /* PT1_17 */ +#define EZH_PIO13_PIO1_17 N9X_MUX('1',17,7) /* PT1_17 */ +#define PLU_OUT5_PIO1_17 N9X_MUX('1',17,8) /* PT1_17 */ +#define ENET0_RXD3_PIO1_17 N9X_MUX('1',17,9) /* PT1_17 */ +#define I3C1_SCL_PIO1_17 N9X_MUX('1',17,10) /* PT1_17 */ +#define PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define ADC1_A18_PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define FREQME_CLK_IN0_PIO1_18 N9X_MUX('1',18,1) /* PT1_18 */ +#define FC5_P2_PIO1_18 N9X_MUX('1',18,2) /* PT1_18 */ +#define FC3_P6_PIO1_18 N9X_MUX('1',18,3) /* PT1_18 */ +#define CT3_MAT0_PIO1_18 N9X_MUX('1',18,4) /* PT1_18 */ +#define SCT0_IN6_PIO1_18 N9X_MUX('1',18,5) /* PT1_18 */ +#define FLEXIO0_D26_PIO1_18 N9X_MUX('1',18,6) /* PT1_18 */ +#define EZH_PIO14_PIO1_18 N9X_MUX('1',18,7) /* PT1_18 */ +#define PLU_IN4_PIO1_18 N9X_MUX('1',18,8) /* PT1_18 */ +#define ENET0_COL_PIO1_18 N9X_MUX('1',18,9) /* PT1_18 */ +#define CAN0_TXD_PIO1_18 N9X_MUX('1',18,11) /* PT1_18 */ +#define WUU0_IN15_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define ADC1_A19_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define FREQME_CLK_IN1_PIO1_19 N9X_MUX('1',19,1) /* PT1_19 */ +#define FC5_P3_PIO1_19 N9X_MUX('1',19,2) /* PT1_19 */ +#define CT3_MAT1_PIO1_19 N9X_MUX('1',19,4) /* PT1_19 */ +#define SCT0_IN7_PIO1_19 N9X_MUX('1',19,5) /* PT1_19 */ +#define FLEXIO0_D27_PIO1_19 N9X_MUX('1',19,6) /* PT1_19 */ +#define EZH_PIO15_PIO1_19 N9X_MUX('1',19,7) /* PT1_19 */ +#define PLU_IN5_PIO1_19 N9X_MUX('1',19,8) /* PT1_19 */ +#define ENET0_CRS_PIO1_19 N9X_MUX('1',19,9) /* PT1_19 */ +#define CAN0_RXD_PIO1_19 N9X_MUX('1',19,11) /* PT1_19 */ +#define PIO1_20 N9X_MUX('1',20,0) /* PT1_20 */ +#define CMP1_IN3_PIO1_20 N9X_MUX('1',20,0) /* PT1_20 */ +#define ADC1_A20_PIO1_20 N9X_MUX('1',20,0) /* PT1_20 */ +#define TRIG_IN2_PIO1_20 N9X_MUX('1',20,1) /* PT1_20 */ +#define FC5_P4_PIO1_20 N9X_MUX('1',20,2) /* PT1_20 */ +#define FC4_P0_PIO1_20 N9X_MUX('1',20,3) /* PT1_20 */ +#define CT3_MAT2_PIO1_20 N9X_MUX('1',20,4) /* PT1_20 */ +#define SCT0_OUT8_PIO1_20 N9X_MUX('1',20,5) /* PT1_20 */ +#define FLEXIO0_D28_PIO1_20 N9X_MUX('1',20,6) /* PT1_20 */ +#define EZH_PIO16_PIO1_20 N9X_MUX('1',20,7) /* PT1_20 */ +#define PLU_OUT6_PIO1_20 N9X_MUX('1',20,8) /* PT1_20 */ +#define ENET0_MDC_PIO1_20 N9X_MUX('1',20,9) /* PT1_20 */ +#define PIO1_21 N9X_MUX('1',21,0) /* PT1_21 */ +#define ADC1_A21_PIO1_21 N9X_MUX('1',21,0) /* PT1_21 */ +#define TRIG_OUT2_PIO1_21 N9X_MUX('1',21,1) /* PT1_21 */ +#define FC5_P5_PIO1_21 N9X_MUX('1',21,2) /* PT1_21 */ +#define FC4_P1_PIO1_21 N9X_MUX('1',21,3) /* PT1_21 */ +#define CT3_MAT3_PIO1_21 N9X_MUX('1',21,4) /* PT1_21 */ +#define SCT0_OUT9_PIO1_21 N9X_MUX('1',21,5) /* PT1_21 */ +#define FLEXIO0_D29_PIO1_21 N9X_MUX('1',21,6) /* PT1_21 */ +#define EZH_PIO17_PIO1_21 N9X_MUX('1',21,7) /* PT1_21 */ +#define PLU_OUT7_PIO1_21 N9X_MUX('1',21,8) /* PT1_21 */ +#define ENET0_MDIO_PIO1_21 N9X_MUX('1',21,9) /* PT1_21 */ +#define SAI1_MCLK_PIO1_21 N9X_MUX('1',21,10) /* PT1_21 */ +#define PIO1_22 N9X_MUX('1',22,0) /* PT1_22 */ +#define ADC1_A22_PIO1_22 N9X_MUX('1',22,0) /* PT1_22 */ +#define TRIG_IN3_PIO1_22 N9X_MUX('1',22,1) /* PT1_22 */ +#define FC5_P6_PIO1_22 N9X_MUX('1',22,2) /* PT1_22 */ +#define FC4_P2_PIO1_22 N9X_MUX('1',22,3) /* PT1_22 */ +#define CT_INP14_PIO1_22 N9X_MUX('1',22,4) /* PT1_22 */ +#define SCT0_OUT4_PIO1_22 N9X_MUX('1',22,5) /* PT1_22 */ +#define FLEXIO0_D30_PIO1_22 N9X_MUX('1',22,6) /* PT1_22 */ +#define EZH_PIO18_PIO1_22 N9X_MUX('1',22,7) /* PT1_22 */ +#define PIO1_23 N9X_MUX('1',23,0) /* PT1_23 */ +#define ADC1_A23_PIO1_23 N9X_MUX('1',23,0) /* PT1_23 */ +#define FC4_P3_PIO1_23 N9X_MUX('1',23,3) /* PT1_23 */ +#define CT_INP15_PIO1_23 N9X_MUX('1',23,4) /* PT1_23 */ +#define SCT0_OUT5_PIO1_23 N9X_MUX('1',23,5) /* PT1_23 */ +#define FLEXIO0_D31_PIO1_23 N9X_MUX('1',23,6) /* PT1_23 */ +#define EZH_PIO19_PIO1_23 N9X_MUX('1',23,7) /* PT1_23 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SCT0_OUT8_PIO1_30 N9X_MUX('1',30,5) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define SCT0_OUT9_PIO1_31 N9X_MUX('1',31,5) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define FC9_P6_PIO2_0 N9X_MUX('2',0,2) /* PT2_0 */ +#define SDHC0_D5_PIO2_0 N9X_MUX('2',0,3) /* PT2_0 */ +#define SCT0_IN0_PIO2_0 N9X_MUX('2',0,4) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define FLEXSPI0_B_SS1_b_PIO2_0 N9X_MUX('2',0,8) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define SDHC0_D4_PIO2_1 N9X_MUX('2',1,3) /* PT2_1 */ +#define SCT0_IN1_PIO2_1 N9X_MUX('2',1,4) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define FLEXSPI0_B_DQS_PIO2_1 N9X_MUX('2',1,8) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define FC9_P3_PIO2_2 N9X_MUX('2',2,2) /* PT2_2 */ +#define SDHC0_D1_PIO2_2 N9X_MUX('2',2,3) /* PT2_2 */ +#define SCT0_OUT0_PIO2_2 N9X_MUX('2',2,4) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define FLEXSPI0_B_SS0_b_PIO2_2 N9X_MUX('2',2,8) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define FC9_P1_PIO2_3 N9X_MUX('2',3,2) /* PT2_3 */ +#define SDHC0_D0_PIO2_3 N9X_MUX('2',3,3) /* PT2_3 */ +#define SCT0_OUT1_PIO2_3 N9X_MUX('2',3,4) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define FLEXSPI0_B_SCLK_PIO2_3 N9X_MUX('2',3,8) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define FC9_P0_PIO2_4 N9X_MUX('2',4,2) /* PT2_4 */ +#define SDHC0_CLK_PIO2_4 N9X_MUX('2',4,3) /* PT2_4 */ +#define SCT0_OUT2_PIO2_4 N9X_MUX('2',4,4) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define FLEXSPI0_B_DATA0_PIO2_4 N9X_MUX('2',4,8) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define FC9_P2_PIO2_5 N9X_MUX('2',5,2) /* PT2_5 */ +#define SDHC0_CMD_PIO2_5 N9X_MUX('2',5,3) /* PT2_5 */ +#define SCT0_OUT3_PIO2_5 N9X_MUX('2',5,4) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define FLEXSPI0_B_DATA1_PIO2_5 N9X_MUX('2',5,8) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define FC9_P4_PIO2_6 N9X_MUX('2',6,2) /* PT2_6 */ +#define SDHC0_D3_PIO2_6 N9X_MUX('2',6,3) /* PT2_6 */ +#define SCT0_OUT4_PIO2_6 N9X_MUX('2',6,4) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define FLEXSPI0_B_DATA2_PIO2_6 N9X_MUX('2',6,8) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define FC9_P5_PIO2_7 N9X_MUX('2',7,2) /* PT2_7 */ +#define SDHC0_D2_PIO2_7 N9X_MUX('2',7,3) /* PT2_7 */ +#define SCT0_OUT5_PIO2_7 N9X_MUX('2',7,4) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define FLEXSPI0_B_DATA3_PIO2_7 N9X_MUX('2',7,8) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO2_8 N9X_MUX('2',8,0) /* PT2_8 */ +#define TRACE_DATA0_PIO2_8 N9X_MUX('2',8,1) /* PT2_8 */ +#define SDHC0_D7_PIO2_8 N9X_MUX('2',8,3) /* PT2_8 */ +#define SCT0_IN2_PIO2_8 N9X_MUX('2',8,4) /* PT2_8 */ +#define FLEXIO0_D16_PIO2_8 N9X_MUX('2',8,6) /* PT2_8 */ +#define EZH_PIO28_PIO2_8 N9X_MUX('2',8,7) /* PT2_8 */ +#define FLEXSPI0_B_DATA4_PIO2_8 N9X_MUX('2',8,8) /* PT2_8 */ +#define SAI1_TXD0_PIO2_8 N9X_MUX('2',8,10) /* PT2_8 */ +#define PIO2_9 N9X_MUX('2',9,0) /* PT2_9 */ +#define TRACE_DATA1_PIO2_9 N9X_MUX('2',9,1) /* PT2_9 */ +#define SDHC0_D6_PIO2_9 N9X_MUX('2',9,3) /* PT2_9 */ +#define SCT0_IN3_PIO2_9 N9X_MUX('2',9,4) /* PT2_9 */ +#define FLEXIO0_D17_PIO2_9 N9X_MUX('2',9,6) /* PT2_9 */ +#define EZH_PIO29_PIO2_9 N9X_MUX('2',9,7) /* PT2_9 */ +#define FLEXSPI0_B_DATA5_PIO2_9 N9X_MUX('2',9,8) /* PT2_9 */ +#define SAI1_RXD0_PIO2_9 N9X_MUX('2',9,10) /* PT2_9 */ +#define PIO2_10 N9X_MUX('2',10,0) /* PT2_10 */ +#define TRACE_DATA2_PIO2_10 N9X_MUX('2',10,1) /* PT2_10 */ +#define SCT0_IN4_PIO2_10 N9X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_PIO2_10 N9X_MUX('2',10,6) /* PT2_10 */ +#define EZH_PIO31_PIO2_10 N9X_MUX('2',10,7) /* PT2_10 */ +#define FLEXSPI0_B_DATA6_PIO2_10 N9X_MUX('2',10,8) /* PT2_10 */ +#define SAI1_RXD1_PIO2_10 N9X_MUX('2',10,10) /* PT2_10 */ +#define PIO2_11 N9X_MUX('2',11,0) /* PT2_11 */ +#define TRACE_DATA3_PIO2_11 N9X_MUX('2',11,1) /* PT2_11 */ +#define SCT0_IN5_PIO2_11 N9X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_PIO2_11 N9X_MUX('2',11,6) /* PT2_11 */ +#define EZH_PIO30_PIO2_11 N9X_MUX('2',11,7) /* PT2_11 */ +#define FLEXSPI0_B_DATA7_PIO2_11 N9X_MUX('2',11,8) /* PT2_11 */ +#define SAI1_TXD1_PIO2_11 N9X_MUX('2',11,10) /* PT2_11 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define FLEXSPI0_A_SS0_b_PIO3_0 N9X_MUX('3',0,8) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FLEXSPI0_A_SS1_b_PIO3_1 N9X_MUX('3',1,8) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_2 N9X_MUX('3',2,0) /* PT3_2 */ +#define FC7_P0_PIO3_2 N9X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_PIO3_2 N9X_MUX('3',2,4) /* PT3_2 */ +#define PWM0_X0_PIO3_2 N9X_MUX('3',2,5) /* PT3_2 */ +#define FLEXIO0_D10_PIO3_2 N9X_MUX('3',2,6) /* PT3_2 */ +#define EZH_PIO2_PIO3_2 N9X_MUX('3',2,7) /* PT3_2 */ +#define SIM1_PD_PIO3_2 N9X_MUX('3',2,9) /* PT3_2 */ +#define PIO3_3 N9X_MUX('3',3,0) /* PT3_3 */ +#define FC7_P1_PIO3_3 N9X_MUX('3',3,2) /* PT3_3 */ +#define CT4_MAT1_PIO3_3 N9X_MUX('3',3,4) /* PT3_3 */ +#define PWM0_X1_PIO3_3 N9X_MUX('3',3,5) /* PT3_3 */ +#define FLEXIO0_D11_PIO3_3 N9X_MUX('3',3,6) /* PT3_3 */ +#define EZH_PIO3_PIO3_3 N9X_MUX('3',3,7) /* PT3_3 */ +#define SIM1_RST_PIO3_3 N9X_MUX('3',3,9) /* PT3_3 */ +#define PIO3_4 N9X_MUX('3',4,0) /* PT3_4 */ +#define FC7_P2_PIO3_4 N9X_MUX('3',4,2) /* PT3_4 */ +#define CT_INP18_PIO3_4 N9X_MUX('3',4,4) /* PT3_4 */ +#define PWM0_X2_PIO3_4 N9X_MUX('3',4,5) /* PT3_4 */ +#define FLEXIO0_D12_PIO3_4 N9X_MUX('3',4,6) /* PT3_4 */ +#define EZH_PIO4_PIO3_4 N9X_MUX('3',4,7) /* PT3_4 */ +#define SIM1_CLK_PIO3_4 N9X_MUX('3',4,9) /* PT3_4 */ +#define PIO3_5 N9X_MUX('3',5,0) /* PT3_5 */ +#define FC7_P3_PIO3_5 N9X_MUX('3',5,2) /* PT3_5 */ +#define CT_INP19_PIO3_5 N9X_MUX('3',5,4) /* PT3_5 */ +#define PWM0_X3_PIO3_5 N9X_MUX('3',5,5) /* PT3_5 */ +#define FLEXIO0_D13_PIO3_5 N9X_MUX('3',5,6) /* PT3_5 */ +#define EZH_PIO5_PIO3_5 N9X_MUX('3',5,7) /* PT3_5 */ +#define SIM1_IO_PIO3_5 N9X_MUX('3',5,9) /* PT3_5 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define FLEXSPI0_A_DQS_PIO3_6 N9X_MUX('3',6,8) /* PT3_6 */ +#define SIM1_VCCEN_PIO3_6 N9X_MUX('3',6,9) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define FLEXSPI0_A_SCLK_PIO3_7 N9X_MUX('3',7,8) /* PT3_7 */ +#define SIM0_VCCEN_PIO3_7 N9X_MUX('3',7,9) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define FLEXSPI0_A_DATA0_PIO3_8 N9X_MUX('3',8,8) /* PT3_8 */ +#define SIM0_PD_PIO3_8 N9X_MUX('3',8,9) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define FLEXSPI0_A_DATA1_PIO3_9 N9X_MUX('3',9,8) /* PT3_9 */ +#define SIM0_RST_PIO3_9 N9X_MUX('3',9,9) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define FLEXSPI0_A_DATA2_PIO3_10 N9X_MUX('3',10,8) /* PT3_10 */ +#define SIM0_CLK_PIO3_10 N9X_MUX('3',10,9) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define FLEXSPI0_A_DATA3_PIO3_11 N9X_MUX('3',11,8) /* PT3_11 */ +#define SIM0_IO_PIO3_11 N9X_MUX('3',11,9) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define FLEXSPI0_A_DATA4_PIO3_12 N9X_MUX('3',12,8) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define FLEXSPI0_A_DATA5_PIO3_13 N9X_MUX('3',13,8) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define FC8_P0_PIO3_14 N9X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define FLEXSPI0_A_DATA6_PIO3_14 N9X_MUX('3',14,8) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define FC8_P1_PIO3_15 N9X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define FLEXSPI0_A_DATA7_PIO3_15 N9X_MUX('3',15,8) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define FC8_P2_PIO3_16 N9X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SIM0_CLK_PIO3_16 N9X_MUX('3',16,9) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define FC8_P3_PIO3_17 N9X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SIM0_IO_PIO3_17 N9X_MUX('3',17,9) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define PIO3_18 N9X_MUX('3',18,0) /* PT3_18 */ +#define FC6_P6_PIO3_18 N9X_MUX('3',18,3) /* PT3_18 */ +#define CT2_MAT0_PIO3_18 N9X_MUX('3',18,4) /* PT3_18 */ +#define FLEXIO0_D26_PIO3_18 N9X_MUX('3',18,6) /* PT3_18 */ +#define EZH_PIO18_PIO3_18 N9X_MUX('3',18,7) /* PT3_18 */ +#define SAI1_RX_BCLK_PIO3_18 N9X_MUX('3',18,10) /* PT3_18 */ +#define PIO3_19 N9X_MUX('3',19,0) /* PT3_19 */ +#define FC7_P6_PIO3_19 N9X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_PIO3_19 N9X_MUX('3',19,4) /* PT3_19 */ +#define FLEXIO0_D27_PIO3_19 N9X_MUX('3',19,6) /* PT3_19 */ +#define EZH_PIO19_PIO3_19 N9X_MUX('3',19,7) /* PT3_19 */ +#define SAI1_RX_FS_PIO3_19 N9X_MUX('3',19,10) /* PT3_19 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC8_P4_PIO3_20 N9X_MUX('3',20,2) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SIM0_PD_PIO3_20 N9X_MUX('3',20,9) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC8_P5_PIO3_21 N9X_MUX('3',21,2) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SIM0_RST_PIO3_21 N9X_MUX('3',21,9) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO3_22 N9X_MUX('3',22,0) /* PT3_22 */ +#define FC8_P6_PIO3_22 N9X_MUX('3',22,2) /* PT3_22 */ +#define FC6_P2_PIO3_22 N9X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_PIO3_22 N9X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_PIO3_22 N9X_MUX('3',22,6) /* PT3_22 */ +#define EZH_PIO22_PIO3_22 N9X_MUX('3',22,7) /* PT3_22 */ +#define SIM0_VCCEN_PIO3_22 N9X_MUX('3',22,9) /* PT3_22 */ +#define SAI1_RXD1_PIO3_22 N9X_MUX('3',22,10) /* PT3_22 */ +#define PIO3_23 N9X_MUX('3',23,0) /* PT3_23 */ +#define FC6_P3_PIO3_23 N9X_MUX('3',23,3) /* PT3_23 */ +#define CT_INP11_PIO3_23 N9X_MUX('3',23,4) /* PT3_23 */ +#define FLEXIO0_D31_PIO3_23 N9X_MUX('3',23,6) /* PT3_23 */ +#define EZH_PIO23_PIO3_23 N9X_MUX('3',23,7) /* PT3_23 */ +#define SAI1_TXD1_PIO3_23 N9X_MUX('3',23,10) /* PT3_23 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PLU_IN0_PIO4_0 N9X_MUX('4',0,8) /* PT4_0 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define PLU_IN1_PIO4_1 N9X_MUX('4',1,8) /* PT4_1 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define DAC0_OUT_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define PLU_IN2_PIO4_2 N9X_MUX('4',2,8) /* PT4_2 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PLU_IN3_PIO4_3 N9X_MUX('4',3,8) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define PLU_IN4_PIO4_4 N9X_MUX('4',4,8) /* PT4_4 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PLU_IN5_PIO4_5 N9X_MUX('4',5,8) /* PT4_5 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PLU_CLK_PIO4_6 N9X_MUX('4',6,8) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define USB0_VBUS_DET_PIO4_12 N9X_MUX('4',12,1) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define PLU_OUT0_PIO4_12 N9X_MUX('4',12,8) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define PLU_OUT1_PIO4_13 N9X_MUX('4',13,8) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_14 N9X_MUX('4',14,0) /* PT4_14 */ +#define CT4_MAT2_PIO4_14 N9X_MUX('4',14,4) /* PT4_14 */ +#define FLEXIO0_D22_PIO4_14 N9X_MUX('4',14,6) /* PT4_14 */ +#define PLU_OUT2_PIO4_14 N9X_MUX('4',14,8) /* PT4_14 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define PLU_OUT3_PIO4_15 N9X_MUX('4',15,8) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define PLU_OUT4_PIO4_16 N9X_MUX('4',16,8) /* PT4_16 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PLU_OUT5_PIO4_17 N9X_MUX('4',17,8) /* PT4_17 */ +#define PIO4_18 N9X_MUX('4',18,0) /* PT4_18 */ +#define CT3_MAT2_PIO4_18 N9X_MUX('4',18,4) /* PT4_18 */ +#define FLEXIO0_D26_PIO4_18 N9X_MUX('4',18,6) /* PT4_18 */ +#define PLU_OUT6_PIO4_18 N9X_MUX('4',18,8) /* PT4_18 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define PLU_OUT7_PIO4_19 N9X_MUX('4',19,8) /* PT4_19 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define PIO4_22 N9X_MUX('4',22,0) /* PT4_22 */ +#define CT2_MAT2_PIO4_22 N9X_MUX('4',22,4) /* PT4_22 */ +#define FLEXIO0_D30_PIO4_22 N9X_MUX('4',22,6) /* PT4_22 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#define PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define ADC1_B12_PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define TRIG_OUT7_PIO5_4 N9X_MUX('5',4,1) /* PT5_4 */ +#define SPC_LPREQ_PIO5_4 N9X_MUX('5',4,2) /* PT5_4 */ +#define TAMPER2_PIO5_4 N9X_MUX('5',4,3) /* PT5_4 */ +#define ADC1_B13_PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define TRIG_IN10_PIO5_5 N9X_MUX('5',5,1) /* PT5_5 */ +#define LPTMR0_ALT2_PIO5_5 N9X_MUX('5',5,2) /* PT5_5 */ +#define TAMPER3_PIO5_5 N9X_MUX('5',5,3) /* PT5_5 */ +#define ADC1_B14_PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define TRIG_OUT6_PIO5_6 N9X_MUX('5',6,1) /* PT5_6 */ +#define LPTMR1_ALT2_PIO5_6 N9X_MUX('5',6,2) /* PT5_6 */ +#define TAMPER4_PIO5_6 N9X_MUX('5',6,3) /* PT5_6 */ +#define PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define ADC1_B15_PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define TRIG_IN11_PIO5_7 N9X_MUX('5',7,1) /* PT5_7 */ +#define TAMPER5_PIO5_7 N9X_MUX('5',7,3) /* PT5_7 */ +#define ADC1_B16_PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define TRIG_OUT7_PIO5_8 N9X_MUX('5',8,1) /* PT5_8 */ +#define TAMPER6_PIO5_8 N9X_MUX('5',8,3) /* PT5_8 */ +#define PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define ADC1_B17_PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define TAMPER7_PIO5_9 N9X_MUX('5',9,3) /* PT5_9 */ +#endif diff --git a/dts/nxp/mcx/MCXN546VNL-pinctrl.h b/dts/nxp/mcx/MCXN546VNL-pinctrl.h new file mode 100644 index 000000000..0910afdbe --- /dev/null +++ b/dts/nxp/mcx/MCXN546VNL-pinctrl.h @@ -0,0 +1,695 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN546VNL/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN546VNL_ +#define _ZEPHYR_DTS_BINDING_MCXN546VNL_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define TSI0_CH8_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define TSI0_CH9_PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define TSI0_CH10_PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define TSI0_CH11_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define TSI0_CH12_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define TSI0_CH13_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define TSI0_CH14_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define TSI0_CH15_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define TSI0_CH16_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TSI0_CH0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define SCT0_OUT6_PIO1_0 N9X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define TSI0_CH1_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define SCT0_OUT7_PIO1_1 N9X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TSI0_CH2_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define SCT0_IN6_PIO1_2 N9X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define ENET0_MDC_PIO1_2 N9X_MUX('1',2,9) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TSI0_CH3_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define SCT0_IN7_PIO1_3 N9X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define ENET0_MDIO_PIO1_3 N9X_MUX('1',3,9) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define TSI0_CH4_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define SCT0_OUT0_PIO1_4 N9X_MUX('1',4,5) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define ENET0_TX_CLK_PIO1_4 N9X_MUX('1',4,9) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define TSI0_CH5_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define SCT0_OUT1_PIO1_5 N9X_MUX('1',5,5) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define ENET0_TXEN_PIO1_5 N9X_MUX('1',5,9) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TSI0_CH6_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define SCT0_IN0_PIO1_6 N9X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define ENET0_TXD0_PIO1_6 N9X_MUX('1',6,9) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define TSI0_CH7_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define SCT0_IN1_PIO1_7 N9X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define PLU_CLK_PIO1_7 N9X_MUX('1',7,8) /* PT1_7 */ +#define ENET0_TXD1_PIO1_7 N9X_MUX('1',7,9) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TSI0_CH17_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define SCT0_OUT2_PIO1_8 N9X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define PLU_OUT0_PIO1_8 N9X_MUX('1',8,8) /* PT1_8 */ +#define ENET0_TXD2_PIO1_8 N9X_MUX('1',8,9) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TSI0_CH18_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define SCT0_OUT3_PIO1_9 N9X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define PLU_OUT1_PIO1_9 N9X_MUX('1',9,8) /* PT1_9 */ +#define ENET0_TXD3_PIO1_9 N9X_MUX('1',9,9) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TSI0_CH19_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define SCT0_IN2_PIO1_10 N9X_MUX('1',10,5) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define PLU_IN0_PIO1_10 N9X_MUX('1',10,8) /* PT1_10 */ +#define ENET0_TXER_PIO1_10 N9X_MUX('1',10,9) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TSI0_CH20_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define SCT0_IN3_PIO1_11 N9X_MUX('1',11,5) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define PLU_IN1_PIO1_11 N9X_MUX('1',11,8) /* PT1_11 */ +#define ENET0_RX_CLK_PIO1_11 N9X_MUX('1',11,9) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TSI0_CH21_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define SCT0_OUT4_PIO1_12 N9X_MUX('1',12,5) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define PLU_OUT2_PIO1_12 N9X_MUX('1',12,8) /* PT1_12 */ +#define ENET0_RXER_PIO1_12 N9X_MUX('1',12,9) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TSI0_CH22_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define SCT0_OUT5_PIO1_13 N9X_MUX('1',13,5) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define PLU_OUT3_PIO1_13 N9X_MUX('1',13,8) /* PT1_13 */ +#define ENET0_RXDV_PIO1_13 N9X_MUX('1',13,9) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define TSI0_CH23_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define SCT0_IN4_PIO1_14 N9X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PLU_IN2_PIO1_14 N9X_MUX('1',14,8) /* PT1_14 */ +#define ENET0_RXD0_PIO1_14 N9X_MUX('1',14,9) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define TSI0_CH24_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define SCT0_IN5_PIO1_15 N9X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define PLU_IN3_PIO1_15 N9X_MUX('1',15,8) /* PT1_15 */ +#define ENET0_RXD1_PIO1_15 N9X_MUX('1',15,9) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SCT0_OUT8_PIO1_30 N9X_MUX('1',30,5) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define SCT0_OUT9_PIO1_31 N9X_MUX('1',31,5) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define FC9_P6_PIO2_0 N9X_MUX('2',0,2) /* PT2_0 */ +#define SDHC0_D5_PIO2_0 N9X_MUX('2',0,3) /* PT2_0 */ +#define SCT0_IN0_PIO2_0 N9X_MUX('2',0,4) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define FLEXSPI0_B_SS1_b_PIO2_0 N9X_MUX('2',0,8) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define SDHC0_D4_PIO2_1 N9X_MUX('2',1,3) /* PT2_1 */ +#define SCT0_IN1_PIO2_1 N9X_MUX('2',1,4) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define FLEXSPI0_B_DQS_PIO2_1 N9X_MUX('2',1,8) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define FC9_P3_PIO2_2 N9X_MUX('2',2,2) /* PT2_2 */ +#define SDHC0_D1_PIO2_2 N9X_MUX('2',2,3) /* PT2_2 */ +#define SCT0_OUT0_PIO2_2 N9X_MUX('2',2,4) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define FLEXSPI0_B_SS0_b_PIO2_2 N9X_MUX('2',2,8) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define FC9_P1_PIO2_3 N9X_MUX('2',3,2) /* PT2_3 */ +#define SDHC0_D0_PIO2_3 N9X_MUX('2',3,3) /* PT2_3 */ +#define SCT0_OUT1_PIO2_3 N9X_MUX('2',3,4) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define FLEXSPI0_B_SCLK_PIO2_3 N9X_MUX('2',3,8) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define FC9_P0_PIO2_4 N9X_MUX('2',4,2) /* PT2_4 */ +#define SDHC0_CLK_PIO2_4 N9X_MUX('2',4,3) /* PT2_4 */ +#define SCT0_OUT2_PIO2_4 N9X_MUX('2',4,4) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define FLEXSPI0_B_DATA0_PIO2_4 N9X_MUX('2',4,8) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define FC9_P2_PIO2_5 N9X_MUX('2',5,2) /* PT2_5 */ +#define SDHC0_CMD_PIO2_5 N9X_MUX('2',5,3) /* PT2_5 */ +#define SCT0_OUT3_PIO2_5 N9X_MUX('2',5,4) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define FLEXSPI0_B_DATA1_PIO2_5 N9X_MUX('2',5,8) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define FC9_P4_PIO2_6 N9X_MUX('2',6,2) /* PT2_6 */ +#define SDHC0_D3_PIO2_6 N9X_MUX('2',6,3) /* PT2_6 */ +#define SCT0_OUT4_PIO2_6 N9X_MUX('2',6,4) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define FLEXSPI0_B_DATA2_PIO2_6 N9X_MUX('2',6,8) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define FC9_P5_PIO2_7 N9X_MUX('2',7,2) /* PT2_7 */ +#define SDHC0_D2_PIO2_7 N9X_MUX('2',7,3) /* PT2_7 */ +#define SCT0_OUT5_PIO2_7 N9X_MUX('2',7,4) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define FLEXSPI0_B_DATA3_PIO2_7 N9X_MUX('2',7,8) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define FLEXSPI0_A_SS0_b_PIO3_0 N9X_MUX('3',0,8) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FLEXSPI0_A_SS1_b_PIO3_1 N9X_MUX('3',1,8) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define FLEXSPI0_A_DQS_PIO3_6 N9X_MUX('3',6,8) /* PT3_6 */ +#define SIM1_VCCEN_PIO3_6 N9X_MUX('3',6,9) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define FLEXSPI0_A_SCLK_PIO3_7 N9X_MUX('3',7,8) /* PT3_7 */ +#define SIM0_VCCEN_PIO3_7 N9X_MUX('3',7,9) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define FLEXSPI0_A_DATA0_PIO3_8 N9X_MUX('3',8,8) /* PT3_8 */ +#define SIM0_PD_PIO3_8 N9X_MUX('3',8,9) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define FLEXSPI0_A_DATA1_PIO3_9 N9X_MUX('3',9,8) /* PT3_9 */ +#define SIM0_RST_PIO3_9 N9X_MUX('3',9,9) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define FLEXSPI0_A_DATA2_PIO3_10 N9X_MUX('3',10,8) /* PT3_10 */ +#define SIM0_CLK_PIO3_10 N9X_MUX('3',10,9) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define FLEXSPI0_A_DATA3_PIO3_11 N9X_MUX('3',11,8) /* PT3_11 */ +#define SIM0_IO_PIO3_11 N9X_MUX('3',11,9) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define FLEXSPI0_A_DATA4_PIO3_12 N9X_MUX('3',12,8) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define FLEXSPI0_A_DATA5_PIO3_13 N9X_MUX('3',13,8) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define FC8_P0_PIO3_14 N9X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define FLEXSPI0_A_DATA6_PIO3_14 N9X_MUX('3',14,8) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define FC8_P1_PIO3_15 N9X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define FLEXSPI0_A_DATA7_PIO3_15 N9X_MUX('3',15,8) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define FC8_P2_PIO3_16 N9X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SIM0_CLK_PIO3_16 N9X_MUX('3',16,9) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define FC8_P3_PIO3_17 N9X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SIM0_IO_PIO3_17 N9X_MUX('3',17,9) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC8_P4_PIO3_20 N9X_MUX('3',20,2) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SIM0_PD_PIO3_20 N9X_MUX('3',20,9) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC8_P5_PIO3_21 N9X_MUX('3',21,2) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SIM0_RST_PIO3_21 N9X_MUX('3',21,9) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define ADC0_A0_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PLU_IN0_PIO4_0 N9X_MUX('4',0,8) /* PT4_0 */ +#define ADC0_B0_PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define PLU_IN1_PIO4_1 N9X_MUX('4',1,8) /* PT4_1 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define DAC0_OUT_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define PLU_IN2_PIO4_2 N9X_MUX('4',2,8) /* PT4_2 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PLU_IN3_PIO4_3 N9X_MUX('4',3,8) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define ADC1_A0_PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define PLU_IN4_PIO4_4 N9X_MUX('4',4,8) /* PT4_4 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define ADC1_B0_PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PLU_IN5_PIO4_5 N9X_MUX('4',5,8) /* PT4_5 */ +#define ADC1_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define ADC0_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PLU_CLK_PIO4_6 N9X_MUX('4',6,8) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define ADC0_A7_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define ADC1_A7_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define VREFO_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define USB0_VBUS_DET_PIO4_12 N9X_MUX('4',12,1) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define PLU_OUT0_PIO4_12 N9X_MUX('4',12,8) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define PLU_OUT1_PIO4_13 N9X_MUX('4',13,8) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define PLU_OUT3_PIO4_15 N9X_MUX('4',15,8) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define PLU_OUT4_PIO4_16 N9X_MUX('4',16,8) /* PT4_16 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PLU_OUT5_PIO4_17 N9X_MUX('4',17,8) /* PT4_17 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#endif diff --git a/dts/nxp/mcx/MCXN546VPB-pinctrl.h b/dts/nxp/mcx/MCXN546VPB-pinctrl.h new file mode 100644 index 000000000..c8942bf66 --- /dev/null +++ b/dts/nxp/mcx/MCXN546VPB-pinctrl.h @@ -0,0 +1,933 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN546VPB/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN546VPB_ +#define _ZEPHYR_DTS_BINDING_MCXN546VPB_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define TSI0_CH8_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define TSI0_CH9_PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define TSI0_CH10_PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define WUU0_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define FC0_P3_PIO0_7 N9X_MUX('0',7,2) /* PT0_7 */ +#define CT_INP3_PIO0_7 N9X_MUX('0',7,4) /* PT0_7 */ +#define PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define ADC0_B8_PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define FC0_P4_PIO0_8 N9X_MUX('0',8,2) /* PT0_8 */ +#define CT_INP0_PIO0_8 N9X_MUX('0',8,4) /* PT0_8 */ +#define FLEXIO0_D0_PIO0_8 N9X_MUX('0',8,6) /* PT0_8 */ +#define PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define ADC0_B9_PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define FC0_P5_PIO0_9 N9X_MUX('0',9,2) /* PT0_9 */ +#define CT_INP1_PIO0_9 N9X_MUX('0',9,4) /* PT0_9 */ +#define FLEXIO0_D1_PIO0_9 N9X_MUX('0',9,6) /* PT0_9 */ +#define PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define ADC0_B10_PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define FC0_P6_PIO0_10 N9X_MUX('0',10,2) /* PT0_10 */ +#define CT0_MAT0_PIO0_10 N9X_MUX('0',10,4) /* PT0_10 */ +#define FLEXIO0_D2_PIO0_10 N9X_MUX('0',10,6) /* PT0_10 */ +#define PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define ADC0_B11_PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define CT0_MAT1_PIO0_11 N9X_MUX('0',11,4) /* PT0_11 */ +#define FLEXIO0_D3_PIO0_11 N9X_MUX('0',11,6) /* PT0_11 */ +#define PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define ADC0_B12_PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define FC1_P4_PIO0_12 N9X_MUX('0',12,2) /* PT0_12 */ +#define FC0_P0_PIO0_12 N9X_MUX('0',12,3) /* PT0_12 */ +#define CT0_MAT2_PIO0_12 N9X_MUX('0',12,4) /* PT0_12 */ +#define FLEXIO0_D4_PIO0_12 N9X_MUX('0',12,6) /* PT0_12 */ +#define PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define ADC0_B13_PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define FC1_P5_PIO0_13 N9X_MUX('0',13,2) /* PT0_13 */ +#define FC0_P1_PIO0_13 N9X_MUX('0',13,3) /* PT0_13 */ +#define CT0_MAT3_PIO0_13 N9X_MUX('0',13,4) /* PT0_13 */ +#define FLEXIO0_D5_PIO0_13 N9X_MUX('0',13,6) /* PT0_13 */ +#define ADC0_B14_PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define FC1_P6_PIO0_14 N9X_MUX('0',14,2) /* PT0_14 */ +#define FC0_P2_PIO0_14 N9X_MUX('0',14,3) /* PT0_14 */ +#define CT_INP2_PIO0_14 N9X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_PIO0_14 N9X_MUX('0',14,5) /* PT0_14 */ +#define FLEXIO0_D6_PIO0_14 N9X_MUX('0',14,6) /* PT0_14 */ +#define PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define ADC0_B15_PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define FC0_P3_PIO0_15 N9X_MUX('0',15,3) /* PT0_15 */ +#define CT_INP3_PIO0_15 N9X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_PIO0_15 N9X_MUX('0',15,5) /* PT0_15 */ +#define FLEXIO0_D7_PIO0_15 N9X_MUX('0',15,6) /* PT0_15 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define TSI0_CH11_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define TSI0_CH12_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define TSI0_CH13_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define TSI0_CH14_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define TSI0_CH15_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define TSI0_CH16_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define ADC0_B16_PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define FC1_P0_PIO0_24 N9X_MUX('0',24,2) /* PT0_24 */ +#define CT0_MAT0_PIO0_24 N9X_MUX('0',24,4) /* PT0_24 */ +#define PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define ADC0_B17_PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define FC1_P1_PIO0_25 N9X_MUX('0',25,2) /* PT0_25 */ +#define CT0_MAT1_PIO0_25 N9X_MUX('0',25,4) /* PT0_25 */ +#define PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define ADC0_B18_PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define FC1_P2_PIO0_26 N9X_MUX('0',26,2) /* PT0_26 */ +#define CT0_MAT2_PIO0_26 N9X_MUX('0',26,4) /* PT0_26 */ +#define PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define ADC0_B19_PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define FC1_P3_PIO0_27 N9X_MUX('0',27,2) /* PT0_27 */ +#define CT0_MAT3_PIO0_27 N9X_MUX('0',27,4) /* PT0_27 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TSI0_CH0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define SCT0_OUT6_PIO1_0 N9X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define TSI0_CH1_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define SCT0_OUT7_PIO1_1 N9X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TSI0_CH2_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define SCT0_IN6_PIO1_2 N9X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define ENET0_MDC_PIO1_2 N9X_MUX('1',2,9) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TSI0_CH3_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define SCT0_IN7_PIO1_3 N9X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define ENET0_MDIO_PIO1_3 N9X_MUX('1',3,9) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define TSI0_CH4_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define SCT0_OUT0_PIO1_4 N9X_MUX('1',4,5) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define ENET0_TX_CLK_PIO1_4 N9X_MUX('1',4,9) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define TSI0_CH5_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define SCT0_OUT1_PIO1_5 N9X_MUX('1',5,5) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define ENET0_TXEN_PIO1_5 N9X_MUX('1',5,9) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TSI0_CH6_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define SCT0_IN0_PIO1_6 N9X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define ENET0_TXD0_PIO1_6 N9X_MUX('1',6,9) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define TSI0_CH7_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define SCT0_IN1_PIO1_7 N9X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define PLU_CLK_PIO1_7 N9X_MUX('1',7,8) /* PT1_7 */ +#define ENET0_TXD1_PIO1_7 N9X_MUX('1',7,9) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TSI0_CH17_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define SCT0_OUT2_PIO1_8 N9X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define PLU_OUT0_PIO1_8 N9X_MUX('1',8,8) /* PT1_8 */ +#define ENET0_TXD2_PIO1_8 N9X_MUX('1',8,9) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TSI0_CH18_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define SCT0_OUT3_PIO1_9 N9X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define PLU_OUT1_PIO1_9 N9X_MUX('1',9,8) /* PT1_9 */ +#define ENET0_TXD3_PIO1_9 N9X_MUX('1',9,9) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TSI0_CH19_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define SCT0_IN2_PIO1_10 N9X_MUX('1',10,5) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define PLU_IN0_PIO1_10 N9X_MUX('1',10,8) /* PT1_10 */ +#define ENET0_TXER_PIO1_10 N9X_MUX('1',10,9) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TSI0_CH20_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define SCT0_IN3_PIO1_11 N9X_MUX('1',11,5) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define PLU_IN1_PIO1_11 N9X_MUX('1',11,8) /* PT1_11 */ +#define ENET0_RX_CLK_PIO1_11 N9X_MUX('1',11,9) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TSI0_CH21_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define SCT0_OUT4_PIO1_12 N9X_MUX('1',12,5) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define PLU_OUT2_PIO1_12 N9X_MUX('1',12,8) /* PT1_12 */ +#define ENET0_RXER_PIO1_12 N9X_MUX('1',12,9) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TSI0_CH22_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define SCT0_OUT5_PIO1_13 N9X_MUX('1',13,5) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define PLU_OUT3_PIO1_13 N9X_MUX('1',13,8) /* PT1_13 */ +#define ENET0_RXDV_PIO1_13 N9X_MUX('1',13,9) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define TSI0_CH23_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define SCT0_IN4_PIO1_14 N9X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PLU_IN2_PIO1_14 N9X_MUX('1',14,8) /* PT1_14 */ +#define ENET0_RXD0_PIO1_14 N9X_MUX('1',14,9) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define TSI0_CH24_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define SCT0_IN5_PIO1_15 N9X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define PLU_IN3_PIO1_15 N9X_MUX('1',15,8) /* PT1_15 */ +#define ENET0_RXD1_PIO1_15 N9X_MUX('1',15,9) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define WUU0_IN14_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define ADC1_A16_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define FC5_P0_PIO1_16 N9X_MUX('1',16,2) /* PT1_16 */ +#define FC3_P4_PIO1_16 N9X_MUX('1',16,3) /* PT1_16 */ +#define CT_INP12_PIO1_16 N9X_MUX('1',16,4) /* PT1_16 */ +#define SCT0_OUT6_PIO1_16 N9X_MUX('1',16,5) /* PT1_16 */ +#define FLEXIO0_D24_PIO1_16 N9X_MUX('1',16,6) /* PT1_16 */ +#define EZH_PIO12_PIO1_16 N9X_MUX('1',16,7) /* PT1_16 */ +#define PLU_OUT4_PIO1_16 N9X_MUX('1',16,8) /* PT1_16 */ +#define ENET0_RXD2_PIO1_16 N9X_MUX('1',16,9) /* PT1_16 */ +#define I3C1_SDA_PIO1_16 N9X_MUX('1',16,10) /* PT1_16 */ +#define PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define ADC1_A17_PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define FC5_P1_PIO1_17 N9X_MUX('1',17,2) /* PT1_17 */ +#define FC3_P5_PIO1_17 N9X_MUX('1',17,3) /* PT1_17 */ +#define CT_INP13_PIO1_17 N9X_MUX('1',17,4) /* PT1_17 */ +#define SCT0_OUT7_PIO1_17 N9X_MUX('1',17,5) /* PT1_17 */ +#define FLEXIO0_D25_PIO1_17 N9X_MUX('1',17,6) /* PT1_17 */ +#define EZH_PIO13_PIO1_17 N9X_MUX('1',17,7) /* PT1_17 */ +#define PLU_OUT5_PIO1_17 N9X_MUX('1',17,8) /* PT1_17 */ +#define ENET0_RXD3_PIO1_17 N9X_MUX('1',17,9) /* PT1_17 */ +#define I3C1_SCL_PIO1_17 N9X_MUX('1',17,10) /* PT1_17 */ +#define PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define ADC1_A18_PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define FREQME_CLK_IN0_PIO1_18 N9X_MUX('1',18,1) /* PT1_18 */ +#define FC5_P2_PIO1_18 N9X_MUX('1',18,2) /* PT1_18 */ +#define FC3_P6_PIO1_18 N9X_MUX('1',18,3) /* PT1_18 */ +#define CT3_MAT0_PIO1_18 N9X_MUX('1',18,4) /* PT1_18 */ +#define SCT0_IN6_PIO1_18 N9X_MUX('1',18,5) /* PT1_18 */ +#define FLEXIO0_D26_PIO1_18 N9X_MUX('1',18,6) /* PT1_18 */ +#define EZH_PIO14_PIO1_18 N9X_MUX('1',18,7) /* PT1_18 */ +#define PLU_IN4_PIO1_18 N9X_MUX('1',18,8) /* PT1_18 */ +#define ENET0_COL_PIO1_18 N9X_MUX('1',18,9) /* PT1_18 */ +#define CAN0_TXD_PIO1_18 N9X_MUX('1',18,11) /* PT1_18 */ +#define WUU0_IN15_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define ADC1_A19_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define FREQME_CLK_IN1_PIO1_19 N9X_MUX('1',19,1) /* PT1_19 */ +#define FC5_P3_PIO1_19 N9X_MUX('1',19,2) /* PT1_19 */ +#define CT3_MAT1_PIO1_19 N9X_MUX('1',19,4) /* PT1_19 */ +#define SCT0_IN7_PIO1_19 N9X_MUX('1',19,5) /* PT1_19 */ +#define FLEXIO0_D27_PIO1_19 N9X_MUX('1',19,6) /* PT1_19 */ +#define EZH_PIO15_PIO1_19 N9X_MUX('1',19,7) /* PT1_19 */ +#define PLU_IN5_PIO1_19 N9X_MUX('1',19,8) /* PT1_19 */ +#define ENET0_CRS_PIO1_19 N9X_MUX('1',19,9) /* PT1_19 */ +#define CAN0_RXD_PIO1_19 N9X_MUX('1',19,11) /* PT1_19 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SCT0_OUT8_PIO1_30 N9X_MUX('1',30,5) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define SCT0_OUT9_PIO1_31 N9X_MUX('1',31,5) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define FC9_P6_PIO2_0 N9X_MUX('2',0,2) /* PT2_0 */ +#define SDHC0_D5_PIO2_0 N9X_MUX('2',0,3) /* PT2_0 */ +#define SCT0_IN0_PIO2_0 N9X_MUX('2',0,4) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define FLEXSPI0_B_SS1_b_PIO2_0 N9X_MUX('2',0,8) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define SDHC0_D4_PIO2_1 N9X_MUX('2',1,3) /* PT2_1 */ +#define SCT0_IN1_PIO2_1 N9X_MUX('2',1,4) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define FLEXSPI0_B_DQS_PIO2_1 N9X_MUX('2',1,8) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define FC9_P3_PIO2_2 N9X_MUX('2',2,2) /* PT2_2 */ +#define SDHC0_D1_PIO2_2 N9X_MUX('2',2,3) /* PT2_2 */ +#define SCT0_OUT0_PIO2_2 N9X_MUX('2',2,4) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define FLEXSPI0_B_SS0_b_PIO2_2 N9X_MUX('2',2,8) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define FC9_P1_PIO2_3 N9X_MUX('2',3,2) /* PT2_3 */ +#define SDHC0_D0_PIO2_3 N9X_MUX('2',3,3) /* PT2_3 */ +#define SCT0_OUT1_PIO2_3 N9X_MUX('2',3,4) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define FLEXSPI0_B_SCLK_PIO2_3 N9X_MUX('2',3,8) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define FC9_P0_PIO2_4 N9X_MUX('2',4,2) /* PT2_4 */ +#define SDHC0_CLK_PIO2_4 N9X_MUX('2',4,3) /* PT2_4 */ +#define SCT0_OUT2_PIO2_4 N9X_MUX('2',4,4) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define FLEXSPI0_B_DATA0_PIO2_4 N9X_MUX('2',4,8) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define FC9_P2_PIO2_5 N9X_MUX('2',5,2) /* PT2_5 */ +#define SDHC0_CMD_PIO2_5 N9X_MUX('2',5,3) /* PT2_5 */ +#define SCT0_OUT3_PIO2_5 N9X_MUX('2',5,4) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define FLEXSPI0_B_DATA1_PIO2_5 N9X_MUX('2',5,8) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define FC9_P4_PIO2_6 N9X_MUX('2',6,2) /* PT2_6 */ +#define SDHC0_D3_PIO2_6 N9X_MUX('2',6,3) /* PT2_6 */ +#define SCT0_OUT4_PIO2_6 N9X_MUX('2',6,4) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define FLEXSPI0_B_DATA2_PIO2_6 N9X_MUX('2',6,8) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define FC9_P5_PIO2_7 N9X_MUX('2',7,2) /* PT2_7 */ +#define SDHC0_D2_PIO2_7 N9X_MUX('2',7,3) /* PT2_7 */ +#define SCT0_OUT5_PIO2_7 N9X_MUX('2',7,4) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define FLEXSPI0_B_DATA3_PIO2_7 N9X_MUX('2',7,8) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO2_8 N9X_MUX('2',8,0) /* PT2_8 */ +#define TRACE_DATA0_PIO2_8 N9X_MUX('2',8,1) /* PT2_8 */ +#define SDHC0_D7_PIO2_8 N9X_MUX('2',8,3) /* PT2_8 */ +#define SCT0_IN2_PIO2_8 N9X_MUX('2',8,4) /* PT2_8 */ +#define FLEXIO0_D16_PIO2_8 N9X_MUX('2',8,6) /* PT2_8 */ +#define EZH_PIO28_PIO2_8 N9X_MUX('2',8,7) /* PT2_8 */ +#define FLEXSPI0_B_DATA4_PIO2_8 N9X_MUX('2',8,8) /* PT2_8 */ +#define SAI1_TXD0_PIO2_8 N9X_MUX('2',8,10) /* PT2_8 */ +#define PIO2_9 N9X_MUX('2',9,0) /* PT2_9 */ +#define TRACE_DATA1_PIO2_9 N9X_MUX('2',9,1) /* PT2_9 */ +#define SDHC0_D6_PIO2_9 N9X_MUX('2',9,3) /* PT2_9 */ +#define SCT0_IN3_PIO2_9 N9X_MUX('2',9,4) /* PT2_9 */ +#define FLEXIO0_D17_PIO2_9 N9X_MUX('2',9,6) /* PT2_9 */ +#define EZH_PIO29_PIO2_9 N9X_MUX('2',9,7) /* PT2_9 */ +#define FLEXSPI0_B_DATA5_PIO2_9 N9X_MUX('2',9,8) /* PT2_9 */ +#define SAI1_RXD0_PIO2_9 N9X_MUX('2',9,10) /* PT2_9 */ +#define PIO2_10 N9X_MUX('2',10,0) /* PT2_10 */ +#define TRACE_DATA2_PIO2_10 N9X_MUX('2',10,1) /* PT2_10 */ +#define SCT0_IN4_PIO2_10 N9X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_PIO2_10 N9X_MUX('2',10,6) /* PT2_10 */ +#define EZH_PIO31_PIO2_10 N9X_MUX('2',10,7) /* PT2_10 */ +#define FLEXSPI0_B_DATA6_PIO2_10 N9X_MUX('2',10,8) /* PT2_10 */ +#define SAI1_RXD1_PIO2_10 N9X_MUX('2',10,10) /* PT2_10 */ +#define PIO2_11 N9X_MUX('2',11,0) /* PT2_11 */ +#define TRACE_DATA3_PIO2_11 N9X_MUX('2',11,1) /* PT2_11 */ +#define SCT0_IN5_PIO2_11 N9X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_PIO2_11 N9X_MUX('2',11,6) /* PT2_11 */ +#define EZH_PIO30_PIO2_11 N9X_MUX('2',11,7) /* PT2_11 */ +#define FLEXSPI0_B_DATA7_PIO2_11 N9X_MUX('2',11,8) /* PT2_11 */ +#define SAI1_TXD1_PIO2_11 N9X_MUX('2',11,10) /* PT2_11 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define FLEXSPI0_A_SS0_b_PIO3_0 N9X_MUX('3',0,8) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FLEXSPI0_A_SS1_b_PIO3_1 N9X_MUX('3',1,8) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_2 N9X_MUX('3',2,0) /* PT3_2 */ +#define FC7_P0_PIO3_2 N9X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_PIO3_2 N9X_MUX('3',2,4) /* PT3_2 */ +#define PWM0_X0_PIO3_2 N9X_MUX('3',2,5) /* PT3_2 */ +#define FLEXIO0_D10_PIO3_2 N9X_MUX('3',2,6) /* PT3_2 */ +#define EZH_PIO2_PIO3_2 N9X_MUX('3',2,7) /* PT3_2 */ +#define SIM1_PD_PIO3_2 N9X_MUX('3',2,9) /* PT3_2 */ +#define PIO3_3 N9X_MUX('3',3,0) /* PT3_3 */ +#define FC7_P1_PIO3_3 N9X_MUX('3',3,2) /* PT3_3 */ +#define CT4_MAT1_PIO3_3 N9X_MUX('3',3,4) /* PT3_3 */ +#define PWM0_X1_PIO3_3 N9X_MUX('3',3,5) /* PT3_3 */ +#define FLEXIO0_D11_PIO3_3 N9X_MUX('3',3,6) /* PT3_3 */ +#define EZH_PIO3_PIO3_3 N9X_MUX('3',3,7) /* PT3_3 */ +#define SIM1_RST_PIO3_3 N9X_MUX('3',3,9) /* PT3_3 */ +#define PIO3_4 N9X_MUX('3',4,0) /* PT3_4 */ +#define FC7_P2_PIO3_4 N9X_MUX('3',4,2) /* PT3_4 */ +#define CT_INP18_PIO3_4 N9X_MUX('3',4,4) /* PT3_4 */ +#define PWM0_X2_PIO3_4 N9X_MUX('3',4,5) /* PT3_4 */ +#define FLEXIO0_D12_PIO3_4 N9X_MUX('3',4,6) /* PT3_4 */ +#define EZH_PIO4_PIO3_4 N9X_MUX('3',4,7) /* PT3_4 */ +#define SIM1_CLK_PIO3_4 N9X_MUX('3',4,9) /* PT3_4 */ +#define PIO3_5 N9X_MUX('3',5,0) /* PT3_5 */ +#define FC7_P3_PIO3_5 N9X_MUX('3',5,2) /* PT3_5 */ +#define CT_INP19_PIO3_5 N9X_MUX('3',5,4) /* PT3_5 */ +#define PWM0_X3_PIO3_5 N9X_MUX('3',5,5) /* PT3_5 */ +#define FLEXIO0_D13_PIO3_5 N9X_MUX('3',5,6) /* PT3_5 */ +#define EZH_PIO5_PIO3_5 N9X_MUX('3',5,7) /* PT3_5 */ +#define SIM1_IO_PIO3_5 N9X_MUX('3',5,9) /* PT3_5 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define FLEXSPI0_A_DQS_PIO3_6 N9X_MUX('3',6,8) /* PT3_6 */ +#define SIM1_VCCEN_PIO3_6 N9X_MUX('3',6,9) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define FLEXSPI0_A_SCLK_PIO3_7 N9X_MUX('3',7,8) /* PT3_7 */ +#define SIM0_VCCEN_PIO3_7 N9X_MUX('3',7,9) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define FLEXSPI0_A_DATA0_PIO3_8 N9X_MUX('3',8,8) /* PT3_8 */ +#define SIM0_PD_PIO3_8 N9X_MUX('3',8,9) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define FLEXSPI0_A_DATA1_PIO3_9 N9X_MUX('3',9,8) /* PT3_9 */ +#define SIM0_RST_PIO3_9 N9X_MUX('3',9,9) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define FLEXSPI0_A_DATA2_PIO3_10 N9X_MUX('3',10,8) /* PT3_10 */ +#define SIM0_CLK_PIO3_10 N9X_MUX('3',10,9) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define FLEXSPI0_A_DATA3_PIO3_11 N9X_MUX('3',11,8) /* PT3_11 */ +#define SIM0_IO_PIO3_11 N9X_MUX('3',11,9) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define FLEXSPI0_A_DATA4_PIO3_12 N9X_MUX('3',12,8) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define FLEXSPI0_A_DATA5_PIO3_13 N9X_MUX('3',13,8) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define FC8_P0_PIO3_14 N9X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define FLEXSPI0_A_DATA6_PIO3_14 N9X_MUX('3',14,8) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define FC8_P1_PIO3_15 N9X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define FLEXSPI0_A_DATA7_PIO3_15 N9X_MUX('3',15,8) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define FC8_P2_PIO3_16 N9X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SIM0_CLK_PIO3_16 N9X_MUX('3',16,9) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define FC8_P3_PIO3_17 N9X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SIM0_IO_PIO3_17 N9X_MUX('3',17,9) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC8_P4_PIO3_20 N9X_MUX('3',20,2) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SIM0_PD_PIO3_20 N9X_MUX('3',20,9) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC8_P5_PIO3_21 N9X_MUX('3',21,2) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SIM0_RST_PIO3_21 N9X_MUX('3',21,9) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO3_22 N9X_MUX('3',22,0) /* PT3_22 */ +#define FC8_P6_PIO3_22 N9X_MUX('3',22,2) /* PT3_22 */ +#define FC6_P2_PIO3_22 N9X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_PIO3_22 N9X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_PIO3_22 N9X_MUX('3',22,6) /* PT3_22 */ +#define EZH_PIO22_PIO3_22 N9X_MUX('3',22,7) /* PT3_22 */ +#define SIM0_VCCEN_PIO3_22 N9X_MUX('3',22,9) /* PT3_22 */ +#define SAI1_RXD1_PIO3_22 N9X_MUX('3',22,10) /* PT3_22 */ +#define PIO3_23 N9X_MUX('3',23,0) /* PT3_23 */ +#define FC6_P3_PIO3_23 N9X_MUX('3',23,3) /* PT3_23 */ +#define CT_INP11_PIO3_23 N9X_MUX('3',23,4) /* PT3_23 */ +#define FLEXIO0_D31_PIO3_23 N9X_MUX('3',23,6) /* PT3_23 */ +#define EZH_PIO23_PIO3_23 N9X_MUX('3',23,7) /* PT3_23 */ +#define SAI1_TXD1_PIO3_23 N9X_MUX('3',23,10) /* PT3_23 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PLU_IN0_PIO4_0 N9X_MUX('4',0,8) /* PT4_0 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define PLU_IN1_PIO4_1 N9X_MUX('4',1,8) /* PT4_1 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define DAC0_OUT_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define PLU_IN2_PIO4_2 N9X_MUX('4',2,8) /* PT4_2 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PLU_IN3_PIO4_3 N9X_MUX('4',3,8) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define PLU_IN4_PIO4_4 N9X_MUX('4',4,8) /* PT4_4 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PLU_IN5_PIO4_5 N9X_MUX('4',5,8) /* PT4_5 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PLU_CLK_PIO4_6 N9X_MUX('4',6,8) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define USB0_VBUS_DET_PIO4_12 N9X_MUX('4',12,1) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define PLU_OUT0_PIO4_12 N9X_MUX('4',12,8) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define PLU_OUT1_PIO4_13 N9X_MUX('4',13,8) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_14 N9X_MUX('4',14,0) /* PT4_14 */ +#define CT4_MAT2_PIO4_14 N9X_MUX('4',14,4) /* PT4_14 */ +#define FLEXIO0_D22_PIO4_14 N9X_MUX('4',14,6) /* PT4_14 */ +#define PLU_OUT2_PIO4_14 N9X_MUX('4',14,8) /* PT4_14 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define PLU_OUT3_PIO4_15 N9X_MUX('4',15,8) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define PLU_OUT4_PIO4_16 N9X_MUX('4',16,8) /* PT4_16 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PLU_OUT5_PIO4_17 N9X_MUX('4',17,8) /* PT4_17 */ +#define PIO4_18 N9X_MUX('4',18,0) /* PT4_18 */ +#define CT3_MAT2_PIO4_18 N9X_MUX('4',18,4) /* PT4_18 */ +#define FLEXIO0_D26_PIO4_18 N9X_MUX('4',18,6) /* PT4_18 */ +#define PLU_OUT6_PIO4_18 N9X_MUX('4',18,8) /* PT4_18 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define PLU_OUT7_PIO4_19 N9X_MUX('4',19,8) /* PT4_19 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define PIO4_22 N9X_MUX('4',22,0) /* PT4_22 */ +#define CT2_MAT2_PIO4_22 N9X_MUX('4',22,4) /* PT4_22 */ +#define FLEXIO0_D30_PIO4_22 N9X_MUX('4',22,6) /* PT4_22 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#define PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define ADC1_B12_PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define TRIG_OUT7_PIO5_4 N9X_MUX('5',4,1) /* PT5_4 */ +#define SPC_LPREQ_PIO5_4 N9X_MUX('5',4,2) /* PT5_4 */ +#define TAMPER2_PIO5_4 N9X_MUX('5',4,3) /* PT5_4 */ +#define ADC1_B13_PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define TRIG_IN10_PIO5_5 N9X_MUX('5',5,1) /* PT5_5 */ +#define LPTMR0_ALT2_PIO5_5 N9X_MUX('5',5,2) /* PT5_5 */ +#define TAMPER3_PIO5_5 N9X_MUX('5',5,3) /* PT5_5 */ +#define ADC1_B14_PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define TRIG_OUT6_PIO5_6 N9X_MUX('5',6,1) /* PT5_6 */ +#define LPTMR1_ALT2_PIO5_6 N9X_MUX('5',6,2) /* PT5_6 */ +#define TAMPER4_PIO5_6 N9X_MUX('5',6,3) /* PT5_6 */ +#define PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define ADC1_B15_PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define TRIG_IN11_PIO5_7 N9X_MUX('5',7,1) /* PT5_7 */ +#define TAMPER5_PIO5_7 N9X_MUX('5',7,3) /* PT5_7 */ +#define ADC1_B16_PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define TRIG_OUT7_PIO5_8 N9X_MUX('5',8,1) /* PT5_8 */ +#define TAMPER6_PIO5_8 N9X_MUX('5',8,3) /* PT5_8 */ +#define PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define ADC1_B17_PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define TAMPER7_PIO5_9 N9X_MUX('5',9,3) /* PT5_9 */ +#endif diff --git a/dts/nxp/mcx/MCXN547VDF-pinctrl.h b/dts/nxp/mcx/MCXN547VDF-pinctrl.h new file mode 100644 index 000000000..1fe03574b --- /dev/null +++ b/dts/nxp/mcx/MCXN547VDF-pinctrl.h @@ -0,0 +1,1003 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN547VDF/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN547VDF_ +#define _ZEPHYR_DTS_BINDING_MCXN547VDF_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define TSI0_CH8_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define TSI0_CH9_PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define TSI0_CH10_PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define WUU0_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define FC0_P3_PIO0_7 N9X_MUX('0',7,2) /* PT0_7 */ +#define CT_INP3_PIO0_7 N9X_MUX('0',7,4) /* PT0_7 */ +#define PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define ADC0_B8_PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define FC0_P4_PIO0_8 N9X_MUX('0',8,2) /* PT0_8 */ +#define CT_INP0_PIO0_8 N9X_MUX('0',8,4) /* PT0_8 */ +#define FLEXIO0_D0_PIO0_8 N9X_MUX('0',8,6) /* PT0_8 */ +#define PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define ADC0_B9_PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define FC0_P5_PIO0_9 N9X_MUX('0',9,2) /* PT0_9 */ +#define CT_INP1_PIO0_9 N9X_MUX('0',9,4) /* PT0_9 */ +#define FLEXIO0_D1_PIO0_9 N9X_MUX('0',9,6) /* PT0_9 */ +#define PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define ADC0_B10_PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define FC0_P6_PIO0_10 N9X_MUX('0',10,2) /* PT0_10 */ +#define CT0_MAT0_PIO0_10 N9X_MUX('0',10,4) /* PT0_10 */ +#define FLEXIO0_D2_PIO0_10 N9X_MUX('0',10,6) /* PT0_10 */ +#define PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define ADC0_B11_PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define CT0_MAT1_PIO0_11 N9X_MUX('0',11,4) /* PT0_11 */ +#define FLEXIO0_D3_PIO0_11 N9X_MUX('0',11,6) /* PT0_11 */ +#define PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define ADC0_B12_PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define FC1_P4_PIO0_12 N9X_MUX('0',12,2) /* PT0_12 */ +#define FC0_P0_PIO0_12 N9X_MUX('0',12,3) /* PT0_12 */ +#define CT0_MAT2_PIO0_12 N9X_MUX('0',12,4) /* PT0_12 */ +#define FLEXIO0_D4_PIO0_12 N9X_MUX('0',12,6) /* PT0_12 */ +#define PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define ADC0_B13_PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define FC1_P5_PIO0_13 N9X_MUX('0',13,2) /* PT0_13 */ +#define FC0_P1_PIO0_13 N9X_MUX('0',13,3) /* PT0_13 */ +#define CT0_MAT3_PIO0_13 N9X_MUX('0',13,4) /* PT0_13 */ +#define FLEXIO0_D5_PIO0_13 N9X_MUX('0',13,6) /* PT0_13 */ +#define PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define ADC0_B14_PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define FC1_P6_PIO0_14 N9X_MUX('0',14,2) /* PT0_14 */ +#define FC0_P2_PIO0_14 N9X_MUX('0',14,3) /* PT0_14 */ +#define CT_INP2_PIO0_14 N9X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_PIO0_14 N9X_MUX('0',14,5) /* PT0_14 */ +#define FLEXIO0_D6_PIO0_14 N9X_MUX('0',14,6) /* PT0_14 */ +#define PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define ADC0_B15_PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define FC0_P3_PIO0_15 N9X_MUX('0',15,3) /* PT0_15 */ +#define CT_INP3_PIO0_15 N9X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_PIO0_15 N9X_MUX('0',15,5) /* PT0_15 */ +#define FLEXIO0_D7_PIO0_15 N9X_MUX('0',15,6) /* PT0_15 */ +#define TSI0_CH11_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define TSI0_CH12_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define TSI0_CH13_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define TSI0_CH14_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define TSI0_CH15_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define TSI0_CH16_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define ADC0_B16_PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define FC1_P0_PIO0_24 N9X_MUX('0',24,2) /* PT0_24 */ +#define CT0_MAT0_PIO0_24 N9X_MUX('0',24,4) /* PT0_24 */ +#define PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define ADC0_B17_PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define FC1_P1_PIO0_25 N9X_MUX('0',25,2) /* PT0_25 */ +#define CT0_MAT1_PIO0_25 N9X_MUX('0',25,4) /* PT0_25 */ +#define PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define ADC0_B18_PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define FC1_P2_PIO0_26 N9X_MUX('0',26,2) /* PT0_26 */ +#define CT0_MAT2_PIO0_26 N9X_MUX('0',26,4) /* PT0_26 */ +#define PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define ADC0_B19_PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define FC1_P3_PIO0_27 N9X_MUX('0',27,2) /* PT0_27 */ +#define CT0_MAT3_PIO0_27 N9X_MUX('0',27,4) /* PT0_27 */ +#define PIO0_28 N9X_MUX('0',28,0) /* PT0_28 */ +#define ADC0_B20_PIO0_28 N9X_MUX('0',28,0) /* PT0_28 */ +#define FC1_P4_PIO0_28 N9X_MUX('0',28,2) /* PT0_28 */ +#define FC0_P4_PIO0_28 N9X_MUX('0',28,3) /* PT0_28 */ +#define CT_INP0_PIO0_28 N9X_MUX('0',28,4) /* PT0_28 */ +#define PIO0_29 N9X_MUX('0',29,0) /* PT0_29 */ +#define ADC0_B21_PIO0_29 N9X_MUX('0',29,0) /* PT0_29 */ +#define FC1_P5_PIO0_29 N9X_MUX('0',29,2) /* PT0_29 */ +#define FC0_P5_PIO0_29 N9X_MUX('0',29,3) /* PT0_29 */ +#define CT_INP1_PIO0_29 N9X_MUX('0',29,4) /* PT0_29 */ +#define PIO0_30 N9X_MUX('0',30,0) /* PT0_30 */ +#define ADC0_B22_PIO0_30 N9X_MUX('0',30,0) /* PT0_30 */ +#define FC1_P6_PIO0_30 N9X_MUX('0',30,2) /* PT0_30 */ +#define FC0_P6_PIO0_30 N9X_MUX('0',30,3) /* PT0_30 */ +#define CT_INP2_PIO0_30 N9X_MUX('0',30,4) /* PT0_30 */ +#define PIO0_31 N9X_MUX('0',31,0) /* PT0_31 */ +#define ADC0_B23_PIO0_31 N9X_MUX('0',31,0) /* PT0_31 */ +#define CT_INP3_PIO0_31 N9X_MUX('0',31,4) /* PT0_31 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TSI0_CH0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define SCT0_OUT6_PIO1_0 N9X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TSI0_CH1_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define SCT0_OUT7_PIO1_1 N9X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define TSI0_CH2_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define SCT0_IN6_PIO1_2 N9X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define ENET0_MDC_PIO1_2 N9X_MUX('1',2,9) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TSI0_CH3_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define SCT0_IN7_PIO1_3 N9X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define ENET0_MDIO_PIO1_3 N9X_MUX('1',3,9) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define TSI0_CH4_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define SCT0_OUT0_PIO1_4 N9X_MUX('1',4,5) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define ENET0_TX_CLK_PIO1_4 N9X_MUX('1',4,9) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define TSI0_CH5_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define SCT0_OUT1_PIO1_5 N9X_MUX('1',5,5) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define ENET0_TXEN_PIO1_5 N9X_MUX('1',5,9) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TSI0_CH6_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define SCT0_IN0_PIO1_6 N9X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define ENET0_TXD0_PIO1_6 N9X_MUX('1',6,9) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TSI0_CH7_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define SCT0_IN1_PIO1_7 N9X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define PLU_CLK_PIO1_7 N9X_MUX('1',7,8) /* PT1_7 */ +#define ENET0_TXD1_PIO1_7 N9X_MUX('1',7,9) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TSI0_CH17_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define SCT0_OUT2_PIO1_8 N9X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define PLU_OUT0_PIO1_8 N9X_MUX('1',8,8) /* PT1_8 */ +#define ENET0_TXD2_PIO1_8 N9X_MUX('1',8,9) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TSI0_CH18_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define SCT0_OUT3_PIO1_9 N9X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define PLU_OUT1_PIO1_9 N9X_MUX('1',9,8) /* PT1_9 */ +#define ENET0_TXD3_PIO1_9 N9X_MUX('1',9,9) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TSI0_CH19_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define SCT0_IN2_PIO1_10 N9X_MUX('1',10,5) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define PLU_IN0_PIO1_10 N9X_MUX('1',10,8) /* PT1_10 */ +#define ENET0_TXER_PIO1_10 N9X_MUX('1',10,9) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TSI0_CH20_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define SCT0_IN3_PIO1_11 N9X_MUX('1',11,5) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define PLU_IN1_PIO1_11 N9X_MUX('1',11,8) /* PT1_11 */ +#define ENET0_RX_CLK_PIO1_11 N9X_MUX('1',11,9) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TSI0_CH21_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define SCT0_OUT4_PIO1_12 N9X_MUX('1',12,5) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define PLU_OUT2_PIO1_12 N9X_MUX('1',12,8) /* PT1_12 */ +#define ENET0_RXER_PIO1_12 N9X_MUX('1',12,9) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TSI0_CH22_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define SCT0_OUT5_PIO1_13 N9X_MUX('1',13,5) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define PLU_OUT3_PIO1_13 N9X_MUX('1',13,8) /* PT1_13 */ +#define ENET0_RXDV_PIO1_13 N9X_MUX('1',13,9) /* PT1_13 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define TSI0_CH23_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define SCT0_IN4_PIO1_14 N9X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PLU_IN2_PIO1_14 N9X_MUX('1',14,8) /* PT1_14 */ +#define ENET0_RXD0_PIO1_14 N9X_MUX('1',14,9) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define TSI0_CH24_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define SCT0_IN5_PIO1_15 N9X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define PLU_IN3_PIO1_15 N9X_MUX('1',15,8) /* PT1_15 */ +#define ENET0_RXD1_PIO1_15 N9X_MUX('1',15,9) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define ADC1_A16_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define WUU0_IN14_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define FC5_P0_PIO1_16 N9X_MUX('1',16,2) /* PT1_16 */ +#define FC3_P4_PIO1_16 N9X_MUX('1',16,3) /* PT1_16 */ +#define CT_INP12_PIO1_16 N9X_MUX('1',16,4) /* PT1_16 */ +#define SCT0_OUT6_PIO1_16 N9X_MUX('1',16,5) /* PT1_16 */ +#define FLEXIO0_D24_PIO1_16 N9X_MUX('1',16,6) /* PT1_16 */ +#define EZH_PIO12_PIO1_16 N9X_MUX('1',16,7) /* PT1_16 */ +#define PLU_OUT4_PIO1_16 N9X_MUX('1',16,8) /* PT1_16 */ +#define ENET0_RXD2_PIO1_16 N9X_MUX('1',16,9) /* PT1_16 */ +#define I3C1_SDA_PIO1_16 N9X_MUX('1',16,10) /* PT1_16 */ +#define PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define ADC1_A17_PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define FC5_P1_PIO1_17 N9X_MUX('1',17,2) /* PT1_17 */ +#define FC3_P5_PIO1_17 N9X_MUX('1',17,3) /* PT1_17 */ +#define CT_INP13_PIO1_17 N9X_MUX('1',17,4) /* PT1_17 */ +#define SCT0_OUT7_PIO1_17 N9X_MUX('1',17,5) /* PT1_17 */ +#define FLEXIO0_D25_PIO1_17 N9X_MUX('1',17,6) /* PT1_17 */ +#define EZH_PIO13_PIO1_17 N9X_MUX('1',17,7) /* PT1_17 */ +#define PLU_OUT5_PIO1_17 N9X_MUX('1',17,8) /* PT1_17 */ +#define ENET0_RXD3_PIO1_17 N9X_MUX('1',17,9) /* PT1_17 */ +#define I3C1_SCL_PIO1_17 N9X_MUX('1',17,10) /* PT1_17 */ +#define PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define ADC1_A18_PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define FREQME_CLK_IN0_PIO1_18 N9X_MUX('1',18,1) /* PT1_18 */ +#define FC5_P2_PIO1_18 N9X_MUX('1',18,2) /* PT1_18 */ +#define FC3_P6_PIO1_18 N9X_MUX('1',18,3) /* PT1_18 */ +#define CT3_MAT0_PIO1_18 N9X_MUX('1',18,4) /* PT1_18 */ +#define SCT0_IN6_PIO1_18 N9X_MUX('1',18,5) /* PT1_18 */ +#define FLEXIO0_D26_PIO1_18 N9X_MUX('1',18,6) /* PT1_18 */ +#define EZH_PIO14_PIO1_18 N9X_MUX('1',18,7) /* PT1_18 */ +#define PLU_IN4_PIO1_18 N9X_MUX('1',18,8) /* PT1_18 */ +#define ENET0_COL_PIO1_18 N9X_MUX('1',18,9) /* PT1_18 */ +#define CAN0_TXD_PIO1_18 N9X_MUX('1',18,11) /* PT1_18 */ +#define PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define ADC1_A19_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define WUU0_IN15_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define FREQME_CLK_IN1_PIO1_19 N9X_MUX('1',19,1) /* PT1_19 */ +#define FC5_P3_PIO1_19 N9X_MUX('1',19,2) /* PT1_19 */ +#define CT3_MAT1_PIO1_19 N9X_MUX('1',19,4) /* PT1_19 */ +#define SCT0_IN7_PIO1_19 N9X_MUX('1',19,5) /* PT1_19 */ +#define FLEXIO0_D27_PIO1_19 N9X_MUX('1',19,6) /* PT1_19 */ +#define EZH_PIO15_PIO1_19 N9X_MUX('1',19,7) /* PT1_19 */ +#define PLU_IN5_PIO1_19 N9X_MUX('1',19,8) /* PT1_19 */ +#define ENET0_CRS_PIO1_19 N9X_MUX('1',19,9) /* PT1_19 */ +#define CAN0_RXD_PIO1_19 N9X_MUX('1',19,11) /* PT1_19 */ +#define CMP1_IN3_PIO1_20 N9X_MUX('1',20,0) /* PT1_20 */ +#define PIO1_20 N9X_MUX('1',20,0) /* PT1_20 */ +#define ADC1_A20_PIO1_20 N9X_MUX('1',20,0) /* PT1_20 */ +#define TRIG_IN2_PIO1_20 N9X_MUX('1',20,1) /* PT1_20 */ +#define FC5_P4_PIO1_20 N9X_MUX('1',20,2) /* PT1_20 */ +#define FC4_P0_PIO1_20 N9X_MUX('1',20,3) /* PT1_20 */ +#define CT3_MAT2_PIO1_20 N9X_MUX('1',20,4) /* PT1_20 */ +#define SCT0_OUT8_PIO1_20 N9X_MUX('1',20,5) /* PT1_20 */ +#define FLEXIO0_D28_PIO1_20 N9X_MUX('1',20,6) /* PT1_20 */ +#define EZH_PIO16_PIO1_20 N9X_MUX('1',20,7) /* PT1_20 */ +#define PLU_OUT6_PIO1_20 N9X_MUX('1',20,8) /* PT1_20 */ +#define ENET0_MDC_PIO1_20 N9X_MUX('1',20,9) /* PT1_20 */ +#define PIO1_21 N9X_MUX('1',21,0) /* PT1_21 */ +#define ADC1_A21_PIO1_21 N9X_MUX('1',21,0) /* PT1_21 */ +#define TRIG_OUT2_PIO1_21 N9X_MUX('1',21,1) /* PT1_21 */ +#define FC5_P5_PIO1_21 N9X_MUX('1',21,2) /* PT1_21 */ +#define FC4_P1_PIO1_21 N9X_MUX('1',21,3) /* PT1_21 */ +#define CT3_MAT3_PIO1_21 N9X_MUX('1',21,4) /* PT1_21 */ +#define SCT0_OUT9_PIO1_21 N9X_MUX('1',21,5) /* PT1_21 */ +#define FLEXIO0_D29_PIO1_21 N9X_MUX('1',21,6) /* PT1_21 */ +#define EZH_PIO17_PIO1_21 N9X_MUX('1',21,7) /* PT1_21 */ +#define PLU_OUT7_PIO1_21 N9X_MUX('1',21,8) /* PT1_21 */ +#define ENET0_MDIO_PIO1_21 N9X_MUX('1',21,9) /* PT1_21 */ +#define SAI1_MCLK_PIO1_21 N9X_MUX('1',21,10) /* PT1_21 */ +#define PIO1_22 N9X_MUX('1',22,0) /* PT1_22 */ +#define ADC1_A22_PIO1_22 N9X_MUX('1',22,0) /* PT1_22 */ +#define TRIG_IN3_PIO1_22 N9X_MUX('1',22,1) /* PT1_22 */ +#define FC5_P6_PIO1_22 N9X_MUX('1',22,2) /* PT1_22 */ +#define FC4_P2_PIO1_22 N9X_MUX('1',22,3) /* PT1_22 */ +#define CT_INP14_PIO1_22 N9X_MUX('1',22,4) /* PT1_22 */ +#define SCT0_OUT4_PIO1_22 N9X_MUX('1',22,5) /* PT1_22 */ +#define FLEXIO0_D30_PIO1_22 N9X_MUX('1',22,6) /* PT1_22 */ +#define EZH_PIO18_PIO1_22 N9X_MUX('1',22,7) /* PT1_22 */ +#define PIO1_23 N9X_MUX('1',23,0) /* PT1_23 */ +#define ADC1_A23_PIO1_23 N9X_MUX('1',23,0) /* PT1_23 */ +#define FC4_P3_PIO1_23 N9X_MUX('1',23,3) /* PT1_23 */ +#define CT_INP15_PIO1_23 N9X_MUX('1',23,4) /* PT1_23 */ +#define SCT0_OUT5_PIO1_23 N9X_MUX('1',23,5) /* PT1_23 */ +#define FLEXIO0_D31_PIO1_23 N9X_MUX('1',23,6) /* PT1_23 */ +#define EZH_PIO19_PIO1_23 N9X_MUX('1',23,7) /* PT1_23 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SCT0_OUT8_PIO1_30 N9X_MUX('1',30,5) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define SCT0_OUT9_PIO1_31 N9X_MUX('1',31,5) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define FC9_P6_PIO2_0 N9X_MUX('2',0,2) /* PT2_0 */ +#define SDHC0_D5_PIO2_0 N9X_MUX('2',0,3) /* PT2_0 */ +#define SCT0_IN0_PIO2_0 N9X_MUX('2',0,4) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define FLEXSPI0_B_SS1_b_PIO2_0 N9X_MUX('2',0,8) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define SDHC0_D4_PIO2_1 N9X_MUX('2',1,3) /* PT2_1 */ +#define SCT0_IN1_PIO2_1 N9X_MUX('2',1,4) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define FLEXSPI0_B_DQS_PIO2_1 N9X_MUX('2',1,8) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define FC9_P3_PIO2_2 N9X_MUX('2',2,2) /* PT2_2 */ +#define SDHC0_D1_PIO2_2 N9X_MUX('2',2,3) /* PT2_2 */ +#define SCT0_OUT0_PIO2_2 N9X_MUX('2',2,4) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define FLEXSPI0_B_SS0_b_PIO2_2 N9X_MUX('2',2,8) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define FC9_P1_PIO2_3 N9X_MUX('2',3,2) /* PT2_3 */ +#define SDHC0_D0_PIO2_3 N9X_MUX('2',3,3) /* PT2_3 */ +#define SCT0_OUT1_PIO2_3 N9X_MUX('2',3,4) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define FLEXSPI0_B_SCLK_PIO2_3 N9X_MUX('2',3,8) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define FC9_P0_PIO2_4 N9X_MUX('2',4,2) /* PT2_4 */ +#define SDHC0_CLK_PIO2_4 N9X_MUX('2',4,3) /* PT2_4 */ +#define SCT0_OUT2_PIO2_4 N9X_MUX('2',4,4) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define FLEXSPI0_B_DATA0_PIO2_4 N9X_MUX('2',4,8) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define FC9_P2_PIO2_5 N9X_MUX('2',5,2) /* PT2_5 */ +#define SDHC0_CMD_PIO2_5 N9X_MUX('2',5,3) /* PT2_5 */ +#define SCT0_OUT3_PIO2_5 N9X_MUX('2',5,4) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define FLEXSPI0_B_DATA1_PIO2_5 N9X_MUX('2',5,8) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define FC9_P4_PIO2_6 N9X_MUX('2',6,2) /* PT2_6 */ +#define SDHC0_D3_PIO2_6 N9X_MUX('2',6,3) /* PT2_6 */ +#define SCT0_OUT4_PIO2_6 N9X_MUX('2',6,4) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define FLEXSPI0_B_DATA2_PIO2_6 N9X_MUX('2',6,8) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define FC9_P5_PIO2_7 N9X_MUX('2',7,2) /* PT2_7 */ +#define SDHC0_D2_PIO2_7 N9X_MUX('2',7,3) /* PT2_7 */ +#define SCT0_OUT5_PIO2_7 N9X_MUX('2',7,4) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define FLEXSPI0_B_DATA3_PIO2_7 N9X_MUX('2',7,8) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO2_8 N9X_MUX('2',8,0) /* PT2_8 */ +#define TRACE_DATA0_PIO2_8 N9X_MUX('2',8,1) /* PT2_8 */ +#define SDHC0_D7_PIO2_8 N9X_MUX('2',8,3) /* PT2_8 */ +#define SCT0_IN2_PIO2_8 N9X_MUX('2',8,4) /* PT2_8 */ +#define FLEXIO0_D16_PIO2_8 N9X_MUX('2',8,6) /* PT2_8 */ +#define EZH_PIO28_PIO2_8 N9X_MUX('2',8,7) /* PT2_8 */ +#define FLEXSPI0_B_DATA4_PIO2_8 N9X_MUX('2',8,8) /* PT2_8 */ +#define SAI1_TXD0_PIO2_8 N9X_MUX('2',8,10) /* PT2_8 */ +#define PIO2_9 N9X_MUX('2',9,0) /* PT2_9 */ +#define TRACE_DATA1_PIO2_9 N9X_MUX('2',9,1) /* PT2_9 */ +#define SDHC0_D6_PIO2_9 N9X_MUX('2',9,3) /* PT2_9 */ +#define SCT0_IN3_PIO2_9 N9X_MUX('2',9,4) /* PT2_9 */ +#define FLEXIO0_D17_PIO2_9 N9X_MUX('2',9,6) /* PT2_9 */ +#define EZH_PIO29_PIO2_9 N9X_MUX('2',9,7) /* PT2_9 */ +#define FLEXSPI0_B_DATA5_PIO2_9 N9X_MUX('2',9,8) /* PT2_9 */ +#define SAI1_RXD0_PIO2_9 N9X_MUX('2',9,10) /* PT2_9 */ +#define PIO2_10 N9X_MUX('2',10,0) /* PT2_10 */ +#define TRACE_DATA2_PIO2_10 N9X_MUX('2',10,1) /* PT2_10 */ +#define SCT0_IN4_PIO2_10 N9X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_PIO2_10 N9X_MUX('2',10,6) /* PT2_10 */ +#define EZH_PIO31_PIO2_10 N9X_MUX('2',10,7) /* PT2_10 */ +#define FLEXSPI0_B_DATA6_PIO2_10 N9X_MUX('2',10,8) /* PT2_10 */ +#define SAI1_RXD1_PIO2_10 N9X_MUX('2',10,10) /* PT2_10 */ +#define PIO2_11 N9X_MUX('2',11,0) /* PT2_11 */ +#define TRACE_DATA3_PIO2_11 N9X_MUX('2',11,1) /* PT2_11 */ +#define SCT0_IN5_PIO2_11 N9X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_PIO2_11 N9X_MUX('2',11,6) /* PT2_11 */ +#define EZH_PIO30_PIO2_11 N9X_MUX('2',11,7) /* PT2_11 */ +#define FLEXSPI0_B_DATA7_PIO2_11 N9X_MUX('2',11,8) /* PT2_11 */ +#define SAI1_TXD1_PIO2_11 N9X_MUX('2',11,10) /* PT2_11 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define FLEXSPI0_A_SS0_b_PIO3_0 N9X_MUX('3',0,8) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FLEXSPI0_A_SS1_b_PIO3_1 N9X_MUX('3',1,8) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_2 N9X_MUX('3',2,0) /* PT3_2 */ +#define FC7_P0_PIO3_2 N9X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_PIO3_2 N9X_MUX('3',2,4) /* PT3_2 */ +#define PWM0_X0_PIO3_2 N9X_MUX('3',2,5) /* PT3_2 */ +#define FLEXIO0_D10_PIO3_2 N9X_MUX('3',2,6) /* PT3_2 */ +#define EZH_PIO2_PIO3_2 N9X_MUX('3',2,7) /* PT3_2 */ +#define SIM1_PD_PIO3_2 N9X_MUX('3',2,9) /* PT3_2 */ +#define PIO3_3 N9X_MUX('3',3,0) /* PT3_3 */ +#define FC7_P1_PIO3_3 N9X_MUX('3',3,2) /* PT3_3 */ +#define CT4_MAT1_PIO3_3 N9X_MUX('3',3,4) /* PT3_3 */ +#define PWM0_X1_PIO3_3 N9X_MUX('3',3,5) /* PT3_3 */ +#define FLEXIO0_D11_PIO3_3 N9X_MUX('3',3,6) /* PT3_3 */ +#define EZH_PIO3_PIO3_3 N9X_MUX('3',3,7) /* PT3_3 */ +#define SIM1_RST_PIO3_3 N9X_MUX('3',3,9) /* PT3_3 */ +#define PIO3_4 N9X_MUX('3',4,0) /* PT3_4 */ +#define FC7_P2_PIO3_4 N9X_MUX('3',4,2) /* PT3_4 */ +#define CT_INP18_PIO3_4 N9X_MUX('3',4,4) /* PT3_4 */ +#define PWM0_X2_PIO3_4 N9X_MUX('3',4,5) /* PT3_4 */ +#define FLEXIO0_D12_PIO3_4 N9X_MUX('3',4,6) /* PT3_4 */ +#define EZH_PIO4_PIO3_4 N9X_MUX('3',4,7) /* PT3_4 */ +#define SIM1_CLK_PIO3_4 N9X_MUX('3',4,9) /* PT3_4 */ +#define PIO3_5 N9X_MUX('3',5,0) /* PT3_5 */ +#define FC7_P3_PIO3_5 N9X_MUX('3',5,2) /* PT3_5 */ +#define CT_INP19_PIO3_5 N9X_MUX('3',5,4) /* PT3_5 */ +#define PWM0_X3_PIO3_5 N9X_MUX('3',5,5) /* PT3_5 */ +#define FLEXIO0_D13_PIO3_5 N9X_MUX('3',5,6) /* PT3_5 */ +#define EZH_PIO5_PIO3_5 N9X_MUX('3',5,7) /* PT3_5 */ +#define SIM1_IO_PIO3_5 N9X_MUX('3',5,9) /* PT3_5 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define FLEXSPI0_A_DQS_PIO3_6 N9X_MUX('3',6,8) /* PT3_6 */ +#define SIM1_VCCEN_PIO3_6 N9X_MUX('3',6,9) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define FLEXSPI0_A_SCLK_PIO3_7 N9X_MUX('3',7,8) /* PT3_7 */ +#define SIM0_VCCEN_PIO3_7 N9X_MUX('3',7,9) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define FLEXSPI0_A_DATA0_PIO3_8 N9X_MUX('3',8,8) /* PT3_8 */ +#define SIM0_PD_PIO3_8 N9X_MUX('3',8,9) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define FLEXSPI0_A_DATA1_PIO3_9 N9X_MUX('3',9,8) /* PT3_9 */ +#define SIM0_RST_PIO3_9 N9X_MUX('3',9,9) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define FLEXSPI0_A_DATA2_PIO3_10 N9X_MUX('3',10,8) /* PT3_10 */ +#define SIM0_CLK_PIO3_10 N9X_MUX('3',10,9) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define FLEXSPI0_A_DATA3_PIO3_11 N9X_MUX('3',11,8) /* PT3_11 */ +#define SIM0_IO_PIO3_11 N9X_MUX('3',11,9) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define FLEXSPI0_A_DATA4_PIO3_12 N9X_MUX('3',12,8) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define FLEXSPI0_A_DATA5_PIO3_13 N9X_MUX('3',13,8) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define FC8_P0_PIO3_14 N9X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define FLEXSPI0_A_DATA6_PIO3_14 N9X_MUX('3',14,8) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define FC8_P1_PIO3_15 N9X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define FLEXSPI0_A_DATA7_PIO3_15 N9X_MUX('3',15,8) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define FC8_P2_PIO3_16 N9X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SIM0_CLK_PIO3_16 N9X_MUX('3',16,9) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define FC8_P3_PIO3_17 N9X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SIM0_IO_PIO3_17 N9X_MUX('3',17,9) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define PIO3_18 N9X_MUX('3',18,0) /* PT3_18 */ +#define FC6_P6_PIO3_18 N9X_MUX('3',18,3) /* PT3_18 */ +#define CT2_MAT0_PIO3_18 N9X_MUX('3',18,4) /* PT3_18 */ +#define FLEXIO0_D26_PIO3_18 N9X_MUX('3',18,6) /* PT3_18 */ +#define EZH_PIO18_PIO3_18 N9X_MUX('3',18,7) /* PT3_18 */ +#define SAI1_RX_BCLK_PIO3_18 N9X_MUX('3',18,10) /* PT3_18 */ +#define PIO3_19 N9X_MUX('3',19,0) /* PT3_19 */ +#define FC7_P6_PIO3_19 N9X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_PIO3_19 N9X_MUX('3',19,4) /* PT3_19 */ +#define FLEXIO0_D27_PIO3_19 N9X_MUX('3',19,6) /* PT3_19 */ +#define EZH_PIO19_PIO3_19 N9X_MUX('3',19,7) /* PT3_19 */ +#define SAI1_RX_FS_PIO3_19 N9X_MUX('3',19,10) /* PT3_19 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC8_P4_PIO3_20 N9X_MUX('3',20,2) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SIM0_PD_PIO3_20 N9X_MUX('3',20,9) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC8_P5_PIO3_21 N9X_MUX('3',21,2) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SIM0_RST_PIO3_21 N9X_MUX('3',21,9) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO3_22 N9X_MUX('3',22,0) /* PT3_22 */ +#define FC8_P6_PIO3_22 N9X_MUX('3',22,2) /* PT3_22 */ +#define FC6_P2_PIO3_22 N9X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_PIO3_22 N9X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_PIO3_22 N9X_MUX('3',22,6) /* PT3_22 */ +#define EZH_PIO22_PIO3_22 N9X_MUX('3',22,7) /* PT3_22 */ +#define SIM0_VCCEN_PIO3_22 N9X_MUX('3',22,9) /* PT3_22 */ +#define SAI1_RXD1_PIO3_22 N9X_MUX('3',22,10) /* PT3_22 */ +#define PIO3_23 N9X_MUX('3',23,0) /* PT3_23 */ +#define FC6_P3_PIO3_23 N9X_MUX('3',23,3) /* PT3_23 */ +#define CT_INP11_PIO3_23 N9X_MUX('3',23,4) /* PT3_23 */ +#define FLEXIO0_D31_PIO3_23 N9X_MUX('3',23,6) /* PT3_23 */ +#define EZH_PIO23_PIO3_23 N9X_MUX('3',23,7) /* PT3_23 */ +#define SAI1_TXD1_PIO3_23 N9X_MUX('3',23,10) /* PT3_23 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PLU_IN0_PIO4_0 N9X_MUX('4',0,8) /* PT4_0 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define PLU_IN1_PIO4_1 N9X_MUX('4',1,8) /* PT4_1 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define DAC0_OUT_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define PLU_IN2_PIO4_2 N9X_MUX('4',2,8) /* PT4_2 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PLU_IN3_PIO4_3 N9X_MUX('4',3,8) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define PLU_IN4_PIO4_4 N9X_MUX('4',4,8) /* PT4_4 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PLU_IN5_PIO4_5 N9X_MUX('4',5,8) /* PT4_5 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PLU_CLK_PIO4_6 N9X_MUX('4',6,8) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define USB0_VBUS_DET_PIO4_12 N9X_MUX('4',12,1) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define PLU_OUT0_PIO4_12 N9X_MUX('4',12,8) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define PLU_OUT1_PIO4_13 N9X_MUX('4',13,8) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_14 N9X_MUX('4',14,0) /* PT4_14 */ +#define CT4_MAT2_PIO4_14 N9X_MUX('4',14,4) /* PT4_14 */ +#define FLEXIO0_D22_PIO4_14 N9X_MUX('4',14,6) /* PT4_14 */ +#define PLU_OUT2_PIO4_14 N9X_MUX('4',14,8) /* PT4_14 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define PLU_OUT3_PIO4_15 N9X_MUX('4',15,8) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define PLU_OUT4_PIO4_16 N9X_MUX('4',16,8) /* PT4_16 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PLU_OUT5_PIO4_17 N9X_MUX('4',17,8) /* PT4_17 */ +#define PIO4_18 N9X_MUX('4',18,0) /* PT4_18 */ +#define CT3_MAT2_PIO4_18 N9X_MUX('4',18,4) /* PT4_18 */ +#define FLEXIO0_D26_PIO4_18 N9X_MUX('4',18,6) /* PT4_18 */ +#define PLU_OUT6_PIO4_18 N9X_MUX('4',18,8) /* PT4_18 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define PLU_OUT7_PIO4_19 N9X_MUX('4',19,8) /* PT4_19 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define PIO4_22 N9X_MUX('4',22,0) /* PT4_22 */ +#define CT2_MAT2_PIO4_22 N9X_MUX('4',22,4) /* PT4_22 */ +#define FLEXIO0_D30_PIO4_22 N9X_MUX('4',22,6) /* PT4_22 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#define ADC1_B12_PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define TRIG_OUT7_PIO5_4 N9X_MUX('5',4,1) /* PT5_4 */ +#define SPC_LPREQ_PIO5_4 N9X_MUX('5',4,2) /* PT5_4 */ +#define TAMPER2_PIO5_4 N9X_MUX('5',4,3) /* PT5_4 */ +#define PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define ADC1_B13_PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define TRIG_IN10_PIO5_5 N9X_MUX('5',5,1) /* PT5_5 */ +#define LPTMR0_ALT2_PIO5_5 N9X_MUX('5',5,2) /* PT5_5 */ +#define TAMPER3_PIO5_5 N9X_MUX('5',5,3) /* PT5_5 */ +#define ADC1_B14_PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define TRIG_OUT6_PIO5_6 N9X_MUX('5',6,1) /* PT5_6 */ +#define LPTMR1_ALT2_PIO5_6 N9X_MUX('5',6,2) /* PT5_6 */ +#define TAMPER4_PIO5_6 N9X_MUX('5',6,3) /* PT5_6 */ +#define PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define ADC1_B15_PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define TRIG_IN11_PIO5_7 N9X_MUX('5',7,1) /* PT5_7 */ +#define TAMPER5_PIO5_7 N9X_MUX('5',7,3) /* PT5_7 */ +#define ADC1_B16_PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define TRIG_OUT7_PIO5_8 N9X_MUX('5',8,1) /* PT5_8 */ +#define TAMPER6_PIO5_8 N9X_MUX('5',8,3) /* PT5_8 */ +#define PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define ADC1_B17_PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define TAMPER7_PIO5_9 N9X_MUX('5',9,3) /* PT5_9 */ +#endif diff --git a/dts/nxp/mcx/MCXN547VNL-pinctrl.h b/dts/nxp/mcx/MCXN547VNL-pinctrl.h new file mode 100644 index 000000000..8f7085012 --- /dev/null +++ b/dts/nxp/mcx/MCXN547VNL-pinctrl.h @@ -0,0 +1,695 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN547VNL/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN547VNL_ +#define _ZEPHYR_DTS_BINDING_MCXN547VNL_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define TSI0_CH8_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define TSI0_CH9_PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define TSI0_CH10_PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define TSI0_CH11_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define TSI0_CH12_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define TSI0_CH13_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define TSI0_CH14_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define TSI0_CH15_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define TSI0_CH16_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TSI0_CH0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define SCT0_OUT6_PIO1_0 N9X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TSI0_CH1_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define SCT0_OUT7_PIO1_1 N9X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define TSI0_CH2_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define SCT0_IN6_PIO1_2 N9X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define ENET0_MDC_PIO1_2 N9X_MUX('1',2,9) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TSI0_CH3_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define SCT0_IN7_PIO1_3 N9X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define ENET0_MDIO_PIO1_3 N9X_MUX('1',3,9) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define TSI0_CH4_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define SCT0_OUT0_PIO1_4 N9X_MUX('1',4,5) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define ENET0_TX_CLK_PIO1_4 N9X_MUX('1',4,9) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define TSI0_CH5_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define SCT0_OUT1_PIO1_5 N9X_MUX('1',5,5) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define ENET0_TXEN_PIO1_5 N9X_MUX('1',5,9) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TSI0_CH6_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define SCT0_IN0_PIO1_6 N9X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define ENET0_TXD0_PIO1_6 N9X_MUX('1',6,9) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TSI0_CH7_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define SCT0_IN1_PIO1_7 N9X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define PLU_CLK_PIO1_7 N9X_MUX('1',7,8) /* PT1_7 */ +#define ENET0_TXD1_PIO1_7 N9X_MUX('1',7,9) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TSI0_CH17_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define SCT0_OUT2_PIO1_8 N9X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define PLU_OUT0_PIO1_8 N9X_MUX('1',8,8) /* PT1_8 */ +#define ENET0_TXD2_PIO1_8 N9X_MUX('1',8,9) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TSI0_CH18_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define SCT0_OUT3_PIO1_9 N9X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define PLU_OUT1_PIO1_9 N9X_MUX('1',9,8) /* PT1_9 */ +#define ENET0_TXD3_PIO1_9 N9X_MUX('1',9,9) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TSI0_CH19_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define SCT0_IN2_PIO1_10 N9X_MUX('1',10,5) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define PLU_IN0_PIO1_10 N9X_MUX('1',10,8) /* PT1_10 */ +#define ENET0_TXER_PIO1_10 N9X_MUX('1',10,9) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TSI0_CH20_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define SCT0_IN3_PIO1_11 N9X_MUX('1',11,5) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define PLU_IN1_PIO1_11 N9X_MUX('1',11,8) /* PT1_11 */ +#define ENET0_RX_CLK_PIO1_11 N9X_MUX('1',11,9) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TSI0_CH21_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define SCT0_OUT4_PIO1_12 N9X_MUX('1',12,5) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define PLU_OUT2_PIO1_12 N9X_MUX('1',12,8) /* PT1_12 */ +#define ENET0_RXER_PIO1_12 N9X_MUX('1',12,9) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TSI0_CH22_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define SCT0_OUT5_PIO1_13 N9X_MUX('1',13,5) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define PLU_OUT3_PIO1_13 N9X_MUX('1',13,8) /* PT1_13 */ +#define ENET0_RXDV_PIO1_13 N9X_MUX('1',13,9) /* PT1_13 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define TSI0_CH23_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define SCT0_IN4_PIO1_14 N9X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PLU_IN2_PIO1_14 N9X_MUX('1',14,8) /* PT1_14 */ +#define ENET0_RXD0_PIO1_14 N9X_MUX('1',14,9) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define TSI0_CH24_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define SCT0_IN5_PIO1_15 N9X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define PLU_IN3_PIO1_15 N9X_MUX('1',15,8) /* PT1_15 */ +#define ENET0_RXD1_PIO1_15 N9X_MUX('1',15,9) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SCT0_OUT8_PIO1_30 N9X_MUX('1',30,5) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define SCT0_OUT9_PIO1_31 N9X_MUX('1',31,5) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define FC9_P6_PIO2_0 N9X_MUX('2',0,2) /* PT2_0 */ +#define SDHC0_D5_PIO2_0 N9X_MUX('2',0,3) /* PT2_0 */ +#define SCT0_IN0_PIO2_0 N9X_MUX('2',0,4) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define FLEXSPI0_B_SS1_b_PIO2_0 N9X_MUX('2',0,8) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define SDHC0_D4_PIO2_1 N9X_MUX('2',1,3) /* PT2_1 */ +#define SCT0_IN1_PIO2_1 N9X_MUX('2',1,4) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define FLEXSPI0_B_DQS_PIO2_1 N9X_MUX('2',1,8) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define FC9_P3_PIO2_2 N9X_MUX('2',2,2) /* PT2_2 */ +#define SDHC0_D1_PIO2_2 N9X_MUX('2',2,3) /* PT2_2 */ +#define SCT0_OUT0_PIO2_2 N9X_MUX('2',2,4) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define FLEXSPI0_B_SS0_b_PIO2_2 N9X_MUX('2',2,8) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define FC9_P1_PIO2_3 N9X_MUX('2',3,2) /* PT2_3 */ +#define SDHC0_D0_PIO2_3 N9X_MUX('2',3,3) /* PT2_3 */ +#define SCT0_OUT1_PIO2_3 N9X_MUX('2',3,4) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define FLEXSPI0_B_SCLK_PIO2_3 N9X_MUX('2',3,8) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define FC9_P0_PIO2_4 N9X_MUX('2',4,2) /* PT2_4 */ +#define SDHC0_CLK_PIO2_4 N9X_MUX('2',4,3) /* PT2_4 */ +#define SCT0_OUT2_PIO2_4 N9X_MUX('2',4,4) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define FLEXSPI0_B_DATA0_PIO2_4 N9X_MUX('2',4,8) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define FC9_P2_PIO2_5 N9X_MUX('2',5,2) /* PT2_5 */ +#define SDHC0_CMD_PIO2_5 N9X_MUX('2',5,3) /* PT2_5 */ +#define SCT0_OUT3_PIO2_5 N9X_MUX('2',5,4) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define FLEXSPI0_B_DATA1_PIO2_5 N9X_MUX('2',5,8) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define FC9_P4_PIO2_6 N9X_MUX('2',6,2) /* PT2_6 */ +#define SDHC0_D3_PIO2_6 N9X_MUX('2',6,3) /* PT2_6 */ +#define SCT0_OUT4_PIO2_6 N9X_MUX('2',6,4) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define FLEXSPI0_B_DATA2_PIO2_6 N9X_MUX('2',6,8) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define FC9_P5_PIO2_7 N9X_MUX('2',7,2) /* PT2_7 */ +#define SDHC0_D2_PIO2_7 N9X_MUX('2',7,3) /* PT2_7 */ +#define SCT0_OUT5_PIO2_7 N9X_MUX('2',7,4) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define FLEXSPI0_B_DATA3_PIO2_7 N9X_MUX('2',7,8) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define FLEXSPI0_A_SS0_b_PIO3_0 N9X_MUX('3',0,8) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FLEXSPI0_A_SS1_b_PIO3_1 N9X_MUX('3',1,8) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define FLEXSPI0_A_DQS_PIO3_6 N9X_MUX('3',6,8) /* PT3_6 */ +#define SIM1_VCCEN_PIO3_6 N9X_MUX('3',6,9) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define FLEXSPI0_A_SCLK_PIO3_7 N9X_MUX('3',7,8) /* PT3_7 */ +#define SIM0_VCCEN_PIO3_7 N9X_MUX('3',7,9) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define FLEXSPI0_A_DATA0_PIO3_8 N9X_MUX('3',8,8) /* PT3_8 */ +#define SIM0_PD_PIO3_8 N9X_MUX('3',8,9) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define FLEXSPI0_A_DATA1_PIO3_9 N9X_MUX('3',9,8) /* PT3_9 */ +#define SIM0_RST_PIO3_9 N9X_MUX('3',9,9) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define FLEXSPI0_A_DATA2_PIO3_10 N9X_MUX('3',10,8) /* PT3_10 */ +#define SIM0_CLK_PIO3_10 N9X_MUX('3',10,9) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define FLEXSPI0_A_DATA3_PIO3_11 N9X_MUX('3',11,8) /* PT3_11 */ +#define SIM0_IO_PIO3_11 N9X_MUX('3',11,9) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define FLEXSPI0_A_DATA4_PIO3_12 N9X_MUX('3',12,8) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define FLEXSPI0_A_DATA5_PIO3_13 N9X_MUX('3',13,8) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define FC8_P0_PIO3_14 N9X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define FLEXSPI0_A_DATA6_PIO3_14 N9X_MUX('3',14,8) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define FC8_P1_PIO3_15 N9X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define FLEXSPI0_A_DATA7_PIO3_15 N9X_MUX('3',15,8) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define FC8_P2_PIO3_16 N9X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SIM0_CLK_PIO3_16 N9X_MUX('3',16,9) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define FC8_P3_PIO3_17 N9X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SIM0_IO_PIO3_17 N9X_MUX('3',17,9) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC8_P4_PIO3_20 N9X_MUX('3',20,2) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SIM0_PD_PIO3_20 N9X_MUX('3',20,9) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC8_P5_PIO3_21 N9X_MUX('3',21,2) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SIM0_RST_PIO3_21 N9X_MUX('3',21,9) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define ADC0_A0_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PLU_IN0_PIO4_0 N9X_MUX('4',0,8) /* PT4_0 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define ADC0_B0_PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define PLU_IN1_PIO4_1 N9X_MUX('4',1,8) /* PT4_1 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define DAC0_OUT_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define PLU_IN2_PIO4_2 N9X_MUX('4',2,8) /* PT4_2 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PLU_IN3_PIO4_3 N9X_MUX('4',3,8) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define ADC1_A0_PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define PLU_IN4_PIO4_4 N9X_MUX('4',4,8) /* PT4_4 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define ADC1_B0_PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PLU_IN5_PIO4_5 N9X_MUX('4',5,8) /* PT4_5 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define ADC1_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define ADC0_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PLU_CLK_PIO4_6 N9X_MUX('4',6,8) /* PT4_6 */ +#define VREFO_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define ADC1_A7_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define ADC0_A7_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define USB0_VBUS_DET_PIO4_12 N9X_MUX('4',12,1) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define PLU_OUT0_PIO4_12 N9X_MUX('4',12,8) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define PLU_OUT1_PIO4_13 N9X_MUX('4',13,8) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define PLU_OUT3_PIO4_15 N9X_MUX('4',15,8) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define PLU_OUT4_PIO4_16 N9X_MUX('4',16,8) /* PT4_16 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PLU_OUT5_PIO4_17 N9X_MUX('4',17,8) /* PT4_17 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#endif diff --git a/dts/nxp/mcx/MCXN547VPB-pinctrl.h b/dts/nxp/mcx/MCXN547VPB-pinctrl.h new file mode 100644 index 000000000..4f683e51a --- /dev/null +++ b/dts/nxp/mcx/MCXN547VPB-pinctrl.h @@ -0,0 +1,933 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN547VPB/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN547VPB_ +#define _ZEPHYR_DTS_BINDING_MCXN547VPB_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define TSI0_CH8_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define TSI0_CH9_PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define TSI0_CH10_PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define WUU0_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define FC0_P3_PIO0_7 N9X_MUX('0',7,2) /* PT0_7 */ +#define CT_INP3_PIO0_7 N9X_MUX('0',7,4) /* PT0_7 */ +#define PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define ADC0_B8_PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define FC0_P4_PIO0_8 N9X_MUX('0',8,2) /* PT0_8 */ +#define CT_INP0_PIO0_8 N9X_MUX('0',8,4) /* PT0_8 */ +#define FLEXIO0_D0_PIO0_8 N9X_MUX('0',8,6) /* PT0_8 */ +#define PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define ADC0_B9_PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define FC0_P5_PIO0_9 N9X_MUX('0',9,2) /* PT0_9 */ +#define CT_INP1_PIO0_9 N9X_MUX('0',9,4) /* PT0_9 */ +#define FLEXIO0_D1_PIO0_9 N9X_MUX('0',9,6) /* PT0_9 */ +#define PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define ADC0_B10_PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define FC0_P6_PIO0_10 N9X_MUX('0',10,2) /* PT0_10 */ +#define CT0_MAT0_PIO0_10 N9X_MUX('0',10,4) /* PT0_10 */ +#define FLEXIO0_D2_PIO0_10 N9X_MUX('0',10,6) /* PT0_10 */ +#define PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define ADC0_B11_PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define CT0_MAT1_PIO0_11 N9X_MUX('0',11,4) /* PT0_11 */ +#define FLEXIO0_D3_PIO0_11 N9X_MUX('0',11,6) /* PT0_11 */ +#define PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define ADC0_B12_PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define FC1_P4_PIO0_12 N9X_MUX('0',12,2) /* PT0_12 */ +#define FC0_P0_PIO0_12 N9X_MUX('0',12,3) /* PT0_12 */ +#define CT0_MAT2_PIO0_12 N9X_MUX('0',12,4) /* PT0_12 */ +#define FLEXIO0_D4_PIO0_12 N9X_MUX('0',12,6) /* PT0_12 */ +#define PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define ADC0_B13_PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define FC1_P5_PIO0_13 N9X_MUX('0',13,2) /* PT0_13 */ +#define FC0_P1_PIO0_13 N9X_MUX('0',13,3) /* PT0_13 */ +#define CT0_MAT3_PIO0_13 N9X_MUX('0',13,4) /* PT0_13 */ +#define FLEXIO0_D5_PIO0_13 N9X_MUX('0',13,6) /* PT0_13 */ +#define PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define ADC0_B14_PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define FC1_P6_PIO0_14 N9X_MUX('0',14,2) /* PT0_14 */ +#define FC0_P2_PIO0_14 N9X_MUX('0',14,3) /* PT0_14 */ +#define CT_INP2_PIO0_14 N9X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_PIO0_14 N9X_MUX('0',14,5) /* PT0_14 */ +#define FLEXIO0_D6_PIO0_14 N9X_MUX('0',14,6) /* PT0_14 */ +#define PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define ADC0_B15_PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define FC0_P3_PIO0_15 N9X_MUX('0',15,3) /* PT0_15 */ +#define CT_INP3_PIO0_15 N9X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_PIO0_15 N9X_MUX('0',15,5) /* PT0_15 */ +#define FLEXIO0_D7_PIO0_15 N9X_MUX('0',15,6) /* PT0_15 */ +#define TSI0_CH11_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define TSI0_CH12_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define TSI0_CH13_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define TSI0_CH14_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define TSI0_CH15_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define TSI0_CH16_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define ADC0_B16_PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define FC1_P0_PIO0_24 N9X_MUX('0',24,2) /* PT0_24 */ +#define CT0_MAT0_PIO0_24 N9X_MUX('0',24,4) /* PT0_24 */ +#define PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define ADC0_B17_PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define FC1_P1_PIO0_25 N9X_MUX('0',25,2) /* PT0_25 */ +#define CT0_MAT1_PIO0_25 N9X_MUX('0',25,4) /* PT0_25 */ +#define PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define ADC0_B18_PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define FC1_P2_PIO0_26 N9X_MUX('0',26,2) /* PT0_26 */ +#define CT0_MAT2_PIO0_26 N9X_MUX('0',26,4) /* PT0_26 */ +#define PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define ADC0_B19_PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define FC1_P3_PIO0_27 N9X_MUX('0',27,2) /* PT0_27 */ +#define CT0_MAT3_PIO0_27 N9X_MUX('0',27,4) /* PT0_27 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TSI0_CH0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define SCT0_OUT6_PIO1_0 N9X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TSI0_CH1_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define SCT0_OUT7_PIO1_1 N9X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define TSI0_CH2_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define SCT0_IN6_PIO1_2 N9X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define ENET0_MDC_PIO1_2 N9X_MUX('1',2,9) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TSI0_CH3_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define SCT0_IN7_PIO1_3 N9X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define ENET0_MDIO_PIO1_3 N9X_MUX('1',3,9) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define TSI0_CH4_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define SCT0_OUT0_PIO1_4 N9X_MUX('1',4,5) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define ENET0_TX_CLK_PIO1_4 N9X_MUX('1',4,9) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define TSI0_CH5_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define SCT0_OUT1_PIO1_5 N9X_MUX('1',5,5) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define ENET0_TXEN_PIO1_5 N9X_MUX('1',5,9) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TSI0_CH6_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define SCT0_IN0_PIO1_6 N9X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define ENET0_TXD0_PIO1_6 N9X_MUX('1',6,9) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TSI0_CH7_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define SCT0_IN1_PIO1_7 N9X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define PLU_CLK_PIO1_7 N9X_MUX('1',7,8) /* PT1_7 */ +#define ENET0_TXD1_PIO1_7 N9X_MUX('1',7,9) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TSI0_CH17_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define SCT0_OUT2_PIO1_8 N9X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define PLU_OUT0_PIO1_8 N9X_MUX('1',8,8) /* PT1_8 */ +#define ENET0_TXD2_PIO1_8 N9X_MUX('1',8,9) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TSI0_CH18_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define SCT0_OUT3_PIO1_9 N9X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define PLU_OUT1_PIO1_9 N9X_MUX('1',9,8) /* PT1_9 */ +#define ENET0_TXD3_PIO1_9 N9X_MUX('1',9,9) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TSI0_CH19_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define SCT0_IN2_PIO1_10 N9X_MUX('1',10,5) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define PLU_IN0_PIO1_10 N9X_MUX('1',10,8) /* PT1_10 */ +#define ENET0_TXER_PIO1_10 N9X_MUX('1',10,9) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TSI0_CH20_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define SCT0_IN3_PIO1_11 N9X_MUX('1',11,5) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define PLU_IN1_PIO1_11 N9X_MUX('1',11,8) /* PT1_11 */ +#define ENET0_RX_CLK_PIO1_11 N9X_MUX('1',11,9) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TSI0_CH21_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define SCT0_OUT4_PIO1_12 N9X_MUX('1',12,5) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define PLU_OUT2_PIO1_12 N9X_MUX('1',12,8) /* PT1_12 */ +#define ENET0_RXER_PIO1_12 N9X_MUX('1',12,9) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TSI0_CH22_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define SCT0_OUT5_PIO1_13 N9X_MUX('1',13,5) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define PLU_OUT3_PIO1_13 N9X_MUX('1',13,8) /* PT1_13 */ +#define ENET0_RXDV_PIO1_13 N9X_MUX('1',13,9) /* PT1_13 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define TSI0_CH23_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define SCT0_IN4_PIO1_14 N9X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PLU_IN2_PIO1_14 N9X_MUX('1',14,8) /* PT1_14 */ +#define ENET0_RXD0_PIO1_14 N9X_MUX('1',14,9) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define TSI0_CH24_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define SCT0_IN5_PIO1_15 N9X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define PLU_IN3_PIO1_15 N9X_MUX('1',15,8) /* PT1_15 */ +#define ENET0_RXD1_PIO1_15 N9X_MUX('1',15,9) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define ADC1_A16_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define WUU0_IN14_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define FC5_P0_PIO1_16 N9X_MUX('1',16,2) /* PT1_16 */ +#define FC3_P4_PIO1_16 N9X_MUX('1',16,3) /* PT1_16 */ +#define CT_INP12_PIO1_16 N9X_MUX('1',16,4) /* PT1_16 */ +#define SCT0_OUT6_PIO1_16 N9X_MUX('1',16,5) /* PT1_16 */ +#define FLEXIO0_D24_PIO1_16 N9X_MUX('1',16,6) /* PT1_16 */ +#define EZH_PIO12_PIO1_16 N9X_MUX('1',16,7) /* PT1_16 */ +#define PLU_OUT4_PIO1_16 N9X_MUX('1',16,8) /* PT1_16 */ +#define ENET0_RXD2_PIO1_16 N9X_MUX('1',16,9) /* PT1_16 */ +#define I3C1_SDA_PIO1_16 N9X_MUX('1',16,10) /* PT1_16 */ +#define PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define ADC1_A17_PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define FC5_P1_PIO1_17 N9X_MUX('1',17,2) /* PT1_17 */ +#define FC3_P5_PIO1_17 N9X_MUX('1',17,3) /* PT1_17 */ +#define CT_INP13_PIO1_17 N9X_MUX('1',17,4) /* PT1_17 */ +#define SCT0_OUT7_PIO1_17 N9X_MUX('1',17,5) /* PT1_17 */ +#define FLEXIO0_D25_PIO1_17 N9X_MUX('1',17,6) /* PT1_17 */ +#define EZH_PIO13_PIO1_17 N9X_MUX('1',17,7) /* PT1_17 */ +#define PLU_OUT5_PIO1_17 N9X_MUX('1',17,8) /* PT1_17 */ +#define ENET0_RXD3_PIO1_17 N9X_MUX('1',17,9) /* PT1_17 */ +#define I3C1_SCL_PIO1_17 N9X_MUX('1',17,10) /* PT1_17 */ +#define PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define ADC1_A18_PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define FREQME_CLK_IN0_PIO1_18 N9X_MUX('1',18,1) /* PT1_18 */ +#define FC5_P2_PIO1_18 N9X_MUX('1',18,2) /* PT1_18 */ +#define FC3_P6_PIO1_18 N9X_MUX('1',18,3) /* PT1_18 */ +#define CT3_MAT0_PIO1_18 N9X_MUX('1',18,4) /* PT1_18 */ +#define SCT0_IN6_PIO1_18 N9X_MUX('1',18,5) /* PT1_18 */ +#define FLEXIO0_D26_PIO1_18 N9X_MUX('1',18,6) /* PT1_18 */ +#define EZH_PIO14_PIO1_18 N9X_MUX('1',18,7) /* PT1_18 */ +#define PLU_IN4_PIO1_18 N9X_MUX('1',18,8) /* PT1_18 */ +#define ENET0_COL_PIO1_18 N9X_MUX('1',18,9) /* PT1_18 */ +#define CAN0_TXD_PIO1_18 N9X_MUX('1',18,11) /* PT1_18 */ +#define PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define ADC1_A19_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define WUU0_IN15_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define FREQME_CLK_IN1_PIO1_19 N9X_MUX('1',19,1) /* PT1_19 */ +#define FC5_P3_PIO1_19 N9X_MUX('1',19,2) /* PT1_19 */ +#define CT3_MAT1_PIO1_19 N9X_MUX('1',19,4) /* PT1_19 */ +#define SCT0_IN7_PIO1_19 N9X_MUX('1',19,5) /* PT1_19 */ +#define FLEXIO0_D27_PIO1_19 N9X_MUX('1',19,6) /* PT1_19 */ +#define EZH_PIO15_PIO1_19 N9X_MUX('1',19,7) /* PT1_19 */ +#define PLU_IN5_PIO1_19 N9X_MUX('1',19,8) /* PT1_19 */ +#define ENET0_CRS_PIO1_19 N9X_MUX('1',19,9) /* PT1_19 */ +#define CAN0_RXD_PIO1_19 N9X_MUX('1',19,11) /* PT1_19 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SCT0_OUT8_PIO1_30 N9X_MUX('1',30,5) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define SCT0_OUT9_PIO1_31 N9X_MUX('1',31,5) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define FC9_P6_PIO2_0 N9X_MUX('2',0,2) /* PT2_0 */ +#define SDHC0_D5_PIO2_0 N9X_MUX('2',0,3) /* PT2_0 */ +#define SCT0_IN0_PIO2_0 N9X_MUX('2',0,4) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define FLEXSPI0_B_SS1_b_PIO2_0 N9X_MUX('2',0,8) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define SDHC0_D4_PIO2_1 N9X_MUX('2',1,3) /* PT2_1 */ +#define SCT0_IN1_PIO2_1 N9X_MUX('2',1,4) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define FLEXSPI0_B_DQS_PIO2_1 N9X_MUX('2',1,8) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define FC9_P3_PIO2_2 N9X_MUX('2',2,2) /* PT2_2 */ +#define SDHC0_D1_PIO2_2 N9X_MUX('2',2,3) /* PT2_2 */ +#define SCT0_OUT0_PIO2_2 N9X_MUX('2',2,4) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define FLEXSPI0_B_SS0_b_PIO2_2 N9X_MUX('2',2,8) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define FC9_P1_PIO2_3 N9X_MUX('2',3,2) /* PT2_3 */ +#define SDHC0_D0_PIO2_3 N9X_MUX('2',3,3) /* PT2_3 */ +#define SCT0_OUT1_PIO2_3 N9X_MUX('2',3,4) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define FLEXSPI0_B_SCLK_PIO2_3 N9X_MUX('2',3,8) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define FC9_P0_PIO2_4 N9X_MUX('2',4,2) /* PT2_4 */ +#define SDHC0_CLK_PIO2_4 N9X_MUX('2',4,3) /* PT2_4 */ +#define SCT0_OUT2_PIO2_4 N9X_MUX('2',4,4) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define FLEXSPI0_B_DATA0_PIO2_4 N9X_MUX('2',4,8) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define FC9_P2_PIO2_5 N9X_MUX('2',5,2) /* PT2_5 */ +#define SDHC0_CMD_PIO2_5 N9X_MUX('2',5,3) /* PT2_5 */ +#define SCT0_OUT3_PIO2_5 N9X_MUX('2',5,4) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define FLEXSPI0_B_DATA1_PIO2_5 N9X_MUX('2',5,8) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define FC9_P4_PIO2_6 N9X_MUX('2',6,2) /* PT2_6 */ +#define SDHC0_D3_PIO2_6 N9X_MUX('2',6,3) /* PT2_6 */ +#define SCT0_OUT4_PIO2_6 N9X_MUX('2',6,4) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define FLEXSPI0_B_DATA2_PIO2_6 N9X_MUX('2',6,8) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define FC9_P5_PIO2_7 N9X_MUX('2',7,2) /* PT2_7 */ +#define SDHC0_D2_PIO2_7 N9X_MUX('2',7,3) /* PT2_7 */ +#define SCT0_OUT5_PIO2_7 N9X_MUX('2',7,4) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define FLEXSPI0_B_DATA3_PIO2_7 N9X_MUX('2',7,8) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO2_8 N9X_MUX('2',8,0) /* PT2_8 */ +#define TRACE_DATA0_PIO2_8 N9X_MUX('2',8,1) /* PT2_8 */ +#define SDHC0_D7_PIO2_8 N9X_MUX('2',8,3) /* PT2_8 */ +#define SCT0_IN2_PIO2_8 N9X_MUX('2',8,4) /* PT2_8 */ +#define FLEXIO0_D16_PIO2_8 N9X_MUX('2',8,6) /* PT2_8 */ +#define EZH_PIO28_PIO2_8 N9X_MUX('2',8,7) /* PT2_8 */ +#define FLEXSPI0_B_DATA4_PIO2_8 N9X_MUX('2',8,8) /* PT2_8 */ +#define SAI1_TXD0_PIO2_8 N9X_MUX('2',8,10) /* PT2_8 */ +#define PIO2_9 N9X_MUX('2',9,0) /* PT2_9 */ +#define TRACE_DATA1_PIO2_9 N9X_MUX('2',9,1) /* PT2_9 */ +#define SDHC0_D6_PIO2_9 N9X_MUX('2',9,3) /* PT2_9 */ +#define SCT0_IN3_PIO2_9 N9X_MUX('2',9,4) /* PT2_9 */ +#define FLEXIO0_D17_PIO2_9 N9X_MUX('2',9,6) /* PT2_9 */ +#define EZH_PIO29_PIO2_9 N9X_MUX('2',9,7) /* PT2_9 */ +#define FLEXSPI0_B_DATA5_PIO2_9 N9X_MUX('2',9,8) /* PT2_9 */ +#define SAI1_RXD0_PIO2_9 N9X_MUX('2',9,10) /* PT2_9 */ +#define PIO2_10 N9X_MUX('2',10,0) /* PT2_10 */ +#define TRACE_DATA2_PIO2_10 N9X_MUX('2',10,1) /* PT2_10 */ +#define SCT0_IN4_PIO2_10 N9X_MUX('2',10,4) /* PT2_10 */ +#define FLEXIO0_D18_PIO2_10 N9X_MUX('2',10,6) /* PT2_10 */ +#define EZH_PIO31_PIO2_10 N9X_MUX('2',10,7) /* PT2_10 */ +#define FLEXSPI0_B_DATA6_PIO2_10 N9X_MUX('2',10,8) /* PT2_10 */ +#define SAI1_RXD1_PIO2_10 N9X_MUX('2',10,10) /* PT2_10 */ +#define PIO2_11 N9X_MUX('2',11,0) /* PT2_11 */ +#define TRACE_DATA3_PIO2_11 N9X_MUX('2',11,1) /* PT2_11 */ +#define SCT0_IN5_PIO2_11 N9X_MUX('2',11,4) /* PT2_11 */ +#define FLEXIO0_D19_PIO2_11 N9X_MUX('2',11,6) /* PT2_11 */ +#define EZH_PIO30_PIO2_11 N9X_MUX('2',11,7) /* PT2_11 */ +#define FLEXSPI0_B_DATA7_PIO2_11 N9X_MUX('2',11,8) /* PT2_11 */ +#define SAI1_TXD1_PIO2_11 N9X_MUX('2',11,10) /* PT2_11 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define FLEXSPI0_A_SS0_b_PIO3_0 N9X_MUX('3',0,8) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FLEXSPI0_A_SS1_b_PIO3_1 N9X_MUX('3',1,8) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_2 N9X_MUX('3',2,0) /* PT3_2 */ +#define FC7_P0_PIO3_2 N9X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_PIO3_2 N9X_MUX('3',2,4) /* PT3_2 */ +#define PWM0_X0_PIO3_2 N9X_MUX('3',2,5) /* PT3_2 */ +#define FLEXIO0_D10_PIO3_2 N9X_MUX('3',2,6) /* PT3_2 */ +#define EZH_PIO2_PIO3_2 N9X_MUX('3',2,7) /* PT3_2 */ +#define SIM1_PD_PIO3_2 N9X_MUX('3',2,9) /* PT3_2 */ +#define PIO3_3 N9X_MUX('3',3,0) /* PT3_3 */ +#define FC7_P1_PIO3_3 N9X_MUX('3',3,2) /* PT3_3 */ +#define CT4_MAT1_PIO3_3 N9X_MUX('3',3,4) /* PT3_3 */ +#define PWM0_X1_PIO3_3 N9X_MUX('3',3,5) /* PT3_3 */ +#define FLEXIO0_D11_PIO3_3 N9X_MUX('3',3,6) /* PT3_3 */ +#define EZH_PIO3_PIO3_3 N9X_MUX('3',3,7) /* PT3_3 */ +#define SIM1_RST_PIO3_3 N9X_MUX('3',3,9) /* PT3_3 */ +#define PIO3_4 N9X_MUX('3',4,0) /* PT3_4 */ +#define FC7_P2_PIO3_4 N9X_MUX('3',4,2) /* PT3_4 */ +#define CT_INP18_PIO3_4 N9X_MUX('3',4,4) /* PT3_4 */ +#define PWM0_X2_PIO3_4 N9X_MUX('3',4,5) /* PT3_4 */ +#define FLEXIO0_D12_PIO3_4 N9X_MUX('3',4,6) /* PT3_4 */ +#define EZH_PIO4_PIO3_4 N9X_MUX('3',4,7) /* PT3_4 */ +#define SIM1_CLK_PIO3_4 N9X_MUX('3',4,9) /* PT3_4 */ +#define PIO3_5 N9X_MUX('3',5,0) /* PT3_5 */ +#define FC7_P3_PIO3_5 N9X_MUX('3',5,2) /* PT3_5 */ +#define CT_INP19_PIO3_5 N9X_MUX('3',5,4) /* PT3_5 */ +#define PWM0_X3_PIO3_5 N9X_MUX('3',5,5) /* PT3_5 */ +#define FLEXIO0_D13_PIO3_5 N9X_MUX('3',5,6) /* PT3_5 */ +#define EZH_PIO5_PIO3_5 N9X_MUX('3',5,7) /* PT3_5 */ +#define SIM1_IO_PIO3_5 N9X_MUX('3',5,9) /* PT3_5 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define FLEXSPI0_A_DQS_PIO3_6 N9X_MUX('3',6,8) /* PT3_6 */ +#define SIM1_VCCEN_PIO3_6 N9X_MUX('3',6,9) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define FLEXSPI0_A_SCLK_PIO3_7 N9X_MUX('3',7,8) /* PT3_7 */ +#define SIM0_VCCEN_PIO3_7 N9X_MUX('3',7,9) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define FLEXSPI0_A_DATA0_PIO3_8 N9X_MUX('3',8,8) /* PT3_8 */ +#define SIM0_PD_PIO3_8 N9X_MUX('3',8,9) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define FLEXSPI0_A_DATA1_PIO3_9 N9X_MUX('3',9,8) /* PT3_9 */ +#define SIM0_RST_PIO3_9 N9X_MUX('3',9,9) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define FLEXSPI0_A_DATA2_PIO3_10 N9X_MUX('3',10,8) /* PT3_10 */ +#define SIM0_CLK_PIO3_10 N9X_MUX('3',10,9) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define FLEXSPI0_A_DATA3_PIO3_11 N9X_MUX('3',11,8) /* PT3_11 */ +#define SIM0_IO_PIO3_11 N9X_MUX('3',11,9) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define FLEXSPI0_A_DATA4_PIO3_12 N9X_MUX('3',12,8) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define FLEXSPI0_A_DATA5_PIO3_13 N9X_MUX('3',13,8) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define FC8_P0_PIO3_14 N9X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define FLEXSPI0_A_DATA6_PIO3_14 N9X_MUX('3',14,8) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define FC8_P1_PIO3_15 N9X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define FLEXSPI0_A_DATA7_PIO3_15 N9X_MUX('3',15,8) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define FC8_P2_PIO3_16 N9X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SIM0_CLK_PIO3_16 N9X_MUX('3',16,9) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define FC8_P3_PIO3_17 N9X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SIM0_IO_PIO3_17 N9X_MUX('3',17,9) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC8_P4_PIO3_20 N9X_MUX('3',20,2) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SIM0_PD_PIO3_20 N9X_MUX('3',20,9) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC8_P5_PIO3_21 N9X_MUX('3',21,2) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SIM0_RST_PIO3_21 N9X_MUX('3',21,9) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO3_22 N9X_MUX('3',22,0) /* PT3_22 */ +#define FC8_P6_PIO3_22 N9X_MUX('3',22,2) /* PT3_22 */ +#define FC6_P2_PIO3_22 N9X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_PIO3_22 N9X_MUX('3',22,4) /* PT3_22 */ +#define FLEXIO0_D30_PIO3_22 N9X_MUX('3',22,6) /* PT3_22 */ +#define EZH_PIO22_PIO3_22 N9X_MUX('3',22,7) /* PT3_22 */ +#define SIM0_VCCEN_PIO3_22 N9X_MUX('3',22,9) /* PT3_22 */ +#define SAI1_RXD1_PIO3_22 N9X_MUX('3',22,10) /* PT3_22 */ +#define PIO3_23 N9X_MUX('3',23,0) /* PT3_23 */ +#define FC6_P3_PIO3_23 N9X_MUX('3',23,3) /* PT3_23 */ +#define CT_INP11_PIO3_23 N9X_MUX('3',23,4) /* PT3_23 */ +#define FLEXIO0_D31_PIO3_23 N9X_MUX('3',23,6) /* PT3_23 */ +#define EZH_PIO23_PIO3_23 N9X_MUX('3',23,7) /* PT3_23 */ +#define SAI1_TXD1_PIO3_23 N9X_MUX('3',23,10) /* PT3_23 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PLU_IN0_PIO4_0 N9X_MUX('4',0,8) /* PT4_0 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define PLU_IN1_PIO4_1 N9X_MUX('4',1,8) /* PT4_1 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define DAC0_OUT_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define PLU_IN2_PIO4_2 N9X_MUX('4',2,8) /* PT4_2 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PLU_IN3_PIO4_3 N9X_MUX('4',3,8) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define PLU_IN4_PIO4_4 N9X_MUX('4',4,8) /* PT4_4 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PLU_IN5_PIO4_5 N9X_MUX('4',5,8) /* PT4_5 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PLU_CLK_PIO4_6 N9X_MUX('4',6,8) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define USB0_VBUS_DET_PIO4_12 N9X_MUX('4',12,1) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define PLU_OUT0_PIO4_12 N9X_MUX('4',12,8) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define PLU_OUT1_PIO4_13 N9X_MUX('4',13,8) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_14 N9X_MUX('4',14,0) /* PT4_14 */ +#define CT4_MAT2_PIO4_14 N9X_MUX('4',14,4) /* PT4_14 */ +#define FLEXIO0_D22_PIO4_14 N9X_MUX('4',14,6) /* PT4_14 */ +#define PLU_OUT2_PIO4_14 N9X_MUX('4',14,8) /* PT4_14 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define PLU_OUT3_PIO4_15 N9X_MUX('4',15,8) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define PLU_OUT4_PIO4_16 N9X_MUX('4',16,8) /* PT4_16 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PLU_OUT5_PIO4_17 N9X_MUX('4',17,8) /* PT4_17 */ +#define PIO4_18 N9X_MUX('4',18,0) /* PT4_18 */ +#define CT3_MAT2_PIO4_18 N9X_MUX('4',18,4) /* PT4_18 */ +#define FLEXIO0_D26_PIO4_18 N9X_MUX('4',18,6) /* PT4_18 */ +#define PLU_OUT6_PIO4_18 N9X_MUX('4',18,8) /* PT4_18 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define PLU_OUT7_PIO4_19 N9X_MUX('4',19,8) /* PT4_19 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define PIO4_22 N9X_MUX('4',22,0) /* PT4_22 */ +#define CT2_MAT2_PIO4_22 N9X_MUX('4',22,4) /* PT4_22 */ +#define FLEXIO0_D30_PIO4_22 N9X_MUX('4',22,6) /* PT4_22 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#define ADC1_B12_PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define TRIG_OUT7_PIO5_4 N9X_MUX('5',4,1) /* PT5_4 */ +#define SPC_LPREQ_PIO5_4 N9X_MUX('5',4,2) /* PT5_4 */ +#define TAMPER2_PIO5_4 N9X_MUX('5',4,3) /* PT5_4 */ +#define PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define ADC1_B13_PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define TRIG_IN10_PIO5_5 N9X_MUX('5',5,1) /* PT5_5 */ +#define LPTMR0_ALT2_PIO5_5 N9X_MUX('5',5,2) /* PT5_5 */ +#define TAMPER3_PIO5_5 N9X_MUX('5',5,3) /* PT5_5 */ +#define ADC1_B14_PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define TRIG_OUT6_PIO5_6 N9X_MUX('5',6,1) /* PT5_6 */ +#define LPTMR1_ALT2_PIO5_6 N9X_MUX('5',6,2) /* PT5_6 */ +#define TAMPER4_PIO5_6 N9X_MUX('5',6,3) /* PT5_6 */ +#define PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define ADC1_B15_PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define TRIG_IN11_PIO5_7 N9X_MUX('5',7,1) /* PT5_7 */ +#define TAMPER5_PIO5_7 N9X_MUX('5',7,3) /* PT5_7 */ +#define ADC1_B16_PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define TRIG_OUT7_PIO5_8 N9X_MUX('5',8,1) /* PT5_8 */ +#define TAMPER6_PIO5_8 N9X_MUX('5',8,3) /* PT5_8 */ +#define PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define ADC1_B17_PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define TAMPER7_PIO5_9 N9X_MUX('5',9,3) /* PT5_9 */ +#endif diff --git a/dts/nxp/mcx/MCXN946VDF-pinctrl.h b/dts/nxp/mcx/MCXN946VDF-pinctrl.h new file mode 100644 index 000000000..3129b395e --- /dev/null +++ b/dts/nxp/mcx/MCXN946VDF-pinctrl.h @@ -0,0 +1,1022 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN946VDF/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN946VDF_ +#define _ZEPHYR_DTS_BINDING_MCXN946VDF_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define HSCMP2_OUT_PIO0_6 N9X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define CMP2_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define WUU0_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define FC0_P3_PIO0_7 N9X_MUX('0',7,2) /* PT0_7 */ +#define CT_INP3_PIO0_7 N9X_MUX('0',7,4) /* PT0_7 */ +#define PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define ADC0_B8_PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define FC0_P4_PIO0_8 N9X_MUX('0',8,2) /* PT0_8 */ +#define CT_INP0_PIO0_8 N9X_MUX('0',8,4) /* PT0_8 */ +#define FLEXIO0_D0_PIO0_8 N9X_MUX('0',8,6) /* PT0_8 */ +#define PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define ADC0_B9_PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define FC0_P5_PIO0_9 N9X_MUX('0',9,2) /* PT0_9 */ +#define CT_INP1_PIO0_9 N9X_MUX('0',9,4) /* PT0_9 */ +#define FLEXIO0_D1_PIO0_9 N9X_MUX('0',9,6) /* PT0_9 */ +#define PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define ADC0_B10_PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define FC0_P6_PIO0_10 N9X_MUX('0',10,2) /* PT0_10 */ +#define CT0_MAT0_PIO0_10 N9X_MUX('0',10,4) /* PT0_10 */ +#define FLEXIO0_D2_PIO0_10 N9X_MUX('0',10,6) /* PT0_10 */ +#define ADC0_B11_PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define CT0_MAT1_PIO0_11 N9X_MUX('0',11,4) /* PT0_11 */ +#define FLEXIO0_D3_PIO0_11 N9X_MUX('0',11,6) /* PT0_11 */ +#define HSCMP2_OUT_PIO0_11 N9X_MUX('0',11,8) /* PT0_11 */ +#define PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define ADC0_B12_PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define FC1_P4_PIO0_12 N9X_MUX('0',12,2) /* PT0_12 */ +#define FC0_P0_PIO0_12 N9X_MUX('0',12,3) /* PT0_12 */ +#define CT0_MAT2_PIO0_12 N9X_MUX('0',12,4) /* PT0_12 */ +#define FLEXIO0_D4_PIO0_12 N9X_MUX('0',12,6) /* PT0_12 */ +#define PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define ADC0_B13_PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define FC1_P5_PIO0_13 N9X_MUX('0',13,2) /* PT0_13 */ +#define FC0_P1_PIO0_13 N9X_MUX('0',13,3) /* PT0_13 */ +#define CT0_MAT3_PIO0_13 N9X_MUX('0',13,4) /* PT0_13 */ +#define FLEXIO0_D5_PIO0_13 N9X_MUX('0',13,6) /* PT0_13 */ +#define PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define ADC0_B14_PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define FC1_P6_PIO0_14 N9X_MUX('0',14,2) /* PT0_14 */ +#define FC0_P2_PIO0_14 N9X_MUX('0',14,3) /* PT0_14 */ +#define CT_INP2_PIO0_14 N9X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_PIO0_14 N9X_MUX('0',14,5) /* PT0_14 */ +#define FLEXIO0_D6_PIO0_14 N9X_MUX('0',14,6) /* PT0_14 */ +#define PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define ADC0_B15_PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define FC0_P3_PIO0_15 N9X_MUX('0',15,3) /* PT0_15 */ +#define CT_INP3_PIO0_15 N9X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_PIO0_15 N9X_MUX('0',15,5) /* PT0_15 */ +#define FLEXIO0_D7_PIO0_15 N9X_MUX('0',15,6) /* PT0_15 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define CMP2_IN2_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define ADC0_B16_PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define FC1_P0_PIO0_24 N9X_MUX('0',24,2) /* PT0_24 */ +#define CT0_MAT0_PIO0_24 N9X_MUX('0',24,4) /* PT0_24 */ +#define PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define ADC0_B17_PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define FC1_P1_PIO0_25 N9X_MUX('0',25,2) /* PT0_25 */ +#define CT0_MAT1_PIO0_25 N9X_MUX('0',25,4) /* PT0_25 */ +#define PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define ADC0_B18_PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define FC1_P2_PIO0_26 N9X_MUX('0',26,2) /* PT0_26 */ +#define CT0_MAT2_PIO0_26 N9X_MUX('0',26,4) /* PT0_26 */ +#define PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define ADC0_B19_PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define FC1_P3_PIO0_27 N9X_MUX('0',27,2) /* PT0_27 */ +#define CT0_MAT3_PIO0_27 N9X_MUX('0',27,4) /* PT0_27 */ +#define PIO0_28 N9X_MUX('0',28,0) /* PT0_28 */ +#define ADC0_B20_PIO0_28 N9X_MUX('0',28,0) /* PT0_28 */ +#define FC1_P4_PIO0_28 N9X_MUX('0',28,2) /* PT0_28 */ +#define FC0_P4_PIO0_28 N9X_MUX('0',28,3) /* PT0_28 */ +#define CT_INP0_PIO0_28 N9X_MUX('0',28,4) /* PT0_28 */ +#define PIO0_29 N9X_MUX('0',29,0) /* PT0_29 */ +#define ADC0_B21_PIO0_29 N9X_MUX('0',29,0) /* PT0_29 */ +#define FC1_P5_PIO0_29 N9X_MUX('0',29,2) /* PT0_29 */ +#define FC0_P5_PIO0_29 N9X_MUX('0',29,3) /* PT0_29 */ +#define CT_INP1_PIO0_29 N9X_MUX('0',29,4) /* PT0_29 */ +#define PIO0_30 N9X_MUX('0',30,0) /* PT0_30 */ +#define ADC0_B22_PIO0_30 N9X_MUX('0',30,0) /* PT0_30 */ +#define FC1_P6_PIO0_30 N9X_MUX('0',30,2) /* PT0_30 */ +#define FC0_P6_PIO0_30 N9X_MUX('0',30,3) /* PT0_30 */ +#define CT_INP2_PIO0_30 N9X_MUX('0',30,4) /* PT0_30 */ +#define PIO0_31 N9X_MUX('0',31,0) /* PT0_31 */ +#define ADC0_B23_PIO0_31 N9X_MUX('0',31,0) /* PT0_31 */ +#define CT_INP3_PIO0_31 N9X_MUX('0',31,4) /* PT0_31 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define SCT0_OUT6_PIO1_0 N9X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define SCT0_OUT7_PIO1_1 N9X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define CMP2_IN0_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define SCT0_IN6_PIO1_2 N9X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define ENET0_MDC_PIO1_2 N9X_MUX('1',2,9) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define SCT0_IN7_PIO1_3 N9X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define ENET0_MDIO_PIO1_3 N9X_MUX('1',3,9) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define SCT0_OUT0_PIO1_4 N9X_MUX('1',4,5) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define ENET0_TX_CLK_PIO1_4 N9X_MUX('1',4,9) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define SCT0_OUT1_PIO1_5 N9X_MUX('1',5,5) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define ENET0_TXEN_PIO1_5 N9X_MUX('1',5,9) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define SCT0_IN0_PIO1_6 N9X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define ENET0_TXD0_PIO1_6 N9X_MUX('1',6,9) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define CAN1_TXD_PIO1_6 N9X_MUX('1',6,11) /* PT1_6 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define SCT0_IN1_PIO1_7 N9X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define PLU_CLK_PIO1_7 N9X_MUX('1',7,8) /* PT1_7 */ +#define ENET0_TXD1_PIO1_7 N9X_MUX('1',7,9) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define CAN1_RXD_PIO1_7 N9X_MUX('1',7,11) /* PT1_7 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define SCT0_OUT2_PIO1_8 N9X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define PLU_OUT0_PIO1_8 N9X_MUX('1',8,8) /* PT1_8 */ +#define ENET0_TXD2_PIO1_8 N9X_MUX('1',8,9) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define SCT0_OUT3_PIO1_9 N9X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define PLU_OUT1_PIO1_9 N9X_MUX('1',9,8) /* PT1_9 */ +#define ENET0_TXD3_PIO1_9 N9X_MUX('1',9,9) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define SCT0_IN2_PIO1_10 N9X_MUX('1',10,5) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define PLU_IN0_PIO1_10 N9X_MUX('1',10,8) /* PT1_10 */ +#define ENET0_TXER_PIO1_10 N9X_MUX('1',10,9) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define SCT0_IN3_PIO1_11 N9X_MUX('1',11,5) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define PLU_IN1_PIO1_11 N9X_MUX('1',11,8) /* PT1_11 */ +#define ENET0_RX_CLK_PIO1_11 N9X_MUX('1',11,9) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define SCT0_OUT4_PIO1_12 N9X_MUX('1',12,5) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define PLU_OUT2_PIO1_12 N9X_MUX('1',12,8) /* PT1_12 */ +#define ENET0_RXER_PIO1_12 N9X_MUX('1',12,9) /* PT1_12 */ +#define CAN1_RXD_PIO1_12 N9X_MUX('1',12,11) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define SCT0_OUT5_PIO1_13 N9X_MUX('1',13,5) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define PLU_OUT3_PIO1_13 N9X_MUX('1',13,8) /* PT1_13 */ +#define ENET0_RXDV_PIO1_13 N9X_MUX('1',13,9) /* PT1_13 */ +#define CAN1_TXD_PIO1_13 N9X_MUX('1',13,11) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define SCT0_IN4_PIO1_14 N9X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PLU_IN2_PIO1_14 N9X_MUX('1',14,8) /* PT1_14 */ +#define ENET0_RXD0_PIO1_14 N9X_MUX('1',14,9) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define SCT0_IN5_PIO1_15 N9X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define PLU_IN3_PIO1_15 N9X_MUX('1',15,8) /* PT1_15 */ +#define ENET0_RXD1_PIO1_15 N9X_MUX('1',15,9) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define ADC1_A16_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define WUU0_IN14_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define FC5_P0_PIO1_16 N9X_MUX('1',16,2) /* PT1_16 */ +#define FC3_P4_PIO1_16 N9X_MUX('1',16,3) /* PT1_16 */ +#define CT_INP12_PIO1_16 N9X_MUX('1',16,4) /* PT1_16 */ +#define SCT0_OUT6_PIO1_16 N9X_MUX('1',16,5) /* PT1_16 */ +#define FLEXIO0_D24_PIO1_16 N9X_MUX('1',16,6) /* PT1_16 */ +#define EZH_PIO12_PIO1_16 N9X_MUX('1',16,7) /* PT1_16 */ +#define PLU_OUT4_PIO1_16 N9X_MUX('1',16,8) /* PT1_16 */ +#define ENET0_RXD2_PIO1_16 N9X_MUX('1',16,9) /* PT1_16 */ +#define I3C1_SDA_PIO1_16 N9X_MUX('1',16,10) /* PT1_16 */ +#define PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define ADC1_A17_PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define FC5_P1_PIO1_17 N9X_MUX('1',17,2) /* PT1_17 */ +#define FC3_P5_PIO1_17 N9X_MUX('1',17,3) /* PT1_17 */ +#define CT_INP13_PIO1_17 N9X_MUX('1',17,4) /* PT1_17 */ +#define SCT0_OUT7_PIO1_17 N9X_MUX('1',17,5) /* PT1_17 */ +#define FLEXIO0_D25_PIO1_17 N9X_MUX('1',17,6) /* PT1_17 */ +#define EZH_PIO13_PIO1_17 N9X_MUX('1',17,7) /* PT1_17 */ +#define PLU_OUT5_PIO1_17 N9X_MUX('1',17,8) /* PT1_17 */ +#define ENET0_RXD3_PIO1_17 N9X_MUX('1',17,9) /* PT1_17 */ +#define I3C1_SCL_PIO1_17 N9X_MUX('1',17,10) /* PT1_17 */ +#define PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define ADC1_A18_PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define FREQME_CLK_IN0_PIO1_18 N9X_MUX('1',18,1) /* PT1_18 */ +#define FC5_P2_PIO1_18 N9X_MUX('1',18,2) /* PT1_18 */ +#define FC3_P6_PIO1_18 N9X_MUX('1',18,3) /* PT1_18 */ +#define CT3_MAT0_PIO1_18 N9X_MUX('1',18,4) /* PT1_18 */ +#define SCT0_IN6_PIO1_18 N9X_MUX('1',18,5) /* PT1_18 */ +#define FLEXIO0_D26_PIO1_18 N9X_MUX('1',18,6) /* PT1_18 */ +#define EZH_PIO14_PIO1_18 N9X_MUX('1',18,7) /* PT1_18 */ +#define PLU_IN4_PIO1_18 N9X_MUX('1',18,8) /* PT1_18 */ +#define ENET0_COL_PIO1_18 N9X_MUX('1',18,9) /* PT1_18 */ +#define CAN0_TXD_PIO1_18 N9X_MUX('1',18,11) /* PT1_18 */ +#define PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define ADC1_A19_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define WUU0_IN15_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define FREQME_CLK_IN1_PIO1_19 N9X_MUX('1',19,1) /* PT1_19 */ +#define FC5_P3_PIO1_19 N9X_MUX('1',19,2) /* PT1_19 */ +#define CT3_MAT1_PIO1_19 N9X_MUX('1',19,4) /* PT1_19 */ +#define SCT0_IN7_PIO1_19 N9X_MUX('1',19,5) /* PT1_19 */ +#define FLEXIO0_D27_PIO1_19 N9X_MUX('1',19,6) /* PT1_19 */ +#define EZH_PIO15_PIO1_19 N9X_MUX('1',19,7) /* PT1_19 */ +#define PLU_IN5_PIO1_19 N9X_MUX('1',19,8) /* PT1_19 */ +#define ENET0_CRS_PIO1_19 N9X_MUX('1',19,9) /* PT1_19 */ +#define CAN0_RXD_PIO1_19 N9X_MUX('1',19,11) /* PT1_19 */ +#define PIO1_20 N9X_MUX('1',20,0) /* PT1_20 */ +#define ADC1_A20_PIO1_20 N9X_MUX('1',20,0) /* PT1_20 */ +#define CMP1_IN3_PIO1_20 N9X_MUX('1',20,0) /* PT1_20 */ +#define TRIG_IN2_PIO1_20 N9X_MUX('1',20,1) /* PT1_20 */ +#define FC5_P4_PIO1_20 N9X_MUX('1',20,2) /* PT1_20 */ +#define FC4_P0_PIO1_20 N9X_MUX('1',20,3) /* PT1_20 */ +#define CT3_MAT2_PIO1_20 N9X_MUX('1',20,4) /* PT1_20 */ +#define SCT0_OUT8_PIO1_20 N9X_MUX('1',20,5) /* PT1_20 */ +#define FLEXIO0_D28_PIO1_20 N9X_MUX('1',20,6) /* PT1_20 */ +#define EZH_PIO16_PIO1_20 N9X_MUX('1',20,7) /* PT1_20 */ +#define PLU_OUT6_PIO1_20 N9X_MUX('1',20,8) /* PT1_20 */ +#define ENET0_MDC_PIO1_20 N9X_MUX('1',20,9) /* PT1_20 */ +#define CAN1_TXD_PIO1_20 N9X_MUX('1',20,11) /* PT1_20 */ +#define PIO1_21 N9X_MUX('1',21,0) /* PT1_21 */ +#define CMP2_IN3_PIO1_21 N9X_MUX('1',21,0) /* PT1_21 */ +#define ADC1_A21_PIO1_21 N9X_MUX('1',21,0) /* PT1_21 */ +#define TRIG_OUT2_PIO1_21 N9X_MUX('1',21,1) /* PT1_21 */ +#define FC5_P5_PIO1_21 N9X_MUX('1',21,2) /* PT1_21 */ +#define FC4_P1_PIO1_21 N9X_MUX('1',21,3) /* PT1_21 */ +#define CT3_MAT3_PIO1_21 N9X_MUX('1',21,4) /* PT1_21 */ +#define SCT0_OUT9_PIO1_21 N9X_MUX('1',21,5) /* PT1_21 */ +#define FLEXIO0_D29_PIO1_21 N9X_MUX('1',21,6) /* PT1_21 */ +#define EZH_PIO17_PIO1_21 N9X_MUX('1',21,7) /* PT1_21 */ +#define PLU_OUT7_PIO1_21 N9X_MUX('1',21,8) /* PT1_21 */ +#define ENET0_MDIO_PIO1_21 N9X_MUX('1',21,9) /* PT1_21 */ +#define SAI1_MCLK_PIO1_21 N9X_MUX('1',21,10) /* PT1_21 */ +#define CAN1_RXD_PIO1_21 N9X_MUX('1',21,11) /* PT1_21 */ +#define PIO1_22 N9X_MUX('1',22,0) /* PT1_22 */ +#define ADC1_A22_PIO1_22 N9X_MUX('1',22,0) /* PT1_22 */ +#define TRIG_IN3_PIO1_22 N9X_MUX('1',22,1) /* PT1_22 */ +#define FC5_P6_PIO1_22 N9X_MUX('1',22,2) /* PT1_22 */ +#define FC4_P2_PIO1_22 N9X_MUX('1',22,3) /* PT1_22 */ +#define CT_INP14_PIO1_22 N9X_MUX('1',22,4) /* PT1_22 */ +#define SCT0_OUT4_PIO1_22 N9X_MUX('1',22,5) /* PT1_22 */ +#define FLEXIO0_D30_PIO1_22 N9X_MUX('1',22,6) /* PT1_22 */ +#define EZH_PIO18_PIO1_22 N9X_MUX('1',22,7) /* PT1_22 */ +#define PIO1_23 N9X_MUX('1',23,0) /* PT1_23 */ +#define ADC1_A23_PIO1_23 N9X_MUX('1',23,0) /* PT1_23 */ +#define FC4_P3_PIO1_23 N9X_MUX('1',23,3) /* PT1_23 */ +#define CT_INP15_PIO1_23 N9X_MUX('1',23,4) /* PT1_23 */ +#define SCT0_OUT5_PIO1_23 N9X_MUX('1',23,5) /* PT1_23 */ +#define FLEXIO0_D31_PIO1_23 N9X_MUX('1',23,6) /* PT1_23 */ +#define EZH_PIO19_PIO1_23 N9X_MUX('1',23,7) /* PT1_23 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SCT0_OUT8_PIO1_30 N9X_MUX('1',30,5) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define SCT0_OUT9_PIO1_31 N9X_MUX('1',31,5) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define FC9_P6_PIO2_0 N9X_MUX('2',0,2) /* PT2_0 */ +#define SCT0_IN0_PIO2_0 N9X_MUX('2',0,4) /* PT2_0 */ +#define PWM1_A3_PIO2_0 N9X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define FLEXSPI0_B_SS1_b_PIO2_0 N9X_MUX('2',0,8) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define SCT0_IN1_PIO2_1 N9X_MUX('2',1,4) /* PT2_1 */ +#define PWM1_B3_PIO2_1 N9X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define FLEXSPI0_B_DQS_PIO2_1 N9X_MUX('2',1,8) /* PT2_1 */ +#define SINC0_MCLK_OUT0_PIO2_1 N9X_MUX('2',1,9) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define FC9_P3_PIO2_2 N9X_MUX('2',2,2) /* PT2_2 */ +#define SCT0_OUT0_PIO2_2 N9X_MUX('2',2,4) /* PT2_2 */ +#define PWM1_A2_PIO2_2 N9X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define FLEXSPI0_B_SS0_b_PIO2_2 N9X_MUX('2',2,8) /* PT2_2 */ +#define SINC0_MCLK0_PIO2_2 N9X_MUX('2',2,9) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define FC9_P1_PIO2_3 N9X_MUX('2',3,2) /* PT2_3 */ +#define SCT0_OUT1_PIO2_3 N9X_MUX('2',3,4) /* PT2_3 */ +#define PWM1_B2_PIO2_3 N9X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define FLEXSPI0_B_SCLK_PIO2_3 N9X_MUX('2',3,8) /* PT2_3 */ +#define SINC0_MBIT0_PIO2_3 N9X_MUX('2',3,9) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define FC9_P0_PIO2_4 N9X_MUX('2',4,2) /* PT2_4 */ +#define SCT0_OUT2_PIO2_4 N9X_MUX('2',4,4) /* PT2_4 */ +#define PWM1_A1_PIO2_4 N9X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define FLEXSPI0_B_DATA0_PIO2_4 N9X_MUX('2',4,8) /* PT2_4 */ +#define SINC0_MCLK1_PIO2_4 N9X_MUX('2',4,9) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define FC9_P2_PIO2_5 N9X_MUX('2',5,2) /* PT2_5 */ +#define SCT0_OUT3_PIO2_5 N9X_MUX('2',5,4) /* PT2_5 */ +#define PWM1_B1_PIO2_5 N9X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define FLEXSPI0_B_DATA1_PIO2_5 N9X_MUX('2',5,8) /* PT2_5 */ +#define SINC0_MBIT1_PIO2_5 N9X_MUX('2',5,9) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define FC9_P4_PIO2_6 N9X_MUX('2',6,2) /* PT2_6 */ +#define SCT0_OUT4_PIO2_6 N9X_MUX('2',6,4) /* PT2_6 */ +#define PWM1_A0_PIO2_6 N9X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define FLEXSPI0_B_DATA2_PIO2_6 N9X_MUX('2',6,8) /* PT2_6 */ +#define SINC0_MCLK2_PIO2_6 N9X_MUX('2',6,9) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define FC9_P5_PIO2_7 N9X_MUX('2',7,2) /* PT2_7 */ +#define SCT0_OUT5_PIO2_7 N9X_MUX('2',7,4) /* PT2_7 */ +#define PWM1_B0_PIO2_7 N9X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define FLEXSPI0_B_DATA3_PIO2_7 N9X_MUX('2',7,8) /* PT2_7 */ +#define SINC0_MBIT2_PIO2_7 N9X_MUX('2',7,9) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO2_8 N9X_MUX('2',8,0) /* PT2_8 */ +#define TRACE_DATA0_PIO2_8 N9X_MUX('2',8,1) /* PT2_8 */ +#define SCT0_IN2_PIO2_8 N9X_MUX('2',8,4) /* PT2_8 */ +#define PWM1_X0_PIO2_8 N9X_MUX('2',8,5) /* PT2_8 */ +#define FLEXIO0_D16_PIO2_8 N9X_MUX('2',8,6) /* PT2_8 */ +#define EZH_PIO28_PIO2_8 N9X_MUX('2',8,7) /* PT2_8 */ +#define FLEXSPI0_B_DATA4_PIO2_8 N9X_MUX('2',8,8) /* PT2_8 */ +#define SINC0_MCLK3_PIO2_8 N9X_MUX('2',8,9) /* PT2_8 */ +#define SAI1_TXD0_PIO2_8 N9X_MUX('2',8,10) /* PT2_8 */ +#define PIO2_9 N9X_MUX('2',9,0) /* PT2_9 */ +#define TRACE_DATA1_PIO2_9 N9X_MUX('2',9,1) /* PT2_9 */ +#define SCT0_IN3_PIO2_9 N9X_MUX('2',9,4) /* PT2_9 */ +#define PWM1_X1_PIO2_9 N9X_MUX('2',9,5) /* PT2_9 */ +#define FLEXIO0_D17_PIO2_9 N9X_MUX('2',9,6) /* PT2_9 */ +#define EZH_PIO29_PIO2_9 N9X_MUX('2',9,7) /* PT2_9 */ +#define FLEXSPI0_B_DATA5_PIO2_9 N9X_MUX('2',9,8) /* PT2_9 */ +#define SINC0_MBIT3_PIO2_9 N9X_MUX('2',9,9) /* PT2_9 */ +#define SAI1_RXD0_PIO2_9 N9X_MUX('2',9,10) /* PT2_9 */ +#define PIO2_10 N9X_MUX('2',10,0) /* PT2_10 */ +#define TRACE_DATA2_PIO2_10 N9X_MUX('2',10,1) /* PT2_10 */ +#define SCT0_IN4_PIO2_10 N9X_MUX('2',10,4) /* PT2_10 */ +#define PWM1_X2_PIO2_10 N9X_MUX('2',10,5) /* PT2_10 */ +#define FLEXIO0_D18_PIO2_10 N9X_MUX('2',10,6) /* PT2_10 */ +#define EZH_PIO31_PIO2_10 N9X_MUX('2',10,7) /* PT2_10 */ +#define FLEXSPI0_B_DATA6_PIO2_10 N9X_MUX('2',10,8) /* PT2_10 */ +#define SINC0_MCLK4_PIO2_10 N9X_MUX('2',10,9) /* PT2_10 */ +#define SAI1_RXD1_PIO2_10 N9X_MUX('2',10,10) /* PT2_10 */ +#define PIO2_11 N9X_MUX('2',11,0) /* PT2_11 */ +#define TRACE_DATA3_PIO2_11 N9X_MUX('2',11,1) /* PT2_11 */ +#define SCT0_IN5_PIO2_11 N9X_MUX('2',11,4) /* PT2_11 */ +#define PWM1_X3_PIO2_11 N9X_MUX('2',11,5) /* PT2_11 */ +#define FLEXIO0_D19_PIO2_11 N9X_MUX('2',11,6) /* PT2_11 */ +#define EZH_PIO30_PIO2_11 N9X_MUX('2',11,7) /* PT2_11 */ +#define FLEXSPI0_B_DATA7_PIO2_11 N9X_MUX('2',11,8) /* PT2_11 */ +#define SINC0_MBIT4_PIO2_11 N9X_MUX('2',11,9) /* PT2_11 */ +#define SAI1_TXD1_PIO2_11 N9X_MUX('2',11,10) /* PT2_11 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define FLEXSPI0_A_SS0_b_PIO3_0 N9X_MUX('3',0,8) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FLEXSPI0_A_SS1_b_PIO3_1 N9X_MUX('3',1,8) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_2 N9X_MUX('3',2,0) /* PT3_2 */ +#define FC7_P0_PIO3_2 N9X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_PIO3_2 N9X_MUX('3',2,4) /* PT3_2 */ +#define PWM0_X0_PIO3_2 N9X_MUX('3',2,5) /* PT3_2 */ +#define FLEXIO0_D10_PIO3_2 N9X_MUX('3',2,6) /* PT3_2 */ +#define EZH_PIO2_PIO3_2 N9X_MUX('3',2,7) /* PT3_2 */ +#define PIO3_3 N9X_MUX('3',3,0) /* PT3_3 */ +#define FC7_P1_PIO3_3 N9X_MUX('3',3,2) /* PT3_3 */ +#define CT4_MAT1_PIO3_3 N9X_MUX('3',3,4) /* PT3_3 */ +#define PWM0_X1_PIO3_3 N9X_MUX('3',3,5) /* PT3_3 */ +#define FLEXIO0_D11_PIO3_3 N9X_MUX('3',3,6) /* PT3_3 */ +#define EZH_PIO3_PIO3_3 N9X_MUX('3',3,7) /* PT3_3 */ +#define PIO3_4 N9X_MUX('3',4,0) /* PT3_4 */ +#define FC7_P2_PIO3_4 N9X_MUX('3',4,2) /* PT3_4 */ +#define CT_INP18_PIO3_4 N9X_MUX('3',4,4) /* PT3_4 */ +#define PWM0_X2_PIO3_4 N9X_MUX('3',4,5) /* PT3_4 */ +#define FLEXIO0_D12_PIO3_4 N9X_MUX('3',4,6) /* PT3_4 */ +#define EZH_PIO4_PIO3_4 N9X_MUX('3',4,7) /* PT3_4 */ +#define PIO3_5 N9X_MUX('3',5,0) /* PT3_5 */ +#define FC7_P3_PIO3_5 N9X_MUX('3',5,2) /* PT3_5 */ +#define CT_INP19_PIO3_5 N9X_MUX('3',5,4) /* PT3_5 */ +#define PWM0_X3_PIO3_5 N9X_MUX('3',5,5) /* PT3_5 */ +#define FLEXIO0_D13_PIO3_5 N9X_MUX('3',5,6) /* PT3_5 */ +#define EZH_PIO5_PIO3_5 N9X_MUX('3',5,7) /* PT3_5 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define FLEXSPI0_A_DQS_PIO3_6 N9X_MUX('3',6,8) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define FLEXSPI0_A_SCLK_PIO3_7 N9X_MUX('3',7,8) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define FLEXSPI0_A_DATA0_PIO3_8 N9X_MUX('3',8,8) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define FLEXSPI0_A_DATA1_PIO3_9 N9X_MUX('3',9,8) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define FLEXSPI0_A_DATA2_PIO3_10 N9X_MUX('3',10,8) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define FLEXSPI0_A_DATA3_PIO3_11 N9X_MUX('3',11,8) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define PWM1_A0_PIO3_12 N9X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define FLEXSPI0_A_DATA4_PIO3_12 N9X_MUX('3',12,8) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define PWM1_B0_PIO3_13 N9X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define FLEXSPI0_A_DATA5_PIO3_13 N9X_MUX('3',13,8) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define FC8_P0_PIO3_14 N9X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define PWM1_A1_PIO3_14 N9X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define FLEXSPI0_A_DATA6_PIO3_14 N9X_MUX('3',14,8) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define FC8_P1_PIO3_15 N9X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define PWM1_B1_PIO3_15 N9X_MUX('3',15,5) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define FLEXSPI0_A_DATA7_PIO3_15 N9X_MUX('3',15,8) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define FC8_P2_PIO3_16 N9X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define PWM1_A2_PIO3_16 N9X_MUX('3',16,5) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define FC8_P3_PIO3_17 N9X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define PWM1_B2_PIO3_17 N9X_MUX('3',17,5) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define PIO3_18 N9X_MUX('3',18,0) /* PT3_18 */ +#define FC6_P6_PIO3_18 N9X_MUX('3',18,3) /* PT3_18 */ +#define CT2_MAT0_PIO3_18 N9X_MUX('3',18,4) /* PT3_18 */ +#define PWM1_X0_PIO3_18 N9X_MUX('3',18,5) /* PT3_18 */ +#define FLEXIO0_D26_PIO3_18 N9X_MUX('3',18,6) /* PT3_18 */ +#define EZH_PIO18_PIO3_18 N9X_MUX('3',18,7) /* PT3_18 */ +#define SAI1_RX_BCLK_PIO3_18 N9X_MUX('3',18,10) /* PT3_18 */ +#define PIO3_19 N9X_MUX('3',19,0) /* PT3_19 */ +#define FC7_P6_PIO3_19 N9X_MUX('3',19,2) /* PT3_19 */ +#define CT2_MAT1_PIO3_19 N9X_MUX('3',19,4) /* PT3_19 */ +#define PWM1_X1_PIO3_19 N9X_MUX('3',19,5) /* PT3_19 */ +#define FLEXIO0_D27_PIO3_19 N9X_MUX('3',19,6) /* PT3_19 */ +#define EZH_PIO19_PIO3_19 N9X_MUX('3',19,7) /* PT3_19 */ +#define SAI1_RX_FS_PIO3_19 N9X_MUX('3',19,10) /* PT3_19 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC8_P4_PIO3_20 N9X_MUX('3',20,2) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define PWM1_A3_PIO3_20 N9X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC8_P5_PIO3_21 N9X_MUX('3',21,2) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define PWM1_B3_PIO3_21 N9X_MUX('3',21,5) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO3_22 N9X_MUX('3',22,0) /* PT3_22 */ +#define FC8_P6_PIO3_22 N9X_MUX('3',22,2) /* PT3_22 */ +#define FC6_P2_PIO3_22 N9X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_PIO3_22 N9X_MUX('3',22,4) /* PT3_22 */ +#define PWM1_X2_PIO3_22 N9X_MUX('3',22,5) /* PT3_22 */ +#define FLEXIO0_D30_PIO3_22 N9X_MUX('3',22,6) /* PT3_22 */ +#define EZH_PIO22_PIO3_22 N9X_MUX('3',22,7) /* PT3_22 */ +#define SAI1_RXD1_PIO3_22 N9X_MUX('3',22,10) /* PT3_22 */ +#define PIO3_23 N9X_MUX('3',23,0) /* PT3_23 */ +#define FC6_P3_PIO3_23 N9X_MUX('3',23,3) /* PT3_23 */ +#define CT_INP11_PIO3_23 N9X_MUX('3',23,4) /* PT3_23 */ +#define PWM1_X3_PIO3_23 N9X_MUX('3',23,5) /* PT3_23 */ +#define FLEXIO0_D31_PIO3_23 N9X_MUX('3',23,6) /* PT3_23 */ +#define EZH_PIO23_PIO3_23 N9X_MUX('3',23,7) /* PT3_23 */ +#define SAI1_TXD1_PIO3_23 N9X_MUX('3',23,10) /* PT3_23 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PLU_IN0_PIO4_0 N9X_MUX('4',0,8) /* PT4_0 */ +#define SINC0_MCLK3_PIO4_0 N9X_MUX('4',0,9) /* PT4_0 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define PLU_IN1_PIO4_1 N9X_MUX('4',1,8) /* PT4_1 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP2_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define DAC0_OUT_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define PLU_IN2_PIO4_2 N9X_MUX('4',2,8) /* PT4_2 */ +#define SINC0_MBIT3_PIO4_2 N9X_MUX('4',2,9) /* PT4_2 */ +#define DAC1_OUT_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP2_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PLU_IN3_PIO4_3 N9X_MUX('4',3,8) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define PLU_IN4_PIO4_4 N9X_MUX('4',4,8) /* PT4_4 */ +#define SINC0_MCLK4_PIO4_4 N9X_MUX('4',4,9) /* PT4_4 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PLU_IN5_PIO4_5 N9X_MUX('4',5,8) /* PT4_5 */ +#define SINC0_MBIT4_PIO4_5 N9X_MUX('4',5,9) /* PT4_5 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PLU_CLK_PIO4_6 N9X_MUX('4',6,8) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define OPAMP0_INP0_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define USB0_VBUS_DET_PIO4_12 N9X_MUX('4',12,1) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define PLU_OUT0_PIO4_12 N9X_MUX('4',12,8) /* PT4_12 */ +#define SINC0_MCLK0_PIO4_12 N9X_MUX('4',12,9) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define OPAMP0_INP1_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define PLU_OUT1_PIO4_13 N9X_MUX('4',13,8) /* PT4_13 */ +#define SINC0_MBIT0_PIO4_13 N9X_MUX('4',13,9) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_14 N9X_MUX('4',14,0) /* PT4_14 */ +#define CT4_MAT2_PIO4_14 N9X_MUX('4',14,4) /* PT4_14 */ +#define FLEXIO0_D22_PIO4_14 N9X_MUX('4',14,6) /* PT4_14 */ +#define PLU_OUT2_PIO4_14 N9X_MUX('4',14,8) /* PT4_14 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define OPAMP0_OUT_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define PLU_OUT3_PIO4_15 N9X_MUX('4',15,8) /* PT4_15 */ +#define SINC0_MCLK_OUT0_PIO4_15 N9X_MUX('4',15,9) /* PT4_15 */ +#define CAN1_RXD_PIO4_15 N9X_MUX('4',15,11) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define OPAMP1_INP0_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define PLU_OUT4_PIO4_16 N9X_MUX('4',16,8) /* PT4_16 */ +#define SINC0_MCLK1_PIO4_16 N9X_MUX('4',16,9) /* PT4_16 */ +#define CAN1_TXD_PIO4_16 N9X_MUX('4',16,11) /* PT4_16 */ +#define OPAMP1_INP1_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PLU_OUT5_PIO4_17 N9X_MUX('4',17,8) /* PT4_17 */ +#define SINC0_MBIT1_PIO4_17 N9X_MUX('4',17,9) /* PT4_17 */ +#define PIO4_18 N9X_MUX('4',18,0) /* PT4_18 */ +#define CT3_MAT2_PIO4_18 N9X_MUX('4',18,4) /* PT4_18 */ +#define FLEXIO0_D26_PIO4_18 N9X_MUX('4',18,6) /* PT4_18 */ +#define PLU_OUT6_PIO4_18 N9X_MUX('4',18,8) /* PT4_18 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define OPAMP1_OUT_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define PLU_OUT7_PIO4_19 N9X_MUX('4',19,8) /* PT4_19 */ +#define SINC0_MCLK_OUT1_PIO4_19 N9X_MUX('4',19,9) /* PT4_19 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define OPAMP2_INP0_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define SINC0_MCLK2_PIO4_20 N9X_MUX('4',20,9) /* PT4_20 */ +#define OPAMP2_INP1_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define SINC0_MBIT2_PIO4_21 N9X_MUX('4',21,9) /* PT4_21 */ +#define PIO4_22 N9X_MUX('4',22,0) /* PT4_22 */ +#define CT2_MAT2_PIO4_22 N9X_MUX('4',22,4) /* PT4_22 */ +#define FLEXIO0_D30_PIO4_22 N9X_MUX('4',22,6) /* PT4_22 */ +#define CMP2_IN4P_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define OPAMP2_OUT_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define SINC0_MCLK_OUT2_PIO4_23 N9X_MUX('4',23,9) /* PT4_23 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#define PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define ADC1_B12_PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define TRIG_OUT7_PIO5_4 N9X_MUX('5',4,1) /* PT5_4 */ +#define SPC_LPREQ_PIO5_4 N9X_MUX('5',4,2) /* PT5_4 */ +#define TAMPER2_PIO5_4 N9X_MUX('5',4,3) /* PT5_4 */ +#define PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define ADC1_B13_PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define TRIG_IN10_PIO5_5 N9X_MUX('5',5,1) /* PT5_5 */ +#define LPTMR0_ALT2_PIO5_5 N9X_MUX('5',5,2) /* PT5_5 */ +#define TAMPER3_PIO5_5 N9X_MUX('5',5,3) /* PT5_5 */ +#define ADC1_B14_PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define TRIG_OUT6_PIO5_6 N9X_MUX('5',6,1) /* PT5_6 */ +#define LPTMR1_ALT2_PIO5_6 N9X_MUX('5',6,2) /* PT5_6 */ +#define TAMPER4_PIO5_6 N9X_MUX('5',6,3) /* PT5_6 */ +#define PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define ADC1_B15_PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define TRIG_IN11_PIO5_7 N9X_MUX('5',7,1) /* PT5_7 */ +#define TAMPER5_PIO5_7 N9X_MUX('5',7,3) /* PT5_7 */ +#define PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define ADC1_B16_PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define TRIG_OUT7_PIO5_8 N9X_MUX('5',8,1) /* PT5_8 */ +#define TAMPER6_PIO5_8 N9X_MUX('5',8,3) /* PT5_8 */ +#define PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define ADC1_B17_PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define TAMPER7_PIO5_9 N9X_MUX('5',9,3) /* PT5_9 */ +#endif diff --git a/dts/nxp/mcx/MCXN946VNL-pinctrl.h b/dts/nxp/mcx/MCXN946VNL-pinctrl.h new file mode 100644 index 000000000..c0c3626a2 --- /dev/null +++ b/dts/nxp/mcx/MCXN946VNL-pinctrl.h @@ -0,0 +1,731 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN946VNL/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN946VNL_ +#define _ZEPHYR_DTS_BINDING_MCXN946VNL_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define HSCMP2_OUT_PIO0_6 N9X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define CMP2_IN2_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define SCT0_OUT6_PIO1_0 N9X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define SCT0_OUT7_PIO1_1 N9X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define CMP2_IN0_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define SCT0_IN6_PIO1_2 N9X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define ENET0_MDC_PIO1_2 N9X_MUX('1',2,9) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define SCT0_IN7_PIO1_3 N9X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define ENET0_MDIO_PIO1_3 N9X_MUX('1',3,9) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define SCT0_OUT0_PIO1_4 N9X_MUX('1',4,5) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define ENET0_TX_CLK_PIO1_4 N9X_MUX('1',4,9) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define SCT0_OUT1_PIO1_5 N9X_MUX('1',5,5) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define ENET0_TXEN_PIO1_5 N9X_MUX('1',5,9) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define SCT0_IN0_PIO1_6 N9X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define ENET0_TXD0_PIO1_6 N9X_MUX('1',6,9) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define CAN1_TXD_PIO1_6 N9X_MUX('1',6,11) /* PT1_6 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define SCT0_IN1_PIO1_7 N9X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define PLU_CLK_PIO1_7 N9X_MUX('1',7,8) /* PT1_7 */ +#define ENET0_TXD1_PIO1_7 N9X_MUX('1',7,9) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define CAN1_RXD_PIO1_7 N9X_MUX('1',7,11) /* PT1_7 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define SCT0_OUT2_PIO1_8 N9X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define PLU_OUT0_PIO1_8 N9X_MUX('1',8,8) /* PT1_8 */ +#define ENET0_TXD2_PIO1_8 N9X_MUX('1',8,9) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define SCT0_OUT3_PIO1_9 N9X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define PLU_OUT1_PIO1_9 N9X_MUX('1',9,8) /* PT1_9 */ +#define ENET0_TXD3_PIO1_9 N9X_MUX('1',9,9) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define SCT0_IN2_PIO1_10 N9X_MUX('1',10,5) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define PLU_IN0_PIO1_10 N9X_MUX('1',10,8) /* PT1_10 */ +#define ENET0_TXER_PIO1_10 N9X_MUX('1',10,9) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define SCT0_IN3_PIO1_11 N9X_MUX('1',11,5) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define PLU_IN1_PIO1_11 N9X_MUX('1',11,8) /* PT1_11 */ +#define ENET0_RX_CLK_PIO1_11 N9X_MUX('1',11,9) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define SCT0_OUT4_PIO1_12 N9X_MUX('1',12,5) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define PLU_OUT2_PIO1_12 N9X_MUX('1',12,8) /* PT1_12 */ +#define ENET0_RXER_PIO1_12 N9X_MUX('1',12,9) /* PT1_12 */ +#define CAN1_RXD_PIO1_12 N9X_MUX('1',12,11) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define SCT0_OUT5_PIO1_13 N9X_MUX('1',13,5) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define PLU_OUT3_PIO1_13 N9X_MUX('1',13,8) /* PT1_13 */ +#define ENET0_RXDV_PIO1_13 N9X_MUX('1',13,9) /* PT1_13 */ +#define CAN1_TXD_PIO1_13 N9X_MUX('1',13,11) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define SCT0_IN4_PIO1_14 N9X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PLU_IN2_PIO1_14 N9X_MUX('1',14,8) /* PT1_14 */ +#define ENET0_RXD0_PIO1_14 N9X_MUX('1',14,9) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define SCT0_IN5_PIO1_15 N9X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define PLU_IN3_PIO1_15 N9X_MUX('1',15,8) /* PT1_15 */ +#define ENET0_RXD1_PIO1_15 N9X_MUX('1',15,9) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SCT0_OUT8_PIO1_30 N9X_MUX('1',30,5) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define SCT0_OUT9_PIO1_31 N9X_MUX('1',31,5) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define FC9_P6_PIO2_0 N9X_MUX('2',0,2) /* PT2_0 */ +#define SCT0_IN0_PIO2_0 N9X_MUX('2',0,4) /* PT2_0 */ +#define PWM1_A3_PIO2_0 N9X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define FLEXSPI0_B_SS1_b_PIO2_0 N9X_MUX('2',0,8) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define SCT0_IN1_PIO2_1 N9X_MUX('2',1,4) /* PT2_1 */ +#define PWM1_B3_PIO2_1 N9X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define FLEXSPI0_B_DQS_PIO2_1 N9X_MUX('2',1,8) /* PT2_1 */ +#define SINC0_MCLK_OUT0_PIO2_1 N9X_MUX('2',1,9) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define FC9_P3_PIO2_2 N9X_MUX('2',2,2) /* PT2_2 */ +#define SCT0_OUT0_PIO2_2 N9X_MUX('2',2,4) /* PT2_2 */ +#define PWM1_A2_PIO2_2 N9X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define FLEXSPI0_B_SS0_b_PIO2_2 N9X_MUX('2',2,8) /* PT2_2 */ +#define SINC0_MCLK0_PIO2_2 N9X_MUX('2',2,9) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define FC9_P1_PIO2_3 N9X_MUX('2',3,2) /* PT2_3 */ +#define SCT0_OUT1_PIO2_3 N9X_MUX('2',3,4) /* PT2_3 */ +#define PWM1_B2_PIO2_3 N9X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define FLEXSPI0_B_SCLK_PIO2_3 N9X_MUX('2',3,8) /* PT2_3 */ +#define SINC0_MBIT0_PIO2_3 N9X_MUX('2',3,9) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define FC9_P0_PIO2_4 N9X_MUX('2',4,2) /* PT2_4 */ +#define SCT0_OUT2_PIO2_4 N9X_MUX('2',4,4) /* PT2_4 */ +#define PWM1_A1_PIO2_4 N9X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define FLEXSPI0_B_DATA0_PIO2_4 N9X_MUX('2',4,8) /* PT2_4 */ +#define SINC0_MCLK1_PIO2_4 N9X_MUX('2',4,9) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define FC9_P2_PIO2_5 N9X_MUX('2',5,2) /* PT2_5 */ +#define SCT0_OUT3_PIO2_5 N9X_MUX('2',5,4) /* PT2_5 */ +#define PWM1_B1_PIO2_5 N9X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define FLEXSPI0_B_DATA1_PIO2_5 N9X_MUX('2',5,8) /* PT2_5 */ +#define SINC0_MBIT1_PIO2_5 N9X_MUX('2',5,9) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define FC9_P4_PIO2_6 N9X_MUX('2',6,2) /* PT2_6 */ +#define SCT0_OUT4_PIO2_6 N9X_MUX('2',6,4) /* PT2_6 */ +#define PWM1_A0_PIO2_6 N9X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define FLEXSPI0_B_DATA2_PIO2_6 N9X_MUX('2',6,8) /* PT2_6 */ +#define SINC0_MCLK2_PIO2_6 N9X_MUX('2',6,9) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define FC9_P5_PIO2_7 N9X_MUX('2',7,2) /* PT2_7 */ +#define SCT0_OUT5_PIO2_7 N9X_MUX('2',7,4) /* PT2_7 */ +#define PWM1_B0_PIO2_7 N9X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define FLEXSPI0_B_DATA3_PIO2_7 N9X_MUX('2',7,8) /* PT2_7 */ +#define SINC0_MBIT2_PIO2_7 N9X_MUX('2',7,9) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define FLEXSPI0_A_SS0_b_PIO3_0 N9X_MUX('3',0,8) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FLEXSPI0_A_SS1_b_PIO3_1 N9X_MUX('3',1,8) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define FLEXSPI0_A_DQS_PIO3_6 N9X_MUX('3',6,8) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define FLEXSPI0_A_SCLK_PIO3_7 N9X_MUX('3',7,8) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define FLEXSPI0_A_DATA0_PIO3_8 N9X_MUX('3',8,8) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define FLEXSPI0_A_DATA1_PIO3_9 N9X_MUX('3',9,8) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define FLEXSPI0_A_DATA2_PIO3_10 N9X_MUX('3',10,8) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define FLEXSPI0_A_DATA3_PIO3_11 N9X_MUX('3',11,8) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define PWM1_A0_PIO3_12 N9X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define FLEXSPI0_A_DATA4_PIO3_12 N9X_MUX('3',12,8) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define PWM1_B0_PIO3_13 N9X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define FLEXSPI0_A_DATA5_PIO3_13 N9X_MUX('3',13,8) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define FC8_P0_PIO3_14 N9X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define PWM1_A1_PIO3_14 N9X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define FLEXSPI0_A_DATA6_PIO3_14 N9X_MUX('3',14,8) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define FC8_P1_PIO3_15 N9X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define PWM1_B1_PIO3_15 N9X_MUX('3',15,5) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define FLEXSPI0_A_DATA7_PIO3_15 N9X_MUX('3',15,8) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define FC8_P2_PIO3_16 N9X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define PWM1_A2_PIO3_16 N9X_MUX('3',16,5) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define FC8_P3_PIO3_17 N9X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define PWM1_B2_PIO3_17 N9X_MUX('3',17,5) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC8_P4_PIO3_20 N9X_MUX('3',20,2) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define PWM1_A3_PIO3_20 N9X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC8_P5_PIO3_21 N9X_MUX('3',21,2) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define PWM1_B3_PIO3_21 N9X_MUX('3',21,5) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define ADC0_A0_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PLU_IN0_PIO4_0 N9X_MUX('4',0,8) /* PT4_0 */ +#define SINC0_MCLK3_PIO4_0 N9X_MUX('4',0,9) /* PT4_0 */ +#define ADC0_B0_PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define PLU_IN1_PIO4_1 N9X_MUX('4',1,8) /* PT4_1 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP2_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define DAC0_OUT_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define PLU_IN2_PIO4_2 N9X_MUX('4',2,8) /* PT4_2 */ +#define SINC0_MBIT3_PIO4_2 N9X_MUX('4',2,9) /* PT4_2 */ +#define DAC1_OUT_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP2_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PLU_IN3_PIO4_3 N9X_MUX('4',3,8) /* PT4_3 */ +#define ADC1_A0_PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define PLU_IN4_PIO4_4 N9X_MUX('4',4,8) /* PT4_4 */ +#define SINC0_MCLK4_PIO4_4 N9X_MUX('4',4,9) /* PT4_4 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define ADC1_B0_PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PLU_IN5_PIO4_5 N9X_MUX('4',5,8) /* PT4_5 */ +#define SINC0_MBIT4_PIO4_5 N9X_MUX('4',5,9) /* PT4_5 */ +#define DAC2_OUT_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define ADC1_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define ADC0_A3_PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PLU_CLK_PIO4_6 N9X_MUX('4',6,8) /* PT4_6 */ +#define ADC1_A7_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define VREFO_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define ADC0_A7_PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define OPAMP0_INP0_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define USB0_VBUS_DET_PIO4_12 N9X_MUX('4',12,1) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define PLU_OUT0_PIO4_12 N9X_MUX('4',12,8) /* PT4_12 */ +#define SINC0_MCLK0_PIO4_12 N9X_MUX('4',12,9) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define OPAMP0_INP1_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define OPAMP0_INN_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define PLU_OUT1_PIO4_13 N9X_MUX('4',13,8) /* PT4_13 */ +#define SINC0_MBIT0_PIO4_13 N9X_MUX('4',13,9) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define OPAMP0_OUT_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define PLU_OUT3_PIO4_15 N9X_MUX('4',15,8) /* PT4_15 */ +#define SINC0_MCLK_OUT0_PIO4_15 N9X_MUX('4',15,9) /* PT4_15 */ +#define CAN1_RXD_PIO4_15 N9X_MUX('4',15,11) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define OPAMP1_INP0_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define PLU_OUT4_PIO4_16 N9X_MUX('4',16,8) /* PT4_16 */ +#define SINC0_MCLK1_PIO4_16 N9X_MUX('4',16,9) /* PT4_16 */ +#define CAN1_TXD_PIO4_16 N9X_MUX('4',16,11) /* PT4_16 */ +#define OPAMP1_INP1_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define OPAMP1_INN_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PLU_OUT5_PIO4_17 N9X_MUX('4',17,8) /* PT4_17 */ +#define SINC0_MBIT1_PIO4_17 N9X_MUX('4',17,9) /* PT4_17 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define OPAMP1_OUT_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define PLU_OUT7_PIO4_19 N9X_MUX('4',19,8) /* PT4_19 */ +#define SINC0_MCLK_OUT1_PIO4_19 N9X_MUX('4',19,9) /* PT4_19 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define OPAMP2_INP0_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define SINC0_MCLK2_PIO4_20 N9X_MUX('4',20,9) /* PT4_20 */ +#define OPAMP2_INP1_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define OPAMP2_INN_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define SINC0_MBIT2_PIO4_21 N9X_MUX('4',21,9) /* PT4_21 */ +#define CMP2_IN4P_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define OPAMP2_OUT_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define SINC0_MCLK_OUT2_PIO4_23 N9X_MUX('4',23,9) /* PT4_23 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#endif diff --git a/dts/nxp/mcx/MCXN946VPB-pinctrl.h b/dts/nxp/mcx/MCXN946VPB-pinctrl.h new file mode 100644 index 000000000..6321998c7 --- /dev/null +++ b/dts/nxp/mcx/MCXN946VPB-pinctrl.h @@ -0,0 +1,947 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN946VPB/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN946VPB_ +#define _ZEPHYR_DTS_BINDING_MCXN946VPB_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define HSCMP2_OUT_PIO0_6 N9X_MUX('0',6,8) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define CMP2_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define WUU0_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define FC0_P3_PIO0_7 N9X_MUX('0',7,2) /* PT0_7 */ +#define CT_INP3_PIO0_7 N9X_MUX('0',7,4) /* PT0_7 */ +#define PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define ADC0_B8_PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define FC0_P4_PIO0_8 N9X_MUX('0',8,2) /* PT0_8 */ +#define CT_INP0_PIO0_8 N9X_MUX('0',8,4) /* PT0_8 */ +#define FLEXIO0_D0_PIO0_8 N9X_MUX('0',8,6) /* PT0_8 */ +#define PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define ADC0_B9_PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define FC0_P5_PIO0_9 N9X_MUX('0',9,2) /* PT0_9 */ +#define CT_INP1_PIO0_9 N9X_MUX('0',9,4) /* PT0_9 */ +#define FLEXIO0_D1_PIO0_9 N9X_MUX('0',9,6) /* PT0_9 */ +#define PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define ADC0_B10_PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define FC0_P6_PIO0_10 N9X_MUX('0',10,2) /* PT0_10 */ +#define CT0_MAT0_PIO0_10 N9X_MUX('0',10,4) /* PT0_10 */ +#define FLEXIO0_D2_PIO0_10 N9X_MUX('0',10,6) /* PT0_10 */ +#define ADC0_B11_PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define CT0_MAT1_PIO0_11 N9X_MUX('0',11,4) /* PT0_11 */ +#define FLEXIO0_D3_PIO0_11 N9X_MUX('0',11,6) /* PT0_11 */ +#define HSCMP2_OUT_PIO0_11 N9X_MUX('0',11,8) /* PT0_11 */ +#define PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define ADC0_B12_PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define FC1_P4_PIO0_12 N9X_MUX('0',12,2) /* PT0_12 */ +#define FC0_P0_PIO0_12 N9X_MUX('0',12,3) /* PT0_12 */ +#define CT0_MAT2_PIO0_12 N9X_MUX('0',12,4) /* PT0_12 */ +#define FLEXIO0_D4_PIO0_12 N9X_MUX('0',12,6) /* PT0_12 */ +#define PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define ADC0_B13_PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define FC1_P5_PIO0_13 N9X_MUX('0',13,2) /* PT0_13 */ +#define FC0_P1_PIO0_13 N9X_MUX('0',13,3) /* PT0_13 */ +#define CT0_MAT3_PIO0_13 N9X_MUX('0',13,4) /* PT0_13 */ +#define FLEXIO0_D5_PIO0_13 N9X_MUX('0',13,6) /* PT0_13 */ +#define PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define ADC0_B14_PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define FC1_P6_PIO0_14 N9X_MUX('0',14,2) /* PT0_14 */ +#define FC0_P2_PIO0_14 N9X_MUX('0',14,3) /* PT0_14 */ +#define CT_INP2_PIO0_14 N9X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_PIO0_14 N9X_MUX('0',14,5) /* PT0_14 */ +#define FLEXIO0_D6_PIO0_14 N9X_MUX('0',14,6) /* PT0_14 */ +#define PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define ADC0_B15_PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define FC0_P3_PIO0_15 N9X_MUX('0',15,3) /* PT0_15 */ +#define CT_INP3_PIO0_15 N9X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_PIO0_15 N9X_MUX('0',15,5) /* PT0_15 */ +#define FLEXIO0_D7_PIO0_15 N9X_MUX('0',15,6) /* PT0_15 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define CMP2_IN2_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define ADC0_B16_PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define FC1_P0_PIO0_24 N9X_MUX('0',24,2) /* PT0_24 */ +#define CT0_MAT0_PIO0_24 N9X_MUX('0',24,4) /* PT0_24 */ +#define PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define ADC0_B17_PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define FC1_P1_PIO0_25 N9X_MUX('0',25,2) /* PT0_25 */ +#define CT0_MAT1_PIO0_25 N9X_MUX('0',25,4) /* PT0_25 */ +#define PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define ADC0_B18_PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define FC1_P2_PIO0_26 N9X_MUX('0',26,2) /* PT0_26 */ +#define CT0_MAT2_PIO0_26 N9X_MUX('0',26,4) /* PT0_26 */ +#define PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define ADC0_B19_PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define FC1_P3_PIO0_27 N9X_MUX('0',27,2) /* PT0_27 */ +#define CT0_MAT3_PIO0_27 N9X_MUX('0',27,4) /* PT0_27 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define SCT0_OUT6_PIO1_0 N9X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define SCT0_OUT7_PIO1_1 N9X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define CMP2_IN0_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define SCT0_IN6_PIO1_2 N9X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define ENET0_MDC_PIO1_2 N9X_MUX('1',2,9) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define SCT0_IN7_PIO1_3 N9X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define ENET0_MDIO_PIO1_3 N9X_MUX('1',3,9) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define SCT0_OUT0_PIO1_4 N9X_MUX('1',4,5) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define ENET0_TX_CLK_PIO1_4 N9X_MUX('1',4,9) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define SCT0_OUT1_PIO1_5 N9X_MUX('1',5,5) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define ENET0_TXEN_PIO1_5 N9X_MUX('1',5,9) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define SCT0_IN0_PIO1_6 N9X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define ENET0_TXD0_PIO1_6 N9X_MUX('1',6,9) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define CAN1_TXD_PIO1_6 N9X_MUX('1',6,11) /* PT1_6 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define SCT0_IN1_PIO1_7 N9X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define PLU_CLK_PIO1_7 N9X_MUX('1',7,8) /* PT1_7 */ +#define ENET0_TXD1_PIO1_7 N9X_MUX('1',7,9) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define CAN1_RXD_PIO1_7 N9X_MUX('1',7,11) /* PT1_7 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define SCT0_OUT2_PIO1_8 N9X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define PLU_OUT0_PIO1_8 N9X_MUX('1',8,8) /* PT1_8 */ +#define ENET0_TXD2_PIO1_8 N9X_MUX('1',8,9) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define SCT0_OUT3_PIO1_9 N9X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define PLU_OUT1_PIO1_9 N9X_MUX('1',9,8) /* PT1_9 */ +#define ENET0_TXD3_PIO1_9 N9X_MUX('1',9,9) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define SCT0_IN2_PIO1_10 N9X_MUX('1',10,5) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define PLU_IN0_PIO1_10 N9X_MUX('1',10,8) /* PT1_10 */ +#define ENET0_TXER_PIO1_10 N9X_MUX('1',10,9) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define SCT0_IN3_PIO1_11 N9X_MUX('1',11,5) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define PLU_IN1_PIO1_11 N9X_MUX('1',11,8) /* PT1_11 */ +#define ENET0_RX_CLK_PIO1_11 N9X_MUX('1',11,9) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define SCT0_OUT4_PIO1_12 N9X_MUX('1',12,5) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define PLU_OUT2_PIO1_12 N9X_MUX('1',12,8) /* PT1_12 */ +#define ENET0_RXER_PIO1_12 N9X_MUX('1',12,9) /* PT1_12 */ +#define CAN1_RXD_PIO1_12 N9X_MUX('1',12,11) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define SCT0_OUT5_PIO1_13 N9X_MUX('1',13,5) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define PLU_OUT3_PIO1_13 N9X_MUX('1',13,8) /* PT1_13 */ +#define ENET0_RXDV_PIO1_13 N9X_MUX('1',13,9) /* PT1_13 */ +#define CAN1_TXD_PIO1_13 N9X_MUX('1',13,11) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define SCT0_IN4_PIO1_14 N9X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PLU_IN2_PIO1_14 N9X_MUX('1',14,8) /* PT1_14 */ +#define ENET0_RXD0_PIO1_14 N9X_MUX('1',14,9) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define SCT0_IN5_PIO1_15 N9X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define PLU_IN3_PIO1_15 N9X_MUX('1',15,8) /* PT1_15 */ +#define ENET0_RXD1_PIO1_15 N9X_MUX('1',15,9) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define ADC1_A16_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define WUU0_IN14_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define FC5_P0_PIO1_16 N9X_MUX('1',16,2) /* PT1_16 */ +#define FC3_P4_PIO1_16 N9X_MUX('1',16,3) /* PT1_16 */ +#define CT_INP12_PIO1_16 N9X_MUX('1',16,4) /* PT1_16 */ +#define SCT0_OUT6_PIO1_16 N9X_MUX('1',16,5) /* PT1_16 */ +#define FLEXIO0_D24_PIO1_16 N9X_MUX('1',16,6) /* PT1_16 */ +#define EZH_PIO12_PIO1_16 N9X_MUX('1',16,7) /* PT1_16 */ +#define PLU_OUT4_PIO1_16 N9X_MUX('1',16,8) /* PT1_16 */ +#define ENET0_RXD2_PIO1_16 N9X_MUX('1',16,9) /* PT1_16 */ +#define I3C1_SDA_PIO1_16 N9X_MUX('1',16,10) /* PT1_16 */ +#define PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define ADC1_A17_PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define FC5_P1_PIO1_17 N9X_MUX('1',17,2) /* PT1_17 */ +#define FC3_P5_PIO1_17 N9X_MUX('1',17,3) /* PT1_17 */ +#define CT_INP13_PIO1_17 N9X_MUX('1',17,4) /* PT1_17 */ +#define SCT0_OUT7_PIO1_17 N9X_MUX('1',17,5) /* PT1_17 */ +#define FLEXIO0_D25_PIO1_17 N9X_MUX('1',17,6) /* PT1_17 */ +#define EZH_PIO13_PIO1_17 N9X_MUX('1',17,7) /* PT1_17 */ +#define PLU_OUT5_PIO1_17 N9X_MUX('1',17,8) /* PT1_17 */ +#define ENET0_RXD3_PIO1_17 N9X_MUX('1',17,9) /* PT1_17 */ +#define I3C1_SCL_PIO1_17 N9X_MUX('1',17,10) /* PT1_17 */ +#define PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define ADC1_A18_PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define FREQME_CLK_IN0_PIO1_18 N9X_MUX('1',18,1) /* PT1_18 */ +#define FC5_P2_PIO1_18 N9X_MUX('1',18,2) /* PT1_18 */ +#define FC3_P6_PIO1_18 N9X_MUX('1',18,3) /* PT1_18 */ +#define CT3_MAT0_PIO1_18 N9X_MUX('1',18,4) /* PT1_18 */ +#define SCT0_IN6_PIO1_18 N9X_MUX('1',18,5) /* PT1_18 */ +#define FLEXIO0_D26_PIO1_18 N9X_MUX('1',18,6) /* PT1_18 */ +#define EZH_PIO14_PIO1_18 N9X_MUX('1',18,7) /* PT1_18 */ +#define PLU_IN4_PIO1_18 N9X_MUX('1',18,8) /* PT1_18 */ +#define ENET0_COL_PIO1_18 N9X_MUX('1',18,9) /* PT1_18 */ +#define CAN0_TXD_PIO1_18 N9X_MUX('1',18,11) /* PT1_18 */ +#define PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define ADC1_A19_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define WUU0_IN15_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define FREQME_CLK_IN1_PIO1_19 N9X_MUX('1',19,1) /* PT1_19 */ +#define FC5_P3_PIO1_19 N9X_MUX('1',19,2) /* PT1_19 */ +#define CT3_MAT1_PIO1_19 N9X_MUX('1',19,4) /* PT1_19 */ +#define SCT0_IN7_PIO1_19 N9X_MUX('1',19,5) /* PT1_19 */ +#define FLEXIO0_D27_PIO1_19 N9X_MUX('1',19,6) /* PT1_19 */ +#define EZH_PIO15_PIO1_19 N9X_MUX('1',19,7) /* PT1_19 */ +#define PLU_IN5_PIO1_19 N9X_MUX('1',19,8) /* PT1_19 */ +#define ENET0_CRS_PIO1_19 N9X_MUX('1',19,9) /* PT1_19 */ +#define CAN0_RXD_PIO1_19 N9X_MUX('1',19,11) /* PT1_19 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SCT0_OUT8_PIO1_30 N9X_MUX('1',30,5) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define SCT0_OUT9_PIO1_31 N9X_MUX('1',31,5) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define FC9_P6_PIO2_0 N9X_MUX('2',0,2) /* PT2_0 */ +#define SCT0_IN0_PIO2_0 N9X_MUX('2',0,4) /* PT2_0 */ +#define PWM1_A3_PIO2_0 N9X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define FLEXSPI0_B_SS1_b_PIO2_0 N9X_MUX('2',0,8) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define SCT0_IN1_PIO2_1 N9X_MUX('2',1,4) /* PT2_1 */ +#define PWM1_B3_PIO2_1 N9X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define FLEXSPI0_B_DQS_PIO2_1 N9X_MUX('2',1,8) /* PT2_1 */ +#define SINC0_MCLK_OUT0_PIO2_1 N9X_MUX('2',1,9) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define FC9_P3_PIO2_2 N9X_MUX('2',2,2) /* PT2_2 */ +#define SCT0_OUT0_PIO2_2 N9X_MUX('2',2,4) /* PT2_2 */ +#define PWM1_A2_PIO2_2 N9X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define FLEXSPI0_B_SS0_b_PIO2_2 N9X_MUX('2',2,8) /* PT2_2 */ +#define SINC0_MCLK0_PIO2_2 N9X_MUX('2',2,9) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define FC9_P1_PIO2_3 N9X_MUX('2',3,2) /* PT2_3 */ +#define SCT0_OUT1_PIO2_3 N9X_MUX('2',3,4) /* PT2_3 */ +#define PWM1_B2_PIO2_3 N9X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define FLEXSPI0_B_SCLK_PIO2_3 N9X_MUX('2',3,8) /* PT2_3 */ +#define SINC0_MBIT0_PIO2_3 N9X_MUX('2',3,9) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define FC9_P0_PIO2_4 N9X_MUX('2',4,2) /* PT2_4 */ +#define SCT0_OUT2_PIO2_4 N9X_MUX('2',4,4) /* PT2_4 */ +#define PWM1_A1_PIO2_4 N9X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define FLEXSPI0_B_DATA0_PIO2_4 N9X_MUX('2',4,8) /* PT2_4 */ +#define SINC0_MCLK1_PIO2_4 N9X_MUX('2',4,9) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define FC9_P2_PIO2_5 N9X_MUX('2',5,2) /* PT2_5 */ +#define SCT0_OUT3_PIO2_5 N9X_MUX('2',5,4) /* PT2_5 */ +#define PWM1_B1_PIO2_5 N9X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define FLEXSPI0_B_DATA1_PIO2_5 N9X_MUX('2',5,8) /* PT2_5 */ +#define SINC0_MBIT1_PIO2_5 N9X_MUX('2',5,9) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define FC9_P4_PIO2_6 N9X_MUX('2',6,2) /* PT2_6 */ +#define SCT0_OUT4_PIO2_6 N9X_MUX('2',6,4) /* PT2_6 */ +#define PWM1_A0_PIO2_6 N9X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define FLEXSPI0_B_DATA2_PIO2_6 N9X_MUX('2',6,8) /* PT2_6 */ +#define SINC0_MCLK2_PIO2_6 N9X_MUX('2',6,9) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define FC9_P5_PIO2_7 N9X_MUX('2',7,2) /* PT2_7 */ +#define SCT0_OUT5_PIO2_7 N9X_MUX('2',7,4) /* PT2_7 */ +#define PWM1_B0_PIO2_7 N9X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define FLEXSPI0_B_DATA3_PIO2_7 N9X_MUX('2',7,8) /* PT2_7 */ +#define SINC0_MBIT2_PIO2_7 N9X_MUX('2',7,9) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO2_8 N9X_MUX('2',8,0) /* PT2_8 */ +#define TRACE_DATA0_PIO2_8 N9X_MUX('2',8,1) /* PT2_8 */ +#define SCT0_IN2_PIO2_8 N9X_MUX('2',8,4) /* PT2_8 */ +#define PWM1_X0_PIO2_8 N9X_MUX('2',8,5) /* PT2_8 */ +#define FLEXIO0_D16_PIO2_8 N9X_MUX('2',8,6) /* PT2_8 */ +#define EZH_PIO28_PIO2_8 N9X_MUX('2',8,7) /* PT2_8 */ +#define FLEXSPI0_B_DATA4_PIO2_8 N9X_MUX('2',8,8) /* PT2_8 */ +#define SINC0_MCLK3_PIO2_8 N9X_MUX('2',8,9) /* PT2_8 */ +#define SAI1_TXD0_PIO2_8 N9X_MUX('2',8,10) /* PT2_8 */ +#define PIO2_9 N9X_MUX('2',9,0) /* PT2_9 */ +#define TRACE_DATA1_PIO2_9 N9X_MUX('2',9,1) /* PT2_9 */ +#define SCT0_IN3_PIO2_9 N9X_MUX('2',9,4) /* PT2_9 */ +#define PWM1_X1_PIO2_9 N9X_MUX('2',9,5) /* PT2_9 */ +#define FLEXIO0_D17_PIO2_9 N9X_MUX('2',9,6) /* PT2_9 */ +#define EZH_PIO29_PIO2_9 N9X_MUX('2',9,7) /* PT2_9 */ +#define FLEXSPI0_B_DATA5_PIO2_9 N9X_MUX('2',9,8) /* PT2_9 */ +#define SINC0_MBIT3_PIO2_9 N9X_MUX('2',9,9) /* PT2_9 */ +#define SAI1_RXD0_PIO2_9 N9X_MUX('2',9,10) /* PT2_9 */ +#define PIO2_10 N9X_MUX('2',10,0) /* PT2_10 */ +#define TRACE_DATA2_PIO2_10 N9X_MUX('2',10,1) /* PT2_10 */ +#define SCT0_IN4_PIO2_10 N9X_MUX('2',10,4) /* PT2_10 */ +#define PWM1_X2_PIO2_10 N9X_MUX('2',10,5) /* PT2_10 */ +#define FLEXIO0_D18_PIO2_10 N9X_MUX('2',10,6) /* PT2_10 */ +#define EZH_PIO31_PIO2_10 N9X_MUX('2',10,7) /* PT2_10 */ +#define FLEXSPI0_B_DATA6_PIO2_10 N9X_MUX('2',10,8) /* PT2_10 */ +#define SINC0_MCLK4_PIO2_10 N9X_MUX('2',10,9) /* PT2_10 */ +#define SAI1_RXD1_PIO2_10 N9X_MUX('2',10,10) /* PT2_10 */ +#define PIO2_11 N9X_MUX('2',11,0) /* PT2_11 */ +#define TRACE_DATA3_PIO2_11 N9X_MUX('2',11,1) /* PT2_11 */ +#define SCT0_IN5_PIO2_11 N9X_MUX('2',11,4) /* PT2_11 */ +#define PWM1_X3_PIO2_11 N9X_MUX('2',11,5) /* PT2_11 */ +#define FLEXIO0_D19_PIO2_11 N9X_MUX('2',11,6) /* PT2_11 */ +#define EZH_PIO30_PIO2_11 N9X_MUX('2',11,7) /* PT2_11 */ +#define FLEXSPI0_B_DATA7_PIO2_11 N9X_MUX('2',11,8) /* PT2_11 */ +#define SINC0_MBIT4_PIO2_11 N9X_MUX('2',11,9) /* PT2_11 */ +#define SAI1_TXD1_PIO2_11 N9X_MUX('2',11,10) /* PT2_11 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define FLEXSPI0_A_SS0_b_PIO3_0 N9X_MUX('3',0,8) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FLEXSPI0_A_SS1_b_PIO3_1 N9X_MUX('3',1,8) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_2 N9X_MUX('3',2,0) /* PT3_2 */ +#define FC7_P0_PIO3_2 N9X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_PIO3_2 N9X_MUX('3',2,4) /* PT3_2 */ +#define PWM0_X0_PIO3_2 N9X_MUX('3',2,5) /* PT3_2 */ +#define FLEXIO0_D10_PIO3_2 N9X_MUX('3',2,6) /* PT3_2 */ +#define EZH_PIO2_PIO3_2 N9X_MUX('3',2,7) /* PT3_2 */ +#define PIO3_3 N9X_MUX('3',3,0) /* PT3_3 */ +#define FC7_P1_PIO3_3 N9X_MUX('3',3,2) /* PT3_3 */ +#define CT4_MAT1_PIO3_3 N9X_MUX('3',3,4) /* PT3_3 */ +#define PWM0_X1_PIO3_3 N9X_MUX('3',3,5) /* PT3_3 */ +#define FLEXIO0_D11_PIO3_3 N9X_MUX('3',3,6) /* PT3_3 */ +#define EZH_PIO3_PIO3_3 N9X_MUX('3',3,7) /* PT3_3 */ +#define PIO3_4 N9X_MUX('3',4,0) /* PT3_4 */ +#define FC7_P2_PIO3_4 N9X_MUX('3',4,2) /* PT3_4 */ +#define CT_INP18_PIO3_4 N9X_MUX('3',4,4) /* PT3_4 */ +#define PWM0_X2_PIO3_4 N9X_MUX('3',4,5) /* PT3_4 */ +#define FLEXIO0_D12_PIO3_4 N9X_MUX('3',4,6) /* PT3_4 */ +#define EZH_PIO4_PIO3_4 N9X_MUX('3',4,7) /* PT3_4 */ +#define PIO3_5 N9X_MUX('3',5,0) /* PT3_5 */ +#define FC7_P3_PIO3_5 N9X_MUX('3',5,2) /* PT3_5 */ +#define CT_INP19_PIO3_5 N9X_MUX('3',5,4) /* PT3_5 */ +#define PWM0_X3_PIO3_5 N9X_MUX('3',5,5) /* PT3_5 */ +#define FLEXIO0_D13_PIO3_5 N9X_MUX('3',5,6) /* PT3_5 */ +#define EZH_PIO5_PIO3_5 N9X_MUX('3',5,7) /* PT3_5 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define FLEXSPI0_A_DQS_PIO3_6 N9X_MUX('3',6,8) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define FLEXSPI0_A_SCLK_PIO3_7 N9X_MUX('3',7,8) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define FLEXSPI0_A_DATA0_PIO3_8 N9X_MUX('3',8,8) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define FLEXSPI0_A_DATA1_PIO3_9 N9X_MUX('3',9,8) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define FLEXSPI0_A_DATA2_PIO3_10 N9X_MUX('3',10,8) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define FLEXSPI0_A_DATA3_PIO3_11 N9X_MUX('3',11,8) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define PWM1_A0_PIO3_12 N9X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define FLEXSPI0_A_DATA4_PIO3_12 N9X_MUX('3',12,8) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define PWM1_B0_PIO3_13 N9X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define FLEXSPI0_A_DATA5_PIO3_13 N9X_MUX('3',13,8) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define FC8_P0_PIO3_14 N9X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define PWM1_A1_PIO3_14 N9X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define FLEXSPI0_A_DATA6_PIO3_14 N9X_MUX('3',14,8) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define FC8_P1_PIO3_15 N9X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define PWM1_B1_PIO3_15 N9X_MUX('3',15,5) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define FLEXSPI0_A_DATA7_PIO3_15 N9X_MUX('3',15,8) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define FC8_P2_PIO3_16 N9X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define PWM1_A2_PIO3_16 N9X_MUX('3',16,5) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define FC8_P3_PIO3_17 N9X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define PWM1_B2_PIO3_17 N9X_MUX('3',17,5) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC8_P4_PIO3_20 N9X_MUX('3',20,2) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define PWM1_A3_PIO3_20 N9X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC8_P5_PIO3_21 N9X_MUX('3',21,2) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define PWM1_B3_PIO3_21 N9X_MUX('3',21,5) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO3_22 N9X_MUX('3',22,0) /* PT3_22 */ +#define FC8_P6_PIO3_22 N9X_MUX('3',22,2) /* PT3_22 */ +#define FC6_P2_PIO3_22 N9X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_PIO3_22 N9X_MUX('3',22,4) /* PT3_22 */ +#define PWM1_X2_PIO3_22 N9X_MUX('3',22,5) /* PT3_22 */ +#define FLEXIO0_D30_PIO3_22 N9X_MUX('3',22,6) /* PT3_22 */ +#define EZH_PIO22_PIO3_22 N9X_MUX('3',22,7) /* PT3_22 */ +#define SAI1_RXD1_PIO3_22 N9X_MUX('3',22,10) /* PT3_22 */ +#define PIO3_23 N9X_MUX('3',23,0) /* PT3_23 */ +#define FC6_P3_PIO3_23 N9X_MUX('3',23,3) /* PT3_23 */ +#define CT_INP11_PIO3_23 N9X_MUX('3',23,4) /* PT3_23 */ +#define PWM1_X3_PIO3_23 N9X_MUX('3',23,5) /* PT3_23 */ +#define FLEXIO0_D31_PIO3_23 N9X_MUX('3',23,6) /* PT3_23 */ +#define EZH_PIO23_PIO3_23 N9X_MUX('3',23,7) /* PT3_23 */ +#define SAI1_TXD1_PIO3_23 N9X_MUX('3',23,10) /* PT3_23 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PLU_IN0_PIO4_0 N9X_MUX('4',0,8) /* PT4_0 */ +#define SINC0_MCLK3_PIO4_0 N9X_MUX('4',0,9) /* PT4_0 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define PLU_IN1_PIO4_1 N9X_MUX('4',1,8) /* PT4_1 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP2_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define DAC0_OUT_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define PLU_IN2_PIO4_2 N9X_MUX('4',2,8) /* PT4_2 */ +#define SINC0_MBIT3_PIO4_2 N9X_MUX('4',2,9) /* PT4_2 */ +#define DAC1_OUT_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP2_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PLU_IN3_PIO4_3 N9X_MUX('4',3,8) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define PLU_IN4_PIO4_4 N9X_MUX('4',4,8) /* PT4_4 */ +#define SINC0_MCLK4_PIO4_4 N9X_MUX('4',4,9) /* PT4_4 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PLU_IN5_PIO4_5 N9X_MUX('4',5,8) /* PT4_5 */ +#define SINC0_MBIT4_PIO4_5 N9X_MUX('4',5,9) /* PT4_5 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PLU_CLK_PIO4_6 N9X_MUX('4',6,8) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define OPAMP0_INP0_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define USB0_VBUS_DET_PIO4_12 N9X_MUX('4',12,1) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define PLU_OUT0_PIO4_12 N9X_MUX('4',12,8) /* PT4_12 */ +#define SINC0_MCLK0_PIO4_12 N9X_MUX('4',12,9) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define OPAMP0_INP1_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define PLU_OUT1_PIO4_13 N9X_MUX('4',13,8) /* PT4_13 */ +#define SINC0_MBIT0_PIO4_13 N9X_MUX('4',13,9) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_14 N9X_MUX('4',14,0) /* PT4_14 */ +#define CT4_MAT2_PIO4_14 N9X_MUX('4',14,4) /* PT4_14 */ +#define FLEXIO0_D22_PIO4_14 N9X_MUX('4',14,6) /* PT4_14 */ +#define PLU_OUT2_PIO4_14 N9X_MUX('4',14,8) /* PT4_14 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define OPAMP0_OUT_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define PLU_OUT3_PIO4_15 N9X_MUX('4',15,8) /* PT4_15 */ +#define SINC0_MCLK_OUT0_PIO4_15 N9X_MUX('4',15,9) /* PT4_15 */ +#define CAN1_RXD_PIO4_15 N9X_MUX('4',15,11) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define OPAMP1_INP0_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define PLU_OUT4_PIO4_16 N9X_MUX('4',16,8) /* PT4_16 */ +#define SINC0_MCLK1_PIO4_16 N9X_MUX('4',16,9) /* PT4_16 */ +#define CAN1_TXD_PIO4_16 N9X_MUX('4',16,11) /* PT4_16 */ +#define OPAMP1_INP1_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PLU_OUT5_PIO4_17 N9X_MUX('4',17,8) /* PT4_17 */ +#define SINC0_MBIT1_PIO4_17 N9X_MUX('4',17,9) /* PT4_17 */ +#define PIO4_18 N9X_MUX('4',18,0) /* PT4_18 */ +#define CT3_MAT2_PIO4_18 N9X_MUX('4',18,4) /* PT4_18 */ +#define FLEXIO0_D26_PIO4_18 N9X_MUX('4',18,6) /* PT4_18 */ +#define PLU_OUT6_PIO4_18 N9X_MUX('4',18,8) /* PT4_18 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define OPAMP1_OUT_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define PLU_OUT7_PIO4_19 N9X_MUX('4',19,8) /* PT4_19 */ +#define SINC0_MCLK_OUT1_PIO4_19 N9X_MUX('4',19,9) /* PT4_19 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define OPAMP2_INP0_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define SINC0_MCLK2_PIO4_20 N9X_MUX('4',20,9) /* PT4_20 */ +#define OPAMP2_INP1_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define SINC0_MBIT2_PIO4_21 N9X_MUX('4',21,9) /* PT4_21 */ +#define PIO4_22 N9X_MUX('4',22,0) /* PT4_22 */ +#define CT2_MAT2_PIO4_22 N9X_MUX('4',22,4) /* PT4_22 */ +#define FLEXIO0_D30_PIO4_22 N9X_MUX('4',22,6) /* PT4_22 */ +#define CMP2_IN4P_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define OPAMP2_OUT_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define SINC0_MCLK_OUT2_PIO4_23 N9X_MUX('4',23,9) /* PT4_23 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#define PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define ADC1_B12_PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define TRIG_OUT7_PIO5_4 N9X_MUX('5',4,1) /* PT5_4 */ +#define SPC_LPREQ_PIO5_4 N9X_MUX('5',4,2) /* PT5_4 */ +#define TAMPER2_PIO5_4 N9X_MUX('5',4,3) /* PT5_4 */ +#define PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define ADC1_B13_PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define TRIG_IN10_PIO5_5 N9X_MUX('5',5,1) /* PT5_5 */ +#define LPTMR0_ALT2_PIO5_5 N9X_MUX('5',5,2) /* PT5_5 */ +#define TAMPER3_PIO5_5 N9X_MUX('5',5,3) /* PT5_5 */ +#define ADC1_B14_PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define TRIG_OUT6_PIO5_6 N9X_MUX('5',6,1) /* PT5_6 */ +#define LPTMR1_ALT2_PIO5_6 N9X_MUX('5',6,2) /* PT5_6 */ +#define TAMPER4_PIO5_6 N9X_MUX('5',6,3) /* PT5_6 */ +#define PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define ADC1_B15_PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define TRIG_IN11_PIO5_7 N9X_MUX('5',7,1) /* PT5_7 */ +#define TAMPER5_PIO5_7 N9X_MUX('5',7,3) /* PT5_7 */ +#define PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define ADC1_B16_PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define TRIG_OUT7_PIO5_8 N9X_MUX('5',8,1) /* PT5_8 */ +#define TAMPER6_PIO5_8 N9X_MUX('5',8,3) /* PT5_8 */ +#define PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define ADC1_B17_PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define TAMPER7_PIO5_9 N9X_MUX('5',9,3) /* PT5_9 */ +#endif diff --git a/dts/nxp/mcx/MCXN947VPB-pinctrl.h b/dts/nxp/mcx/MCXN947VPB-pinctrl.h new file mode 100644 index 000000000..d540cb264 --- /dev/null +++ b/dts/nxp/mcx/MCXN947VPB-pinctrl.h @@ -0,0 +1,1003 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXN947VPB/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXN947VPB_ +#define _ZEPHYR_DTS_BINDING_MCXN947VPB_ + +#define N9X_MUX(port, pin, mux) \ + (((((port) - '0') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0xF) << 8)) + +#define PIO0_0 N9X_MUX('0',0,0) /* PT0_0 */ +#define TMS_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define SWDIO_PIO0_0 N9X_MUX('0',0,1) /* PT0_0 */ +#define FC1_P0_PIO0_0 N9X_MUX('0',0,2) /* PT0_0 */ +#define CT_INP0_PIO0_0 N9X_MUX('0',0,4) /* PT0_0 */ +#define PIO0_1 N9X_MUX('0',1,0) /* PT0_1 */ +#define TCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define SWCLK_PIO0_1 N9X_MUX('0',1,1) /* PT0_1 */ +#define FC1_P1_PIO0_1 N9X_MUX('0',1,2) /* PT0_1 */ +#define CT_INP1_PIO0_1 N9X_MUX('0',1,4) /* PT0_1 */ +#define PIO0_2 N9X_MUX('0',2,0) /* PT0_2 */ +#define TDO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define SWO_PIO0_2 N9X_MUX('0',2,1) /* PT0_2 */ +#define FC1_P2_PIO0_2 N9X_MUX('0',2,2) /* PT0_2 */ +#define CT0_MAT0_PIO0_2 N9X_MUX('0',2,4) /* PT0_2 */ +#define UTICK_CAP0_PIO0_2 N9X_MUX('0',2,5) /* PT0_2 */ +#define I3C0_PUR_PIO0_2 N9X_MUX('0',2,10) /* PT0_2 */ +#define PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define CMP1_IN1_PIO0_3 N9X_MUX('0',3,0) /* PT0_3 */ +#define TDI_PIO0_3 N9X_MUX('0',3,1) /* PT0_3 */ +#define FC1_P3_PIO0_3 N9X_MUX('0',3,2) /* PT0_3 */ +#define CT0_MAT1_PIO0_3 N9X_MUX('0',3,4) /* PT0_3 */ +#define UTICK_CAP1_PIO0_3 N9X_MUX('0',3,5) /* PT0_3 */ +#define HSCMP0_OUT_PIO0_3 N9X_MUX('0',3,8) /* PT0_3 */ +#define PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define TSI0_CH8_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define WUU0_IN0_PIO0_4 N9X_MUX('0',4,0) /* PT0_4 */ +#define EWM0_IN_PIO0_4 N9X_MUX('0',4,1) /* PT0_4 */ +#define FC0_P0_PIO0_4 N9X_MUX('0',4,2) /* PT0_4 */ +#define FC1_P4_PIO0_4 N9X_MUX('0',4,3) /* PT0_4 */ +#define CT0_MAT2_PIO0_4 N9X_MUX('0',4,4) /* PT0_4 */ +#define UTICK_CAP2_PIO0_4 N9X_MUX('0',4,5) /* PT0_4 */ +#define HSCMP1_OUT_PIO0_4 N9X_MUX('0',4,8) /* PT0_4 */ +#define PDM0_CLK_PIO0_4 N9X_MUX('0',4,9) /* PT0_4 */ +#define PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define TSI0_CH9_PIO0_5 N9X_MUX('0',5,0) /* PT0_5 */ +#define EWM0_OUT_b_PIO0_5 N9X_MUX('0',5,1) /* PT0_5 */ +#define FC0_P1_PIO0_5 N9X_MUX('0',5,2) /* PT0_5 */ +#define FC1_P5_PIO0_5 N9X_MUX('0',5,3) /* PT0_5 */ +#define CT0_MAT3_PIO0_5 N9X_MUX('0',5,4) /* PT0_5 */ +#define UTICK_CAP3_PIO0_5 N9X_MUX('0',5,5) /* PT0_5 */ +#define PDM0_DATA0_PIO0_5 N9X_MUX('0',5,9) /* PT0_5 */ +#define TSI0_CH10_PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define PIO0_6 N9X_MUX('0',6,0) /* PT0_6 */ +#define ISPMODE_N_PIO0_6 N9X_MUX('0',6,1) /* PT0_6 */ +#define FC0_P2_PIO0_6 N9X_MUX('0',6,2) /* PT0_6 */ +#define FC1_P6_PIO0_6 N9X_MUX('0',6,3) /* PT0_6 */ +#define CT_INP2_PIO0_6 N9X_MUX('0',6,4) /* PT0_6 */ +#define HSCMP2_OUT_PIO0_6 N9X_MUX('0',6,8) /* PT0_6 */ +#define PDM0_DATA1_PIO0_6 N9X_MUX('0',6,9) /* PT0_6 */ +#define CLKOUT_PIO0_6 N9X_MUX('0',6,12) /* PT0_6 */ +#define PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define WUU0_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define CMP2_IN1_PIO0_7 N9X_MUX('0',7,0) /* PT0_7 */ +#define FC0_P3_PIO0_7 N9X_MUX('0',7,2) /* PT0_7 */ +#define CT_INP3_PIO0_7 N9X_MUX('0',7,4) /* PT0_7 */ +#define PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define ADC0_B8_PIO0_8 N9X_MUX('0',8,0) /* PT0_8 */ +#define FC0_P4_PIO0_8 N9X_MUX('0',8,2) /* PT0_8 */ +#define CT_INP0_PIO0_8 N9X_MUX('0',8,4) /* PT0_8 */ +#define FLEXIO0_D0_PIO0_8 N9X_MUX('0',8,6) /* PT0_8 */ +#define PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define ADC0_B9_PIO0_9 N9X_MUX('0',9,0) /* PT0_9 */ +#define FC0_P5_PIO0_9 N9X_MUX('0',9,2) /* PT0_9 */ +#define CT_INP1_PIO0_9 N9X_MUX('0',9,4) /* PT0_9 */ +#define FLEXIO0_D1_PIO0_9 N9X_MUX('0',9,6) /* PT0_9 */ +#define PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define ADC0_B10_PIO0_10 N9X_MUX('0',10,0) /* PT0_10 */ +#define FC0_P6_PIO0_10 N9X_MUX('0',10,2) /* PT0_10 */ +#define CT0_MAT0_PIO0_10 N9X_MUX('0',10,4) /* PT0_10 */ +#define FLEXIO0_D2_PIO0_10 N9X_MUX('0',10,6) /* PT0_10 */ +#define PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define ADC0_B11_PIO0_11 N9X_MUX('0',11,0) /* PT0_11 */ +#define CT0_MAT1_PIO0_11 N9X_MUX('0',11,4) /* PT0_11 */ +#define FLEXIO0_D3_PIO0_11 N9X_MUX('0',11,6) /* PT0_11 */ +#define HSCMP2_OUT_PIO0_11 N9X_MUX('0',11,8) /* PT0_11 */ +#define PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define ADC0_B12_PIO0_12 N9X_MUX('0',12,0) /* PT0_12 */ +#define FC1_P4_PIO0_12 N9X_MUX('0',12,2) /* PT0_12 */ +#define FC0_P0_PIO0_12 N9X_MUX('0',12,3) /* PT0_12 */ +#define CT0_MAT2_PIO0_12 N9X_MUX('0',12,4) /* PT0_12 */ +#define FLEXIO0_D4_PIO0_12 N9X_MUX('0',12,6) /* PT0_12 */ +#define PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define ADC0_B13_PIO0_13 N9X_MUX('0',13,0) /* PT0_13 */ +#define FC1_P5_PIO0_13 N9X_MUX('0',13,2) /* PT0_13 */ +#define FC0_P1_PIO0_13 N9X_MUX('0',13,3) /* PT0_13 */ +#define CT0_MAT3_PIO0_13 N9X_MUX('0',13,4) /* PT0_13 */ +#define FLEXIO0_D5_PIO0_13 N9X_MUX('0',13,6) /* PT0_13 */ +#define PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define ADC0_B14_PIO0_14 N9X_MUX('0',14,0) /* PT0_14 */ +#define FC1_P6_PIO0_14 N9X_MUX('0',14,2) /* PT0_14 */ +#define FC0_P2_PIO0_14 N9X_MUX('0',14,3) /* PT0_14 */ +#define CT_INP2_PIO0_14 N9X_MUX('0',14,4) /* PT0_14 */ +#define UTICK_CAP0_PIO0_14 N9X_MUX('0',14,5) /* PT0_14 */ +#define FLEXIO0_D6_PIO0_14 N9X_MUX('0',14,6) /* PT0_14 */ +#define PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define ADC0_B15_PIO0_15 N9X_MUX('0',15,0) /* PT0_15 */ +#define FC0_P3_PIO0_15 N9X_MUX('0',15,3) /* PT0_15 */ +#define CT_INP3_PIO0_15 N9X_MUX('0',15,4) /* PT0_15 */ +#define UTICK_CAP1_PIO0_15 N9X_MUX('0',15,5) /* PT0_15 */ +#define FLEXIO0_D7_PIO0_15 N9X_MUX('0',15,6) /* PT0_15 */ +#define TSI0_CH11_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define WUU0_IN2_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define ADC0_A8_PIO0_16 N9X_MUX('0',16,0) /* PT0_16 */ +#define FC0_P0_PIO0_16 N9X_MUX('0',16,2) /* PT0_16 */ +#define CT0_MAT0_PIO0_16 N9X_MUX('0',16,4) /* PT0_16 */ +#define UTICK_CAP2_PIO0_16 N9X_MUX('0',16,5) /* PT0_16 */ +#define FLEXIO0_D0_PIO0_16 N9X_MUX('0',16,6) /* PT0_16 */ +#define PDM0_CLK_PIO0_16 N9X_MUX('0',16,9) /* PT0_16 */ +#define I3C0_SDA_PIO0_16 N9X_MUX('0',16,10) /* PT0_16 */ +#define PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define ADC0_A9_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define TSI0_CH12_PIO0_17 N9X_MUX('0',17,0) /* PT0_17 */ +#define FC0_P1_PIO0_17 N9X_MUX('0',17,2) /* PT0_17 */ +#define CT0_MAT1_PIO0_17 N9X_MUX('0',17,4) /* PT0_17 */ +#define UTICK_CAP3_PIO0_17 N9X_MUX('0',17,5) /* PT0_17 */ +#define FLEXIO0_D1_PIO0_17 N9X_MUX('0',17,6) /* PT0_17 */ +#define PDM0_DATA0_PIO0_17 N9X_MUX('0',17,9) /* PT0_17 */ +#define I3C0_SCL_PIO0_17 N9X_MUX('0',17,10) /* PT0_17 */ +#define PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define ADC0_A10_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define TSI0_CH13_PIO0_18 N9X_MUX('0',18,0) /* PT0_18 */ +#define EWM0_IN_PIO0_18 N9X_MUX('0',18,1) /* PT0_18 */ +#define FC0_P2_PIO0_18 N9X_MUX('0',18,2) /* PT0_18 */ +#define CT0_MAT2_PIO0_18 N9X_MUX('0',18,4) /* PT0_18 */ +#define FLEXIO0_D2_PIO0_18 N9X_MUX('0',18,6) /* PT0_18 */ +#define HSCMP0_OUT_PIO0_18 N9X_MUX('0',18,8) /* PT0_18 */ +#define PDM0_DATA1_PIO0_18 N9X_MUX('0',18,9) /* PT0_18 */ +#define TSI0_CH14_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define WUU0_IN3_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define ADC0_A11_PIO0_19 N9X_MUX('0',19,0) /* PT0_19 */ +#define EWM0_OUT_b_PIO0_19 N9X_MUX('0',19,1) /* PT0_19 */ +#define FC0_P3_PIO0_19 N9X_MUX('0',19,2) /* PT0_19 */ +#define CT0_MAT3_PIO0_19 N9X_MUX('0',19,4) /* PT0_19 */ +#define FLEXIO0_D3_PIO0_19 N9X_MUX('0',19,6) /* PT0_19 */ +#define HSCMP1_OUT_PIO0_19 N9X_MUX('0',19,8) /* PT0_19 */ +#define PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define TSI0_CH15_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define WUU0_IN4_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define ADC0_A12_PIO0_20 N9X_MUX('0',20,0) /* PT0_20 */ +#define FC0_P4_PIO0_20 N9X_MUX('0',20,2) /* PT0_20 */ +#define FC1_P0_PIO0_20 N9X_MUX('0',20,3) /* PT0_20 */ +#define CT_INP0_PIO0_20 N9X_MUX('0',20,4) /* PT0_20 */ +#define FLEXIO0_D4_PIO0_20 N9X_MUX('0',20,6) /* PT0_20 */ +#define I3C0_SDA_PIO0_20 N9X_MUX('0',20,10) /* PT0_20 */ +#define ADC0_A13_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define TSI0_CH16_PIO0_21 N9X_MUX('0',21,0) /* PT0_21 */ +#define FC0_P5_PIO0_21 N9X_MUX('0',21,2) /* PT0_21 */ +#define FC1_P1_PIO0_21 N9X_MUX('0',21,3) /* PT0_21 */ +#define CT_INP1_PIO0_21 N9X_MUX('0',21,4) /* PT0_21 */ +#define FLEXIO0_D5_PIO0_21 N9X_MUX('0',21,6) /* PT0_21 */ +#define I3C0_SCL_PIO0_21 N9X_MUX('0',21,10) /* PT0_21 */ +#define PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define ADC0_A14_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define CMP1_IN2_PIO0_22 N9X_MUX('0',22,0) /* PT0_22 */ +#define EWM0_IN_PIO0_22 N9X_MUX('0',22,1) /* PT0_22 */ +#define FC0_P6_PIO0_22 N9X_MUX('0',22,2) /* PT0_22 */ +#define FC1_P2_PIO0_22 N9X_MUX('0',22,3) /* PT0_22 */ +#define CT_INP2_PIO0_22 N9X_MUX('0',22,4) /* PT0_22 */ +#define FLEXIO0_D6_PIO0_22 N9X_MUX('0',22,6) /* PT0_22 */ +#define I3C0_PUR_PIO0_22 N9X_MUX('0',22,10) /* PT0_22 */ +#define PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define CMP2_IN2_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define ADC0_A15_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define WUU0_IN5_PIO0_23 N9X_MUX('0',23,0) /* PT0_23 */ +#define EWM0_OUT_b_PIO0_23 N9X_MUX('0',23,1) /* PT0_23 */ +#define FC1_P3_PIO0_23 N9X_MUX('0',23,3) /* PT0_23 */ +#define CT_INP3_PIO0_23 N9X_MUX('0',23,4) /* PT0_23 */ +#define FLEXIO0_D7_PIO0_23 N9X_MUX('0',23,6) /* PT0_23 */ +#define PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define ADC0_B16_PIO0_24 N9X_MUX('0',24,0) /* PT0_24 */ +#define FC1_P0_PIO0_24 N9X_MUX('0',24,2) /* PT0_24 */ +#define CT0_MAT0_PIO0_24 N9X_MUX('0',24,4) /* PT0_24 */ +#define PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define ADC0_B17_PIO0_25 N9X_MUX('0',25,0) /* PT0_25 */ +#define FC1_P1_PIO0_25 N9X_MUX('0',25,2) /* PT0_25 */ +#define CT0_MAT1_PIO0_25 N9X_MUX('0',25,4) /* PT0_25 */ +#define PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define ADC0_B18_PIO0_26 N9X_MUX('0',26,0) /* PT0_26 */ +#define FC1_P2_PIO0_26 N9X_MUX('0',26,2) /* PT0_26 */ +#define CT0_MAT2_PIO0_26 N9X_MUX('0',26,4) /* PT0_26 */ +#define PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define ADC0_B19_PIO0_27 N9X_MUX('0',27,0) /* PT0_27 */ +#define FC1_P3_PIO0_27 N9X_MUX('0',27,2) /* PT0_27 */ +#define CT0_MAT3_PIO0_27 N9X_MUX('0',27,4) /* PT0_27 */ +#define PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define WUU0_IN6_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TSI0_CH0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define CMP0_IN0_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define ADC0_A16_PIO1_0 N9X_MUX('1',0,0) /* PT1_0 */ +#define TRIG_IN0_PIO1_0 N9X_MUX('1',0,1) /* PT1_0 */ +#define FC3_P0_PIO1_0 N9X_MUX('1',0,2) /* PT1_0 */ +#define FC4_P4_PIO1_0 N9X_MUX('1',0,3) /* PT1_0 */ +#define CT_INP4_PIO1_0 N9X_MUX('1',0,4) /* PT1_0 */ +#define SCT0_OUT6_PIO1_0 N9X_MUX('1',0,5) /* PT1_0 */ +#define FLEXIO0_D8_PIO1_0 N9X_MUX('1',0,6) /* PT1_0 */ +#define SAI1_TX_BCLK_PIO1_0 N9X_MUX('1',0,10) /* PT1_0 */ +#define PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define ADC0_A17_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define CMP1_IN0_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TSI0_CH1_PIO1_1 N9X_MUX('1',1,0) /* PT1_1 */ +#define TRIG_IN1_PIO1_1 N9X_MUX('1',1,1) /* PT1_1 */ +#define FC3_P1_PIO1_1 N9X_MUX('1',1,2) /* PT1_1 */ +#define FC4_P5_PIO1_1 N9X_MUX('1',1,3) /* PT1_1 */ +#define CT_INP5_PIO1_1 N9X_MUX('1',1,4) /* PT1_1 */ +#define SCT0_OUT7_PIO1_1 N9X_MUX('1',1,5) /* PT1_1 */ +#define FLEXIO0_D9_PIO1_1 N9X_MUX('1',1,6) /* PT1_1 */ +#define SAI1_TX_FS_PIO1_1 N9X_MUX('1',1,10) /* PT1_1 */ +#define PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define ADC0_A18_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TSI0_CH2_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define CMP2_IN0_PIO1_2 N9X_MUX('1',2,0) /* PT1_2 */ +#define TRIG_OUT0_PIO1_2 N9X_MUX('1',2,1) /* PT1_2 */ +#define FC3_P2_PIO1_2 N9X_MUX('1',2,2) /* PT1_2 */ +#define FC4_P6_PIO1_2 N9X_MUX('1',2,3) /* PT1_2 */ +#define CT1_MAT0_PIO1_2 N9X_MUX('1',2,4) /* PT1_2 */ +#define SCT0_IN6_PIO1_2 N9X_MUX('1',2,5) /* PT1_2 */ +#define FLEXIO0_D10_PIO1_2 N9X_MUX('1',2,6) /* PT1_2 */ +#define ENET0_MDC_PIO1_2 N9X_MUX('1',2,9) /* PT1_2 */ +#define SAI1_TXD0_PIO1_2 N9X_MUX('1',2,10) /* PT1_2 */ +#define CAN0_TXD_PIO1_2 N9X_MUX('1',2,11) /* PT1_2 */ +#define PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TSI0_CH3_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define WUU0_IN7_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define CMP0_IN1_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define ADC0_A19_PIO1_3 N9X_MUX('1',3,0) /* PT1_3 */ +#define TRIG_OUT1_PIO1_3 N9X_MUX('1',3,1) /* PT1_3 */ +#define FC3_P3_PIO1_3 N9X_MUX('1',3,2) /* PT1_3 */ +#define CT1_MAT1_PIO1_3 N9X_MUX('1',3,4) /* PT1_3 */ +#define SCT0_IN7_PIO1_3 N9X_MUX('1',3,5) /* PT1_3 */ +#define FLEXIO0_D11_PIO1_3 N9X_MUX('1',3,6) /* PT1_3 */ +#define ENET0_MDIO_PIO1_3 N9X_MUX('1',3,9) /* PT1_3 */ +#define SAI1_RXD0_PIO1_3 N9X_MUX('1',3,10) /* PT1_3 */ +#define CAN0_RXD_PIO1_3 N9X_MUX('1',3,11) /* PT1_3 */ +#define PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define TSI0_CH4_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define WUU0_IN8_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define ADC0_A20_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define CMP0_IN2_PIO1_4 N9X_MUX('1',4,0) /* PT1_4 */ +#define FREQME_CLK_IN0_PIO1_4 N9X_MUX('1',4,1) /* PT1_4 */ +#define FC3_P4_PIO1_4 N9X_MUX('1',4,2) /* PT1_4 */ +#define FC5_P0_PIO1_4 N9X_MUX('1',4,3) /* PT1_4 */ +#define CT1_MAT2_PIO1_4 N9X_MUX('1',4,4) /* PT1_4 */ +#define SCT0_OUT0_PIO1_4 N9X_MUX('1',4,5) /* PT1_4 */ +#define FLEXIO0_D12_PIO1_4 N9X_MUX('1',4,6) /* PT1_4 */ +#define EZH_PIO0_PIO1_4 N9X_MUX('1',4,7) /* PT1_4 */ +#define ENET0_TX_CLK_PIO1_4 N9X_MUX('1',4,9) /* PT1_4 */ +#define SAI0_TXD1_PIO1_4 N9X_MUX('1',4,10) /* PT1_4 */ +#define PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define CMP0_IN3_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define TSI0_CH5_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define ADC0_A21_PIO1_5 N9X_MUX('1',5,0) /* PT1_5 */ +#define FREQME_CLK_IN1_PIO1_5 N9X_MUX('1',5,1) /* PT1_5 */ +#define FC3_P5_PIO1_5 N9X_MUX('1',5,2) /* PT1_5 */ +#define FC5_P1_PIO1_5 N9X_MUX('1',5,3) /* PT1_5 */ +#define CT1_MAT3_PIO1_5 N9X_MUX('1',5,4) /* PT1_5 */ +#define SCT0_OUT1_PIO1_5 N9X_MUX('1',5,5) /* PT1_5 */ +#define FLEXIO0_D13_PIO1_5 N9X_MUX('1',5,6) /* PT1_5 */ +#define EZH_PIO1_PIO1_5 N9X_MUX('1',5,7) /* PT1_5 */ +#define ENET0_TXEN_PIO1_5 N9X_MUX('1',5,9) /* PT1_5 */ +#define SAI0_RXD1_PIO1_5 N9X_MUX('1',5,10) /* PT1_5 */ +#define PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TSI0_CH6_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define ADC0_A22_PIO1_6 N9X_MUX('1',6,0) /* PT1_6 */ +#define TRIG_IN2_PIO1_6 N9X_MUX('1',6,1) /* PT1_6 */ +#define FC3_P6_PIO1_6 N9X_MUX('1',6,2) /* PT1_6 */ +#define FC5_P2_PIO1_6 N9X_MUX('1',6,3) /* PT1_6 */ +#define CT_INP6_PIO1_6 N9X_MUX('1',6,4) /* PT1_6 */ +#define SCT0_IN0_PIO1_6 N9X_MUX('1',6,5) /* PT1_6 */ +#define FLEXIO0_D14_PIO1_6 N9X_MUX('1',6,6) /* PT1_6 */ +#define EZH_PIO2_PIO1_6 N9X_MUX('1',6,7) /* PT1_6 */ +#define ENET0_TXD0_PIO1_6 N9X_MUX('1',6,9) /* PT1_6 */ +#define SAI1_RX_BCLK_PIO1_6 N9X_MUX('1',6,10) /* PT1_6 */ +#define CAN1_TXD_PIO1_6 N9X_MUX('1',6,11) /* PT1_6 */ +#define PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TSI0_CH7_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define ADC0_A23_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define WUU0_IN9_PIO1_7 N9X_MUX('1',7,0) /* PT1_7 */ +#define TRIG_OUT2_PIO1_7 N9X_MUX('1',7,1) /* PT1_7 */ +#define FC5_P3_PIO1_7 N9X_MUX('1',7,3) /* PT1_7 */ +#define CT_INP7_PIO1_7 N9X_MUX('1',7,4) /* PT1_7 */ +#define SCT0_IN1_PIO1_7 N9X_MUX('1',7,5) /* PT1_7 */ +#define FLEXIO0_D15_PIO1_7 N9X_MUX('1',7,6) /* PT1_7 */ +#define EZH_PIO3_PIO1_7 N9X_MUX('1',7,7) /* PT1_7 */ +#define PLU_CLK_PIO1_7 N9X_MUX('1',7,8) /* PT1_7 */ +#define ENET0_TXD1_PIO1_7 N9X_MUX('1',7,9) /* PT1_7 */ +#define SAI1_RX_FS_PIO1_7 N9X_MUX('1',7,10) /* PT1_7 */ +#define CAN1_RXD_PIO1_7 N9X_MUX('1',7,11) /* PT1_7 */ +#define TSI0_CH17_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define ADC1_A8_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define WUU0_IN10_PIO1_8 N9X_MUX('1',8,0) /* PT1_8 */ +#define TRACE_DATA0_PIO1_8 N9X_MUX('1',8,1) /* PT1_8 */ +#define FC4_P0_PIO1_8 N9X_MUX('1',8,2) /* PT1_8 */ +#define FC5_P4_PIO1_8 N9X_MUX('1',8,3) /* PT1_8 */ +#define CT_INP8_PIO1_8 N9X_MUX('1',8,4) /* PT1_8 */ +#define SCT0_OUT2_PIO1_8 N9X_MUX('1',8,5) /* PT1_8 */ +#define FLEXIO0_D16_PIO1_8 N9X_MUX('1',8,6) /* PT1_8 */ +#define EZH_PIO4_PIO1_8 N9X_MUX('1',8,7) /* PT1_8 */ +#define PLU_OUT0_PIO1_8 N9X_MUX('1',8,8) /* PT1_8 */ +#define ENET0_TXD2_PIO1_8 N9X_MUX('1',8,9) /* PT1_8 */ +#define I3C1_SDA_PIO1_8 N9X_MUX('1',8,10) /* PT1_8 */ +#define PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TSI0_CH18_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define ADC1_A9_PIO1_9 N9X_MUX('1',9,0) /* PT1_9 */ +#define TRACE_DATA1_PIO1_9 N9X_MUX('1',9,1) /* PT1_9 */ +#define FC4_P1_PIO1_9 N9X_MUX('1',9,2) /* PT1_9 */ +#define FC5_P5_PIO1_9 N9X_MUX('1',9,3) /* PT1_9 */ +#define CT_INP9_PIO1_9 N9X_MUX('1',9,4) /* PT1_9 */ +#define SCT0_OUT3_PIO1_9 N9X_MUX('1',9,5) /* PT1_9 */ +#define FLEXIO0_D17_PIO1_9 N9X_MUX('1',9,6) /* PT1_9 */ +#define EZH_PIO5_PIO1_9 N9X_MUX('1',9,7) /* PT1_9 */ +#define PLU_OUT1_PIO1_9 N9X_MUX('1',9,8) /* PT1_9 */ +#define ENET0_TXD3_PIO1_9 N9X_MUX('1',9,9) /* PT1_9 */ +#define I3C1_SCL_PIO1_9 N9X_MUX('1',9,10) /* PT1_9 */ +#define TSI0_CH19_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define ADC1_A10_PIO1_10 N9X_MUX('1',10,0) /* PT1_10 */ +#define TRACE_DATA2_PIO1_10 N9X_MUX('1',10,1) /* PT1_10 */ +#define FC4_P2_PIO1_10 N9X_MUX('1',10,2) /* PT1_10 */ +#define FC5_P6_PIO1_10 N9X_MUX('1',10,3) /* PT1_10 */ +#define CT2_MAT0_PIO1_10 N9X_MUX('1',10,4) /* PT1_10 */ +#define SCT0_IN2_PIO1_10 N9X_MUX('1',10,5) /* PT1_10 */ +#define FLEXIO0_D18_PIO1_10 N9X_MUX('1',10,6) /* PT1_10 */ +#define EZH_PIO6_PIO1_10 N9X_MUX('1',10,7) /* PT1_10 */ +#define PLU_IN0_PIO1_10 N9X_MUX('1',10,8) /* PT1_10 */ +#define ENET0_TXER_PIO1_10 N9X_MUX('1',10,9) /* PT1_10 */ +#define CAN0_TXD_PIO1_10 N9X_MUX('1',10,11) /* PT1_10 */ +#define ADC1_A11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TSI0_CH20_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define WUU0_IN11_PIO1_11 N9X_MUX('1',11,0) /* PT1_11 */ +#define TRACE_DATA3_PIO1_11 N9X_MUX('1',11,1) /* PT1_11 */ +#define FC4_P3_PIO1_11 N9X_MUX('1',11,2) /* PT1_11 */ +#define CT2_MAT1_PIO1_11 N9X_MUX('1',11,4) /* PT1_11 */ +#define SCT0_IN3_PIO1_11 N9X_MUX('1',11,5) /* PT1_11 */ +#define FLEXIO0_D19_PIO1_11 N9X_MUX('1',11,6) /* PT1_11 */ +#define EZH_PIO7_PIO1_11 N9X_MUX('1',11,7) /* PT1_11 */ +#define PLU_IN1_PIO1_11 N9X_MUX('1',11,8) /* PT1_11 */ +#define ENET0_RX_CLK_PIO1_11 N9X_MUX('1',11,9) /* PT1_11 */ +#define I3C1_PUR_PIO1_11 N9X_MUX('1',11,10) /* PT1_11 */ +#define CAN0_RXD_PIO1_11 N9X_MUX('1',11,11) /* PT1_11 */ +#define PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TSI0_CH21_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define WUU0_IN12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define ADC1_A12_PIO1_12 N9X_MUX('1',12,0) /* PT1_12 */ +#define TRACE_CLK_PIO1_12 N9X_MUX('1',12,1) /* PT1_12 */ +#define FC4_P4_PIO1_12 N9X_MUX('1',12,2) /* PT1_12 */ +#define FC3_P0_PIO1_12 N9X_MUX('1',12,3) /* PT1_12 */ +#define CT2_MAT2_PIO1_12 N9X_MUX('1',12,4) /* PT1_12 */ +#define SCT0_OUT4_PIO1_12 N9X_MUX('1',12,5) /* PT1_12 */ +#define FLEXIO0_D20_PIO1_12 N9X_MUX('1',12,6) /* PT1_12 */ +#define EZH_PIO8_PIO1_12 N9X_MUX('1',12,7) /* PT1_12 */ +#define PLU_OUT2_PIO1_12 N9X_MUX('1',12,8) /* PT1_12 */ +#define ENET0_RXER_PIO1_12 N9X_MUX('1',12,9) /* PT1_12 */ +#define CAN1_RXD_PIO1_12 N9X_MUX('1',12,11) /* PT1_12 */ +#define PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TSI0_CH22_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define ADC1_A13_PIO1_13 N9X_MUX('1',13,0) /* PT1_13 */ +#define TRIG_IN3_PIO1_13 N9X_MUX('1',13,1) /* PT1_13 */ +#define FC4_P5_PIO1_13 N9X_MUX('1',13,2) /* PT1_13 */ +#define FC3_P1_PIO1_13 N9X_MUX('1',13,3) /* PT1_13 */ +#define CT2_MAT3_PIO1_13 N9X_MUX('1',13,4) /* PT1_13 */ +#define SCT0_OUT5_PIO1_13 N9X_MUX('1',13,5) /* PT1_13 */ +#define FLEXIO0_D21_PIO1_13 N9X_MUX('1',13,6) /* PT1_13 */ +#define EZH_PIO9_PIO1_13 N9X_MUX('1',13,7) /* PT1_13 */ +#define PLU_OUT3_PIO1_13 N9X_MUX('1',13,8) /* PT1_13 */ +#define ENET0_RXDV_PIO1_13 N9X_MUX('1',13,9) /* PT1_13 */ +#define CAN1_TXD_PIO1_13 N9X_MUX('1',13,11) /* PT1_13 */ +#define PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define ADC1_A14_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define TSI0_CH23_PIO1_14 N9X_MUX('1',14,0) /* PT1_14 */ +#define FC4_P6_PIO1_14 N9X_MUX('1',14,2) /* PT1_14 */ +#define FC3_P2_PIO1_14 N9X_MUX('1',14,3) /* PT1_14 */ +#define CT_INP10_PIO1_14 N9X_MUX('1',14,4) /* PT1_14 */ +#define SCT0_IN4_PIO1_14 N9X_MUX('1',14,5) /* PT1_14 */ +#define FLEXIO0_D22_PIO1_14 N9X_MUX('1',14,6) /* PT1_14 */ +#define EZH_PIO10_PIO1_14 N9X_MUX('1',14,7) /* PT1_14 */ +#define PLU_IN2_PIO1_14 N9X_MUX('1',14,8) /* PT1_14 */ +#define ENET0_RXD0_PIO1_14 N9X_MUX('1',14,9) /* PT1_14 */ +#define PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define WUU0_IN13_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define ADC1_A15_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define TSI0_CH24_PIO1_15 N9X_MUX('1',15,0) /* PT1_15 */ +#define FC3_P3_PIO1_15 N9X_MUX('1',15,3) /* PT1_15 */ +#define CT_INP11_PIO1_15 N9X_MUX('1',15,4) /* PT1_15 */ +#define SCT0_IN5_PIO1_15 N9X_MUX('1',15,5) /* PT1_15 */ +#define FLEXIO0_D23_PIO1_15 N9X_MUX('1',15,6) /* PT1_15 */ +#define EZH_PIO11_PIO1_15 N9X_MUX('1',15,7) /* PT1_15 */ +#define PLU_IN3_PIO1_15 N9X_MUX('1',15,8) /* PT1_15 */ +#define ENET0_RXD1_PIO1_15 N9X_MUX('1',15,9) /* PT1_15 */ +#define I3C1_PUR_PIO1_15 N9X_MUX('1',15,10) /* PT1_15 */ +#define PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define ADC1_A16_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define WUU0_IN14_PIO1_16 N9X_MUX('1',16,0) /* PT1_16 */ +#define FC5_P0_PIO1_16 N9X_MUX('1',16,2) /* PT1_16 */ +#define FC3_P4_PIO1_16 N9X_MUX('1',16,3) /* PT1_16 */ +#define CT_INP12_PIO1_16 N9X_MUX('1',16,4) /* PT1_16 */ +#define SCT0_OUT6_PIO1_16 N9X_MUX('1',16,5) /* PT1_16 */ +#define FLEXIO0_D24_PIO1_16 N9X_MUX('1',16,6) /* PT1_16 */ +#define EZH_PIO12_PIO1_16 N9X_MUX('1',16,7) /* PT1_16 */ +#define PLU_OUT4_PIO1_16 N9X_MUX('1',16,8) /* PT1_16 */ +#define ENET0_RXD2_PIO1_16 N9X_MUX('1',16,9) /* PT1_16 */ +#define I3C1_SDA_PIO1_16 N9X_MUX('1',16,10) /* PT1_16 */ +#define PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define ADC1_A17_PIO1_17 N9X_MUX('1',17,0) /* PT1_17 */ +#define FC5_P1_PIO1_17 N9X_MUX('1',17,2) /* PT1_17 */ +#define FC3_P5_PIO1_17 N9X_MUX('1',17,3) /* PT1_17 */ +#define CT_INP13_PIO1_17 N9X_MUX('1',17,4) /* PT1_17 */ +#define SCT0_OUT7_PIO1_17 N9X_MUX('1',17,5) /* PT1_17 */ +#define FLEXIO0_D25_PIO1_17 N9X_MUX('1',17,6) /* PT1_17 */ +#define EZH_PIO13_PIO1_17 N9X_MUX('1',17,7) /* PT1_17 */ +#define PLU_OUT5_PIO1_17 N9X_MUX('1',17,8) /* PT1_17 */ +#define ENET0_RXD3_PIO1_17 N9X_MUX('1',17,9) /* PT1_17 */ +#define I3C1_SCL_PIO1_17 N9X_MUX('1',17,10) /* PT1_17 */ +#define ADC1_A18_PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define PIO1_18 N9X_MUX('1',18,0) /* PT1_18 */ +#define FREQME_CLK_IN0_PIO1_18 N9X_MUX('1',18,1) /* PT1_18 */ +#define FC5_P2_PIO1_18 N9X_MUX('1',18,2) /* PT1_18 */ +#define FC3_P6_PIO1_18 N9X_MUX('1',18,3) /* PT1_18 */ +#define CT3_MAT0_PIO1_18 N9X_MUX('1',18,4) /* PT1_18 */ +#define SCT0_IN6_PIO1_18 N9X_MUX('1',18,5) /* PT1_18 */ +#define FLEXIO0_D26_PIO1_18 N9X_MUX('1',18,6) /* PT1_18 */ +#define EZH_PIO14_PIO1_18 N9X_MUX('1',18,7) /* PT1_18 */ +#define PLU_IN4_PIO1_18 N9X_MUX('1',18,8) /* PT1_18 */ +#define ENET0_COL_PIO1_18 N9X_MUX('1',18,9) /* PT1_18 */ +#define CAN0_TXD_PIO1_18 N9X_MUX('1',18,11) /* PT1_18 */ +#define PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define ADC1_A19_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define WUU0_IN15_PIO1_19 N9X_MUX('1',19,0) /* PT1_19 */ +#define FREQME_CLK_IN1_PIO1_19 N9X_MUX('1',19,1) /* PT1_19 */ +#define FC5_P3_PIO1_19 N9X_MUX('1',19,2) /* PT1_19 */ +#define CT3_MAT1_PIO1_19 N9X_MUX('1',19,4) /* PT1_19 */ +#define SCT0_IN7_PIO1_19 N9X_MUX('1',19,5) /* PT1_19 */ +#define FLEXIO0_D27_PIO1_19 N9X_MUX('1',19,6) /* PT1_19 */ +#define EZH_PIO15_PIO1_19 N9X_MUX('1',19,7) /* PT1_19 */ +#define PLU_IN5_PIO1_19 N9X_MUX('1',19,8) /* PT1_19 */ +#define ENET0_CRS_PIO1_19 N9X_MUX('1',19,9) /* PT1_19 */ +#define CAN0_RXD_PIO1_19 N9X_MUX('1',19,11) /* PT1_19 */ +#define XTAL48M_PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define PIO1_30 N9X_MUX('1',30,0) /* PT1_30 */ +#define TRIG_OUT3_PIO1_30 N9X_MUX('1',30,1) /* PT1_30 */ +#define CT_INP16_PIO1_30 N9X_MUX('1',30,4) /* PT1_30 */ +#define SCT0_OUT8_PIO1_30 N9X_MUX('1',30,5) /* PT1_30 */ +#define SAI0_MCLK_PIO1_30 N9X_MUX('1',30,10) /* PT1_30 */ +#define PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define EXTAL48M_PIO1_31 N9X_MUX('1',31,0) /* PT1_31 */ +#define TRIG_IN4_PIO1_31 N9X_MUX('1',31,1) /* PT1_31 */ +#define CT_INP17_PIO1_31 N9X_MUX('1',31,4) /* PT1_31 */ +#define SCT0_OUT9_PIO1_31 N9X_MUX('1',31,5) /* PT1_31 */ +#define PIO2_0 N9X_MUX('2',0,0) /* PT2_0 */ +#define TRIG_IN5_PIO2_0 N9X_MUX('2',0,1) /* PT2_0 */ +#define FC9_P6_PIO2_0 N9X_MUX('2',0,2) /* PT2_0 */ +#define SDHC0_D5_PIO2_0 N9X_MUX('2',0,3) /* PT2_0 */ +#define SCT0_IN0_PIO2_0 N9X_MUX('2',0,4) /* PT2_0 */ +#define PWM1_A3_PIO2_0 N9X_MUX('2',0,5) /* PT2_0 */ +#define FLEXIO0_D8_PIO2_0 N9X_MUX('2',0,6) /* PT2_0 */ +#define EZH_PIO20_PIO2_0 N9X_MUX('2',0,7) /* PT2_0 */ +#define FLEXSPI0_B_SS1_b_PIO2_0 N9X_MUX('2',0,8) /* PT2_0 */ +#define SAI0_RX_BCLK_PIO2_0 N9X_MUX('2',0,10) /* PT2_0 */ +#define PIO2_1 N9X_MUX('2',1,0) /* PT2_1 */ +#define TRACE_CLK_PIO2_1 N9X_MUX('2',1,1) /* PT2_1 */ +#define SDHC0_D4_PIO2_1 N9X_MUX('2',1,3) /* PT2_1 */ +#define SCT0_IN1_PIO2_1 N9X_MUX('2',1,4) /* PT2_1 */ +#define PWM1_B3_PIO2_1 N9X_MUX('2',1,5) /* PT2_1 */ +#define FLEXIO0_D9_PIO2_1 N9X_MUX('2',1,6) /* PT2_1 */ +#define EZH_PIO21_PIO2_1 N9X_MUX('2',1,7) /* PT2_1 */ +#define FLEXSPI0_B_DQS_PIO2_1 N9X_MUX('2',1,8) /* PT2_1 */ +#define SINC0_MCLK_OUT0_PIO2_1 N9X_MUX('2',1,9) /* PT2_1 */ +#define SAI0_RX_FS_PIO2_1 N9X_MUX('2',1,10) /* PT2_1 */ +#define PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define WUU0_IN16_PIO2_2 N9X_MUX('2',2,0) /* PT2_2 */ +#define CLKOUT_PIO2_2 N9X_MUX('2',2,1) /* PT2_2 */ +#define FC9_P3_PIO2_2 N9X_MUX('2',2,2) /* PT2_2 */ +#define SDHC0_D1_PIO2_2 N9X_MUX('2',2,3) /* PT2_2 */ +#define SCT0_OUT0_PIO2_2 N9X_MUX('2',2,4) /* PT2_2 */ +#define PWM1_A2_PIO2_2 N9X_MUX('2',2,5) /* PT2_2 */ +#define FLEXIO0_D10_PIO2_2 N9X_MUX('2',2,6) /* PT2_2 */ +#define EZH_PIO22_PIO2_2 N9X_MUX('2',2,7) /* PT2_2 */ +#define FLEXSPI0_B_SS0_b_PIO2_2 N9X_MUX('2',2,8) /* PT2_2 */ +#define SINC0_MCLK0_PIO2_2 N9X_MUX('2',2,9) /* PT2_2 */ +#define SAI0_TXD0_PIO2_2 N9X_MUX('2',2,10) /* PT2_2 */ +#define PIO2_3 N9X_MUX('2',3,0) /* PT2_3 */ +#define FC9_P1_PIO2_3 N9X_MUX('2',3,2) /* PT2_3 */ +#define SDHC0_D0_PIO2_3 N9X_MUX('2',3,3) /* PT2_3 */ +#define SCT0_OUT1_PIO2_3 N9X_MUX('2',3,4) /* PT2_3 */ +#define PWM1_B2_PIO2_3 N9X_MUX('2',3,5) /* PT2_3 */ +#define FLEXIO0_D11_PIO2_3 N9X_MUX('2',3,6) /* PT2_3 */ +#define EZH_PIO23_PIO2_3 N9X_MUX('2',3,7) /* PT2_3 */ +#define FLEXSPI0_B_SCLK_PIO2_3 N9X_MUX('2',3,8) /* PT2_3 */ +#define SINC0_MBIT0_PIO2_3 N9X_MUX('2',3,9) /* PT2_3 */ +#define SAI0_RXD0_PIO2_3 N9X_MUX('2',3,10) /* PT2_3 */ +#define WUU0_IN17_PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define PIO2_4 N9X_MUX('2',4,0) /* PT2_4 */ +#define FC9_P0_PIO2_4 N9X_MUX('2',4,2) /* PT2_4 */ +#define SDHC0_CLK_PIO2_4 N9X_MUX('2',4,3) /* PT2_4 */ +#define SCT0_OUT2_PIO2_4 N9X_MUX('2',4,4) /* PT2_4 */ +#define PWM1_A1_PIO2_4 N9X_MUX('2',4,5) /* PT2_4 */ +#define FLEXIO0_D12_PIO2_4 N9X_MUX('2',4,6) /* PT2_4 */ +#define EZH_PIO24_PIO2_4 N9X_MUX('2',4,7) /* PT2_4 */ +#define FLEXSPI0_B_DATA0_PIO2_4 N9X_MUX('2',4,8) /* PT2_4 */ +#define SINC0_MCLK1_PIO2_4 N9X_MUX('2',4,9) /* PT2_4 */ +#define SAI0_RXD1_PIO2_4 N9X_MUX('2',4,10) /* PT2_4 */ +#define PIO2_5 N9X_MUX('2',5,0) /* PT2_5 */ +#define TRIG_OUT3_PIO2_5 N9X_MUX('2',5,1) /* PT2_5 */ +#define FC9_P2_PIO2_5 N9X_MUX('2',5,2) /* PT2_5 */ +#define SDHC0_CMD_PIO2_5 N9X_MUX('2',5,3) /* PT2_5 */ +#define SCT0_OUT3_PIO2_5 N9X_MUX('2',5,4) /* PT2_5 */ +#define PWM1_B1_PIO2_5 N9X_MUX('2',5,5) /* PT2_5 */ +#define FLEXIO0_D13_PIO2_5 N9X_MUX('2',5,6) /* PT2_5 */ +#define EZH_PIO25_PIO2_5 N9X_MUX('2',5,7) /* PT2_5 */ +#define FLEXSPI0_B_DATA1_PIO2_5 N9X_MUX('2',5,8) /* PT2_5 */ +#define SINC0_MBIT1_PIO2_5 N9X_MUX('2',5,9) /* PT2_5 */ +#define SAI0_TXD1_PIO2_5 N9X_MUX('2',5,10) /* PT2_5 */ +#define PIO2_6 N9X_MUX('2',6,0) /* PT2_6 */ +#define TRIG_IN4_PIO2_6 N9X_MUX('2',6,1) /* PT2_6 */ +#define FC9_P4_PIO2_6 N9X_MUX('2',6,2) /* PT2_6 */ +#define SDHC0_D3_PIO2_6 N9X_MUX('2',6,3) /* PT2_6 */ +#define SCT0_OUT4_PIO2_6 N9X_MUX('2',6,4) /* PT2_6 */ +#define PWM1_A0_PIO2_6 N9X_MUX('2',6,5) /* PT2_6 */ +#define FLEXIO0_D14_PIO2_6 N9X_MUX('2',6,6) /* PT2_6 */ +#define EZH_PIO26_PIO2_6 N9X_MUX('2',6,7) /* PT2_6 */ +#define FLEXSPI0_B_DATA2_PIO2_6 N9X_MUX('2',6,8) /* PT2_6 */ +#define SINC0_MCLK2_PIO2_6 N9X_MUX('2',6,9) /* PT2_6 */ +#define SAI0_TX_BCLK_PIO2_6 N9X_MUX('2',6,10) /* PT2_6 */ +#define PIO2_7 N9X_MUX('2',7,0) /* PT2_7 */ +#define TRIG_IN5_PIO2_7 N9X_MUX('2',7,1) /* PT2_7 */ +#define FC9_P5_PIO2_7 N9X_MUX('2',7,2) /* PT2_7 */ +#define SDHC0_D2_PIO2_7 N9X_MUX('2',7,3) /* PT2_7 */ +#define SCT0_OUT5_PIO2_7 N9X_MUX('2',7,4) /* PT2_7 */ +#define PWM1_B0_PIO2_7 N9X_MUX('2',7,5) /* PT2_7 */ +#define FLEXIO0_D15_PIO2_7 N9X_MUX('2',7,6) /* PT2_7 */ +#define EZH_PIO27_PIO2_7 N9X_MUX('2',7,7) /* PT2_7 */ +#define FLEXSPI0_B_DATA3_PIO2_7 N9X_MUX('2',7,8) /* PT2_7 */ +#define SINC0_MBIT2_PIO2_7 N9X_MUX('2',7,9) /* PT2_7 */ +#define SAI0_TX_FS_PIO2_7 N9X_MUX('2',7,10) /* PT2_7 */ +#define PIO2_8 N9X_MUX('2',8,0) /* PT2_8 */ +#define TRACE_DATA0_PIO2_8 N9X_MUX('2',8,1) /* PT2_8 */ +#define SDHC0_D7_PIO2_8 N9X_MUX('2',8,3) /* PT2_8 */ +#define SCT0_IN2_PIO2_8 N9X_MUX('2',8,4) /* PT2_8 */ +#define PWM1_X0_PIO2_8 N9X_MUX('2',8,5) /* PT2_8 */ +#define FLEXIO0_D16_PIO2_8 N9X_MUX('2',8,6) /* PT2_8 */ +#define EZH_PIO28_PIO2_8 N9X_MUX('2',8,7) /* PT2_8 */ +#define FLEXSPI0_B_DATA4_PIO2_8 N9X_MUX('2',8,8) /* PT2_8 */ +#define SINC0_MCLK3_PIO2_8 N9X_MUX('2',8,9) /* PT2_8 */ +#define SAI1_TXD0_PIO2_8 N9X_MUX('2',8,10) /* PT2_8 */ +#define PIO2_9 N9X_MUX('2',9,0) /* PT2_9 */ +#define TRACE_DATA1_PIO2_9 N9X_MUX('2',9,1) /* PT2_9 */ +#define SDHC0_D6_PIO2_9 N9X_MUX('2',9,3) /* PT2_9 */ +#define SCT0_IN3_PIO2_9 N9X_MUX('2',9,4) /* PT2_9 */ +#define PWM1_X1_PIO2_9 N9X_MUX('2',9,5) /* PT2_9 */ +#define FLEXIO0_D17_PIO2_9 N9X_MUX('2',9,6) /* PT2_9 */ +#define EZH_PIO29_PIO2_9 N9X_MUX('2',9,7) /* PT2_9 */ +#define FLEXSPI0_B_DATA5_PIO2_9 N9X_MUX('2',9,8) /* PT2_9 */ +#define SINC0_MBIT3_PIO2_9 N9X_MUX('2',9,9) /* PT2_9 */ +#define SAI1_RXD0_PIO2_9 N9X_MUX('2',9,10) /* PT2_9 */ +#define PIO2_10 N9X_MUX('2',10,0) /* PT2_10 */ +#define TRACE_DATA2_PIO2_10 N9X_MUX('2',10,1) /* PT2_10 */ +#define SCT0_IN4_PIO2_10 N9X_MUX('2',10,4) /* PT2_10 */ +#define PWM1_X2_PIO2_10 N9X_MUX('2',10,5) /* PT2_10 */ +#define FLEXIO0_D18_PIO2_10 N9X_MUX('2',10,6) /* PT2_10 */ +#define EZH_PIO31_PIO2_10 N9X_MUX('2',10,7) /* PT2_10 */ +#define FLEXSPI0_B_DATA6_PIO2_10 N9X_MUX('2',10,8) /* PT2_10 */ +#define SINC0_MCLK4_PIO2_10 N9X_MUX('2',10,9) /* PT2_10 */ +#define SAI1_RXD1_PIO2_10 N9X_MUX('2',10,10) /* PT2_10 */ +#define PIO2_11 N9X_MUX('2',11,0) /* PT2_11 */ +#define TRACE_DATA3_PIO2_11 N9X_MUX('2',11,1) /* PT2_11 */ +#define SCT0_IN5_PIO2_11 N9X_MUX('2',11,4) /* PT2_11 */ +#define PWM1_X3_PIO2_11 N9X_MUX('2',11,5) /* PT2_11 */ +#define FLEXIO0_D19_PIO2_11 N9X_MUX('2',11,6) /* PT2_11 */ +#define EZH_PIO30_PIO2_11 N9X_MUX('2',11,7) /* PT2_11 */ +#define FLEXSPI0_B_DATA7_PIO2_11 N9X_MUX('2',11,8) /* PT2_11 */ +#define SINC0_MBIT4_PIO2_11 N9X_MUX('2',11,9) /* PT2_11 */ +#define SAI1_TXD1_PIO2_11 N9X_MUX('2',11,10) /* PT2_11 */ +#define WUU0_IN22_PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define PIO3_0 N9X_MUX('3',0,0) /* PT3_0 */ +#define TRIG_IN0_PIO3_0 N9X_MUX('3',0,1) /* PT3_0 */ +#define FC7_P3_PIO3_0 N9X_MUX('3',0,3) /* PT3_0 */ +#define CT_INP16_PIO3_0 N9X_MUX('3',0,4) /* PT3_0 */ +#define PWM0_A0_PIO3_0 N9X_MUX('3',0,5) /* PT3_0 */ +#define FLEXIO0_D8_PIO3_0 N9X_MUX('3',0,6) /* PT3_0 */ +#define EZH_PIO0_PIO3_0 N9X_MUX('3',0,7) /* PT3_0 */ +#define FLEXSPI0_A_SS0_b_PIO3_0 N9X_MUX('3',0,8) /* PT3_0 */ +#define PIO3_1 N9X_MUX('3',1,0) /* PT3_1 */ +#define TRIG_IN1_PIO3_1 N9X_MUX('3',1,1) /* PT3_1 */ +#define FC6_P0_PIO3_1 N9X_MUX('3',1,2) /* PT3_1 */ +#define FC7_P6_PIO3_1 N9X_MUX('3',1,3) /* PT3_1 */ +#define CT_INP17_PIO3_1 N9X_MUX('3',1,4) /* PT3_1 */ +#define PWM0_B0_PIO3_1 N9X_MUX('3',1,5) /* PT3_1 */ +#define FLEXIO0_D9_PIO3_1 N9X_MUX('3',1,6) /* PT3_1 */ +#define EZH_PIO1_PIO3_1 N9X_MUX('3',1,7) /* PT3_1 */ +#define FLEXSPI0_A_SS1_b_PIO3_1 N9X_MUX('3',1,8) /* PT3_1 */ +#define FREQME_CLK_OUT0_PIO3_1 N9X_MUX('3',1,12) /* PT3_1 */ +#define PIO3_2 N9X_MUX('3',2,0) /* PT3_2 */ +#define FC7_P0_PIO3_2 N9X_MUX('3',2,2) /* PT3_2 */ +#define CT4_MAT0_PIO3_2 N9X_MUX('3',2,4) /* PT3_2 */ +#define PWM0_X0_PIO3_2 N9X_MUX('3',2,5) /* PT3_2 */ +#define FLEXIO0_D10_PIO3_2 N9X_MUX('3',2,6) /* PT3_2 */ +#define EZH_PIO2_PIO3_2 N9X_MUX('3',2,7) /* PT3_2 */ +#define SIM1_PD_PIO3_2 N9X_MUX('3',2,9) /* PT3_2 */ +#define PIO3_3 N9X_MUX('3',3,0) /* PT3_3 */ +#define FC7_P1_PIO3_3 N9X_MUX('3',3,2) /* PT3_3 */ +#define CT4_MAT1_PIO3_3 N9X_MUX('3',3,4) /* PT3_3 */ +#define PWM0_X1_PIO3_3 N9X_MUX('3',3,5) /* PT3_3 */ +#define FLEXIO0_D11_PIO3_3 N9X_MUX('3',3,6) /* PT3_3 */ +#define EZH_PIO3_PIO3_3 N9X_MUX('3',3,7) /* PT3_3 */ +#define SIM1_RST_PIO3_3 N9X_MUX('3',3,9) /* PT3_3 */ +#define PIO3_4 N9X_MUX('3',4,0) /* PT3_4 */ +#define FC7_P2_PIO3_4 N9X_MUX('3',4,2) /* PT3_4 */ +#define CT_INP18_PIO3_4 N9X_MUX('3',4,4) /* PT3_4 */ +#define PWM0_X2_PIO3_4 N9X_MUX('3',4,5) /* PT3_4 */ +#define FLEXIO0_D12_PIO3_4 N9X_MUX('3',4,6) /* PT3_4 */ +#define EZH_PIO4_PIO3_4 N9X_MUX('3',4,7) /* PT3_4 */ +#define SIM1_CLK_PIO3_4 N9X_MUX('3',4,9) /* PT3_4 */ +#define PIO3_5 N9X_MUX('3',5,0) /* PT3_5 */ +#define FC7_P3_PIO3_5 N9X_MUX('3',5,2) /* PT3_5 */ +#define CT_INP19_PIO3_5 N9X_MUX('3',5,4) /* PT3_5 */ +#define PWM0_X3_PIO3_5 N9X_MUX('3',5,5) /* PT3_5 */ +#define FLEXIO0_D13_PIO3_5 N9X_MUX('3',5,6) /* PT3_5 */ +#define EZH_PIO5_PIO3_5 N9X_MUX('3',5,7) /* PT3_5 */ +#define SIM1_IO_PIO3_5 N9X_MUX('3',5,9) /* PT3_5 */ +#define PIO3_6 N9X_MUX('3',6,0) /* PT3_6 */ +#define CLKOUT_PIO3_6 N9X_MUX('3',6,1) /* PT3_6 */ +#define FC6_P1_PIO3_6 N9X_MUX('3',6,2) /* PT3_6 */ +#define CT4_MAT2_PIO3_6 N9X_MUX('3',6,4) /* PT3_6 */ +#define PWM0_A1_PIO3_6 N9X_MUX('3',6,5) /* PT3_6 */ +#define FLEXIO0_D14_PIO3_6 N9X_MUX('3',6,6) /* PT3_6 */ +#define EZH_PIO6_PIO3_6 N9X_MUX('3',6,7) /* PT3_6 */ +#define FLEXSPI0_A_DQS_PIO3_6 N9X_MUX('3',6,8) /* PT3_6 */ +#define SIM1_VCCEN_PIO3_6 N9X_MUX('3',6,9) /* PT3_6 */ +#define SAI1_MCLK_PIO3_6 N9X_MUX('3',6,10) /* PT3_6 */ +#define FREQME_CLK_OUT1_PIO3_6 N9X_MUX('3',6,12) /* PT3_6 */ +#define PIO3_7 N9X_MUX('3',7,0) /* PT3_7 */ +#define FC6_P6_PIO3_7 N9X_MUX('3',7,2) /* PT3_7 */ +#define FC7_P1_PIO3_7 N9X_MUX('3',7,3) /* PT3_7 */ +#define CT4_MAT3_PIO3_7 N9X_MUX('3',7,4) /* PT3_7 */ +#define PWM0_B1_PIO3_7 N9X_MUX('3',7,5) /* PT3_7 */ +#define FLEXIO0_D15_PIO3_7 N9X_MUX('3',7,6) /* PT3_7 */ +#define EZH_PIO7_PIO3_7 N9X_MUX('3',7,7) /* PT3_7 */ +#define FLEXSPI0_A_SCLK_PIO3_7 N9X_MUX('3',7,8) /* PT3_7 */ +#define SIM0_VCCEN_PIO3_7 N9X_MUX('3',7,9) /* PT3_7 */ +#define SAI0_MCLK_PIO3_7 N9X_MUX('3',7,10) /* PT3_7 */ +#define PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define WUU0_IN23_PIO3_8 N9X_MUX('3',8,0) /* PT3_8 */ +#define FC6_P4_PIO3_8 N9X_MUX('3',8,2) /* PT3_8 */ +#define FC7_P0_PIO3_8 N9X_MUX('3',8,3) /* PT3_8 */ +#define CT_INP4_PIO3_8 N9X_MUX('3',8,4) /* PT3_8 */ +#define PWM0_A2_PIO3_8 N9X_MUX('3',8,5) /* PT3_8 */ +#define FLEXIO0_D16_PIO3_8 N9X_MUX('3',8,6) /* PT3_8 */ +#define EZH_PIO8_PIO3_8 N9X_MUX('3',8,7) /* PT3_8 */ +#define FLEXSPI0_A_DATA0_PIO3_8 N9X_MUX('3',8,8) /* PT3_8 */ +#define SIM0_PD_PIO3_8 N9X_MUX('3',8,9) /* PT3_8 */ +#define SAI0_TX_BCLK_PIO3_8 N9X_MUX('3',8,10) /* PT3_8 */ +#define PIO3_9 N9X_MUX('3',9,0) /* PT3_9 */ +#define FC6_P5_PIO3_9 N9X_MUX('3',9,2) /* PT3_9 */ +#define FC7_P2_PIO3_9 N9X_MUX('3',9,3) /* PT3_9 */ +#define CT_INP5_PIO3_9 N9X_MUX('3',9,4) /* PT3_9 */ +#define PWM0_B2_PIO3_9 N9X_MUX('3',9,5) /* PT3_9 */ +#define FLEXIO0_D17_PIO3_9 N9X_MUX('3',9,6) /* PT3_9 */ +#define EZH_PIO9_PIO3_9 N9X_MUX('3',9,7) /* PT3_9 */ +#define FLEXSPI0_A_DATA1_PIO3_9 N9X_MUX('3',9,8) /* PT3_9 */ +#define SIM0_RST_PIO3_9 N9X_MUX('3',9,9) /* PT3_9 */ +#define SAI0_TX_FS_PIO3_9 N9X_MUX('3',9,10) /* PT3_9 */ +#define PIO3_10 N9X_MUX('3',10,0) /* PT3_10 */ +#define FC6_P2_PIO3_10 N9X_MUX('3',10,2) /* PT3_10 */ +#define FC7_P4_PIO3_10 N9X_MUX('3',10,3) /* PT3_10 */ +#define CT1_MAT0_PIO3_10 N9X_MUX('3',10,4) /* PT3_10 */ +#define PWM0_A3_PIO3_10 N9X_MUX('3',10,5) /* PT3_10 */ +#define FLEXIO0_D18_PIO3_10 N9X_MUX('3',10,6) /* PT3_10 */ +#define EZH_PIO10_PIO3_10 N9X_MUX('3',10,7) /* PT3_10 */ +#define FLEXSPI0_A_DATA2_PIO3_10 N9X_MUX('3',10,8) /* PT3_10 */ +#define SIM0_CLK_PIO3_10 N9X_MUX('3',10,9) /* PT3_10 */ +#define SAI0_TXD0_PIO3_10 N9X_MUX('3',10,10) /* PT3_10 */ +#define WUU0_IN24_PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define PIO3_11 N9X_MUX('3',11,0) /* PT3_11 */ +#define FC6_P3_PIO3_11 N9X_MUX('3',11,2) /* PT3_11 */ +#define FC7_P5_PIO3_11 N9X_MUX('3',11,3) /* PT3_11 */ +#define CT1_MAT1_PIO3_11 N9X_MUX('3',11,4) /* PT3_11 */ +#define PWM0_B3_PIO3_11 N9X_MUX('3',11,5) /* PT3_11 */ +#define FLEXIO0_D19_PIO3_11 N9X_MUX('3',11,6) /* PT3_11 */ +#define EZH_PIO11_PIO3_11 N9X_MUX('3',11,7) /* PT3_11 */ +#define FLEXSPI0_A_DATA3_PIO3_11 N9X_MUX('3',11,8) /* PT3_11 */ +#define SIM0_IO_PIO3_11 N9X_MUX('3',11,9) /* PT3_11 */ +#define SAI0_RXD0_PIO3_11 N9X_MUX('3',11,10) /* PT3_11 */ +#define PIO3_12 N9X_MUX('3',12,0) /* PT3_12 */ +#define FC7_P4_PIO3_12 N9X_MUX('3',12,2) /* PT3_12 */ +#define FC6_P4_PIO3_12 N9X_MUX('3',12,3) /* PT3_12 */ +#define CT1_MAT2_PIO3_12 N9X_MUX('3',12,4) /* PT3_12 */ +#define PWM1_A0_PIO3_12 N9X_MUX('3',12,5) /* PT3_12 */ +#define FLEXIO0_D20_PIO3_12 N9X_MUX('3',12,6) /* PT3_12 */ +#define EZH_PIO12_PIO3_12 N9X_MUX('3',12,7) /* PT3_12 */ +#define FLEXSPI0_A_DATA4_PIO3_12 N9X_MUX('3',12,8) /* PT3_12 */ +#define SAI0_RXD1_PIO3_12 N9X_MUX('3',12,10) /* PT3_12 */ +#define PIO3_13 N9X_MUX('3',13,0) /* PT3_13 */ +#define FC7_P5_PIO3_13 N9X_MUX('3',13,2) /* PT3_13 */ +#define FC6_P5_PIO3_13 N9X_MUX('3',13,3) /* PT3_13 */ +#define CT1_MAT3_PIO3_13 N9X_MUX('3',13,4) /* PT3_13 */ +#define PWM1_B0_PIO3_13 N9X_MUX('3',13,5) /* PT3_13 */ +#define FLEXIO0_D21_PIO3_13 N9X_MUX('3',13,6) /* PT3_13 */ +#define EZH_PIO13_PIO3_13 N9X_MUX('3',13,7) /* PT3_13 */ +#define FLEXSPI0_A_DATA5_PIO3_13 N9X_MUX('3',13,8) /* PT3_13 */ +#define SAI0_TXD1_PIO3_13 N9X_MUX('3',13,10) /* PT3_13 */ +#define WUU0_IN25_PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define PIO3_14 N9X_MUX('3',14,0) /* PT3_14 */ +#define FC8_P0_PIO3_14 N9X_MUX('3',14,2) /* PT3_14 */ +#define CT_INP6_PIO3_14 N9X_MUX('3',14,4) /* PT3_14 */ +#define PWM1_A1_PIO3_14 N9X_MUX('3',14,5) /* PT3_14 */ +#define FLEXIO0_D22_PIO3_14 N9X_MUX('3',14,6) /* PT3_14 */ +#define EZH_PIO14_PIO3_14 N9X_MUX('3',14,7) /* PT3_14 */ +#define FLEXSPI0_A_DATA6_PIO3_14 N9X_MUX('3',14,8) /* PT3_14 */ +#define SAI0_RX_BCLK_PIO3_14 N9X_MUX('3',14,10) /* PT3_14 */ +#define PIO3_15 N9X_MUX('3',15,0) /* PT3_15 */ +#define FC8_P1_PIO3_15 N9X_MUX('3',15,2) /* PT3_15 */ +#define CT_INP7_PIO3_15 N9X_MUX('3',15,4) /* PT3_15 */ +#define PWM1_B1_PIO3_15 N9X_MUX('3',15,5) /* PT3_15 */ +#define FLEXIO0_D23_PIO3_15 N9X_MUX('3',15,6) /* PT3_15 */ +#define EZH_PIO15_PIO3_15 N9X_MUX('3',15,7) /* PT3_15 */ +#define FLEXSPI0_A_DATA7_PIO3_15 N9X_MUX('3',15,8) /* PT3_15 */ +#define SAI0_RX_FS_PIO3_15 N9X_MUX('3',15,10) /* PT3_15 */ +#define PIO3_16 N9X_MUX('3',16,0) /* PT3_16 */ +#define FC8_P2_PIO3_16 N9X_MUX('3',16,2) /* PT3_16 */ +#define CT_INP8_PIO3_16 N9X_MUX('3',16,4) /* PT3_16 */ +#define PWM1_A2_PIO3_16 N9X_MUX('3',16,5) /* PT3_16 */ +#define FLEXIO0_D24_PIO3_16 N9X_MUX('3',16,6) /* PT3_16 */ +#define EZH_PIO16_PIO3_16 N9X_MUX('3',16,7) /* PT3_16 */ +#define SIM0_CLK_PIO3_16 N9X_MUX('3',16,9) /* PT3_16 */ +#define SAI1_TX_BCLK_PIO3_16 N9X_MUX('3',16,10) /* PT3_16 */ +#define PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define WUU0_IN26_PIO3_17 N9X_MUX('3',17,0) /* PT3_17 */ +#define FC8_P3_PIO3_17 N9X_MUX('3',17,2) /* PT3_17 */ +#define CT_INP9_PIO3_17 N9X_MUX('3',17,4) /* PT3_17 */ +#define PWM1_B2_PIO3_17 N9X_MUX('3',17,5) /* PT3_17 */ +#define FLEXIO0_D25_PIO3_17 N9X_MUX('3',17,6) /* PT3_17 */ +#define EZH_PIO17_PIO3_17 N9X_MUX('3',17,7) /* PT3_17 */ +#define SIM0_IO_PIO3_17 N9X_MUX('3',17,9) /* PT3_17 */ +#define SAI1_TX_FS_PIO3_17 N9X_MUX('3',17,10) /* PT3_17 */ +#define PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define WUU0_IN27_PIO3_20 N9X_MUX('3',20,0) /* PT3_20 */ +#define TRIG_OUT0_PIO3_20 N9X_MUX('3',20,1) /* PT3_20 */ +#define FC8_P4_PIO3_20 N9X_MUX('3',20,2) /* PT3_20 */ +#define FC6_P0_PIO3_20 N9X_MUX('3',20,3) /* PT3_20 */ +#define CT2_MAT2_PIO3_20 N9X_MUX('3',20,4) /* PT3_20 */ +#define PWM1_A3_PIO3_20 N9X_MUX('3',20,5) /* PT3_20 */ +#define FLEXIO0_D28_PIO3_20 N9X_MUX('3',20,6) /* PT3_20 */ +#define EZH_PIO20_PIO3_20 N9X_MUX('3',20,7) /* PT3_20 */ +#define SIM0_PD_PIO3_20 N9X_MUX('3',20,9) /* PT3_20 */ +#define SAI1_TXD0_PIO3_20 N9X_MUX('3',20,10) /* PT3_20 */ +#define PIO3_21 N9X_MUX('3',21,0) /* PT3_21 */ +#define TRIG_OUT1_PIO3_21 N9X_MUX('3',21,1) /* PT3_21 */ +#define FC8_P5_PIO3_21 N9X_MUX('3',21,2) /* PT3_21 */ +#define FC6_P1_PIO3_21 N9X_MUX('3',21,3) /* PT3_21 */ +#define CT2_MAT3_PIO3_21 N9X_MUX('3',21,4) /* PT3_21 */ +#define PWM1_B3_PIO3_21 N9X_MUX('3',21,5) /* PT3_21 */ +#define FLEXIO0_D29_PIO3_21 N9X_MUX('3',21,6) /* PT3_21 */ +#define EZH_PIO21_PIO3_21 N9X_MUX('3',21,7) /* PT3_21 */ +#define SIM0_RST_PIO3_21 N9X_MUX('3',21,9) /* PT3_21 */ +#define SAI1_RXD0_PIO3_21 N9X_MUX('3',21,10) /* PT3_21 */ +#define PIO3_22 N9X_MUX('3',22,0) /* PT3_22 */ +#define FC8_P6_PIO3_22 N9X_MUX('3',22,2) /* PT3_22 */ +#define FC6_P2_PIO3_22 N9X_MUX('3',22,3) /* PT3_22 */ +#define CT_INP10_PIO3_22 N9X_MUX('3',22,4) /* PT3_22 */ +#define PWM1_X2_PIO3_22 N9X_MUX('3',22,5) /* PT3_22 */ +#define FLEXIO0_D30_PIO3_22 N9X_MUX('3',22,6) /* PT3_22 */ +#define EZH_PIO22_PIO3_22 N9X_MUX('3',22,7) /* PT3_22 */ +#define SIM0_VCCEN_PIO3_22 N9X_MUX('3',22,9) /* PT3_22 */ +#define SAI1_RXD1_PIO3_22 N9X_MUX('3',22,10) /* PT3_22 */ +#define PIO3_23 N9X_MUX('3',23,0) /* PT3_23 */ +#define FC6_P3_PIO3_23 N9X_MUX('3',23,3) /* PT3_23 */ +#define CT_INP11_PIO3_23 N9X_MUX('3',23,4) /* PT3_23 */ +#define PWM1_X3_PIO3_23 N9X_MUX('3',23,5) /* PT3_23 */ +#define FLEXIO0_D31_PIO3_23 N9X_MUX('3',23,6) /* PT3_23 */ +#define EZH_PIO23_PIO3_23 N9X_MUX('3',23,7) /* PT3_23 */ +#define SAI1_TXD1_PIO3_23 N9X_MUX('3',23,10) /* PT3_23 */ +#define PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define WUU0_IN18_PIO4_0 N9X_MUX('4',0,0) /* PT4_0 */ +#define TRIG_IN6_PIO4_0 N9X_MUX('4',0,1) /* PT4_0 */ +#define FC2_P0_PIO4_0 N9X_MUX('4',0,2) /* PT4_0 */ +#define CT_INP16_PIO4_0 N9X_MUX('4',0,4) /* PT4_0 */ +#define EZH_PIO24_PIO4_0 N9X_MUX('4',0,7) /* PT4_0 */ +#define PLU_IN0_PIO4_0 N9X_MUX('4',0,8) /* PT4_0 */ +#define SINC0_MCLK3_PIO4_0 N9X_MUX('4',0,9) /* PT4_0 */ +#define PIO4_1 N9X_MUX('4',1,0) /* PT4_1 */ +#define TRIG_IN7_PIO4_1 N9X_MUX('4',1,1) /* PT4_1 */ +#define FC2_P1_PIO4_1 N9X_MUX('4',1,2) /* PT4_1 */ +#define CT_INP17_PIO4_1 N9X_MUX('4',1,4) /* PT4_1 */ +#define EZH_PIO25_PIO4_1 N9X_MUX('4',1,7) /* PT4_1 */ +#define PLU_IN1_PIO4_1 N9X_MUX('4',1,8) /* PT4_1 */ +#define CMP1_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP2_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC1_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define CMP0_IN4N_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define ADC0_A4_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define DAC0_OUT_PIO4_2 N9X_MUX('4',2,0) /* PT4_2 */ +#define TRIG_IN6_PIO4_2 N9X_MUX('4',2,1) /* PT4_2 */ +#define FC2_P2_PIO4_2 N9X_MUX('4',2,2) /* PT4_2 */ +#define CT_INP12_PIO4_2 N9X_MUX('4',2,4) /* PT4_2 */ +#define EZH_PIO26_PIO4_2 N9X_MUX('4',2,7) /* PT4_2 */ +#define PLU_IN2_PIO4_2 N9X_MUX('4',2,8) /* PT4_2 */ +#define SINC0_MBIT3_PIO4_2 N9X_MUX('4',2,9) /* PT4_2 */ +#define CMP0_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP2_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC0_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define DAC1_OUT_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define WUU0_IN19_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define CMP1_IN5N_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define ADC1_B4_PIO4_3 N9X_MUX('4',3,0) /* PT4_3 */ +#define TRIG_IN7_PIO4_3 N9X_MUX('4',3,1) /* PT4_3 */ +#define FC2_P3_PIO4_3 N9X_MUX('4',3,2) /* PT4_3 */ +#define CT_INP13_PIO4_3 N9X_MUX('4',3,4) /* PT4_3 */ +#define EZH_PIO27_PIO4_3 N9X_MUX('4',3,7) /* PT4_3 */ +#define PLU_IN3_PIO4_3 N9X_MUX('4',3,8) /* PT4_3 */ +#define PIO4_4 N9X_MUX('4',4,0) /* PT4_4 */ +#define FC2_P4_PIO4_4 N9X_MUX('4',4,2) /* PT4_4 */ +#define CT_INP14_PIO4_4 N9X_MUX('4',4,4) /* PT4_4 */ +#define EZH_PIO28_PIO4_4 N9X_MUX('4',4,7) /* PT4_4 */ +#define PLU_IN4_PIO4_4 N9X_MUX('4',4,8) /* PT4_4 */ +#define SINC0_MCLK4_PIO4_4 N9X_MUX('4',4,9) /* PT4_4 */ +#define PIO4_5 N9X_MUX('4',5,0) /* PT4_5 */ +#define FC2_P5_PIO4_5 N9X_MUX('4',5,2) /* PT4_5 */ +#define CT_INP15_PIO4_5 N9X_MUX('4',5,4) /* PT4_5 */ +#define EZH_PIO29_PIO4_5 N9X_MUX('4',5,7) /* PT4_5 */ +#define PLU_IN5_PIO4_5 N9X_MUX('4',5,8) /* PT4_5 */ +#define SINC0_MBIT4_PIO4_5 N9X_MUX('4',5,9) /* PT4_5 */ +#define PIO4_6 N9X_MUX('4',6,0) /* PT4_6 */ +#define TRIG_OUT4_PIO4_6 N9X_MUX('4',6,1) /* PT4_6 */ +#define FC2_P6_PIO4_6 N9X_MUX('4',6,2) /* PT4_6 */ +#define CT_INP18_PIO4_6 N9X_MUX('4',6,4) /* PT4_6 */ +#define EZH_PIO30_PIO4_6 N9X_MUX('4',6,7) /* PT4_6 */ +#define PLU_CLK_PIO4_6 N9X_MUX('4',6,8) /* PT4_6 */ +#define PIO4_7 N9X_MUX('4',7,0) /* PT4_7 */ +#define CT_INP19_PIO4_7 N9X_MUX('4',7,4) /* PT4_7 */ +#define EZH_PIO31_PIO4_7 N9X_MUX('4',7,7) /* PT4_7 */ +#define ADC1_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define ADC0_A5_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define OPAMP0_INP0_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define WUU0_IN20_PIO4_12 N9X_MUX('4',12,0) /* PT4_12 */ +#define USB0_VBUS_DET_PIO4_12 N9X_MUX('4',12,1) /* PT4_12 */ +#define FC2_P0_PIO4_12 N9X_MUX('4',12,2) /* PT4_12 */ +#define CT4_MAT0_PIO4_12 N9X_MUX('4',12,4) /* PT4_12 */ +#define FLEXIO0_D20_PIO4_12 N9X_MUX('4',12,6) /* PT4_12 */ +#define PLU_OUT0_PIO4_12 N9X_MUX('4',12,8) /* PT4_12 */ +#define SINC0_MCLK0_PIO4_12 N9X_MUX('4',12,9) /* PT4_12 */ +#define CAN0_RXD_PIO4_12 N9X_MUX('4',12,11) /* PT4_12 */ +#define OPAMP0_INP1_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC1_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define ADC0_B5_PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define PIO4_13 N9X_MUX('4',13,0) /* PT4_13 */ +#define TRIG_IN8_PIO4_13 N9X_MUX('4',13,1) /* PT4_13 */ +#define FC2_P1_PIO4_13 N9X_MUX('4',13,2) /* PT4_13 */ +#define USB1_ID_PIO4_13 N9X_MUX('4',13,3) /* PT4_13 */ +#define CT4_MAT1_PIO4_13 N9X_MUX('4',13,4) /* PT4_13 */ +#define FLEXIO0_D21_PIO4_13 N9X_MUX('4',13,6) /* PT4_13 */ +#define PLU_OUT1_PIO4_13 N9X_MUX('4',13,8) /* PT4_13 */ +#define SINC0_MBIT0_PIO4_13 N9X_MUX('4',13,9) /* PT4_13 */ +#define CAN0_TXD_PIO4_13 N9X_MUX('4',13,11) /* PT4_13 */ +#define PIO4_14 N9X_MUX('4',14,0) /* PT4_14 */ +#define CT4_MAT2_PIO4_14 N9X_MUX('4',14,4) /* PT4_14 */ +#define FLEXIO0_D22_PIO4_14 N9X_MUX('4',14,6) /* PT4_14 */ +#define PLU_OUT2_PIO4_14 N9X_MUX('4',14,8) /* PT4_14 */ +#define OPAMP0_OUT_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define WUU0_IN21_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define CMP0_IN4P_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define ADC0_A1_PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define PIO4_15 N9X_MUX('4',15,0) /* PT4_15 */ +#define TRIG_OUT4_PIO4_15 N9X_MUX('4',15,1) /* PT4_15 */ +#define USB1_VBUS_DIG_PIO4_15 N9X_MUX('4',15,3) /* PT4_15 */ +#define CT4_MAT3_PIO4_15 N9X_MUX('4',15,4) /* PT4_15 */ +#define FLEXIO0_D23_PIO4_15 N9X_MUX('4',15,6) /* PT4_15 */ +#define PLU_OUT3_PIO4_15 N9X_MUX('4',15,8) /* PT4_15 */ +#define SINC0_MCLK_OUT0_PIO4_15 N9X_MUX('4',15,9) /* PT4_15 */ +#define CAN1_RXD_PIO4_15 N9X_MUX('4',15,11) /* PT4_15 */ +#define PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define ADC0_A6_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define OPAMP1_INP0_PIO4_16 N9X_MUX('4',16,0) /* PT4_16 */ +#define FC2_P2_PIO4_16 N9X_MUX('4',16,2) /* PT4_16 */ +#define USB1_OTG_PWR_PIO4_16 N9X_MUX('4',16,3) /* PT4_16 */ +#define CT3_MAT0_PIO4_16 N9X_MUX('4',16,4) /* PT4_16 */ +#define FLEXIO0_D24_PIO4_16 N9X_MUX('4',16,6) /* PT4_16 */ +#define PLU_OUT4_PIO4_16 N9X_MUX('4',16,8) /* PT4_16 */ +#define SINC0_MCLK1_PIO4_16 N9X_MUX('4',16,9) /* PT4_16 */ +#define CAN1_TXD_PIO4_16 N9X_MUX('4',16,11) /* PT4_16 */ +#define PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define ADC0_B6_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define OPAMP1_INP1_PIO4_17 N9X_MUX('4',17,0) /* PT4_17 */ +#define TRIG_IN9_PIO4_17 N9X_MUX('4',17,1) /* PT4_17 */ +#define FC2_P3_PIO4_17 N9X_MUX('4',17,2) /* PT4_17 */ +#define USB1_OTG_OC_PIO4_17 N9X_MUX('4',17,3) /* PT4_17 */ +#define CT3_MAT1_PIO4_17 N9X_MUX('4',17,4) /* PT4_17 */ +#define FLEXIO0_D25_PIO4_17 N9X_MUX('4',17,6) /* PT4_17 */ +#define PLU_OUT5_PIO4_17 N9X_MUX('4',17,8) /* PT4_17 */ +#define SINC0_MBIT1_PIO4_17 N9X_MUX('4',17,9) /* PT4_17 */ +#define PIO4_18 N9X_MUX('4',18,0) /* PT4_18 */ +#define CT3_MAT2_PIO4_18 N9X_MUX('4',18,4) /* PT4_18 */ +#define FLEXIO0_D26_PIO4_18 N9X_MUX('4',18,6) /* PT4_18 */ +#define PLU_OUT6_PIO4_18 N9X_MUX('4',18,8) /* PT4_18 */ +#define CMP1_IN4P_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define ADC0_B1_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define OPAMP1_OUT_PIO4_19 N9X_MUX('4',19,0) /* PT4_19 */ +#define TRIG_OUT5_PIO4_19 N9X_MUX('4',19,1) /* PT4_19 */ +#define CT3_MAT3_PIO4_19 N9X_MUX('4',19,4) /* PT4_19 */ +#define FLEXIO0_D27_PIO4_19 N9X_MUX('4',19,6) /* PT4_19 */ +#define PLU_OUT7_PIO4_19 N9X_MUX('4',19,8) /* PT4_19 */ +#define SINC0_MCLK_OUT1_PIO4_19 N9X_MUX('4',19,9) /* PT4_19 */ +#define OPAMP2_INP0_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define ADC1_A6_PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define PIO4_20 N9X_MUX('4',20,0) /* PT4_20 */ +#define TRIG_IN8_PIO4_20 N9X_MUX('4',20,1) /* PT4_20 */ +#define FC2_P4_PIO4_20 N9X_MUX('4',20,2) /* PT4_20 */ +#define CT2_MAT0_PIO4_20 N9X_MUX('4',20,4) /* PT4_20 */ +#define FLEXIO0_D28_PIO4_20 N9X_MUX('4',20,6) /* PT4_20 */ +#define SINC0_MCLK2_PIO4_20 N9X_MUX('4',20,9) /* PT4_20 */ +#define OPAMP2_INP1_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define ADC1_B6_PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define PIO4_21 N9X_MUX('4',21,0) /* PT4_21 */ +#define TRIG_IN9_PIO4_21 N9X_MUX('4',21,1) /* PT4_21 */ +#define FC2_P5_PIO4_21 N9X_MUX('4',21,2) /* PT4_21 */ +#define CT2_MAT1_PIO4_21 N9X_MUX('4',21,4) /* PT4_21 */ +#define FLEXIO0_D29_PIO4_21 N9X_MUX('4',21,6) /* PT4_21 */ +#define SINC0_MBIT2_PIO4_21 N9X_MUX('4',21,9) /* PT4_21 */ +#define PIO4_22 N9X_MUX('4',22,0) /* PT4_22 */ +#define CT2_MAT2_PIO4_22 N9X_MUX('4',22,4) /* PT4_22 */ +#define FLEXIO0_D30_PIO4_22 N9X_MUX('4',22,6) /* PT4_22 */ +#define ADC0_B2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC0_A2_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define ADC1_B3_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define OPAMP2_OUT_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define CMP2_IN4P_PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define PIO4_23 N9X_MUX('4',23,0) /* PT4_23 */ +#define TRIG_OUT5_PIO4_23 N9X_MUX('4',23,1) /* PT4_23 */ +#define FC2_P6_PIO4_23 N9X_MUX('4',23,2) /* PT4_23 */ +#define CT2_MAT3_PIO4_23 N9X_MUX('4',23,4) /* PT4_23 */ +#define FLEXIO0_D31_PIO4_23 N9X_MUX('4',23,6) /* PT4_23 */ +#define SINC0_MCLK_OUT2_PIO4_23 N9X_MUX('4',23,9) /* PT4_23 */ +#define EXTAL32K_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define ADC1_B8_PIO5_0 N9X_MUX('5',0,0) /* PT5_0 */ +#define TRIG_IN10_PIO5_0 N9X_MUX('5',0,1) /* PT5_0 */ +#define LPTMR0_ALT2_PIO5_0 N9X_MUX('5',0,2) /* PT5_0 */ +#define PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define ADC1_B9_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define XTAL32K_PIO5_1 N9X_MUX('5',1,0) /* PT5_1 */ +#define TRIG_OUT6_PIO5_1 N9X_MUX('5',1,1) /* PT5_1 */ +#define LPTMR1_ALT2_PIO5_1 N9X_MUX('5',1,2) /* PT5_1 */ +#define ADC1_B10_PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define PIO5_2 N9X_MUX('5',2,0) /* PT5_2 */ +#define VBAT_WAKEUP_b_PIO5_2 N9X_MUX('5',2,1) /* PT5_2 */ +#define SPC_LPREQ_PIO5_2 N9X_MUX('5',2,2) /* PT5_2 */ +#define TAMPER0_PIO5_2 N9X_MUX('5',2,3) /* PT5_2 */ +#define PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define ADC1_B11_PIO5_3 N9X_MUX('5',3,0) /* PT5_3 */ +#define TRIG_IN11_PIO5_3 N9X_MUX('5',3,1) /* PT5_3 */ +#define RTC_CLKOUT_PIO5_3 N9X_MUX('5',3,2) /* PT5_3 */ +#define TAMPER1_PIO5_3 N9X_MUX('5',3,3) /* PT5_3 */ +#define PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define ADC1_B12_PIO5_4 N9X_MUX('5',4,0) /* PT5_4 */ +#define TRIG_OUT7_PIO5_4 N9X_MUX('5',4,1) /* PT5_4 */ +#define SPC_LPREQ_PIO5_4 N9X_MUX('5',4,2) /* PT5_4 */ +#define TAMPER2_PIO5_4 N9X_MUX('5',4,3) /* PT5_4 */ +#define ADC1_B13_PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define PIO5_5 N9X_MUX('5',5,0) /* PT5_5 */ +#define TRIG_IN10_PIO5_5 N9X_MUX('5',5,1) /* PT5_5 */ +#define LPTMR0_ALT2_PIO5_5 N9X_MUX('5',5,2) /* PT5_5 */ +#define TAMPER3_PIO5_5 N9X_MUX('5',5,3) /* PT5_5 */ +#define ADC1_B14_PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define PIO5_6 N9X_MUX('5',6,0) /* PT5_6 */ +#define TRIG_OUT6_PIO5_6 N9X_MUX('5',6,1) /* PT5_6 */ +#define LPTMR1_ALT2_PIO5_6 N9X_MUX('5',6,2) /* PT5_6 */ +#define TAMPER4_PIO5_6 N9X_MUX('5',6,3) /* PT5_6 */ +#define PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define ADC1_B15_PIO5_7 N9X_MUX('5',7,0) /* PT5_7 */ +#define TRIG_IN11_PIO5_7 N9X_MUX('5',7,1) /* PT5_7 */ +#define TAMPER5_PIO5_7 N9X_MUX('5',7,3) /* PT5_7 */ +#define PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define ADC1_B16_PIO5_8 N9X_MUX('5',8,0) /* PT5_8 */ +#define TRIG_OUT7_PIO5_8 N9X_MUX('5',8,1) /* PT5_8 */ +#define TAMPER6_PIO5_8 N9X_MUX('5',8,3) /* PT5_8 */ +#define PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define ADC1_B17_PIO5_9 N9X_MUX('5',9,0) /* PT5_9 */ +#define TAMPER7_PIO5_9 N9X_MUX('5',9,3) /* PT5_9 */ +#endif diff --git a/dts/nxp/mcx/MCXW716AMFPA-pinctrl.h b/dts/nxp/mcx/MCXW716AMFPA-pinctrl.h new file mode 100644 index 000000000..04bcdf4b3 --- /dev/null +++ b/dts/nxp/mcx/MCXW716AMFPA-pinctrl.h @@ -0,0 +1,179 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXW716AMFPA/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXW716AMFPA_ +#define _ZEPHYR_DTS_BINDING_MCXW716AMFPA_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define WUU0_P0_PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define CMP0_OUT_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define RF_GPO_11_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define TPM0_CH4_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define FLEXIO0_D0_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define SWD_DIO_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define CMP1_OUT_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPUART0_RTS_b_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define RF_GPO_10_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define TPM0_CH5_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define FLEXIO0_D1_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define SWD_CLK_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define CMP0_IN0_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define ADC0_A10_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define RF_XTAL_OUT_ENABLE_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define WUU0_P2_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define RF_GPO_9_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define TPM0_CLKIN_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define TRACE_SWO_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define FLEXIO0_D4_PTA4 KINETIS_MUX('A',4,6) /* PTA_4 */ +#define BOOT_CONFIG_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define ADC0_A13_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define WUU0_P3_PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define RF_NOT_ALLOWED_PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define LPSPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM0_IN_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define LPI2C0_SDAS_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define TPM0_CH5_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define LPUART0_TX_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define RF_GPO_7_PTA17 KINETIS_MUX('A',17,7) /* PTA_17 */ +#define RF_GPO_8_PTA17 KINETIS_MUX('A',17,8) /* PTA_17 */ +#define FLEXIO0_D6_PTA17 KINETIS_MUX('A',17,9) /* PTA_17 */ +#define RF_EXT_XTAL_REQUEST_PTA17 KINETIS_MUX('A',17,11) /* PTA_17 */ +#define CMP1_IN1_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPSPI0_SOUT_PTA18 KINETIS_MUX('A',18,2) /* PTA_18 */ +#define LPUART0_CTS_b_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define LPI2C0_SDA_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM0_CH3_PTA18 KINETIS_MUX('A',18,5) /* PTA_18 */ +#define RF_GPO_0_PTA18 KINETIS_MUX('A',18,6) /* PTA_18 */ +#define LPUART0_RX_PTA18 KINETIS_MUX('A',18,10) /* PTA_18 */ +#define SPC0_LPREQ_PTA18 KINETIS_MUX('A',18,11) /* PTA_18 */ +#define CMP1_IN0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define WUU0_P4_PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPSPI0_SCK_PTA19 KINETIS_MUX('A',19,2) /* PTA_19 */ +#define LPUART0_RTS_b_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define LPI2C0_SCL_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define TPM0_CH2_PTA19 KINETIS_MUX('A',19,5) /* PTA_19 */ +#define RF_GPO_1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define CMP0_IN3_PTA20 KINETIS_MUX('A',20,0) /* PTA_20 */ +#define ADC0_A14_PTA20 KINETIS_MUX('A',20,0) /* PTA_20 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define LPSPI0_PCS2_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART0_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define EWM0_IN_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define TPM0_CH1_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define RF_GPO_2_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define FLEXIO0_D7_PTA20 KINETIS_MUX('A',20,8) /* PTA_20 */ +#define ADC0_A15_PTA21 KINETIS_MUX('A',21,0) /* PTA_21 */ +#define CMP0_IN2_PTA21 KINETIS_MUX('A',21,0) /* PTA_21 */ +#define WUU0_P5_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LPSPI0_PCS3_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART0_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define EWM0_OUT_b_PTA21 KINETIS_MUX('A',21,4) /* PTA_21 */ +#define TPM0_CH0_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define RF_GPO_3_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define RF_GPO_7_PTA21 KINETIS_MUX('A',21,7) /* PTA_21 */ +#define FLEXIO0_D8_PTA21 KINETIS_MUX('A',21,8) /* PTA_21 */ +#define RF_GPO_10_PTA21 KINETIS_MUX('A',21,9) /* PTA_21 */ +#define ADC0_B10_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define WUU0_P13_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPSPI1_PCS0_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FLEXIO0_D26_PTB0 KINETIS_MUX('B',0,9) /* PTB_0 */ +#define ADC0_B11_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPSPI1_SIN_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FLEXIO0_D27_PTB1 KINETIS_MUX('B',1,9) /* PTB_1 */ +#define ADC0_B12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define LPSPI1_SCK_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART1_TX_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TPM1_CH2_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FLEXIO0_D28_PTB2 KINETIS_MUX('B',2,9) /* PTB_2 */ +#define ADC0_B13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define WUU0_P14_PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define LPSPI1_SOUT_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART1_RX_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TPM1_CH3_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FLEXIO0_D29_PTB3 KINETIS_MUX('B',3,9) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define WUU0_P15_PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define LPSPI1_PCS3_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPUART1_CTS_b_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define LPI2C1_SDA_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define I3C0_SDA_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define TRGMUX0_IN0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define FLEXIO0_D30_PTB4 KINETIS_MUX('B',4,9) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define LPSPI1_PCS2_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPUART1_RTS_b_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define LPI2C1_SCL_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define I3C0_SCL_PTB5 KINETIS_MUX('B',5,5) /* PTB_5 */ +#define TRGMUX0_OUT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define FLEXIO0_D31_PTB5 KINETIS_MUX('B',5,9) /* PTB_5 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define WUU0_P9_PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define LPSPI1_SOUT_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_RX_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define LPI2C1_SCLS_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define TPM1_CH2_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I3C0_PUR_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define FLEXIO0_D18_PTC2 KINETIS_MUX('C',2,9) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LPSPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_TX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define LPI2C1_SDAS_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define TPM1_CH3_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define FLEXIO0_D19_PTC3 KINETIS_MUX('C',3,9) /* PTC_3 */ +#define WUU0_P10_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LPSPI1_SIN_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPI2C1_SCL_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define TPM2_CH0_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define FLEXIO0_D20_PTC4 KINETIS_MUX('C',4,9) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LPSPI1_PCS0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPI2C1_SDA_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define TPM1_CH4_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define TPM2_CH1_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FLEXIO0_D21_PTC5 KINETIS_MUX('C',5,9) /* PTC_5 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define NMI_b_PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define RF_NOT_ALLOWED_PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define WUU0_P12_PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define TRGMUX0_IN3_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define TRGMUX0_OUT3_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SFA0_CLK_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define TPM1_CLKIN_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define TPM2_CLKIN_PTC7 KINETIS_MUX('C',7,6) /* PTC_7 */ +#define CLKOUT_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define FLEXIO0_D23_PTC7 KINETIS_MUX('C',7,9) /* PTC_7 */ +#define ADC0_A5_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define RESET_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define XTAL32K_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LPTMR0_ALT2_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define TAMPER2_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define EXTAL32K_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPTMR1_ALT2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#endif diff --git a/dts/nxp/mcx/MCXW716AMFTA-pinctrl.h b/dts/nxp/mcx/MCXW716AMFTA-pinctrl.h new file mode 100644 index 000000000..3bf0726e5 --- /dev/null +++ b/dts/nxp/mcx/MCXW716AMFTA-pinctrl.h @@ -0,0 +1,225 @@ +/* + * NOTE: Autogenerated file by gen_soc_headers.py + * for MCXW716AMFTA/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MCXW716AMFTA_ +#define _ZEPHYR_DTS_BINDING_MCXW716AMFTA_ + +#define KINETIS_MUX(port, pin, mux) \ + (((((port) - 'A') & 0xF) << 28) | \ + (((pin) & 0x3F) << 22) | \ + (((mux) & 0x7) << 8)) + +#define PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define WUU0_P0_PTA0 KINETIS_MUX('A',0,1) /* PTA_0 */ +#define CMP0_OUT_PTA0 KINETIS_MUX('A',0,2) /* PTA_0 */ +#define LPUART0_CTS_b_PTA0 KINETIS_MUX('A',0,3) /* PTA_0 */ +#define RF_GPO_11_PTA0 KINETIS_MUX('A',0,4) /* PTA_0 */ +#define TPM0_CH4_PTA0 KINETIS_MUX('A',0,5) /* PTA_0 */ +#define FLEXIO0_D0_PTA0 KINETIS_MUX('A',0,6) /* PTA_0 */ +#define SWD_DIO_PTA0 KINETIS_MUX('A',0,7) /* PTA_0 */ +#define PTA1 KINETIS_MUX('A',1,1) /* PTA_1 */ +#define CMP1_OUT_PTA1 KINETIS_MUX('A',1,2) /* PTA_1 */ +#define LPUART0_RTS_b_PTA1 KINETIS_MUX('A',1,3) /* PTA_1 */ +#define RF_GPO_10_PTA1 KINETIS_MUX('A',1,4) /* PTA_1 */ +#define TPM0_CH5_PTA1 KINETIS_MUX('A',1,5) /* PTA_1 */ +#define FLEXIO0_D1_PTA1 KINETIS_MUX('A',1,6) /* PTA_1 */ +#define SWD_CLK_PTA1 KINETIS_MUX('A',1,7) /* PTA_1 */ +#define CMP0_IN0_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define ADC0_A10_PTA4 KINETIS_MUX('A',4,0) /* PTA_4 */ +#define RF_XTAL_OUT_ENABLE_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define WUU0_P2_PTA4 KINETIS_MUX('A',4,1) /* PTA_4 */ +#define RF_GPO_9_PTA4 KINETIS_MUX('A',4,3) /* PTA_4 */ +#define TPM0_CLKIN_PTA4 KINETIS_MUX('A',4,4) /* PTA_4 */ +#define TRACE_SWO_PTA4 KINETIS_MUX('A',4,5) /* PTA_4 */ +#define FLEXIO0_D4_PTA4 KINETIS_MUX('A',4,6) /* PTA_4 */ +#define BOOT_CONFIG_PTA4 KINETIS_MUX('A',4,7) /* PTA_4 */ +#define ADC0_A12_PTA16 KINETIS_MUX('A',16,0) /* PTA_16 */ +#define PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define RF_NOT_ALLOWED_PTA16 KINETIS_MUX('A',16,1) /* PTA_16 */ +#define LPSPI0_PCS0_PTA16 KINETIS_MUX('A',16,2) /* PTA_16 */ +#define EWM0_OUT_b_PTA16 KINETIS_MUX('A',16,3) /* PTA_16 */ +#define LPI2C0_SCLS_PTA16 KINETIS_MUX('A',16,4) /* PTA_16 */ +#define TPM0_CH4_PTA16 KINETIS_MUX('A',16,5) /* PTA_16 */ +#define LPUART0_RX_PTA16 KINETIS_MUX('A',16,6) /* PTA_16 */ +#define RF_GPO_8_PTA16 KINETIS_MUX('A',16,7) /* PTA_16 */ +#define FLEXIO0_D5_PTA16 KINETIS_MUX('A',16,9) /* PTA_16 */ +#define ADC0_A13_PTA17 KINETIS_MUX('A',17,0) /* PTA_17 */ +#define WUU0_P3_PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define RF_NOT_ALLOWED_PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define PTA17 KINETIS_MUX('A',17,1) /* PTA_17 */ +#define LPSPI0_SIN_PTA17 KINETIS_MUX('A',17,2) /* PTA_17 */ +#define EWM0_IN_PTA17 KINETIS_MUX('A',17,3) /* PTA_17 */ +#define LPI2C0_SDAS_PTA17 KINETIS_MUX('A',17,4) /* PTA_17 */ +#define TPM0_CH5_PTA17 KINETIS_MUX('A',17,5) /* PTA_17 */ +#define LPUART0_TX_PTA17 KINETIS_MUX('A',17,6) /* PTA_17 */ +#define RF_GPO_7_PTA17 KINETIS_MUX('A',17,7) /* PTA_17 */ +#define RF_GPO_8_PTA17 KINETIS_MUX('A',17,8) /* PTA_17 */ +#define FLEXIO0_D6_PTA17 KINETIS_MUX('A',17,9) /* PTA_17 */ +#define RF_EXT_XTAL_REQUEST_PTA17 KINETIS_MUX('A',17,11) /* PTA_17 */ +#define CMP1_IN1_PTA18 KINETIS_MUX('A',18,0) /* PTA_18 */ +#define PTA18 KINETIS_MUX('A',18,1) /* PTA_18 */ +#define LPSPI0_SOUT_PTA18 KINETIS_MUX('A',18,2) /* PTA_18 */ +#define LPUART0_CTS_b_PTA18 KINETIS_MUX('A',18,3) /* PTA_18 */ +#define LPI2C0_SDA_PTA18 KINETIS_MUX('A',18,4) /* PTA_18 */ +#define TPM0_CH3_PTA18 KINETIS_MUX('A',18,5) /* PTA_18 */ +#define RF_GPO_0_PTA18 KINETIS_MUX('A',18,6) /* PTA_18 */ +#define LPUART0_RX_PTA18 KINETIS_MUX('A',18,10) /* PTA_18 */ +#define SPC0_LPREQ_PTA18 KINETIS_MUX('A',18,11) /* PTA_18 */ +#define CMP1_IN0_PTA19 KINETIS_MUX('A',19,0) /* PTA_19 */ +#define PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define WUU0_P4_PTA19 KINETIS_MUX('A',19,1) /* PTA_19 */ +#define LPSPI0_SCK_PTA19 KINETIS_MUX('A',19,2) /* PTA_19 */ +#define LPUART0_RTS_b_PTA19 KINETIS_MUX('A',19,3) /* PTA_19 */ +#define LPI2C0_SCL_PTA19 KINETIS_MUX('A',19,4) /* PTA_19 */ +#define TPM0_CH2_PTA19 KINETIS_MUX('A',19,5) /* PTA_19 */ +#define RF_GPO_1_PTA19 KINETIS_MUX('A',19,6) /* PTA_19 */ +#define CMP0_IN3_PTA20 KINETIS_MUX('A',20,0) /* PTA_20 */ +#define ADC0_A14_PTA20 KINETIS_MUX('A',20,0) /* PTA_20 */ +#define PTA20 KINETIS_MUX('A',20,1) /* PTA_20 */ +#define LPSPI0_PCS2_PTA20 KINETIS_MUX('A',20,2) /* PTA_20 */ +#define LPUART0_TX_PTA20 KINETIS_MUX('A',20,3) /* PTA_20 */ +#define EWM0_IN_PTA20 KINETIS_MUX('A',20,4) /* PTA_20 */ +#define TPM0_CH1_PTA20 KINETIS_MUX('A',20,5) /* PTA_20 */ +#define RF_GPO_2_PTA20 KINETIS_MUX('A',20,6) /* PTA_20 */ +#define FLEXIO0_D7_PTA20 KINETIS_MUX('A',20,8) /* PTA_20 */ +#define ADC0_A15_PTA21 KINETIS_MUX('A',21,0) /* PTA_21 */ +#define CMP0_IN2_PTA21 KINETIS_MUX('A',21,0) /* PTA_21 */ +#define WUU0_P5_PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define PTA21 KINETIS_MUX('A',21,1) /* PTA_21 */ +#define LPSPI0_PCS3_PTA21 KINETIS_MUX('A',21,2) /* PTA_21 */ +#define LPUART0_RX_PTA21 KINETIS_MUX('A',21,3) /* PTA_21 */ +#define EWM0_OUT_b_PTA21 KINETIS_MUX('A',21,4) /* PTA_21 */ +#define TPM0_CH0_PTA21 KINETIS_MUX('A',21,5) /* PTA_21 */ +#define RF_GPO_3_PTA21 KINETIS_MUX('A',21,6) /* PTA_21 */ +#define RF_GPO_7_PTA21 KINETIS_MUX('A',21,7) /* PTA_21 */ +#define FLEXIO0_D8_PTA21 KINETIS_MUX('A',21,8) /* PTA_21 */ +#define RF_GPO_10_PTA21 KINETIS_MUX('A',21,9) /* PTA_21 */ +#define ADC0_B10_PTB0 KINETIS_MUX('B',0,0) /* PTB_0 */ +#define PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define WUU0_P13_PTB0 KINETIS_MUX('B',0,1) /* PTB_0 */ +#define LPSPI1_PCS0_PTB0 KINETIS_MUX('B',0,2) /* PTB_0 */ +#define TPM1_CH0_PTB0 KINETIS_MUX('B',0,5) /* PTB_0 */ +#define FLEXIO0_D26_PTB0 KINETIS_MUX('B',0,9) /* PTB_0 */ +#define ADC0_B11_PTB1 KINETIS_MUX('B',1,0) /* PTB_1 */ +#define PTB1 KINETIS_MUX('B',1,1) /* PTB_1 */ +#define LPSPI1_SIN_PTB1 KINETIS_MUX('B',1,2) /* PTB_1 */ +#define TPM1_CH1_PTB1 KINETIS_MUX('B',1,5) /* PTB_1 */ +#define FLEXIO0_D27_PTB1 KINETIS_MUX('B',1,9) /* PTB_1 */ +#define ADC0_B12_PTB2 KINETIS_MUX('B',2,0) /* PTB_2 */ +#define PTB2 KINETIS_MUX('B',2,1) /* PTB_2 */ +#define LPSPI1_SCK_PTB2 KINETIS_MUX('B',2,2) /* PTB_2 */ +#define LPUART1_TX_PTB2 KINETIS_MUX('B',2,3) /* PTB_2 */ +#define TPM1_CH2_PTB2 KINETIS_MUX('B',2,5) /* PTB_2 */ +#define FLEXIO0_D28_PTB2 KINETIS_MUX('B',2,9) /* PTB_2 */ +#define ADC0_B13_PTB3 KINETIS_MUX('B',3,0) /* PTB_3 */ +#define PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define WUU0_P14_PTB3 KINETIS_MUX('B',3,1) /* PTB_3 */ +#define LPSPI1_SOUT_PTB3 KINETIS_MUX('B',3,2) /* PTB_3 */ +#define LPUART1_RX_PTB3 KINETIS_MUX('B',3,3) /* PTB_3 */ +#define TPM1_CH3_PTB3 KINETIS_MUX('B',3,5) /* PTB_3 */ +#define FLEXIO0_D29_PTB3 KINETIS_MUX('B',3,9) /* PTB_3 */ +#define PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define WUU0_P15_PTB4 KINETIS_MUX('B',4,1) /* PTB_4 */ +#define LPSPI1_PCS3_PTB4 KINETIS_MUX('B',4,2) /* PTB_4 */ +#define LPUART1_CTS_b_PTB4 KINETIS_MUX('B',4,3) /* PTB_4 */ +#define LPI2C1_SDA_PTB4 KINETIS_MUX('B',4,4) /* PTB_4 */ +#define I3C0_SDA_PTB4 KINETIS_MUX('B',4,5) /* PTB_4 */ +#define TRGMUX0_IN0_PTB4 KINETIS_MUX('B',4,6) /* PTB_4 */ +#define FLEXIO0_D30_PTB4 KINETIS_MUX('B',4,9) /* PTB_4 */ +#define PTB5 KINETIS_MUX('B',5,1) /* PTB_5 */ +#define LPSPI1_PCS2_PTB5 KINETIS_MUX('B',5,2) /* PTB_5 */ +#define LPUART1_RTS_b_PTB5 KINETIS_MUX('B',5,3) /* PTB_5 */ +#define LPI2C1_SCL_PTB5 KINETIS_MUX('B',5,4) /* PTB_5 */ +#define I3C0_SCL_PTB5 KINETIS_MUX('B',5,5) /* PTB_5 */ +#define TRGMUX0_OUT0_PTB5 KINETIS_MUX('B',5,6) /* PTB_5 */ +#define FLEXIO0_D31_PTB5 KINETIS_MUX('B',5,9) /* PTB_5 */ +#define PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define WUU0_P7_PTC0 KINETIS_MUX('C',0,1) /* PTC_0 */ +#define LPSPI1_PCS2_PTC0 KINETIS_MUX('C',0,2) /* PTC_0 */ +#define I3C0_SDA_PTC0 KINETIS_MUX('C',0,4) /* PTC_0 */ +#define TPM1_CH0_PTC0 KINETIS_MUX('C',0,5) /* PTC_0 */ +#define LPI2C1_SCL_PTC0 KINETIS_MUX('C',0,7) /* PTC_0 */ +#define FLEXIO0_D16_PTC0 KINETIS_MUX('C',0,9) /* PTC_0 */ +#define PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define WUU0_P8_PTC1 KINETIS_MUX('C',1,1) /* PTC_1 */ +#define LPSPI1_PCS3_PTC1 KINETIS_MUX('C',1,2) /* PTC_1 */ +#define I3C0_SCL_PTC1 KINETIS_MUX('C',1,4) /* PTC_1 */ +#define TPM1_CH1_PTC1 KINETIS_MUX('C',1,5) /* PTC_1 */ +#define LPI2C1_SDA_PTC1 KINETIS_MUX('C',1,7) /* PTC_1 */ +#define FLEXIO0_D17_PTC1 KINETIS_MUX('C',1,9) /* PTC_1 */ +#define PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define WUU0_P9_PTC2 KINETIS_MUX('C',2,1) /* PTC_2 */ +#define LPSPI1_SOUT_PTC2 KINETIS_MUX('C',2,2) /* PTC_2 */ +#define LPUART1_RX_PTC2 KINETIS_MUX('C',2,3) /* PTC_2 */ +#define LPI2C1_SCLS_PTC2 KINETIS_MUX('C',2,4) /* PTC_2 */ +#define TPM1_CH2_PTC2 KINETIS_MUX('C',2,5) /* PTC_2 */ +#define I3C0_PUR_PTC2 KINETIS_MUX('C',2,7) /* PTC_2 */ +#define FLEXIO0_D18_PTC2 KINETIS_MUX('C',2,9) /* PTC_2 */ +#define PTC3 KINETIS_MUX('C',3,1) /* PTC_3 */ +#define LPSPI1_SCK_PTC3 KINETIS_MUX('C',3,2) /* PTC_3 */ +#define LPUART1_TX_PTC3 KINETIS_MUX('C',3,3) /* PTC_3 */ +#define LPI2C1_SDAS_PTC3 KINETIS_MUX('C',3,4) /* PTC_3 */ +#define TPM1_CH3_PTC3 KINETIS_MUX('C',3,5) /* PTC_3 */ +#define FLEXIO0_D19_PTC3 KINETIS_MUX('C',3,9) /* PTC_3 */ +#define WUU0_P10_PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define PTC4 KINETIS_MUX('C',4,1) /* PTC_4 */ +#define LPSPI1_SIN_PTC4 KINETIS_MUX('C',4,2) /* PTC_4 */ +#define LPI2C1_SCL_PTC4 KINETIS_MUX('C',4,4) /* PTC_4 */ +#define TPM2_CH0_PTC4 KINETIS_MUX('C',4,6) /* PTC_4 */ +#define FLEXIO0_D20_PTC4 KINETIS_MUX('C',4,9) /* PTC_4 */ +#define PTC5 KINETIS_MUX('C',5,1) /* PTC_5 */ +#define LPSPI1_PCS0_PTC5 KINETIS_MUX('C',5,2) /* PTC_5 */ +#define LPI2C1_SDA_PTC5 KINETIS_MUX('C',5,4) /* PTC_5 */ +#define TPM1_CH4_PTC5 KINETIS_MUX('C',5,5) /* PTC_5 */ +#define TPM2_CH1_PTC5 KINETIS_MUX('C',5,6) /* PTC_5 */ +#define FLEXIO0_D21_PTC5 KINETIS_MUX('C',5,9) /* PTC_5 */ +#define ADC0_A8_PTC6 KINETIS_MUX('C',6,0) /* PTC_6 */ +#define PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define WUU0_P11_PTC6 KINETIS_MUX('C',6,1) /* PTC_6 */ +#define LPSPI1_PCS1_PTC6 KINETIS_MUX('C',6,2) /* PTC_6 */ +#define TPM1_CH5_PTC6 KINETIS_MUX('C',6,5) /* PTC_6 */ +#define FLEXIO0_D22_PTC6 KINETIS_MUX('C',6,9) /* PTC_6 */ +#define PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define NMI_b_PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define RF_NOT_ALLOWED_PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define WUU0_P12_PTC7 KINETIS_MUX('C',7,1) /* PTC_7 */ +#define TRGMUX0_IN3_PTC7 KINETIS_MUX('C',7,2) /* PTC_7 */ +#define TRGMUX0_OUT3_PTC7 KINETIS_MUX('C',7,3) /* PTC_7 */ +#define SFA0_CLK_PTC7 KINETIS_MUX('C',7,4) /* PTC_7 */ +#define TPM1_CLKIN_PTC7 KINETIS_MUX('C',7,5) /* PTC_7 */ +#define TPM2_CLKIN_PTC7 KINETIS_MUX('C',7,6) /* PTC_7 */ +#define CLKOUT_PTC7 KINETIS_MUX('C',7,7) /* PTC_7 */ +#define FLEXIO0_D23_PTC7 KINETIS_MUX('C',7,9) /* PTC_7 */ +#define ADC0_A5_PTD0 KINETIS_MUX('D',0,0) /* PTD_0 */ +#define PTD0 KINETIS_MUX('D',0,1) /* PTD_0 */ +#define RESET_b_PTD0 KINETIS_MUX('D',0,3) /* PTD_0 */ +#define ADC0_B5_PTD1 KINETIS_MUX('D',1,0) /* PTD_1 */ +#define PTD1 KINETIS_MUX('D',1,1) /* PTD_1 */ +#define SPC0_LPREQ_PTD1 KINETIS_MUX('D',1,2) /* PTD_1 */ +#define NMI_b_PTD1 KINETIS_MUX('D',1,3) /* PTD_1 */ +#define RF_GPO_4_PTD1 KINETIS_MUX('D',1,4) /* PTD_1 */ +#define ADC0_A6_PTD2 KINETIS_MUX('D',2,0) /* PTD_2 */ +#define PTD2 KINETIS_MUX('D',2,1) /* PTD_2 */ +#define LPTMR0_ALT3_PTD2 KINETIS_MUX('D',2,2) /* PTD_2 */ +#define TAMPER0_PTD2 KINETIS_MUX('D',2,3) /* PTD_2 */ +#define RF_GPO_5_PTD2 KINETIS_MUX('D',2,4) /* PTD_2 */ +#define ADC0_B6_PTD3 KINETIS_MUX('D',3,0) /* PTD_3 */ +#define PTD3 KINETIS_MUX('D',3,1) /* PTD_3 */ +#define LPTMR1_ALT3_PTD3 KINETIS_MUX('D',3,2) /* PTD_3 */ +#define TAMPER1_PTD3 KINETIS_MUX('D',3,3) /* PTD_3 */ +#define RF_GPO_6_PTD3 KINETIS_MUX('D',3,4) /* PTD_3 */ +#define TRGMUX0_IN2_PTD3 KINETIS_MUX('D',3,6) /* PTD_3 */ +#define XTAL32K_PTD4 KINETIS_MUX('D',4,0) /* PTD_4 */ +#define PTD4 KINETIS_MUX('D',4,1) /* PTD_4 */ +#define LPTMR0_ALT2_PTD4 KINETIS_MUX('D',4,2) /* PTD_4 */ +#define TAMPER2_PTD4 KINETIS_MUX('D',4,3) /* PTD_4 */ +#define EXTAL32K_PTD5 KINETIS_MUX('D',5,0) /* PTD_5 */ +#define PTD5 KINETIS_MUX('D',5,1) /* PTD_5 */ +#define LPTMR1_ALT2_PTD5 KINETIS_MUX('D',5,2) /* PTD_5 */ +#endif diff --git a/dts/nxp/nxp_imx/mimx8md6cvahz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8md6cvahz-pinctrl.dtsi new file mode 100644 index 000000000..f8b33fdab --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8md6cvahz-pinctrl.dtsi @@ -0,0 +1,1489 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MD6CVAHZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_I2C4_SDA_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330230 2 0x30330528 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_snvs_rtc_snvs_rtc: IOMUXC_RTC_SNVS_RTC_SNVS_RTC { + pinmux = <0x0 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_capture_gpt1_capture2: IOMUXC_SAI3_RXC_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_clk_gpt1_clk: IOMUXC_SAI3_TXFS_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai4_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI4_MCLK { + pinmux = <0x30330158 2 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_UART4_TXD_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330250 2 0x30330528 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8md6dvajz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8md6dvajz-pinctrl.dtsi new file mode 100644 index 000000000..294d89e92 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8md6dvajz-pinctrl.dtsi @@ -0,0 +1,1489 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MD6DVAJZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_I2C4_SDA_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330230 2 0x30330528 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_snvs_rtc_snvs_rtc: IOMUXC_RTC_SNVS_RTC_SNVS_RTC { + pinmux = <0x0 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_capture_gpt1_capture2: IOMUXC_SAI3_RXC_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_clk_gpt1_clk: IOMUXC_SAI3_TXFS_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai4_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI4_MCLK { + pinmux = <0x30330158 2 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_UART4_TXD_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330250 2 0x30330528 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8md7cvahz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8md7cvahz-pinctrl.dtsi new file mode 100644 index 000000000..a34e044e5 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8md7cvahz-pinctrl.dtsi @@ -0,0 +1,1489 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MD7CVAHZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_I2C4_SDA_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330230 2 0x30330528 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_snvs_rtc_snvs_rtc: IOMUXC_RTC_SNVS_RTC_SNVS_RTC { + pinmux = <0x0 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_capture_gpt1_capture2: IOMUXC_SAI3_RXC_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_clk_gpt1_clk: IOMUXC_SAI3_TXFS_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai4_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI4_MCLK { + pinmux = <0x30330158 2 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_UART4_TXD_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330250 2 0x30330528 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8md7dvajz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8md7dvajz-pinctrl.dtsi new file mode 100644 index 000000000..fd8ccb3e8 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8md7dvajz-pinctrl.dtsi @@ -0,0 +1,1489 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MD7DVAJZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_I2C4_SDA_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330230 2 0x30330528 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_snvs_rtc_snvs_rtc: IOMUXC_RTC_SNVS_RTC_SNVS_RTC { + pinmux = <0x0 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_capture_gpt1_capture2: IOMUXC_SAI3_RXC_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_clk_gpt1_clk: IOMUXC_SAI3_TXFS_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai4_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI4_MCLK { + pinmux = <0x30330158 2 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_UART4_TXD_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330250 2 0x30330528 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8ml6cvnkz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8ml6cvnkz-pinctrl.dtsi new file mode 100644 index 000000000..a78d26608 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8ml6cvnkz-pinctrl.dtsi @@ -0,0 +1,2404 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8ML6CVNKZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330250>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301e8 0 0x3033055c 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301e8 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301e8 2 0x303305ac 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai7_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x303301e8 3 0x30330534 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301e8 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301e8 1 0x303305f4 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301e4 0 0x30330560 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301e4 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301e4 2 0x303305a8 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x303301e4 3 0x30330530 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301e4 1 0x303305f8 5 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301e4 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301e0 0 0x30330558 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301e0 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301e0 2 0x303305a4 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai7_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x303301e0 3 0x30330538 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301e0 1 0x303305f8 4 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301e0 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x303301ec 0 0x30330564 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x303301ec 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x303301ec 2 0x303305b0 1 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai7_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x303301ec 3 0x30330540 1 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303301ec 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303301ec 1 0x303305f4 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ccm_clko_ccm_clko1: IOMUXC_ECSPI2_MISO_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x303301f8 4 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303301f8 0 0x3033056c 1 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x303301f8 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x303301f8 2 0x303305bc 4 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai7_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI7_MCLK { + pinmux = <0x303301f8 3 0x3033052c 1 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x303301f8 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x303301f8 1 0x303305fc 2 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303301f4 0 0x30330570 1 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x303301f4 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x303301f4 2 0x303305b8 3 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai7_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x303301f4 3 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x303301f4 1 0x30330600 7 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x303301f4 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303301f0 0 0x30330568 1 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x303301f0 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x303301f0 2 0x303305b4 3 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x303301f0 3 0x3033053c 1 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x303301f0 1 0x30330600 6 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x303301f0 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ccm_clko_ccm_clko2: IOMUXC_ECSPI2_SS0_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x303301fc 4 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303301fc 0 0x30330574 1 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x303301fc 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x303301fc 2 0x303305c0 4 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x303301fc 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x303301fc 1 0x303305fc 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC_ENET_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x30330054 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330054 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330054 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330054 6 0x30330630 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC_ENET_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x30330058 0 0x30330590 1 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x30330058 5 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330058 3 0x303304cc 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x30330058 2 0x30330528 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330058 6 0x30330624 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC_ENET_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x3033007c 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x303304c4 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x3033007c 2 0x30330534 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x3033007c 6 0x30330620 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC_ENET_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x30330080 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330080 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330080 3 0x303304c0 1 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330080 2 0x30330538 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330080 6 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC_ENET_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x30330084 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330084 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330084 3 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330084 2 0x30330530 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330084 6 0x30330604 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC_ENET_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x30330088 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x30330088 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x30330088 2 0x3033052c 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x30330088 3 0x30330544 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x30330088 6 0x3033060c 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_qos_rgmii_rxc_enet_qos_rgmii_rxc: IOMUXC_ENET_RXC_ENET_QOS_RGMII_RXC_ENET_QOS_RGMII_RXC { + pinmux = <0x30330078 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC_ENET_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x30330078 1 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x30330078 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x303304c8 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x30330078 2 0x3033053c 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330078 6 0x3033061c 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x30330074 0 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330074 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x303304cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330074 2 0x30330540 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330074 6 0x30330618 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC_ENET_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x30330068 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x30330068 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_clk_pdm_clk: IOMUXC_ENET_TD0_PDM_CLK_PDM_CLK { + pinmux = <0x30330068 3 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330068 2 0x30330518 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x30330068 6 0x30330634 1 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC_ENET_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x30330064 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330064 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330064 3 0x303304c0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330064 2 0x30330520 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330064 6 0x30330608 1 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC_ENET_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x30330060 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_qos_tx_clk_enet_qos_tx_clk: IOMUXC_ENET_TD2_ENET_QOS_TX_CLK_ENET_QOS_TX_CLK { + pinmux = <0x30330060 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330060 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330060 3 0x303304c4 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330060 2 0x3033051c 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330060 6 0x3033062c 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC_ENET_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x3033005c 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x3033005c 5 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033005c 3 0x303304c8 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033005c 2 0x30330524 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x3033005c 6 0x30330628 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_qos_rgmii_txc_enet_qos_rgmii_txc: IOMUXC_ENET_TXC_ENET_QOS_RGMII_TXC_ENET_QOS_RGMII_TXC { + pinmux = <0x30330070 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC_ENET_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x30330070 1 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330070 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330070 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330070 6 0x30330614 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x3033006c 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x3033006c 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x3033006c 2 0x30330514 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_spdif_out_spdif1_out: IOMUXC_ENET_TX_CTL_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x3033006c 3 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033006c 6 0x30330610 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330014 1 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330014 6 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330014 5 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330014 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_isp_fl_trig_isp_fl_trig_0: IOMUXC_GPIO1_IO00_ISP_FL_TRIG_ISP_FL_TRIG_0 { + pinmux = <0x30330014 3 0x303305d4 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x30330018 6 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x30330018 5 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x30330018 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_isp_shutter_trig_isp_shutter_trig_0: IOMUXC_GPIO1_IO01_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_0 { + pinmux = <0x30330018 3 0x303305dc 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x30330018 1 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x3033001c 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_isp_flash_trig_isp_flash_trig_0: IOMUXC_GPIO1_IO02_ISP_FLASH_TRIG_ISP_FLASH_TRIG_0 { + pinmux = <0x3033001c 3 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x3033001c 7 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x3033001c 5 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x3033001c 1 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330020 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_isp_prelight_trig_isp_prelight_trig_0: IOMUXC_GPIO1_IO03_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_0 { + pinmux = <0x30330020 3 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330020 5 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330020 1 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330024 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_isp_shutter_open_isp_shutter_open_0: IOMUXC_GPIO1_IO04_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_0 { + pinmux = <0x30330024 3 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330024 5 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330024 1 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330028 5 0x30330554 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x30330028 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_isp_fl_trig_isp_fl_trig_1: IOMUXC_GPIO1_IO05_ISP_FL_TRIG_ISP_FL_TRIG_1 { + pinmux = <0x30330028 3 0x303305d8 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x30330028 1 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x3033002c 6 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_qos_mdc_enet_qos_mdc: IOMUXC_GPIO1_IO06_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x3033002c 1 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x3033002c 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_isp_shutter_trig_isp_shutter_trig_1: IOMUXC_GPIO1_IO06_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_1 { + pinmux = <0x3033002c 3 0x303305e0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x3033002c 5 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330030 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_qos_mdio_enet_qos_mdio: IOMUXC_GPIO1_IO07_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x30330030 1 0x30330590 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330030 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_isp_flash_trig_isp_flash_trig_1: IOMUXC_GPIO1_IO07_ISP_FLASH_TRIG_ISP_FLASH_TRIG_1 { + pinmux = <0x30330030 3 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330030 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_qos_1588_event0_aux_in_enet_qos_1588_event0_aux_in: IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_AUX_IN_ENET_QOS_1588_EVENT0_AUX_IN { + pinmux = <0x30330034 4 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x30330034 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330034 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_isp_prelight_trig_isp_prelight_trig_1: IOMUXC_GPIO1_IO08_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_1 { + pinmux = <0x30330034 3 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330034 2 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330034 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x30330038 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x30330038 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_isp_shutter_open_isp_shutter_open_1: IOMUXC_GPIO1_IO09_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_1 { + pinmux = <0x30330038 3 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x30330038 2 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x30330038 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330038 4 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x3033003c 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x3033003c 2 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_id_usb1_id: IOMUXC_GPIO1_IO10_USB_ID_USB1_ID { + pinmux = <0x3033003c 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330040 5 0x30330554 1 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330040 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330040 2 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_id_usb2_id: IOMUXC_GPIO1_IO11_USB_ID_USB2_ID { + pinmux = <0x30330040 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330040 4 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330044 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330044 5 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_pwr_usb1_pwr: IOMUXC_GPIO1_IO12_USB_PWR_USB1_PWR { + pinmux = <0x30330044 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x30330048 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x30330048 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_oc_usb1_oc: IOMUXC_GPIO1_IO13_USB_OC_USB1_OC { + pinmux = <0x30330048 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x3033004c 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x3033004c 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x3033004c 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_pwr_usb2_pwr: IOMUXC_GPIO1_IO14_USB_PWR_USB2_PWR { + pinmux = <0x3033004c 1 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033004c 4 0x30330608 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330050 6 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330050 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330050 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_oc_usb2_oc: IOMUXC_GPIO1_IO15_USB_OC_USB2_OC { + pinmux = <0x30330050 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330050 4 0x30330634 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_can_tx_can2_tx: IOMUXC_HDMI_CEC_CAN_TX_CAN2_TX { + pinmux = <0x30330248 4 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_gpio_io_gpio3_io28: IOMUXC_HDMI_CEC_GPIO_IO_GPIO3_IO28 { + pinmux = <0x30330248 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_hdmi_cec_hdmi_cec: IOMUXC_HDMI_CEC_HDMI_CEC_HDMI_CEC { + pinmux = <0x30330248 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_i2c_scl_i2c6_scl: IOMUXC_HDMI_CEC_I2C_SCL_I2C6_SCL { + pinmux = <0x30330248 3 0x303305cc 3 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_can_tx_can1_tx: IOMUXC_HDMI_DDC_SCL_CAN_TX_CAN1_TX { + pinmux = <0x30330240 4 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_gpio_io_gpio3_io26: IOMUXC_HDMI_DDC_SCL_GPIO_IO_GPIO3_IO26 { + pinmux = <0x30330240 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_hdmi_scl_hdmi_scl: IOMUXC_HDMI_DDC_SCL_HDMI_SCL_HDMI_SCL { + pinmux = <0x30330240 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_i2c_scl_i2c5_scl: IOMUXC_HDMI_DDC_SCL_I2C_SCL_I2C5_SCL { + pinmux = <0x30330240 3 0x303305c4 3 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_can_rx_can1_rx: IOMUXC_HDMI_DDC_SDA_CAN_RX_CAN1_RX { + pinmux = <0x30330244 4 0x3033054c 3 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_gpio_io_gpio3_io27: IOMUXC_HDMI_DDC_SDA_GPIO_IO_GPIO3_IO27 { + pinmux = <0x30330244 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_hdmi_sda_hdmi_sda: IOMUXC_HDMI_DDC_SDA_HDMI_SDA_HDMI_SDA { + pinmux = <0x30330244 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_i2c_sda_i2c5_sda: IOMUXC_HDMI_DDC_SDA_I2C_SDA_I2C5_SDA { + pinmux = <0x30330244 3 0x303305c8 3 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_can_rx_can2_rx: IOMUXC_HDMI_HPD_CAN_RX_CAN2_RX { + pinmux = <0x3033024c 4 0x30330550 3 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_gpio_io_gpio3_io29: IOMUXC_HDMI_HPD_GPIO_IO_GPIO3_IO29 { + pinmux = <0x3033024c 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_hdmi_hpd_hdmi_hpd: IOMUXC_HDMI_HPD_HDMI_HPD_HDMI_HPD { + pinmux = <0x3033024c 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_hdmi_hpd_o_hdmi_hpd_o: IOMUXC_HDMI_HPD_HDMI_HPD_O_HDMI_HPD_O { + pinmux = <0x3033024c 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_i2c_sda_i2c6_sda: IOMUXC_HDMI_HPD_I2C_SDA_I2C6_SDA { + pinmux = <0x3033024c 3 0x303305d0 3 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330200 3 0x30330558 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_qos_mdc_enet_qos_mdc: IOMUXC_I2C1_SCL_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x30330200 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330200 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330200 0 0x303305a4 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330204 3 0x30330560 1 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_qos_mdio_enet_qos_mdio: IOMUXC_I2C1_SDA_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x30330204 1 0x30330590 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330204 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330204 0 0x303305a8 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x30330208 3 0x3033055c 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_qos_1588_event1_aux_in_enet_qos_1588_event1_aux_in: IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_AUX_IN_ENET_QOS_1588_EVENT1_AUX_IN { + pinmux = <0x30330208 4 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_qos_1588_event1_in_enet_qos_1588_event1_in: IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_IN_ENET_QOS_1588_EVENT1_IN { + pinmux = <0x30330208 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x30330208 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x30330208 0 0x303305ac 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330208 2 0x30330608 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x3033020c 3 0x30330564 1 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_qos_1588_event1_out_enet_qos_1588_event1_out: IOMUXC_I2C2_SDA_ENET_QOS_1588_EVENT1_OUT_ENET_QOS_1588_EVENT1_OUT { + pinmux = <0x3033020c 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x3033020c 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x3033020c 0 0x303305b0 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x3033020c 2 0x30330634 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330210 3 0x30330568 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330210 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330210 2 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330210 0 0x303305b4 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330210 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330214 3 0x30330570 2 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330214 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330214 2 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330214 0 0x303305b8 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330214 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x30330218 3 0x3033056c 2 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x30330218 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x30330218 0 0x303305bc 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x30330218 2 0x303305a0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x30330218 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x3033021c 3 0x30330574 2 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x3033021c 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x3033021c 0 0x303305c0 5 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x3033021c 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300e0 6 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300e0 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_isp_fl_trig_isp_fl_trig_0: IOMUXC_NAND_ALE_ISP_FL_TRIG_ISP_FL_TRIG_0 { + pinmux = <0x303300e0 3 0x303305d4 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300e0 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300e0 1 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_sai_tx_bclk_sai3_tx_bclk: IOMUXC_NAND_ALE_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303300e0 2 0x303304e8 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300e0 4 0x303305f8 2 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300e0 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300e4 6 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300e4 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_isp_shutter_trig_isp_shutter_trig_0: IOMUXC_NAND_CE0_B_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_0 { + pinmux = <0x303300e4 3 0x303305dc 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300e4 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300e4 1 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_sai_tx_data_sai3_tx_data0: IOMUXC_NAND_CE0_B_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303300e4 2 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300e4 4 0x303305f8 3 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300e4 4 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300e8 6 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300e8 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e8 4 0x303305bc 2 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300e8 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300e8 1 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300e8 2 0x30330630 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x303300ec 6 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x303300ec 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x303300ec 4 0x303305c0 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x303300ec 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x303300ec 1 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x303300ec 2 0x30330624 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x303300f0 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x303300f0 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x303300f0 4 0x303305b8 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x303300f0 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x303300f0 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x303300f0 2 0x30330628 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x303300f4 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x303300f4 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x303300f4 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_uart_rx_uart4_rx: IOMUXC_NAND_CLE_UART_RX_UART4_RX { + pinmux = <0x303300f4 4 0x30330600 2 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_uart_tx_uart4_rx: IOMUXC_NAND_CLE_UART_TX_UART4_RX { + pinmux = <0x303300f4 4 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x303300f4 2 0x3033062c 1 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x303300f8 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x303300f8 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_isp_flash_trig_isp_flash_trig_0: IOMUXC_NAND_DATA00_ISP_FLASH_TRIG_ISP_FLASH_TRIG_0 { + pinmux = <0x303300f8 3 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x303300f8 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x303300f8 1 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_sai_rx_data_sai3_rx_data0: IOMUXC_NAND_DATA00_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303300f8 2 0x303304e4 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x303300f8 4 0x30330600 3 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x303300f8 4 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x303300fc 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x303300fc 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_isp_prelight_trig_isp_prelight_trig_0: IOMUXC_NAND_DATA01_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_0 { + pinmux = <0x303300fc 3 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x303300fc 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x303300fc 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_sai_tx_sync_sai3_tx_sync: IOMUXC_NAND_DATA01_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303300fc 2 0x303304ec 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x303300fc 4 0x30330600 4 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x303300fc 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330100 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330100 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x303305c0 3 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330100 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330100 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_uart_cts_b_uart4_cts_b: IOMUXC_NAND_DATA02_UART_CTS_B_UART4_CTS_B { + pinmux = <0x30330100 3 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_uart_rts_b_uart4_cts_b: IOMUXC_NAND_DATA02_UART_RTS_B_UART4_CTS_B { + pinmux = <0x30330100 3 0x303305fc 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330100 2 0x30330608 2 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330104 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330104 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_isp_fl_trig_isp_fl_trig_1: IOMUXC_NAND_DATA03_ISP_FL_TRIG_ISP_FL_TRIG_1 { + pinmux = <0x30330104 4 0x303305d8 1 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330104 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330104 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_uart_cts_b_uart4_rts_b: IOMUXC_NAND_DATA03_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330104 3 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_uart_rts_b_uart4_rts_b: IOMUXC_NAND_DATA03_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330104 3 0x303305fc 1 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330104 2 0x30330634 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x30330108 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x30330108 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_isp_shutter_trig_isp_shutter_trig_1: IOMUXC_NAND_DATA04_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_1 { + pinmux = <0x30330108 4 0x303305e0 1 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x30330108 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_a_data_qspi_a_data4: IOMUXC_NAND_DATA04_QSPI_A_DATA_QSPI_A_DATA4 { + pinmux = <0x30330108 3 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x30330108 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330108 2 0x30330610 1 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x3033010c 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x3033010c 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_isp_flash_trig_isp_flash_trig_1: IOMUXC_NAND_DATA05_ISP_FLASH_TRIG_ISP_FLASH_TRIG_1 { + pinmux = <0x3033010c 4 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x3033010c 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_a_data_qspi_a_data5: IOMUXC_NAND_DATA05_QSPI_A_DATA_QSPI_A_DATA5 { + pinmux = <0x3033010c 3 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x3033010c 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x3033010c 2 0x30330614 1 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330110 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330110 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_isp_prelight_trig_isp_prelight_trig_1: IOMUXC_NAND_DATA06_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_1 { + pinmux = <0x30330110 4 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330110 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_a_data_qspi_a_data6: IOMUXC_NAND_DATA06_QSPI_A_DATA_QSPI_A_DATA6 { + pinmux = <0x30330110 3 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330110 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330110 2 0x30330618 1 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330114 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330114 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_isp_shutter_open_isp_shutter_open_1: IOMUXC_NAND_DATA07_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_1 { + pinmux = <0x30330114 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330114 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_a_data_qspi_a_data7: IOMUXC_NAND_DATA07_QSPI_A_DATA_QSPI_A_DATA7 { + pinmux = <0x30330114 3 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330114 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330114 2 0x3033061c 1 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x30330118 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x30330118 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x30330118 4 0x303305b4 1 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_isp_shutter_open_isp_shutter_open_0: IOMUXC_NAND_DQS_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_0 { + pinmux = <0x30330118 3 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x30330118 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x30330118 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_sai_mclk_sai3_mclk: IOMUXC_NAND_DQS_SAI_MCLK_SAI3_MCLK { + pinmux = <0x30330118 2 0x303304e0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330120 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330120 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330120 4 0x303305b4 2 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330120 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330120 2 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x3033011c 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x3033011c 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x3033011c 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x3033011c 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_uart_rx_uart4_tx: IOMUXC_NAND_RE_B_UART_RX_UART4_TX { + pinmux = <0x3033011c 4 0x30330600 5 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_uart_tx_uart4_tx: IOMUXC_NAND_RE_B_UART_TX_UART4_TX { + pinmux = <0x3033011c 4 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x3033011c 2 0x30330620 1 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330124 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330124 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330124 4 0x303305b8 2 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330124 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330124 2 0x30330604 1 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x30330128 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x30330128 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_scl_i2c4_scl: IOMUXC_NAND_WP_B_I2C_SCL_I2C4_SCL { + pinmux = <0x30330128 4 0x303305bc 3 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x30330128 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x30330128 2 0x3033060c 1 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_enet_tx_clk_enet1_tx_clk: IOMUXC_SAI1_MCLK_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330198 4 0x30330578 1 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x30330198 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x30330198 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330198 2 0x303304d4 2 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_SAI1_RXC_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033014c 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io1: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO1 { + pinmux = <0x3033014c 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_pdm_clk_pdm_clk: IOMUXC_SAI1_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x3033014c 3 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x3033014c 0 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_SAI1_RXD0_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x30330150 4 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io2: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO2 { + pinmux = <0x30330150 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330150 3 0x303304c0 4 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330150 0 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330150 2 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_SAI1_RXD1_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330154 4 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io3: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO3 { + pinmux = <0x30330154 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330154 3 0x303304c4 4 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330154 0 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_enet_mdc_enet1_mdc: IOMUXC_SAI1_RXD2_ENET_MDC_ENET1_MDC { + pinmux = <0x30330158 4 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io4: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO4 { + pinmux = <0x30330158 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330158 3 0x303304c8 4 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x30330158 0 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_enet_mdio_enet1_mdio: IOMUXC_SAI1_RXD3_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033015c 4 0x3033057c 1 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io5: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO5 { + pinmux = <0x3033015c 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x3033015c 3 0x303304cc 4 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x3033015c 0 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SAI1_RXD4_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330160 4 0x30330580 1 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io6: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO6 { + pinmux = <0x30330160 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330160 2 0x30330518 1 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330160 0 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330160 1 0x30330524 1 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SAI1_RXD5_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330164 4 0x30330584 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io7: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO7 { + pinmux = <0x30330164 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330164 0 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330164 2 0x3033051c 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330164 3 0x303304d0 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330164 1 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_SAI1_RXD6_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330168 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io8: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO8 { + pinmux = <0x30330168 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x30330168 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330168 2 0x30330520 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x30330168 1 0x30330528 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_SAI1_RXD7_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033016c 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io9: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO9 { + pinmux = <0x3033016c 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x3033016c 1 0x30330514 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x3033016c 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033016c 3 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033016c 2 0x303304d8 3 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_SAI1_RXFS_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330148 4 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io0: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO0 { + pinmux = <0x30330148 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330148 0 0x303304d0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_SAI1_TXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x30330174 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330174 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330174 0 0x303304d4 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SAI1_TXD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x30330178 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x30330178 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330178 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SAI1_TXD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x3033017c 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x3033017c 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x3033017c 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_SAI1_TXD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330180 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330180 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330180 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_SAI1_TXD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330184 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330184 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330184 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SAI1_TXD4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330188 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x30330188 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330188 1 0x30330518 2 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330188 2 0x30330524 2 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330188 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_SAI1_TXD5_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x3033018c 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x3033018c 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x3033018c 1 0x3033051c 2 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x3033018c 0 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x3033018c 2 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_enet_rx_er_enet1_rx_er: IOMUXC_SAI1_TXD6_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x30330190 4 0x3033058c 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x30330190 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330190 1 0x30330520 2 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x30330190 0 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x30330190 2 0x30330528 2 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_enet_tx_er_enet1_tx_er: IOMUXC_SAI1_TXD7_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330194 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x30330194 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x30330194 3 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330194 1 0x30330514 2 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x30330194 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SAI1_TXFS_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330170 4 0x30330588 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330170 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330170 0 0x303304d8 4 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_can_rx_can2_rx: IOMUXC_SAI2_MCLK_CAN_RX_CAN2_RX { + pinmux = <0x303301b4 3 0x30330550 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_enet_qos_1588_event3_aux_in_enet_qos_1588_event3_aux_in: IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_AUX_IN_ENET_QOS_1588_EVENT3_AUX_IN { + pinmux = <0x303301b4 4 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_enet_qos_1588_event3_in_enet_qos_1588_event3_in: IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_IN_ENET_QOS_1588_EVENT3_IN { + pinmux = <0x303301b4 2 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301b4 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301b4 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301b4 6 0x303304e0 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301b4 1 0x303304f0 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_can_tx_can1_tx: IOMUXC_SAI2_RXC_CAN_TX_CAN1_TX { + pinmux = <0x303301a0 3 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301a0 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301a0 6 0x303304c4 5 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301a0 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301a0 1 0x3033050c 2 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301a0 4 0x303305e8 3 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301a0 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_enet_qos_1588_event2_out_enet_qos_1588_event2_out: IOMUXC_SAI2_RXD0_ENET_QOS_1588_EVENT2_OUT_ENET_QOS_1588_EVENT2_OUT { + pinmux = <0x303301a4 2 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301a4 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301a4 6 0x303304cc 5 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301a4 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301a4 3 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301a4 1 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301a4 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301a4 4 0x303305e4 2 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x3033019c 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033019c 6 0x303304c8 5 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x3033019c 3 0x303304dc 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x3033019c 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x3033019c 2 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033019c 1 0x30330510 2 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x3033019c 4 0x303305e8 2 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x3033019c 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_can_rx_can1_rx: IOMUXC_SAI2_TXC_CAN_RX_CAN1_RX { + pinmux = <0x303301ac 3 0x3033054c 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301ac 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301ac 6 0x303304c4 6 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301ac 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301ac 1 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_can_tx_can2_tx: IOMUXC_SAI2_TXD0_CAN_TX_CAN2_TX { + pinmux = <0x303301b0 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_enet_qos_1588_event2_aux_in_enet_qos_1588_event2_aux_in: IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_AUX_IN_ENET_QOS_1588_EVENT2_AUX_IN { + pinmux = <0x303301b0 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_enet_qos_1588_event2_in_enet_qos_1588_event2_in: IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_IN_ENET_QOS_1588_EVENT2_IN { + pinmux = <0x303301b0 2 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301b0 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301b0 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301b0 1 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_enet_qos_1588_event3_out_enet_qos_1588_event3_out: IOMUXC_SAI2_TXFS_ENET_QOS_1588_EVENT3_OUT_ENET_QOS_1588_EVENT3_OUT { + pinmux = <0x303301a8 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301a8 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301a8 6 0x303304c8 6 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301a8 3 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301a8 1 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301a8 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301a8 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301a8 4 0x303305e4 3 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301d0 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301d0 1 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301d0 0 0x303304e0 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301d0 2 0x303304f0 3 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301d0 6 0x30330544 3 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301d0 4 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301bc 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301bc 3 0x3033059c 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301bc 6 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301bc 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301bc 2 0x303304f4 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data2: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA2 { + pinmux = <0x303301bc 1 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301bc 4 0x303305ec 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301c0 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x303304c4 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai2_rx_data3: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI2_RX_DATA3 { + pinmux = <0x303301c0 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301c0 0 0x303304e4 1 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301c0 2 0x303304f8 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301c0 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301c0 4 0x303305ec 3 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301b8 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301b8 6 0x303304c0 5 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b8 1 0x303304dc 1 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301b8 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301b8 2 0x30330508 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301b8 4 0x30330544 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301c8 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_capture_gpt1_capture1: IOMUXC_SAI3_TXC_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301c8 3 0x30330594 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301c8 6 0x303304c8 7 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301c8 2 0x30330500 2 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301c8 0 0x303304e8 1 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data2: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA2 { + pinmux = <0x303301c8 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301c8 4 0x303305f0 5 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301c8 4 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301cc 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301cc 3 0x30330598 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301cc 2 0x30330504 2 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai2_tx_data3: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI2_TX_DATA3 { + pinmux = <0x303301cc 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301cc 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301cc 4 0x30330548 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301c4 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301c4 6 0x303304cc 6 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301c4 2 0x303304fc 2 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301c4 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301c4 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301c4 0 0x303304ec 1 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301c4 4 0x303305f0 4 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301c4 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_can_rx_can2_rx: IOMUXC_SAI5_MCLK_CAN_RX_CAN2_RX { + pinmux = <0x30330144 6 0x30330550 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330144 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_i2c_sda_i2c5_sda: IOMUXC_SAI5_MCLK_I2C_SDA_I2C5_SDA { + pinmux = <0x30330144 3 0x303305c8 1 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_pwm_out_pwm1_out: IOMUXC_SAI5_MCLK_PWM_OUT_PWM1_OUT { + pinmux = <0x30330144 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330144 0 0x303304f0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330144 1 0x303304d4 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330130 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_i2c_sda_i2c6_sda: IOMUXC_SAI5_RXC_I2C_SDA_I2C6_SDA { + pinmux = <0x30330130 3 0x303305d0 1 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330130 4 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pwm_out_pwm3_out: IOMUXC_SAI5_RXC_PWM_OUT_PWM3_OUT { + pinmux = <0x30330130 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330130 0 0x303304f4 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330130 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330134 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_i2c_scl_i2c5_scl: IOMUXC_SAI5_RXD0_I2C_SCL_I2C5_SCL { + pinmux = <0x30330134 3 0x303305c4 1 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330134 4 0x303304c0 3 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pwm_out_pwm2_out: IOMUXC_SAI5_RXD0_PWM_OUT_PWM2_OUT { + pinmux = <0x30330134 2 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330134 0 0x303304f8 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330134 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_can_tx_can1_tx: IOMUXC_SAI5_RXD1_CAN_TX_CAN1_TX { + pinmux = <0x30330138 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x30330138 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330138 4 0x303304c4 3 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330138 0 0x303304fc 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330138 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330138 2 0x303304d8 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330138 3 0x30330510 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_can_rx_can1_rx: IOMUXC_SAI5_RXD2_CAN_RX_CAN1_RX { + pinmux = <0x3033013c 6 0x3033054c 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x3033013c 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033013c 4 0x303304c8 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033013c 0 0x30330500 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x3033013c 3 0x3033050c 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033013c 1 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033013c 2 0x303304d8 1 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_can_tx_can2_tx: IOMUXC_SAI5_RXD3_CAN_TX_CAN2_TX { + pinmux = <0x30330140 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330140 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330140 4 0x303304cc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330140 0 0x30330504 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330140 1 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330140 3 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330140 2 0x303304d8 2 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x3033012c 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_i2c_scl_i2c6_scl: IOMUXC_SAI5_RXFS_I2C_SCL_I2C6_SCL { + pinmux = <0x3033012c 3 0x303305cc 1 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_pwm_out_pwm4_out: IOMUXC_SAI5_RXFS_PWM_OUT_PWM4_OUT { + pinmux = <0x3033012c 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033012c 0 0x30330508 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033012c 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x3033008c 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x3033008c 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_i2c_scl_i2c5_scl: IOMUXC_SD1_CLK_I2C_SCL_I2C5_SCL { + pinmux = <0x3033008c 3 0x303305c4 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x3033008c 4 0x303305e8 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x3033008c 4 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x3033008c 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330090 1 0x3033057c 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x30330090 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_i2c_sda_i2c5_sda: IOMUXC_SD1_CMD_I2C_SDA_I2C5_SDA { + pinmux = <0x30330090 3 0x303305c8 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x30330090 4 0x303305e8 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x30330090 4 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x30330090 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330094 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x30330094 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_i2c_scl_i2c6_scl: IOMUXC_SD1_DATA0_I2C_SCL_I2C6_SCL { + pinmux = <0x30330094 3 0x303305cc 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330094 4 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330094 4 0x303305e4 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x30330094 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x30330098 1 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x30330098 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_i2c_sda_i2c6_sda: IOMUXC_SD1_DATA1_I2C_SDA_I2C6_SDA { + pinmux = <0x30330098 3 0x303305d0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330098 4 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330098 4 0x303305e4 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x30330098 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x3033009c 1 0x30330580 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x3033009c 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_i2c_scl_i2c4_scl: IOMUXC_SD1_DATA2_I2C_SCL_I2C4_SCL { + pinmux = <0x3033009c 3 0x303305bc 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x3033009c 4 0x303305f0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x3033009c 4 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x3033009c 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300a0 1 0x30330584 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300a0 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_i2c_sda_i2c4_sda: IOMUXC_SD1_DATA3_I2C_SDA_I2C4_SDA { + pinmux = <0x303300a0 3 0x303305c0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300a0 4 0x303305f0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300a0 4 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300a0 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300a4 1 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300a4 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300a4 3 0x303305a4 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300a4 4 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300a4 4 0x303305ec 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300a4 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300a8 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300a8 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300a8 3 0x303305a8 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300a8 4 0x303305ec 1 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300a8 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300ac 1 0x30330588 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300ac 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300ac 3 0x303305ac 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300ac 4 0x303305f8 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300ac 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300ac 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300b0 1 0x3033058c 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300b0 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300b0 3 0x303305b0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300b0 4 0x303305f8 1 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300b0 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300b0 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300b4 1 0x30330578 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300b4 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300b4 3 0x303305b4 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300b4 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300b4 4 0x303305f4 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300b4 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300b8 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300b8 3 0x303305b8 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300b8 4 0x303305f4 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300b8 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300bc 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300bc 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300c0 2 0x30330568 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300c0 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300c0 3 0x30330600 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300c0 3 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300c0 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300c4 2 0x30330570 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300c4 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300c4 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300c4 3 0x30330600 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300c4 3 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300c4 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300c8 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300c8 2 0x303305c0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300c8 4 0x303304c0 2 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300c8 3 0x303305f0 2 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300c8 3 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300c8 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300cc 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300cc 2 0x303305bc 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300cc 4 0x303304c4 2 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300cc 3 0x303305f0 3 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300cc 3 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300cc 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300d0 2 0x30330574 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300d0 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300d0 4 0x303304c8 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300d0 3 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300d0 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300d4 2 0x3033056c 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300d4 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300d4 4 0x303304cc 2 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300d4 3 0x30330544 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300d4 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300d8 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300d8 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300dc 6 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300dc 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300dc 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301dc 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpt_compare_gpt1_compare3: IOMUXC_SPDIF_EXT_CLK_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301dc 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301dc 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301dc 0 0x30330548 1 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_can_rx_can1_rx: IOMUXC_SPDIF_RX_CAN_RX_CAN1_RX { + pinmux = <0x303301d8 4 0x3033054c 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301d8 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpt_compare_gpt1_compare2: IOMUXC_SPDIF_RX_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301d8 3 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_i2c_sda_i2c5_sda: IOMUXC_SPDIF_RX_I2C_SDA_I2C5_SDA { + pinmux = <0x303301d8 2 0x303305c8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301d8 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301d8 0 0x30330544 4 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_can_tx_can1_tx: IOMUXC_SPDIF_TX_CAN_TX_CAN1_TX { + pinmux = <0x303301d4 4 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301d4 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpt_compare_gpt1_compare1: IOMUXC_SPDIF_TX_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_i2c_scl_i2c5_scl: IOMUXC_SPDIF_TX_I2C_SCL_I2C5_SCL { + pinmux = <0x303301d4 2 0x303305c4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301d4 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301d4 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330220 1 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330220 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330220 0 0x303305e8 4 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330220 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330224 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330224 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330224 0 0x303305e8 5 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330224 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x30330228 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x30330228 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x30330228 3 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x30330228 0 0x303305f0 6 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x30330228 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x3033022c 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x3033022c 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x3033022c 3 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x3033022c 0 0x303305f0 7 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x3033022c 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_can_tx_can2_tx: IOMUXC_UART3_RXD_CAN_TX_CAN2_TX { + pinmux = <0x30330230 4 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330230 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330230 3 0x30330598 1 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330230 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330230 1 0x303305e4 4 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330230 0 0x303305f8 6 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330230 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330230 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_can_rx_can2_rx: IOMUXC_UART3_TXD_CAN_RX_CAN2_RX { + pinmux = <0x30330234 4 0x30330550 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330234 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330234 3 0x3033059c 1 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330234 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330234 1 0x303305e4 5 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330234 0 0x303305f8 7 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330234 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330234 2 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x30330238 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x30330238 3 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_i2c_scl_i2c6_scl: IOMUXC_UART4_RXD_I2C_SCL_I2C6_SCL { + pinmux = <0x30330238 4 0x303305cc 2 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x30330238 2 0x303305a0 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x30330238 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x30330238 1 0x303305ec 4 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x30330238 0 0x30330600 8 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x30330238 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x3033023c 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x3033023c 3 0x30330594 1 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_i2c_sda_i2c6_sda: IOMUXC_UART4_TXD_I2C_SDA_I2C6_SDA { + pinmux = <0x3033023c 4 0x303305d0 2 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x3033023c 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x3033023c 1 0x303305ec 5 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x3033023c 0 0x30330600 9 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x3033023c 0 0x0 0 0x3033049c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8ml6dvnlz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8ml6dvnlz-pinctrl.dtsi new file mode 100644 index 000000000..e19004ca8 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8ml6dvnlz-pinctrl.dtsi @@ -0,0 +1,2404 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8ML6DVNLZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330250>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301e8 0 0x3033055c 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301e8 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301e8 2 0x303305ac 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai7_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x303301e8 3 0x30330534 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301e8 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301e8 1 0x303305f4 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301e4 0 0x30330560 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301e4 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301e4 2 0x303305a8 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x303301e4 3 0x30330530 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301e4 1 0x303305f8 5 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301e4 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301e0 0 0x30330558 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301e0 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301e0 2 0x303305a4 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai7_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x303301e0 3 0x30330538 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301e0 1 0x303305f8 4 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301e0 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x303301ec 0 0x30330564 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x303301ec 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x303301ec 2 0x303305b0 1 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai7_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x303301ec 3 0x30330540 1 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303301ec 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303301ec 1 0x303305f4 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ccm_clko_ccm_clko1: IOMUXC_ECSPI2_MISO_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x303301f8 4 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303301f8 0 0x3033056c 1 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x303301f8 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x303301f8 2 0x303305bc 4 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai7_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI7_MCLK { + pinmux = <0x303301f8 3 0x3033052c 1 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x303301f8 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x303301f8 1 0x303305fc 2 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303301f4 0 0x30330570 1 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x303301f4 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x303301f4 2 0x303305b8 3 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai7_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x303301f4 3 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x303301f4 1 0x30330600 7 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x303301f4 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303301f0 0 0x30330568 1 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x303301f0 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x303301f0 2 0x303305b4 3 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x303301f0 3 0x3033053c 1 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x303301f0 1 0x30330600 6 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x303301f0 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ccm_clko_ccm_clko2: IOMUXC_ECSPI2_SS0_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x303301fc 4 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303301fc 0 0x30330574 1 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x303301fc 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x303301fc 2 0x303305c0 4 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x303301fc 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x303301fc 1 0x303305fc 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC_ENET_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x30330054 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330054 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330054 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330054 6 0x30330630 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC_ENET_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x30330058 0 0x30330590 1 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x30330058 5 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330058 3 0x303304cc 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x30330058 2 0x30330528 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330058 6 0x30330624 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC_ENET_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x3033007c 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x303304c4 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x3033007c 2 0x30330534 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x3033007c 6 0x30330620 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC_ENET_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x30330080 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330080 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330080 3 0x303304c0 1 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330080 2 0x30330538 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330080 6 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC_ENET_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x30330084 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330084 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330084 3 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330084 2 0x30330530 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330084 6 0x30330604 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC_ENET_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x30330088 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x30330088 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x30330088 2 0x3033052c 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x30330088 3 0x30330544 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x30330088 6 0x3033060c 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_qos_rgmii_rxc_enet_qos_rgmii_rxc: IOMUXC_ENET_RXC_ENET_QOS_RGMII_RXC_ENET_QOS_RGMII_RXC { + pinmux = <0x30330078 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC_ENET_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x30330078 1 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x30330078 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x303304c8 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x30330078 2 0x3033053c 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330078 6 0x3033061c 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x30330074 0 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330074 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x303304cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330074 2 0x30330540 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330074 6 0x30330618 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC_ENET_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x30330068 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x30330068 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_clk_pdm_clk: IOMUXC_ENET_TD0_PDM_CLK_PDM_CLK { + pinmux = <0x30330068 3 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330068 2 0x30330518 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x30330068 6 0x30330634 1 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC_ENET_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x30330064 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330064 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330064 3 0x303304c0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330064 2 0x30330520 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330064 6 0x30330608 1 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC_ENET_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x30330060 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_qos_tx_clk_enet_qos_tx_clk: IOMUXC_ENET_TD2_ENET_QOS_TX_CLK_ENET_QOS_TX_CLK { + pinmux = <0x30330060 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330060 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330060 3 0x303304c4 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330060 2 0x3033051c 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330060 6 0x3033062c 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC_ENET_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x3033005c 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x3033005c 5 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033005c 3 0x303304c8 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033005c 2 0x30330524 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x3033005c 6 0x30330628 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_qos_rgmii_txc_enet_qos_rgmii_txc: IOMUXC_ENET_TXC_ENET_QOS_RGMII_TXC_ENET_QOS_RGMII_TXC { + pinmux = <0x30330070 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC_ENET_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x30330070 1 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330070 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330070 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330070 6 0x30330614 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x3033006c 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x3033006c 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x3033006c 2 0x30330514 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_spdif_out_spdif1_out: IOMUXC_ENET_TX_CTL_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x3033006c 3 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033006c 6 0x30330610 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330014 1 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330014 6 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330014 5 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330014 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_isp_fl_trig_isp_fl_trig_0: IOMUXC_GPIO1_IO00_ISP_FL_TRIG_ISP_FL_TRIG_0 { + pinmux = <0x30330014 3 0x303305d4 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x30330018 6 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x30330018 5 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x30330018 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_isp_shutter_trig_isp_shutter_trig_0: IOMUXC_GPIO1_IO01_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_0 { + pinmux = <0x30330018 3 0x303305dc 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x30330018 1 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x3033001c 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_isp_flash_trig_isp_flash_trig_0: IOMUXC_GPIO1_IO02_ISP_FLASH_TRIG_ISP_FLASH_TRIG_0 { + pinmux = <0x3033001c 3 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x3033001c 7 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x3033001c 5 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x3033001c 1 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330020 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_isp_prelight_trig_isp_prelight_trig_0: IOMUXC_GPIO1_IO03_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_0 { + pinmux = <0x30330020 3 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330020 5 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330020 1 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330024 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_isp_shutter_open_isp_shutter_open_0: IOMUXC_GPIO1_IO04_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_0 { + pinmux = <0x30330024 3 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330024 5 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330024 1 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330028 5 0x30330554 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x30330028 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_isp_fl_trig_isp_fl_trig_1: IOMUXC_GPIO1_IO05_ISP_FL_TRIG_ISP_FL_TRIG_1 { + pinmux = <0x30330028 3 0x303305d8 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x30330028 1 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x3033002c 6 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_qos_mdc_enet_qos_mdc: IOMUXC_GPIO1_IO06_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x3033002c 1 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x3033002c 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_isp_shutter_trig_isp_shutter_trig_1: IOMUXC_GPIO1_IO06_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_1 { + pinmux = <0x3033002c 3 0x303305e0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x3033002c 5 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330030 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_qos_mdio_enet_qos_mdio: IOMUXC_GPIO1_IO07_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x30330030 1 0x30330590 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330030 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_isp_flash_trig_isp_flash_trig_1: IOMUXC_GPIO1_IO07_ISP_FLASH_TRIG_ISP_FLASH_TRIG_1 { + pinmux = <0x30330030 3 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330030 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_qos_1588_event0_aux_in_enet_qos_1588_event0_aux_in: IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_AUX_IN_ENET_QOS_1588_EVENT0_AUX_IN { + pinmux = <0x30330034 4 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x30330034 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330034 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_isp_prelight_trig_isp_prelight_trig_1: IOMUXC_GPIO1_IO08_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_1 { + pinmux = <0x30330034 3 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330034 2 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330034 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x30330038 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x30330038 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_isp_shutter_open_isp_shutter_open_1: IOMUXC_GPIO1_IO09_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_1 { + pinmux = <0x30330038 3 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x30330038 2 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x30330038 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330038 4 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x3033003c 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x3033003c 2 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_id_usb1_id: IOMUXC_GPIO1_IO10_USB_ID_USB1_ID { + pinmux = <0x3033003c 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330040 5 0x30330554 1 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330040 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330040 2 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_id_usb2_id: IOMUXC_GPIO1_IO11_USB_ID_USB2_ID { + pinmux = <0x30330040 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330040 4 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330044 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330044 5 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_pwr_usb1_pwr: IOMUXC_GPIO1_IO12_USB_PWR_USB1_PWR { + pinmux = <0x30330044 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x30330048 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x30330048 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_oc_usb1_oc: IOMUXC_GPIO1_IO13_USB_OC_USB1_OC { + pinmux = <0x30330048 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x3033004c 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x3033004c 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x3033004c 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_pwr_usb2_pwr: IOMUXC_GPIO1_IO14_USB_PWR_USB2_PWR { + pinmux = <0x3033004c 1 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033004c 4 0x30330608 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330050 6 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330050 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330050 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_oc_usb2_oc: IOMUXC_GPIO1_IO15_USB_OC_USB2_OC { + pinmux = <0x30330050 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330050 4 0x30330634 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_can_tx_can2_tx: IOMUXC_HDMI_CEC_CAN_TX_CAN2_TX { + pinmux = <0x30330248 4 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_gpio_io_gpio3_io28: IOMUXC_HDMI_CEC_GPIO_IO_GPIO3_IO28 { + pinmux = <0x30330248 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_hdmi_cec_hdmi_cec: IOMUXC_HDMI_CEC_HDMI_CEC_HDMI_CEC { + pinmux = <0x30330248 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_i2c_scl_i2c6_scl: IOMUXC_HDMI_CEC_I2C_SCL_I2C6_SCL { + pinmux = <0x30330248 3 0x303305cc 3 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_can_tx_can1_tx: IOMUXC_HDMI_DDC_SCL_CAN_TX_CAN1_TX { + pinmux = <0x30330240 4 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_gpio_io_gpio3_io26: IOMUXC_HDMI_DDC_SCL_GPIO_IO_GPIO3_IO26 { + pinmux = <0x30330240 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_hdmi_scl_hdmi_scl: IOMUXC_HDMI_DDC_SCL_HDMI_SCL_HDMI_SCL { + pinmux = <0x30330240 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_i2c_scl_i2c5_scl: IOMUXC_HDMI_DDC_SCL_I2C_SCL_I2C5_SCL { + pinmux = <0x30330240 3 0x303305c4 3 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_can_rx_can1_rx: IOMUXC_HDMI_DDC_SDA_CAN_RX_CAN1_RX { + pinmux = <0x30330244 4 0x3033054c 3 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_gpio_io_gpio3_io27: IOMUXC_HDMI_DDC_SDA_GPIO_IO_GPIO3_IO27 { + pinmux = <0x30330244 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_hdmi_sda_hdmi_sda: IOMUXC_HDMI_DDC_SDA_HDMI_SDA_HDMI_SDA { + pinmux = <0x30330244 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_i2c_sda_i2c5_sda: IOMUXC_HDMI_DDC_SDA_I2C_SDA_I2C5_SDA { + pinmux = <0x30330244 3 0x303305c8 3 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_can_rx_can2_rx: IOMUXC_HDMI_HPD_CAN_RX_CAN2_RX { + pinmux = <0x3033024c 4 0x30330550 3 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_gpio_io_gpio3_io29: IOMUXC_HDMI_HPD_GPIO_IO_GPIO3_IO29 { + pinmux = <0x3033024c 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_hdmi_hpd_hdmi_hpd: IOMUXC_HDMI_HPD_HDMI_HPD_HDMI_HPD { + pinmux = <0x3033024c 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_hdmi_hpd_o_hdmi_hpd_o: IOMUXC_HDMI_HPD_HDMI_HPD_O_HDMI_HPD_O { + pinmux = <0x3033024c 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_i2c_sda_i2c6_sda: IOMUXC_HDMI_HPD_I2C_SDA_I2C6_SDA { + pinmux = <0x3033024c 3 0x303305d0 3 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330200 3 0x30330558 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_qos_mdc_enet_qos_mdc: IOMUXC_I2C1_SCL_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x30330200 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330200 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330200 0 0x303305a4 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330204 3 0x30330560 1 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_qos_mdio_enet_qos_mdio: IOMUXC_I2C1_SDA_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x30330204 1 0x30330590 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330204 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330204 0 0x303305a8 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x30330208 3 0x3033055c 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_qos_1588_event1_aux_in_enet_qos_1588_event1_aux_in: IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_AUX_IN_ENET_QOS_1588_EVENT1_AUX_IN { + pinmux = <0x30330208 4 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_qos_1588_event1_in_enet_qos_1588_event1_in: IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_IN_ENET_QOS_1588_EVENT1_IN { + pinmux = <0x30330208 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x30330208 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x30330208 0 0x303305ac 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330208 2 0x30330608 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x3033020c 3 0x30330564 1 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_qos_1588_event1_out_enet_qos_1588_event1_out: IOMUXC_I2C2_SDA_ENET_QOS_1588_EVENT1_OUT_ENET_QOS_1588_EVENT1_OUT { + pinmux = <0x3033020c 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x3033020c 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x3033020c 0 0x303305b0 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x3033020c 2 0x30330634 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330210 3 0x30330568 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330210 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330210 2 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330210 0 0x303305b4 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330210 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330214 3 0x30330570 2 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330214 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330214 2 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330214 0 0x303305b8 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330214 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x30330218 3 0x3033056c 2 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x30330218 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x30330218 0 0x303305bc 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x30330218 2 0x303305a0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x30330218 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x3033021c 3 0x30330574 2 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x3033021c 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x3033021c 0 0x303305c0 5 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x3033021c 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300e0 6 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300e0 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_isp_fl_trig_isp_fl_trig_0: IOMUXC_NAND_ALE_ISP_FL_TRIG_ISP_FL_TRIG_0 { + pinmux = <0x303300e0 3 0x303305d4 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300e0 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300e0 1 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_sai_tx_bclk_sai3_tx_bclk: IOMUXC_NAND_ALE_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303300e0 2 0x303304e8 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300e0 4 0x303305f8 2 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300e0 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300e4 6 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300e4 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_isp_shutter_trig_isp_shutter_trig_0: IOMUXC_NAND_CE0_B_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_0 { + pinmux = <0x303300e4 3 0x303305dc 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300e4 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300e4 1 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_sai_tx_data_sai3_tx_data0: IOMUXC_NAND_CE0_B_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303300e4 2 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300e4 4 0x303305f8 3 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300e4 4 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300e8 6 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300e8 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e8 4 0x303305bc 2 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300e8 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300e8 1 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300e8 2 0x30330630 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x303300ec 6 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x303300ec 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x303300ec 4 0x303305c0 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x303300ec 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x303300ec 1 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x303300ec 2 0x30330624 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x303300f0 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x303300f0 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x303300f0 4 0x303305b8 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x303300f0 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x303300f0 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x303300f0 2 0x30330628 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x303300f4 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x303300f4 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x303300f4 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_uart_rx_uart4_rx: IOMUXC_NAND_CLE_UART_RX_UART4_RX { + pinmux = <0x303300f4 4 0x30330600 2 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_uart_tx_uart4_rx: IOMUXC_NAND_CLE_UART_TX_UART4_RX { + pinmux = <0x303300f4 4 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x303300f4 2 0x3033062c 1 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x303300f8 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x303300f8 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_isp_flash_trig_isp_flash_trig_0: IOMUXC_NAND_DATA00_ISP_FLASH_TRIG_ISP_FLASH_TRIG_0 { + pinmux = <0x303300f8 3 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x303300f8 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x303300f8 1 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_sai_rx_data_sai3_rx_data0: IOMUXC_NAND_DATA00_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303300f8 2 0x303304e4 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x303300f8 4 0x30330600 3 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x303300f8 4 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x303300fc 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x303300fc 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_isp_prelight_trig_isp_prelight_trig_0: IOMUXC_NAND_DATA01_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_0 { + pinmux = <0x303300fc 3 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x303300fc 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x303300fc 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_sai_tx_sync_sai3_tx_sync: IOMUXC_NAND_DATA01_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303300fc 2 0x303304ec 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x303300fc 4 0x30330600 4 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x303300fc 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330100 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330100 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x303305c0 3 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330100 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330100 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_uart_cts_b_uart4_cts_b: IOMUXC_NAND_DATA02_UART_CTS_B_UART4_CTS_B { + pinmux = <0x30330100 3 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_uart_rts_b_uart4_cts_b: IOMUXC_NAND_DATA02_UART_RTS_B_UART4_CTS_B { + pinmux = <0x30330100 3 0x303305fc 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330100 2 0x30330608 2 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330104 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330104 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_isp_fl_trig_isp_fl_trig_1: IOMUXC_NAND_DATA03_ISP_FL_TRIG_ISP_FL_TRIG_1 { + pinmux = <0x30330104 4 0x303305d8 1 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330104 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330104 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_uart_cts_b_uart4_rts_b: IOMUXC_NAND_DATA03_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330104 3 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_uart_rts_b_uart4_rts_b: IOMUXC_NAND_DATA03_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330104 3 0x303305fc 1 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330104 2 0x30330634 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x30330108 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x30330108 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_isp_shutter_trig_isp_shutter_trig_1: IOMUXC_NAND_DATA04_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_1 { + pinmux = <0x30330108 4 0x303305e0 1 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x30330108 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_a_data_qspi_a_data4: IOMUXC_NAND_DATA04_QSPI_A_DATA_QSPI_A_DATA4 { + pinmux = <0x30330108 3 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x30330108 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330108 2 0x30330610 1 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x3033010c 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x3033010c 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_isp_flash_trig_isp_flash_trig_1: IOMUXC_NAND_DATA05_ISP_FLASH_TRIG_ISP_FLASH_TRIG_1 { + pinmux = <0x3033010c 4 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x3033010c 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_a_data_qspi_a_data5: IOMUXC_NAND_DATA05_QSPI_A_DATA_QSPI_A_DATA5 { + pinmux = <0x3033010c 3 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x3033010c 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x3033010c 2 0x30330614 1 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330110 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330110 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_isp_prelight_trig_isp_prelight_trig_1: IOMUXC_NAND_DATA06_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_1 { + pinmux = <0x30330110 4 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330110 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_a_data_qspi_a_data6: IOMUXC_NAND_DATA06_QSPI_A_DATA_QSPI_A_DATA6 { + pinmux = <0x30330110 3 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330110 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330110 2 0x30330618 1 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330114 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330114 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_isp_shutter_open_isp_shutter_open_1: IOMUXC_NAND_DATA07_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_1 { + pinmux = <0x30330114 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330114 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_a_data_qspi_a_data7: IOMUXC_NAND_DATA07_QSPI_A_DATA_QSPI_A_DATA7 { + pinmux = <0x30330114 3 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330114 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330114 2 0x3033061c 1 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x30330118 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x30330118 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x30330118 4 0x303305b4 1 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_isp_shutter_open_isp_shutter_open_0: IOMUXC_NAND_DQS_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_0 { + pinmux = <0x30330118 3 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x30330118 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x30330118 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_sai_mclk_sai3_mclk: IOMUXC_NAND_DQS_SAI_MCLK_SAI3_MCLK { + pinmux = <0x30330118 2 0x303304e0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330120 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330120 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330120 4 0x303305b4 2 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330120 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330120 2 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x3033011c 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x3033011c 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x3033011c 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x3033011c 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_uart_rx_uart4_tx: IOMUXC_NAND_RE_B_UART_RX_UART4_TX { + pinmux = <0x3033011c 4 0x30330600 5 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_uart_tx_uart4_tx: IOMUXC_NAND_RE_B_UART_TX_UART4_TX { + pinmux = <0x3033011c 4 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x3033011c 2 0x30330620 1 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330124 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330124 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330124 4 0x303305b8 2 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330124 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330124 2 0x30330604 1 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x30330128 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x30330128 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_scl_i2c4_scl: IOMUXC_NAND_WP_B_I2C_SCL_I2C4_SCL { + pinmux = <0x30330128 4 0x303305bc 3 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x30330128 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x30330128 2 0x3033060c 1 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_enet_tx_clk_enet1_tx_clk: IOMUXC_SAI1_MCLK_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330198 4 0x30330578 1 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x30330198 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x30330198 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330198 2 0x303304d4 2 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_SAI1_RXC_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033014c 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io1: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO1 { + pinmux = <0x3033014c 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_pdm_clk_pdm_clk: IOMUXC_SAI1_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x3033014c 3 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x3033014c 0 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_SAI1_RXD0_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x30330150 4 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io2: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO2 { + pinmux = <0x30330150 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330150 3 0x303304c0 4 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330150 0 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330150 2 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_SAI1_RXD1_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330154 4 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io3: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO3 { + pinmux = <0x30330154 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330154 3 0x303304c4 4 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330154 0 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_enet_mdc_enet1_mdc: IOMUXC_SAI1_RXD2_ENET_MDC_ENET1_MDC { + pinmux = <0x30330158 4 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io4: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO4 { + pinmux = <0x30330158 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330158 3 0x303304c8 4 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x30330158 0 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_enet_mdio_enet1_mdio: IOMUXC_SAI1_RXD3_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033015c 4 0x3033057c 1 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io5: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO5 { + pinmux = <0x3033015c 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x3033015c 3 0x303304cc 4 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x3033015c 0 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SAI1_RXD4_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330160 4 0x30330580 1 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io6: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO6 { + pinmux = <0x30330160 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330160 2 0x30330518 1 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330160 0 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330160 1 0x30330524 1 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SAI1_RXD5_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330164 4 0x30330584 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io7: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO7 { + pinmux = <0x30330164 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330164 0 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330164 2 0x3033051c 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330164 3 0x303304d0 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330164 1 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_SAI1_RXD6_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330168 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io8: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO8 { + pinmux = <0x30330168 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x30330168 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330168 2 0x30330520 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x30330168 1 0x30330528 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_SAI1_RXD7_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033016c 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io9: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO9 { + pinmux = <0x3033016c 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x3033016c 1 0x30330514 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x3033016c 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033016c 3 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033016c 2 0x303304d8 3 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_SAI1_RXFS_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330148 4 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io0: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO0 { + pinmux = <0x30330148 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330148 0 0x303304d0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_SAI1_TXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x30330174 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330174 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330174 0 0x303304d4 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SAI1_TXD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x30330178 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x30330178 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330178 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SAI1_TXD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x3033017c 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x3033017c 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x3033017c 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_SAI1_TXD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330180 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330180 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330180 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_SAI1_TXD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330184 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330184 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330184 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SAI1_TXD4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330188 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x30330188 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330188 1 0x30330518 2 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330188 2 0x30330524 2 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330188 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_SAI1_TXD5_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x3033018c 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x3033018c 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x3033018c 1 0x3033051c 2 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x3033018c 0 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x3033018c 2 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_enet_rx_er_enet1_rx_er: IOMUXC_SAI1_TXD6_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x30330190 4 0x3033058c 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x30330190 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330190 1 0x30330520 2 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x30330190 0 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x30330190 2 0x30330528 2 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_enet_tx_er_enet1_tx_er: IOMUXC_SAI1_TXD7_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330194 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x30330194 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x30330194 3 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330194 1 0x30330514 2 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x30330194 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SAI1_TXFS_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330170 4 0x30330588 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330170 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330170 0 0x303304d8 4 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_can_rx_can2_rx: IOMUXC_SAI2_MCLK_CAN_RX_CAN2_RX { + pinmux = <0x303301b4 3 0x30330550 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_enet_qos_1588_event3_aux_in_enet_qos_1588_event3_aux_in: IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_AUX_IN_ENET_QOS_1588_EVENT3_AUX_IN { + pinmux = <0x303301b4 4 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_enet_qos_1588_event3_in_enet_qos_1588_event3_in: IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_IN_ENET_QOS_1588_EVENT3_IN { + pinmux = <0x303301b4 2 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301b4 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301b4 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301b4 6 0x303304e0 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301b4 1 0x303304f0 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_can_tx_can1_tx: IOMUXC_SAI2_RXC_CAN_TX_CAN1_TX { + pinmux = <0x303301a0 3 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301a0 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301a0 6 0x303304c4 5 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301a0 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301a0 1 0x3033050c 2 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301a0 4 0x303305e8 3 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301a0 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_enet_qos_1588_event2_out_enet_qos_1588_event2_out: IOMUXC_SAI2_RXD0_ENET_QOS_1588_EVENT2_OUT_ENET_QOS_1588_EVENT2_OUT { + pinmux = <0x303301a4 2 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301a4 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301a4 6 0x303304cc 5 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301a4 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301a4 3 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301a4 1 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301a4 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301a4 4 0x303305e4 2 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x3033019c 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033019c 6 0x303304c8 5 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x3033019c 3 0x303304dc 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x3033019c 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x3033019c 2 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033019c 1 0x30330510 2 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x3033019c 4 0x303305e8 2 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x3033019c 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_can_rx_can1_rx: IOMUXC_SAI2_TXC_CAN_RX_CAN1_RX { + pinmux = <0x303301ac 3 0x3033054c 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301ac 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301ac 6 0x303304c4 6 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301ac 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301ac 1 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_can_tx_can2_tx: IOMUXC_SAI2_TXD0_CAN_TX_CAN2_TX { + pinmux = <0x303301b0 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_enet_qos_1588_event2_aux_in_enet_qos_1588_event2_aux_in: IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_AUX_IN_ENET_QOS_1588_EVENT2_AUX_IN { + pinmux = <0x303301b0 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_enet_qos_1588_event2_in_enet_qos_1588_event2_in: IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_IN_ENET_QOS_1588_EVENT2_IN { + pinmux = <0x303301b0 2 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301b0 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301b0 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301b0 1 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_enet_qos_1588_event3_out_enet_qos_1588_event3_out: IOMUXC_SAI2_TXFS_ENET_QOS_1588_EVENT3_OUT_ENET_QOS_1588_EVENT3_OUT { + pinmux = <0x303301a8 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301a8 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301a8 6 0x303304c8 6 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301a8 3 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301a8 1 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301a8 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301a8 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301a8 4 0x303305e4 3 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301d0 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301d0 1 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301d0 0 0x303304e0 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301d0 2 0x303304f0 3 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301d0 6 0x30330544 3 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301d0 4 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301bc 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301bc 3 0x3033059c 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301bc 6 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301bc 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301bc 2 0x303304f4 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data2: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA2 { + pinmux = <0x303301bc 1 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301bc 4 0x303305ec 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301c0 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x303304c4 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai2_rx_data3: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI2_RX_DATA3 { + pinmux = <0x303301c0 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301c0 0 0x303304e4 1 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301c0 2 0x303304f8 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301c0 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301c0 4 0x303305ec 3 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301b8 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301b8 6 0x303304c0 5 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b8 1 0x303304dc 1 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301b8 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301b8 2 0x30330508 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301b8 4 0x30330544 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301c8 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_capture_gpt1_capture1: IOMUXC_SAI3_TXC_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301c8 3 0x30330594 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301c8 6 0x303304c8 7 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301c8 2 0x30330500 2 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301c8 0 0x303304e8 1 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data2: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA2 { + pinmux = <0x303301c8 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301c8 4 0x303305f0 5 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301c8 4 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301cc 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301cc 3 0x30330598 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301cc 2 0x30330504 2 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai2_tx_data3: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI2_TX_DATA3 { + pinmux = <0x303301cc 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301cc 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301cc 4 0x30330548 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301c4 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301c4 6 0x303304cc 6 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301c4 2 0x303304fc 2 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301c4 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301c4 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301c4 0 0x303304ec 1 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301c4 4 0x303305f0 4 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301c4 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_can_rx_can2_rx: IOMUXC_SAI5_MCLK_CAN_RX_CAN2_RX { + pinmux = <0x30330144 6 0x30330550 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330144 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_i2c_sda_i2c5_sda: IOMUXC_SAI5_MCLK_I2C_SDA_I2C5_SDA { + pinmux = <0x30330144 3 0x303305c8 1 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_pwm_out_pwm1_out: IOMUXC_SAI5_MCLK_PWM_OUT_PWM1_OUT { + pinmux = <0x30330144 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330144 0 0x303304f0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330144 1 0x303304d4 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330130 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_i2c_sda_i2c6_sda: IOMUXC_SAI5_RXC_I2C_SDA_I2C6_SDA { + pinmux = <0x30330130 3 0x303305d0 1 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330130 4 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pwm_out_pwm3_out: IOMUXC_SAI5_RXC_PWM_OUT_PWM3_OUT { + pinmux = <0x30330130 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330130 0 0x303304f4 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330130 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330134 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_i2c_scl_i2c5_scl: IOMUXC_SAI5_RXD0_I2C_SCL_I2C5_SCL { + pinmux = <0x30330134 3 0x303305c4 1 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330134 4 0x303304c0 3 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pwm_out_pwm2_out: IOMUXC_SAI5_RXD0_PWM_OUT_PWM2_OUT { + pinmux = <0x30330134 2 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330134 0 0x303304f8 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330134 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_can_tx_can1_tx: IOMUXC_SAI5_RXD1_CAN_TX_CAN1_TX { + pinmux = <0x30330138 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x30330138 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330138 4 0x303304c4 3 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330138 0 0x303304fc 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330138 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330138 2 0x303304d8 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330138 3 0x30330510 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_can_rx_can1_rx: IOMUXC_SAI5_RXD2_CAN_RX_CAN1_RX { + pinmux = <0x3033013c 6 0x3033054c 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x3033013c 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033013c 4 0x303304c8 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033013c 0 0x30330500 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x3033013c 3 0x3033050c 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033013c 1 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033013c 2 0x303304d8 1 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_can_tx_can2_tx: IOMUXC_SAI5_RXD3_CAN_TX_CAN2_TX { + pinmux = <0x30330140 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330140 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330140 4 0x303304cc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330140 0 0x30330504 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330140 1 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330140 3 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330140 2 0x303304d8 2 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x3033012c 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_i2c_scl_i2c6_scl: IOMUXC_SAI5_RXFS_I2C_SCL_I2C6_SCL { + pinmux = <0x3033012c 3 0x303305cc 1 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_pwm_out_pwm4_out: IOMUXC_SAI5_RXFS_PWM_OUT_PWM4_OUT { + pinmux = <0x3033012c 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033012c 0 0x30330508 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033012c 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x3033008c 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x3033008c 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_i2c_scl_i2c5_scl: IOMUXC_SD1_CLK_I2C_SCL_I2C5_SCL { + pinmux = <0x3033008c 3 0x303305c4 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x3033008c 4 0x303305e8 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x3033008c 4 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x3033008c 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330090 1 0x3033057c 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x30330090 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_i2c_sda_i2c5_sda: IOMUXC_SD1_CMD_I2C_SDA_I2C5_SDA { + pinmux = <0x30330090 3 0x303305c8 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x30330090 4 0x303305e8 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x30330090 4 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x30330090 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330094 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x30330094 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_i2c_scl_i2c6_scl: IOMUXC_SD1_DATA0_I2C_SCL_I2C6_SCL { + pinmux = <0x30330094 3 0x303305cc 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330094 4 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330094 4 0x303305e4 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x30330094 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x30330098 1 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x30330098 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_i2c_sda_i2c6_sda: IOMUXC_SD1_DATA1_I2C_SDA_I2C6_SDA { + pinmux = <0x30330098 3 0x303305d0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330098 4 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330098 4 0x303305e4 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x30330098 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x3033009c 1 0x30330580 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x3033009c 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_i2c_scl_i2c4_scl: IOMUXC_SD1_DATA2_I2C_SCL_I2C4_SCL { + pinmux = <0x3033009c 3 0x303305bc 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x3033009c 4 0x303305f0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x3033009c 4 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x3033009c 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300a0 1 0x30330584 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300a0 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_i2c_sda_i2c4_sda: IOMUXC_SD1_DATA3_I2C_SDA_I2C4_SDA { + pinmux = <0x303300a0 3 0x303305c0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300a0 4 0x303305f0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300a0 4 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300a0 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300a4 1 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300a4 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300a4 3 0x303305a4 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300a4 4 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300a4 4 0x303305ec 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300a4 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300a8 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300a8 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300a8 3 0x303305a8 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300a8 4 0x303305ec 1 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300a8 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300ac 1 0x30330588 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300ac 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300ac 3 0x303305ac 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300ac 4 0x303305f8 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300ac 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300ac 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300b0 1 0x3033058c 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300b0 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300b0 3 0x303305b0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300b0 4 0x303305f8 1 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300b0 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300b0 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300b4 1 0x30330578 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300b4 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300b4 3 0x303305b4 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300b4 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300b4 4 0x303305f4 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300b4 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300b8 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300b8 3 0x303305b8 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300b8 4 0x303305f4 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300b8 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300bc 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300bc 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300c0 2 0x30330568 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300c0 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300c0 3 0x30330600 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300c0 3 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300c0 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300c4 2 0x30330570 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300c4 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300c4 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300c4 3 0x30330600 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300c4 3 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300c4 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300c8 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300c8 2 0x303305c0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300c8 4 0x303304c0 2 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300c8 3 0x303305f0 2 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300c8 3 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300c8 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300cc 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300cc 2 0x303305bc 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300cc 4 0x303304c4 2 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300cc 3 0x303305f0 3 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300cc 3 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300cc 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300d0 2 0x30330574 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300d0 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300d0 4 0x303304c8 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300d0 3 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300d0 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300d4 2 0x3033056c 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300d4 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300d4 4 0x303304cc 2 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300d4 3 0x30330544 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300d4 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300d8 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300d8 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300dc 6 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300dc 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300dc 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301dc 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpt_compare_gpt1_compare3: IOMUXC_SPDIF_EXT_CLK_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301dc 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301dc 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301dc 0 0x30330548 1 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_can_rx_can1_rx: IOMUXC_SPDIF_RX_CAN_RX_CAN1_RX { + pinmux = <0x303301d8 4 0x3033054c 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301d8 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpt_compare_gpt1_compare2: IOMUXC_SPDIF_RX_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301d8 3 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_i2c_sda_i2c5_sda: IOMUXC_SPDIF_RX_I2C_SDA_I2C5_SDA { + pinmux = <0x303301d8 2 0x303305c8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301d8 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301d8 0 0x30330544 4 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_can_tx_can1_tx: IOMUXC_SPDIF_TX_CAN_TX_CAN1_TX { + pinmux = <0x303301d4 4 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301d4 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpt_compare_gpt1_compare1: IOMUXC_SPDIF_TX_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_i2c_scl_i2c5_scl: IOMUXC_SPDIF_TX_I2C_SCL_I2C5_SCL { + pinmux = <0x303301d4 2 0x303305c4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301d4 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301d4 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330220 1 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330220 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330220 0 0x303305e8 4 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330220 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330224 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330224 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330224 0 0x303305e8 5 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330224 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x30330228 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x30330228 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x30330228 3 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x30330228 0 0x303305f0 6 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x30330228 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x3033022c 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x3033022c 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x3033022c 3 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x3033022c 0 0x303305f0 7 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x3033022c 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_can_tx_can2_tx: IOMUXC_UART3_RXD_CAN_TX_CAN2_TX { + pinmux = <0x30330230 4 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330230 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330230 3 0x30330598 1 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330230 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330230 1 0x303305e4 4 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330230 0 0x303305f8 6 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330230 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330230 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_can_rx_can2_rx: IOMUXC_UART3_TXD_CAN_RX_CAN2_RX { + pinmux = <0x30330234 4 0x30330550 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330234 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330234 3 0x3033059c 1 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330234 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330234 1 0x303305e4 5 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330234 0 0x303305f8 7 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330234 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330234 2 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x30330238 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x30330238 3 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_i2c_scl_i2c6_scl: IOMUXC_UART4_RXD_I2C_SCL_I2C6_SCL { + pinmux = <0x30330238 4 0x303305cc 2 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x30330238 2 0x303305a0 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x30330238 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x30330238 1 0x303305ec 4 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x30330238 0 0x30330600 8 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x30330238 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x3033023c 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x3033023c 3 0x30330594 1 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_i2c_sda_i2c6_sda: IOMUXC_UART4_TXD_I2C_SDA_I2C6_SDA { + pinmux = <0x3033023c 4 0x303305d0 2 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x3033023c 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x3033023c 1 0x303305ec 5 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x3033023c 0 0x30330600 9 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x3033023c 0 0x0 0 0x3033049c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8ml8cvnkz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8ml8cvnkz-pinctrl.dtsi new file mode 100644 index 000000000..71ba75c68 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8ml8cvnkz-pinctrl.dtsi @@ -0,0 +1,2404 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8ML8CVNKZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330250>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301e8 0 0x3033055c 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301e8 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301e8 2 0x303305ac 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai7_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x303301e8 3 0x30330534 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301e8 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301e8 1 0x303305f4 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301e4 0 0x30330560 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301e4 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301e4 2 0x303305a8 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x303301e4 3 0x30330530 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301e4 1 0x303305f8 5 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301e4 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301e0 0 0x30330558 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301e0 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301e0 2 0x303305a4 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai7_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x303301e0 3 0x30330538 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301e0 1 0x303305f8 4 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301e0 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x303301ec 0 0x30330564 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x303301ec 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x303301ec 2 0x303305b0 1 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai7_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x303301ec 3 0x30330540 1 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303301ec 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303301ec 1 0x303305f4 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ccm_clko_ccm_clko1: IOMUXC_ECSPI2_MISO_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x303301f8 4 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303301f8 0 0x3033056c 1 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x303301f8 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x303301f8 2 0x303305bc 4 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai7_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI7_MCLK { + pinmux = <0x303301f8 3 0x3033052c 1 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x303301f8 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x303301f8 1 0x303305fc 2 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303301f4 0 0x30330570 1 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x303301f4 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x303301f4 2 0x303305b8 3 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai7_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x303301f4 3 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x303301f4 1 0x30330600 7 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x303301f4 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303301f0 0 0x30330568 1 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x303301f0 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x303301f0 2 0x303305b4 3 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x303301f0 3 0x3033053c 1 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x303301f0 1 0x30330600 6 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x303301f0 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ccm_clko_ccm_clko2: IOMUXC_ECSPI2_SS0_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x303301fc 4 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303301fc 0 0x30330574 1 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x303301fc 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x303301fc 2 0x303305c0 4 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x303301fc 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x303301fc 1 0x303305fc 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC_ENET_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x30330054 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330054 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330054 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330054 6 0x30330630 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC_ENET_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x30330058 0 0x30330590 1 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x30330058 5 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330058 3 0x303304cc 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x30330058 2 0x30330528 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330058 6 0x30330624 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC_ENET_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x3033007c 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x303304c4 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x3033007c 2 0x30330534 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x3033007c 6 0x30330620 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC_ENET_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x30330080 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330080 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330080 3 0x303304c0 1 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330080 2 0x30330538 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330080 6 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC_ENET_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x30330084 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330084 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330084 3 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330084 2 0x30330530 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330084 6 0x30330604 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC_ENET_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x30330088 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x30330088 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x30330088 2 0x3033052c 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x30330088 3 0x30330544 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x30330088 6 0x3033060c 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_qos_rgmii_rxc_enet_qos_rgmii_rxc: IOMUXC_ENET_RXC_ENET_QOS_RGMII_RXC_ENET_QOS_RGMII_RXC { + pinmux = <0x30330078 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC_ENET_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x30330078 1 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x30330078 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x303304c8 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x30330078 2 0x3033053c 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330078 6 0x3033061c 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x30330074 0 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330074 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x303304cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330074 2 0x30330540 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330074 6 0x30330618 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC_ENET_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x30330068 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x30330068 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_clk_pdm_clk: IOMUXC_ENET_TD0_PDM_CLK_PDM_CLK { + pinmux = <0x30330068 3 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330068 2 0x30330518 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x30330068 6 0x30330634 1 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC_ENET_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x30330064 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330064 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330064 3 0x303304c0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330064 2 0x30330520 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330064 6 0x30330608 1 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC_ENET_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x30330060 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_qos_tx_clk_enet_qos_tx_clk: IOMUXC_ENET_TD2_ENET_QOS_TX_CLK_ENET_QOS_TX_CLK { + pinmux = <0x30330060 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330060 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330060 3 0x303304c4 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330060 2 0x3033051c 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330060 6 0x3033062c 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC_ENET_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x3033005c 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x3033005c 5 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033005c 3 0x303304c8 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033005c 2 0x30330524 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x3033005c 6 0x30330628 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_qos_rgmii_txc_enet_qos_rgmii_txc: IOMUXC_ENET_TXC_ENET_QOS_RGMII_TXC_ENET_QOS_RGMII_TXC { + pinmux = <0x30330070 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC_ENET_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x30330070 1 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330070 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330070 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330070 6 0x30330614 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x3033006c 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x3033006c 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x3033006c 2 0x30330514 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_spdif_out_spdif1_out: IOMUXC_ENET_TX_CTL_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x3033006c 3 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033006c 6 0x30330610 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330014 1 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330014 6 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330014 5 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330014 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_isp_fl_trig_isp_fl_trig_0: IOMUXC_GPIO1_IO00_ISP_FL_TRIG_ISP_FL_TRIG_0 { + pinmux = <0x30330014 3 0x303305d4 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x30330018 6 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x30330018 5 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x30330018 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_isp_shutter_trig_isp_shutter_trig_0: IOMUXC_GPIO1_IO01_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_0 { + pinmux = <0x30330018 3 0x303305dc 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x30330018 1 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x3033001c 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_isp_flash_trig_isp_flash_trig_0: IOMUXC_GPIO1_IO02_ISP_FLASH_TRIG_ISP_FLASH_TRIG_0 { + pinmux = <0x3033001c 3 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x3033001c 7 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x3033001c 5 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x3033001c 1 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330020 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_isp_prelight_trig_isp_prelight_trig_0: IOMUXC_GPIO1_IO03_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_0 { + pinmux = <0x30330020 3 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330020 5 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330020 1 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330024 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_isp_shutter_open_isp_shutter_open_0: IOMUXC_GPIO1_IO04_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_0 { + pinmux = <0x30330024 3 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330024 5 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330024 1 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330028 5 0x30330554 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x30330028 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_isp_fl_trig_isp_fl_trig_1: IOMUXC_GPIO1_IO05_ISP_FL_TRIG_ISP_FL_TRIG_1 { + pinmux = <0x30330028 3 0x303305d8 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x30330028 1 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x3033002c 6 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_qos_mdc_enet_qos_mdc: IOMUXC_GPIO1_IO06_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x3033002c 1 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x3033002c 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_isp_shutter_trig_isp_shutter_trig_1: IOMUXC_GPIO1_IO06_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_1 { + pinmux = <0x3033002c 3 0x303305e0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x3033002c 5 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330030 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_qos_mdio_enet_qos_mdio: IOMUXC_GPIO1_IO07_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x30330030 1 0x30330590 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330030 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_isp_flash_trig_isp_flash_trig_1: IOMUXC_GPIO1_IO07_ISP_FLASH_TRIG_ISP_FLASH_TRIG_1 { + pinmux = <0x30330030 3 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330030 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_qos_1588_event0_aux_in_enet_qos_1588_event0_aux_in: IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_AUX_IN_ENET_QOS_1588_EVENT0_AUX_IN { + pinmux = <0x30330034 4 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x30330034 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330034 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_isp_prelight_trig_isp_prelight_trig_1: IOMUXC_GPIO1_IO08_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_1 { + pinmux = <0x30330034 3 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330034 2 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330034 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x30330038 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x30330038 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_isp_shutter_open_isp_shutter_open_1: IOMUXC_GPIO1_IO09_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_1 { + pinmux = <0x30330038 3 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x30330038 2 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x30330038 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330038 4 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x3033003c 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x3033003c 2 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_id_usb1_id: IOMUXC_GPIO1_IO10_USB_ID_USB1_ID { + pinmux = <0x3033003c 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330040 5 0x30330554 1 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330040 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330040 2 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_id_usb2_id: IOMUXC_GPIO1_IO11_USB_ID_USB2_ID { + pinmux = <0x30330040 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330040 4 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330044 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330044 5 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_pwr_usb1_pwr: IOMUXC_GPIO1_IO12_USB_PWR_USB1_PWR { + pinmux = <0x30330044 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x30330048 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x30330048 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_oc_usb1_oc: IOMUXC_GPIO1_IO13_USB_OC_USB1_OC { + pinmux = <0x30330048 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x3033004c 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x3033004c 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x3033004c 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_pwr_usb2_pwr: IOMUXC_GPIO1_IO14_USB_PWR_USB2_PWR { + pinmux = <0x3033004c 1 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033004c 4 0x30330608 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330050 6 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330050 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330050 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_oc_usb2_oc: IOMUXC_GPIO1_IO15_USB_OC_USB2_OC { + pinmux = <0x30330050 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330050 4 0x30330634 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_can_tx_can2_tx: IOMUXC_HDMI_CEC_CAN_TX_CAN2_TX { + pinmux = <0x30330248 4 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_gpio_io_gpio3_io28: IOMUXC_HDMI_CEC_GPIO_IO_GPIO3_IO28 { + pinmux = <0x30330248 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_hdmi_cec_hdmi_cec: IOMUXC_HDMI_CEC_HDMI_CEC_HDMI_CEC { + pinmux = <0x30330248 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_cec_i2c_scl_i2c6_scl: IOMUXC_HDMI_CEC_I2C_SCL_I2C6_SCL { + pinmux = <0x30330248 3 0x303305cc 3 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_can_tx_can1_tx: IOMUXC_HDMI_DDC_SCL_CAN_TX_CAN1_TX { + pinmux = <0x30330240 4 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_gpio_io_gpio3_io26: IOMUXC_HDMI_DDC_SCL_GPIO_IO_GPIO3_IO26 { + pinmux = <0x30330240 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_hdmi_scl_hdmi_scl: IOMUXC_HDMI_DDC_SCL_HDMI_SCL_HDMI_SCL { + pinmux = <0x30330240 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_scl_i2c_scl_i2c5_scl: IOMUXC_HDMI_DDC_SCL_I2C_SCL_I2C5_SCL { + pinmux = <0x30330240 3 0x303305c4 3 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_can_rx_can1_rx: IOMUXC_HDMI_DDC_SDA_CAN_RX_CAN1_RX { + pinmux = <0x30330244 4 0x3033054c 3 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_gpio_io_gpio3_io27: IOMUXC_HDMI_DDC_SDA_GPIO_IO_GPIO3_IO27 { + pinmux = <0x30330244 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_hdmi_sda_hdmi_sda: IOMUXC_HDMI_DDC_SDA_HDMI_SDA_HDMI_SDA { + pinmux = <0x30330244 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_ddc_sda_i2c_sda_i2c5_sda: IOMUXC_HDMI_DDC_SDA_I2C_SDA_I2C5_SDA { + pinmux = <0x30330244 3 0x303305c8 3 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_can_rx_can2_rx: IOMUXC_HDMI_HPD_CAN_RX_CAN2_RX { + pinmux = <0x3033024c 4 0x30330550 3 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_gpio_io_gpio3_io29: IOMUXC_HDMI_HPD_GPIO_IO_GPIO3_IO29 { + pinmux = <0x3033024c 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_hdmi_hpd_hdmi_hpd: IOMUXC_HDMI_HPD_HDMI_HPD_HDMI_HPD { + pinmux = <0x3033024c 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_hdmi_hpd_o_hdmi_hpd_o: IOMUXC_HDMI_HPD_HDMI_HPD_O_HDMI_HPD_O { + pinmux = <0x3033024c 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_hdmi_hpd_i2c_sda_i2c6_sda: IOMUXC_HDMI_HPD_I2C_SDA_I2C6_SDA { + pinmux = <0x3033024c 3 0x303305d0 3 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330200 3 0x30330558 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_qos_mdc_enet_qos_mdc: IOMUXC_I2C1_SCL_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x30330200 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330200 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330200 0 0x303305a4 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330204 3 0x30330560 1 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_qos_mdio_enet_qos_mdio: IOMUXC_I2C1_SDA_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x30330204 1 0x30330590 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330204 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330204 0 0x303305a8 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x30330208 3 0x3033055c 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_qos_1588_event1_aux_in_enet_qos_1588_event1_aux_in: IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_AUX_IN_ENET_QOS_1588_EVENT1_AUX_IN { + pinmux = <0x30330208 4 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_qos_1588_event1_in_enet_qos_1588_event1_in: IOMUXC_I2C2_SCL_ENET_QOS_1588_EVENT1_IN_ENET_QOS_1588_EVENT1_IN { + pinmux = <0x30330208 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x30330208 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x30330208 0 0x303305ac 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330208 2 0x30330608 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x3033020c 3 0x30330564 1 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_qos_1588_event1_out_enet_qos_1588_event1_out: IOMUXC_I2C2_SDA_ENET_QOS_1588_EVENT1_OUT_ENET_QOS_1588_EVENT1_OUT { + pinmux = <0x3033020c 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x3033020c 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x3033020c 0 0x303305b0 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x3033020c 2 0x30330634 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330210 3 0x30330568 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330210 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330210 2 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330210 0 0x303305b4 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330210 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330214 3 0x30330570 2 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330214 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330214 2 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330214 0 0x303305b8 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330214 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x30330218 3 0x3033056c 2 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x30330218 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x30330218 0 0x303305bc 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x30330218 2 0x303305a0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x30330218 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x3033021c 3 0x30330574 2 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x3033021c 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x3033021c 0 0x303305c0 5 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x3033021c 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300e0 6 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300e0 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_isp_fl_trig_isp_fl_trig_0: IOMUXC_NAND_ALE_ISP_FL_TRIG_ISP_FL_TRIG_0 { + pinmux = <0x303300e0 3 0x303305d4 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300e0 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300e0 1 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_sai_tx_bclk_sai3_tx_bclk: IOMUXC_NAND_ALE_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303300e0 2 0x303304e8 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300e0 4 0x303305f8 2 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300e0 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300e4 6 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300e4 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_isp_shutter_trig_isp_shutter_trig_0: IOMUXC_NAND_CE0_B_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_0 { + pinmux = <0x303300e4 3 0x303305dc 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300e4 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300e4 1 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_sai_tx_data_sai3_tx_data0: IOMUXC_NAND_CE0_B_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303300e4 2 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300e4 4 0x303305f8 3 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300e4 4 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300e8 6 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300e8 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e8 4 0x303305bc 2 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300e8 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300e8 1 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300e8 2 0x30330630 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x303300ec 6 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x303300ec 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x303300ec 4 0x303305c0 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x303300ec 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x303300ec 1 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x303300ec 2 0x30330624 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x303300f0 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x303300f0 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x303300f0 4 0x303305b8 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x303300f0 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x303300f0 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x303300f0 2 0x30330628 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x303300f4 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x303300f4 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x303300f4 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_uart_rx_uart4_rx: IOMUXC_NAND_CLE_UART_RX_UART4_RX { + pinmux = <0x303300f4 4 0x30330600 2 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_uart_tx_uart4_rx: IOMUXC_NAND_CLE_UART_TX_UART4_RX { + pinmux = <0x303300f4 4 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x303300f4 2 0x3033062c 1 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x303300f8 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x303300f8 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_isp_flash_trig_isp_flash_trig_0: IOMUXC_NAND_DATA00_ISP_FLASH_TRIG_ISP_FLASH_TRIG_0 { + pinmux = <0x303300f8 3 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x303300f8 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x303300f8 1 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_sai_rx_data_sai3_rx_data0: IOMUXC_NAND_DATA00_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303300f8 2 0x303304e4 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x303300f8 4 0x30330600 3 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x303300f8 4 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x303300fc 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x303300fc 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_isp_prelight_trig_isp_prelight_trig_0: IOMUXC_NAND_DATA01_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_0 { + pinmux = <0x303300fc 3 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x303300fc 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x303300fc 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_sai_tx_sync_sai3_tx_sync: IOMUXC_NAND_DATA01_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303300fc 2 0x303304ec 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x303300fc 4 0x30330600 4 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x303300fc 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330100 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330100 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x303305c0 3 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330100 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330100 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_uart_cts_b_uart4_cts_b: IOMUXC_NAND_DATA02_UART_CTS_B_UART4_CTS_B { + pinmux = <0x30330100 3 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_uart_rts_b_uart4_cts_b: IOMUXC_NAND_DATA02_UART_RTS_B_UART4_CTS_B { + pinmux = <0x30330100 3 0x303305fc 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330100 2 0x30330608 2 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330104 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330104 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_isp_fl_trig_isp_fl_trig_1: IOMUXC_NAND_DATA03_ISP_FL_TRIG_ISP_FL_TRIG_1 { + pinmux = <0x30330104 4 0x303305d8 1 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330104 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330104 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_uart_cts_b_uart4_rts_b: IOMUXC_NAND_DATA03_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330104 3 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_uart_rts_b_uart4_rts_b: IOMUXC_NAND_DATA03_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330104 3 0x303305fc 1 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330104 2 0x30330634 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x30330108 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x30330108 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_isp_shutter_trig_isp_shutter_trig_1: IOMUXC_NAND_DATA04_ISP_SHUTTER_TRIG_ISP_SHUTTER_TRIG_1 { + pinmux = <0x30330108 4 0x303305e0 1 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x30330108 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_a_data_qspi_a_data4: IOMUXC_NAND_DATA04_QSPI_A_DATA_QSPI_A_DATA4 { + pinmux = <0x30330108 3 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x30330108 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330108 2 0x30330610 1 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x3033010c 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x3033010c 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_isp_flash_trig_isp_flash_trig_1: IOMUXC_NAND_DATA05_ISP_FLASH_TRIG_ISP_FLASH_TRIG_1 { + pinmux = <0x3033010c 4 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x3033010c 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_a_data_qspi_a_data5: IOMUXC_NAND_DATA05_QSPI_A_DATA_QSPI_A_DATA5 { + pinmux = <0x3033010c 3 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x3033010c 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x3033010c 2 0x30330614 1 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330110 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330110 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_isp_prelight_trig_isp_prelight_trig_1: IOMUXC_NAND_DATA06_ISP_PRELIGHT_TRIG_ISP_PRELIGHT_TRIG_1 { + pinmux = <0x30330110 4 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330110 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_a_data_qspi_a_data6: IOMUXC_NAND_DATA06_QSPI_A_DATA_QSPI_A_DATA6 { + pinmux = <0x30330110 3 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330110 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330110 2 0x30330618 1 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330114 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330114 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_isp_shutter_open_isp_shutter_open_1: IOMUXC_NAND_DATA07_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_1 { + pinmux = <0x30330114 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330114 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_a_data_qspi_a_data7: IOMUXC_NAND_DATA07_QSPI_A_DATA_QSPI_A_DATA7 { + pinmux = <0x30330114 3 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330114 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330114 2 0x3033061c 1 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x30330118 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x30330118 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x30330118 4 0x303305b4 1 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_isp_shutter_open_isp_shutter_open_0: IOMUXC_NAND_DQS_ISP_SHUTTER_OPEN_ISP_SHUTTER_OPEN_0 { + pinmux = <0x30330118 3 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x30330118 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x30330118 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_sai_mclk_sai3_mclk: IOMUXC_NAND_DQS_SAI_MCLK_SAI3_MCLK { + pinmux = <0x30330118 2 0x303304e0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330120 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330120 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330120 4 0x303305b4 2 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330120 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330120 2 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x3033011c 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x3033011c 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x3033011c 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x3033011c 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_uart_rx_uart4_tx: IOMUXC_NAND_RE_B_UART_RX_UART4_TX { + pinmux = <0x3033011c 4 0x30330600 5 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_uart_tx_uart4_tx: IOMUXC_NAND_RE_B_UART_TX_UART4_TX { + pinmux = <0x3033011c 4 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x3033011c 2 0x30330620 1 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330124 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330124 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330124 4 0x303305b8 2 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330124 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330124 2 0x30330604 1 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x30330128 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x30330128 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_scl_i2c4_scl: IOMUXC_NAND_WP_B_I2C_SCL_I2C4_SCL { + pinmux = <0x30330128 4 0x303305bc 3 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x30330128 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x30330128 2 0x3033060c 1 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_enet_tx_clk_enet1_tx_clk: IOMUXC_SAI1_MCLK_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330198 4 0x30330578 1 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x30330198 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x30330198 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330198 2 0x303304d4 2 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_SAI1_RXC_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033014c 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io1: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO1 { + pinmux = <0x3033014c 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_pdm_clk_pdm_clk: IOMUXC_SAI1_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x3033014c 3 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x3033014c 0 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_SAI1_RXD0_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x30330150 4 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io2: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO2 { + pinmux = <0x30330150 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330150 3 0x303304c0 4 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330150 0 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330150 2 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_SAI1_RXD1_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330154 4 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io3: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO3 { + pinmux = <0x30330154 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330154 3 0x303304c4 4 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330154 0 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_enet_mdc_enet1_mdc: IOMUXC_SAI1_RXD2_ENET_MDC_ENET1_MDC { + pinmux = <0x30330158 4 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io4: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO4 { + pinmux = <0x30330158 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330158 3 0x303304c8 4 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x30330158 0 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_enet_mdio_enet1_mdio: IOMUXC_SAI1_RXD3_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033015c 4 0x3033057c 1 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io5: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO5 { + pinmux = <0x3033015c 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x3033015c 3 0x303304cc 4 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x3033015c 0 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SAI1_RXD4_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330160 4 0x30330580 1 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io6: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO6 { + pinmux = <0x30330160 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330160 2 0x30330518 1 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330160 0 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330160 1 0x30330524 1 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SAI1_RXD5_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330164 4 0x30330584 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io7: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO7 { + pinmux = <0x30330164 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330164 0 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330164 2 0x3033051c 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330164 3 0x303304d0 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330164 1 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_SAI1_RXD6_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330168 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io8: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO8 { + pinmux = <0x30330168 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x30330168 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330168 2 0x30330520 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x30330168 1 0x30330528 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_SAI1_RXD7_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033016c 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io9: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO9 { + pinmux = <0x3033016c 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x3033016c 1 0x30330514 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x3033016c 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033016c 3 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033016c 2 0x303304d8 3 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_SAI1_RXFS_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330148 4 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io0: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO0 { + pinmux = <0x30330148 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330148 0 0x303304d0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_SAI1_TXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x30330174 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330174 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330174 0 0x303304d4 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SAI1_TXD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x30330178 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x30330178 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330178 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SAI1_TXD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x3033017c 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x3033017c 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x3033017c 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_SAI1_TXD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330180 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330180 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330180 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_SAI1_TXD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330184 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330184 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330184 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SAI1_TXD4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330188 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x30330188 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330188 1 0x30330518 2 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330188 2 0x30330524 2 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330188 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_SAI1_TXD5_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x3033018c 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x3033018c 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x3033018c 1 0x3033051c 2 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x3033018c 0 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x3033018c 2 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_enet_rx_er_enet1_rx_er: IOMUXC_SAI1_TXD6_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x30330190 4 0x3033058c 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x30330190 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330190 1 0x30330520 2 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x30330190 0 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x30330190 2 0x30330528 2 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_enet_tx_er_enet1_tx_er: IOMUXC_SAI1_TXD7_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330194 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x30330194 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x30330194 3 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330194 1 0x30330514 2 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x30330194 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SAI1_TXFS_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330170 4 0x30330588 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330170 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330170 0 0x303304d8 4 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_can_rx_can2_rx: IOMUXC_SAI2_MCLK_CAN_RX_CAN2_RX { + pinmux = <0x303301b4 3 0x30330550 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_enet_qos_1588_event3_aux_in_enet_qos_1588_event3_aux_in: IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_AUX_IN_ENET_QOS_1588_EVENT3_AUX_IN { + pinmux = <0x303301b4 4 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_enet_qos_1588_event3_in_enet_qos_1588_event3_in: IOMUXC_SAI2_MCLK_ENET_QOS_1588_EVENT3_IN_ENET_QOS_1588_EVENT3_IN { + pinmux = <0x303301b4 2 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301b4 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301b4 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301b4 6 0x303304e0 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301b4 1 0x303304f0 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_can_tx_can1_tx: IOMUXC_SAI2_RXC_CAN_TX_CAN1_TX { + pinmux = <0x303301a0 3 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301a0 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301a0 6 0x303304c4 5 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301a0 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301a0 1 0x3033050c 2 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301a0 4 0x303305e8 3 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301a0 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_enet_qos_1588_event2_out_enet_qos_1588_event2_out: IOMUXC_SAI2_RXD0_ENET_QOS_1588_EVENT2_OUT_ENET_QOS_1588_EVENT2_OUT { + pinmux = <0x303301a4 2 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301a4 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301a4 6 0x303304cc 5 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301a4 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301a4 3 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301a4 1 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301a4 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301a4 4 0x303305e4 2 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x3033019c 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033019c 6 0x303304c8 5 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x3033019c 3 0x303304dc 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x3033019c 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x3033019c 2 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033019c 1 0x30330510 2 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x3033019c 4 0x303305e8 2 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x3033019c 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_can_rx_can1_rx: IOMUXC_SAI2_TXC_CAN_RX_CAN1_RX { + pinmux = <0x303301ac 3 0x3033054c 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301ac 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301ac 6 0x303304c4 6 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301ac 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301ac 1 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_can_tx_can2_tx: IOMUXC_SAI2_TXD0_CAN_TX_CAN2_TX { + pinmux = <0x303301b0 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_enet_qos_1588_event2_aux_in_enet_qos_1588_event2_aux_in: IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_AUX_IN_ENET_QOS_1588_EVENT2_AUX_IN { + pinmux = <0x303301b0 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_enet_qos_1588_event2_in_enet_qos_1588_event2_in: IOMUXC_SAI2_TXD0_ENET_QOS_1588_EVENT2_IN_ENET_QOS_1588_EVENT2_IN { + pinmux = <0x303301b0 2 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301b0 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301b0 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301b0 1 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_enet_qos_1588_event3_out_enet_qos_1588_event3_out: IOMUXC_SAI2_TXFS_ENET_QOS_1588_EVENT3_OUT_ENET_QOS_1588_EVENT3_OUT { + pinmux = <0x303301a8 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301a8 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301a8 6 0x303304c8 6 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301a8 3 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301a8 1 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301a8 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301a8 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301a8 4 0x303305e4 3 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301d0 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301d0 1 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301d0 0 0x303304e0 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301d0 2 0x303304f0 3 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301d0 6 0x30330544 3 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301d0 4 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301bc 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301bc 3 0x3033059c 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301bc 6 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301bc 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301bc 2 0x303304f4 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data2: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA2 { + pinmux = <0x303301bc 1 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301bc 4 0x303305ec 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301c0 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x303304c4 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai2_rx_data3: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI2_RX_DATA3 { + pinmux = <0x303301c0 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301c0 0 0x303304e4 1 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301c0 2 0x303304f8 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301c0 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301c0 4 0x303305ec 3 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301b8 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301b8 6 0x303304c0 5 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b8 1 0x303304dc 1 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301b8 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301b8 2 0x30330508 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301b8 4 0x30330544 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301c8 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_capture_gpt1_capture1: IOMUXC_SAI3_TXC_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301c8 3 0x30330594 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301c8 6 0x303304c8 7 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301c8 2 0x30330500 2 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301c8 0 0x303304e8 1 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data2: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA2 { + pinmux = <0x303301c8 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301c8 4 0x303305f0 5 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301c8 4 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301cc 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301cc 3 0x30330598 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301cc 2 0x30330504 2 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai2_tx_data3: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI2_TX_DATA3 { + pinmux = <0x303301cc 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301cc 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301cc 4 0x30330548 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301c4 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301c4 6 0x303304cc 6 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301c4 2 0x303304fc 2 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301c4 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301c4 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301c4 0 0x303304ec 1 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301c4 4 0x303305f0 4 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301c4 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_can_rx_can2_rx: IOMUXC_SAI5_MCLK_CAN_RX_CAN2_RX { + pinmux = <0x30330144 6 0x30330550 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330144 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_i2c_sda_i2c5_sda: IOMUXC_SAI5_MCLK_I2C_SDA_I2C5_SDA { + pinmux = <0x30330144 3 0x303305c8 1 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_pwm_out_pwm1_out: IOMUXC_SAI5_MCLK_PWM_OUT_PWM1_OUT { + pinmux = <0x30330144 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330144 0 0x303304f0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330144 1 0x303304d4 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330130 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_i2c_sda_i2c6_sda: IOMUXC_SAI5_RXC_I2C_SDA_I2C6_SDA { + pinmux = <0x30330130 3 0x303305d0 1 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330130 4 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pwm_out_pwm3_out: IOMUXC_SAI5_RXC_PWM_OUT_PWM3_OUT { + pinmux = <0x30330130 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330130 0 0x303304f4 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330130 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330134 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_i2c_scl_i2c5_scl: IOMUXC_SAI5_RXD0_I2C_SCL_I2C5_SCL { + pinmux = <0x30330134 3 0x303305c4 1 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330134 4 0x303304c0 3 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pwm_out_pwm2_out: IOMUXC_SAI5_RXD0_PWM_OUT_PWM2_OUT { + pinmux = <0x30330134 2 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330134 0 0x303304f8 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330134 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_can_tx_can1_tx: IOMUXC_SAI5_RXD1_CAN_TX_CAN1_TX { + pinmux = <0x30330138 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x30330138 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330138 4 0x303304c4 3 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330138 0 0x303304fc 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330138 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330138 2 0x303304d8 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330138 3 0x30330510 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_can_rx_can1_rx: IOMUXC_SAI5_RXD2_CAN_RX_CAN1_RX { + pinmux = <0x3033013c 6 0x3033054c 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x3033013c 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033013c 4 0x303304c8 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033013c 0 0x30330500 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x3033013c 3 0x3033050c 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033013c 1 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033013c 2 0x303304d8 1 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_can_tx_can2_tx: IOMUXC_SAI5_RXD3_CAN_TX_CAN2_TX { + pinmux = <0x30330140 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330140 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330140 4 0x303304cc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330140 0 0x30330504 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330140 1 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330140 3 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330140 2 0x303304d8 2 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x3033012c 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_i2c_scl_i2c6_scl: IOMUXC_SAI5_RXFS_I2C_SCL_I2C6_SCL { + pinmux = <0x3033012c 3 0x303305cc 1 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_pwm_out_pwm4_out: IOMUXC_SAI5_RXFS_PWM_OUT_PWM4_OUT { + pinmux = <0x3033012c 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033012c 0 0x30330508 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033012c 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x3033008c 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x3033008c 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_i2c_scl_i2c5_scl: IOMUXC_SD1_CLK_I2C_SCL_I2C5_SCL { + pinmux = <0x3033008c 3 0x303305c4 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x3033008c 4 0x303305e8 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x3033008c 4 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x3033008c 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330090 1 0x3033057c 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x30330090 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_i2c_sda_i2c5_sda: IOMUXC_SD1_CMD_I2C_SDA_I2C5_SDA { + pinmux = <0x30330090 3 0x303305c8 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x30330090 4 0x303305e8 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x30330090 4 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x30330090 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330094 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x30330094 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_i2c_scl_i2c6_scl: IOMUXC_SD1_DATA0_I2C_SCL_I2C6_SCL { + pinmux = <0x30330094 3 0x303305cc 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330094 4 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330094 4 0x303305e4 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x30330094 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x30330098 1 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x30330098 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_i2c_sda_i2c6_sda: IOMUXC_SD1_DATA1_I2C_SDA_I2C6_SDA { + pinmux = <0x30330098 3 0x303305d0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330098 4 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330098 4 0x303305e4 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x30330098 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x3033009c 1 0x30330580 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x3033009c 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_i2c_scl_i2c4_scl: IOMUXC_SD1_DATA2_I2C_SCL_I2C4_SCL { + pinmux = <0x3033009c 3 0x303305bc 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x3033009c 4 0x303305f0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x3033009c 4 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x3033009c 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300a0 1 0x30330584 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300a0 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_i2c_sda_i2c4_sda: IOMUXC_SD1_DATA3_I2C_SDA_I2C4_SDA { + pinmux = <0x303300a0 3 0x303305c0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300a0 4 0x303305f0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300a0 4 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300a0 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300a4 1 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300a4 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300a4 3 0x303305a4 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300a4 4 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300a4 4 0x303305ec 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300a4 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300a8 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300a8 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300a8 3 0x303305a8 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300a8 4 0x303305ec 1 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300a8 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300ac 1 0x30330588 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300ac 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300ac 3 0x303305ac 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300ac 4 0x303305f8 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300ac 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300ac 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300b0 1 0x3033058c 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300b0 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300b0 3 0x303305b0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300b0 4 0x303305f8 1 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300b0 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300b0 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300b4 1 0x30330578 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300b4 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300b4 3 0x303305b4 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300b4 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300b4 4 0x303305f4 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300b4 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300b8 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300b8 3 0x303305b8 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300b8 4 0x303305f4 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300b8 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300bc 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300bc 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300c0 2 0x30330568 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300c0 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300c0 3 0x30330600 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300c0 3 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300c0 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300c4 2 0x30330570 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300c4 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300c4 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300c4 3 0x30330600 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300c4 3 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300c4 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300c8 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300c8 2 0x303305c0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300c8 4 0x303304c0 2 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300c8 3 0x303305f0 2 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300c8 3 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300c8 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300cc 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300cc 2 0x303305bc 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300cc 4 0x303304c4 2 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300cc 3 0x303305f0 3 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300cc 3 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300cc 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300d0 2 0x30330574 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300d0 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300d0 4 0x303304c8 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300d0 3 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300d0 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300d4 2 0x3033056c 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300d4 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300d4 4 0x303304cc 2 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300d4 3 0x30330544 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300d4 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300d8 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300d8 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300dc 6 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300dc 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300dc 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301dc 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpt_compare_gpt1_compare3: IOMUXC_SPDIF_EXT_CLK_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301dc 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301dc 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301dc 0 0x30330548 1 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_can_rx_can1_rx: IOMUXC_SPDIF_RX_CAN_RX_CAN1_RX { + pinmux = <0x303301d8 4 0x3033054c 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301d8 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpt_compare_gpt1_compare2: IOMUXC_SPDIF_RX_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301d8 3 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_i2c_sda_i2c5_sda: IOMUXC_SPDIF_RX_I2C_SDA_I2C5_SDA { + pinmux = <0x303301d8 2 0x303305c8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301d8 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301d8 0 0x30330544 4 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_can_tx_can1_tx: IOMUXC_SPDIF_TX_CAN_TX_CAN1_TX { + pinmux = <0x303301d4 4 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301d4 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpt_compare_gpt1_compare1: IOMUXC_SPDIF_TX_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_i2c_scl_i2c5_scl: IOMUXC_SPDIF_TX_I2C_SCL_I2C5_SCL { + pinmux = <0x303301d4 2 0x303305c4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301d4 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301d4 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330220 1 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330220 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330220 0 0x303305e8 4 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330220 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330224 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330224 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330224 0 0x303305e8 5 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330224 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x30330228 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x30330228 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x30330228 3 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x30330228 0 0x303305f0 6 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x30330228 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x3033022c 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x3033022c 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x3033022c 3 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x3033022c 0 0x303305f0 7 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x3033022c 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_can_tx_can2_tx: IOMUXC_UART3_RXD_CAN_TX_CAN2_TX { + pinmux = <0x30330230 4 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330230 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330230 3 0x30330598 1 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330230 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330230 1 0x303305e4 4 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330230 0 0x303305f8 6 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330230 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330230 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_can_rx_can2_rx: IOMUXC_UART3_TXD_CAN_RX_CAN2_RX { + pinmux = <0x30330234 4 0x30330550 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330234 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330234 3 0x3033059c 1 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330234 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330234 1 0x303305e4 5 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330234 0 0x303305f8 7 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330234 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330234 2 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x30330238 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x30330238 3 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_i2c_scl_i2c6_scl: IOMUXC_UART4_RXD_I2C_SCL_I2C6_SCL { + pinmux = <0x30330238 4 0x303305cc 2 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x30330238 2 0x303305a0 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x30330238 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x30330238 1 0x303305ec 4 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x30330238 0 0x30330600 8 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x30330238 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x3033023c 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x3033023c 3 0x30330594 1 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_i2c_sda_i2c6_sda: IOMUXC_UART4_TXD_I2C_SDA_I2C6_SDA { + pinmux = <0x3033023c 4 0x303305d0 2 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x3033023c 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x3033023c 1 0x303305ec 5 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x3033023c 0 0x30330600 9 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x3033023c 0 0x0 0 0x3033049c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm1cvtkz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm1cvtkz-pinctrl.dtsi new file mode 100644 index 000000000..3b3ace116 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm1cvtkz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM1CVTKZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm1dvtlz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm1dvtlz-pinctrl.dtsi new file mode 100644 index 000000000..43b850c4d --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm1dvtlz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM1DVTLZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm2cvtkz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm2cvtkz-pinctrl.dtsi new file mode 100644 index 000000000..8a6e4204e --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm2cvtkz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM2CVTKZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm2dvtlz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm2dvtlz-pinctrl.dtsi new file mode 100644 index 000000000..8b97607d6 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm2dvtlz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM2DVTLZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm3cvtkz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm3cvtkz-pinctrl.dtsi new file mode 100644 index 000000000..bdd783b06 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm3cvtkz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM3CVTKZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm3dvtlz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm3dvtlz-pinctrl.dtsi new file mode 100644 index 000000000..dbb9cd212 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm3dvtlz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM3DVTLZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm4cvtkz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm4cvtkz-pinctrl.dtsi new file mode 100644 index 000000000..e895bd52a --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm4cvtkz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM4CVTKZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm4dvtlz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm4dvtlz-pinctrl.dtsi new file mode 100644 index 000000000..f01948747 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm4dvtlz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM4DVTLZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm5cvtkz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm5cvtkz-pinctrl.dtsi new file mode 100644 index 000000000..4f8686e17 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm5cvtkz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM5CVTKZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm5dvtlz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm5dvtlz-pinctrl.dtsi new file mode 100644 index 000000000..d2be9696e --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm5dvtlz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM5DVTLZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mm6cvtkz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mm6cvtkz-pinctrl.dtsi new file mode 100644 index 000000000..ae54b8315 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mm6cvtkz-pinctrl.dtsi @@ -0,0 +1,1648 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MM6CVTKZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330544 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x30330548 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330544 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x30330548 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_rawnand_ale_rawnand_ale: IOMUXC_NAND_ALE_RAWNAND_ALE_RAWNAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_rawnand_ce0_b_rawnand_ce0_b: IOMUXC_NAND_CE0_B_RAWNAND_CE0_B_RAWNAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_rawnand_ce1_b_rawnand_ce1_b: IOMUXC_NAND_CE1_B_RAWNAND_CE1_B_RAWNAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_rawnand_ce2_b_rawnand_ce2_b: IOMUXC_NAND_CE2_B_RAWNAND_CE2_B_RAWNAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_rawnand_ce3_b_rawnand_ce3_b: IOMUXC_NAND_CE3_B_RAWNAND_CE3_B_RAWNAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_rawnand_cle_rawnand_cle: IOMUXC_NAND_CLE_RAWNAND_CLE_RAWNAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_rawnand_data_rawnand_data00: IOMUXC_NAND_DATA00_RAWNAND_DATA_RAWNAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_rawnand_data_rawnand_data01: IOMUXC_NAND_DATA01_RAWNAND_DATA_RAWNAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_rawnand_data_rawnand_data02: IOMUXC_NAND_DATA02_RAWNAND_DATA_RAWNAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330544 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_rawnand_data_rawnand_data03: IOMUXC_NAND_DATA03_RAWNAND_DATA_RAWNAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x30330548 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_rawnand_data_rawnand_data04: IOMUXC_NAND_DATA04_RAWNAND_DATA_RAWNAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_rawnand_data_rawnand_data05: IOMUXC_NAND_DATA05_RAWNAND_DATA_RAWNAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_rawnand_data_rawnand_data06: IOMUXC_NAND_DATA06_RAWNAND_DATA_RAWNAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_rawnand_data_rawnand_data07: IOMUXC_NAND_DATA07_RAWNAND_DATA_RAWNAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_rawnand_dqs_rawnand_dqs: IOMUXC_NAND_DQS_RAWNAND_DQS_RAWNAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_rawnand_ready_b_rawnand_ready_b: IOMUXC_NAND_READY_B_RAWNAND_READY_B_RAWNAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_rawnand_re_b_rawnand_re_b: IOMUXC_NAND_RE_B_RAWNAND_RE_B_RAWNAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_rawnand_we_b_rawnand_we_b: IOMUXC_NAND_WE_B_RAWNAND_WE_B_RAWNAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_rawnand_wp_b_rawnand_wp_b: IOMUXC_NAND_WP_B_RAWNAND_WP_B_RAWNAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_pdm_clk_pdm_clk: IOMUXC_SAI1_MCLK_PDM_CLK_PDM_CLK { + pinmux = <0x303301ac 3 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI1_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330164 3 0x30330534 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_RXD0_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330164 2 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI1_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330168 3 0x30330538 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI1_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033016c 3 0x3033053c 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI1_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330170 3 0x30330540 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_pdm_clk_pdm_clk: IOMUXC_SAI1_TXD7_PDM_CLK_PDM_CLK { + pinmux = <0x303301a8 3 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_src_early_reset_src_early_reset: IOMUXC_SD2_DATA3_SRC_EARLY_RESET_SRC_EARLY_RESET { + pinmux = <0x303300e8 6 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_src_system_reset_src_system_reset: IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET_SRC_SYSTEM_RESET { + pinmux = <0x303300ec 6 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn1cvpiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn1cvpiz-pinctrl.dtsi new file mode 100644 index 000000000..02e92f5e6 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn1cvpiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN1CVPIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn1cvtiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn1cvtiz-pinctrl.dtsi new file mode 100644 index 000000000..fc844c60a --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn1cvtiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN1CVTIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn1dvpiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn1dvpiz-pinctrl.dtsi new file mode 100644 index 000000000..8bf1aac35 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn1dvpiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN1DVPIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn1dvtjz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn1dvtjz-pinctrl.dtsi new file mode 100644 index 000000000..707ddcced --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn1dvtjz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN1DVTJZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn2cvtiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn2cvtiz-pinctrl.dtsi new file mode 100644 index 000000000..db7931f95 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn2cvtiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN2CVTIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn2dvtjz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn2dvtjz-pinctrl.dtsi new file mode 100644 index 000000000..95e0915f6 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn2dvtjz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN2DVTJZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn3cvpiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn3cvpiz-pinctrl.dtsi new file mode 100644 index 000000000..6b50e57b9 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn3cvpiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN3CVPIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn3cvtiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn3cvtiz-pinctrl.dtsi new file mode 100644 index 000000000..de0224b6a --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn3cvtiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN3CVTIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn3dvpiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn3dvpiz-pinctrl.dtsi new file mode 100644 index 000000000..fe60a0d4a --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn3dvpiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN3DVPIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn3dvtjz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn3dvtjz-pinctrl.dtsi new file mode 100644 index 000000000..b864ff2c4 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn3dvtjz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN3DVTJZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn4cvtiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn4cvtiz-pinctrl.dtsi new file mode 100644 index 000000000..cbc757dc8 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn4cvtiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN4CVTIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn4dvtjz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn4dvtjz-pinctrl.dtsi new file mode 100644 index 000000000..c13fe5b16 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn4dvtjz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN4DVTJZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn5cvpiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn5cvpiz-pinctrl.dtsi new file mode 100644 index 000000000..aaf49c575 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn5cvpiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN5CVPIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn5cvtiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn5cvtiz-pinctrl.dtsi new file mode 100644 index 000000000..14e092730 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn5cvtiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN5CVTIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn5dvpiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn5dvpiz-pinctrl.dtsi new file mode 100644 index 000000000..4dc5a99a5 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn5dvpiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN5DVPIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn5dvtjz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn5dvtjz-pinctrl.dtsi new file mode 100644 index 000000000..789097573 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn5dvtjz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN5DVTJZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mn6cvtiz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mn6cvtiz-pinctrl.dtsi new file mode 100644 index 000000000..bef59fd06 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mn6cvtiz-pinctrl.dtsi @@ -0,0 +1,1894 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MN6CVTIZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_i2c_scl_i2c1_scl: IOMUXC_BOOT_MODE2_I2C_SCL_I2C1_SCL { + pinmux = <0x30330020 1 0x3033055c 3 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode2_src_boot_mode_src_boot_mode2: IOMUXC_BOOT_MODE2_SRC_BOOT_MODE_SRC_BOOT_MODE2 { + pinmux = <0x30330020 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_i2c_sda_i2c1_sda: IOMUXC_BOOT_MODE3_I2C_SDA_I2C1_SDA { + pinmux = <0x30330024 1 0x3033056c 3 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_boot_mode3_src_boot_mode_src_boot_mode3: IOMUXC_BOOT_MODE3_SRC_BOOT_MODE_SRC_BOOT_MODE3 { + pinmux = <0x30330024 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x303305c4 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io8: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO8 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_i2c_scl_i2c2_scl: IOMUXC_ECSPI1_MISO_I2C_SCL_I2C2_SCL { + pinmux = <0x303301fc 2 0x303305d0 2 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_sai_rx_data_sai5_rx_data0: IOMUXC_ECSPI1_MISO_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301fc 3 0x303304d4 3 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x303305a8 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io7: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO7 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_i2c_sda_i2c1_sda: IOMUXC_ECSPI1_MOSI_I2C_SDA_I2C1_SDA { + pinmux = <0x303301f8 2 0x3033056c 2 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_sai_rx_bclk_sai5_rx_bclk: IOMUXC_ECSPI1_MOSI_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301f8 3 0x303304d0 3 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x303305d8 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io6: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO6 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_i2c_scl_i2c1_scl: IOMUXC_ECSPI1_SCLK_I2C_SCL_I2C1_SCL { + pinmux = <0x303301f4 2 0x3033055c 2 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_sai_rx_sync_sai5_rx_sync: IOMUXC_ECSPI1_SCLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301f4 3 0x303304e4 3 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x30330564 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io9: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO9 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_i2c_sda_i2c2_sda: IOMUXC_ECSPI1_SS0_I2C_SDA_I2C2_SDA { + pinmux = <0x30330200 2 0x30330560 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_rx_data_sai5_rx_data1: IOMUXC_ECSPI1_SS0_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330200 3 0x303304d8 2 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_sai_tx_sync_sai5_tx_sync: IOMUXC_ECSPI1_SS0_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330200 4 0x303304ec 3 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x30330578 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_i2c_scl_i2c4_scl: IOMUXC_ECSPI2_MISO_I2C_SCL_I2C4_SCL { + pinmux = <0x3033020c 2 0x303305d4 3 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_sai_mclk_sai5_mclk: IOMUXC_ECSPI2_MISO_SAI_MCLK_SAI5_MCLK { + pinmux = <0x3033020c 3 0x30330594 4 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x30330590 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_i2c_sda_i2c3_sda: IOMUXC_ECSPI2_MOSI_I2C_SDA_I2C3_SDA { + pinmux = <0x30330208 2 0x303305bc 4 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_rx_data_sai5_rx_data3: IOMUXC_ECSPI2_MOSI_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330208 3 0x303304e0 2 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_sai_tx_data_sai5_tx_data0: IOMUXC_ECSPI2_MOSI_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330208 4 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x30330580 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_i2c_scl_i2c3_scl: IOMUXC_ECSPI2_SCLK_I2C_SCL_I2C3_SCL { + pinmux = <0x30330204 2 0x30330588 4 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_rx_data_sai5_rx_data2: IOMUXC_ECSPI2_SCLK_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330204 3 0x303304dc 2 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_sai_tx_bclk_sai5_tx_bclk: IOMUXC_ECSPI2_SCLK_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330204 4 0x303304e8 3 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x30330570 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_i2c_sda_i2c4_sda: IOMUXC_ECSPI2_SS0_I2C_SDA_I2C4_SDA { + pinmux = <0x30330210 2 0x3033058c 5 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_MDC_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330068 3 0x30330540 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_sai_tx_data_sai6_tx_data0: IOMUXC_ENET_MDC_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330068 2 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_spdif_out_spdif1_out: IOMUXC_ENET_MDC_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x30330068 4 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_usdhc_strobe_usdhc3_strobe: IOMUXC_ENET_MDC_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x30330068 6 0x3033059c 1 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_MDIO_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033006c 3 0x3033053c 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_sai_tx_sync_sai6_tx_sync: IOMUXC_ENET_MDIO_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033006c 2 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_spdif_in_spdif1_in: IOMUXC_ENET_MDIO_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033006c 4 0x303305cc 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_usdhc_data_usdhc3_data5: IOMUXC_ENET_MDIO_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x3033006c 6 0x30330550 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x3033057c 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_RD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330090 3 0x30330538 3 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_sai_rx_data_sai7_rx_data0: IOMUXC_ENET_RD0_SAI_RX_DATA_SAI7_RX_DATA0 { + pinmux = <0x30330090 2 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_usdhc_data_usdhc3_data4: IOMUXC_ENET_RD0_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330090 6 0x30330558 1 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x30330554 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_pdm_bit_stream_pdm_bit_stream0: IOMUXC_ENET_RD1_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330094 3 0x30330534 1 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_sai_rx_sync_sai7_rx_sync: IOMUXC_ENET_RD1_SAI_RX_SYNC_SAI7_RX_SYNC { + pinmux = <0x30330094 2 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_usdhc_reset_b_usdhc3_reset_b: IOMUXC_ENET_RD1_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330094 6 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_pdm_clk_pdm_clk: IOMUXC_ENET_RD2_PDM_CLK_PDM_CLK { + pinmux = <0x30330098 3 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_sai_rx_bclk_sai7_rx_bclk: IOMUXC_ENET_RD2_SAI_RX_BCLK_SAI7_RX_BCLK { + pinmux = <0x30330098 2 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_usdhc_clk_usdhc3_clk: IOMUXC_ENET_RD2_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330098 6 0x303305a0 1 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_sai_mclk_sai7_mclk: IOMUXC_ENET_RD3_SAI_MCLK_SAI7_MCLK { + pinmux = <0x3033009c 2 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_spdif_in_spdif1_in: IOMUXC_ENET_RD3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x3033009c 3 0x303305cc 5 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_usdhc_cmd_usdhc3_cmd: IOMUXC_ENET_RD3_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033009c 6 0x303305dc 1 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x303305c8 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033008c 3 0x3033053c 3 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_sai_tx_bclk_sai7_tx_bclk: IOMUXC_ENET_RXC_SAI_TX_BCLK_SAI7_TX_BCLK { + pinmux = <0x3033008c 2 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_usdhc_data_usdhc3_data3: IOMUXC_ENET_RXC_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x3033008c 6 0x303305e0 1 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x30330574 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330088 3 0x30330540 3 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_sai_tx_sync_sai7_tx_sync: IOMUXC_ENET_RX_CTL_SAI_TX_SYNC_SAI7_TX_SYNC { + pinmux = <0x30330088 2 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_usdhc_data_usdhc3_data2: IOMUXC_ENET_RX_CTL_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330088 6 0x303305e4 1 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD0_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033007c 3 0x30330538 2 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_sai_rx_bclk_sai6_rx_bclk: IOMUXC_ENET_TD0_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033007c 2 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_usdhc_wp_usdhc3_wp: IOMUXC_ENET_TD0_USDHC_WP_USDHC3_WP { + pinmux = <0x3033007c 6 0x303305b8 3 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_pdm_bit_stream_pdm_bit_stream2: IOMUXC_ENET_TD1_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330078 3 0x3033053c 2 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_sai_rx_sync_sai6_rx_sync: IOMUXC_ENET_TD1_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x30330078 2 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_usdhc_cd_b_usdhc3_cd_b: IOMUXC_ENET_TD1_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330078 6 0x30330598 3 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x303305a4 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_pdm_bit_stream_pdm_bit_stream3: IOMUXC_ENET_TD2_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330074 3 0x30330540 2 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_sai_rx_data_sai6_rx_data0: IOMUXC_ENET_TD2_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330074 2 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_usdhc_data_usdhc3_data7: IOMUXC_ENET_TD2_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330074 6 0x3033054c 1 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_pdm_bit_stream_pdm_bit_stream1: IOMUXC_ENET_TD3_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330070 3 0x30330538 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_sai_tx_bclk_sai6_tx_bclk: IOMUXC_ENET_TD3_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330070 2 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_spdif_ext_clk_spdif1_ext_clk: IOMUXC_ENET_TD3_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x30330070 4 0x30330568 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_usdhc_data_usdhc3_data6: IOMUXC_ENET_TD3_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330070 6 0x30330584 1 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_sai_tx_data_sai7_tx_data0: IOMUXC_ENET_TXC_SAI_TX_DATA_SAI7_TX_DATA0 { + pinmux = <0x30330084 2 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_usdhc_data_usdhc3_data1: IOMUXC_ENET_TXC_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330084 6 0x303305b0 1 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_sai_mclk_sai6_mclk: IOMUXC_ENET_TX_CTL_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330080 2 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_usdhc_data_usdhc3_data0: IOMUXC_ENET_TX_CTL_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x30330080 6 0x303305b4 1 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ref_clk_32k_ccm_ref_clk_32k: IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K_CCM_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io0: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO0 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ref_clk_24m_ccm_ref_clk_24m: IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M_CCM_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io1: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO1 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io2: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO2 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_sjc_de_b_sjc_de_b: IOMUXC_GPIO1_IO02_SJC_DE_B_SJC_DE_B { + pinmux = <0x30330030 7 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io3: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO3 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io4: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO4 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io5: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO5 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m7_nmi_m7_nmi: IOMUXC_GPIO1_IO05_M7_NMI_M7_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io6: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO6 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io7: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO7 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io8: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO8 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_pwm_out_pwm1_out: IOMUXC_GPIO1_IO08_PWM_OUT_PWM1_OUT { + pinmux = <0x30330048 2 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io9: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO9 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_pwm_out_pwm2_out: IOMUXC_GPIO1_IO09_PWM_OUT_PWM2_OUT { + pinmux = <0x3033004c 2 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_usdhc_reset_b_usdhc3_reset_b: IOMUXC_GPIO1_IO09_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x3033004c 4 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_pwm_out_pwm3_out: IOMUXC_GPIO1_IO10_PWM_OUT_PWM3_OUT { + pinmux = <0x30330050 2 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_pwm_out_pwm2_out: IOMUXC_GPIO1_IO11_PWM_OUT_PWM2_OUT { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usdhc_vselect_usdhc3_vselect: IOMUXC_GPIO1_IO11_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330054 4 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usdhc_cd_b_usdhc3_cd_b: IOMUXC_GPIO1_IO14_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330060 4 0x30330598 2 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usdhc_wp_usdhc3_wp: IOMUXC_GPIO1_IO15_USDHC_WP_USDHC3_WP { + pinmux = <0x30330064 4 0x303305b8 2 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_ecspi_sclk_ecspi1_sclk: IOMUXC_I2C1_SCL_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x30330214 3 0x303305d8 1 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x3033055c 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_ecspi_mosi_ecspi1_mosi: IOMUXC_I2C1_SDA_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x30330218 3 0x303305a8 1 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x3033056c 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_ecspi_miso_ecspi1_miso: IOMUXC_I2C2_SCL_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x3033021c 3 0x303305c4 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x303305d0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_usdhc_cd_b_usdhc3_cd_b: IOMUXC_I2C2_SCL_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x3033021c 2 0x30330598 1 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_ecspi_ss_ecspi1_ss0: IOMUXC_I2C2_SDA_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330220 3 0x30330564 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x30330560 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_usdhc_wp_usdhc3_wp: IOMUXC_I2C2_SDA_USDHC_WP_USDHC3_WP { + pinmux = <0x30330220 2 0x303305b8 1 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_ecspi_sclk_ecspi2_sclk: IOMUXC_I2C3_SCL_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330224 3 0x30330580 2 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x30330588 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_ecspi_mosi_ecspi2_mosi: IOMUXC_I2C3_SDA_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330228 3 0x30330590 2 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x303305bc 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_ecspi_miso_ecspi2_miso: IOMUXC_I2C4_SCL_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033022c 3 0x30330578 2 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x303305d4 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_ecspi_ss_ecspi2_ss0: IOMUXC_I2C4_SDA_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330230 3 0x30330570 1 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x3033058c 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_coresight_trace_clk_coresight_trace_clk: IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK_CORESIGHT_TRACE_CLK { + pinmux = <0x303300f4 6 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io0: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO0 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_ALE_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300f4 3 0x30330534 3 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_rx_uart3_rx: IOMUXC_NAND_ALE_UART_RX_UART3_RX { + pinmux = <0x303300f4 4 0x30330504 6 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_uart_tx_uart3_rx: IOMUXC_NAND_ALE_UART_TX_UART3_RX { + pinmux = <0x303300f4 4 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_coresight_trace_ctl_coresight_trace_ctl: IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL_CORESIGHT_TRACE_CTL { + pinmux = <0x303300f8 6 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io1: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO1 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE0_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300f8 3 0x30330538 5 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_rx_uart3_tx: IOMUXC_NAND_CE0_B_UART_RX_UART3_TX { + pinmux = <0x303300f8 4 0x30330504 7 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_uart_tx_uart3_tx: IOMUXC_NAND_CE0_B_UART_TX_UART3_TX { + pinmux = <0x303300f8 4 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_coresight_trace_coresight_trace0: IOMUXC_NAND_CE1_B_CORESIGHT_TRACE_CORESIGHT_TRACE0 { + pinmux = <0x303300fc 6 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io2: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO2 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_i2c_scl_i2c4_scl: IOMUXC_NAND_CE1_B_I2C_SCL_I2C4_SCL { + pinmux = <0x303300fc 4 0x303305d4 2 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_pdm_bit_stream_pdm_bit_stream0: IOMUXC_NAND_CE1_B_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300fc 3 0x30330534 4 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_usdhc_strobe_usdhc3_strobe: IOMUXC_NAND_CE1_B_USDHC_STROBE_USDHC3_STROBE { + pinmux = <0x303300fc 2 0x3033059c 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_coresight_trace_coresight_trace1: IOMUXC_NAND_CE2_B_CORESIGHT_TRACE_CORESIGHT_TRACE1 { + pinmux = <0x30330100 6 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io3: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO3 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_i2c_sda_i2c4_sda: IOMUXC_NAND_CE2_B_I2C_SDA_I2C4_SDA { + pinmux = <0x30330100 4 0x3033058c 2 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_CE2_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330100 3 0x30330538 6 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_usdhc_data_usdhc3_data5: IOMUXC_NAND_CE2_B_USDHC_DATA_USDHC3_DATA5 { + pinmux = <0x30330100 2 0x30330550 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_coresight_trace_coresight_trace2: IOMUXC_NAND_CE3_B_CORESIGHT_TRACE_CORESIGHT_TRACE2 { + pinmux = <0x30330104 6 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io4: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO4 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_i2c_sda_i2c3_sda: IOMUXC_NAND_CE3_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330104 4 0x303305bc 2 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_CE3_B_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330104 3 0x3033053c 5 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_usdhc_data_usdhc3_data6: IOMUXC_NAND_CE3_B_USDHC_DATA_USDHC3_DATA6 { + pinmux = <0x30330104 2 0x30330584 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_coresight_trace_coresight_trace3: IOMUXC_NAND_CLE_CORESIGHT_TRACE_CORESIGHT_TRACE3 { + pinmux = <0x30330108 6 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io5: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO5 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_usdhc_data_usdhc3_data7: IOMUXC_NAND_CLE_USDHC_DATA_USDHC3_DATA7 { + pinmux = <0x30330108 2 0x3033054c 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_coresight_trace_coresight_trace4: IOMUXC_NAND_DATA00_CORESIGHT_TRACE_CORESIGHT_TRACE4 { + pinmux = <0x3033010c 6 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io6: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO6 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_pdm_bit_stream_pdm_bit_stream2: IOMUXC_NAND_DATA00_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x3033010c 3 0x3033053c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_rx_uart4_rx: IOMUXC_NAND_DATA00_UART_RX_UART4_RX { + pinmux = <0x3033010c 4 0x3033050c 6 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_uart_tx_uart4_rx: IOMUXC_NAND_DATA00_UART_TX_UART4_RX { + pinmux = <0x3033010c 4 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_coresight_trace_coresight_trace5: IOMUXC_NAND_DATA01_CORESIGHT_TRACE_CORESIGHT_TRACE5 { + pinmux = <0x30330110 6 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io7: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO7 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_DATA01_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330110 3 0x30330540 5 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_rx_uart4_tx: IOMUXC_NAND_DATA01_UART_RX_UART4_TX { + pinmux = <0x30330110 4 0x3033050c 7 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_uart_tx_uart4_tx: IOMUXC_NAND_DATA01_UART_TX_UART4_TX { + pinmux = <0x30330110 4 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_coresight_trace_coresight_trace6: IOMUXC_NAND_DATA02_CORESIGHT_TRACE_CORESIGHT_TRACE6 { + pinmux = <0x30330114 6 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io8: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO8 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_i2c_sda_i2c4_sda: IOMUXC_NAND_DATA02_I2C_SDA_I2C4_SDA { + pinmux = <0x30330114 4 0x3033058c 3 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_usdhc_cd_b_usdhc3_cd_b: IOMUXC_NAND_DATA02_USDHC_CD_B_USDHC3_CD_B { + pinmux = <0x30330114 2 0x30330598 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_coresight_trace_coresight_trace7: IOMUXC_NAND_DATA03_CORESIGHT_TRACE_CORESIGHT_TRACE7 { + pinmux = <0x30330118 6 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io9: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO9 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_usdhc_wp_usdhc3_wp: IOMUXC_NAND_DATA03_USDHC_WP_USDHC3_WP { + pinmux = <0x30330118 2 0x303305b8 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_coresight_trace_coresight_trace8: IOMUXC_NAND_DATA04_CORESIGHT_TRACE_CORESIGHT_TRACE8 { + pinmux = <0x3033011c 6 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_usdhc_data_usdhc3_data0: IOMUXC_NAND_DATA04_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x3033011c 2 0x303305b4 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_coresight_trace_coresight_trace9: IOMUXC_NAND_DATA05_CORESIGHT_TRACE_CORESIGHT_TRACE9 { + pinmux = <0x30330120 6 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_usdhc_data_usdhc3_data1: IOMUXC_NAND_DATA05_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x30330120 2 0x303305b0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_coresight_trace_coresight_trace10: IOMUXC_NAND_DATA06_CORESIGHT_TRACE_CORESIGHT_TRACE10 { + pinmux = <0x30330124 6 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_usdhc_data_usdhc3_data2: IOMUXC_NAND_DATA06_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x30330124 2 0x303305e4 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_coresight_trace_coresight_trace11: IOMUXC_NAND_DATA07_CORESIGHT_TRACE_CORESIGHT_TRACE11 { + pinmux = <0x30330128 6 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_usdhc_data_usdhc3_data3: IOMUXC_NAND_DATA07_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x30330128 2 0x303305e0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_coresight_trace_coresight_trace12: IOMUXC_NAND_DQS_CORESIGHT_TRACE_CORESIGHT_TRACE12 { + pinmux = <0x3033012c 6 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_i2c_scl_i2c3_scl: IOMUXC_NAND_DQS_I2C_SCL_I2C3_SCL { + pinmux = <0x3033012c 4 0x30330588 2 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_pdm_clk_pdm_clk: IOMUXC_NAND_DQS_PDM_CLK_PDM_CLK { + pinmux = <0x3033012c 3 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_coresight_trace_coresight_trace14: IOMUXC_NAND_READY_B_CORESIGHT_TRACE_CORESIGHT_TRACE14 { + pinmux = <0x30330134 6 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_i2c_scl_i2c3_scl: IOMUXC_NAND_READY_B_I2C_SCL_I2C3_SCL { + pinmux = <0x30330134 4 0x30330588 3 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_pdm_bit_stream_pdm_bit_stream3: IOMUXC_NAND_READY_B_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330134 3 0x30330540 6 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_usdhc_reset_b_usdhc3_reset_b: IOMUXC_NAND_READY_B_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330134 2 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_coresight_trace_coresight_trace13: IOMUXC_NAND_RE_B_CORESIGHT_TRACE_CORESIGHT_TRACE13 { + pinmux = <0x30330130 6 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_pdm_bit_stream_pdm_bit_stream1: IOMUXC_NAND_RE_B_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x30330130 3 0x30330538 7 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_usdhc_data_usdhc3_data4: IOMUXC_NAND_RE_B_USDHC_DATA_USDHC3_DATA4 { + pinmux = <0x30330130 2 0x30330558 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_coresight_trace_coresight_trace15: IOMUXC_NAND_WE_B_CORESIGHT_TRACE_CORESIGHT_TRACE15 { + pinmux = <0x30330138 6 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_i2c_sda_i2c3_sda: IOMUXC_NAND_WE_B_I2C_SDA_I2C3_SDA { + pinmux = <0x30330138 4 0x303305bc 3 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_usdhc_clk_usdhc3_clk: IOMUXC_NAND_WE_B_USDHC_CLK_USDHC3_CLK { + pinmux = <0x30330138 2 0x303305a0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_coresight_evento_coresight_evento: IOMUXC_NAND_WP_B_CORESIGHT_EVENTO_CORESIGHT_EVENTO { + pinmux = <0x3033013c 6 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_i2c_sda_i2c4_sda: IOMUXC_NAND_WP_B_I2C_SDA_I2C4_SDA { + pinmux = <0x3033013c 4 0x3033058c 4 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_usdhc_cmd_usdhc3_cmd: IOMUXC_NAND_WP_B_USDHC_CMD_USDHC3_CMD { + pinmux = <0x3033013c 2 0x303305dc 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301c8 6 0x303305c0 1 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x30330594 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_RXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301b4 6 0x30330538 8 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_rx_uart1_rx: IOMUXC_SAI2_RXC_UART_RX_UART1_RX { + pinmux = <0x303301b4 4 0x303304f4 3 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_uart_tx_uart1_rx: IOMUXC_SAI2_RXC_UART_TX_UART1_RX { + pinmux = <0x303301b4 4 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI2_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301b8 6 0x30330540 7 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301b8 3 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_cts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b: IOMUXC_SAI2_RXD0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303301b8 4 0x303304f0 2 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301b0 6 0x3033053c 7 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_data_sai2_rx_data1: IOMUXC_SAI2_RXFS_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301b0 3 0x303305ac 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_RXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301b0 2 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_rx_uart1_tx: IOMUXC_SAI2_RXFS_UART_RX_UART1_TX { + pinmux = <0x303301b0 4 0x303304f4 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_uart_tx_uart1_tx: IOMUXC_SAI2_RXFS_UART_TX_UART1_TX { + pinmux = <0x303301b0 4 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI2_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301c0 6 0x30330538 9 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_src_boot_mode_src_boot_mode4: IOMUXC_SAI2_TXD0_SRC_BOOT_MODE_SRC_BOOT_MODE4 { + pinmux = <0x303301c4 6 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI2_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301bc 6 0x3033053c 8 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai2_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301bc 3 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_uart_rts_b_uart1_cts_b: IOMUXC_SAI2_TXFS_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303301bc 4 0x303304f0 3 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io2: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO2 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x303305c0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x30330594 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_in_spdif1_in: IOMUXC_SAI3_MCLK_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301e4 6 0x303305cc 4 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_spdif_out_spdif1_out: IOMUXC_SAI3_MCLK_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e4 4 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_clk_gpt1_clk: IOMUXC_SAI3_RXC_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d0 1 0x303305e8 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_pdm_clk_pdm_clk: IOMUXC_SAI3_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x303301d0 6 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_data_sai2_rx_data1: IOMUXC_SAI3_RXC_SAI_RX_DATA_SAI2_RX_DATA1 { + pinmux = <0x303301d0 3 0x303305ac 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_cts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_uart_rts_b_uart2_cts_b: IOMUXC_SAI3_RXC_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303301d0 4 0x303304f8 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI3_RXD_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303301d4 6 0x30330538 10 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_RXD_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d4 3 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b: IOMUXC_SAI3_RXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303301d4 4 0x303304f8 3 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x303305f0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI3_RXFS_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303301cc 6 0x30330534 5 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_data_sai3_rx_data1: IOMUXC_SAI3_RXFS_SAI_RX_DATA_SAI3_RX_DATA1 { + pinmux = <0x303301cc 3 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_spdif_in_spdif1_in: IOMUXC_SAI3_RXFS_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301cc 4 0x303305cc 3 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io0: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO0 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI3_TXC_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303301dc 6 0x3033053c 9 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 1 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_data_sai2_tx_data1: IOMUXC_SAI3_TXC_SAI_TX_DATA_SAI2_TX_DATA1 { + pinmux = <0x303301dc 3 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_rx_uart2_tx: IOMUXC_SAI3_TXC_UART_RX_UART2_TX { + pinmux = <0x303301dc 4 0x303304fc 3 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_uart_tx_uart2_tx: IOMUXC_SAI3_TXC_UART_TX_UART2_TX { + pinmux = <0x303301dc 4 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io1: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO1 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 1 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SAI3_TXD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301e0 4 0x30330568 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_src_boot_mode_src_boot_mode5: IOMUXC_SAI3_TXD_SRC_BOOT_MODE_SRC_BOOT_MODE5 { + pinmux = <0x303301e0 6 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_capture_gpt1_capture2: IOMUXC_SAI3_TXFS_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d8 1 0x303305ec 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI3_TXFS_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303301d8 6 0x30330540 9 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 1 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_data_sai3_tx_data1: IOMUXC_SAI3_TXFS_SAI_TX_DATA_SAI3_TX_DATA1 { + pinmux = <0x303301d8 3 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_rx_uart2_rx: IOMUXC_SAI3_TXFS_UART_RX_UART2_RX { + pinmux = <0x303301d8 4 0x303304fc 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_uart_tx_uart2_rx: IOMUXC_SAI3_TXFS_UART_TX_UART2_RX { + pinmux = <0x303301d8 4 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x30330594 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_pdm_clk_pdm_clk: IOMUXC_SAI5_RXC_PDM_CLK_PDM_CLK { + pinmux = <0x30330144 4 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SAI5_RXD0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x30330148 4 0x30330534 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SAI5_RXD1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x3033014c 4 0x30330538 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SAI5_RXD2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x30330150 4 0x3033053c 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SAI5_RXD3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x30330154 4 0x30330540 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_enet_mdc_enet1_mdc: IOMUXC_SD1_CLK_ENET_MDC_ENET1_MDC { + pinmux = <0x303300a0 1 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io0: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO0 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_rx_uart1_tx: IOMUXC_SD1_CLK_UART_RX_UART1_TX { + pinmux = <0x303300a0 4 0x303304f4 4 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_uart_tx_uart1_tx: IOMUXC_SD1_CLK_UART_TX_UART1_TX { + pinmux = <0x303300a0 4 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_enet_mdio_enet1_mdio: IOMUXC_SD1_CMD_ENET_MDIO_ENET1_MDIO { + pinmux = <0x303300a4 1 0x303304c0 3 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io1: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO1 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_rx_uart1_rx: IOMUXC_SD1_CMD_UART_RX_UART1_RX { + pinmux = <0x303300a4 4 0x303304f4 5 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_uart_tx_uart1_rx: IOMUXC_SD1_CMD_UART_TX_UART1_RX { + pinmux = <0x303300a4 4 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_SD1_DATA0_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x303300a8 1 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io2: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO2 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_cts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_CTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_uart_rts_b_uart1_rts_b: IOMUXC_SD1_DATA0_UART_RTS_B_UART1_RTS_B { + pinmux = <0x303300a8 4 0x303304f0 4 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_SD1_DATA1_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x303300ac 1 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io3: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO3 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_cts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_CTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_uart_rts_b_uart1_cts_b: IOMUXC_SD1_DATA1_UART_RTS_B_UART1_CTS_B { + pinmux = <0x303300ac 4 0x303304f0 5 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_SD1_DATA2_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x303300b0 1 0x3033057c 1 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io4: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO4 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_rx_uart2_tx: IOMUXC_SD1_DATA2_UART_RX_UART2_TX { + pinmux = <0x303300b0 4 0x303304fc 4 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_uart_tx_uart2_tx: IOMUXC_SD1_DATA2_UART_TX_UART2_TX { + pinmux = <0x303300b0 4 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_SD1_DATA3_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x303300b4 1 0x30330554 1 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io5: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO5 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_rx_uart2_rx: IOMUXC_SD1_DATA3_UART_RX_UART2_RX { + pinmux = <0x303300b4 4 0x303304fc 5 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_uart_tx_uart2_rx: IOMUXC_SD1_DATA3_UART_TX_UART2_RX { + pinmux = <0x303300b4 4 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_SD1_DATA4_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x303300b8 1 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io6: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO6 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_i2c_scl_i2c1_scl: IOMUXC_SD1_DATA4_I2C_SCL_I2C1_SCL { + pinmux = <0x303300b8 3 0x3033055c 1 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_cts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_CTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_uart_rts_b_uart2_rts_b: IOMUXC_SD1_DATA4_UART_RTS_B_UART2_RTS_B { + pinmux = <0x303300b8 4 0x303304f8 4 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_enet_tx_er_enet1_tx_er: IOMUXC_SD1_DATA5_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x303300bc 1 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io7: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO7 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_i2c_sda_i2c1_sda: IOMUXC_SD1_DATA5_I2C_SDA_I2C1_SDA { + pinmux = <0x303300bc 3 0x3033056c 1 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_cts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_CTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_uart_rts_b_uart2_cts_b: IOMUXC_SD1_DATA5_UART_RTS_B_UART2_CTS_B { + pinmux = <0x303300bc 4 0x303304f8 5 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_SD1_DATA6_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x303300c0 1 0x30330574 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io8: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO8 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_i2c_scl_i2c2_scl: IOMUXC_SD1_DATA6_I2C_SCL_I2C2_SCL { + pinmux = <0x303300c0 3 0x303305d0 1 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_rx_uart3_tx: IOMUXC_SD1_DATA6_UART_RX_UART3_TX { + pinmux = <0x303300c0 4 0x30330504 4 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_uart_tx_uart3_tx: IOMUXC_SD1_DATA6_UART_TX_UART3_TX { + pinmux = <0x303300c0 4 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_enet_rx_er_enet1_rx_er: IOMUXC_SD1_DATA7_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x303300c4 1 0x303305c8 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io9: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO9 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_i2c_sda_i2c2_sda: IOMUXC_SD1_DATA7_I2C_SDA_I2C2_SDA { + pinmux = <0x303300c4 3 0x30330560 1 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_rx_uart3_rx: IOMUXC_SD1_DATA7_UART_RX_UART3_RX { + pinmux = <0x303300c4 4 0x30330504 5 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_uart_tx_uart3_rx: IOMUXC_SD1_DATA7_UART_TX_UART3_RX { + pinmux = <0x303300c4 4 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_enet_tx_clk_enet1_tx_clk: IOMUXC_SD1_RESET_B_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x303300c8 1 0x303305a4 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_i2c_scl_i2c3_scl: IOMUXC_SD1_RESET_B_I2C_SCL_I2C3_SCL { + pinmux = <0x303300c8 3 0x30330588 1 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_cts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_CTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_uart_rts_b_uart3_rts_b: IOMUXC_SD1_RESET_B_UART_RTS_B_UART3_RTS_B { + pinmux = <0x303300c8 4 0x30330500 2 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_i2c_sda_i2c3_sda: IOMUXC_SD1_STROBE_I2C_SDA_I2C3_SDA { + pinmux = <0x303300cc 3 0x303305bc 1 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_cts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_uart_rts_b_uart3_cts_b: IOMUXC_SD1_STROBE_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303300cc 4 0x30330500 3 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ecspi_sclk_ecspi2_sclk: IOMUXC_SD2_CLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x303300d4 2 0x30330580 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_mclk_sai5_mclk: IOMUXC_SD2_CLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303300d4 4 0x30330594 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_sai_rx_sync_sai5_rx_sync: IOMUXC_SD2_CLK_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303300d4 1 0x303304e4 1 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_rx_uart4_rx: IOMUXC_SD2_CLK_UART_RX_UART4_RX { + pinmux = <0x303300d4 3 0x3033050c 4 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_uart_tx_uart4_rx: IOMUXC_SD2_CLK_UART_TX_UART4_RX { + pinmux = <0x303300d4 3 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ecspi_mosi_ecspi2_mosi: IOMUXC_SD2_CMD_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x303300d8 2 0x30330590 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_pdm_clk_pdm_clk: IOMUXC_SD2_CMD_PDM_CLK_PDM_CLK { + pinmux = <0x303300d8 4 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD2_CMD_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303300d8 1 0x303304d0 1 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_rx_uart4_tx: IOMUXC_SD2_CMD_UART_RX_UART4_TX { + pinmux = <0x303300d8 3 0x3033050c 5 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_uart_tx_uart4_tx: IOMUXC_SD2_CMD_UART_TX_UART4_TX { + pinmux = <0x303300d8 3 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_i2c_sda_i2c4_sda: IOMUXC_SD2_DATA0_I2C_SDA_I2C4_SDA { + pinmux = <0x303300dc 2 0x3033058c 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_pdm_bit_stream_pdm_bit_stream0: IOMUXC_SD2_DATA0_PDM_BIT_STREAM_PDM_BIT_STREAM0 { + pinmux = <0x303300dc 4 0x30330534 2 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_sai_rx_data_sai5_rx_data0: IOMUXC_SD2_DATA0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303300dc 1 0x303304d4 1 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_rx_uart2_rx: IOMUXC_SD2_DATA0_UART_RX_UART2_RX { + pinmux = <0x303300dc 3 0x303304fc 6 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_uart_tx_uart2_rx: IOMUXC_SD2_DATA0_UART_TX_UART2_RX { + pinmux = <0x303300dc 3 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_i2c_scl_i2c4_scl: IOMUXC_SD2_DATA1_I2C_SCL_I2C4_SCL { + pinmux = <0x303300e0 2 0x303305d4 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_pdm_bit_stream_pdm_bit_stream1: IOMUXC_SD2_DATA1_PDM_BIT_STREAM_PDM_BIT_STREAM1 { + pinmux = <0x303300e0 4 0x30330538 4 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_sai_tx_sync_sai5_tx_sync: IOMUXC_SD2_DATA1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303300e0 1 0x303304ec 1 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_rx_uart2_tx: IOMUXC_SD2_DATA1_UART_RX_UART2_TX { + pinmux = <0x303300e0 3 0x303304fc 7 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_uart_tx_uart2_tx: IOMUXC_SD2_DATA1_UART_TX_UART2_TX { + pinmux = <0x303300e0 3 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_ecspi_ss_ecspi2_ss0: IOMUXC_SD2_DATA2_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x303300e4 2 0x30330570 2 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_pdm_bit_stream_pdm_bit_stream2: IOMUXC_SD2_DATA2_PDM_BIT_STREAM_PDM_BIT_STREAM2 { + pinmux = <0x303300e4 4 0x3033053c 4 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD2_DATA2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303300e4 1 0x303304e8 1 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_spdif_out_spdif1_out: IOMUXC_SD2_DATA2_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303300e4 3 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_ecspi_miso_ecspi2_miso: IOMUXC_SD2_DATA3_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x303300e8 2 0x30330578 1 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_pdm_bit_stream_pdm_bit_stream3: IOMUXC_SD2_DATA3_PDM_BIT_STREAM_PDM_BIT_STREAM3 { + pinmux = <0x303300e8 4 0x30330540 4 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_sai_tx_data_sai5_tx_data0: IOMUXC_SD2_DATA3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303300e8 1 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_spdif_in_spdif1_in: IOMUXC_SD2_DATA3_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303300e8 3 0x303305cc 2 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_coresight_eventi_coresight_eventi: IOMUXC_SD2_WP_CORESIGHT_EVENTI_CORESIGHT_EVENTI { + pinmux = <0x303300f0 6 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io5: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO5 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif1_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF1_EXT_CLK { + pinmux = <0x303301f0 0 0x30330568 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io4: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO4 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif1_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF1_IN { + pinmux = <0x303301ec 0 0x303305cc 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io3: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO3 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif1_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF1_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpt_compare_gpt1_compare3: IOMUXC_UART2_RXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x3033023c 3 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpt_compare_gpt1_compare2: IOMUXC_UART2_TXD_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x30330240 3 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpt_capture_gpt1_capture2: IOMUXC_UART3_RXD_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x30330244 3 0x303305ec 1 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_usdhc_reset_b_usdhc3_reset_b: IOMUXC_UART3_RXD_USDHC_RESET_B_USDHC3_RESET_B { + pinmux = <0x30330244 2 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpt_clk_gpt1_clk: IOMUXC_UART3_TXD_GPT_CLK_GPT1_CLK { + pinmux = <0x30330248 3 0x303305e8 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_usdhc_vselect_usdhc3_vselect: IOMUXC_UART3_TXD_USDHC_VSELECT_USDHC3_VSELECT { + pinmux = <0x30330248 2 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpt_compare_gpt1_compare1: IOMUXC_UART4_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x3033024c 3 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpt_capture_gpt1_capture1: IOMUXC_UART4_TXD_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x30330250 3 0x303305f0 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mq5cvahz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mq5cvahz-pinctrl.dtsi new file mode 100644 index 000000000..4bd60d13d --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mq5cvahz-pinctrl.dtsi @@ -0,0 +1,1489 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MQ5CVAHZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_I2C4_SDA_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330230 2 0x30330528 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_snvs_rtc_snvs_rtc: IOMUXC_RTC_SNVS_RTC_SNVS_RTC { + pinmux = <0x0 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_capture_gpt1_capture2: IOMUXC_SAI3_RXC_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_clk_gpt1_clk: IOMUXC_SAI3_TXFS_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai4_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI4_MCLK { + pinmux = <0x30330158 2 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_UART4_TXD_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330250 2 0x30330528 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mq5dvajz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mq5dvajz-pinctrl.dtsi new file mode 100644 index 000000000..0b167124d --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mq5dvajz-pinctrl.dtsi @@ -0,0 +1,1489 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MQ5DVAJZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_I2C4_SDA_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330230 2 0x30330528 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_snvs_rtc_snvs_rtc: IOMUXC_RTC_SNVS_RTC_SNVS_RTC { + pinmux = <0x0 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_capture_gpt1_capture2: IOMUXC_SAI3_RXC_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_clk_gpt1_clk: IOMUXC_SAI3_TXFS_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai4_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI4_MCLK { + pinmux = <0x30330158 2 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_UART4_TXD_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330250 2 0x30330528 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mq6cvahz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mq6cvahz-pinctrl.dtsi new file mode 100644 index 000000000..6a07f3a61 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mq6cvahz-pinctrl.dtsi @@ -0,0 +1,1489 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MQ6CVAHZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_I2C4_SDA_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330230 2 0x30330528 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_snvs_rtc_snvs_rtc: IOMUXC_RTC_SNVS_RTC_SNVS_RTC { + pinmux = <0x0 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_capture_gpt1_capture2: IOMUXC_SAI3_RXC_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_clk_gpt1_clk: IOMUXC_SAI3_TXFS_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai4_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI4_MCLK { + pinmux = <0x30330158 2 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_UART4_TXD_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330250 2 0x30330528 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mq7cvahz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mq7cvahz-pinctrl.dtsi new file mode 100644 index 000000000..83bd6a109 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mq7cvahz-pinctrl.dtsi @@ -0,0 +1,1489 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MQ7CVAHZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_I2C4_SDA_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330230 2 0x30330528 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_snvs_rtc_snvs_rtc: IOMUXC_RTC_SNVS_RTC_SNVS_RTC { + pinmux = <0x0 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_capture_gpt1_capture2: IOMUXC_SAI3_RXC_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_clk_gpt1_clk: IOMUXC_SAI3_TXFS_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai4_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI4_MCLK { + pinmux = <0x30330158 2 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_UART4_TXD_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330250 2 0x30330528 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx8mq7dvajz-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx8mq7dvajz-pinctrl.dtsi new file mode 100644 index 000000000..f30c7abb7 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx8mq7dvajz-pinctrl.dtsi @@ -0,0 +1,1489 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX8MQ7DVAJZ + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_boot_mode0_src_boot_mode_src_boot_mode0: IOMUXC_BOOT_MODE0_SRC_BOOT_MODE_SRC_BOOT_MODE0 { + pinmux = <0x0 0 0x0 0 0x30330258>; + }; + /omit-if-no-ref/ iomuxc_boot_mode1_src_boot_mode_src_boot_mode1: IOMUXC_BOOT_MODE1_SRC_BOOT_MODE_SRC_BOOT_MODE1 { + pinmux = <0x0 0 0x0 0 0x3033025c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso: IOMUXC_ECSPI1_MISO_ECSPI_MISO_ECSPI1_MISO { + pinmux = <0x303301fc 0 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_gpio_io_gpio5_io08: IOMUXC_ECSPI1_MISO_GPIO_IO_GPIO5_IO08 { + pinmux = <0x303301fc 5 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_cts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_CTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x0 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_miso_uart_rts_b_uart3_cts_b: IOMUXC_ECSPI1_MISO_UART_RTS_B_UART3_CTS_B { + pinmux = <0x303301fc 1 0x30330500 0 0x30330464>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi: IOMUXC_ECSPI1_MOSI_ECSPI_MOSI_ECSPI1_MOSI { + pinmux = <0x303301f8 0 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_gpio_io_gpio5_io07: IOMUXC_ECSPI1_MOSI_GPIO_IO_GPIO5_IO07 { + pinmux = <0x303301f8 5 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_rx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_RX_UART3_TX { + pinmux = <0x303301f8 1 0x30330504 1 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_mosi_uart_tx_uart3_tx: IOMUXC_ECSPI1_MOSI_UART_TX_UART3_TX { + pinmux = <0x303301f8 1 0x0 0 0x30330460>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk: IOMUXC_ECSPI1_SCLK_ECSPI_SCLK_ECSPI1_SCLK { + pinmux = <0x303301f4 0 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_gpio_io_gpio5_io06: IOMUXC_ECSPI1_SCLK_GPIO_IO_GPIO5_IO06 { + pinmux = <0x303301f4 5 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_rx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_RX_UART3_RX { + pinmux = <0x303301f4 1 0x30330504 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_sclk_uart_tx_uart3_rx: IOMUXC_ECSPI1_SCLK_UART_TX_UART3_RX { + pinmux = <0x303301f4 1 0x0 0 0x3033045c>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0: IOMUXC_ECSPI1_SS0_ECSPI_SS_ECSPI1_SS0 { + pinmux = <0x30330200 0 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_gpio_io_gpio5_io09: IOMUXC_ECSPI1_SS0_GPIO_IO_GPIO5_IO09 { + pinmux = <0x30330200 5 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_cts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_CTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x0 0 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi1_ss0_uart_rts_b_uart3_rts_b: IOMUXC_ECSPI1_SS0_UART_RTS_B_UART3_RTS_B { + pinmux = <0x30330200 1 0x30330500 1 0x30330468>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso: IOMUXC_ECSPI2_MISO_ECSPI_MISO_ECSPI2_MISO { + pinmux = <0x3033020c 0 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_gpio_io_gpio5_io12: IOMUXC_ECSPI2_MISO_GPIO_IO_GPIO5_IO12 { + pinmux = <0x3033020c 5 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_cts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_CTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x0 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_miso_uart_rts_b_uart4_cts_b: IOMUXC_ECSPI2_MISO_UART_RTS_B_UART4_CTS_B { + pinmux = <0x3033020c 1 0x30330508 0 0x30330474>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi: IOMUXC_ECSPI2_MOSI_ECSPI_MOSI_ECSPI2_MOSI { + pinmux = <0x30330208 0 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_gpio_io_gpio5_io11: IOMUXC_ECSPI2_MOSI_GPIO_IO_GPIO5_IO11 { + pinmux = <0x30330208 5 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_rx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_RX_UART4_TX { + pinmux = <0x30330208 1 0x3033050c 1 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_mosi_uart_tx_uart4_tx: IOMUXC_ECSPI2_MOSI_UART_TX_UART4_TX { + pinmux = <0x30330208 1 0x0 0 0x30330470>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk: IOMUXC_ECSPI2_SCLK_ECSPI_SCLK_ECSPI2_SCLK { + pinmux = <0x30330204 0 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_gpio_io_gpio5_io10: IOMUXC_ECSPI2_SCLK_GPIO_IO_GPIO5_IO10 { + pinmux = <0x30330204 5 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_rx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_RX_UART4_RX { + pinmux = <0x30330204 1 0x3033050c 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_sclk_uart_tx_uart4_rx: IOMUXC_ECSPI2_SCLK_UART_TX_UART4_RX { + pinmux = <0x30330204 1 0x0 0 0x3033046c>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_ecspi_ss_ecspi2_ss0: IOMUXC_ECSPI2_SS0_ECSPI_SS_ECSPI2_SS0 { + pinmux = <0x30330210 0 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_gpio_io_gpio5_io13: IOMUXC_ECSPI2_SS0_GPIO_IO_GPIO5_IO13 { + pinmux = <0x30330210 5 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_cts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_CTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x0 0 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_ecspi2_ss0_uart_rts_b_uart4_rts_b: IOMUXC_ECSPI2_SS0_UART_RTS_B_UART4_RTS_B { + pinmux = <0x30330210 1 0x30330508 1 0x30330478>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_enet_mdc_enet1_mdc: IOMUXC_ENET_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x30330068 0 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdc_gpio_io_gpio1_io16: IOMUXC_ENET_MDC_GPIO_IO_GPIO1_IO16 { + pinmux = <0x30330068 5 0x0 0 0x303302d0>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_enet_mdio_enet1_mdio: IOMUXC_ENET_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x3033006c 0 0x303304c0 1 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_mdio_gpio_io_gpio1_io17: IOMUXC_ENET_MDIO_GPIO_IO_GPIO1_IO17 { + pinmux = <0x3033006c 5 0x0 0 0x303302d4>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC_ENET_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x30330090 0 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd0_gpio_io_gpio1_io26: IOMUXC_ENET_RD0_GPIO_IO_GPIO1_IO26 { + pinmux = <0x30330090 5 0x0 0 0x303302f8>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC_ENET_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x30330094 0 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd1_gpio_io_gpio1_io27: IOMUXC_ENET_RD1_GPIO_IO_GPIO1_IO27 { + pinmux = <0x30330094 5 0x0 0 0x303302fc>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC_ENET_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x30330098 0 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd2_gpio_io_gpio1_io28: IOMUXC_ENET_RD2_GPIO_IO_GPIO1_IO28 { + pinmux = <0x30330098 5 0x0 0 0x30330300>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC_ENET_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x3033009c 0 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rd3_gpio_io_gpio1_io29: IOMUXC_ENET_RD3_GPIO_IO_GPIO1_IO29 { + pinmux = <0x3033009c 5 0x0 0 0x30330304>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC_ENET_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x3033008c 0 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_enet_rx_er_enet1_rx_er: IOMUXC_ENET_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x3033008c 1 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rxc_gpio_io_gpio1_io25: IOMUXC_ENET_RXC_GPIO_IO_GPIO1_IO25 { + pinmux = <0x3033008c 5 0x0 0 0x303302f4>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC_ENET_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x30330088 0 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_rx_ctl_gpio_io_gpio1_io24: IOMUXC_ENET_RX_CTL_GPIO_IO_GPIO1_IO24 { + pinmux = <0x30330088 5 0x0 0 0x303302f0>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC_ENET_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x3033007c 0 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td0_gpio_io_gpio1_io21: IOMUXC_ENET_TD0_GPIO_IO_GPIO1_IO21 { + pinmux = <0x3033007c 5 0x0 0 0x303302e4>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC_ENET_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x30330078 0 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td1_gpio_io_gpio1_io20: IOMUXC_ENET_TD1_GPIO_IO_GPIO1_IO20 { + pinmux = <0x30330078 5 0x0 0 0x303302e0>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_ccm_enet_ref_clk_root_ccm_enet_ref_clk_root: IOMUXC_ENET_TD2_CCM_ENET_REF_CLK_ROOT_CCM_ENET_REF_CLK_ROOT { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC_ENET_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x30330074 0 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_enet_tx_clk_enet1_tx_clk: IOMUXC_ENET_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x30330074 1 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td2_gpio_io_gpio1_io19: IOMUXC_ENET_TD2_GPIO_IO_GPIO1_IO19 { + pinmux = <0x30330074 5 0x0 0 0x303302dc>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC_ENET_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x30330070 0 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_td3_gpio_io_gpio1_io18: IOMUXC_ENET_TD3_GPIO_IO_GPIO1_IO18 { + pinmux = <0x30330070 5 0x0 0 0x303302d8>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC_ENET_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x30330084 0 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_enet_tx_er_enet1_tx_er: IOMUXC_ENET_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x30330084 1 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_txc_gpio_io_gpio1_io23: IOMUXC_ENET_TXC_GPIO_IO_GPIO1_IO23 { + pinmux = <0x30330084 5 0x0 0 0x303302ec>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC_ENET_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x30330080 0 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_enet_tx_ctl_gpio_io_gpio1_io22: IOMUXC_ENET_TX_CTL_GPIO_IO_GPIO1_IO22 { + pinmux = <0x30330080 5 0x0 0 0x303302e8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_enet_phy_ref_clk_root_ccm_enet_phy_ref_clk_root: IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT_CCM_ENET_PHY_REF_CLK_ROOT { + pinmux = <0x30330028 1 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_ccm_ext_clk_ccm_ext_clk1: IOMUXC_GPIO1_IO00_CCM_EXT_CLK_CCM_EXT_CLK1 { + pinmux = <0x30330028 6 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_gpio_io_gpio1_io00: IOMUXC_GPIO1_IO00_GPIO_IO_GPIO1_IO00 { + pinmux = <0x30330028 0 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io00_xtalosc_ref_clk_32k_xtalosc_ref_clk_32k: IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K_XTALOSC_REF_CLK_32K { + pinmux = <0x30330028 5 0x0 0 0x30330290>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_ccm_ext_clk_ccm_ext_clk2: IOMUXC_GPIO1_IO01_CCM_EXT_CLK_CCM_EXT_CLK2 { + pinmux = <0x3033002c 6 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_gpio_io_gpio1_io01: IOMUXC_GPIO1_IO01_GPIO_IO_GPIO1_IO01 { + pinmux = <0x3033002c 0 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_pwm_out_pwm1_out: IOMUXC_GPIO1_IO01_PWM_OUT_PWM1_OUT { + pinmux = <0x3033002c 1 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io01_xtalosc_ref_clk_24m_xtalosc_ref_clk_24m: IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M_XTALOSC_REF_CLK_24M { + pinmux = <0x3033002c 5 0x0 0 0x30330294>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_gpio_io_gpio1_io02: IOMUXC_GPIO1_IO02_GPIO_IO_GPIO1_IO02 { + pinmux = <0x30330030 0 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_any_wdog1_wdog_any: IOMUXC_GPIO1_IO02_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x30330030 5 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io02_wdog_wdog_b_wdog1_wdog_b: IOMUXC_GPIO1_IO02_WDOG_WDOG_B_WDOG1_WDOG_B { + pinmux = <0x30330030 1 0x0 0 0x30330298>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_gpio_io_gpio1_io03: IOMUXC_GPIO1_IO03_GPIO_IO_GPIO1_IO03 { + pinmux = <0x30330034 0 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_sdma_ext_event_sdma1_ext_event0: IOMUXC_GPIO1_IO03_SDMA_EXT_EVENT_SDMA1_EXT_EVENT0 { + pinmux = <0x30330034 5 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io03_usdhc_vselect_usdhc1_vselect: IOMUXC_GPIO1_IO03_USDHC_VSELECT_USDHC1_VSELECT { + pinmux = <0x30330034 1 0x0 0 0x3033029c>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_gpio_io_gpio1_io04: IOMUXC_GPIO1_IO04_GPIO_IO_GPIO1_IO04 { + pinmux = <0x30330038 0 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_sdma_ext_event_sdma1_ext_event1: IOMUXC_GPIO1_IO04_SDMA_EXT_EVENT_SDMA1_EXT_EVENT1 { + pinmux = <0x30330038 5 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io04_usdhc_vselect_usdhc2_vselect: IOMUXC_GPIO1_IO04_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x30330038 1 0x0 0 0x303302a0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO05_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x3033003c 5 0x303304bc 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_gpio_io_gpio1_io05: IOMUXC_GPIO1_IO05_GPIO_IO_GPIO1_IO05 { + pinmux = <0x3033003c 0 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io05_m4_nmi_m4_nmi: IOMUXC_GPIO1_IO05_M4_NMI_M4_NMI { + pinmux = <0x3033003c 1 0x0 0 0x303302a4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_ccm_ext_clk_ccm_ext_clk3: IOMUXC_GPIO1_IO06_CCM_EXT_CLK_CCM_EXT_CLK3 { + pinmux = <0x30330040 6 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_enet_mdc_enet1_mdc: IOMUXC_GPIO1_IO06_ENET_MDC_ENET1_MDC { + pinmux = <0x30330040 1 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_gpio_io_gpio1_io06: IOMUXC_GPIO1_IO06_GPIO_IO_GPIO1_IO06 { + pinmux = <0x30330040 0 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io06_usdhc_cd_b_usdhc1_cd_b: IOMUXC_GPIO1_IO06_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x30330040 5 0x0 0 0x303302a8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_ccm_ext_clk_ccm_ext_clk4: IOMUXC_GPIO1_IO07_CCM_EXT_CLK_CCM_EXT_CLK4 { + pinmux = <0x30330044 6 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_enet_mdio_enet1_mdio: IOMUXC_GPIO1_IO07_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330044 1 0x303304c0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_gpio_io_gpio1_io07: IOMUXC_GPIO1_IO07_GPIO_IO_GPIO1_IO07 { + pinmux = <0x30330044 0 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io07_usdhc_wp_usdhc1_wp: IOMUXC_GPIO1_IO07_USDHC_WP_USDHC1_WP { + pinmux = <0x30330044 5 0x0 0 0x303302ac>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_enet_1588_event0_in_enet1_1588_event0_in: IOMUXC_GPIO1_IO08_ENET_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x30330048 1 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_gpio_io_gpio1_io08: IOMUXC_GPIO1_IO08_GPIO_IO_GPIO1_IO08 { + pinmux = <0x30330048 0 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io08_usdhc_reset_b_usdhc2_reset_b: IOMUXC_GPIO1_IO08_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x30330048 5 0x0 0 0x303302b0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_enet_1588_event0_out_enet1_1588_event0_out: IOMUXC_GPIO1_IO09_ENET_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x3033004c 1 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_gpio_io_gpio1_io09: IOMUXC_GPIO1_IO09_GPIO_IO_GPIO1_IO09 { + pinmux = <0x3033004c 0 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io09_sdma_ext_event_sdma2_ext_event0: IOMUXC_GPIO1_IO09_SDMA_EXT_EVENT_SDMA2_EXT_EVENT0 { + pinmux = <0x3033004c 5 0x0 0 0x303302b4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_gpio_io_gpio1_io10: IOMUXC_GPIO1_IO10_GPIO_IO_GPIO1_IO10 { + pinmux = <0x30330050 0 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io10_usb_otg_id_usb1_otg_id: IOMUXC_GPIO1_IO10_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x30330050 1 0x0 0 0x303302b8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_ccm_pmic_ready_ccm_pmic_ready: IOMUXC_GPIO1_IO11_CCM_PMIC_READY_CCM_PMIC_READY { + pinmux = <0x30330054 5 0x303304bc 1 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_gpio_io_gpio1_io11: IOMUXC_GPIO1_IO11_GPIO_IO_GPIO1_IO11 { + pinmux = <0x30330054 0 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io11_usb_otg_id_usb2_otg_id: IOMUXC_GPIO1_IO11_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x30330054 1 0x0 0 0x303302bc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_gpio_io_gpio1_io12: IOMUXC_GPIO1_IO12_GPIO_IO_GPIO1_IO12 { + pinmux = <0x30330058 0 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_sdma_ext_event_sdma2_ext_event1: IOMUXC_GPIO1_IO12_SDMA_EXT_EVENT_SDMA2_EXT_EVENT1 { + pinmux = <0x30330058 5 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io12_usb_otg_pwr_usb1_otg_pwr: IOMUXC_GPIO1_IO12_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x30330058 1 0x0 0 0x303302c0>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_gpio_io_gpio1_io13: IOMUXC_GPIO1_IO13_GPIO_IO_GPIO1_IO13 { + pinmux = <0x3033005c 0 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_pwm_out_pwm2_out: IOMUXC_GPIO1_IO13_PWM_OUT_PWM2_OUT { + pinmux = <0x3033005c 5 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io13_usb_otg_oc_usb1_otg_oc: IOMUXC_GPIO1_IO13_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x3033005c 1 0x0 0 0x303302c4>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_ccm_clko_ccm_clko1: IOMUXC_GPIO1_IO14_CCM_CLKO_CCM_CLKO1 { + pinmux = <0x30330060 6 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_gpio_io_gpio1_io14: IOMUXC_GPIO1_IO14_GPIO_IO_GPIO1_IO14 { + pinmux = <0x30330060 0 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_pwm_out_pwm3_out: IOMUXC_GPIO1_IO14_PWM_OUT_PWM3_OUT { + pinmux = <0x30330060 5 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io14_usb_otg_pwr_usb2_otg_pwr: IOMUXC_GPIO1_IO14_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x30330060 1 0x0 0 0x303302c8>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_ccm_clko_ccm_clko2: IOMUXC_GPIO1_IO15_CCM_CLKO_CCM_CLKO2 { + pinmux = <0x30330064 6 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_gpio_io_gpio1_io15: IOMUXC_GPIO1_IO15_GPIO_IO_GPIO1_IO15 { + pinmux = <0x30330064 0 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_pwm_out_pwm4_out: IOMUXC_GPIO1_IO15_PWM_OUT_PWM4_OUT { + pinmux = <0x30330064 5 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_gpio1_io15_usb_otg_oc_usb2_otg_oc: IOMUXC_GPIO1_IO15_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x30330064 1 0x0 0 0x303302cc>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_enet_mdc_enet1_mdc: IOMUXC_I2C1_SCL_ENET_MDC_ENET1_MDC { + pinmux = <0x30330214 1 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_gpio5_io14: IOMUXC_I2C1_SCL_GPIO_IO_GPIO5_IO14 { + pinmux = <0x30330214 5 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i2c_scl_i2c1_scl: IOMUXC_I2C1_SCL_I2C_SCL_I2C1_SCL { + pinmux = <0x30330214 0 0x0 0 0x3033047c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_enet_mdio_enet1_mdio: IOMUXC_I2C1_SDA_ENET_MDIO_ENET1_MDIO { + pinmux = <0x30330218 1 0x303304c0 2 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_gpio5_io15: IOMUXC_I2C1_SDA_GPIO_IO_GPIO5_IO15 { + pinmux = <0x30330218 5 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i2c_sda_i2c1_sda: IOMUXC_I2C1_SDA_I2C_SDA_I2C1_SDA { + pinmux = <0x30330218 0 0x0 0 0x30330480>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_enet_1588_event1_in_enet1_1588_event1_in: IOMUXC_I2C2_SCL_ENET_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x3033021c 1 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_gpio5_io16: IOMUXC_I2C2_SCL_GPIO_IO_GPIO5_IO16 { + pinmux = <0x3033021c 5 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i2c_scl_i2c2_scl: IOMUXC_I2C2_SCL_I2C_SCL_I2C2_SCL { + pinmux = <0x3033021c 0 0x0 0 0x30330484>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_enet_1588_event1_out_enet1_1588_event1_out: IOMUXC_I2C2_SDA_ENET_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x30330220 1 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_gpio5_io17: IOMUXC_I2C2_SDA_GPIO_IO_GPIO5_IO17 { + pinmux = <0x30330220 5 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_i2c_sda_i2c2_sda: IOMUXC_I2C2_SDA_I2C_SDA_I2C2_SDA { + pinmux = <0x30330220 0 0x0 0 0x30330488>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpio_io_gpio5_io18: IOMUXC_I2C3_SCL_GPIO_IO_GPIO5_IO18 { + pinmux = <0x30330224 5 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_gpt_clk_gpt2_clk: IOMUXC_I2C3_SCL_GPT_CLK_GPT2_CLK { + pinmux = <0x30330224 2 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_i2c_scl_i2c3_scl: IOMUXC_I2C3_SCL_I2C_SCL_I2C3_SCL { + pinmux = <0x30330224 0 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_scl_pwm_out_pwm4_out: IOMUXC_I2C3_SCL_PWM_OUT_PWM4_OUT { + pinmux = <0x30330224 1 0x0 0 0x3033048c>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpio_io_gpio5_io19: IOMUXC_I2C3_SDA_GPIO_IO_GPIO5_IO19 { + pinmux = <0x30330228 5 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_gpt_clk_gpt3_clk: IOMUXC_I2C3_SDA_GPT_CLK_GPT3_CLK { + pinmux = <0x30330228 2 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_i2c_sda_i2c3_sda: IOMUXC_I2C3_SDA_I2C_SDA_I2C3_SDA { + pinmux = <0x30330228 0 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c3_sda_pwm_out_pwm3_out: IOMUXC_I2C3_SDA_PWM_OUT_PWM3_OUT { + pinmux = <0x30330228 1 0x0 0 0x30330490>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_gpio_io_gpio5_io20: IOMUXC_I2C4_SCL_GPIO_IO_GPIO5_IO20 { + pinmux = <0x3033022c 5 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_i2c_scl_i2c4_scl: IOMUXC_I2C4_SCL_I2C_SCL_I2C4_SCL { + pinmux = <0x3033022c 0 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_I2C4_SCL_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033022c 2 0x30330524 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_scl_pwm_out_pwm2_out: IOMUXC_I2C4_SCL_PWM_OUT_PWM2_OUT { + pinmux = <0x3033022c 1 0x0 0 0x30330494>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_gpio_io_gpio5_io21: IOMUXC_I2C4_SDA_GPIO_IO_GPIO5_IO21 { + pinmux = <0x30330230 5 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_i2c_sda_i2c4_sda: IOMUXC_I2C4_SDA_I2C_SDA_I2C4_SDA { + pinmux = <0x30330230 0 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_I2C4_SDA_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330230 2 0x30330528 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_i2c4_sda_pwm_out_pwm1_out: IOMUXC_I2C4_SDA_PWM_OUT_PWM1_OUT { + pinmux = <0x30330230 1 0x0 0 0x30330498>; + }; + /omit-if-no-ref/ iomuxc_jtag_mod_jtag_mode_jtag_mode: IOMUXC_JTAG_MOD_JTAG_MODE_JTAG_MODE { + pinmux = <0x0 0 0x0 0 0x30330260>; + }; + /omit-if-no-ref/ iomuxc_jtag_tck_jtag_tck_jtag_tck: IOMUXC_JTAG_TCK_JTAG_TCK_JTAG_TCK { + pinmux = <0x0 0 0x0 0 0x30330270>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdi_jtag_tdi_jtag_tdi: IOMUXC_JTAG_TDI_JTAG_TDI_JTAG_TDI { + pinmux = <0x0 0 0x0 0 0x30330268>; + }; + /omit-if-no-ref/ iomuxc_jtag_tdo_jtag_tdo_jtag_tdo: IOMUXC_JTAG_TDO_JTAG_TDO_JTAG_TDO { + pinmux = <0x0 0 0x0 0 0x30330274>; + }; + /omit-if-no-ref/ iomuxc_jtag_tms_jtag_tms_jtag_tms: IOMUXC_JTAG_TMS_JTAG_TMS_JTAG_TMS { + pinmux = <0x0 0 0x0 0 0x3033026c>; + }; + /omit-if-no-ref/ iomuxc_jtag_trst_b_jtag_trst_b_jtag_trst_b: IOMUXC_JTAG_TRST_B_JTAG_TRST_B_JTAG_TRST_B { + pinmux = <0x0 0 0x0 0 0x30330264>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_gpio_io_gpio3_io00: IOMUXC_NAND_ALE_GPIO_IO_GPIO3_IO00 { + pinmux = <0x303300f4 5 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_nand_ale_nand_ale: IOMUXC_NAND_ALE_NAND_ALE_NAND_ALE { + pinmux = <0x303300f4 0 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ale_qspi_a_sclk_qspi_a_sclk: IOMUXC_NAND_ALE_QSPI_A_SCLK_QSPI_A_SCLK { + pinmux = <0x303300f4 1 0x0 0 0x3033035c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_gpio_io_gpio3_io01: IOMUXC_NAND_CE0_B_GPIO_IO_GPIO3_IO01 { + pinmux = <0x303300f8 5 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_nand_ce0_b_nand_ce0_b: IOMUXC_NAND_CE0_B_NAND_CE0_B_NAND_CE0_B { + pinmux = <0x303300f8 0 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce0_b_qspi_a_ss0_b_qspi_a_ss0_b: IOMUXC_NAND_CE0_B_QSPI_A_SS0_B_QSPI_A_SS0_B { + pinmux = <0x303300f8 1 0x0 0 0x30330360>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_gpio_io_gpio3_io02: IOMUXC_NAND_CE1_B_GPIO_IO_GPIO3_IO02 { + pinmux = <0x303300fc 5 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_nand_ce1_b_nand_ce1_b: IOMUXC_NAND_CE1_B_NAND_CE1_B_NAND_CE1_B { + pinmux = <0x303300fc 0 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce1_b_qspi_a_ss1_b_qspi_a_ss1_b: IOMUXC_NAND_CE1_B_QSPI_A_SS1_B_QSPI_A_SS1_B { + pinmux = <0x303300fc 1 0x0 0 0x30330364>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_gpio_io_gpio3_io03: IOMUXC_NAND_CE2_B_GPIO_IO_GPIO3_IO03 { + pinmux = <0x30330100 5 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_nand_ce2_b_nand_ce2_b: IOMUXC_NAND_CE2_B_NAND_CE2_B_NAND_CE2_B { + pinmux = <0x30330100 0 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce2_b_qspi_b_ss0_b_qspi_b_ss0_b: IOMUXC_NAND_CE2_B_QSPI_B_SS0_B_QSPI_B_SS0_B { + pinmux = <0x30330100 1 0x0 0 0x30330368>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_gpio_io_gpio3_io04: IOMUXC_NAND_CE3_B_GPIO_IO_GPIO3_IO04 { + pinmux = <0x30330104 5 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_nand_ce3_b_nand_ce3_b: IOMUXC_NAND_CE3_B_NAND_CE3_B_NAND_CE3_B { + pinmux = <0x30330104 0 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_ce3_b_qspi_b_ss1_b_qspi_b_ss1_b: IOMUXC_NAND_CE3_B_QSPI_B_SS1_B_QSPI_B_SS1_B { + pinmux = <0x30330104 1 0x0 0 0x3033036c>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_gpio_io_gpio3_io05: IOMUXC_NAND_CLE_GPIO_IO_GPIO3_IO05 { + pinmux = <0x30330108 5 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_nand_cle_nand_cle: IOMUXC_NAND_CLE_NAND_CLE_NAND_CLE { + pinmux = <0x30330108 0 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_cle_qspi_b_sclk_qspi_b_sclk: IOMUXC_NAND_CLE_QSPI_B_SCLK_QSPI_B_SCLK { + pinmux = <0x30330108 1 0x0 0 0x30330370>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_gpio_io_gpio3_io06: IOMUXC_NAND_DATA00_GPIO_IO_GPIO3_IO06 { + pinmux = <0x3033010c 5 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_nand_data_nand_data00: IOMUXC_NAND_DATA00_NAND_DATA_NAND_DATA00 { + pinmux = <0x3033010c 0 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data00_qspi_a_data_qspi_a_data0: IOMUXC_NAND_DATA00_QSPI_A_DATA_QSPI_A_DATA0 { + pinmux = <0x3033010c 1 0x0 0 0x30330374>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_gpio_io_gpio3_io07: IOMUXC_NAND_DATA01_GPIO_IO_GPIO3_IO07 { + pinmux = <0x30330110 5 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_nand_data_nand_data01: IOMUXC_NAND_DATA01_NAND_DATA_NAND_DATA01 { + pinmux = <0x30330110 0 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data01_qspi_a_data_qspi_a_data1: IOMUXC_NAND_DATA01_QSPI_A_DATA_QSPI_A_DATA1 { + pinmux = <0x30330110 1 0x0 0 0x30330378>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_gpio_io_gpio3_io08: IOMUXC_NAND_DATA02_GPIO_IO_GPIO3_IO08 { + pinmux = <0x30330114 5 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_nand_data_nand_data02: IOMUXC_NAND_DATA02_NAND_DATA_NAND_DATA02 { + pinmux = <0x30330114 0 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data02_qspi_a_data_qspi_a_data2: IOMUXC_NAND_DATA02_QSPI_A_DATA_QSPI_A_DATA2 { + pinmux = <0x30330114 1 0x0 0 0x3033037c>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_gpio_io_gpio3_io09: IOMUXC_NAND_DATA03_GPIO_IO_GPIO3_IO09 { + pinmux = <0x30330118 5 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_nand_data_nand_data03: IOMUXC_NAND_DATA03_NAND_DATA_NAND_DATA03 { + pinmux = <0x30330118 0 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data03_qspi_a_data_qspi_a_data3: IOMUXC_NAND_DATA03_QSPI_A_DATA_QSPI_A_DATA3 { + pinmux = <0x30330118 1 0x0 0 0x30330380>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_gpio_io_gpio3_io10: IOMUXC_NAND_DATA04_GPIO_IO_GPIO3_IO10 { + pinmux = <0x3033011c 5 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_nand_data_nand_data04: IOMUXC_NAND_DATA04_NAND_DATA_NAND_DATA04 { + pinmux = <0x3033011c 0 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data04_qspi_b_data_qspi_b_data0: IOMUXC_NAND_DATA04_QSPI_B_DATA_QSPI_B_DATA0 { + pinmux = <0x3033011c 1 0x0 0 0x30330384>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_gpio_io_gpio3_io11: IOMUXC_NAND_DATA05_GPIO_IO_GPIO3_IO11 { + pinmux = <0x30330120 5 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_nand_data_nand_data05: IOMUXC_NAND_DATA05_NAND_DATA_NAND_DATA05 { + pinmux = <0x30330120 0 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data05_qspi_b_data_qspi_b_data1: IOMUXC_NAND_DATA05_QSPI_B_DATA_QSPI_B_DATA1 { + pinmux = <0x30330120 1 0x0 0 0x30330388>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_gpio_io_gpio3_io12: IOMUXC_NAND_DATA06_GPIO_IO_GPIO3_IO12 { + pinmux = <0x30330124 5 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_nand_data_nand_data06: IOMUXC_NAND_DATA06_NAND_DATA_NAND_DATA06 { + pinmux = <0x30330124 0 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data06_qspi_b_data_qspi_b_data2: IOMUXC_NAND_DATA06_QSPI_B_DATA_QSPI_B_DATA2 { + pinmux = <0x30330124 1 0x0 0 0x3033038c>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_gpio_io_gpio3_io13: IOMUXC_NAND_DATA07_GPIO_IO_GPIO3_IO13 { + pinmux = <0x30330128 5 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_nand_data_nand_data07: IOMUXC_NAND_DATA07_NAND_DATA_NAND_DATA07 { + pinmux = <0x30330128 0 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_data07_qspi_b_data_qspi_b_data3: IOMUXC_NAND_DATA07_QSPI_B_DATA_QSPI_B_DATA3 { + pinmux = <0x30330128 1 0x0 0 0x30330390>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_gpio_io_gpio3_io14: IOMUXC_NAND_DQS_GPIO_IO_GPIO3_IO14 { + pinmux = <0x3033012c 5 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_nand_dqs_nand_dqs: IOMUXC_NAND_DQS_NAND_DQS_NAND_DQS { + pinmux = <0x3033012c 0 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_dqs_qspi_a_dqs_qspi_a_dqs: IOMUXC_NAND_DQS_QSPI_A_DQS_QSPI_A_DQS { + pinmux = <0x3033012c 1 0x0 0 0x30330394>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_gpio_io_gpio3_io16: IOMUXC_NAND_READY_B_GPIO_IO_GPIO3_IO16 { + pinmux = <0x30330134 5 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_ready_b_nand_ready_b_nand_ready_b: IOMUXC_NAND_READY_B_NAND_READY_B_NAND_READY_B { + pinmux = <0x30330134 0 0x0 0 0x3033039c>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_gpio_io_gpio3_io15: IOMUXC_NAND_RE_B_GPIO_IO_GPIO3_IO15 { + pinmux = <0x30330130 5 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_nand_re_b_nand_re_b: IOMUXC_NAND_RE_B_NAND_RE_B_NAND_RE_B { + pinmux = <0x30330130 0 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_re_b_qspi_b_dqs_qspi_b_dqs: IOMUXC_NAND_RE_B_QSPI_B_DQS_QSPI_B_DQS { + pinmux = <0x30330130 1 0x0 0 0x30330398>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_gpio_io_gpio3_io17: IOMUXC_NAND_WE_B_GPIO_IO_GPIO3_IO17 { + pinmux = <0x30330138 5 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_we_b_nand_we_b_nand_we_b: IOMUXC_NAND_WE_B_NAND_WE_B_NAND_WE_B { + pinmux = <0x30330138 0 0x0 0 0x303303a0>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_gpio_io_gpio3_io18: IOMUXC_NAND_WP_B_GPIO_IO_GPIO3_IO18 { + pinmux = <0x3033013c 5 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_nand_wp_b_nand_wp_b_nand_wp_b: IOMUXC_NAND_WP_B_NAND_WP_B_NAND_WP_B { + pinmux = <0x3033013c 0 0x0 0 0x303303a4>; + }; + /omit-if-no-ref/ iomuxc_onoff_snvs_onoff_snvs_onoff: IOMUXC_ONOFF_SNVS_ONOFF_SNVS_ONOFF { + pinmux = <0x0 0 0x0 0 0x30330284>; + }; + /omit-if-no-ref/ iomuxc_pmic_on_req_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x0 0 0x0 0 0x30330280>; + }; + /omit-if-no-ref/ iomuxc_pmic_stby_req_ccm_pmic_stby_req_ccm_pmic_stby_req: IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ { + pinmux = <0x0 0 0x0 0 0x3033027c>; + }; + /omit-if-no-ref/ iomuxc_por_b_snvs_por_b_snvs_por_b: IOMUXC_POR_B_SNVS_POR_B_SNVS_POR_B { + pinmux = <0x0 0 0x0 0 0x30330288>; + }; + /omit-if-no-ref/ iomuxc_rtc_snvs_rtc_snvs_rtc: IOMUXC_RTC_SNVS_RTC_SNVS_RTC { + pinmux = <0x0 0 0x0 0 0x30330278>; + }; + /omit-if-no-ref/ iomuxc_rtc_reset_b_snvs_rtc_reset_b_snvs_rtc_reset_b: IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B_SNVS_RTC_RESET_B { + pinmux = <0x0 0 0x0 0 0x3033028c>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_gpio_io_gpio4_io20: IOMUXC_SAI1_MCLK_GPIO_IO_GPIO4_IO20 { + pinmux = <0x303301ac 5 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai1_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI1_MCLK { + pinmux = <0x303301ac 0 0x0 0 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI1_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301ac 1 0x3033052c 1 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x303301ac 2 0x303304c8 2 0x30330414>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_arm_platform_trace_ctl_arm_platform_trace_ctl: IOMUXC_SAI1_RXC_ARM_PLATFORM_TRACE_CTL_ARM_PLATFORM_TRACE_CTL { + pinmux = <0x30330160 4 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_gpio_io_gpio4_io01: IOMUXC_SAI1_RXC_GPIO_IO_GPIO4_IO01 { + pinmux = <0x30330160 5 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai1_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x30330160 0 0x0 0 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI1_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330160 1 0x303304d0 1 0x303303c8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_arm_platform_trace_arm_platform_trace0: IOMUXC_SAI1_RXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE0 { + pinmux = <0x30330164 4 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_gpio4_io02: IOMUXC_SAI1_RXD0_GPIO_IO_GPIO4_IO02 { + pinmux = <0x30330164 5 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai1_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA0 { + pinmux = <0x30330164 0 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330164 1 0x303304d4 1 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_src_boot_cfg_src_boot_cfg0: IOMUXC_SAI1_RXD0_SRC_BOOT_CFG_SRC_BOOT_CFG0 { + pinmux = <0x30330164 6 0x0 0 0x303303cc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_arm_platform_trace_arm_platform_trace1: IOMUXC_SAI1_RXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE1 { + pinmux = <0x30330168 4 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_gpio_io_gpio4_io03: IOMUXC_SAI1_RXD1_GPIO_IO_GPIO4_IO03 { + pinmux = <0x30330168 5 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai1_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI1_RX_DATA1 { + pinmux = <0x30330168 0 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI1_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x30330168 1 0x303304d8 1 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd1_src_boot_cfg_src_boot_cfg1: IOMUXC_SAI1_RXD1_SRC_BOOT_CFG_SRC_BOOT_CFG1 { + pinmux = <0x30330168 6 0x0 0 0x303303d0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_arm_platform_trace_arm_platform_trace2: IOMUXC_SAI1_RXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE2 { + pinmux = <0x3033016c 4 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_gpio_io_gpio4_io04: IOMUXC_SAI1_RXD2_GPIO_IO_GPIO4_IO04 { + pinmux = <0x3033016c 5 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai1_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI1_RX_DATA2 { + pinmux = <0x3033016c 0 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI1_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x3033016c 1 0x303304dc 1 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd2_src_boot_cfg_src_boot_cfg2: IOMUXC_SAI1_RXD2_SRC_BOOT_CFG_SRC_BOOT_CFG2 { + pinmux = <0x3033016c 6 0x0 0 0x303303d4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_arm_platform_trace_arm_platform_trace3: IOMUXC_SAI1_RXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE3 { + pinmux = <0x30330170 4 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_gpio_io_gpio4_io05: IOMUXC_SAI1_RXD3_GPIO_IO_GPIO4_IO05 { + pinmux = <0x30330170 5 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai1_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI1_RX_DATA3 { + pinmux = <0x30330170 0 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI1_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330170 1 0x303304e0 1 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd3_src_boot_cfg_src_boot_cfg3: IOMUXC_SAI1_RXD3_SRC_BOOT_CFG_SRC_BOOT_CFG3 { + pinmux = <0x30330170 6 0x0 0 0x303303d8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_arm_platform_trace_arm_platform_trace4: IOMUXC_SAI1_RXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE4 { + pinmux = <0x30330174 4 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_gpio_io_gpio4_io06: IOMUXC_SAI1_RXD4_GPIO_IO_GPIO4_IO06 { + pinmux = <0x30330174 5 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_RXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x30330174 2 0x30330510 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_rx_data_sai1_rx_data4: IOMUXC_SAI1_RXD4_SAI_RX_DATA_SAI1_RX_DATA4 { + pinmux = <0x30330174 0 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_RXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x30330174 1 0x3033051c 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd4_src_boot_cfg_src_boot_cfg4: IOMUXC_SAI1_RXD4_SRC_BOOT_CFG_SRC_BOOT_CFG4 { + pinmux = <0x30330174 6 0x0 0 0x303303dc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_arm_platform_trace_arm_platform_trace5: IOMUXC_SAI1_RXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE5 { + pinmux = <0x30330178 4 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_gpio_io_gpio4_io07: IOMUXC_SAI1_RXD5_GPIO_IO_GPIO4_IO07 { + pinmux = <0x30330178 5 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai1_rx_data5: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI1_RX_DATA5 { + pinmux = <0x30330178 0 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_RXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x30330178 2 0x30330514 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXD5_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x30330178 3 0x303304c4 1 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_RXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x30330178 1 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd5_src_boot_cfg_src_boot_cfg5: IOMUXC_SAI1_RXD5_SRC_BOOT_CFG_SRC_BOOT_CFG5 { + pinmux = <0x30330178 6 0x0 0 0x303303e0>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_arm_platform_trace_arm_platform_trace6: IOMUXC_SAI1_RXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE6 { + pinmux = <0x3033017c 4 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_gpio_io_gpio4_io08: IOMUXC_SAI1_RXD6_GPIO_IO_GPIO4_IO08 { + pinmux = <0x3033017c 5 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_data_sai1_rx_data6: IOMUXC_SAI1_RXD6_SAI_RX_DATA_SAI1_RX_DATA6 { + pinmux = <0x3033017c 0 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_RXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x3033017c 2 0x30330518 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_RXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x3033017c 1 0x30330520 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd6_src_boot_cfg_src_boot_cfg6: IOMUXC_SAI1_RXD6_SRC_BOOT_CFG_SRC_BOOT_CFG6 { + pinmux = <0x3033017c 6 0x0 0 0x303303e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_arm_platform_trace_arm_platform_trace7: IOMUXC_SAI1_RXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE7 { + pinmux = <0x30330180 4 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_gpio_io_gpio4_io09: IOMUXC_SAI1_RXD7_GPIO_IO_GPIO4_IO09 { + pinmux = <0x30330180 5 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_RXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x30330180 1 0x30330530 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_rx_data_sai1_rx_data7: IOMUXC_SAI1_RXD7_SAI_RX_DATA_SAI1_RX_DATA7 { + pinmux = <0x30330180 0 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_RXD7_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330180 3 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_RXD7_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330180 2 0x303304cc 4 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd7_src_boot_cfg_src_boot_cfg7: IOMUXC_SAI1_RXD7_SRC_BOOT_CFG_SRC_BOOT_CFG7 { + pinmux = <0x30330180 6 0x0 0 0x303303e8>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_arm_platform_trace_clk_arm_platform_trace_clk: IOMUXC_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK_ARM_PLATFORM_TRACE_CLK { + pinmux = <0x3033015c 4 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_gpio_io_gpio4_io00: IOMUXC_SAI1_RXFS_GPIO_IO_GPIO4_IO00 { + pinmux = <0x3033015c 5 0x0 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai1_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x3033015c 0 0x303304c4 0 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI1_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x3033015c 1 0x303304e4 1 0x303303c4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_arm_platform_eventi_arm_platform_eventi: IOMUXC_SAI1_TXC_ARM_PLATFORM_EVENTI_ARM_PLATFORM_EVENTI { + pinmux = <0x30330188 4 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_gpio4_io11: IOMUXC_SAI1_TXC_GPIO_IO_GPIO4_IO11 { + pinmux = <0x30330188 5 0x0 0 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330188 0 0x303304c8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330188 1 0x303304e8 1 0x303303f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_arm_platform_trace_arm_platform_trace8: IOMUXC_SAI1_TXD0_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE8 { + pinmux = <0x3033018c 4 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_gpio4_io12: IOMUXC_SAI1_TXD0_GPIO_IO_GPIO4_IO12 { + pinmux = <0x3033018c 5 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai1_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x3033018c 0 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x3033018c 1 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_src_boot_cfg_src_boot_cfg8: IOMUXC_SAI1_TXD0_SRC_BOOT_CFG_SRC_BOOT_CFG8 { + pinmux = <0x3033018c 6 0x0 0 0x303303f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_arm_platform_trace_arm_platform_trace9: IOMUXC_SAI1_TXD1_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE9 { + pinmux = <0x30330190 4 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_gpio_io_gpio4_io13: IOMUXC_SAI1_TXD1_GPIO_IO_GPIO4_IO13 { + pinmux = <0x30330190 5 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai1_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330190 0 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_sai_tx_data_sai5_tx_data1: IOMUXC_SAI1_TXD1_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x30330190 1 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd1_src_boot_cfg_src_boot_cfg9: IOMUXC_SAI1_TXD1_SRC_BOOT_CFG_SRC_BOOT_CFG9 { + pinmux = <0x30330190 6 0x0 0 0x303303f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_arm_platform_trace_arm_platform_trace10: IOMUXC_SAI1_TXD2_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE10 { + pinmux = <0x30330194 4 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_gpio_io_gpio4_io14: IOMUXC_SAI1_TXD2_GPIO_IO_GPIO4_IO14 { + pinmux = <0x30330194 5 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai1_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330194 0 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_sai_tx_data_sai5_tx_data2: IOMUXC_SAI1_TXD2_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x30330194 1 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd2_src_boot_cfg_src_boot_cfg10: IOMUXC_SAI1_TXD2_SRC_BOOT_CFG_SRC_BOOT_CFG10 { + pinmux = <0x30330194 6 0x0 0 0x303303fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_arm_platform_trace_arm_platform_trace11: IOMUXC_SAI1_TXD3_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE11 { + pinmux = <0x30330198 4 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_gpio_io_gpio4_io15: IOMUXC_SAI1_TXD3_GPIO_IO_GPIO4_IO15 { + pinmux = <0x30330198 5 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai1_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x30330198 0 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_sai_tx_data_sai5_tx_data3: IOMUXC_SAI1_TXD3_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x30330198 1 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd3_src_boot_cfg_src_boot_cfg11: IOMUXC_SAI1_TXD3_SRC_BOOT_CFG_SRC_BOOT_CFG11 { + pinmux = <0x30330198 6 0x0 0 0x30330400>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_arm_platform_trace_arm_platform_trace12: IOMUXC_SAI1_TXD4_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE12 { + pinmux = <0x3033019c 4 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_gpio_io_gpio4_io16: IOMUXC_SAI1_TXD4_GPIO_IO_GPIO4_IO16 { + pinmux = <0x3033019c 5 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_rx_bclk_sai6_rx_bclk: IOMUXC_SAI1_TXD4_SAI_RX_BCLK_SAI6_RX_BCLK { + pinmux = <0x3033019c 1 0x30330510 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_bclk_sai6_tx_bclk: IOMUXC_SAI1_TXD4_SAI_TX_BCLK_SAI6_TX_BCLK { + pinmux = <0x3033019c 2 0x3033051c 1 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_sai_tx_data_sai1_tx_data4: IOMUXC_SAI1_TXD4_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x3033019c 0 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd4_src_boot_cfg_src_boot_cfg12: IOMUXC_SAI1_TXD4_SRC_BOOT_CFG_SRC_BOOT_CFG12 { + pinmux = <0x3033019c 6 0x0 0 0x30330404>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_arm_platform_trace_arm_platform_trace13: IOMUXC_SAI1_TXD5_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE13 { + pinmux = <0x303301a0 4 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_gpio_io_gpio4_io17: IOMUXC_SAI1_TXD5_GPIO_IO_GPIO4_IO17 { + pinmux = <0x303301a0 5 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_rx_data_sai6_rx_data0: IOMUXC_SAI1_TXD5_SAI_RX_DATA_SAI6_RX_DATA0 { + pinmux = <0x303301a0 1 0x30330514 1 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai1_tx_data5: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x303301a0 0 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_sai_tx_data_sai6_tx_data0: IOMUXC_SAI1_TXD5_SAI_TX_DATA_SAI6_TX_DATA0 { + pinmux = <0x303301a0 2 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd5_src_boot_cfg_src_boot_cfg13: IOMUXC_SAI1_TXD5_SRC_BOOT_CFG_SRC_BOOT_CFG13 { + pinmux = <0x303301a0 6 0x0 0 0x30330408>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_arm_platform_trace_arm_platform_trace14: IOMUXC_SAI1_TXD6_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE14 { + pinmux = <0x303301a4 4 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_gpio_io_gpio4_io18: IOMUXC_SAI1_TXD6_GPIO_IO_GPIO4_IO18 { + pinmux = <0x303301a4 5 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_rx_sync_sai6_rx_sync: IOMUXC_SAI1_TXD6_SAI_RX_SYNC_SAI6_RX_SYNC { + pinmux = <0x303301a4 1 0x30330518 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_data_sai1_tx_data6: IOMUXC_SAI1_TXD6_SAI_TX_DATA_SAI1_TX_DATA6 { + pinmux = <0x303301a4 0 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_sai_tx_sync_sai6_tx_sync: IOMUXC_SAI1_TXD6_SAI_TX_SYNC_SAI6_TX_SYNC { + pinmux = <0x303301a4 2 0x30330520 1 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd6_src_boot_cfg_src_boot_cfg14: IOMUXC_SAI1_TXD6_SRC_BOOT_CFG_SRC_BOOT_CFG14 { + pinmux = <0x303301a4 6 0x0 0 0x3033040c>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_arm_platform_trace_arm_platform_trace15: IOMUXC_SAI1_TXD7_ARM_PLATFORM_TRACE_ARM_PLATFORM_TRACE15 { + pinmux = <0x303301a8 4 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_gpio_io_gpio4_io19: IOMUXC_SAI1_TXD7_GPIO_IO_GPIO4_IO19 { + pinmux = <0x303301a8 5 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_mclk_sai6_mclk: IOMUXC_SAI1_TXD7_SAI_MCLK_SAI6_MCLK { + pinmux = <0x303301a8 1 0x30330530 1 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_sai_tx_data_sai1_tx_data7: IOMUXC_SAI1_TXD7_SAI_TX_DATA_SAI1_TX_DATA7 { + pinmux = <0x303301a8 0 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd7_src_boot_cfg_src_boot_cfg15: IOMUXC_SAI1_TXD7_SRC_BOOT_CFG_SRC_BOOT_CFG15 { + pinmux = <0x303301a8 6 0x0 0 0x30330410>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_arm_platform_evento_arm_platform_evento: IOMUXC_SAI1_TXFS_ARM_PLATFORM_EVENTO_ARM_PLATFORM_EVENTO { + pinmux = <0x30330184 4 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_gpio4_io10: IOMUXC_SAI1_TXFS_GPIO_IO_GPIO4_IO10 { + pinmux = <0x30330184 5 0x0 0 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330184 0 0x303304cc 3 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x30330184 1 0x303304ec 1 0x303303ec>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_gpio_io_gpio4_io27: IOMUXC_SAI2_MCLK_GPIO_IO_GPIO4_IO27 { + pinmux = <0x303301c8 5 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai2_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI2_MCLK { + pinmux = <0x303301c8 0 0x0 0 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI2_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301c8 1 0x3033052c 2 0x30330430>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_gpio_io_gpio4_io22: IOMUXC_SAI2_RXC_GPIO_IO_GPIO4_IO22 { + pinmux = <0x303301b4 5 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_rx_bclk_sai2_rx_bclk: IOMUXC_SAI2_RXC_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x303301b4 0 0x0 0 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxc_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI2_RXC_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x303301b4 1 0x303304e8 2 0x3033041c>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_gpio_io_gpio4_io23: IOMUXC_SAI2_RXD0_GPIO_IO_GPIO4_IO23 { + pinmux = <0x303301b8 5 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_rx_data_sai2_rx_data0: IOMUXC_SAI2_RXD0_SAI_RX_DATA_SAI2_RX_DATA0 { + pinmux = <0x303301b8 0 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxd0_sai_tx_data_sai5_tx_data0: IOMUXC_SAI2_RXD0_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x303301b8 1 0x0 0 0x30330420>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_gpio_io_gpio4_io21: IOMUXC_SAI2_RXFS_GPIO_IO_GPIO4_IO21 { + pinmux = <0x303301b0 5 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_rx_sync_sai2_rx_sync: IOMUXC_SAI2_RXFS_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x303301b0 0 0x0 0 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_rxfs_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI2_RXFS_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x303301b0 1 0x303304ec 2 0x30330418>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_gpio_io_gpio4_io25: IOMUXC_SAI2_TXC_GPIO_IO_GPIO4_IO25 { + pinmux = <0x303301c0 5 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_SAI2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x303301c0 0 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txc_sai_tx_data_sai5_tx_data2: IOMUXC_SAI2_TXC_SAI_TX_DATA_SAI5_TX_DATA2 { + pinmux = <0x303301c0 1 0x0 0 0x30330428>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_gpio_io_gpio4_io26: IOMUXC_SAI2_TXD0_GPIO_IO_GPIO4_IO26 { + pinmux = <0x303301c4 5 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai2_tx_data0: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI2_TX_DATA0 { + pinmux = <0x303301c4 0 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txd0_sai_tx_data_sai5_tx_data3: IOMUXC_SAI2_TXD0_SAI_TX_DATA_SAI5_TX_DATA3 { + pinmux = <0x303301c4 1 0x0 0 0x3033042c>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_gpio_io_gpio4_io24: IOMUXC_SAI2_TXFS_GPIO_IO_GPIO4_IO24 { + pinmux = <0x303301bc 5 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_data_sai5_tx_data1: IOMUXC_SAI2_TXFS_SAI_TX_DATA_SAI5_TX_DATA1 { + pinmux = <0x303301bc 1 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai2_txfs_sai_tx_sync_sai2_tx_sync: IOMUXC_SAI2_TXFS_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x303301bc 0 0x0 0 0x30330424>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_gpio_io_gpio5_io02: IOMUXC_SAI3_MCLK_GPIO_IO_GPIO5_IO02 { + pinmux = <0x303301e4 5 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_pwm_out_pwm4_out: IOMUXC_SAI3_MCLK_PWM_OUT_PWM4_OUT { + pinmux = <0x303301e4 1 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai3_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI3_MCLK { + pinmux = <0x303301e4 0 0x0 0 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI3_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x303301e4 2 0x3033052c 3 0x3033044c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpio_io_gpio4_io29: IOMUXC_SAI3_RXC_GPIO_IO_GPIO4_IO29 { + pinmux = <0x303301d0 5 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_gpt_capture_gpt1_capture2: IOMUXC_SAI3_RXC_GPT_CAPTURE_GPT1_CAPTURE2 { + pinmux = <0x303301d0 1 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai3_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x303301d0 0 0x0 0 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI3_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x303301d0 2 0x303304d0 2 0x30330438>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpio_io_gpio4_io30: IOMUXC_SAI3_RXD_GPIO_IO_GPIO4_IO30 { + pinmux = <0x303301d4 5 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_gpt_compare_gpt1_compare1: IOMUXC_SAI3_RXD_GPT_COMPARE_GPT1_COMPARE1 { + pinmux = <0x303301d4 1 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI3_RX_DATA0 { + pinmux = <0x303301d4 0 0x0 0 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxd_sai_rx_data_sai5_rx_data0: IOMUXC_SAI3_RXD_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x303301d4 2 0x303304d4 2 0x3033043c>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpio_io_gpio4_io28: IOMUXC_SAI3_RXFS_GPIO_IO_GPIO4_IO28 { + pinmux = <0x303301cc 5 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_gpt_capture_gpt1_capture1: IOMUXC_SAI3_RXFS_GPT_CAPTURE_GPT1_CAPTURE1 { + pinmux = <0x303301cc 1 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai3_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x303301cc 0 0x0 0 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI3_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x303301cc 2 0x303304e4 2 0x30330434>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpio_io_gpio5_io00: IOMUXC_SAI3_TXC_GPIO_IO_GPIO5_IO00 { + pinmux = <0x303301dc 5 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_gpt_compare_gpt1_compare2: IOMUXC_SAI3_TXC_GPT_COMPARE_GPT1_COMPARE2 { + pinmux = <0x303301dc 1 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_rx_data_sai5_rx_data2: IOMUXC_SAI3_TXC_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x303301dc 2 0x303304dc 2 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk: IOMUXC_SAI3_TXC_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x303301dc 0 0x0 0 0x30330444>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpio_io_gpio5_io01: IOMUXC_SAI3_TXD_GPIO_IO_GPIO5_IO01 { + pinmux = <0x303301e0 5 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_gpt_compare_gpt1_compare3: IOMUXC_SAI3_TXD_GPT_COMPARE_GPT1_COMPARE3 { + pinmux = <0x303301e0 1 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_rx_data_sai5_rx_data3: IOMUXC_SAI3_TXD_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x303301e0 2 0x303304e0 2 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0: IOMUXC_SAI3_TXD_SAI_TX_DATA_SAI3_TX_DATA0 { + pinmux = <0x303301e0 0 0x0 0 0x30330448>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpio_io_gpio4_io31: IOMUXC_SAI3_TXFS_GPIO_IO_GPIO4_IO31 { + pinmux = <0x303301d8 5 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_gpt_clk_gpt1_clk: IOMUXC_SAI3_TXFS_GPT_CLK_GPT1_CLK { + pinmux = <0x303301d8 1 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_rx_data_sai5_rx_data1: IOMUXC_SAI3_TXFS_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x303301d8 2 0x303304d8 2 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync: IOMUXC_SAI3_TXFS_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x303301d8 0 0x0 0 0x30330440>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_gpio_io_gpio3_io25: IOMUXC_SAI5_MCLK_GPIO_IO_GPIO3_IO25 { + pinmux = <0x30330158 5 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai4_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI4_MCLK { + pinmux = <0x30330158 2 0x0 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_mclk_sai5_mclk: IOMUXC_SAI5_MCLK_SAI_MCLK_SAI5_MCLK { + pinmux = <0x30330158 0 0x3033052c 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_mclk_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI5_MCLK_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x30330158 1 0x303304c8 0 0x303303c0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_gpio_io_gpio3_io20: IOMUXC_SAI5_RXC_GPIO_IO_GPIO3_IO20 { + pinmux = <0x30330144 5 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SAI5_RXC_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x30330144 0 0x303304d0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxc_sai_tx_data_sai1_tx_data1: IOMUXC_SAI5_RXC_SAI_TX_DATA_SAI1_TX_DATA1 { + pinmux = <0x30330144 1 0x0 0 0x303303ac>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_gpio_io_gpio3_io21: IOMUXC_SAI5_RXD0_GPIO_IO_GPIO3_IO21 { + pinmux = <0x30330148 5 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_rx_data_sai5_rx_data0: IOMUXC_SAI5_RXD0_SAI_RX_DATA_SAI5_RX_DATA0 { + pinmux = <0x30330148 0 0x303304d4 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd0_sai_tx_data_sai1_tx_data2: IOMUXC_SAI5_RXD0_SAI_TX_DATA_SAI1_TX_DATA2 { + pinmux = <0x30330148 1 0x0 0 0x303303b0>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_gpio_io_gpio3_io22: IOMUXC_SAI5_RXD1_GPIO_IO_GPIO3_IO22 { + pinmux = <0x3033014c 5 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_rx_data_sai5_rx_data1: IOMUXC_SAI5_RXD1_SAI_RX_DATA_SAI5_RX_DATA1 { + pinmux = <0x3033014c 0 0x303304d8 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_data_sai1_tx_data3: IOMUXC_SAI5_RXD1_SAI_TX_DATA_SAI1_TX_DATA3 { + pinmux = <0x3033014c 1 0x0 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x3033014c 2 0x303304cc 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd1_sai_tx_sync_sai5_tx_sync: IOMUXC_SAI5_RXD1_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x3033014c 3 0x303304ec 0 0x303303b4>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_gpio_io_gpio3_io23: IOMUXC_SAI5_RXD2_GPIO_IO_GPIO3_IO23 { + pinmux = <0x30330150 5 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_rx_data_sai5_rx_data2: IOMUXC_SAI5_RXD2_SAI_RX_DATA_SAI5_RX_DATA2 { + pinmux = <0x30330150 0 0x303304dc 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SAI5_RXD2_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x30330150 3 0x303304e8 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_data_sai1_tx_data4: IOMUXC_SAI5_RXD2_SAI_TX_DATA_SAI1_TX_DATA4 { + pinmux = <0x30330150 1 0x0 0 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd2_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD2_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330150 2 0x303304cc 1 0x303303b8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_gpio_io_gpio3_io24: IOMUXC_SAI5_RXD3_GPIO_IO_GPIO3_IO24 { + pinmux = <0x30330154 5 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_rx_data_sai5_rx_data3: IOMUXC_SAI5_RXD3_SAI_RX_DATA_SAI5_RX_DATA3 { + pinmux = <0x30330154 0 0x303304e0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai1_tx_data5: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI1_TX_DATA5 { + pinmux = <0x30330154 1 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_data_sai5_tx_data0: IOMUXC_SAI5_RXD3_SAI_TX_DATA_SAI5_TX_DATA0 { + pinmux = <0x30330154 3 0x0 0 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxd3_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI5_RXD3_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x30330154 2 0x303304cc 2 0x303303bc>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_gpio_io_gpio3_io19: IOMUXC_SAI5_RXFS_GPIO_IO_GPIO3_IO19 { + pinmux = <0x30330140 5 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_rx_sync_sai5_rx_sync: IOMUXC_SAI5_RXFS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x30330140 0 0x303304e4 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sai5_rxfs_sai_tx_data_sai1_tx_data0: IOMUXC_SAI5_RXFS_SAI_TX_DATA_SAI1_TX_DATA0 { + pinmux = <0x30330140 1 0x0 0 0x303303a8>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_gpio2_io00: IOMUXC_SD1_CLK_GPIO_IO_GPIO2_IO00 { + pinmux = <0x303300a0 5 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x303300a0 0 0x0 0 0x30330308>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_gpio2_io01: IOMUXC_SD1_CMD_GPIO_IO_GPIO2_IO01 { + pinmux = <0x303300a4 5 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x303300a4 0 0x0 0 0x3033030c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_gpio2_io02: IOMUXC_SD1_DATA0_GPIO_IO_GPIO2_IO02 { + pinmux = <0x303300a8 5 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x303300a8 0 0x0 0 0x30330310>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_gpio2_io03: IOMUXC_SD1_DATA1_GPIO_IO_GPIO2_IO03 { + pinmux = <0x303300ac 5 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x303300ac 0 0x0 0 0x30330314>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_gpio2_io04: IOMUXC_SD1_DATA2_GPIO_IO_GPIO2_IO04 { + pinmux = <0x303300b0 5 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x303300b0 0 0x0 0 0x30330318>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_gpio2_io05: IOMUXC_SD1_DATA3_GPIO_IO_GPIO2_IO05 { + pinmux = <0x303300b4 5 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x303300b4 0 0x0 0 0x3033031c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_gpio2_io06: IOMUXC_SD1_DATA4_GPIO_IO_GPIO2_IO06 { + pinmux = <0x303300b8 5 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x303300b8 0 0x0 0 0x30330320>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_gpio2_io07: IOMUXC_SD1_DATA5_GPIO_IO_GPIO2_IO07 { + pinmux = <0x303300bc 5 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x303300bc 0 0x0 0 0x30330324>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_gpio2_io08: IOMUXC_SD1_DATA6_GPIO_IO_GPIO2_IO08 { + pinmux = <0x303300c0 5 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x303300c0 0 0x0 0 0x30330328>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_gpio2_io09: IOMUXC_SD1_DATA7_GPIO_IO_GPIO2_IO09 { + pinmux = <0x303300c4 5 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x303300c4 0 0x0 0 0x3033032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_gpio_io_gpio2_io10: IOMUXC_SD1_RESET_B_GPIO_IO_GPIO2_IO10 { + pinmux = <0x303300c8 5 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_reset_b_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_RESET_B_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x303300c8 0 0x0 0 0x30330330>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_gpio2_io11: IOMUXC_SD1_STROBE_GPIO_IO_GPIO2_IO11 { + pinmux = <0x303300cc 5 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x303300cc 0 0x0 0 0x30330334>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_gpio2_io12: IOMUXC_SD2_CD_B_GPIO_IO_GPIO2_IO12 { + pinmux = <0x303300d0 5 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x303300d0 0 0x0 0 0x30330338>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_gpio2_io13: IOMUXC_SD2_CLK_GPIO_IO_GPIO2_IO13 { + pinmux = <0x303300d4 5 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x303300d4 0 0x0 0 0x3033033c>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_gpio2_io14: IOMUXC_SD2_CMD_GPIO_IO_GPIO2_IO14 { + pinmux = <0x303300d8 5 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x303300d8 0 0x0 0 0x30330340>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_gpio2_io15: IOMUXC_SD2_DATA0_GPIO_IO_GPIO2_IO15 { + pinmux = <0x303300dc 5 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x303300dc 0 0x0 0 0x30330344>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_gpio2_io16: IOMUXC_SD2_DATA1_GPIO_IO_GPIO2_IO16 { + pinmux = <0x303300e0 5 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x303300e0 0 0x0 0 0x30330348>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_gpio2_io17: IOMUXC_SD2_DATA2_GPIO_IO_GPIO2_IO17 { + pinmux = <0x303300e4 5 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x303300e4 0 0x0 0 0x3033034c>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_gpio2_io18: IOMUXC_SD2_DATA3_GPIO_IO_GPIO2_IO18 { + pinmux = <0x303300e8 5 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x303300e8 0 0x0 0 0x30330350>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_gpio2_io19: IOMUXC_SD2_RESET_B_GPIO_IO_GPIO2_IO19 { + pinmux = <0x303300ec 5 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x303300ec 0 0x0 0 0x30330354>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_gpio_io_gpio2_io20: IOMUXC_SD2_WP_GPIO_IO_GPIO2_IO20 { + pinmux = <0x303300f0 5 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_sd2_wp_usdhc_wp_usdhc2_wp: IOMUXC_SD2_WP_USDHC_WP_USDHC2_WP { + pinmux = <0x303300f0 0 0x0 0 0x30330358>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_gpio_io_gpio5_io05: IOMUXC_SPDIF_EXT_CLK_GPIO_IO_GPIO5_IO05 { + pinmux = <0x303301f0 5 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_pwm_out_pwm1_out: IOMUXC_SPDIF_EXT_CLK_PWM_OUT_PWM1_OUT { + pinmux = <0x303301f0 1 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_ext_clk_spdif_ext_clk_spdif_ext_clk: IOMUXC_SPDIF_EXT_CLK_SPDIF_EXT_CLK_SPDIF_EXT_CLK { + pinmux = <0x303301f0 0 0x0 0 0x30330458>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_gpio_io_gpio5_io04: IOMUXC_SPDIF_RX_GPIO_IO_GPIO5_IO04 { + pinmux = <0x303301ec 5 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_pwm_out_pwm2_out: IOMUXC_SPDIF_RX_PWM_OUT_PWM2_OUT { + pinmux = <0x303301ec 1 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_rx_spdif_in_spdif_in: IOMUXC_SPDIF_RX_SPDIF_IN_SPDIF_IN { + pinmux = <0x303301ec 0 0x0 0 0x30330454>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_gpio_io_gpio5_io03: IOMUXC_SPDIF_TX_GPIO_IO_GPIO5_IO03 { + pinmux = <0x303301e8 5 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_pwm_out_pwm3_out: IOMUXC_SPDIF_TX_PWM_OUT_PWM3_OUT { + pinmux = <0x303301e8 1 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_spdif_tx_spdif_out_spdif_out: IOMUXC_SPDIF_TX_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x303301e8 0 0x0 0 0x30330450>; + }; + /omit-if-no-ref/ iomuxc_test_mode_tcu_test_mode_tcu_test_mode: IOMUXC_TEST_MODE_TCU_TEST_MODE_TCU_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x30330254>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_ecspi_sclk_ecspi3_sclk: IOMUXC_UART1_RXD_ECSPI_SCLK_ECSPI3_SCLK { + pinmux = <0x30330234 1 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_gpio5_io22: IOMUXC_UART1_RXD_GPIO_IO_GPIO5_IO22 { + pinmux = <0x30330234 5 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_rx_uart1_rx: IOMUXC_UART1_RXD_UART_RX_UART1_RX { + pinmux = <0x30330234 0 0x303304f4 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_uart_tx_uart1_rx: IOMUXC_UART1_RXD_UART_TX_UART1_RX { + pinmux = <0x30330234 0 0x0 0 0x3033049c>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_ecspi_mosi_ecspi3_mosi: IOMUXC_UART1_TXD_ECSPI_MOSI_ECSPI3_MOSI { + pinmux = <0x30330238 1 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_gpio5_io23: IOMUXC_UART1_TXD_GPIO_IO_GPIO5_IO23 { + pinmux = <0x30330238 5 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_rx_uart1_tx: IOMUXC_UART1_TXD_UART_RX_UART1_TX { + pinmux = <0x30330238 0 0x303304f4 1 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_uart_tx_uart1_tx: IOMUXC_UART1_TXD_UART_TX_UART1_TX { + pinmux = <0x30330238 0 0x0 0 0x303304a0>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_ecspi_miso_ecspi3_miso: IOMUXC_UART2_RXD_ECSPI_MISO_ECSPI3_MISO { + pinmux = <0x3033023c 1 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_gpio5_io24: IOMUXC_UART2_RXD_GPIO_IO_GPIO5_IO24 { + pinmux = <0x3033023c 5 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_rx_uart2_rx: IOMUXC_UART2_RXD_UART_RX_UART2_RX { + pinmux = <0x3033023c 0 0x303304fc 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_uart_tx_uart2_rx: IOMUXC_UART2_RXD_UART_TX_UART2_RX { + pinmux = <0x3033023c 0 0x0 0 0x303304a4>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_ecspi_ss_ecspi3_ss0: IOMUXC_UART2_TXD_ECSPI_SS_ECSPI3_SS0 { + pinmux = <0x30330240 1 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_gpio5_io25: IOMUXC_UART2_TXD_GPIO_IO_GPIO5_IO25 { + pinmux = <0x30330240 5 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_rx_uart2_tx: IOMUXC_UART2_TXD_UART_RX_UART2_TX { + pinmux = <0x30330240 0 0x303304fc 1 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_uart_tx_uart2_tx: IOMUXC_UART2_TXD_UART_TX_UART2_TX { + pinmux = <0x30330240 0 0x0 0 0x303304a8>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_gpio_io_gpio5_io26: IOMUXC_UART3_RXD_GPIO_IO_GPIO5_IO26 { + pinmux = <0x30330244 5 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_cts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_CTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rts_b_uart1_cts_b: IOMUXC_UART3_RXD_UART_RTS_B_UART1_CTS_B { + pinmux = <0x30330244 1 0x303304f0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_rx_uart3_rx: IOMUXC_UART3_RXD_UART_RX_UART3_RX { + pinmux = <0x30330244 0 0x30330504 2 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_rxd_uart_tx_uart3_rx: IOMUXC_UART3_RXD_UART_TX_UART3_RX { + pinmux = <0x30330244 0 0x0 0 0x303304ac>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_gpio_io_gpio5_io27: IOMUXC_UART3_TXD_GPIO_IO_GPIO5_IO27 { + pinmux = <0x30330248 5 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_cts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_CTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rts_b_uart1_rts_b: IOMUXC_UART3_TXD_UART_RTS_B_UART1_RTS_B { + pinmux = <0x30330248 1 0x303304f0 1 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_rx_uart3_tx: IOMUXC_UART3_TXD_UART_RX_UART3_TX { + pinmux = <0x30330248 0 0x30330504 3 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart3_txd_uart_tx_uart3_tx: IOMUXC_UART3_TXD_UART_TX_UART3_TX { + pinmux = <0x30330248 0 0x0 0 0x303304b0>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_gpio_io_gpio5_io28: IOMUXC_UART4_RXD_GPIO_IO_GPIO5_IO28 { + pinmux = <0x3033024c 5 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_UART4_RXD_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x3033024c 2 0x30330524 1 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_cts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_CTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rts_b_uart2_cts_b: IOMUXC_UART4_RXD_UART_RTS_B_UART2_CTS_B { + pinmux = <0x3033024c 1 0x303304f8 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_rx_uart4_rx: IOMUXC_UART4_RXD_UART_RX_UART4_RX { + pinmux = <0x3033024c 0 0x3033050c 2 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_rxd_uart_tx_uart4_rx: IOMUXC_UART4_RXD_UART_TX_UART4_RX { + pinmux = <0x3033024c 0 0x0 0 0x303304b4>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_gpio_io_gpio5_io29: IOMUXC_UART4_TXD_GPIO_IO_GPIO5_IO29 { + pinmux = <0x30330250 5 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_pcie_clkreq_b_pcie2_clkreq_b: IOMUXC_UART4_TXD_PCIE_CLKREQ_B_PCIE2_CLKREQ_B { + pinmux = <0x30330250 2 0x30330528 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_cts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_CTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x0 0 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rts_b_uart2_rts_b: IOMUXC_UART4_TXD_UART_RTS_B_UART2_RTS_B { + pinmux = <0x30330250 1 0x303304f8 1 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_rx_uart4_tx: IOMUXC_UART4_TXD_UART_RX_UART4_TX { + pinmux = <0x30330250 0 0x3033050c 3 0x303304b8>; + }; + /omit-if-no-ref/ iomuxc_uart4_txd_uart_tx_uart4_tx: IOMUXC_UART4_TXD_UART_TX_UART4_TX { + pinmux = <0x30330250 0 0x0 0 0x303304b8>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx9351avtxm-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx9351avtxm-pinctrl.dtsi new file mode 100644 index 000000000..4cde60783 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx9351avtxm-pinctrl.dtsi @@ -0,0 +1,1831 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX9351AVTXM + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc1_ccm_clko1_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko1: IOMUXC1_CCM_CLKO1_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO1 { + pinmux = <0x443c0088 0 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_flexio_flexio_flexio1_flexio26: IOMUXC1_CCM_CLKO1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO26 { + pinmux = <0x443c0088 4 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_gpio_io_gpio3_io26: IOMUXC1_CCM_CLKO1_GPIO_IO_GPIO3_IO26 { + pinmux = <0x443c0088 5 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko2: IOMUXC1_CCM_CLKO2_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO2 { + pinmux = <0x443c008c 0 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_flexio_flexio_flexio1_flexio27: IOMUXC1_CCM_CLKO2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c008c 4 0x443c03c8 1 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_gpio_io_gpio3_io27: IOMUXC1_CCM_CLKO2_GPIO_IO_GPIO3_IO27 { + pinmux = <0x443c008c 5 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko3: IOMUXC1_CCM_CLKO3_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO3 { + pinmux = <0x443c0090 0 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_flexio_flexio_flexio2_flexio28: IOMUXC1_CCM_CLKO3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO28 { + pinmux = <0x443c0090 4 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_gpio_io_gpio4_io28: IOMUXC1_CCM_CLKO3_GPIO_IO_GPIO4_IO28 { + pinmux = <0x443c0090 5 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko4: IOMUXC1_CCM_CLKO4_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO4 { + pinmux = <0x443c0094 0 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_flexio_flexio_flexio2_flexio29: IOMUXC1_CCM_CLKO4_FLEXIO_FLEXIO_FLEXIO2_FLEXIO29 { + pinmux = <0x443c0094 4 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_gpio_io_gpio4_io29: IOMUXC1_CCM_CLKO4_GPIO_IO_GPIO4_IO29 { + pinmux = <0x443c0094 5 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_flexio_flexio_flexio1_flexio30: IOMUXC1_DAP_TCLK_SWCLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO30 { + pinmux = <0x443c0008 4 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30: IOMUXC1_DAP_TCLK_SWCLK_GPIO_IO_GPIO3_IO30 { + pinmux = <0x443c0008 5 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_jtag_mux_tck_jtag_mux_tck: IOMUXC1_DAP_TCLK_SWCLK_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0008 0 0x443c03d4 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_DAP_TCLK_SWCLK_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0008 6 0x443c042c 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_can_tx_can2_tx: IOMUXC1_DAP_TDI_CAN_TX_CAN2_TX { + pinmux = <0x443c0000 3 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_flexio_flexio_flexio2_flexio30: IOMUXC1_DAP_TDI_FLEXIO_FLEXIO_FLEXIO2_FLEXIO30 { + pinmux = <0x443c0000 4 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_gpio_io_gpio3_io28: IOMUXC1_DAP_TDI_GPIO_IO_GPIO3_IO28 { + pinmux = <0x443c0000 5 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_DAP_TDI_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0000 0 0x443c03d8 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_lpuart_rx_lpuart5_rx: IOMUXC1_DAP_TDI_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0000 6 0x443c0430 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_mqs_left_mqs2_left: IOMUXC1_DAP_TDI_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0000 1 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_can_rx_can2_rx: IOMUXC1_DAP_TDO_TRACESWO_CAN_RX_CAN2_RX { + pinmux = <0x443c000c 3 0x443c0364 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_flexio_flexio_flexio1_flexio31: IOMUXC1_DAP_TDO_TRACESWO_FLEXIO_FLEXIO_FLEXIO1_FLEXIO31 { + pinmux = <0x443c000c 4 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31: IOMUXC1_DAP_TDO_TRACESWO_GPIO_IO_GPIO3_IO31 { + pinmux = <0x443c000c 5 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_DAP_TDO_TRACESWO_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c000c 0 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_lpuart_tx_lpuart5_tx: IOMUXC1_DAP_TDO_TRACESWO_LPUART_TX_LPUART5_TX { + pinmux = <0x443c000c 6 0x443c0434 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_mqs_right_mqs2_right: IOMUXC1_DAP_TDO_TRACESWO_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c000c 1 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_flexio_flexio_flexio2_flexio31: IOMUXC1_DAP_TMS_SWDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO31 { + pinmux = <0x443c0004 4 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29: IOMUXC1_DAP_TMS_SWDIO_GPIO_IO_GPIO3_IO29 { + pinmux = <0x443c0004 5 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_jtag_mux_tms_jtag_mux_tms: IOMUXC1_DAP_TMS_SWDIO_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c0004 0 0x443c03dc 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_DAP_TMS_SWDIO_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c0004 6 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC1_ENET1_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x443c0098 0 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_flexio_flexio_flexio2_flexio00: IOMUXC1_ENET1_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO00 { + pinmux = <0x443c0098 4 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_gpio_io_gpio4_io00: IOMUXC1_ENET1_MDC_GPIO_IO_GPIO4_IO00 { + pinmux = <0x443c0098 5 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_hsiomix_otg_id_hsiomix_otg_id1: IOMUXC1_ENET1_MDC_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID1 { + pinmux = <0x443c0098 3 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_i3c_scl_i3c2_scl: IOMUXC1_ENET1_MDC_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0098 2 0x443c03cc 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_lpuart_dcb_b_lpuart3_dcb_b: IOMUXC1_ENET1_MDC_LPUART_DCB_B_LPUART3_DCB_B { + pinmux = <0x443c0098 1 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC1_ENET1_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x443c009c 0 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_flexio_flexio_flexio2_flexio01: IOMUXC1_ENET1_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO01 { + pinmux = <0x443c009c 4 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_gpio_io_gpio4_io01: IOMUXC1_ENET1_MDIO_GPIO_IO_GPIO4_IO01 { + pinmux = <0x443c009c 5 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_hsiomix_otg_pwr_hsiomix_otg_pwr1: IOMUXC1_ENET1_MDIO_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR1 { + pinmux = <0x443c009c 3 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_i3c_sda_i3c2_sda: IOMUXC1_ENET1_MDIO_I3C_SDA_I3C2_SDA { + pinmux = <0x443c009c 2 0x443c03d0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_lpuart_rin_b_lpuart3_rin_b: IOMUXC1_ENET1_MDIO_LPUART_RIN_B_LPUART3_RIN_B { + pinmux = <0x443c009c 1 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC1_ENET1_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x443c00c0 0 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_flexio_flexio_flexio2_flexio10: IOMUXC1_ENET1_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO10 { + pinmux = <0x443c00c0 4 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_gpio_io_gpio4_io10: IOMUXC1_ENET1_RD0_GPIO_IO_GPIO4_IO10 { + pinmux = <0x443c00c0 5 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_lpuart_rx_lpuart3_rx: IOMUXC1_ENET1_RD0_LPUART_RX_LPUART3_RX { + pinmux = <0x443c00c0 1 0x443c0418 1 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC1_ENET1_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x443c00c4 0 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_flexio_flexio_flexio2_flexio11: IOMUXC1_ENET1_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO11 { + pinmux = <0x443c00c4 4 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_gpio_io_gpio4_io11: IOMUXC1_ENET1_RD1_GPIO_IO_GPIO4_IO11 { + pinmux = <0x443c00c4 5 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lptmr_alt_lptmr2_alt1: IOMUXC1_ENET1_RD1_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c00c4 3 0x443c0408 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_ENET1_RD1_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c00c4 1 0x443c0414 1 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC1_ENET1_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x443c00c8 0 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_flexio_flexio_flexio2_flexio12: IOMUXC1_ENET1_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO12 { + pinmux = <0x443c00c8 4 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_gpio_io_gpio4_io12: IOMUXC1_ENET1_RD2_GPIO_IO_GPIO4_IO12 { + pinmux = <0x443c00c8 5 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_lptmr_alt_lptmr2_alt2: IOMUXC1_ENET1_RD2_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c00c8 3 0x443c040c 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC1_ENET1_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x443c00cc 0 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_flexio_flexio_flexio2_flexio13: IOMUXC1_ENET1_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO13 { + pinmux = <0x443c00cc 4 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_gpio_io_gpio4_io13: IOMUXC1_ENET1_RD3_GPIO_IO_GPIO4_IO13 { + pinmux = <0x443c00cc 5 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_lptmr_alt_lptmr2_alt3: IOMUXC1_ENET1_RD3_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c00cc 3 0x443c0410 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_ccm_enet_qos_clock_generate_rx_clk_ccm_enet_qos_clock_generate_rx_clk: IOMUXC1_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK { + pinmux = <0x443c00bc 0 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC1_ENET1_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x443c00bc 1 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_flexio_flexio_flexio2_flexio09: IOMUXC1_ENET1_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO09 { + pinmux = <0x443c00bc 4 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_gpio_io_gpio4_io09: IOMUXC1_ENET1_RXC_GPIO_IO_GPIO4_IO09 { + pinmux = <0x443c00bc 5 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC1_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x443c00b8 0 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_flexio_flexio_flexio2_flexio08: IOMUXC1_ENET1_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO08 { + pinmux = <0x443c00b8 4 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08: IOMUXC1_ENET1_RX_CTL_GPIO_IO_GPIO4_IO08 { + pinmux = <0x443c00b8 5 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_hsiomix_otg_pwr_hsiomix_otg_pwr2: IOMUXC1_ENET1_RX_CTL_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR2 { + pinmux = <0x443c00b8 3 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_lpuart_dsr_b_lpuart3_dsr_b: IOMUXC1_ENET1_RX_CTL_LPUART_DSR_B_LPUART3_DSR_B { + pinmux = <0x443c00b8 1 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC1_ENET1_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x443c00ac 0 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_flexio_flexio_flexio2_flexio05: IOMUXC1_ENET1_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO05 { + pinmux = <0x443c00ac 4 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_gpio_io_gpio4_io05: IOMUXC1_ENET1_TD0_GPIO_IO_GPIO4_IO05 { + pinmux = <0x443c00ac 5 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_lpuart_tx_lpuart3_tx: IOMUXC1_ENET1_TD0_LPUART_TX_LPUART3_TX { + pinmux = <0x443c00ac 1 0x443c041c 1 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC1_ENET1_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x443c00a8 0 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_flexio_flexio_flexio2_flexio04: IOMUXC1_ENET1_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO04 { + pinmux = <0x443c00a8 4 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_gpio_io_gpio4_io04: IOMUXC1_ENET1_TD1_GPIO_IO_GPIO4_IO04 { + pinmux = <0x443c00a8 5 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_hsiomix_otg_oc_hsiomix_otg_oc1: IOMUXC1_ENET1_TD1_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC1 { + pinmux = <0x443c00a8 3 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_b_i3c2_pur_b: IOMUXC1_ENET1_TD1_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c00a8 6 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_i3c2_pur: IOMUXC1_ENET1_TD1_I3C_PUR_I3C2_PUR { + pinmux = <0x443c00a8 2 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_ENET1_TD1_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c00a8 1 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_can_rx_can2_rx: IOMUXC1_ENET1_TD2_CAN_RX_CAN2_RX { + pinmux = <0x443c00a4 2 0x443c0364 2 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_ccm_enet_qos_clock_generate_ref_clk_ccm_enet_qos_clock_generate_ref_clk: IOMUXC1_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK { + pinmux = <0x443c00a4 1 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC1_ENET1_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x443c00a4 0 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_flexio_flexio_flexio2_flexio03: IOMUXC1_ENET1_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO03 { + pinmux = <0x443c00a4 4 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_gpio_io_gpio4_io03: IOMUXC1_ENET1_TD2_GPIO_IO_GPIO4_IO03 { + pinmux = <0x443c00a4 5 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_hsiomix_otg_oc_hsiomix_otg_oc2: IOMUXC1_ENET1_TD2_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC2 { + pinmux = <0x443c00a4 3 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_can_tx_can2_tx: IOMUXC1_ENET1_TD3_CAN_TX_CAN2_TX { + pinmux = <0x443c00a0 2 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC1_ENET1_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x443c00a0 0 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_flexio_flexio_flexio2_flexio02: IOMUXC1_ENET1_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO02 { + pinmux = <0x443c00a0 4 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_gpio_io_gpio4_io02: IOMUXC1_ENET1_TD3_GPIO_IO_GPIO4_IO02 { + pinmux = <0x443c00a0 5 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_hsiomix_otg_id_hsiomix_otg_id2: IOMUXC1_ENET1_TD3_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID2 { + pinmux = <0x443c00a0 3 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_ccm_enet_qos_clock_generate_tx_clk_ccm_enet_qos_clock_generate_tx_clk: IOMUXC1_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK { + pinmux = <0x443c00b4 0 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC1_ENET1_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x443c00b4 1 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_flexio_flexio_flexio2_flexio07: IOMUXC1_ENET1_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO07 { + pinmux = <0x443c00b4 4 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_gpio_io_gpio4_io07: IOMUXC1_ENET1_TXC_GPIO_IO_GPIO4_IO07 { + pinmux = <0x443c00b4 5 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC1_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x443c00b0 0 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_flexio_flexio_flexio2_flexio06: IOMUXC1_ENET1_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO06 { + pinmux = <0x443c00b0 4 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06: IOMUXC1_ENET1_TX_CTL_GPIO_IO_GPIO4_IO06 { + pinmux = <0x443c00b0 5 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_lpuart_dtr_b_lpuart3_dtr_b: IOMUXC1_ENET1_TX_CTL_LPUART_DTR_B_LPUART3_DTR_B { + pinmux = <0x443c00b0 1 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_enet_mdc_enet1_mdc: IOMUXC1_ENET2_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x443c00d0 0 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_flexio_flexio_flexio2_flexio14: IOMUXC1_ENET2_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO14 { + pinmux = <0x443c00d0 4 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_gpio_io_gpio4_io14: IOMUXC1_ENET2_MDC_GPIO_IO_GPIO4_IO14 { + pinmux = <0x443c00d0 5 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_lpuart_dcb_b_lpuart4_dcb_b: IOMUXC1_ENET2_MDC_LPUART_DCB_B_LPUART4_DCB_B { + pinmux = <0x443c00d0 1 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_sai_rx_sync_sai2_rx_sync: IOMUXC1_ENET2_MDC_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x443c00d0 2 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_enet_mdio_enet1_mdio: IOMUXC1_ENET2_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x443c00d4 0 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_flexio_flexio_flexio2_flexio15: IOMUXC1_ENET2_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO15 { + pinmux = <0x443c00d4 4 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_gpio_io_gpio4_io15: IOMUXC1_ENET2_MDIO_GPIO_IO_GPIO4_IO15 { + pinmux = <0x443c00d4 5 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_lpuart_rin_b_lpuart4_rin_b: IOMUXC1_ENET2_MDIO_LPUART_RIN_B_LPUART4_RIN_B { + pinmux = <0x443c00d4 1 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_sai_rx_bclk_sai2_rx_bclk: IOMUXC1_ENET2_MDIO_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x443c00d4 2 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC1_ENET2_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x443c00f8 0 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_flexio_flexio_flexio2_flexio24: IOMUXC1_ENET2_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO24 { + pinmux = <0x443c00f8 4 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_gpio_io_gpio4_io24: IOMUXC1_ENET2_RD0_GPIO_IO_GPIO4_IO24 { + pinmux = <0x443c00f8 5 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_lpuart_rx_lpuart4_rx: IOMUXC1_ENET2_RD0_LPUART_RX_LPUART4_RX { + pinmux = <0x443c00f8 1 0x443c0424 1 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_sai_tx_data_sai2_tx_data02: IOMUXC1_ENET2_RD0_SAI_TX_DATA_SAI2_TX_DATA02 { + pinmux = <0x443c00f8 2 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC1_ENET2_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x443c00fc 0 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_flexio_flexio_flexio2_flexio25: IOMUXC1_ENET2_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO25 { + pinmux = <0x443c00fc 4 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_gpio_io_gpio4_io25: IOMUXC1_ENET2_RD1_GPIO_IO_GPIO4_IO25 { + pinmux = <0x443c00fc 5 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_sai_tx_data_sai2_tx_data03: IOMUXC1_ENET2_RD1_SAI_TX_DATA_SAI2_TX_DATA03 { + pinmux = <0x443c00fc 2 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_spdif_in_spdif_in: IOMUXC1_ENET2_RD1_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c00fc 1 0x443c0454 1 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC1_ENET2_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x443c0100 0 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_flexio_flexio_flexio2_flexio26: IOMUXC1_ENET2_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO26 { + pinmux = <0x443c0100 4 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_gpio_io_gpio4_io26: IOMUXC1_ENET2_RD2_GPIO_IO_GPIO4_IO26 { + pinmux = <0x443c0100 5 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_ENET2_RD2_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0100 1 0x443c0420 1 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_mqs_right_mqs2_right: IOMUXC1_ENET2_RD2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0100 3 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_sai_mclk_sai2_mclk: IOMUXC1_ENET2_RD2_SAI_MCLK_SAI2_MCLK { + pinmux = <0x443c0100 2 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC1_ENET2_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x443c0104 0 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_flexio_flexio_flexio2_flexio27: IOMUXC1_ENET2_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO27 { + pinmux = <0x443c0104 4 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_gpio_io_gpio4_io27: IOMUXC1_ENET2_RD3_GPIO_IO_GPIO4_IO27 { + pinmux = <0x443c0104 5 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_mqs_left_mqs2_left: IOMUXC1_ENET2_RD3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0104 3 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_in_spdif_in: IOMUXC1_ENET2_RD3_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0104 2 0x443c0454 2 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_out_spdif_out: IOMUXC1_ENET2_RD3_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c0104 1 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC1_ENET2_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x443c00f4 0 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rx_er_enet1_rx_er: IOMUXC1_ENET2_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x443c00f4 1 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_flexio_flexio_flexio2_flexio23: IOMUXC1_ENET2_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO23 { + pinmux = <0x443c00f4 4 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_gpio_io_gpio4_io23: IOMUXC1_ENET2_RXC_GPIO_IO_GPIO4_IO23 { + pinmux = <0x443c00f4 5 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_sai_tx_data_sai2_tx_data01: IOMUXC1_ENET2_RXC_SAI_TX_DATA_SAI2_TX_DATA01 { + pinmux = <0x443c00f4 2 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC1_ENET2_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x443c00f0 0 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_flexio_flexio_flexio2_flexio22: IOMUXC1_ENET2_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO22 { + pinmux = <0x443c00f0 4 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22: IOMUXC1_ENET2_RX_CTL_GPIO_IO_GPIO4_IO22 { + pinmux = <0x443c00f0 5 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_lpuart_dsr_b_lpuart4_dsr_b: IOMUXC1_ENET2_RX_CTL_LPUART_DSR_B_LPUART4_DSR_B { + pinmux = <0x443c00f0 1 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_sai_tx_data_sai2_tx_data00: IOMUXC1_ENET2_RX_CTL_SAI_TX_DATA_SAI2_TX_DATA00 { + pinmux = <0x443c00f0 2 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC1_ENET2_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x443c00e4 0 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_flexio_flexio_flexio2_flexio19: IOMUXC1_ENET2_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO19 { + pinmux = <0x443c00e4 4 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_gpio_io_gpio4_io19: IOMUXC1_ENET2_TD0_GPIO_IO_GPIO4_IO19 { + pinmux = <0x443c00e4 5 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_lpuart_tx_lpuart4_tx: IOMUXC1_ENET2_TD0_LPUART_TX_LPUART4_TX { + pinmux = <0x443c00e4 1 0x443c0428 1 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_sai_rx_data_sai2_rx_data03: IOMUXC1_ENET2_TD0_SAI_RX_DATA_SAI2_RX_DATA03 { + pinmux = <0x443c00e4 2 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC1_ENET2_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x443c00e0 0 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_flexio_flexio_flexio2_flexio18: IOMUXC1_ENET2_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO18 { + pinmux = <0x443c00e0 4 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_gpio_io_gpio4_io18: IOMUXC1_ENET2_TD1_GPIO_IO_GPIO4_IO18 { + pinmux = <0x443c00e0 5 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_ENET2_TD1_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c00e0 1 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_sai_rx_data_sai2_rx_data02: IOMUXC1_ENET2_TD1_SAI_RX_DATA_SAI2_RX_DATA02 { + pinmux = <0x443c00e0 2 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC1_ENET2_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x443c00dc 0 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_tx_clk_enet1_tx_clk: IOMUXC1_ENET2_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x443c00dc 1 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_flexio_flexio_flexio2_flexio17: IOMUXC1_ENET2_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO17 { + pinmux = <0x443c00dc 4 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_gpio_io_gpio4_io17: IOMUXC1_ENET2_TD2_GPIO_IO_GPIO4_IO17 { + pinmux = <0x443c00dc 5 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_sai_rx_data_sai2_rx_data01: IOMUXC1_ENET2_TD2_SAI_RX_DATA_SAI2_RX_DATA01 { + pinmux = <0x443c00dc 2 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC1_ENET2_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x443c00d8 0 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_flexio_flexio_flexio2_flexio16: IOMUXC1_ENET2_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO16 { + pinmux = <0x443c00d8 4 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_gpio_io_gpio4_io16: IOMUXC1_ENET2_TD3_GPIO_IO_GPIO4_IO16 { + pinmux = <0x443c00d8 5 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_sai_rx_data_sai2_rx_data00: IOMUXC1_ENET2_TD3_SAI_RX_DATA_SAI2_RX_DATA00 { + pinmux = <0x443c00d8 2 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC1_ENET2_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x443c00ec 0 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_tx_er_enet1_tx_er: IOMUXC1_ENET2_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x443c00ec 1 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_flexio_flexio_flexio2_flexio21: IOMUXC1_ENET2_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO21 { + pinmux = <0x443c00ec 4 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_gpio_io_gpio4_io21: IOMUXC1_ENET2_TXC_GPIO_IO_GPIO4_IO21 { + pinmux = <0x443c00ec 5 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC1_ENET2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x443c00ec 2 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC1_ENET2_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x443c00e8 0 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_flexio_flexio_flexio2_flexio20: IOMUXC1_ENET2_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO20 { + pinmux = <0x443c00e8 4 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20: IOMUXC1_ENET2_TX_CTL_GPIO_IO_GPIO4_IO20 { + pinmux = <0x443c00e8 5 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_lpuart_dtr_b_lpuart4_dtr_b: IOMUXC1_ENET2_TX_CTL_LPUART_DTR_B_LPUART4_DTR_B { + pinmux = <0x443c00e8 1 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_sai_tx_sync_sai2_tx_sync: IOMUXC1_ENET2_TX_CTL_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x443c00e8 2 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_flexio_flexio_flexio1_flexio00: IOMUXC1_GPIO_IO00_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0010 7 0x443c036c 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_gpio_io_gpio2_io00: IOMUXC1_GPIO_IO00_GPIO_IO_GPIO2_IO00 { + pinmux = <0x443c0010 0 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0010 1 0x443c03e4 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0010 6 0x443c03ec 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpspi_pcs_lpspi6_pcs0: IOMUXC1_GPIO_IO00_LPSPI_PCS_LPSPI6_PCS0 { + pinmux = <0x443c0010 4 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpuart_tx_lpuart5_tx: IOMUXC1_GPIO_IO00_LPUART_TX_LPUART5_TX { + pinmux = <0x443c0010 5 0x443c0434 1 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_cam_clk_mediamix_cam_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_CAM_CLK_MEDIAMIX_CAM_CLK { + pinmux = <0x443c0010 2 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_disp_clk_mediamix_disp_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_DISP_CLK_MEDIAMIX_DISP_CLK { + pinmux = <0x443c0010 3 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_flexio_flexio_flexio1_flexio01: IOMUXC1_GPIO_IO01_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0014 7 0x443c0370 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_gpio_io_gpio2_io01: IOMUXC1_GPIO_IO01_GPIO_IO_GPIO2_IO01 { + pinmux = <0x443c0014 0 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0014 1 0x443c03e0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c0014 6 0x443c03e8 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpspi_sin_lpspi6_sin: IOMUXC1_GPIO_IO01_LPSPI_SIN_LPSPI6_SIN { + pinmux = <0x443c0014 4 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpuart_rx_lpuart5_rx: IOMUXC1_GPIO_IO01_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0014 5 0x443c0430 1 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_cam_data_mediamix_cam_data00: IOMUXC1_GPIO_IO01_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA00 { + pinmux = <0x443c0014 2 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_disp_de_mediamix_disp_de: IOMUXC1_GPIO_IO01_MEDIAMIX_DISP_DE_MEDIAMIX_DISP_DE { + pinmux = <0x443c0014 3 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_flexio_flexio_flexio1_flexio02: IOMUXC1_GPIO_IO02_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0018 7 0x443c0374 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_gpio_io_gpio2_io02: IOMUXC1_GPIO_IO02_GPIO_IO_GPIO2_IO02 { + pinmux = <0x443c0018 0 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C4_SDA { + pinmux = <0x443c0018 1 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0018 6 0x443c03f4 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpspi_sout_lpspi6_sout: IOMUXC1_GPIO_IO02_LPSPI_SOUT_LPSPI6_SOUT { + pinmux = <0x443c0018 4 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_GPIO_IO02_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0018 5 0x443c042c 1 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_cam_vsync_mediamix_cam_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_CAM_VSYNC_MEDIAMIX_CAM_VSYNC { + pinmux = <0x443c0018 2 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_disp_vsync_mediamix_disp_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_DISP_VSYNC_MEDIAMIX_DISP_VSYNC { + pinmux = <0x443c0018 3 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_flexio_flexio_flexio1_flexio03: IOMUXC1_GPIO_IO03_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c001c 7 0x443c0378 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_gpio_io_gpio2_io03: IOMUXC1_GPIO_IO03_GPIO_IO_GPIO2_IO03 { + pinmux = <0x443c001c 0 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C4_SCL { + pinmux = <0x443c001c 1 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c001c 6 0x443c03f0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpspi_sck_lpspi6_sck: IOMUXC1_GPIO_IO03_LPSPI_SCK_LPSPI6_SCK { + pinmux = <0x443c001c 4 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_GPIO_IO03_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c001c 5 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_cam_hsync_mediamix_cam_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_CAM_HSYNC_MEDIAMIX_CAM_HSYNC { + pinmux = <0x443c001c 2 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_disp_hsync_mediamix_disp_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_DISP_HSYNC_MEDIAMIX_DISP_HSYNC { + pinmux = <0x443c001c 3 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_flexio_flexio_flexio1_flexio04: IOMUXC1_GPIO_IO04_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0020 7 0x443c037c 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_gpio_io_gpio2_io04: IOMUXC1_GPIO_IO04_GPIO_IO_GPIO2_IO04 { + pinmux = <0x443c0020 0 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO04_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0020 6 0x443c03f4 1 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpspi_pcs_lpspi7_pcs0: IOMUXC1_GPIO_IO04_LPSPI_PCS_LPSPI7_PCS0 { + pinmux = <0x443c0020 4 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpuart_tx_lpuart6_tx: IOMUXC1_GPIO_IO04_LPUART_TX_LPUART6_TX { + pinmux = <0x443c0020 5 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_mediamix_disp_data_mediamix_disp_data00: IOMUXC1_GPIO_IO04_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA00 { + pinmux = <0x443c0020 3 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO04_PDM_CLK_PDM_CLK { + pinmux = <0x443c0020 2 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_tpm_ch_tpm3_ch0: IOMUXC1_GPIO_IO04_TPM_CH_TPM3_CH0 { + pinmux = <0x443c0020 1 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_flexio_flexio_flexio1_flexio05: IOMUXC1_GPIO_IO05_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0024 7 0x443c0380 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_gpio_io_gpio2_io05: IOMUXC1_GPIO_IO05_GPIO_IO_GPIO2_IO05 { + pinmux = <0x443c0024 0 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO05_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c0024 6 0x443c03f0 1 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpspi_sin_lpspi7_sin: IOMUXC1_GPIO_IO05_LPSPI_SIN_LPSPI7_SIN { + pinmux = <0x443c0024 4 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpuart_rx_lpuart6_rx: IOMUXC1_GPIO_IO05_LPUART_RX_LPUART6_RX { + pinmux = <0x443c0024 5 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_mediamix_disp_data_mediamix_disp_data01: IOMUXC1_GPIO_IO05_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA01 { + pinmux = <0x443c0024 3 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO05_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0024 2 0x443c0438 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_tpm_ch_tpm4_ch0: IOMUXC1_GPIO_IO05_TPM_CH_TPM4_CH0 { + pinmux = <0x443c0024 1 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_flexio_flexio_flexio1_flexio06: IOMUXC1_GPIO_IO06_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0028 7 0x443c0384 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_gpio_io_gpio2_io06: IOMUXC1_GPIO_IO06_GPIO_IO_GPIO2_IO06 { + pinmux = <0x443c0028 0 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO06_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0028 6 0x443c03fc 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpspi_sout_lpspi7_sout: IOMUXC1_GPIO_IO06_LPSPI_SOUT_LPSPI7_SOUT { + pinmux = <0x443c0028 4 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpuart_cts_b_lpuart6_cts_b: IOMUXC1_GPIO_IO06_LPUART_CTS_B_LPUART6_CTS_B { + pinmux = <0x443c0028 5 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_mediamix_disp_data_mediamix_disp_data02: IOMUXC1_GPIO_IO06_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA02 { + pinmux = <0x443c0028 3 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO06_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0028 2 0x443c043c 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_tpm_ch_tpm5_ch0: IOMUXC1_GPIO_IO06_TPM_CH_TPM5_CH0 { + pinmux = <0x443c0028 1 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_flexio_flexio_flexio1_flexio07: IOMUXC1_GPIO_IO07_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c002c 7 0x443c0388 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_gpio_io_gpio2_io07: IOMUXC1_GPIO_IO07_GPIO_IO_GPIO2_IO07 { + pinmux = <0x443c002c 0 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO07_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c002c 6 0x443c03f8 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1: IOMUXC1_GPIO_IO07_LPSPI_PCS_LPSPI3_PCS1 { + pinmux = <0x443c002c 1 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_sck_lpspi7_sck: IOMUXC1_GPIO_IO07_LPSPI_SCK_LPSPI7_SCK { + pinmux = <0x443c002c 4 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpuart_rts_b_lpuart6_rts_b: IOMUXC1_GPIO_IO07_LPUART_RTS_B_LPUART6_RTS_B { + pinmux = <0x443c002c 5 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_cam_data_mediamix_cam_data01: IOMUXC1_GPIO_IO07_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA01 { + pinmux = <0x443c002c 2 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_disp_data_mediamix_disp_data03: IOMUXC1_GPIO_IO07_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA03 { + pinmux = <0x443c002c 3 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_flexio_flexio_flexio1_flexio08: IOMUXC1_GPIO_IO08_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0030 7 0x443c038c 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_gpio_io_gpio2_io08: IOMUXC1_GPIO_IO08_GPIO_IO_GPIO2_IO08 { + pinmux = <0x443c0030 0 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO08_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0030 6 0x443c03fc 1 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0: IOMUXC1_GPIO_IO08_LPSPI_PCS_LPSPI3_PCS0 { + pinmux = <0x443c0030 1 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpuart_tx_lpuart7_tx: IOMUXC1_GPIO_IO08_LPUART_TX_LPUART7_TX { + pinmux = <0x443c0030 5 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_cam_data_mediamix_cam_data02: IOMUXC1_GPIO_IO08_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA02 { + pinmux = <0x443c0030 2 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_disp_data_mediamix_disp_data04: IOMUXC1_GPIO_IO08_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA04 { + pinmux = <0x443c0030 3 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_tpm_ch_tpm6_ch0: IOMUXC1_GPIO_IO08_TPM_CH_TPM6_CH0 { + pinmux = <0x443c0030 4 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_flexio_flexio_flexio1_flexio09: IOMUXC1_GPIO_IO09_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c0034 7 0x443c0390 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_gpio_io_gpio2_io09: IOMUXC1_GPIO_IO09_GPIO_IO_GPIO2_IO09 { + pinmux = <0x443c0034 0 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO09_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c0034 6 0x443c03f8 1 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin: IOMUXC1_GPIO_IO09_LPSPI_SIN_LPSPI3_SIN { + pinmux = <0x443c0034 1 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpuart_rx_lpuart7_rx: IOMUXC1_GPIO_IO09_LPUART_RX_LPUART7_RX { + pinmux = <0x443c0034 5 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_cam_data_mediamix_cam_data03: IOMUXC1_GPIO_IO09_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA03 { + pinmux = <0x443c0034 2 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_disp_data_mediamix_disp_data05: IOMUXC1_GPIO_IO09_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA05 { + pinmux = <0x443c0034 3 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_tpm_extclk_tpm3_extclk: IOMUXC1_GPIO_IO09_TPM_EXTCLK_TPM3_EXTCLK { + pinmux = <0x443c0034 4 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_flexio_flexio_flexio1_flexio10: IOMUXC1_GPIO_IO10_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0038 7 0x443c0394 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_gpio_io_gpio2_io10: IOMUXC1_GPIO_IO10_GPIO_IO_GPIO2_IO10 { + pinmux = <0x443c0038 0 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO10_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0038 6 0x443c0404 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout: IOMUXC1_GPIO_IO10_LPSPI_SOUT_LPSPI3_SOUT { + pinmux = <0x443c0038 1 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpuart_cts_b_lpuart7_cts_b: IOMUXC1_GPIO_IO10_LPUART_CTS_B_LPUART7_CTS_B { + pinmux = <0x443c0038 5 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_cam_data_mediamix_cam_data04: IOMUXC1_GPIO_IO10_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA04 { + pinmux = <0x443c0038 2 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_disp_data_mediamix_disp_data06: IOMUXC1_GPIO_IO10_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA06 { + pinmux = <0x443c0038 3 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_tpm_extclk_tpm4_extclk: IOMUXC1_GPIO_IO10_TPM_EXTCLK_TPM4_EXTCLK { + pinmux = <0x443c0038 4 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_flexio_flexio_flexio1_flexio11: IOMUXC1_GPIO_IO11_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c003c 7 0x443c0398 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_gpio_io_gpio2_io11: IOMUXC1_GPIO_IO11_GPIO_IO_GPIO2_IO11 { + pinmux = <0x443c003c 0 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO11_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c003c 6 0x443c0400 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck: IOMUXC1_GPIO_IO11_LPSPI_SCK_LPSPI3_SCK { + pinmux = <0x443c003c 1 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpuart_rts_b_lpuart7_rts_b: IOMUXC1_GPIO_IO11_LPUART_RTS_B_LPUART7_RTS_B { + pinmux = <0x443c003c 5 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_cam_data_mediamix_cam_data05: IOMUXC1_GPIO_IO11_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA05 { + pinmux = <0x443c003c 2 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_disp_data_mediamix_disp_data07: IOMUXC1_GPIO_IO11_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA07 { + pinmux = <0x443c003c 3 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_tpm_extclk_tpm5_extclk: IOMUXC1_GPIO_IO11_TPM_EXTCLK_TPM5_EXTCLK { + pinmux = <0x443c003c 4 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_gpio_io_gpio2_io12: IOMUXC1_GPIO_IO12_GPIO_IO_GPIO2_IO12 { + pinmux = <0x443c0040 0 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO12_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0040 6 0x443c0404 1 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpspi_pcs_lpspi8_pcs0: IOMUXC1_GPIO_IO12_LPSPI_PCS_LPSPI8_PCS0 { + pinmux = <0x443c0040 4 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpuart_tx_lpuart8_tx: IOMUXC1_GPIO_IO12_LPUART_TX_LPUART8_TX { + pinmux = <0x443c0040 5 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_mediamix_disp_data_mediamix_disp_data08: IOMUXC1_GPIO_IO12_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA08 { + pinmux = <0x443c0040 3 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO12_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0040 2 0x443c0440 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO12_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c0040 7 0x443c0450 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_tpm_ch_tpm3_ch2: IOMUXC1_GPIO_IO12_TPM_CH_TPM3_CH2 { + pinmux = <0x443c0040 1 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_flexio_flexio_flexio1_flexio13: IOMUXC1_GPIO_IO13_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c0044 7 0x443c039c 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_gpio_io_gpio2_io13: IOMUXC1_GPIO_IO13_GPIO_IO_GPIO2_IO13 { + pinmux = <0x443c0044 0 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO13_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c0044 6 0x443c0400 1 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpspi_sin_lpspi8_sin: IOMUXC1_GPIO_IO13_LPSPI_SIN_LPSPI8_SIN { + pinmux = <0x443c0044 4 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpuart_rx_lpuart8_rx: IOMUXC1_GPIO_IO13_LPUART_RX_LPUART8_RX { + pinmux = <0x443c0044 5 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_mediamix_disp_data_mediamix_disp_data09: IOMUXC1_GPIO_IO13_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA09 { + pinmux = <0x443c0044 3 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO13_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c0044 2 0x443c0444 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_tpm_ch_tpm4_ch2: IOMUXC1_GPIO_IO13_TPM_CH_TPM4_CH2 { + pinmux = <0x443c0044 1 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_flexio_flexio_flexio1_flexio14: IOMUXC1_GPIO_IO14_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0048 7 0x443c03a0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_gpio_io_gpio2_io14: IOMUXC1_GPIO_IO14_GPIO_IO_GPIO2_IO14 { + pinmux = <0x443c0048 0 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpspi_sout_lpspi8_sout: IOMUXC1_GPIO_IO14_LPSPI_SOUT_LPSPI8_SOUT { + pinmux = <0x443c0048 4 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_cts_b_lpuart8_cts_b: IOMUXC1_GPIO_IO14_LPUART_CTS_B_LPUART8_CTS_B { + pinmux = <0x443c0048 5 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart3_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART3_TX { + pinmux = <0x443c0048 1 0x443c041c 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart4_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART4_TX { + pinmux = <0x443c0048 6 0x443c0428 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_cam_data_mediamix_cam_data06: IOMUXC1_GPIO_IO14_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA06 { + pinmux = <0x443c0048 2 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_disp_data_mediamix_disp_data10: IOMUXC1_GPIO_IO14_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA10 { + pinmux = <0x443c0048 3 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_flexio_flexio_flexio1_flexio15: IOMUXC1_GPIO_IO15_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c004c 7 0x443c03a4 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_gpio_io_gpio2_io15: IOMUXC1_GPIO_IO15_GPIO_IO_GPIO2_IO15 { + pinmux = <0x443c004c 0 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpspi_sck_lpspi8_sck: IOMUXC1_GPIO_IO15_LPSPI_SCK_LPSPI8_SCK { + pinmux = <0x443c004c 4 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rts_b_lpuart8_rts_b: IOMUXC1_GPIO_IO15_LPUART_RTS_B_LPUART8_RTS_B { + pinmux = <0x443c004c 5 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart3_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART3_RX { + pinmux = <0x443c004c 1 0x443c0418 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart4_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART4_RX { + pinmux = <0x443c004c 6 0x443c0424 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_cam_data_mediamix_cam_data07: IOMUXC1_GPIO_IO15_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA07 { + pinmux = <0x443c004c 2 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_disp_data_mediamix_disp_data11: IOMUXC1_GPIO_IO15_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA11 { + pinmux = <0x443c004c 3 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_flexio_flexio_flexio1_flexio16: IOMUXC1_GPIO_IO16_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0050 7 0x443c03a8 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_gpio_io_gpio2_io16: IOMUXC1_GPIO_IO16_GPIO_IO_GPIO2_IO16 { + pinmux = <0x443c0050 0 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpspi_pcs_lpspi4_pcs2: IOMUXC1_GPIO_IO16_LPSPI_PCS_LPSPI4_PCS2 { + pinmux = <0x443c0050 5 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c0050 4 0x443c0414 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0050 6 0x443c0420 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_mediamix_disp_data_mediamix_disp_data12: IOMUXC1_GPIO_IO16_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA12 { + pinmux = <0x443c0050 3 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO16_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0050 2 0x443c0440 1 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk: IOMUXC1_GPIO_IO16_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x443c0050 1 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_flexio_flexio_flexio1_flexio17: IOMUXC1_GPIO_IO17_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c0054 7 0x443c03ac 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_gpio_io_gpio2_io17: IOMUXC1_GPIO_IO17_GPIO_IO_GPIO2_IO17 { + pinmux = <0x443c0054 0 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpspi_pcs_lpspi4_pcs1: IOMUXC1_GPIO_IO17_LPSPI_PCS_LPSPI4_PCS1 { + pinmux = <0x443c0054 5 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c0054 4 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c0054 6 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_cam_data_mediamix_cam_data08: IOMUXC1_GPIO_IO17_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA08 { + pinmux = <0x443c0054 2 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_disp_data_mediamix_disp_data13: IOMUXC1_GPIO_IO17_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA13 { + pinmux = <0x443c0054 3 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_sai_mclk_sai3_mclk: IOMUXC1_GPIO_IO17_SAI_MCLK_SAI3_MCLK { + pinmux = <0x443c0054 1 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_flexio_flexio_flexio1_flexio18: IOMUXC1_GPIO_IO18_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0058 7 0x443c03b0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_gpio_io_gpio2_io18: IOMUXC1_GPIO_IO18_GPIO_IO_GPIO2_IO18 { + pinmux = <0x443c0058 0 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi4_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI4_PCS0 { + pinmux = <0x443c0058 5 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi5_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI5_PCS0 { + pinmux = <0x443c0058 4 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_cam_data_mediamix_cam_data09: IOMUXC1_GPIO_IO18_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA09 { + pinmux = <0x443c0058 2 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_disp_data_mediamix_disp_data14: IOMUXC1_GPIO_IO18_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA14 { + pinmux = <0x443c0058 3 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO18_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0058 1 0x443c044c 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_tpm_ch_tpm5_ch2: IOMUXC1_GPIO_IO18_TPM_CH_TPM5_CH2 { + pinmux = <0x443c0058 6 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_gpio_io_gpio2_io19: IOMUXC1_GPIO_IO19_GPIO_IO_GPIO2_IO19 { + pinmux = <0x443c005c 0 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi4_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI4_SIN { + pinmux = <0x443c005c 5 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi5_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI5_SIN { + pinmux = <0x443c005c 4 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_mediamix_disp_data_mediamix_disp_data15: IOMUXC1_GPIO_IO19_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA15 { + pinmux = <0x443c005c 3 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO19_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c005c 2 0x443c0444 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO19_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c005c 1 0x443c0450 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO19_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c005c 7 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_tpm_ch_tpm6_ch2: IOMUXC1_GPIO_IO19_TPM_CH_TPM6_CH2 { + pinmux = <0x443c005c 6 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_flexio_flexio_flexio1_flexio20: IOMUXC1_GPIO_IO20_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0060 7 0x443c03b4 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_gpio_io_gpio2_io20: IOMUXC1_GPIO_IO20_GPIO_IO_GPIO2_IO20 { + pinmux = <0x443c0060 0 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi4_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI4_SOUT { + pinmux = <0x443c0060 5 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi5_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI5_SOUT { + pinmux = <0x443c0060 4 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_mediamix_disp_data_mediamix_disp_data16: IOMUXC1_GPIO_IO20_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA16 { + pinmux = <0x443c0060 3 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO20_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0060 2 0x443c0438 1 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data00: IOMUXC1_GPIO_IO20_SAI_RX_DATA_SAI3_RX_DATA00 { + pinmux = <0x443c0060 1 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_tpm_ch_tpm3_ch1: IOMUXC1_GPIO_IO20_TPM_CH_TPM3_CH1 { + pinmux = <0x443c0060 6 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_gpio_io_gpio2_io21: IOMUXC1_GPIO_IO21_GPIO_IO_GPIO2_IO21 { + pinmux = <0x443c0064 0 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi4_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI4_SCK { + pinmux = <0x443c0064 5 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi5_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI5_SCK { + pinmux = <0x443c0064 4 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_mediamix_disp_data_mediamix_disp_data17: IOMUXC1_GPIO_IO21_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA17 { + pinmux = <0x443c0064 3 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO21_PDM_CLK_PDM_CLK { + pinmux = <0x443c0064 2 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO21_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0064 7 0x443c044c 1 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO21_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c0064 1 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_tpm_ch_tpm4_ch1: IOMUXC1_GPIO_IO21_TPM_CH_TPM4_CH1 { + pinmux = <0x443c0064 6 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_flexio_flexio_flexio1_flexio22: IOMUXC1_GPIO_IO22_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0068 7 0x443c03b8 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_gpio_io_gpio2_io22: IOMUXC1_GPIO_IO22_GPIO_IO_GPIO2_IO22 { + pinmux = <0x443c0068 0 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO22_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0068 6 0x443c03ec 1 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_mediamix_disp_data_mediamix_disp_data18: IOMUXC1_GPIO_IO22_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA18 { + pinmux = <0x443c0068 3 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_spdif_in_spdif_in: IOMUXC1_GPIO_IO22_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0068 2 0x443c0454 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_ch_tpm5_ch1: IOMUXC1_GPIO_IO22_TPM_CH_TPM5_CH1 { + pinmux = <0x443c0068 4 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_extclk_tpm6_extclk: IOMUXC1_GPIO_IO22_TPM_EXTCLK_TPM6_EXTCLK { + pinmux = <0x443c0068 5 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_usdhc_clk_usdhc3_clk: IOMUXC1_GPIO_IO22_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0068 1 0x443c0458 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_flexio_flexio_flexio1_flexio23: IOMUXC1_GPIO_IO23_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c006c 7 0x443c03bc 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_gpio_io_gpio2_io23: IOMUXC1_GPIO_IO23_GPIO_IO_GPIO2_IO23 { + pinmux = <0x443c006c 0 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO23_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c006c 6 0x443c03e8 1 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_mediamix_disp_data_mediamix_disp_data19: IOMUXC1_GPIO_IO23_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA19 { + pinmux = <0x443c006c 3 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_spdif_out_spdif_out: IOMUXC1_GPIO_IO23_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c006c 2 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_tpm_ch_tpm6_ch1: IOMUXC1_GPIO_IO23_TPM_CH_TPM6_CH1 { + pinmux = <0x443c006c 4 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_usdhc_cmd_usdhc3_cmd: IOMUXC1_GPIO_IO23_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c006c 1 0x443c045c 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_flexio_flexio_flexio1_flexio24: IOMUXC1_GPIO_IO24_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0070 7 0x443c03c0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_gpio_io_gpio2_io24: IOMUXC1_GPIO_IO24_GPIO_IO_GPIO2_IO24 { + pinmux = <0x443c0070 0 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_GPIO_IO24_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c0070 5 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_lpspi_pcs_lpspi6_pcs1: IOMUXC1_GPIO_IO24_LPSPI_PCS_LPSPI6_PCS1 { + pinmux = <0x443c0070 6 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_mediamix_disp_data_mediamix_disp_data20: IOMUXC1_GPIO_IO24_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA20 { + pinmux = <0x443c0070 3 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_tpm_ch_tpm3_ch3: IOMUXC1_GPIO_IO24_TPM_CH_TPM3_CH3 { + pinmux = <0x443c0070 4 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_usdhc_data_usdhc3_data0: IOMUXC1_GPIO_IO24_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0070 1 0x443c0460 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_can_tx_can2_tx: IOMUXC1_GPIO_IO25_CAN_TX_CAN2_TX { + pinmux = <0x443c0074 2 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_flexio_flexio_flexio1_flexio25: IOMUXC1_GPIO_IO25_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c0074 7 0x443c03c4 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_gpio_io_gpio2_io25: IOMUXC1_GPIO_IO25_GPIO_IO_GPIO2_IO25 { + pinmux = <0x443c0074 0 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_jtag_mux_tck_jtag_mux_tck: IOMUXC1_GPIO_IO25_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0074 5 0x443c03d4 1 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_lpspi_pcs_lpspi7_pcs1: IOMUXC1_GPIO_IO25_LPSPI_PCS_LPSPI7_PCS1 { + pinmux = <0x443c0074 6 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_mediamix_disp_data_mediamix_disp_data21: IOMUXC1_GPIO_IO25_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA21 { + pinmux = <0x443c0074 3 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_tpm_ch_tpm4_ch3: IOMUXC1_GPIO_IO25_TPM_CH_TPM4_CH3 { + pinmux = <0x443c0074 4 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_usdhc_data_usdhc3_data1: IOMUXC1_GPIO_IO25_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0074 1 0x443c0464 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_gpio_io_gpio2_io26: IOMUXC1_GPIO_IO26_GPIO_IO_GPIO2_IO26 { + pinmux = <0x443c0078 0 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_GPIO_IO26_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0078 5 0x443c03d8 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_lpspi_pcs_lpspi8_pcs1: IOMUXC1_GPIO_IO26_LPSPI_PCS_LPSPI8_PCS1 { + pinmux = <0x443c0078 6 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_mediamix_disp_data_mediamix_disp_data22: IOMUXC1_GPIO_IO26_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA22 { + pinmux = <0x443c0078 3 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO26_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0078 2 0x443c043c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync: IOMUXC1_GPIO_IO26_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x443c0078 7 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_tpm_ch_tpm5_ch3: IOMUXC1_GPIO_IO26_TPM_CH_TPM5_CH3 { + pinmux = <0x443c0078 4 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_usdhc_data_usdhc3_data2: IOMUXC1_GPIO_IO26_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0078 1 0x443c0468 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_can_rx_can2_rx: IOMUXC1_GPIO_IO27_CAN_RX_CAN2_RX { + pinmux = <0x443c007c 2 0x443c0364 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_flexio_flexio_flexio1_flexio27: IOMUXC1_GPIO_IO27_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c007c 7 0x443c03c8 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_gpio_io_gpio2_io27: IOMUXC1_GPIO_IO27_GPIO_IO_GPIO2_IO27 { + pinmux = <0x443c007c 0 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_jtag_mux_tms_jtag_mux_tms: IOMUXC1_GPIO_IO27_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c007c 5 0x443c03dc 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_lpspi_pcs_lpspi5_pcs1: IOMUXC1_GPIO_IO27_LPSPI_PCS_LPSPI5_PCS1 { + pinmux = <0x443c007c 6 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_mediamix_disp_data_mediamix_disp_data23: IOMUXC1_GPIO_IO27_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA23 { + pinmux = <0x443c007c 3 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_tpm_ch_tpm6_ch3: IOMUXC1_GPIO_IO27_TPM_CH_TPM6_CH3 { + pinmux = <0x443c007c 4 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_usdhc_data_usdhc3_data3: IOMUXC1_GPIO_IO27_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c007c 1 0x443c046c 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_flexio_flexio_flexio1_flexio28: IOMUXC1_GPIO_IO28_FLEXIO_FLEXIO_FLEXIO1_FLEXIO28 { + pinmux = <0x443c0080 7 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_gpio_io_gpio2_io28: IOMUXC1_GPIO_IO28_GPIO_IO_GPIO2_IO28 { + pinmux = <0x443c0080 0 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO28_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0080 1 0x443c03e4 1 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_flexio_flexio_flexio1_flexio29: IOMUXC1_GPIO_IO29_FLEXIO_FLEXIO_FLEXIO1_FLEXIO29 { + pinmux = <0x443c0084 7 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_gpio_io_gpio2_io29: IOMUXC1_GPIO_IO29_GPIO_IO_GPIO2_IO29 { + pinmux = <0x443c0084 0 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO29_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0084 1 0x443c03e0 1 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_gpio_io_gpio1_io00: IOMUXC1_I2C1_SCL_GPIO_IO_GPIO1_IO00 { + pinmux = <0x443c0170 5 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_i3c_scl_i3c1_scl: IOMUXC1_I2C1_SCL_I3C_SCL_I3C1_SCL { + pinmux = <0x443c0170 1 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl: IOMUXC1_I2C1_SCL_LPI2C_SCL_LPI2C1_SCL { + pinmux = <0x443c0170 0 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpuart_dcb_b_lpuart1_dcb_b: IOMUXC1_I2C1_SCL_LPUART_DCB_B_LPUART1_DCB_B { + pinmux = <0x443c0170 2 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_tpm_ch_tpm2_ch0: IOMUXC1_I2C1_SCL_TPM_CH_TPM2_CH0 { + pinmux = <0x443c0170 3 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_gpio_io_gpio1_io01: IOMUXC1_I2C1_SDA_GPIO_IO_GPIO1_IO01 { + pinmux = <0x443c0174 5 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_i3c_sda_i3c1_sda: IOMUXC1_I2C1_SDA_I3C_SDA_I3C1_SDA { + pinmux = <0x443c0174 1 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda: IOMUXC1_I2C1_SDA_LPI2C_SDA_LPI2C1_SDA { + pinmux = <0x443c0174 0 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpuart_rin_b_lpuart1_rin_b: IOMUXC1_I2C1_SDA_LPUART_RIN_B_LPUART1_RIN_B { + pinmux = <0x443c0174 2 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_tpm_ch_tpm2_ch1: IOMUXC1_I2C1_SDA_TPM_CH_TPM2_CH1 { + pinmux = <0x443c0174 3 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_gpio_io_gpio1_io02: IOMUXC1_I2C2_SCL_GPIO_IO_GPIO1_IO02 { + pinmux = <0x443c0178 5 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_b_i3c1_pur_b: IOMUXC1_I2C2_SCL_I3C_PUR_B_I3C1_PUR_B { + pinmux = <0x443c0178 6 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_i3c1_pur: IOMUXC1_I2C2_SCL_I3C_PUR_I3C1_PUR { + pinmux = <0x443c0178 1 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl: IOMUXC1_I2C2_SCL_LPI2C_SCL_LPI2C2_SCL { + pinmux = <0x443c0178 0 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpuart_dcb_b_lpuart2_dcb_b: IOMUXC1_I2C2_SCL_LPUART_DCB_B_LPUART2_DCB_B { + pinmux = <0x443c0178 2 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_sai_rx_sync_sai1_rx_sync: IOMUXC1_I2C2_SCL_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x443c0178 4 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_tpm_ch_tpm2_ch2: IOMUXC1_I2C2_SCL_TPM_CH_TPM2_CH2 { + pinmux = <0x443c0178 3 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_gpio_io_gpio1_io03: IOMUXC1_I2C2_SDA_GPIO_IO_GPIO1_IO03 { + pinmux = <0x443c017c 5 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda: IOMUXC1_I2C2_SDA_LPI2C_SDA_LPI2C2_SDA { + pinmux = <0x443c017c 0 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpuart_rin_b_lpuart2_rin_b: IOMUXC1_I2C2_SDA_LPUART_RIN_B_LPUART2_RIN_B { + pinmux = <0x443c017c 2 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_sai_rx_bclk_sai1_rx_bclk: IOMUXC1_I2C2_SDA_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x443c017c 4 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_tpm_ch_tpm2_ch3: IOMUXC1_I2C2_SDA_TPM_CH_TPM2_CH3 { + pinmux = <0x443c017c 3 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_can_rx_can1_rx: IOMUXC1_PDM_BIT_STREAM0_CAN_RX_CAN1_RX { + pinmux = <0x443c0194 6 0x443c0360 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09: IOMUXC1_PDM_BIT_STREAM0_GPIO_IO_GPIO1_IO09 { + pinmux = <0x443c0194 5 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lpspi_pcs_lpspi1_pcs1: IOMUXC1_PDM_BIT_STREAM0_LPSPI_PCS_LPSPI1_PCS1 { + pinmux = <0x443c0194 2 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lptmr_alt_lptmr1_alt2: IOMUXC1_PDM_BIT_STREAM0_LPTMR_ALT_LPTMR1_ALT2 { + pinmux = <0x443c0194 4 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_mqs_right_mqs1_right: IOMUXC1_PDM_BIT_STREAM0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c0194 1 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_PDM_BIT_STREAM0_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0194 0 0x443c0438 2 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_tpm_extclk_tpm1_extclk: IOMUXC1_PDM_BIT_STREAM0_TPM_EXTCLK_TPM1_EXTCLK { + pinmux = <0x443c0194 3 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0198 6 0x443c0368 1 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10: IOMUXC1_PDM_BIT_STREAM1_GPIO_IO_GPIO1_IO10 { + pinmux = <0x443c0198 5 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lpspi_pcs_lpspi2_pcs1: IOMUXC1_PDM_BIT_STREAM1_LPSPI_PCS_LPSPI2_PCS1 { + pinmux = <0x443c0198 2 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lptmr_alt_lptmr1_alt3: IOMUXC1_PDM_BIT_STREAM1_LPTMR_ALT_LPTMR1_ALT3 { + pinmux = <0x443c0198 4 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_nmi_glue_nmi_nmi_glue_nmi: IOMUXC1_PDM_BIT_STREAM1_NMI_GLUE_NMI_NMI_GLUE_NMI { + pinmux = <0x443c0198 1 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_PDM_BIT_STREAM1_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0198 0 0x443c043c 2 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_tpm_extclk_tpm2_extclk: IOMUXC1_PDM_BIT_STREAM1_TPM_EXTCLK_TPM2_EXTCLK { + pinmux = <0x443c0198 3 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_can_tx_can1_tx: IOMUXC1_PDM_CLK_CAN_TX_CAN1_TX { + pinmux = <0x443c0190 6 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_gpio_io_gpio1_io08: IOMUXC1_PDM_CLK_GPIO_IO_GPIO1_IO08 { + pinmux = <0x443c0190 5 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_lptmr_alt_lptmr1_alt1: IOMUXC1_PDM_CLK_LPTMR_ALT_LPTMR1_ALT1 { + pinmux = <0x443c0190 4 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_mqs_left_mqs1_left: IOMUXC1_PDM_CLK_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c0190 1 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_pdm_clk_pdm_clk: IOMUXC1_PDM_CLK_PDM_CLK_PDM_CLK { + pinmux = <0x443c0190 0 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_gpio_io_gpio1_io14: IOMUXC1_SAI1_RXD0_GPIO_IO_GPIO1_IO14 { + pinmux = <0x443c01a8 5 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpspi_sout_lpspi1_sout: IOMUXC1_SAI1_RXD0_LPSPI_SOUT_LPSPI1_SOUT { + pinmux = <0x443c01a8 2 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpuart_dsr_b_lpuart2_dsr_b: IOMUXC1_SAI1_RXD0_LPUART_DSR_B_LPUART2_DSR_B { + pinmux = <0x443c01a8 3 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_mqs_right_mqs1_right: IOMUXC1_SAI1_RXD0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c01a8 4 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_mclk_sai1_mclk: IOMUXC1_SAI1_RXD0_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c01a8 1 0x443c0448 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_rx_data_sai1_rx_data00: IOMUXC1_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA00 { + pinmux = <0x443c01a8 0 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_can_rx_can1_rx: IOMUXC1_SAI1_TXC_CAN_RX_CAN1_RX { + pinmux = <0x443c01a0 4 0x443c0360 1 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_gpio_io_gpio1_io12: IOMUXC1_SAI1_TXC_GPIO_IO_GPIO1_IO12 { + pinmux = <0x443c01a0 5 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpspi_sin_lpspi1_sin: IOMUXC1_SAI1_TXC_LPSPI_SIN_LPSPI1_SIN { + pinmux = <0x443c01a0 2 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_cts_b_lpuart2_cts_b: IOMUXC1_SAI1_TXC_LPUART_CTS_B_LPUART2_CTS_B { + pinmux = <0x443c01a0 1 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_dsr_b_lpuart1_dsr_b: IOMUXC1_SAI1_TXC_LPUART_DSR_B_LPUART1_DSR_B { + pinmux = <0x443c01a0 3 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC1_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x443c01a0 0 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_can_tx_can1_tx: IOMUXC1_SAI1_TXD0_CAN_TX_CAN1_TX { + pinmux = <0x443c01a4 4 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_gpio_io_gpio1_io13: IOMUXC1_SAI1_TXD0_GPIO_IO_GPIO1_IO13 { + pinmux = <0x443c01a4 5 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpspi_sck_lpspi1_sck: IOMUXC1_SAI1_TXD0_LPSPI_SCK_LPSPI1_SCK { + pinmux = <0x443c01a4 2 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_dtr_b_lpuart1_dtr_b: IOMUXC1_SAI1_TXD0_LPUART_DTR_B_LPUART1_DTR_B { + pinmux = <0x443c01a4 3 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_rts_b_lpuart2_rts_b: IOMUXC1_SAI1_TXD0_LPUART_RTS_B_LPUART2_RTS_B { + pinmux = <0x443c01a4 1 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_sai_tx_data_sai1_tx_data00: IOMUXC1_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA00 { + pinmux = <0x443c01a4 0 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_gpio_io_gpio1_io11: IOMUXC1_SAI1_TXFS_GPIO_IO_GPIO1_IO11 { + pinmux = <0x443c019c 5 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpspi_pcs_lpspi1_pcs0: IOMUXC1_SAI1_TXFS_LPSPI_PCS_LPSPI1_PCS0 { + pinmux = <0x443c019c 2 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpuart_dtr_b_lpuart2_dtr_b: IOMUXC1_SAI1_TXFS_LPUART_DTR_B_LPUART2_DTR_B { + pinmux = <0x443c019c 3 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_mqs_left_mqs1_left: IOMUXC1_SAI1_TXFS_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c019c 4 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_data_sai1_tx_data01: IOMUXC1_SAI1_TXFS_SAI_TX_DATA_SAI1_TX_DATA01 { + pinmux = <0x443c019c 1 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC1_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x443c019c 0 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_flexio_flexio_flexio1_flexio08: IOMUXC1_SD1_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0108 4 0x443c038c 1 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_gpio_io_gpio3_io08: IOMUXC1_SD1_CLK_GPIO_IO_GPIO3_IO08 { + pinmux = <0x443c0108 5 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC1_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x443c0108 0 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_flexio_flexio_flexio1_flexio09: IOMUXC1_SD1_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c010c 4 0x443c0390 1 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_gpio_io_gpio3_io09: IOMUXC1_SD1_CMD_GPIO_IO_GPIO3_IO09 { + pinmux = <0x443c010c 5 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC1_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x443c010c 0 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_flexio_flexio_flexio1_flexio10: IOMUXC1_SD1_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0110 4 0x443c0394 1 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_gpio_io_gpio3_io10: IOMUXC1_SD1_DATA0_GPIO_IO_GPIO3_IO10 { + pinmux = <0x443c0110 5 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC1_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x443c0110 0 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_flexio_flexio_flexio1_flexio11: IOMUXC1_SD1_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c0114 4 0x443c0398 1 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_gpio_io_gpio3_io11: IOMUXC1_SD1_DATA1_GPIO_IO_GPIO3_IO11 { + pinmux = <0x443c0114 5 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC1_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x443c0114 0 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_flexio_flexio_flexio1_flexio12: IOMUXC1_SD1_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO12 { + pinmux = <0x443c0118 4 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_gpio_io_gpio3_io12: IOMUXC1_SD1_DATA2_GPIO_IO_GPIO3_IO12 { + pinmux = <0x443c0118 5 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC1_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x443c0118 0 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexio_flexio_flexio1_flexio13: IOMUXC1_SD1_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c011c 4 0x443c039c 1 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexspi_a_ss_b_flexspi1_a_ss1_b: IOMUXC1_SD1_DATA3_FLEXSPI_A_SS_B_FLEXSPI1_A_SS1_B { + pinmux = <0x443c011c 1 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_gpio_io_gpio3_io13: IOMUXC1_SD1_DATA3_GPIO_IO_GPIO3_IO13 { + pinmux = <0x443c011c 5 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC1_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x443c011c 0 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexio_flexio_flexio1_flexio14: IOMUXC1_SD1_DATA4_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0120 4 0x443c03a0 1 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexspi_a_data_flexspi1_a_data04: IOMUXC1_SD1_DATA4_FLEXSPI_A_DATA_FLEXSPI1_A_DATA04 { + pinmux = <0x443c0120 1 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_gpio_io_gpio3_io14: IOMUXC1_SD1_DATA4_GPIO_IO_GPIO3_IO14 { + pinmux = <0x443c0120 5 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC1_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x443c0120 0 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexio_flexio_flexio1_flexio15: IOMUXC1_SD1_DATA5_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c0124 4 0x443c03a4 1 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexspi_a_data_flexspi1_a_data05: IOMUXC1_SD1_DATA5_FLEXSPI_A_DATA_FLEXSPI1_A_DATA05 { + pinmux = <0x443c0124 1 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_gpio_io_gpio3_io15: IOMUXC1_SD1_DATA5_GPIO_IO_GPIO3_IO15 { + pinmux = <0x443c0124 5 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC1_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x443c0124 0 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_reset_b_usdhc1_reset_b: IOMUXC1_SD1_DATA5_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x443c0124 2 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexio_flexio_flexio1_flexio16: IOMUXC1_SD1_DATA6_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0128 4 0x443c03a8 1 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexspi_a_data_flexspi1_a_data06: IOMUXC1_SD1_DATA6_FLEXSPI_A_DATA_FLEXSPI1_A_DATA06 { + pinmux = <0x443c0128 1 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_gpio_io_gpio3_io16: IOMUXC1_SD1_DATA6_GPIO_IO_GPIO3_IO16 { + pinmux = <0x443c0128 5 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_cd_b_usdhc1_cd_b: IOMUXC1_SD1_DATA6_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x443c0128 2 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC1_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x443c0128 0 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexio_flexio_flexio1_flexio17: IOMUXC1_SD1_DATA7_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c012c 4 0x443c03ac 1 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexspi_a_data_flexspi1_a_data07: IOMUXC1_SD1_DATA7_FLEXSPI_A_DATA_FLEXSPI1_A_DATA07 { + pinmux = <0x443c012c 1 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_gpio_io_gpio3_io17: IOMUXC1_SD1_DATA7_GPIO_IO_GPIO3_IO17 { + pinmux = <0x443c012c 5 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC1_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x443c012c 0 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_wp_usdhc1_wp: IOMUXC1_SD1_DATA7_USDHC_WP_USDHC1_WP { + pinmux = <0x443c012c 2 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexio_flexio_flexio1_flexio18: IOMUXC1_SD1_STROBE_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0130 4 0x443c03b0 1 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexspi_a_dqs_flexspi1_a_dqs: IOMUXC1_SD1_STROBE_FLEXSPI_A_DQS_FLEXSPI1_A_DQS { + pinmux = <0x443c0130 1 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_gpio_io_gpio3_io18: IOMUXC1_SD1_STROBE_GPIO_IO_GPIO3_IO18 { + pinmux = <0x443c0130 5 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC1_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x443c0130 0 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC1_SD2_CD_B_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x443c0150 1 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_flexio_flexio_flexio1_flexio00: IOMUXC1_SD2_CD_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0150 4 0x443c036c 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_gpio_io_gpio3_io00: IOMUXC1_SD2_CD_B_GPIO_IO_GPIO3_IO00 { + pinmux = <0x443c0150 5 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_i3c_scl_i3c2_scl: IOMUXC1_SD2_CD_B_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0150 2 0x443c03cc 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC1_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x443c0150 0 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe0: IOMUXC1_SD2_CLK_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE0 { + pinmux = <0x443c0154 6 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC1_SD2_CLK_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x443c0154 1 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_flexio_flexio_flexio1_flexio01: IOMUXC1_SD2_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0154 4 0x443c0370 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_gpio_io_gpio3_io01: IOMUXC1_SD2_CLK_GPIO_IO_GPIO3_IO01 { + pinmux = <0x443c0154 5 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_i3c_sda_i3c2_sda: IOMUXC1_SD2_CLK_I3C_SDA_I3C2_SDA { + pinmux = <0x443c0154 2 0x443c03d0 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC1_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x443c0154 0 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe1: IOMUXC1_SD2_CMD_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE1 { + pinmux = <0x443c0158 6 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_enet1_1588_event0_in_enet1_1588_event0_in: IOMUXC1_SD2_CMD_ENET1_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x443c0158 1 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_flexio_flexio_flexio1_flexio02: IOMUXC1_SD2_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0158 4 0x443c0374 1 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_gpio_io_gpio3_io02: IOMUXC1_SD2_CMD_GPIO_IO_GPIO3_IO02 { + pinmux = <0x443c0158 5 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_b_i3c2_pur_b: IOMUXC1_SD2_CMD_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c0158 3 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_i3c2_pur: IOMUXC1_SD2_CMD_I3C_PUR_I3C2_PUR { + pinmux = <0x443c0158 2 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC1_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x443c0158 0 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_can_tx_can2_tx: IOMUXC1_SD2_DATA0_CAN_TX_CAN2_TX { + pinmux = <0x443c015c 2 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe2: IOMUXC1_SD2_DATA0_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE2 { + pinmux = <0x443c015c 6 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_enet1_1588_event0_out_enet1_1588_event0_out: IOMUXC1_SD2_DATA0_ENET1_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x443c015c 1 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_flexio_flexio_flexio1_flexio03: IOMUXC1_SD2_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c015c 4 0x443c0378 1 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_gpio_io_gpio3_io03: IOMUXC1_SD2_DATA0_GPIO_IO_GPIO3_IO03 { + pinmux = <0x443c015c 5 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC1_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x443c015c 0 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_can_rx_can2_rx: IOMUXC1_SD2_DATA1_CAN_RX_CAN2_RX { + pinmux = <0x443c0160 2 0x443c0364 3 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_enet1_1588_event1_in_enet1_1588_event1_in: IOMUXC1_SD2_DATA1_ENET1_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x443c0160 1 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_flexio_flexio_flexio1_flexio04: IOMUXC1_SD2_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0160 4 0x443c037c 1 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_gpio_io_gpio3_io04: IOMUXC1_SD2_DATA1_GPIO_IO_GPIO3_IO04 { + pinmux = <0x443c0160 5 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC1_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x443c0160 0 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_enet1_1588_event1_out_enet1_1588_event1_out: IOMUXC1_SD2_DATA2_ENET1_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x443c0164 1 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_flexio_flexio_flexio1_flexio05: IOMUXC1_SD2_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0164 4 0x443c0380 1 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_gpio_io_gpio3_io05: IOMUXC1_SD2_DATA2_GPIO_IO_GPIO3_IO05 { + pinmux = <0x443c0164 5 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_mqs_right_mqs2_right: IOMUXC1_SD2_DATA2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0164 2 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC1_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x443c0164 0 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_flexio_flexio_flexio1_flexio06: IOMUXC1_SD2_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0168 4 0x443c0384 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_gpio_io_gpio3_io06: IOMUXC1_SD2_DATA3_GPIO_IO_GPIO3_IO06 { + pinmux = <0x443c0168 5 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_lptmr_alt_lptmr2_alt1: IOMUXC1_SD2_DATA3_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c0168 1 0x443c0408 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_mqs_left_mqs2_left: IOMUXC1_SD2_DATA3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0168 2 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC1_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x443c0168 0 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_ccmsrcgpcmix_system_reset_ccmsrcgpcmix_system_reset: IOMUXC1_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET_CCMSRCGPCMIX_SYSTEM_RESET { + pinmux = <0x443c016c 6 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_flexio_flexio_flexio1_flexio07: IOMUXC1_SD2_RESET_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c016c 4 0x443c0388 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_gpio_io_gpio3_io07: IOMUXC1_SD2_RESET_B_GPIO_IO_GPIO3_IO07 { + pinmux = <0x443c016c 5 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_lptmr_alt_lptmr2_alt2: IOMUXC1_SD2_RESET_B_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c016c 1 0x443c040c 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC1_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x443c016c 0 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0134 6 0x443c0368 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_flexio_flexio_flexio1_flexio19: IOMUXC1_SD2_VSELECT_FLEXIO_FLEXIO_FLEXIO1_FLEXIO19 { + pinmux = <0x443c0134 4 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_gpio_io_gpio3_io19: IOMUXC1_SD2_VSELECT_GPIO_IO_GPIO3_IO19 { + pinmux = <0x443c0134 5 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_lptmr_alt_lptmr2_alt3: IOMUXC1_SD2_VSELECT_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c0134 2 0x443c0410 1 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect: IOMUXC1_SD2_VSELECT_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x443c0134 0 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_wp_usdhc2_wp: IOMUXC1_SD2_VSELECT_USDHC_WP_USDHC2_WP { + pinmux = <0x443c0134 1 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexio_flexio_flexio1_flexio20: IOMUXC1_SD3_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0138 4 0x443c03b4 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexspi_a_sclk_flexspi1_a_sclk: IOMUXC1_SD3_CLK_FLEXSPI_A_SCLK_FLEXSPI1_A_SCLK { + pinmux = <0x443c0138 1 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_gpio_io_gpio3_io20: IOMUXC1_SD3_CLK_GPIO_IO_GPIO3_IO20 { + pinmux = <0x443c0138 5 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_usdhc_clk_usdhc3_clk: IOMUXC1_SD3_CLK_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0138 0 0x443c0458 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexio_flexio_flexio1_flexio21: IOMUXC1_SD3_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO21 { + pinmux = <0x443c013c 4 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexspi_a_ss_b_flexspi1_a_ss0_b: IOMUXC1_SD3_CMD_FLEXSPI_A_SS_B_FLEXSPI1_A_SS0_B { + pinmux = <0x443c013c 1 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_gpio_io_gpio3_io21: IOMUXC1_SD3_CMD_GPIO_IO_GPIO3_IO21 { + pinmux = <0x443c013c 5 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_usdhc_cmd_usdhc3_cmd: IOMUXC1_SD3_CMD_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c013c 0 0x443c045c 1 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexio_flexio_flexio1_flexio22: IOMUXC1_SD3_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0140 4 0x443c03b8 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexspi_a_data_flexspi1_a_data00: IOMUXC1_SD3_DATA0_FLEXSPI_A_DATA_FLEXSPI1_A_DATA00 { + pinmux = <0x443c0140 1 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_gpio_io_gpio3_io22: IOMUXC1_SD3_DATA0_GPIO_IO_GPIO3_IO22 { + pinmux = <0x443c0140 5 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_usdhc_data_usdhc3_data0: IOMUXC1_SD3_DATA0_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0140 0 0x443c0460 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexio_flexio_flexio1_flexio23: IOMUXC1_SD3_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c0144 4 0x443c03bc 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexspi_a_data_flexspi1_a_data01: IOMUXC1_SD3_DATA1_FLEXSPI_A_DATA_FLEXSPI1_A_DATA01 { + pinmux = <0x443c0144 1 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_gpio_io_gpio3_io23: IOMUXC1_SD3_DATA1_GPIO_IO_GPIO3_IO23 { + pinmux = <0x443c0144 5 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_usdhc_data_usdhc3_data1: IOMUXC1_SD3_DATA1_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0144 0 0x443c0464 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexio_flexio_flexio1_flexio24: IOMUXC1_SD3_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0148 4 0x443c03c0 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexspi_a_data_flexspi1_a_data02: IOMUXC1_SD3_DATA2_FLEXSPI_A_DATA_FLEXSPI1_A_DATA02 { + pinmux = <0x443c0148 1 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_gpio_io_gpio3_io24: IOMUXC1_SD3_DATA2_GPIO_IO_GPIO3_IO24 { + pinmux = <0x443c0148 5 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_usdhc_data_usdhc3_data2: IOMUXC1_SD3_DATA2_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0148 0 0x443c0468 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexio_flexio_flexio1_flexio25: IOMUXC1_SD3_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c014c 4 0x443c03c4 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexspi_a_data_flexspi1_a_data03: IOMUXC1_SD3_DATA3_FLEXSPI_A_DATA_FLEXSPI1_A_DATA03 { + pinmux = <0x443c014c 1 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_gpio_io_gpio3_io25: IOMUXC1_SD3_DATA3_GPIO_IO_GPIO3_IO25 { + pinmux = <0x443c014c 5 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_usdhc_data_usdhc3_data3: IOMUXC1_SD3_DATA3_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c014c 0 0x443c046c 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_gpio_io_gpio1_io04: IOMUXC1_UART1_RXD_GPIO_IO_GPIO1_IO04 { + pinmux = <0x443c0180 5 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpspi_sin_lpspi2_sin: IOMUXC1_UART1_RXD_LPSPI_SIN_LPSPI2_SIN { + pinmux = <0x443c0180 2 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx: IOMUXC1_UART1_RXD_LPUART_RX_LPUART1_RX { + pinmux = <0x443c0180 0 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_s400_uart_rx_s400_uart_rx: IOMUXC1_UART1_RXD_S400_UART_RX_S400_UART_RX { + pinmux = <0x443c0180 1 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_tpm_ch_tpm1_ch0: IOMUXC1_UART1_RXD_TPM_CH_TPM1_CH0 { + pinmux = <0x443c0180 3 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_gpio_io_gpio1_io05: IOMUXC1_UART1_TXD_GPIO_IO_GPIO1_IO05 { + pinmux = <0x443c0184 5 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpspi_pcs_lpspi2_pcs0: IOMUXC1_UART1_TXD_LPSPI_PCS_LPSPI2_PCS0 { + pinmux = <0x443c0184 2 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx: IOMUXC1_UART1_TXD_LPUART_TX_LPUART1_TX { + pinmux = <0x443c0184 0 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_s400_uart_tx_s400_uart_tx: IOMUXC1_UART1_TXD_S400_UART_TX_S400_UART_TX { + pinmux = <0x443c0184 1 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_tpm_ch_tpm1_ch1: IOMUXC1_UART1_TXD_TPM_CH_TPM1_CH1 { + pinmux = <0x443c0184 3 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_gpio_io_gpio1_io06: IOMUXC1_UART2_RXD_GPIO_IO_GPIO1_IO06 { + pinmux = <0x443c0188 5 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpspi_sout_lpspi2_sout: IOMUXC1_UART2_RXD_LPSPI_SOUT_LPSPI2_SOUT { + pinmux = <0x443c0188 2 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_cts_b_lpuart1_cts_b: IOMUXC1_UART2_RXD_LPUART_CTS_B_LPUART1_CTS_B { + pinmux = <0x443c0188 1 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx: IOMUXC1_UART2_RXD_LPUART_RX_LPUART2_RX { + pinmux = <0x443c0188 0 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_sai_mclk_sai1_mclk: IOMUXC1_UART2_RXD_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c0188 4 0x443c0448 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_tpm_ch_tpm1_ch2: IOMUXC1_UART2_RXD_TPM_CH_TPM1_CH2 { + pinmux = <0x443c0188 3 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_gpio_io_gpio1_io07: IOMUXC1_UART2_TXD_GPIO_IO_GPIO1_IO07 { + pinmux = <0x443c018c 5 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpspi_sck_lpspi2_sck: IOMUXC1_UART2_TXD_LPSPI_SCK_LPSPI2_SCK { + pinmux = <0x443c018c 2 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_rts_b_lpuart1_rts_b: IOMUXC1_UART2_TXD_LPUART_RTS_B_LPUART1_RTS_B { + pinmux = <0x443c018c 1 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx: IOMUXC1_UART2_TXD_LPUART_TX_LPUART2_TX { + pinmux = <0x443c018c 0 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_tpm_ch_tpm1_ch3: IOMUXC1_UART2_TXD_TPM_CH_TPM1_CH3 { + pinmux = <0x443c018c 3 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_gpio_io_gpio1_io15: IOMUXC1_WDOG_ANY_GPIO_IO_GPIO1_IO15 { + pinmux = <0x443c01ac 5 0x0 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_wdog_wdog_any_wdog1_wdog_any: IOMUXC1_WDOG_ANY_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x443c01ac 0 0x0 0 0x443c035c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx9351cvvxm-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx9351cvvxm-pinctrl.dtsi new file mode 100644 index 000000000..3b2dcb886 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx9351cvvxm-pinctrl.dtsi @@ -0,0 +1,1831 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX9351CVVXM + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc1_ccm_clko1_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko1: IOMUXC1_CCM_CLKO1_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO1 { + pinmux = <0x443c0088 0 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_flexio_flexio_flexio1_flexio26: IOMUXC1_CCM_CLKO1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO26 { + pinmux = <0x443c0088 4 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_gpio_io_gpio3_io26: IOMUXC1_CCM_CLKO1_GPIO_IO_GPIO3_IO26 { + pinmux = <0x443c0088 5 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko2: IOMUXC1_CCM_CLKO2_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO2 { + pinmux = <0x443c008c 0 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_flexio_flexio_flexio1_flexio27: IOMUXC1_CCM_CLKO2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c008c 4 0x443c03c8 1 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_gpio_io_gpio3_io27: IOMUXC1_CCM_CLKO2_GPIO_IO_GPIO3_IO27 { + pinmux = <0x443c008c 5 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko3: IOMUXC1_CCM_CLKO3_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO3 { + pinmux = <0x443c0090 0 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_flexio_flexio_flexio2_flexio28: IOMUXC1_CCM_CLKO3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO28 { + pinmux = <0x443c0090 4 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_gpio_io_gpio4_io28: IOMUXC1_CCM_CLKO3_GPIO_IO_GPIO4_IO28 { + pinmux = <0x443c0090 5 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko4: IOMUXC1_CCM_CLKO4_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO4 { + pinmux = <0x443c0094 0 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_flexio_flexio_flexio2_flexio29: IOMUXC1_CCM_CLKO4_FLEXIO_FLEXIO_FLEXIO2_FLEXIO29 { + pinmux = <0x443c0094 4 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_gpio_io_gpio4_io29: IOMUXC1_CCM_CLKO4_GPIO_IO_GPIO4_IO29 { + pinmux = <0x443c0094 5 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_flexio_flexio_flexio1_flexio30: IOMUXC1_DAP_TCLK_SWCLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO30 { + pinmux = <0x443c0008 4 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30: IOMUXC1_DAP_TCLK_SWCLK_GPIO_IO_GPIO3_IO30 { + pinmux = <0x443c0008 5 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_jtag_mux_tck_jtag_mux_tck: IOMUXC1_DAP_TCLK_SWCLK_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0008 0 0x443c03d4 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_DAP_TCLK_SWCLK_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0008 6 0x443c042c 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_can_tx_can2_tx: IOMUXC1_DAP_TDI_CAN_TX_CAN2_TX { + pinmux = <0x443c0000 3 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_flexio_flexio_flexio2_flexio30: IOMUXC1_DAP_TDI_FLEXIO_FLEXIO_FLEXIO2_FLEXIO30 { + pinmux = <0x443c0000 4 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_gpio_io_gpio3_io28: IOMUXC1_DAP_TDI_GPIO_IO_GPIO3_IO28 { + pinmux = <0x443c0000 5 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_DAP_TDI_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0000 0 0x443c03d8 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_lpuart_rx_lpuart5_rx: IOMUXC1_DAP_TDI_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0000 6 0x443c0430 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_mqs_left_mqs2_left: IOMUXC1_DAP_TDI_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0000 1 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_can_rx_can2_rx: IOMUXC1_DAP_TDO_TRACESWO_CAN_RX_CAN2_RX { + pinmux = <0x443c000c 3 0x443c0364 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_flexio_flexio_flexio1_flexio31: IOMUXC1_DAP_TDO_TRACESWO_FLEXIO_FLEXIO_FLEXIO1_FLEXIO31 { + pinmux = <0x443c000c 4 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31: IOMUXC1_DAP_TDO_TRACESWO_GPIO_IO_GPIO3_IO31 { + pinmux = <0x443c000c 5 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_DAP_TDO_TRACESWO_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c000c 0 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_lpuart_tx_lpuart5_tx: IOMUXC1_DAP_TDO_TRACESWO_LPUART_TX_LPUART5_TX { + pinmux = <0x443c000c 6 0x443c0434 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_mqs_right_mqs2_right: IOMUXC1_DAP_TDO_TRACESWO_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c000c 1 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_flexio_flexio_flexio2_flexio31: IOMUXC1_DAP_TMS_SWDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO31 { + pinmux = <0x443c0004 4 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29: IOMUXC1_DAP_TMS_SWDIO_GPIO_IO_GPIO3_IO29 { + pinmux = <0x443c0004 5 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_jtag_mux_tms_jtag_mux_tms: IOMUXC1_DAP_TMS_SWDIO_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c0004 0 0x443c03dc 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_DAP_TMS_SWDIO_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c0004 6 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC1_ENET1_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x443c0098 0 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_flexio_flexio_flexio2_flexio00: IOMUXC1_ENET1_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO00 { + pinmux = <0x443c0098 4 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_gpio_io_gpio4_io00: IOMUXC1_ENET1_MDC_GPIO_IO_GPIO4_IO00 { + pinmux = <0x443c0098 5 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_hsiomix_otg_id_hsiomix_otg_id1: IOMUXC1_ENET1_MDC_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID1 { + pinmux = <0x443c0098 3 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_i3c_scl_i3c2_scl: IOMUXC1_ENET1_MDC_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0098 2 0x443c03cc 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_lpuart_dcb_b_lpuart3_dcb_b: IOMUXC1_ENET1_MDC_LPUART_DCB_B_LPUART3_DCB_B { + pinmux = <0x443c0098 1 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC1_ENET1_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x443c009c 0 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_flexio_flexio_flexio2_flexio01: IOMUXC1_ENET1_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO01 { + pinmux = <0x443c009c 4 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_gpio_io_gpio4_io01: IOMUXC1_ENET1_MDIO_GPIO_IO_GPIO4_IO01 { + pinmux = <0x443c009c 5 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_hsiomix_otg_pwr_hsiomix_otg_pwr1: IOMUXC1_ENET1_MDIO_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR1 { + pinmux = <0x443c009c 3 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_i3c_sda_i3c2_sda: IOMUXC1_ENET1_MDIO_I3C_SDA_I3C2_SDA { + pinmux = <0x443c009c 2 0x443c03d0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_lpuart_rin_b_lpuart3_rin_b: IOMUXC1_ENET1_MDIO_LPUART_RIN_B_LPUART3_RIN_B { + pinmux = <0x443c009c 1 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC1_ENET1_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x443c00c0 0 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_flexio_flexio_flexio2_flexio10: IOMUXC1_ENET1_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO10 { + pinmux = <0x443c00c0 4 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_gpio_io_gpio4_io10: IOMUXC1_ENET1_RD0_GPIO_IO_GPIO4_IO10 { + pinmux = <0x443c00c0 5 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_lpuart_rx_lpuart3_rx: IOMUXC1_ENET1_RD0_LPUART_RX_LPUART3_RX { + pinmux = <0x443c00c0 1 0x443c0418 1 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC1_ENET1_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x443c00c4 0 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_flexio_flexio_flexio2_flexio11: IOMUXC1_ENET1_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO11 { + pinmux = <0x443c00c4 4 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_gpio_io_gpio4_io11: IOMUXC1_ENET1_RD1_GPIO_IO_GPIO4_IO11 { + pinmux = <0x443c00c4 5 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lptmr_alt_lptmr2_alt1: IOMUXC1_ENET1_RD1_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c00c4 3 0x443c0408 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_ENET1_RD1_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c00c4 1 0x443c0414 1 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC1_ENET1_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x443c00c8 0 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_flexio_flexio_flexio2_flexio12: IOMUXC1_ENET1_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO12 { + pinmux = <0x443c00c8 4 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_gpio_io_gpio4_io12: IOMUXC1_ENET1_RD2_GPIO_IO_GPIO4_IO12 { + pinmux = <0x443c00c8 5 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_lptmr_alt_lptmr2_alt2: IOMUXC1_ENET1_RD2_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c00c8 3 0x443c040c 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC1_ENET1_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x443c00cc 0 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_flexio_flexio_flexio2_flexio13: IOMUXC1_ENET1_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO13 { + pinmux = <0x443c00cc 4 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_gpio_io_gpio4_io13: IOMUXC1_ENET1_RD3_GPIO_IO_GPIO4_IO13 { + pinmux = <0x443c00cc 5 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_lptmr_alt_lptmr2_alt3: IOMUXC1_ENET1_RD3_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c00cc 3 0x443c0410 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_ccm_enet_qos_clock_generate_rx_clk_ccm_enet_qos_clock_generate_rx_clk: IOMUXC1_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK { + pinmux = <0x443c00bc 0 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC1_ENET1_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x443c00bc 1 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_flexio_flexio_flexio2_flexio09: IOMUXC1_ENET1_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO09 { + pinmux = <0x443c00bc 4 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_gpio_io_gpio4_io09: IOMUXC1_ENET1_RXC_GPIO_IO_GPIO4_IO09 { + pinmux = <0x443c00bc 5 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC1_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x443c00b8 0 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_flexio_flexio_flexio2_flexio08: IOMUXC1_ENET1_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO08 { + pinmux = <0x443c00b8 4 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08: IOMUXC1_ENET1_RX_CTL_GPIO_IO_GPIO4_IO08 { + pinmux = <0x443c00b8 5 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_hsiomix_otg_pwr_hsiomix_otg_pwr2: IOMUXC1_ENET1_RX_CTL_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR2 { + pinmux = <0x443c00b8 3 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_lpuart_dsr_b_lpuart3_dsr_b: IOMUXC1_ENET1_RX_CTL_LPUART_DSR_B_LPUART3_DSR_B { + pinmux = <0x443c00b8 1 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC1_ENET1_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x443c00ac 0 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_flexio_flexio_flexio2_flexio05: IOMUXC1_ENET1_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO05 { + pinmux = <0x443c00ac 4 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_gpio_io_gpio4_io05: IOMUXC1_ENET1_TD0_GPIO_IO_GPIO4_IO05 { + pinmux = <0x443c00ac 5 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_lpuart_tx_lpuart3_tx: IOMUXC1_ENET1_TD0_LPUART_TX_LPUART3_TX { + pinmux = <0x443c00ac 1 0x443c041c 1 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC1_ENET1_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x443c00a8 0 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_flexio_flexio_flexio2_flexio04: IOMUXC1_ENET1_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO04 { + pinmux = <0x443c00a8 4 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_gpio_io_gpio4_io04: IOMUXC1_ENET1_TD1_GPIO_IO_GPIO4_IO04 { + pinmux = <0x443c00a8 5 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_hsiomix_otg_oc_hsiomix_otg_oc1: IOMUXC1_ENET1_TD1_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC1 { + pinmux = <0x443c00a8 3 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_b_i3c2_pur_b: IOMUXC1_ENET1_TD1_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c00a8 6 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_i3c2_pur: IOMUXC1_ENET1_TD1_I3C_PUR_I3C2_PUR { + pinmux = <0x443c00a8 2 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_ENET1_TD1_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c00a8 1 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_can_rx_can2_rx: IOMUXC1_ENET1_TD2_CAN_RX_CAN2_RX { + pinmux = <0x443c00a4 2 0x443c0364 2 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_ccm_enet_qos_clock_generate_ref_clk_ccm_enet_qos_clock_generate_ref_clk: IOMUXC1_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK { + pinmux = <0x443c00a4 1 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC1_ENET1_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x443c00a4 0 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_flexio_flexio_flexio2_flexio03: IOMUXC1_ENET1_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO03 { + pinmux = <0x443c00a4 4 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_gpio_io_gpio4_io03: IOMUXC1_ENET1_TD2_GPIO_IO_GPIO4_IO03 { + pinmux = <0x443c00a4 5 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_hsiomix_otg_oc_hsiomix_otg_oc2: IOMUXC1_ENET1_TD2_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC2 { + pinmux = <0x443c00a4 3 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_can_tx_can2_tx: IOMUXC1_ENET1_TD3_CAN_TX_CAN2_TX { + pinmux = <0x443c00a0 2 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC1_ENET1_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x443c00a0 0 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_flexio_flexio_flexio2_flexio02: IOMUXC1_ENET1_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO02 { + pinmux = <0x443c00a0 4 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_gpio_io_gpio4_io02: IOMUXC1_ENET1_TD3_GPIO_IO_GPIO4_IO02 { + pinmux = <0x443c00a0 5 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_hsiomix_otg_id_hsiomix_otg_id2: IOMUXC1_ENET1_TD3_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID2 { + pinmux = <0x443c00a0 3 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_ccm_enet_qos_clock_generate_tx_clk_ccm_enet_qos_clock_generate_tx_clk: IOMUXC1_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK { + pinmux = <0x443c00b4 0 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC1_ENET1_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x443c00b4 1 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_flexio_flexio_flexio2_flexio07: IOMUXC1_ENET1_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO07 { + pinmux = <0x443c00b4 4 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_gpio_io_gpio4_io07: IOMUXC1_ENET1_TXC_GPIO_IO_GPIO4_IO07 { + pinmux = <0x443c00b4 5 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC1_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x443c00b0 0 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_flexio_flexio_flexio2_flexio06: IOMUXC1_ENET1_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO06 { + pinmux = <0x443c00b0 4 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06: IOMUXC1_ENET1_TX_CTL_GPIO_IO_GPIO4_IO06 { + pinmux = <0x443c00b0 5 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_lpuart_dtr_b_lpuart3_dtr_b: IOMUXC1_ENET1_TX_CTL_LPUART_DTR_B_LPUART3_DTR_B { + pinmux = <0x443c00b0 1 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_enet_mdc_enet1_mdc: IOMUXC1_ENET2_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x443c00d0 0 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_flexio_flexio_flexio2_flexio14: IOMUXC1_ENET2_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO14 { + pinmux = <0x443c00d0 4 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_gpio_io_gpio4_io14: IOMUXC1_ENET2_MDC_GPIO_IO_GPIO4_IO14 { + pinmux = <0x443c00d0 5 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_lpuart_dcb_b_lpuart4_dcb_b: IOMUXC1_ENET2_MDC_LPUART_DCB_B_LPUART4_DCB_B { + pinmux = <0x443c00d0 1 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_sai_rx_sync_sai2_rx_sync: IOMUXC1_ENET2_MDC_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x443c00d0 2 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_enet_mdio_enet1_mdio: IOMUXC1_ENET2_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x443c00d4 0 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_flexio_flexio_flexio2_flexio15: IOMUXC1_ENET2_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO15 { + pinmux = <0x443c00d4 4 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_gpio_io_gpio4_io15: IOMUXC1_ENET2_MDIO_GPIO_IO_GPIO4_IO15 { + pinmux = <0x443c00d4 5 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_lpuart_rin_b_lpuart4_rin_b: IOMUXC1_ENET2_MDIO_LPUART_RIN_B_LPUART4_RIN_B { + pinmux = <0x443c00d4 1 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_sai_rx_bclk_sai2_rx_bclk: IOMUXC1_ENET2_MDIO_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x443c00d4 2 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC1_ENET2_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x443c00f8 0 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_flexio_flexio_flexio2_flexio24: IOMUXC1_ENET2_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO24 { + pinmux = <0x443c00f8 4 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_gpio_io_gpio4_io24: IOMUXC1_ENET2_RD0_GPIO_IO_GPIO4_IO24 { + pinmux = <0x443c00f8 5 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_lpuart_rx_lpuart4_rx: IOMUXC1_ENET2_RD0_LPUART_RX_LPUART4_RX { + pinmux = <0x443c00f8 1 0x443c0424 1 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_sai_tx_data_sai2_tx_data02: IOMUXC1_ENET2_RD0_SAI_TX_DATA_SAI2_TX_DATA02 { + pinmux = <0x443c00f8 2 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC1_ENET2_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x443c00fc 0 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_flexio_flexio_flexio2_flexio25: IOMUXC1_ENET2_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO25 { + pinmux = <0x443c00fc 4 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_gpio_io_gpio4_io25: IOMUXC1_ENET2_RD1_GPIO_IO_GPIO4_IO25 { + pinmux = <0x443c00fc 5 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_sai_tx_data_sai2_tx_data03: IOMUXC1_ENET2_RD1_SAI_TX_DATA_SAI2_TX_DATA03 { + pinmux = <0x443c00fc 2 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_spdif_in_spdif_in: IOMUXC1_ENET2_RD1_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c00fc 1 0x443c0454 1 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC1_ENET2_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x443c0100 0 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_flexio_flexio_flexio2_flexio26: IOMUXC1_ENET2_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO26 { + pinmux = <0x443c0100 4 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_gpio_io_gpio4_io26: IOMUXC1_ENET2_RD2_GPIO_IO_GPIO4_IO26 { + pinmux = <0x443c0100 5 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_ENET2_RD2_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0100 1 0x443c0420 1 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_mqs_right_mqs2_right: IOMUXC1_ENET2_RD2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0100 3 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_sai_mclk_sai2_mclk: IOMUXC1_ENET2_RD2_SAI_MCLK_SAI2_MCLK { + pinmux = <0x443c0100 2 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC1_ENET2_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x443c0104 0 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_flexio_flexio_flexio2_flexio27: IOMUXC1_ENET2_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO27 { + pinmux = <0x443c0104 4 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_gpio_io_gpio4_io27: IOMUXC1_ENET2_RD3_GPIO_IO_GPIO4_IO27 { + pinmux = <0x443c0104 5 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_mqs_left_mqs2_left: IOMUXC1_ENET2_RD3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0104 3 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_in_spdif_in: IOMUXC1_ENET2_RD3_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0104 2 0x443c0454 2 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_out_spdif_out: IOMUXC1_ENET2_RD3_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c0104 1 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC1_ENET2_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x443c00f4 0 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rx_er_enet1_rx_er: IOMUXC1_ENET2_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x443c00f4 1 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_flexio_flexio_flexio2_flexio23: IOMUXC1_ENET2_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO23 { + pinmux = <0x443c00f4 4 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_gpio_io_gpio4_io23: IOMUXC1_ENET2_RXC_GPIO_IO_GPIO4_IO23 { + pinmux = <0x443c00f4 5 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_sai_tx_data_sai2_tx_data01: IOMUXC1_ENET2_RXC_SAI_TX_DATA_SAI2_TX_DATA01 { + pinmux = <0x443c00f4 2 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC1_ENET2_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x443c00f0 0 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_flexio_flexio_flexio2_flexio22: IOMUXC1_ENET2_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO22 { + pinmux = <0x443c00f0 4 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22: IOMUXC1_ENET2_RX_CTL_GPIO_IO_GPIO4_IO22 { + pinmux = <0x443c00f0 5 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_lpuart_dsr_b_lpuart4_dsr_b: IOMUXC1_ENET2_RX_CTL_LPUART_DSR_B_LPUART4_DSR_B { + pinmux = <0x443c00f0 1 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_sai_tx_data_sai2_tx_data00: IOMUXC1_ENET2_RX_CTL_SAI_TX_DATA_SAI2_TX_DATA00 { + pinmux = <0x443c00f0 2 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC1_ENET2_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x443c00e4 0 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_flexio_flexio_flexio2_flexio19: IOMUXC1_ENET2_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO19 { + pinmux = <0x443c00e4 4 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_gpio_io_gpio4_io19: IOMUXC1_ENET2_TD0_GPIO_IO_GPIO4_IO19 { + pinmux = <0x443c00e4 5 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_lpuart_tx_lpuart4_tx: IOMUXC1_ENET2_TD0_LPUART_TX_LPUART4_TX { + pinmux = <0x443c00e4 1 0x443c0428 1 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_sai_rx_data_sai2_rx_data03: IOMUXC1_ENET2_TD0_SAI_RX_DATA_SAI2_RX_DATA03 { + pinmux = <0x443c00e4 2 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC1_ENET2_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x443c00e0 0 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_flexio_flexio_flexio2_flexio18: IOMUXC1_ENET2_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO18 { + pinmux = <0x443c00e0 4 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_gpio_io_gpio4_io18: IOMUXC1_ENET2_TD1_GPIO_IO_GPIO4_IO18 { + pinmux = <0x443c00e0 5 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_ENET2_TD1_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c00e0 1 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_sai_rx_data_sai2_rx_data02: IOMUXC1_ENET2_TD1_SAI_RX_DATA_SAI2_RX_DATA02 { + pinmux = <0x443c00e0 2 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC1_ENET2_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x443c00dc 0 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_tx_clk_enet1_tx_clk: IOMUXC1_ENET2_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x443c00dc 1 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_flexio_flexio_flexio2_flexio17: IOMUXC1_ENET2_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO17 { + pinmux = <0x443c00dc 4 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_gpio_io_gpio4_io17: IOMUXC1_ENET2_TD2_GPIO_IO_GPIO4_IO17 { + pinmux = <0x443c00dc 5 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_sai_rx_data_sai2_rx_data01: IOMUXC1_ENET2_TD2_SAI_RX_DATA_SAI2_RX_DATA01 { + pinmux = <0x443c00dc 2 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC1_ENET2_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x443c00d8 0 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_flexio_flexio_flexio2_flexio16: IOMUXC1_ENET2_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO16 { + pinmux = <0x443c00d8 4 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_gpio_io_gpio4_io16: IOMUXC1_ENET2_TD3_GPIO_IO_GPIO4_IO16 { + pinmux = <0x443c00d8 5 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_sai_rx_data_sai2_rx_data00: IOMUXC1_ENET2_TD3_SAI_RX_DATA_SAI2_RX_DATA00 { + pinmux = <0x443c00d8 2 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC1_ENET2_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x443c00ec 0 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_tx_er_enet1_tx_er: IOMUXC1_ENET2_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x443c00ec 1 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_flexio_flexio_flexio2_flexio21: IOMUXC1_ENET2_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO21 { + pinmux = <0x443c00ec 4 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_gpio_io_gpio4_io21: IOMUXC1_ENET2_TXC_GPIO_IO_GPIO4_IO21 { + pinmux = <0x443c00ec 5 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC1_ENET2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x443c00ec 2 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC1_ENET2_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x443c00e8 0 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_flexio_flexio_flexio2_flexio20: IOMUXC1_ENET2_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO20 { + pinmux = <0x443c00e8 4 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20: IOMUXC1_ENET2_TX_CTL_GPIO_IO_GPIO4_IO20 { + pinmux = <0x443c00e8 5 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_lpuart_dtr_b_lpuart4_dtr_b: IOMUXC1_ENET2_TX_CTL_LPUART_DTR_B_LPUART4_DTR_B { + pinmux = <0x443c00e8 1 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_sai_tx_sync_sai2_tx_sync: IOMUXC1_ENET2_TX_CTL_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x443c00e8 2 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_flexio_flexio_flexio1_flexio00: IOMUXC1_GPIO_IO00_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0010 7 0x443c036c 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_gpio_io_gpio2_io00: IOMUXC1_GPIO_IO00_GPIO_IO_GPIO2_IO00 { + pinmux = <0x443c0010 0 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0010 1 0x443c03e4 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0010 6 0x443c03ec 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpspi_pcs_lpspi6_pcs0: IOMUXC1_GPIO_IO00_LPSPI_PCS_LPSPI6_PCS0 { + pinmux = <0x443c0010 4 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpuart_tx_lpuart5_tx: IOMUXC1_GPIO_IO00_LPUART_TX_LPUART5_TX { + pinmux = <0x443c0010 5 0x443c0434 1 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_cam_clk_mediamix_cam_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_CAM_CLK_MEDIAMIX_CAM_CLK { + pinmux = <0x443c0010 2 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_disp_clk_mediamix_disp_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_DISP_CLK_MEDIAMIX_DISP_CLK { + pinmux = <0x443c0010 3 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_flexio_flexio_flexio1_flexio01: IOMUXC1_GPIO_IO01_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0014 7 0x443c0370 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_gpio_io_gpio2_io01: IOMUXC1_GPIO_IO01_GPIO_IO_GPIO2_IO01 { + pinmux = <0x443c0014 0 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0014 1 0x443c03e0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c0014 6 0x443c03e8 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpspi_sin_lpspi6_sin: IOMUXC1_GPIO_IO01_LPSPI_SIN_LPSPI6_SIN { + pinmux = <0x443c0014 4 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpuart_rx_lpuart5_rx: IOMUXC1_GPIO_IO01_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0014 5 0x443c0430 1 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_cam_data_mediamix_cam_data00: IOMUXC1_GPIO_IO01_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA00 { + pinmux = <0x443c0014 2 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_disp_de_mediamix_disp_de: IOMUXC1_GPIO_IO01_MEDIAMIX_DISP_DE_MEDIAMIX_DISP_DE { + pinmux = <0x443c0014 3 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_flexio_flexio_flexio1_flexio02: IOMUXC1_GPIO_IO02_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0018 7 0x443c0374 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_gpio_io_gpio2_io02: IOMUXC1_GPIO_IO02_GPIO_IO_GPIO2_IO02 { + pinmux = <0x443c0018 0 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C4_SDA { + pinmux = <0x443c0018 1 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0018 6 0x443c03f4 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpspi_sout_lpspi6_sout: IOMUXC1_GPIO_IO02_LPSPI_SOUT_LPSPI6_SOUT { + pinmux = <0x443c0018 4 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_GPIO_IO02_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0018 5 0x443c042c 1 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_cam_vsync_mediamix_cam_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_CAM_VSYNC_MEDIAMIX_CAM_VSYNC { + pinmux = <0x443c0018 2 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_disp_vsync_mediamix_disp_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_DISP_VSYNC_MEDIAMIX_DISP_VSYNC { + pinmux = <0x443c0018 3 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_flexio_flexio_flexio1_flexio03: IOMUXC1_GPIO_IO03_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c001c 7 0x443c0378 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_gpio_io_gpio2_io03: IOMUXC1_GPIO_IO03_GPIO_IO_GPIO2_IO03 { + pinmux = <0x443c001c 0 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C4_SCL { + pinmux = <0x443c001c 1 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c001c 6 0x443c03f0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpspi_sck_lpspi6_sck: IOMUXC1_GPIO_IO03_LPSPI_SCK_LPSPI6_SCK { + pinmux = <0x443c001c 4 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_GPIO_IO03_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c001c 5 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_cam_hsync_mediamix_cam_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_CAM_HSYNC_MEDIAMIX_CAM_HSYNC { + pinmux = <0x443c001c 2 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_disp_hsync_mediamix_disp_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_DISP_HSYNC_MEDIAMIX_DISP_HSYNC { + pinmux = <0x443c001c 3 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_flexio_flexio_flexio1_flexio04: IOMUXC1_GPIO_IO04_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0020 7 0x443c037c 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_gpio_io_gpio2_io04: IOMUXC1_GPIO_IO04_GPIO_IO_GPIO2_IO04 { + pinmux = <0x443c0020 0 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO04_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0020 6 0x443c03f4 1 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpspi_pcs_lpspi7_pcs0: IOMUXC1_GPIO_IO04_LPSPI_PCS_LPSPI7_PCS0 { + pinmux = <0x443c0020 4 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpuart_tx_lpuart6_tx: IOMUXC1_GPIO_IO04_LPUART_TX_LPUART6_TX { + pinmux = <0x443c0020 5 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_mediamix_disp_data_mediamix_disp_data00: IOMUXC1_GPIO_IO04_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA00 { + pinmux = <0x443c0020 3 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO04_PDM_CLK_PDM_CLK { + pinmux = <0x443c0020 2 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_tpm_ch_tpm3_ch0: IOMUXC1_GPIO_IO04_TPM_CH_TPM3_CH0 { + pinmux = <0x443c0020 1 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_flexio_flexio_flexio1_flexio05: IOMUXC1_GPIO_IO05_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0024 7 0x443c0380 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_gpio_io_gpio2_io05: IOMUXC1_GPIO_IO05_GPIO_IO_GPIO2_IO05 { + pinmux = <0x443c0024 0 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO05_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c0024 6 0x443c03f0 1 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpspi_sin_lpspi7_sin: IOMUXC1_GPIO_IO05_LPSPI_SIN_LPSPI7_SIN { + pinmux = <0x443c0024 4 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpuart_rx_lpuart6_rx: IOMUXC1_GPIO_IO05_LPUART_RX_LPUART6_RX { + pinmux = <0x443c0024 5 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_mediamix_disp_data_mediamix_disp_data01: IOMUXC1_GPIO_IO05_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA01 { + pinmux = <0x443c0024 3 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO05_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0024 2 0x443c0438 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_tpm_ch_tpm4_ch0: IOMUXC1_GPIO_IO05_TPM_CH_TPM4_CH0 { + pinmux = <0x443c0024 1 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_flexio_flexio_flexio1_flexio06: IOMUXC1_GPIO_IO06_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0028 7 0x443c0384 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_gpio_io_gpio2_io06: IOMUXC1_GPIO_IO06_GPIO_IO_GPIO2_IO06 { + pinmux = <0x443c0028 0 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO06_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0028 6 0x443c03fc 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpspi_sout_lpspi7_sout: IOMUXC1_GPIO_IO06_LPSPI_SOUT_LPSPI7_SOUT { + pinmux = <0x443c0028 4 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpuart_cts_b_lpuart6_cts_b: IOMUXC1_GPIO_IO06_LPUART_CTS_B_LPUART6_CTS_B { + pinmux = <0x443c0028 5 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_mediamix_disp_data_mediamix_disp_data02: IOMUXC1_GPIO_IO06_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA02 { + pinmux = <0x443c0028 3 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO06_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0028 2 0x443c043c 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_tpm_ch_tpm5_ch0: IOMUXC1_GPIO_IO06_TPM_CH_TPM5_CH0 { + pinmux = <0x443c0028 1 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_flexio_flexio_flexio1_flexio07: IOMUXC1_GPIO_IO07_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c002c 7 0x443c0388 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_gpio_io_gpio2_io07: IOMUXC1_GPIO_IO07_GPIO_IO_GPIO2_IO07 { + pinmux = <0x443c002c 0 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO07_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c002c 6 0x443c03f8 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1: IOMUXC1_GPIO_IO07_LPSPI_PCS_LPSPI3_PCS1 { + pinmux = <0x443c002c 1 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_sck_lpspi7_sck: IOMUXC1_GPIO_IO07_LPSPI_SCK_LPSPI7_SCK { + pinmux = <0x443c002c 4 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpuart_rts_b_lpuart6_rts_b: IOMUXC1_GPIO_IO07_LPUART_RTS_B_LPUART6_RTS_B { + pinmux = <0x443c002c 5 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_cam_data_mediamix_cam_data01: IOMUXC1_GPIO_IO07_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA01 { + pinmux = <0x443c002c 2 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_disp_data_mediamix_disp_data03: IOMUXC1_GPIO_IO07_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA03 { + pinmux = <0x443c002c 3 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_flexio_flexio_flexio1_flexio08: IOMUXC1_GPIO_IO08_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0030 7 0x443c038c 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_gpio_io_gpio2_io08: IOMUXC1_GPIO_IO08_GPIO_IO_GPIO2_IO08 { + pinmux = <0x443c0030 0 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO08_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0030 6 0x443c03fc 1 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0: IOMUXC1_GPIO_IO08_LPSPI_PCS_LPSPI3_PCS0 { + pinmux = <0x443c0030 1 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpuart_tx_lpuart7_tx: IOMUXC1_GPIO_IO08_LPUART_TX_LPUART7_TX { + pinmux = <0x443c0030 5 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_cam_data_mediamix_cam_data02: IOMUXC1_GPIO_IO08_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA02 { + pinmux = <0x443c0030 2 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_disp_data_mediamix_disp_data04: IOMUXC1_GPIO_IO08_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA04 { + pinmux = <0x443c0030 3 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_tpm_ch_tpm6_ch0: IOMUXC1_GPIO_IO08_TPM_CH_TPM6_CH0 { + pinmux = <0x443c0030 4 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_flexio_flexio_flexio1_flexio09: IOMUXC1_GPIO_IO09_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c0034 7 0x443c0390 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_gpio_io_gpio2_io09: IOMUXC1_GPIO_IO09_GPIO_IO_GPIO2_IO09 { + pinmux = <0x443c0034 0 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO09_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c0034 6 0x443c03f8 1 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin: IOMUXC1_GPIO_IO09_LPSPI_SIN_LPSPI3_SIN { + pinmux = <0x443c0034 1 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpuart_rx_lpuart7_rx: IOMUXC1_GPIO_IO09_LPUART_RX_LPUART7_RX { + pinmux = <0x443c0034 5 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_cam_data_mediamix_cam_data03: IOMUXC1_GPIO_IO09_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA03 { + pinmux = <0x443c0034 2 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_disp_data_mediamix_disp_data05: IOMUXC1_GPIO_IO09_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA05 { + pinmux = <0x443c0034 3 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_tpm_extclk_tpm3_extclk: IOMUXC1_GPIO_IO09_TPM_EXTCLK_TPM3_EXTCLK { + pinmux = <0x443c0034 4 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_flexio_flexio_flexio1_flexio10: IOMUXC1_GPIO_IO10_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0038 7 0x443c0394 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_gpio_io_gpio2_io10: IOMUXC1_GPIO_IO10_GPIO_IO_GPIO2_IO10 { + pinmux = <0x443c0038 0 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO10_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0038 6 0x443c0404 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout: IOMUXC1_GPIO_IO10_LPSPI_SOUT_LPSPI3_SOUT { + pinmux = <0x443c0038 1 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpuart_cts_b_lpuart7_cts_b: IOMUXC1_GPIO_IO10_LPUART_CTS_B_LPUART7_CTS_B { + pinmux = <0x443c0038 5 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_cam_data_mediamix_cam_data04: IOMUXC1_GPIO_IO10_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA04 { + pinmux = <0x443c0038 2 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_disp_data_mediamix_disp_data06: IOMUXC1_GPIO_IO10_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA06 { + pinmux = <0x443c0038 3 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_tpm_extclk_tpm4_extclk: IOMUXC1_GPIO_IO10_TPM_EXTCLK_TPM4_EXTCLK { + pinmux = <0x443c0038 4 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_flexio_flexio_flexio1_flexio11: IOMUXC1_GPIO_IO11_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c003c 7 0x443c0398 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_gpio_io_gpio2_io11: IOMUXC1_GPIO_IO11_GPIO_IO_GPIO2_IO11 { + pinmux = <0x443c003c 0 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO11_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c003c 6 0x443c0400 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck: IOMUXC1_GPIO_IO11_LPSPI_SCK_LPSPI3_SCK { + pinmux = <0x443c003c 1 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpuart_rts_b_lpuart7_rts_b: IOMUXC1_GPIO_IO11_LPUART_RTS_B_LPUART7_RTS_B { + pinmux = <0x443c003c 5 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_cam_data_mediamix_cam_data05: IOMUXC1_GPIO_IO11_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA05 { + pinmux = <0x443c003c 2 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_disp_data_mediamix_disp_data07: IOMUXC1_GPIO_IO11_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA07 { + pinmux = <0x443c003c 3 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_tpm_extclk_tpm5_extclk: IOMUXC1_GPIO_IO11_TPM_EXTCLK_TPM5_EXTCLK { + pinmux = <0x443c003c 4 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_gpio_io_gpio2_io12: IOMUXC1_GPIO_IO12_GPIO_IO_GPIO2_IO12 { + pinmux = <0x443c0040 0 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO12_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0040 6 0x443c0404 1 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpspi_pcs_lpspi8_pcs0: IOMUXC1_GPIO_IO12_LPSPI_PCS_LPSPI8_PCS0 { + pinmux = <0x443c0040 4 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpuart_tx_lpuart8_tx: IOMUXC1_GPIO_IO12_LPUART_TX_LPUART8_TX { + pinmux = <0x443c0040 5 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_mediamix_disp_data_mediamix_disp_data08: IOMUXC1_GPIO_IO12_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA08 { + pinmux = <0x443c0040 3 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO12_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0040 2 0x443c0440 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO12_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c0040 7 0x443c0450 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_tpm_ch_tpm3_ch2: IOMUXC1_GPIO_IO12_TPM_CH_TPM3_CH2 { + pinmux = <0x443c0040 1 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_flexio_flexio_flexio1_flexio13: IOMUXC1_GPIO_IO13_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c0044 7 0x443c039c 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_gpio_io_gpio2_io13: IOMUXC1_GPIO_IO13_GPIO_IO_GPIO2_IO13 { + pinmux = <0x443c0044 0 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO13_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c0044 6 0x443c0400 1 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpspi_sin_lpspi8_sin: IOMUXC1_GPIO_IO13_LPSPI_SIN_LPSPI8_SIN { + pinmux = <0x443c0044 4 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpuart_rx_lpuart8_rx: IOMUXC1_GPIO_IO13_LPUART_RX_LPUART8_RX { + pinmux = <0x443c0044 5 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_mediamix_disp_data_mediamix_disp_data09: IOMUXC1_GPIO_IO13_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA09 { + pinmux = <0x443c0044 3 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO13_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c0044 2 0x443c0444 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_tpm_ch_tpm4_ch2: IOMUXC1_GPIO_IO13_TPM_CH_TPM4_CH2 { + pinmux = <0x443c0044 1 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_flexio_flexio_flexio1_flexio14: IOMUXC1_GPIO_IO14_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0048 7 0x443c03a0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_gpio_io_gpio2_io14: IOMUXC1_GPIO_IO14_GPIO_IO_GPIO2_IO14 { + pinmux = <0x443c0048 0 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpspi_sout_lpspi8_sout: IOMUXC1_GPIO_IO14_LPSPI_SOUT_LPSPI8_SOUT { + pinmux = <0x443c0048 4 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_cts_b_lpuart8_cts_b: IOMUXC1_GPIO_IO14_LPUART_CTS_B_LPUART8_CTS_B { + pinmux = <0x443c0048 5 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart3_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART3_TX { + pinmux = <0x443c0048 1 0x443c041c 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart4_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART4_TX { + pinmux = <0x443c0048 6 0x443c0428 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_cam_data_mediamix_cam_data06: IOMUXC1_GPIO_IO14_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA06 { + pinmux = <0x443c0048 2 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_disp_data_mediamix_disp_data10: IOMUXC1_GPIO_IO14_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA10 { + pinmux = <0x443c0048 3 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_flexio_flexio_flexio1_flexio15: IOMUXC1_GPIO_IO15_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c004c 7 0x443c03a4 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_gpio_io_gpio2_io15: IOMUXC1_GPIO_IO15_GPIO_IO_GPIO2_IO15 { + pinmux = <0x443c004c 0 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpspi_sck_lpspi8_sck: IOMUXC1_GPIO_IO15_LPSPI_SCK_LPSPI8_SCK { + pinmux = <0x443c004c 4 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rts_b_lpuart8_rts_b: IOMUXC1_GPIO_IO15_LPUART_RTS_B_LPUART8_RTS_B { + pinmux = <0x443c004c 5 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart3_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART3_RX { + pinmux = <0x443c004c 1 0x443c0418 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart4_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART4_RX { + pinmux = <0x443c004c 6 0x443c0424 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_cam_data_mediamix_cam_data07: IOMUXC1_GPIO_IO15_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA07 { + pinmux = <0x443c004c 2 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_disp_data_mediamix_disp_data11: IOMUXC1_GPIO_IO15_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA11 { + pinmux = <0x443c004c 3 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_flexio_flexio_flexio1_flexio16: IOMUXC1_GPIO_IO16_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0050 7 0x443c03a8 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_gpio_io_gpio2_io16: IOMUXC1_GPIO_IO16_GPIO_IO_GPIO2_IO16 { + pinmux = <0x443c0050 0 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpspi_pcs_lpspi4_pcs2: IOMUXC1_GPIO_IO16_LPSPI_PCS_LPSPI4_PCS2 { + pinmux = <0x443c0050 5 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c0050 4 0x443c0414 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0050 6 0x443c0420 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_mediamix_disp_data_mediamix_disp_data12: IOMUXC1_GPIO_IO16_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA12 { + pinmux = <0x443c0050 3 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO16_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0050 2 0x443c0440 1 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk: IOMUXC1_GPIO_IO16_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x443c0050 1 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_flexio_flexio_flexio1_flexio17: IOMUXC1_GPIO_IO17_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c0054 7 0x443c03ac 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_gpio_io_gpio2_io17: IOMUXC1_GPIO_IO17_GPIO_IO_GPIO2_IO17 { + pinmux = <0x443c0054 0 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpspi_pcs_lpspi4_pcs1: IOMUXC1_GPIO_IO17_LPSPI_PCS_LPSPI4_PCS1 { + pinmux = <0x443c0054 5 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c0054 4 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c0054 6 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_cam_data_mediamix_cam_data08: IOMUXC1_GPIO_IO17_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA08 { + pinmux = <0x443c0054 2 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_disp_data_mediamix_disp_data13: IOMUXC1_GPIO_IO17_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA13 { + pinmux = <0x443c0054 3 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_sai_mclk_sai3_mclk: IOMUXC1_GPIO_IO17_SAI_MCLK_SAI3_MCLK { + pinmux = <0x443c0054 1 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_flexio_flexio_flexio1_flexio18: IOMUXC1_GPIO_IO18_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0058 7 0x443c03b0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_gpio_io_gpio2_io18: IOMUXC1_GPIO_IO18_GPIO_IO_GPIO2_IO18 { + pinmux = <0x443c0058 0 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi4_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI4_PCS0 { + pinmux = <0x443c0058 5 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi5_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI5_PCS0 { + pinmux = <0x443c0058 4 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_cam_data_mediamix_cam_data09: IOMUXC1_GPIO_IO18_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA09 { + pinmux = <0x443c0058 2 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_disp_data_mediamix_disp_data14: IOMUXC1_GPIO_IO18_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA14 { + pinmux = <0x443c0058 3 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO18_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0058 1 0x443c044c 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_tpm_ch_tpm5_ch2: IOMUXC1_GPIO_IO18_TPM_CH_TPM5_CH2 { + pinmux = <0x443c0058 6 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_gpio_io_gpio2_io19: IOMUXC1_GPIO_IO19_GPIO_IO_GPIO2_IO19 { + pinmux = <0x443c005c 0 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi4_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI4_SIN { + pinmux = <0x443c005c 5 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi5_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI5_SIN { + pinmux = <0x443c005c 4 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_mediamix_disp_data_mediamix_disp_data15: IOMUXC1_GPIO_IO19_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA15 { + pinmux = <0x443c005c 3 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO19_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c005c 2 0x443c0444 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO19_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c005c 1 0x443c0450 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO19_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c005c 7 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_tpm_ch_tpm6_ch2: IOMUXC1_GPIO_IO19_TPM_CH_TPM6_CH2 { + pinmux = <0x443c005c 6 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_flexio_flexio_flexio1_flexio20: IOMUXC1_GPIO_IO20_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0060 7 0x443c03b4 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_gpio_io_gpio2_io20: IOMUXC1_GPIO_IO20_GPIO_IO_GPIO2_IO20 { + pinmux = <0x443c0060 0 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi4_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI4_SOUT { + pinmux = <0x443c0060 5 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi5_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI5_SOUT { + pinmux = <0x443c0060 4 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_mediamix_disp_data_mediamix_disp_data16: IOMUXC1_GPIO_IO20_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA16 { + pinmux = <0x443c0060 3 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO20_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0060 2 0x443c0438 1 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data00: IOMUXC1_GPIO_IO20_SAI_RX_DATA_SAI3_RX_DATA00 { + pinmux = <0x443c0060 1 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_tpm_ch_tpm3_ch1: IOMUXC1_GPIO_IO20_TPM_CH_TPM3_CH1 { + pinmux = <0x443c0060 6 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_gpio_io_gpio2_io21: IOMUXC1_GPIO_IO21_GPIO_IO_GPIO2_IO21 { + pinmux = <0x443c0064 0 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi4_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI4_SCK { + pinmux = <0x443c0064 5 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi5_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI5_SCK { + pinmux = <0x443c0064 4 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_mediamix_disp_data_mediamix_disp_data17: IOMUXC1_GPIO_IO21_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA17 { + pinmux = <0x443c0064 3 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO21_PDM_CLK_PDM_CLK { + pinmux = <0x443c0064 2 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO21_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0064 7 0x443c044c 1 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO21_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c0064 1 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_tpm_ch_tpm4_ch1: IOMUXC1_GPIO_IO21_TPM_CH_TPM4_CH1 { + pinmux = <0x443c0064 6 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_flexio_flexio_flexio1_flexio22: IOMUXC1_GPIO_IO22_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0068 7 0x443c03b8 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_gpio_io_gpio2_io22: IOMUXC1_GPIO_IO22_GPIO_IO_GPIO2_IO22 { + pinmux = <0x443c0068 0 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO22_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0068 6 0x443c03ec 1 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_mediamix_disp_data_mediamix_disp_data18: IOMUXC1_GPIO_IO22_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA18 { + pinmux = <0x443c0068 3 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_spdif_in_spdif_in: IOMUXC1_GPIO_IO22_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0068 2 0x443c0454 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_ch_tpm5_ch1: IOMUXC1_GPIO_IO22_TPM_CH_TPM5_CH1 { + pinmux = <0x443c0068 4 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_extclk_tpm6_extclk: IOMUXC1_GPIO_IO22_TPM_EXTCLK_TPM6_EXTCLK { + pinmux = <0x443c0068 5 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_usdhc_clk_usdhc3_clk: IOMUXC1_GPIO_IO22_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0068 1 0x443c0458 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_flexio_flexio_flexio1_flexio23: IOMUXC1_GPIO_IO23_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c006c 7 0x443c03bc 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_gpio_io_gpio2_io23: IOMUXC1_GPIO_IO23_GPIO_IO_GPIO2_IO23 { + pinmux = <0x443c006c 0 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO23_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c006c 6 0x443c03e8 1 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_mediamix_disp_data_mediamix_disp_data19: IOMUXC1_GPIO_IO23_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA19 { + pinmux = <0x443c006c 3 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_spdif_out_spdif_out: IOMUXC1_GPIO_IO23_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c006c 2 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_tpm_ch_tpm6_ch1: IOMUXC1_GPIO_IO23_TPM_CH_TPM6_CH1 { + pinmux = <0x443c006c 4 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_usdhc_cmd_usdhc3_cmd: IOMUXC1_GPIO_IO23_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c006c 1 0x443c045c 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_flexio_flexio_flexio1_flexio24: IOMUXC1_GPIO_IO24_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0070 7 0x443c03c0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_gpio_io_gpio2_io24: IOMUXC1_GPIO_IO24_GPIO_IO_GPIO2_IO24 { + pinmux = <0x443c0070 0 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_GPIO_IO24_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c0070 5 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_lpspi_pcs_lpspi6_pcs1: IOMUXC1_GPIO_IO24_LPSPI_PCS_LPSPI6_PCS1 { + pinmux = <0x443c0070 6 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_mediamix_disp_data_mediamix_disp_data20: IOMUXC1_GPIO_IO24_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA20 { + pinmux = <0x443c0070 3 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_tpm_ch_tpm3_ch3: IOMUXC1_GPIO_IO24_TPM_CH_TPM3_CH3 { + pinmux = <0x443c0070 4 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_usdhc_data_usdhc3_data0: IOMUXC1_GPIO_IO24_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0070 1 0x443c0460 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_can_tx_can2_tx: IOMUXC1_GPIO_IO25_CAN_TX_CAN2_TX { + pinmux = <0x443c0074 2 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_flexio_flexio_flexio1_flexio25: IOMUXC1_GPIO_IO25_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c0074 7 0x443c03c4 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_gpio_io_gpio2_io25: IOMUXC1_GPIO_IO25_GPIO_IO_GPIO2_IO25 { + pinmux = <0x443c0074 0 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_jtag_mux_tck_jtag_mux_tck: IOMUXC1_GPIO_IO25_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0074 5 0x443c03d4 1 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_lpspi_pcs_lpspi7_pcs1: IOMUXC1_GPIO_IO25_LPSPI_PCS_LPSPI7_PCS1 { + pinmux = <0x443c0074 6 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_mediamix_disp_data_mediamix_disp_data21: IOMUXC1_GPIO_IO25_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA21 { + pinmux = <0x443c0074 3 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_tpm_ch_tpm4_ch3: IOMUXC1_GPIO_IO25_TPM_CH_TPM4_CH3 { + pinmux = <0x443c0074 4 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_usdhc_data_usdhc3_data1: IOMUXC1_GPIO_IO25_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0074 1 0x443c0464 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_gpio_io_gpio2_io26: IOMUXC1_GPIO_IO26_GPIO_IO_GPIO2_IO26 { + pinmux = <0x443c0078 0 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_GPIO_IO26_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0078 5 0x443c03d8 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_lpspi_pcs_lpspi8_pcs1: IOMUXC1_GPIO_IO26_LPSPI_PCS_LPSPI8_PCS1 { + pinmux = <0x443c0078 6 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_mediamix_disp_data_mediamix_disp_data22: IOMUXC1_GPIO_IO26_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA22 { + pinmux = <0x443c0078 3 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO26_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0078 2 0x443c043c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync: IOMUXC1_GPIO_IO26_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x443c0078 7 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_tpm_ch_tpm5_ch3: IOMUXC1_GPIO_IO26_TPM_CH_TPM5_CH3 { + pinmux = <0x443c0078 4 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_usdhc_data_usdhc3_data2: IOMUXC1_GPIO_IO26_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0078 1 0x443c0468 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_can_rx_can2_rx: IOMUXC1_GPIO_IO27_CAN_RX_CAN2_RX { + pinmux = <0x443c007c 2 0x443c0364 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_flexio_flexio_flexio1_flexio27: IOMUXC1_GPIO_IO27_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c007c 7 0x443c03c8 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_gpio_io_gpio2_io27: IOMUXC1_GPIO_IO27_GPIO_IO_GPIO2_IO27 { + pinmux = <0x443c007c 0 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_jtag_mux_tms_jtag_mux_tms: IOMUXC1_GPIO_IO27_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c007c 5 0x443c03dc 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_lpspi_pcs_lpspi5_pcs1: IOMUXC1_GPIO_IO27_LPSPI_PCS_LPSPI5_PCS1 { + pinmux = <0x443c007c 6 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_mediamix_disp_data_mediamix_disp_data23: IOMUXC1_GPIO_IO27_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA23 { + pinmux = <0x443c007c 3 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_tpm_ch_tpm6_ch3: IOMUXC1_GPIO_IO27_TPM_CH_TPM6_CH3 { + pinmux = <0x443c007c 4 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_usdhc_data_usdhc3_data3: IOMUXC1_GPIO_IO27_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c007c 1 0x443c046c 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_flexio_flexio_flexio1_flexio28: IOMUXC1_GPIO_IO28_FLEXIO_FLEXIO_FLEXIO1_FLEXIO28 { + pinmux = <0x443c0080 7 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_gpio_io_gpio2_io28: IOMUXC1_GPIO_IO28_GPIO_IO_GPIO2_IO28 { + pinmux = <0x443c0080 0 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO28_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0080 1 0x443c03e4 1 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_flexio_flexio_flexio1_flexio29: IOMUXC1_GPIO_IO29_FLEXIO_FLEXIO_FLEXIO1_FLEXIO29 { + pinmux = <0x443c0084 7 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_gpio_io_gpio2_io29: IOMUXC1_GPIO_IO29_GPIO_IO_GPIO2_IO29 { + pinmux = <0x443c0084 0 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO29_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0084 1 0x443c03e0 1 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_gpio_io_gpio1_io00: IOMUXC1_I2C1_SCL_GPIO_IO_GPIO1_IO00 { + pinmux = <0x443c0170 5 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_i3c_scl_i3c1_scl: IOMUXC1_I2C1_SCL_I3C_SCL_I3C1_SCL { + pinmux = <0x443c0170 1 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl: IOMUXC1_I2C1_SCL_LPI2C_SCL_LPI2C1_SCL { + pinmux = <0x443c0170 0 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpuart_dcb_b_lpuart1_dcb_b: IOMUXC1_I2C1_SCL_LPUART_DCB_B_LPUART1_DCB_B { + pinmux = <0x443c0170 2 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_tpm_ch_tpm2_ch0: IOMUXC1_I2C1_SCL_TPM_CH_TPM2_CH0 { + pinmux = <0x443c0170 3 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_gpio_io_gpio1_io01: IOMUXC1_I2C1_SDA_GPIO_IO_GPIO1_IO01 { + pinmux = <0x443c0174 5 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_i3c_sda_i3c1_sda: IOMUXC1_I2C1_SDA_I3C_SDA_I3C1_SDA { + pinmux = <0x443c0174 1 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda: IOMUXC1_I2C1_SDA_LPI2C_SDA_LPI2C1_SDA { + pinmux = <0x443c0174 0 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpuart_rin_b_lpuart1_rin_b: IOMUXC1_I2C1_SDA_LPUART_RIN_B_LPUART1_RIN_B { + pinmux = <0x443c0174 2 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_tpm_ch_tpm2_ch1: IOMUXC1_I2C1_SDA_TPM_CH_TPM2_CH1 { + pinmux = <0x443c0174 3 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_gpio_io_gpio1_io02: IOMUXC1_I2C2_SCL_GPIO_IO_GPIO1_IO02 { + pinmux = <0x443c0178 5 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_b_i3c1_pur_b: IOMUXC1_I2C2_SCL_I3C_PUR_B_I3C1_PUR_B { + pinmux = <0x443c0178 6 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_i3c1_pur: IOMUXC1_I2C2_SCL_I3C_PUR_I3C1_PUR { + pinmux = <0x443c0178 1 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl: IOMUXC1_I2C2_SCL_LPI2C_SCL_LPI2C2_SCL { + pinmux = <0x443c0178 0 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpuart_dcb_b_lpuart2_dcb_b: IOMUXC1_I2C2_SCL_LPUART_DCB_B_LPUART2_DCB_B { + pinmux = <0x443c0178 2 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_sai_rx_sync_sai1_rx_sync: IOMUXC1_I2C2_SCL_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x443c0178 4 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_tpm_ch_tpm2_ch2: IOMUXC1_I2C2_SCL_TPM_CH_TPM2_CH2 { + pinmux = <0x443c0178 3 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_gpio_io_gpio1_io03: IOMUXC1_I2C2_SDA_GPIO_IO_GPIO1_IO03 { + pinmux = <0x443c017c 5 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda: IOMUXC1_I2C2_SDA_LPI2C_SDA_LPI2C2_SDA { + pinmux = <0x443c017c 0 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpuart_rin_b_lpuart2_rin_b: IOMUXC1_I2C2_SDA_LPUART_RIN_B_LPUART2_RIN_B { + pinmux = <0x443c017c 2 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_sai_rx_bclk_sai1_rx_bclk: IOMUXC1_I2C2_SDA_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x443c017c 4 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_tpm_ch_tpm2_ch3: IOMUXC1_I2C2_SDA_TPM_CH_TPM2_CH3 { + pinmux = <0x443c017c 3 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_can_rx_can1_rx: IOMUXC1_PDM_BIT_STREAM0_CAN_RX_CAN1_RX { + pinmux = <0x443c0194 6 0x443c0360 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09: IOMUXC1_PDM_BIT_STREAM0_GPIO_IO_GPIO1_IO09 { + pinmux = <0x443c0194 5 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lpspi_pcs_lpspi1_pcs1: IOMUXC1_PDM_BIT_STREAM0_LPSPI_PCS_LPSPI1_PCS1 { + pinmux = <0x443c0194 2 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lptmr_alt_lptmr1_alt2: IOMUXC1_PDM_BIT_STREAM0_LPTMR_ALT_LPTMR1_ALT2 { + pinmux = <0x443c0194 4 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_mqs_right_mqs1_right: IOMUXC1_PDM_BIT_STREAM0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c0194 1 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_PDM_BIT_STREAM0_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0194 0 0x443c0438 2 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_tpm_extclk_tpm1_extclk: IOMUXC1_PDM_BIT_STREAM0_TPM_EXTCLK_TPM1_EXTCLK { + pinmux = <0x443c0194 3 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0198 6 0x443c0368 1 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10: IOMUXC1_PDM_BIT_STREAM1_GPIO_IO_GPIO1_IO10 { + pinmux = <0x443c0198 5 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lpspi_pcs_lpspi2_pcs1: IOMUXC1_PDM_BIT_STREAM1_LPSPI_PCS_LPSPI2_PCS1 { + pinmux = <0x443c0198 2 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lptmr_alt_lptmr1_alt3: IOMUXC1_PDM_BIT_STREAM1_LPTMR_ALT_LPTMR1_ALT3 { + pinmux = <0x443c0198 4 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_nmi_glue_nmi_nmi_glue_nmi: IOMUXC1_PDM_BIT_STREAM1_NMI_GLUE_NMI_NMI_GLUE_NMI { + pinmux = <0x443c0198 1 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_PDM_BIT_STREAM1_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0198 0 0x443c043c 2 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_tpm_extclk_tpm2_extclk: IOMUXC1_PDM_BIT_STREAM1_TPM_EXTCLK_TPM2_EXTCLK { + pinmux = <0x443c0198 3 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_can_tx_can1_tx: IOMUXC1_PDM_CLK_CAN_TX_CAN1_TX { + pinmux = <0x443c0190 6 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_gpio_io_gpio1_io08: IOMUXC1_PDM_CLK_GPIO_IO_GPIO1_IO08 { + pinmux = <0x443c0190 5 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_lptmr_alt_lptmr1_alt1: IOMUXC1_PDM_CLK_LPTMR_ALT_LPTMR1_ALT1 { + pinmux = <0x443c0190 4 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_mqs_left_mqs1_left: IOMUXC1_PDM_CLK_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c0190 1 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_pdm_clk_pdm_clk: IOMUXC1_PDM_CLK_PDM_CLK_PDM_CLK { + pinmux = <0x443c0190 0 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_gpio_io_gpio1_io14: IOMUXC1_SAI1_RXD0_GPIO_IO_GPIO1_IO14 { + pinmux = <0x443c01a8 5 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpspi_sout_lpspi1_sout: IOMUXC1_SAI1_RXD0_LPSPI_SOUT_LPSPI1_SOUT { + pinmux = <0x443c01a8 2 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpuart_dsr_b_lpuart2_dsr_b: IOMUXC1_SAI1_RXD0_LPUART_DSR_B_LPUART2_DSR_B { + pinmux = <0x443c01a8 3 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_mqs_right_mqs1_right: IOMUXC1_SAI1_RXD0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c01a8 4 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_mclk_sai1_mclk: IOMUXC1_SAI1_RXD0_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c01a8 1 0x443c0448 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_rx_data_sai1_rx_data00: IOMUXC1_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA00 { + pinmux = <0x443c01a8 0 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_can_rx_can1_rx: IOMUXC1_SAI1_TXC_CAN_RX_CAN1_RX { + pinmux = <0x443c01a0 4 0x443c0360 1 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_gpio_io_gpio1_io12: IOMUXC1_SAI1_TXC_GPIO_IO_GPIO1_IO12 { + pinmux = <0x443c01a0 5 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpspi_sin_lpspi1_sin: IOMUXC1_SAI1_TXC_LPSPI_SIN_LPSPI1_SIN { + pinmux = <0x443c01a0 2 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_cts_b_lpuart2_cts_b: IOMUXC1_SAI1_TXC_LPUART_CTS_B_LPUART2_CTS_B { + pinmux = <0x443c01a0 1 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_dsr_b_lpuart1_dsr_b: IOMUXC1_SAI1_TXC_LPUART_DSR_B_LPUART1_DSR_B { + pinmux = <0x443c01a0 3 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC1_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x443c01a0 0 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_can_tx_can1_tx: IOMUXC1_SAI1_TXD0_CAN_TX_CAN1_TX { + pinmux = <0x443c01a4 4 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_gpio_io_gpio1_io13: IOMUXC1_SAI1_TXD0_GPIO_IO_GPIO1_IO13 { + pinmux = <0x443c01a4 5 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpspi_sck_lpspi1_sck: IOMUXC1_SAI1_TXD0_LPSPI_SCK_LPSPI1_SCK { + pinmux = <0x443c01a4 2 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_dtr_b_lpuart1_dtr_b: IOMUXC1_SAI1_TXD0_LPUART_DTR_B_LPUART1_DTR_B { + pinmux = <0x443c01a4 3 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_rts_b_lpuart2_rts_b: IOMUXC1_SAI1_TXD0_LPUART_RTS_B_LPUART2_RTS_B { + pinmux = <0x443c01a4 1 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_sai_tx_data_sai1_tx_data00: IOMUXC1_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA00 { + pinmux = <0x443c01a4 0 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_gpio_io_gpio1_io11: IOMUXC1_SAI1_TXFS_GPIO_IO_GPIO1_IO11 { + pinmux = <0x443c019c 5 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpspi_pcs_lpspi1_pcs0: IOMUXC1_SAI1_TXFS_LPSPI_PCS_LPSPI1_PCS0 { + pinmux = <0x443c019c 2 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpuart_dtr_b_lpuart2_dtr_b: IOMUXC1_SAI1_TXFS_LPUART_DTR_B_LPUART2_DTR_B { + pinmux = <0x443c019c 3 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_mqs_left_mqs1_left: IOMUXC1_SAI1_TXFS_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c019c 4 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_data_sai1_tx_data01: IOMUXC1_SAI1_TXFS_SAI_TX_DATA_SAI1_TX_DATA01 { + pinmux = <0x443c019c 1 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC1_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x443c019c 0 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_flexio_flexio_flexio1_flexio08: IOMUXC1_SD1_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0108 4 0x443c038c 1 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_gpio_io_gpio3_io08: IOMUXC1_SD1_CLK_GPIO_IO_GPIO3_IO08 { + pinmux = <0x443c0108 5 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC1_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x443c0108 0 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_flexio_flexio_flexio1_flexio09: IOMUXC1_SD1_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c010c 4 0x443c0390 1 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_gpio_io_gpio3_io09: IOMUXC1_SD1_CMD_GPIO_IO_GPIO3_IO09 { + pinmux = <0x443c010c 5 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC1_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x443c010c 0 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_flexio_flexio_flexio1_flexio10: IOMUXC1_SD1_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0110 4 0x443c0394 1 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_gpio_io_gpio3_io10: IOMUXC1_SD1_DATA0_GPIO_IO_GPIO3_IO10 { + pinmux = <0x443c0110 5 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC1_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x443c0110 0 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_flexio_flexio_flexio1_flexio11: IOMUXC1_SD1_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c0114 4 0x443c0398 1 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_gpio_io_gpio3_io11: IOMUXC1_SD1_DATA1_GPIO_IO_GPIO3_IO11 { + pinmux = <0x443c0114 5 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC1_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x443c0114 0 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_flexio_flexio_flexio1_flexio12: IOMUXC1_SD1_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO12 { + pinmux = <0x443c0118 4 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_gpio_io_gpio3_io12: IOMUXC1_SD1_DATA2_GPIO_IO_GPIO3_IO12 { + pinmux = <0x443c0118 5 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC1_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x443c0118 0 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexio_flexio_flexio1_flexio13: IOMUXC1_SD1_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c011c 4 0x443c039c 1 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexspi_a_ss_b_flexspi1_a_ss1_b: IOMUXC1_SD1_DATA3_FLEXSPI_A_SS_B_FLEXSPI1_A_SS1_B { + pinmux = <0x443c011c 1 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_gpio_io_gpio3_io13: IOMUXC1_SD1_DATA3_GPIO_IO_GPIO3_IO13 { + pinmux = <0x443c011c 5 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC1_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x443c011c 0 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexio_flexio_flexio1_flexio14: IOMUXC1_SD1_DATA4_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0120 4 0x443c03a0 1 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexspi_a_data_flexspi1_a_data04: IOMUXC1_SD1_DATA4_FLEXSPI_A_DATA_FLEXSPI1_A_DATA04 { + pinmux = <0x443c0120 1 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_gpio_io_gpio3_io14: IOMUXC1_SD1_DATA4_GPIO_IO_GPIO3_IO14 { + pinmux = <0x443c0120 5 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC1_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x443c0120 0 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexio_flexio_flexio1_flexio15: IOMUXC1_SD1_DATA5_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c0124 4 0x443c03a4 1 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexspi_a_data_flexspi1_a_data05: IOMUXC1_SD1_DATA5_FLEXSPI_A_DATA_FLEXSPI1_A_DATA05 { + pinmux = <0x443c0124 1 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_gpio_io_gpio3_io15: IOMUXC1_SD1_DATA5_GPIO_IO_GPIO3_IO15 { + pinmux = <0x443c0124 5 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC1_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x443c0124 0 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_reset_b_usdhc1_reset_b: IOMUXC1_SD1_DATA5_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x443c0124 2 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexio_flexio_flexio1_flexio16: IOMUXC1_SD1_DATA6_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0128 4 0x443c03a8 1 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexspi_a_data_flexspi1_a_data06: IOMUXC1_SD1_DATA6_FLEXSPI_A_DATA_FLEXSPI1_A_DATA06 { + pinmux = <0x443c0128 1 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_gpio_io_gpio3_io16: IOMUXC1_SD1_DATA6_GPIO_IO_GPIO3_IO16 { + pinmux = <0x443c0128 5 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_cd_b_usdhc1_cd_b: IOMUXC1_SD1_DATA6_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x443c0128 2 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC1_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x443c0128 0 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexio_flexio_flexio1_flexio17: IOMUXC1_SD1_DATA7_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c012c 4 0x443c03ac 1 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexspi_a_data_flexspi1_a_data07: IOMUXC1_SD1_DATA7_FLEXSPI_A_DATA_FLEXSPI1_A_DATA07 { + pinmux = <0x443c012c 1 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_gpio_io_gpio3_io17: IOMUXC1_SD1_DATA7_GPIO_IO_GPIO3_IO17 { + pinmux = <0x443c012c 5 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC1_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x443c012c 0 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_wp_usdhc1_wp: IOMUXC1_SD1_DATA7_USDHC_WP_USDHC1_WP { + pinmux = <0x443c012c 2 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexio_flexio_flexio1_flexio18: IOMUXC1_SD1_STROBE_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0130 4 0x443c03b0 1 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexspi_a_dqs_flexspi1_a_dqs: IOMUXC1_SD1_STROBE_FLEXSPI_A_DQS_FLEXSPI1_A_DQS { + pinmux = <0x443c0130 1 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_gpio_io_gpio3_io18: IOMUXC1_SD1_STROBE_GPIO_IO_GPIO3_IO18 { + pinmux = <0x443c0130 5 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC1_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x443c0130 0 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC1_SD2_CD_B_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x443c0150 1 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_flexio_flexio_flexio1_flexio00: IOMUXC1_SD2_CD_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0150 4 0x443c036c 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_gpio_io_gpio3_io00: IOMUXC1_SD2_CD_B_GPIO_IO_GPIO3_IO00 { + pinmux = <0x443c0150 5 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_i3c_scl_i3c2_scl: IOMUXC1_SD2_CD_B_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0150 2 0x443c03cc 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC1_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x443c0150 0 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe0: IOMUXC1_SD2_CLK_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE0 { + pinmux = <0x443c0154 6 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC1_SD2_CLK_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x443c0154 1 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_flexio_flexio_flexio1_flexio01: IOMUXC1_SD2_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0154 4 0x443c0370 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_gpio_io_gpio3_io01: IOMUXC1_SD2_CLK_GPIO_IO_GPIO3_IO01 { + pinmux = <0x443c0154 5 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_i3c_sda_i3c2_sda: IOMUXC1_SD2_CLK_I3C_SDA_I3C2_SDA { + pinmux = <0x443c0154 2 0x443c03d0 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC1_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x443c0154 0 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe1: IOMUXC1_SD2_CMD_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE1 { + pinmux = <0x443c0158 6 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_enet1_1588_event0_in_enet1_1588_event0_in: IOMUXC1_SD2_CMD_ENET1_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x443c0158 1 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_flexio_flexio_flexio1_flexio02: IOMUXC1_SD2_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0158 4 0x443c0374 1 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_gpio_io_gpio3_io02: IOMUXC1_SD2_CMD_GPIO_IO_GPIO3_IO02 { + pinmux = <0x443c0158 5 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_b_i3c2_pur_b: IOMUXC1_SD2_CMD_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c0158 3 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_i3c2_pur: IOMUXC1_SD2_CMD_I3C_PUR_I3C2_PUR { + pinmux = <0x443c0158 2 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC1_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x443c0158 0 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_can_tx_can2_tx: IOMUXC1_SD2_DATA0_CAN_TX_CAN2_TX { + pinmux = <0x443c015c 2 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe2: IOMUXC1_SD2_DATA0_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE2 { + pinmux = <0x443c015c 6 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_enet1_1588_event0_out_enet1_1588_event0_out: IOMUXC1_SD2_DATA0_ENET1_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x443c015c 1 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_flexio_flexio_flexio1_flexio03: IOMUXC1_SD2_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c015c 4 0x443c0378 1 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_gpio_io_gpio3_io03: IOMUXC1_SD2_DATA0_GPIO_IO_GPIO3_IO03 { + pinmux = <0x443c015c 5 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC1_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x443c015c 0 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_can_rx_can2_rx: IOMUXC1_SD2_DATA1_CAN_RX_CAN2_RX { + pinmux = <0x443c0160 2 0x443c0364 3 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_enet1_1588_event1_in_enet1_1588_event1_in: IOMUXC1_SD2_DATA1_ENET1_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x443c0160 1 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_flexio_flexio_flexio1_flexio04: IOMUXC1_SD2_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0160 4 0x443c037c 1 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_gpio_io_gpio3_io04: IOMUXC1_SD2_DATA1_GPIO_IO_GPIO3_IO04 { + pinmux = <0x443c0160 5 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC1_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x443c0160 0 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_enet1_1588_event1_out_enet1_1588_event1_out: IOMUXC1_SD2_DATA2_ENET1_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x443c0164 1 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_flexio_flexio_flexio1_flexio05: IOMUXC1_SD2_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0164 4 0x443c0380 1 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_gpio_io_gpio3_io05: IOMUXC1_SD2_DATA2_GPIO_IO_GPIO3_IO05 { + pinmux = <0x443c0164 5 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_mqs_right_mqs2_right: IOMUXC1_SD2_DATA2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0164 2 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC1_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x443c0164 0 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_flexio_flexio_flexio1_flexio06: IOMUXC1_SD2_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0168 4 0x443c0384 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_gpio_io_gpio3_io06: IOMUXC1_SD2_DATA3_GPIO_IO_GPIO3_IO06 { + pinmux = <0x443c0168 5 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_lptmr_alt_lptmr2_alt1: IOMUXC1_SD2_DATA3_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c0168 1 0x443c0408 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_mqs_left_mqs2_left: IOMUXC1_SD2_DATA3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0168 2 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC1_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x443c0168 0 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_ccmsrcgpcmix_system_reset_ccmsrcgpcmix_system_reset: IOMUXC1_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET_CCMSRCGPCMIX_SYSTEM_RESET { + pinmux = <0x443c016c 6 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_flexio_flexio_flexio1_flexio07: IOMUXC1_SD2_RESET_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c016c 4 0x443c0388 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_gpio_io_gpio3_io07: IOMUXC1_SD2_RESET_B_GPIO_IO_GPIO3_IO07 { + pinmux = <0x443c016c 5 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_lptmr_alt_lptmr2_alt2: IOMUXC1_SD2_RESET_B_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c016c 1 0x443c040c 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC1_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x443c016c 0 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0134 6 0x443c0368 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_flexio_flexio_flexio1_flexio19: IOMUXC1_SD2_VSELECT_FLEXIO_FLEXIO_FLEXIO1_FLEXIO19 { + pinmux = <0x443c0134 4 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_gpio_io_gpio3_io19: IOMUXC1_SD2_VSELECT_GPIO_IO_GPIO3_IO19 { + pinmux = <0x443c0134 5 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_lptmr_alt_lptmr2_alt3: IOMUXC1_SD2_VSELECT_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c0134 2 0x443c0410 1 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect: IOMUXC1_SD2_VSELECT_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x443c0134 0 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_wp_usdhc2_wp: IOMUXC1_SD2_VSELECT_USDHC_WP_USDHC2_WP { + pinmux = <0x443c0134 1 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexio_flexio_flexio1_flexio20: IOMUXC1_SD3_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0138 4 0x443c03b4 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexspi_a_sclk_flexspi1_a_sclk: IOMUXC1_SD3_CLK_FLEXSPI_A_SCLK_FLEXSPI1_A_SCLK { + pinmux = <0x443c0138 1 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_gpio_io_gpio3_io20: IOMUXC1_SD3_CLK_GPIO_IO_GPIO3_IO20 { + pinmux = <0x443c0138 5 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_usdhc_clk_usdhc3_clk: IOMUXC1_SD3_CLK_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0138 0 0x443c0458 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexio_flexio_flexio1_flexio21: IOMUXC1_SD3_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO21 { + pinmux = <0x443c013c 4 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexspi_a_ss_b_flexspi1_a_ss0_b: IOMUXC1_SD3_CMD_FLEXSPI_A_SS_B_FLEXSPI1_A_SS0_B { + pinmux = <0x443c013c 1 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_gpio_io_gpio3_io21: IOMUXC1_SD3_CMD_GPIO_IO_GPIO3_IO21 { + pinmux = <0x443c013c 5 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_usdhc_cmd_usdhc3_cmd: IOMUXC1_SD3_CMD_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c013c 0 0x443c045c 1 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexio_flexio_flexio1_flexio22: IOMUXC1_SD3_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0140 4 0x443c03b8 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexspi_a_data_flexspi1_a_data00: IOMUXC1_SD3_DATA0_FLEXSPI_A_DATA_FLEXSPI1_A_DATA00 { + pinmux = <0x443c0140 1 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_gpio_io_gpio3_io22: IOMUXC1_SD3_DATA0_GPIO_IO_GPIO3_IO22 { + pinmux = <0x443c0140 5 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_usdhc_data_usdhc3_data0: IOMUXC1_SD3_DATA0_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0140 0 0x443c0460 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexio_flexio_flexio1_flexio23: IOMUXC1_SD3_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c0144 4 0x443c03bc 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexspi_a_data_flexspi1_a_data01: IOMUXC1_SD3_DATA1_FLEXSPI_A_DATA_FLEXSPI1_A_DATA01 { + pinmux = <0x443c0144 1 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_gpio_io_gpio3_io23: IOMUXC1_SD3_DATA1_GPIO_IO_GPIO3_IO23 { + pinmux = <0x443c0144 5 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_usdhc_data_usdhc3_data1: IOMUXC1_SD3_DATA1_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0144 0 0x443c0464 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexio_flexio_flexio1_flexio24: IOMUXC1_SD3_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0148 4 0x443c03c0 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexspi_a_data_flexspi1_a_data02: IOMUXC1_SD3_DATA2_FLEXSPI_A_DATA_FLEXSPI1_A_DATA02 { + pinmux = <0x443c0148 1 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_gpio_io_gpio3_io24: IOMUXC1_SD3_DATA2_GPIO_IO_GPIO3_IO24 { + pinmux = <0x443c0148 5 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_usdhc_data_usdhc3_data2: IOMUXC1_SD3_DATA2_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0148 0 0x443c0468 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexio_flexio_flexio1_flexio25: IOMUXC1_SD3_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c014c 4 0x443c03c4 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexspi_a_data_flexspi1_a_data03: IOMUXC1_SD3_DATA3_FLEXSPI_A_DATA_FLEXSPI1_A_DATA03 { + pinmux = <0x443c014c 1 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_gpio_io_gpio3_io25: IOMUXC1_SD3_DATA3_GPIO_IO_GPIO3_IO25 { + pinmux = <0x443c014c 5 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_usdhc_data_usdhc3_data3: IOMUXC1_SD3_DATA3_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c014c 0 0x443c046c 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_gpio_io_gpio1_io04: IOMUXC1_UART1_RXD_GPIO_IO_GPIO1_IO04 { + pinmux = <0x443c0180 5 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpspi_sin_lpspi2_sin: IOMUXC1_UART1_RXD_LPSPI_SIN_LPSPI2_SIN { + pinmux = <0x443c0180 2 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx: IOMUXC1_UART1_RXD_LPUART_RX_LPUART1_RX { + pinmux = <0x443c0180 0 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_s400_uart_rx_s400_uart_rx: IOMUXC1_UART1_RXD_S400_UART_RX_S400_UART_RX { + pinmux = <0x443c0180 1 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_tpm_ch_tpm1_ch0: IOMUXC1_UART1_RXD_TPM_CH_TPM1_CH0 { + pinmux = <0x443c0180 3 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_gpio_io_gpio1_io05: IOMUXC1_UART1_TXD_GPIO_IO_GPIO1_IO05 { + pinmux = <0x443c0184 5 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpspi_pcs_lpspi2_pcs0: IOMUXC1_UART1_TXD_LPSPI_PCS_LPSPI2_PCS0 { + pinmux = <0x443c0184 2 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx: IOMUXC1_UART1_TXD_LPUART_TX_LPUART1_TX { + pinmux = <0x443c0184 0 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_s400_uart_tx_s400_uart_tx: IOMUXC1_UART1_TXD_S400_UART_TX_S400_UART_TX { + pinmux = <0x443c0184 1 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_tpm_ch_tpm1_ch1: IOMUXC1_UART1_TXD_TPM_CH_TPM1_CH1 { + pinmux = <0x443c0184 3 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_gpio_io_gpio1_io06: IOMUXC1_UART2_RXD_GPIO_IO_GPIO1_IO06 { + pinmux = <0x443c0188 5 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpspi_sout_lpspi2_sout: IOMUXC1_UART2_RXD_LPSPI_SOUT_LPSPI2_SOUT { + pinmux = <0x443c0188 2 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_cts_b_lpuart1_cts_b: IOMUXC1_UART2_RXD_LPUART_CTS_B_LPUART1_CTS_B { + pinmux = <0x443c0188 1 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx: IOMUXC1_UART2_RXD_LPUART_RX_LPUART2_RX { + pinmux = <0x443c0188 0 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_sai_mclk_sai1_mclk: IOMUXC1_UART2_RXD_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c0188 4 0x443c0448 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_tpm_ch_tpm1_ch2: IOMUXC1_UART2_RXD_TPM_CH_TPM1_CH2 { + pinmux = <0x443c0188 3 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_gpio_io_gpio1_io07: IOMUXC1_UART2_TXD_GPIO_IO_GPIO1_IO07 { + pinmux = <0x443c018c 5 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpspi_sck_lpspi2_sck: IOMUXC1_UART2_TXD_LPSPI_SCK_LPSPI2_SCK { + pinmux = <0x443c018c 2 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_rts_b_lpuart1_rts_b: IOMUXC1_UART2_TXD_LPUART_RTS_B_LPUART1_RTS_B { + pinmux = <0x443c018c 1 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx: IOMUXC1_UART2_TXD_LPUART_TX_LPUART2_TX { + pinmux = <0x443c018c 0 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_tpm_ch_tpm1_ch3: IOMUXC1_UART2_TXD_TPM_CH_TPM1_CH3 { + pinmux = <0x443c018c 3 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_gpio_io_gpio1_io15: IOMUXC1_WDOG_ANY_GPIO_IO_GPIO1_IO15 { + pinmux = <0x443c01ac 5 0x0 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_wdog_wdog_any_wdog1_wdog_any: IOMUXC1_WDOG_ANY_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x443c01ac 0 0x0 0 0x443c035c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx9351dvvxm-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx9351dvvxm-pinctrl.dtsi new file mode 100644 index 000000000..b5e64a78f --- /dev/null +++ b/dts/nxp/nxp_imx/mimx9351dvvxm-pinctrl.dtsi @@ -0,0 +1,1831 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX9351DVVXM + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc1_ccm_clko1_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko1: IOMUXC1_CCM_CLKO1_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO1 { + pinmux = <0x443c0088 0 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_flexio_flexio_flexio1_flexio26: IOMUXC1_CCM_CLKO1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO26 { + pinmux = <0x443c0088 4 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_gpio_io_gpio3_io26: IOMUXC1_CCM_CLKO1_GPIO_IO_GPIO3_IO26 { + pinmux = <0x443c0088 5 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko2: IOMUXC1_CCM_CLKO2_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO2 { + pinmux = <0x443c008c 0 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_flexio_flexio_flexio1_flexio27: IOMUXC1_CCM_CLKO2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c008c 4 0x443c03c8 1 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_gpio_io_gpio3_io27: IOMUXC1_CCM_CLKO2_GPIO_IO_GPIO3_IO27 { + pinmux = <0x443c008c 5 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko3: IOMUXC1_CCM_CLKO3_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO3 { + pinmux = <0x443c0090 0 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_flexio_flexio_flexio2_flexio28: IOMUXC1_CCM_CLKO3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO28 { + pinmux = <0x443c0090 4 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_gpio_io_gpio4_io28: IOMUXC1_CCM_CLKO3_GPIO_IO_GPIO4_IO28 { + pinmux = <0x443c0090 5 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko4: IOMUXC1_CCM_CLKO4_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO4 { + pinmux = <0x443c0094 0 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_flexio_flexio_flexio2_flexio29: IOMUXC1_CCM_CLKO4_FLEXIO_FLEXIO_FLEXIO2_FLEXIO29 { + pinmux = <0x443c0094 4 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_gpio_io_gpio4_io29: IOMUXC1_CCM_CLKO4_GPIO_IO_GPIO4_IO29 { + pinmux = <0x443c0094 5 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_flexio_flexio_flexio1_flexio30: IOMUXC1_DAP_TCLK_SWCLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO30 { + pinmux = <0x443c0008 4 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30: IOMUXC1_DAP_TCLK_SWCLK_GPIO_IO_GPIO3_IO30 { + pinmux = <0x443c0008 5 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_jtag_mux_tck_jtag_mux_tck: IOMUXC1_DAP_TCLK_SWCLK_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0008 0 0x443c03d4 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_DAP_TCLK_SWCLK_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0008 6 0x443c042c 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_can_tx_can2_tx: IOMUXC1_DAP_TDI_CAN_TX_CAN2_TX { + pinmux = <0x443c0000 3 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_flexio_flexio_flexio2_flexio30: IOMUXC1_DAP_TDI_FLEXIO_FLEXIO_FLEXIO2_FLEXIO30 { + pinmux = <0x443c0000 4 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_gpio_io_gpio3_io28: IOMUXC1_DAP_TDI_GPIO_IO_GPIO3_IO28 { + pinmux = <0x443c0000 5 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_DAP_TDI_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0000 0 0x443c03d8 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_lpuart_rx_lpuart5_rx: IOMUXC1_DAP_TDI_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0000 6 0x443c0430 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_mqs_left_mqs2_left: IOMUXC1_DAP_TDI_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0000 1 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_can_rx_can2_rx: IOMUXC1_DAP_TDO_TRACESWO_CAN_RX_CAN2_RX { + pinmux = <0x443c000c 3 0x443c0364 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_flexio_flexio_flexio1_flexio31: IOMUXC1_DAP_TDO_TRACESWO_FLEXIO_FLEXIO_FLEXIO1_FLEXIO31 { + pinmux = <0x443c000c 4 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31: IOMUXC1_DAP_TDO_TRACESWO_GPIO_IO_GPIO3_IO31 { + pinmux = <0x443c000c 5 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_DAP_TDO_TRACESWO_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c000c 0 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_lpuart_tx_lpuart5_tx: IOMUXC1_DAP_TDO_TRACESWO_LPUART_TX_LPUART5_TX { + pinmux = <0x443c000c 6 0x443c0434 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_mqs_right_mqs2_right: IOMUXC1_DAP_TDO_TRACESWO_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c000c 1 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_flexio_flexio_flexio2_flexio31: IOMUXC1_DAP_TMS_SWDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO31 { + pinmux = <0x443c0004 4 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29: IOMUXC1_DAP_TMS_SWDIO_GPIO_IO_GPIO3_IO29 { + pinmux = <0x443c0004 5 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_jtag_mux_tms_jtag_mux_tms: IOMUXC1_DAP_TMS_SWDIO_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c0004 0 0x443c03dc 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_DAP_TMS_SWDIO_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c0004 6 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC1_ENET1_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x443c0098 0 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_flexio_flexio_flexio2_flexio00: IOMUXC1_ENET1_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO00 { + pinmux = <0x443c0098 4 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_gpio_io_gpio4_io00: IOMUXC1_ENET1_MDC_GPIO_IO_GPIO4_IO00 { + pinmux = <0x443c0098 5 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_hsiomix_otg_id_hsiomix_otg_id1: IOMUXC1_ENET1_MDC_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID1 { + pinmux = <0x443c0098 3 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_i3c_scl_i3c2_scl: IOMUXC1_ENET1_MDC_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0098 2 0x443c03cc 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_lpuart_dcb_b_lpuart3_dcb_b: IOMUXC1_ENET1_MDC_LPUART_DCB_B_LPUART3_DCB_B { + pinmux = <0x443c0098 1 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC1_ENET1_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x443c009c 0 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_flexio_flexio_flexio2_flexio01: IOMUXC1_ENET1_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO01 { + pinmux = <0x443c009c 4 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_gpio_io_gpio4_io01: IOMUXC1_ENET1_MDIO_GPIO_IO_GPIO4_IO01 { + pinmux = <0x443c009c 5 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_hsiomix_otg_pwr_hsiomix_otg_pwr1: IOMUXC1_ENET1_MDIO_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR1 { + pinmux = <0x443c009c 3 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_i3c_sda_i3c2_sda: IOMUXC1_ENET1_MDIO_I3C_SDA_I3C2_SDA { + pinmux = <0x443c009c 2 0x443c03d0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_lpuart_rin_b_lpuart3_rin_b: IOMUXC1_ENET1_MDIO_LPUART_RIN_B_LPUART3_RIN_B { + pinmux = <0x443c009c 1 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC1_ENET1_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x443c00c0 0 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_flexio_flexio_flexio2_flexio10: IOMUXC1_ENET1_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO10 { + pinmux = <0x443c00c0 4 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_gpio_io_gpio4_io10: IOMUXC1_ENET1_RD0_GPIO_IO_GPIO4_IO10 { + pinmux = <0x443c00c0 5 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_lpuart_rx_lpuart3_rx: IOMUXC1_ENET1_RD0_LPUART_RX_LPUART3_RX { + pinmux = <0x443c00c0 1 0x443c0418 1 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC1_ENET1_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x443c00c4 0 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_flexio_flexio_flexio2_flexio11: IOMUXC1_ENET1_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO11 { + pinmux = <0x443c00c4 4 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_gpio_io_gpio4_io11: IOMUXC1_ENET1_RD1_GPIO_IO_GPIO4_IO11 { + pinmux = <0x443c00c4 5 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lptmr_alt_lptmr2_alt1: IOMUXC1_ENET1_RD1_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c00c4 3 0x443c0408 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_ENET1_RD1_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c00c4 1 0x443c0414 1 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC1_ENET1_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x443c00c8 0 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_flexio_flexio_flexio2_flexio12: IOMUXC1_ENET1_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO12 { + pinmux = <0x443c00c8 4 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_gpio_io_gpio4_io12: IOMUXC1_ENET1_RD2_GPIO_IO_GPIO4_IO12 { + pinmux = <0x443c00c8 5 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_lptmr_alt_lptmr2_alt2: IOMUXC1_ENET1_RD2_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c00c8 3 0x443c040c 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC1_ENET1_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x443c00cc 0 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_flexio_flexio_flexio2_flexio13: IOMUXC1_ENET1_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO13 { + pinmux = <0x443c00cc 4 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_gpio_io_gpio4_io13: IOMUXC1_ENET1_RD3_GPIO_IO_GPIO4_IO13 { + pinmux = <0x443c00cc 5 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_lptmr_alt_lptmr2_alt3: IOMUXC1_ENET1_RD3_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c00cc 3 0x443c0410 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_ccm_enet_qos_clock_generate_rx_clk_ccm_enet_qos_clock_generate_rx_clk: IOMUXC1_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK { + pinmux = <0x443c00bc 0 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC1_ENET1_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x443c00bc 1 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_flexio_flexio_flexio2_flexio09: IOMUXC1_ENET1_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO09 { + pinmux = <0x443c00bc 4 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_gpio_io_gpio4_io09: IOMUXC1_ENET1_RXC_GPIO_IO_GPIO4_IO09 { + pinmux = <0x443c00bc 5 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC1_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x443c00b8 0 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_flexio_flexio_flexio2_flexio08: IOMUXC1_ENET1_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO08 { + pinmux = <0x443c00b8 4 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08: IOMUXC1_ENET1_RX_CTL_GPIO_IO_GPIO4_IO08 { + pinmux = <0x443c00b8 5 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_hsiomix_otg_pwr_hsiomix_otg_pwr2: IOMUXC1_ENET1_RX_CTL_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR2 { + pinmux = <0x443c00b8 3 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_lpuart_dsr_b_lpuart3_dsr_b: IOMUXC1_ENET1_RX_CTL_LPUART_DSR_B_LPUART3_DSR_B { + pinmux = <0x443c00b8 1 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC1_ENET1_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x443c00ac 0 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_flexio_flexio_flexio2_flexio05: IOMUXC1_ENET1_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO05 { + pinmux = <0x443c00ac 4 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_gpio_io_gpio4_io05: IOMUXC1_ENET1_TD0_GPIO_IO_GPIO4_IO05 { + pinmux = <0x443c00ac 5 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_lpuart_tx_lpuart3_tx: IOMUXC1_ENET1_TD0_LPUART_TX_LPUART3_TX { + pinmux = <0x443c00ac 1 0x443c041c 1 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC1_ENET1_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x443c00a8 0 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_flexio_flexio_flexio2_flexio04: IOMUXC1_ENET1_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO04 { + pinmux = <0x443c00a8 4 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_gpio_io_gpio4_io04: IOMUXC1_ENET1_TD1_GPIO_IO_GPIO4_IO04 { + pinmux = <0x443c00a8 5 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_hsiomix_otg_oc_hsiomix_otg_oc1: IOMUXC1_ENET1_TD1_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC1 { + pinmux = <0x443c00a8 3 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_b_i3c2_pur_b: IOMUXC1_ENET1_TD1_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c00a8 6 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_i3c2_pur: IOMUXC1_ENET1_TD1_I3C_PUR_I3C2_PUR { + pinmux = <0x443c00a8 2 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_ENET1_TD1_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c00a8 1 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_can_rx_can2_rx: IOMUXC1_ENET1_TD2_CAN_RX_CAN2_RX { + pinmux = <0x443c00a4 2 0x443c0364 2 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_ccm_enet_qos_clock_generate_ref_clk_ccm_enet_qos_clock_generate_ref_clk: IOMUXC1_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK { + pinmux = <0x443c00a4 1 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC1_ENET1_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x443c00a4 0 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_flexio_flexio_flexio2_flexio03: IOMUXC1_ENET1_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO03 { + pinmux = <0x443c00a4 4 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_gpio_io_gpio4_io03: IOMUXC1_ENET1_TD2_GPIO_IO_GPIO4_IO03 { + pinmux = <0x443c00a4 5 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_hsiomix_otg_oc_hsiomix_otg_oc2: IOMUXC1_ENET1_TD2_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC2 { + pinmux = <0x443c00a4 3 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_can_tx_can2_tx: IOMUXC1_ENET1_TD3_CAN_TX_CAN2_TX { + pinmux = <0x443c00a0 2 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC1_ENET1_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x443c00a0 0 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_flexio_flexio_flexio2_flexio02: IOMUXC1_ENET1_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO02 { + pinmux = <0x443c00a0 4 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_gpio_io_gpio4_io02: IOMUXC1_ENET1_TD3_GPIO_IO_GPIO4_IO02 { + pinmux = <0x443c00a0 5 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_hsiomix_otg_id_hsiomix_otg_id2: IOMUXC1_ENET1_TD3_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID2 { + pinmux = <0x443c00a0 3 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_ccm_enet_qos_clock_generate_tx_clk_ccm_enet_qos_clock_generate_tx_clk: IOMUXC1_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK { + pinmux = <0x443c00b4 0 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC1_ENET1_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x443c00b4 1 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_flexio_flexio_flexio2_flexio07: IOMUXC1_ENET1_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO07 { + pinmux = <0x443c00b4 4 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_gpio_io_gpio4_io07: IOMUXC1_ENET1_TXC_GPIO_IO_GPIO4_IO07 { + pinmux = <0x443c00b4 5 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC1_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x443c00b0 0 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_flexio_flexio_flexio2_flexio06: IOMUXC1_ENET1_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO06 { + pinmux = <0x443c00b0 4 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06: IOMUXC1_ENET1_TX_CTL_GPIO_IO_GPIO4_IO06 { + pinmux = <0x443c00b0 5 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_lpuart_dtr_b_lpuart3_dtr_b: IOMUXC1_ENET1_TX_CTL_LPUART_DTR_B_LPUART3_DTR_B { + pinmux = <0x443c00b0 1 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_enet_mdc_enet1_mdc: IOMUXC1_ENET2_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x443c00d0 0 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_flexio_flexio_flexio2_flexio14: IOMUXC1_ENET2_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO14 { + pinmux = <0x443c00d0 4 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_gpio_io_gpio4_io14: IOMUXC1_ENET2_MDC_GPIO_IO_GPIO4_IO14 { + pinmux = <0x443c00d0 5 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_lpuart_dcb_b_lpuart4_dcb_b: IOMUXC1_ENET2_MDC_LPUART_DCB_B_LPUART4_DCB_B { + pinmux = <0x443c00d0 1 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_sai_rx_sync_sai2_rx_sync: IOMUXC1_ENET2_MDC_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x443c00d0 2 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_enet_mdio_enet1_mdio: IOMUXC1_ENET2_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x443c00d4 0 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_flexio_flexio_flexio2_flexio15: IOMUXC1_ENET2_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO15 { + pinmux = <0x443c00d4 4 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_gpio_io_gpio4_io15: IOMUXC1_ENET2_MDIO_GPIO_IO_GPIO4_IO15 { + pinmux = <0x443c00d4 5 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_lpuart_rin_b_lpuart4_rin_b: IOMUXC1_ENET2_MDIO_LPUART_RIN_B_LPUART4_RIN_B { + pinmux = <0x443c00d4 1 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_sai_rx_bclk_sai2_rx_bclk: IOMUXC1_ENET2_MDIO_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x443c00d4 2 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC1_ENET2_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x443c00f8 0 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_flexio_flexio_flexio2_flexio24: IOMUXC1_ENET2_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO24 { + pinmux = <0x443c00f8 4 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_gpio_io_gpio4_io24: IOMUXC1_ENET2_RD0_GPIO_IO_GPIO4_IO24 { + pinmux = <0x443c00f8 5 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_lpuart_rx_lpuart4_rx: IOMUXC1_ENET2_RD0_LPUART_RX_LPUART4_RX { + pinmux = <0x443c00f8 1 0x443c0424 1 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_sai_tx_data_sai2_tx_data02: IOMUXC1_ENET2_RD0_SAI_TX_DATA_SAI2_TX_DATA02 { + pinmux = <0x443c00f8 2 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC1_ENET2_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x443c00fc 0 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_flexio_flexio_flexio2_flexio25: IOMUXC1_ENET2_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO25 { + pinmux = <0x443c00fc 4 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_gpio_io_gpio4_io25: IOMUXC1_ENET2_RD1_GPIO_IO_GPIO4_IO25 { + pinmux = <0x443c00fc 5 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_sai_tx_data_sai2_tx_data03: IOMUXC1_ENET2_RD1_SAI_TX_DATA_SAI2_TX_DATA03 { + pinmux = <0x443c00fc 2 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_spdif_in_spdif_in: IOMUXC1_ENET2_RD1_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c00fc 1 0x443c0454 1 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC1_ENET2_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x443c0100 0 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_flexio_flexio_flexio2_flexio26: IOMUXC1_ENET2_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO26 { + pinmux = <0x443c0100 4 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_gpio_io_gpio4_io26: IOMUXC1_ENET2_RD2_GPIO_IO_GPIO4_IO26 { + pinmux = <0x443c0100 5 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_ENET2_RD2_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0100 1 0x443c0420 1 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_mqs_right_mqs2_right: IOMUXC1_ENET2_RD2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0100 3 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_sai_mclk_sai2_mclk: IOMUXC1_ENET2_RD2_SAI_MCLK_SAI2_MCLK { + pinmux = <0x443c0100 2 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC1_ENET2_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x443c0104 0 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_flexio_flexio_flexio2_flexio27: IOMUXC1_ENET2_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO27 { + pinmux = <0x443c0104 4 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_gpio_io_gpio4_io27: IOMUXC1_ENET2_RD3_GPIO_IO_GPIO4_IO27 { + pinmux = <0x443c0104 5 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_mqs_left_mqs2_left: IOMUXC1_ENET2_RD3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0104 3 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_in_spdif_in: IOMUXC1_ENET2_RD3_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0104 2 0x443c0454 2 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_out_spdif_out: IOMUXC1_ENET2_RD3_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c0104 1 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC1_ENET2_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x443c00f4 0 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rx_er_enet1_rx_er: IOMUXC1_ENET2_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x443c00f4 1 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_flexio_flexio_flexio2_flexio23: IOMUXC1_ENET2_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO23 { + pinmux = <0x443c00f4 4 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_gpio_io_gpio4_io23: IOMUXC1_ENET2_RXC_GPIO_IO_GPIO4_IO23 { + pinmux = <0x443c00f4 5 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_sai_tx_data_sai2_tx_data01: IOMUXC1_ENET2_RXC_SAI_TX_DATA_SAI2_TX_DATA01 { + pinmux = <0x443c00f4 2 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC1_ENET2_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x443c00f0 0 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_flexio_flexio_flexio2_flexio22: IOMUXC1_ENET2_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO22 { + pinmux = <0x443c00f0 4 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22: IOMUXC1_ENET2_RX_CTL_GPIO_IO_GPIO4_IO22 { + pinmux = <0x443c00f0 5 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_lpuart_dsr_b_lpuart4_dsr_b: IOMUXC1_ENET2_RX_CTL_LPUART_DSR_B_LPUART4_DSR_B { + pinmux = <0x443c00f0 1 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_sai_tx_data_sai2_tx_data00: IOMUXC1_ENET2_RX_CTL_SAI_TX_DATA_SAI2_TX_DATA00 { + pinmux = <0x443c00f0 2 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC1_ENET2_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x443c00e4 0 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_flexio_flexio_flexio2_flexio19: IOMUXC1_ENET2_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO19 { + pinmux = <0x443c00e4 4 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_gpio_io_gpio4_io19: IOMUXC1_ENET2_TD0_GPIO_IO_GPIO4_IO19 { + pinmux = <0x443c00e4 5 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_lpuart_tx_lpuart4_tx: IOMUXC1_ENET2_TD0_LPUART_TX_LPUART4_TX { + pinmux = <0x443c00e4 1 0x443c0428 1 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_sai_rx_data_sai2_rx_data03: IOMUXC1_ENET2_TD0_SAI_RX_DATA_SAI2_RX_DATA03 { + pinmux = <0x443c00e4 2 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC1_ENET2_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x443c00e0 0 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_flexio_flexio_flexio2_flexio18: IOMUXC1_ENET2_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO18 { + pinmux = <0x443c00e0 4 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_gpio_io_gpio4_io18: IOMUXC1_ENET2_TD1_GPIO_IO_GPIO4_IO18 { + pinmux = <0x443c00e0 5 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_ENET2_TD1_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c00e0 1 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_sai_rx_data_sai2_rx_data02: IOMUXC1_ENET2_TD1_SAI_RX_DATA_SAI2_RX_DATA02 { + pinmux = <0x443c00e0 2 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC1_ENET2_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x443c00dc 0 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_tx_clk_enet1_tx_clk: IOMUXC1_ENET2_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x443c00dc 1 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_flexio_flexio_flexio2_flexio17: IOMUXC1_ENET2_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO17 { + pinmux = <0x443c00dc 4 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_gpio_io_gpio4_io17: IOMUXC1_ENET2_TD2_GPIO_IO_GPIO4_IO17 { + pinmux = <0x443c00dc 5 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_sai_rx_data_sai2_rx_data01: IOMUXC1_ENET2_TD2_SAI_RX_DATA_SAI2_RX_DATA01 { + pinmux = <0x443c00dc 2 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC1_ENET2_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x443c00d8 0 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_flexio_flexio_flexio2_flexio16: IOMUXC1_ENET2_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO16 { + pinmux = <0x443c00d8 4 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_gpio_io_gpio4_io16: IOMUXC1_ENET2_TD3_GPIO_IO_GPIO4_IO16 { + pinmux = <0x443c00d8 5 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_sai_rx_data_sai2_rx_data00: IOMUXC1_ENET2_TD3_SAI_RX_DATA_SAI2_RX_DATA00 { + pinmux = <0x443c00d8 2 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC1_ENET2_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x443c00ec 0 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_tx_er_enet1_tx_er: IOMUXC1_ENET2_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x443c00ec 1 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_flexio_flexio_flexio2_flexio21: IOMUXC1_ENET2_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO21 { + pinmux = <0x443c00ec 4 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_gpio_io_gpio4_io21: IOMUXC1_ENET2_TXC_GPIO_IO_GPIO4_IO21 { + pinmux = <0x443c00ec 5 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC1_ENET2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x443c00ec 2 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC1_ENET2_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x443c00e8 0 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_flexio_flexio_flexio2_flexio20: IOMUXC1_ENET2_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO20 { + pinmux = <0x443c00e8 4 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20: IOMUXC1_ENET2_TX_CTL_GPIO_IO_GPIO4_IO20 { + pinmux = <0x443c00e8 5 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_lpuart_dtr_b_lpuart4_dtr_b: IOMUXC1_ENET2_TX_CTL_LPUART_DTR_B_LPUART4_DTR_B { + pinmux = <0x443c00e8 1 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_sai_tx_sync_sai2_tx_sync: IOMUXC1_ENET2_TX_CTL_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x443c00e8 2 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_flexio_flexio_flexio1_flexio00: IOMUXC1_GPIO_IO00_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0010 7 0x443c036c 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_gpio_io_gpio2_io00: IOMUXC1_GPIO_IO00_GPIO_IO_GPIO2_IO00 { + pinmux = <0x443c0010 0 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0010 1 0x443c03e4 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0010 6 0x443c03ec 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpspi_pcs_lpspi6_pcs0: IOMUXC1_GPIO_IO00_LPSPI_PCS_LPSPI6_PCS0 { + pinmux = <0x443c0010 4 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpuart_tx_lpuart5_tx: IOMUXC1_GPIO_IO00_LPUART_TX_LPUART5_TX { + pinmux = <0x443c0010 5 0x443c0434 1 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_cam_clk_mediamix_cam_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_CAM_CLK_MEDIAMIX_CAM_CLK { + pinmux = <0x443c0010 2 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_disp_clk_mediamix_disp_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_DISP_CLK_MEDIAMIX_DISP_CLK { + pinmux = <0x443c0010 3 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_flexio_flexio_flexio1_flexio01: IOMUXC1_GPIO_IO01_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0014 7 0x443c0370 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_gpio_io_gpio2_io01: IOMUXC1_GPIO_IO01_GPIO_IO_GPIO2_IO01 { + pinmux = <0x443c0014 0 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0014 1 0x443c03e0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c0014 6 0x443c03e8 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpspi_sin_lpspi6_sin: IOMUXC1_GPIO_IO01_LPSPI_SIN_LPSPI6_SIN { + pinmux = <0x443c0014 4 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpuart_rx_lpuart5_rx: IOMUXC1_GPIO_IO01_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0014 5 0x443c0430 1 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_cam_data_mediamix_cam_data00: IOMUXC1_GPIO_IO01_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA00 { + pinmux = <0x443c0014 2 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_disp_de_mediamix_disp_de: IOMUXC1_GPIO_IO01_MEDIAMIX_DISP_DE_MEDIAMIX_DISP_DE { + pinmux = <0x443c0014 3 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_flexio_flexio_flexio1_flexio02: IOMUXC1_GPIO_IO02_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0018 7 0x443c0374 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_gpio_io_gpio2_io02: IOMUXC1_GPIO_IO02_GPIO_IO_GPIO2_IO02 { + pinmux = <0x443c0018 0 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C4_SDA { + pinmux = <0x443c0018 1 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0018 6 0x443c03f4 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpspi_sout_lpspi6_sout: IOMUXC1_GPIO_IO02_LPSPI_SOUT_LPSPI6_SOUT { + pinmux = <0x443c0018 4 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_GPIO_IO02_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0018 5 0x443c042c 1 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_cam_vsync_mediamix_cam_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_CAM_VSYNC_MEDIAMIX_CAM_VSYNC { + pinmux = <0x443c0018 2 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_disp_vsync_mediamix_disp_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_DISP_VSYNC_MEDIAMIX_DISP_VSYNC { + pinmux = <0x443c0018 3 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_flexio_flexio_flexio1_flexio03: IOMUXC1_GPIO_IO03_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c001c 7 0x443c0378 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_gpio_io_gpio2_io03: IOMUXC1_GPIO_IO03_GPIO_IO_GPIO2_IO03 { + pinmux = <0x443c001c 0 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C4_SCL { + pinmux = <0x443c001c 1 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c001c 6 0x443c03f0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpspi_sck_lpspi6_sck: IOMUXC1_GPIO_IO03_LPSPI_SCK_LPSPI6_SCK { + pinmux = <0x443c001c 4 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_GPIO_IO03_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c001c 5 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_cam_hsync_mediamix_cam_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_CAM_HSYNC_MEDIAMIX_CAM_HSYNC { + pinmux = <0x443c001c 2 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_disp_hsync_mediamix_disp_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_DISP_HSYNC_MEDIAMIX_DISP_HSYNC { + pinmux = <0x443c001c 3 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_flexio_flexio_flexio1_flexio04: IOMUXC1_GPIO_IO04_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0020 7 0x443c037c 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_gpio_io_gpio2_io04: IOMUXC1_GPIO_IO04_GPIO_IO_GPIO2_IO04 { + pinmux = <0x443c0020 0 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO04_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0020 6 0x443c03f4 1 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpspi_pcs_lpspi7_pcs0: IOMUXC1_GPIO_IO04_LPSPI_PCS_LPSPI7_PCS0 { + pinmux = <0x443c0020 4 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpuart_tx_lpuart6_tx: IOMUXC1_GPIO_IO04_LPUART_TX_LPUART6_TX { + pinmux = <0x443c0020 5 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_mediamix_disp_data_mediamix_disp_data00: IOMUXC1_GPIO_IO04_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA00 { + pinmux = <0x443c0020 3 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO04_PDM_CLK_PDM_CLK { + pinmux = <0x443c0020 2 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_tpm_ch_tpm3_ch0: IOMUXC1_GPIO_IO04_TPM_CH_TPM3_CH0 { + pinmux = <0x443c0020 1 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_flexio_flexio_flexio1_flexio05: IOMUXC1_GPIO_IO05_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0024 7 0x443c0380 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_gpio_io_gpio2_io05: IOMUXC1_GPIO_IO05_GPIO_IO_GPIO2_IO05 { + pinmux = <0x443c0024 0 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO05_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c0024 6 0x443c03f0 1 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpspi_sin_lpspi7_sin: IOMUXC1_GPIO_IO05_LPSPI_SIN_LPSPI7_SIN { + pinmux = <0x443c0024 4 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpuart_rx_lpuart6_rx: IOMUXC1_GPIO_IO05_LPUART_RX_LPUART6_RX { + pinmux = <0x443c0024 5 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_mediamix_disp_data_mediamix_disp_data01: IOMUXC1_GPIO_IO05_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA01 { + pinmux = <0x443c0024 3 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO05_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0024 2 0x443c0438 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_tpm_ch_tpm4_ch0: IOMUXC1_GPIO_IO05_TPM_CH_TPM4_CH0 { + pinmux = <0x443c0024 1 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_flexio_flexio_flexio1_flexio06: IOMUXC1_GPIO_IO06_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0028 7 0x443c0384 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_gpio_io_gpio2_io06: IOMUXC1_GPIO_IO06_GPIO_IO_GPIO2_IO06 { + pinmux = <0x443c0028 0 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO06_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0028 6 0x443c03fc 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpspi_sout_lpspi7_sout: IOMUXC1_GPIO_IO06_LPSPI_SOUT_LPSPI7_SOUT { + pinmux = <0x443c0028 4 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpuart_cts_b_lpuart6_cts_b: IOMUXC1_GPIO_IO06_LPUART_CTS_B_LPUART6_CTS_B { + pinmux = <0x443c0028 5 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_mediamix_disp_data_mediamix_disp_data02: IOMUXC1_GPIO_IO06_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA02 { + pinmux = <0x443c0028 3 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO06_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0028 2 0x443c043c 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_tpm_ch_tpm5_ch0: IOMUXC1_GPIO_IO06_TPM_CH_TPM5_CH0 { + pinmux = <0x443c0028 1 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_flexio_flexio_flexio1_flexio07: IOMUXC1_GPIO_IO07_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c002c 7 0x443c0388 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_gpio_io_gpio2_io07: IOMUXC1_GPIO_IO07_GPIO_IO_GPIO2_IO07 { + pinmux = <0x443c002c 0 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO07_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c002c 6 0x443c03f8 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1: IOMUXC1_GPIO_IO07_LPSPI_PCS_LPSPI3_PCS1 { + pinmux = <0x443c002c 1 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_sck_lpspi7_sck: IOMUXC1_GPIO_IO07_LPSPI_SCK_LPSPI7_SCK { + pinmux = <0x443c002c 4 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpuart_rts_b_lpuart6_rts_b: IOMUXC1_GPIO_IO07_LPUART_RTS_B_LPUART6_RTS_B { + pinmux = <0x443c002c 5 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_cam_data_mediamix_cam_data01: IOMUXC1_GPIO_IO07_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA01 { + pinmux = <0x443c002c 2 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_disp_data_mediamix_disp_data03: IOMUXC1_GPIO_IO07_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA03 { + pinmux = <0x443c002c 3 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_flexio_flexio_flexio1_flexio08: IOMUXC1_GPIO_IO08_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0030 7 0x443c038c 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_gpio_io_gpio2_io08: IOMUXC1_GPIO_IO08_GPIO_IO_GPIO2_IO08 { + pinmux = <0x443c0030 0 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO08_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0030 6 0x443c03fc 1 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0: IOMUXC1_GPIO_IO08_LPSPI_PCS_LPSPI3_PCS0 { + pinmux = <0x443c0030 1 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpuart_tx_lpuart7_tx: IOMUXC1_GPIO_IO08_LPUART_TX_LPUART7_TX { + pinmux = <0x443c0030 5 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_cam_data_mediamix_cam_data02: IOMUXC1_GPIO_IO08_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA02 { + pinmux = <0x443c0030 2 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_disp_data_mediamix_disp_data04: IOMUXC1_GPIO_IO08_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA04 { + pinmux = <0x443c0030 3 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_tpm_ch_tpm6_ch0: IOMUXC1_GPIO_IO08_TPM_CH_TPM6_CH0 { + pinmux = <0x443c0030 4 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_flexio_flexio_flexio1_flexio09: IOMUXC1_GPIO_IO09_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c0034 7 0x443c0390 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_gpio_io_gpio2_io09: IOMUXC1_GPIO_IO09_GPIO_IO_GPIO2_IO09 { + pinmux = <0x443c0034 0 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO09_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c0034 6 0x443c03f8 1 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin: IOMUXC1_GPIO_IO09_LPSPI_SIN_LPSPI3_SIN { + pinmux = <0x443c0034 1 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpuart_rx_lpuart7_rx: IOMUXC1_GPIO_IO09_LPUART_RX_LPUART7_RX { + pinmux = <0x443c0034 5 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_cam_data_mediamix_cam_data03: IOMUXC1_GPIO_IO09_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA03 { + pinmux = <0x443c0034 2 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_disp_data_mediamix_disp_data05: IOMUXC1_GPIO_IO09_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA05 { + pinmux = <0x443c0034 3 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_tpm_extclk_tpm3_extclk: IOMUXC1_GPIO_IO09_TPM_EXTCLK_TPM3_EXTCLK { + pinmux = <0x443c0034 4 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_flexio_flexio_flexio1_flexio10: IOMUXC1_GPIO_IO10_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0038 7 0x443c0394 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_gpio_io_gpio2_io10: IOMUXC1_GPIO_IO10_GPIO_IO_GPIO2_IO10 { + pinmux = <0x443c0038 0 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO10_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0038 6 0x443c0404 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout: IOMUXC1_GPIO_IO10_LPSPI_SOUT_LPSPI3_SOUT { + pinmux = <0x443c0038 1 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpuart_cts_b_lpuart7_cts_b: IOMUXC1_GPIO_IO10_LPUART_CTS_B_LPUART7_CTS_B { + pinmux = <0x443c0038 5 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_cam_data_mediamix_cam_data04: IOMUXC1_GPIO_IO10_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA04 { + pinmux = <0x443c0038 2 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_disp_data_mediamix_disp_data06: IOMUXC1_GPIO_IO10_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA06 { + pinmux = <0x443c0038 3 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_tpm_extclk_tpm4_extclk: IOMUXC1_GPIO_IO10_TPM_EXTCLK_TPM4_EXTCLK { + pinmux = <0x443c0038 4 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_flexio_flexio_flexio1_flexio11: IOMUXC1_GPIO_IO11_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c003c 7 0x443c0398 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_gpio_io_gpio2_io11: IOMUXC1_GPIO_IO11_GPIO_IO_GPIO2_IO11 { + pinmux = <0x443c003c 0 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO11_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c003c 6 0x443c0400 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck: IOMUXC1_GPIO_IO11_LPSPI_SCK_LPSPI3_SCK { + pinmux = <0x443c003c 1 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpuart_rts_b_lpuart7_rts_b: IOMUXC1_GPIO_IO11_LPUART_RTS_B_LPUART7_RTS_B { + pinmux = <0x443c003c 5 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_cam_data_mediamix_cam_data05: IOMUXC1_GPIO_IO11_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA05 { + pinmux = <0x443c003c 2 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_disp_data_mediamix_disp_data07: IOMUXC1_GPIO_IO11_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA07 { + pinmux = <0x443c003c 3 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_tpm_extclk_tpm5_extclk: IOMUXC1_GPIO_IO11_TPM_EXTCLK_TPM5_EXTCLK { + pinmux = <0x443c003c 4 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_gpio_io_gpio2_io12: IOMUXC1_GPIO_IO12_GPIO_IO_GPIO2_IO12 { + pinmux = <0x443c0040 0 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO12_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0040 6 0x443c0404 1 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpspi_pcs_lpspi8_pcs0: IOMUXC1_GPIO_IO12_LPSPI_PCS_LPSPI8_PCS0 { + pinmux = <0x443c0040 4 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpuart_tx_lpuart8_tx: IOMUXC1_GPIO_IO12_LPUART_TX_LPUART8_TX { + pinmux = <0x443c0040 5 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_mediamix_disp_data_mediamix_disp_data08: IOMUXC1_GPIO_IO12_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA08 { + pinmux = <0x443c0040 3 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO12_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0040 2 0x443c0440 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO12_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c0040 7 0x443c0450 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_tpm_ch_tpm3_ch2: IOMUXC1_GPIO_IO12_TPM_CH_TPM3_CH2 { + pinmux = <0x443c0040 1 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_flexio_flexio_flexio1_flexio13: IOMUXC1_GPIO_IO13_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c0044 7 0x443c039c 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_gpio_io_gpio2_io13: IOMUXC1_GPIO_IO13_GPIO_IO_GPIO2_IO13 { + pinmux = <0x443c0044 0 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO13_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c0044 6 0x443c0400 1 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpspi_sin_lpspi8_sin: IOMUXC1_GPIO_IO13_LPSPI_SIN_LPSPI8_SIN { + pinmux = <0x443c0044 4 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpuart_rx_lpuart8_rx: IOMUXC1_GPIO_IO13_LPUART_RX_LPUART8_RX { + pinmux = <0x443c0044 5 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_mediamix_disp_data_mediamix_disp_data09: IOMUXC1_GPIO_IO13_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA09 { + pinmux = <0x443c0044 3 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO13_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c0044 2 0x443c0444 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_tpm_ch_tpm4_ch2: IOMUXC1_GPIO_IO13_TPM_CH_TPM4_CH2 { + pinmux = <0x443c0044 1 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_flexio_flexio_flexio1_flexio14: IOMUXC1_GPIO_IO14_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0048 7 0x443c03a0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_gpio_io_gpio2_io14: IOMUXC1_GPIO_IO14_GPIO_IO_GPIO2_IO14 { + pinmux = <0x443c0048 0 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpspi_sout_lpspi8_sout: IOMUXC1_GPIO_IO14_LPSPI_SOUT_LPSPI8_SOUT { + pinmux = <0x443c0048 4 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_cts_b_lpuart8_cts_b: IOMUXC1_GPIO_IO14_LPUART_CTS_B_LPUART8_CTS_B { + pinmux = <0x443c0048 5 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart3_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART3_TX { + pinmux = <0x443c0048 1 0x443c041c 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart4_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART4_TX { + pinmux = <0x443c0048 6 0x443c0428 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_cam_data_mediamix_cam_data06: IOMUXC1_GPIO_IO14_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA06 { + pinmux = <0x443c0048 2 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_disp_data_mediamix_disp_data10: IOMUXC1_GPIO_IO14_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA10 { + pinmux = <0x443c0048 3 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_flexio_flexio_flexio1_flexio15: IOMUXC1_GPIO_IO15_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c004c 7 0x443c03a4 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_gpio_io_gpio2_io15: IOMUXC1_GPIO_IO15_GPIO_IO_GPIO2_IO15 { + pinmux = <0x443c004c 0 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpspi_sck_lpspi8_sck: IOMUXC1_GPIO_IO15_LPSPI_SCK_LPSPI8_SCK { + pinmux = <0x443c004c 4 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rts_b_lpuart8_rts_b: IOMUXC1_GPIO_IO15_LPUART_RTS_B_LPUART8_RTS_B { + pinmux = <0x443c004c 5 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart3_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART3_RX { + pinmux = <0x443c004c 1 0x443c0418 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart4_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART4_RX { + pinmux = <0x443c004c 6 0x443c0424 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_cam_data_mediamix_cam_data07: IOMUXC1_GPIO_IO15_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA07 { + pinmux = <0x443c004c 2 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_disp_data_mediamix_disp_data11: IOMUXC1_GPIO_IO15_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA11 { + pinmux = <0x443c004c 3 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_flexio_flexio_flexio1_flexio16: IOMUXC1_GPIO_IO16_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0050 7 0x443c03a8 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_gpio_io_gpio2_io16: IOMUXC1_GPIO_IO16_GPIO_IO_GPIO2_IO16 { + pinmux = <0x443c0050 0 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpspi_pcs_lpspi4_pcs2: IOMUXC1_GPIO_IO16_LPSPI_PCS_LPSPI4_PCS2 { + pinmux = <0x443c0050 5 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c0050 4 0x443c0414 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0050 6 0x443c0420 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_mediamix_disp_data_mediamix_disp_data12: IOMUXC1_GPIO_IO16_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA12 { + pinmux = <0x443c0050 3 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO16_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0050 2 0x443c0440 1 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk: IOMUXC1_GPIO_IO16_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x443c0050 1 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_flexio_flexio_flexio1_flexio17: IOMUXC1_GPIO_IO17_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c0054 7 0x443c03ac 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_gpio_io_gpio2_io17: IOMUXC1_GPIO_IO17_GPIO_IO_GPIO2_IO17 { + pinmux = <0x443c0054 0 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpspi_pcs_lpspi4_pcs1: IOMUXC1_GPIO_IO17_LPSPI_PCS_LPSPI4_PCS1 { + pinmux = <0x443c0054 5 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c0054 4 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c0054 6 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_cam_data_mediamix_cam_data08: IOMUXC1_GPIO_IO17_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA08 { + pinmux = <0x443c0054 2 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_disp_data_mediamix_disp_data13: IOMUXC1_GPIO_IO17_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA13 { + pinmux = <0x443c0054 3 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_sai_mclk_sai3_mclk: IOMUXC1_GPIO_IO17_SAI_MCLK_SAI3_MCLK { + pinmux = <0x443c0054 1 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_flexio_flexio_flexio1_flexio18: IOMUXC1_GPIO_IO18_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0058 7 0x443c03b0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_gpio_io_gpio2_io18: IOMUXC1_GPIO_IO18_GPIO_IO_GPIO2_IO18 { + pinmux = <0x443c0058 0 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi4_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI4_PCS0 { + pinmux = <0x443c0058 5 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi5_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI5_PCS0 { + pinmux = <0x443c0058 4 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_cam_data_mediamix_cam_data09: IOMUXC1_GPIO_IO18_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA09 { + pinmux = <0x443c0058 2 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_disp_data_mediamix_disp_data14: IOMUXC1_GPIO_IO18_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA14 { + pinmux = <0x443c0058 3 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO18_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0058 1 0x443c044c 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_tpm_ch_tpm5_ch2: IOMUXC1_GPIO_IO18_TPM_CH_TPM5_CH2 { + pinmux = <0x443c0058 6 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_gpio_io_gpio2_io19: IOMUXC1_GPIO_IO19_GPIO_IO_GPIO2_IO19 { + pinmux = <0x443c005c 0 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi4_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI4_SIN { + pinmux = <0x443c005c 5 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi5_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI5_SIN { + pinmux = <0x443c005c 4 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_mediamix_disp_data_mediamix_disp_data15: IOMUXC1_GPIO_IO19_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA15 { + pinmux = <0x443c005c 3 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO19_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c005c 2 0x443c0444 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO19_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c005c 1 0x443c0450 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO19_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c005c 7 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_tpm_ch_tpm6_ch2: IOMUXC1_GPIO_IO19_TPM_CH_TPM6_CH2 { + pinmux = <0x443c005c 6 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_flexio_flexio_flexio1_flexio20: IOMUXC1_GPIO_IO20_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0060 7 0x443c03b4 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_gpio_io_gpio2_io20: IOMUXC1_GPIO_IO20_GPIO_IO_GPIO2_IO20 { + pinmux = <0x443c0060 0 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi4_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI4_SOUT { + pinmux = <0x443c0060 5 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi5_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI5_SOUT { + pinmux = <0x443c0060 4 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_mediamix_disp_data_mediamix_disp_data16: IOMUXC1_GPIO_IO20_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA16 { + pinmux = <0x443c0060 3 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO20_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0060 2 0x443c0438 1 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data00: IOMUXC1_GPIO_IO20_SAI_RX_DATA_SAI3_RX_DATA00 { + pinmux = <0x443c0060 1 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_tpm_ch_tpm3_ch1: IOMUXC1_GPIO_IO20_TPM_CH_TPM3_CH1 { + pinmux = <0x443c0060 6 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_gpio_io_gpio2_io21: IOMUXC1_GPIO_IO21_GPIO_IO_GPIO2_IO21 { + pinmux = <0x443c0064 0 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi4_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI4_SCK { + pinmux = <0x443c0064 5 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi5_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI5_SCK { + pinmux = <0x443c0064 4 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_mediamix_disp_data_mediamix_disp_data17: IOMUXC1_GPIO_IO21_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA17 { + pinmux = <0x443c0064 3 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO21_PDM_CLK_PDM_CLK { + pinmux = <0x443c0064 2 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO21_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0064 7 0x443c044c 1 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO21_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c0064 1 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_tpm_ch_tpm4_ch1: IOMUXC1_GPIO_IO21_TPM_CH_TPM4_CH1 { + pinmux = <0x443c0064 6 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_flexio_flexio_flexio1_flexio22: IOMUXC1_GPIO_IO22_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0068 7 0x443c03b8 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_gpio_io_gpio2_io22: IOMUXC1_GPIO_IO22_GPIO_IO_GPIO2_IO22 { + pinmux = <0x443c0068 0 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO22_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0068 6 0x443c03ec 1 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_mediamix_disp_data_mediamix_disp_data18: IOMUXC1_GPIO_IO22_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA18 { + pinmux = <0x443c0068 3 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_spdif_in_spdif_in: IOMUXC1_GPIO_IO22_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0068 2 0x443c0454 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_ch_tpm5_ch1: IOMUXC1_GPIO_IO22_TPM_CH_TPM5_CH1 { + pinmux = <0x443c0068 4 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_extclk_tpm6_extclk: IOMUXC1_GPIO_IO22_TPM_EXTCLK_TPM6_EXTCLK { + pinmux = <0x443c0068 5 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_usdhc_clk_usdhc3_clk: IOMUXC1_GPIO_IO22_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0068 1 0x443c0458 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_flexio_flexio_flexio1_flexio23: IOMUXC1_GPIO_IO23_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c006c 7 0x443c03bc 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_gpio_io_gpio2_io23: IOMUXC1_GPIO_IO23_GPIO_IO_GPIO2_IO23 { + pinmux = <0x443c006c 0 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO23_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c006c 6 0x443c03e8 1 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_mediamix_disp_data_mediamix_disp_data19: IOMUXC1_GPIO_IO23_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA19 { + pinmux = <0x443c006c 3 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_spdif_out_spdif_out: IOMUXC1_GPIO_IO23_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c006c 2 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_tpm_ch_tpm6_ch1: IOMUXC1_GPIO_IO23_TPM_CH_TPM6_CH1 { + pinmux = <0x443c006c 4 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_usdhc_cmd_usdhc3_cmd: IOMUXC1_GPIO_IO23_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c006c 1 0x443c045c 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_flexio_flexio_flexio1_flexio24: IOMUXC1_GPIO_IO24_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0070 7 0x443c03c0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_gpio_io_gpio2_io24: IOMUXC1_GPIO_IO24_GPIO_IO_GPIO2_IO24 { + pinmux = <0x443c0070 0 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_GPIO_IO24_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c0070 5 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_lpspi_pcs_lpspi6_pcs1: IOMUXC1_GPIO_IO24_LPSPI_PCS_LPSPI6_PCS1 { + pinmux = <0x443c0070 6 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_mediamix_disp_data_mediamix_disp_data20: IOMUXC1_GPIO_IO24_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA20 { + pinmux = <0x443c0070 3 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_tpm_ch_tpm3_ch3: IOMUXC1_GPIO_IO24_TPM_CH_TPM3_CH3 { + pinmux = <0x443c0070 4 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_usdhc_data_usdhc3_data0: IOMUXC1_GPIO_IO24_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0070 1 0x443c0460 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_can_tx_can2_tx: IOMUXC1_GPIO_IO25_CAN_TX_CAN2_TX { + pinmux = <0x443c0074 2 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_flexio_flexio_flexio1_flexio25: IOMUXC1_GPIO_IO25_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c0074 7 0x443c03c4 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_gpio_io_gpio2_io25: IOMUXC1_GPIO_IO25_GPIO_IO_GPIO2_IO25 { + pinmux = <0x443c0074 0 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_jtag_mux_tck_jtag_mux_tck: IOMUXC1_GPIO_IO25_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0074 5 0x443c03d4 1 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_lpspi_pcs_lpspi7_pcs1: IOMUXC1_GPIO_IO25_LPSPI_PCS_LPSPI7_PCS1 { + pinmux = <0x443c0074 6 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_mediamix_disp_data_mediamix_disp_data21: IOMUXC1_GPIO_IO25_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA21 { + pinmux = <0x443c0074 3 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_tpm_ch_tpm4_ch3: IOMUXC1_GPIO_IO25_TPM_CH_TPM4_CH3 { + pinmux = <0x443c0074 4 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_usdhc_data_usdhc3_data1: IOMUXC1_GPIO_IO25_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0074 1 0x443c0464 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_gpio_io_gpio2_io26: IOMUXC1_GPIO_IO26_GPIO_IO_GPIO2_IO26 { + pinmux = <0x443c0078 0 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_GPIO_IO26_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0078 5 0x443c03d8 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_lpspi_pcs_lpspi8_pcs1: IOMUXC1_GPIO_IO26_LPSPI_PCS_LPSPI8_PCS1 { + pinmux = <0x443c0078 6 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_mediamix_disp_data_mediamix_disp_data22: IOMUXC1_GPIO_IO26_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA22 { + pinmux = <0x443c0078 3 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO26_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0078 2 0x443c043c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync: IOMUXC1_GPIO_IO26_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x443c0078 7 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_tpm_ch_tpm5_ch3: IOMUXC1_GPIO_IO26_TPM_CH_TPM5_CH3 { + pinmux = <0x443c0078 4 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_usdhc_data_usdhc3_data2: IOMUXC1_GPIO_IO26_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0078 1 0x443c0468 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_can_rx_can2_rx: IOMUXC1_GPIO_IO27_CAN_RX_CAN2_RX { + pinmux = <0x443c007c 2 0x443c0364 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_flexio_flexio_flexio1_flexio27: IOMUXC1_GPIO_IO27_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c007c 7 0x443c03c8 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_gpio_io_gpio2_io27: IOMUXC1_GPIO_IO27_GPIO_IO_GPIO2_IO27 { + pinmux = <0x443c007c 0 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_jtag_mux_tms_jtag_mux_tms: IOMUXC1_GPIO_IO27_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c007c 5 0x443c03dc 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_lpspi_pcs_lpspi5_pcs1: IOMUXC1_GPIO_IO27_LPSPI_PCS_LPSPI5_PCS1 { + pinmux = <0x443c007c 6 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_mediamix_disp_data_mediamix_disp_data23: IOMUXC1_GPIO_IO27_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA23 { + pinmux = <0x443c007c 3 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_tpm_ch_tpm6_ch3: IOMUXC1_GPIO_IO27_TPM_CH_TPM6_CH3 { + pinmux = <0x443c007c 4 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_usdhc_data_usdhc3_data3: IOMUXC1_GPIO_IO27_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c007c 1 0x443c046c 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_flexio_flexio_flexio1_flexio28: IOMUXC1_GPIO_IO28_FLEXIO_FLEXIO_FLEXIO1_FLEXIO28 { + pinmux = <0x443c0080 7 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_gpio_io_gpio2_io28: IOMUXC1_GPIO_IO28_GPIO_IO_GPIO2_IO28 { + pinmux = <0x443c0080 0 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO28_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0080 1 0x443c03e4 1 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_flexio_flexio_flexio1_flexio29: IOMUXC1_GPIO_IO29_FLEXIO_FLEXIO_FLEXIO1_FLEXIO29 { + pinmux = <0x443c0084 7 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_gpio_io_gpio2_io29: IOMUXC1_GPIO_IO29_GPIO_IO_GPIO2_IO29 { + pinmux = <0x443c0084 0 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO29_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0084 1 0x443c03e0 1 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_gpio_io_gpio1_io00: IOMUXC1_I2C1_SCL_GPIO_IO_GPIO1_IO00 { + pinmux = <0x443c0170 5 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_i3c_scl_i3c1_scl: IOMUXC1_I2C1_SCL_I3C_SCL_I3C1_SCL { + pinmux = <0x443c0170 1 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl: IOMUXC1_I2C1_SCL_LPI2C_SCL_LPI2C1_SCL { + pinmux = <0x443c0170 0 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpuart_dcb_b_lpuart1_dcb_b: IOMUXC1_I2C1_SCL_LPUART_DCB_B_LPUART1_DCB_B { + pinmux = <0x443c0170 2 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_tpm_ch_tpm2_ch0: IOMUXC1_I2C1_SCL_TPM_CH_TPM2_CH0 { + pinmux = <0x443c0170 3 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_gpio_io_gpio1_io01: IOMUXC1_I2C1_SDA_GPIO_IO_GPIO1_IO01 { + pinmux = <0x443c0174 5 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_i3c_sda_i3c1_sda: IOMUXC1_I2C1_SDA_I3C_SDA_I3C1_SDA { + pinmux = <0x443c0174 1 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda: IOMUXC1_I2C1_SDA_LPI2C_SDA_LPI2C1_SDA { + pinmux = <0x443c0174 0 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpuart_rin_b_lpuart1_rin_b: IOMUXC1_I2C1_SDA_LPUART_RIN_B_LPUART1_RIN_B { + pinmux = <0x443c0174 2 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_tpm_ch_tpm2_ch1: IOMUXC1_I2C1_SDA_TPM_CH_TPM2_CH1 { + pinmux = <0x443c0174 3 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_gpio_io_gpio1_io02: IOMUXC1_I2C2_SCL_GPIO_IO_GPIO1_IO02 { + pinmux = <0x443c0178 5 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_b_i3c1_pur_b: IOMUXC1_I2C2_SCL_I3C_PUR_B_I3C1_PUR_B { + pinmux = <0x443c0178 6 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_i3c1_pur: IOMUXC1_I2C2_SCL_I3C_PUR_I3C1_PUR { + pinmux = <0x443c0178 1 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl: IOMUXC1_I2C2_SCL_LPI2C_SCL_LPI2C2_SCL { + pinmux = <0x443c0178 0 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpuart_dcb_b_lpuart2_dcb_b: IOMUXC1_I2C2_SCL_LPUART_DCB_B_LPUART2_DCB_B { + pinmux = <0x443c0178 2 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_sai_rx_sync_sai1_rx_sync: IOMUXC1_I2C2_SCL_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x443c0178 4 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_tpm_ch_tpm2_ch2: IOMUXC1_I2C2_SCL_TPM_CH_TPM2_CH2 { + pinmux = <0x443c0178 3 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_gpio_io_gpio1_io03: IOMUXC1_I2C2_SDA_GPIO_IO_GPIO1_IO03 { + pinmux = <0x443c017c 5 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda: IOMUXC1_I2C2_SDA_LPI2C_SDA_LPI2C2_SDA { + pinmux = <0x443c017c 0 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpuart_rin_b_lpuart2_rin_b: IOMUXC1_I2C2_SDA_LPUART_RIN_B_LPUART2_RIN_B { + pinmux = <0x443c017c 2 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_sai_rx_bclk_sai1_rx_bclk: IOMUXC1_I2C2_SDA_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x443c017c 4 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_tpm_ch_tpm2_ch3: IOMUXC1_I2C2_SDA_TPM_CH_TPM2_CH3 { + pinmux = <0x443c017c 3 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_can_rx_can1_rx: IOMUXC1_PDM_BIT_STREAM0_CAN_RX_CAN1_RX { + pinmux = <0x443c0194 6 0x443c0360 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09: IOMUXC1_PDM_BIT_STREAM0_GPIO_IO_GPIO1_IO09 { + pinmux = <0x443c0194 5 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lpspi_pcs_lpspi1_pcs1: IOMUXC1_PDM_BIT_STREAM0_LPSPI_PCS_LPSPI1_PCS1 { + pinmux = <0x443c0194 2 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lptmr_alt_lptmr1_alt2: IOMUXC1_PDM_BIT_STREAM0_LPTMR_ALT_LPTMR1_ALT2 { + pinmux = <0x443c0194 4 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_mqs_right_mqs1_right: IOMUXC1_PDM_BIT_STREAM0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c0194 1 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_PDM_BIT_STREAM0_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0194 0 0x443c0438 2 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_tpm_extclk_tpm1_extclk: IOMUXC1_PDM_BIT_STREAM0_TPM_EXTCLK_TPM1_EXTCLK { + pinmux = <0x443c0194 3 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0198 6 0x443c0368 1 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10: IOMUXC1_PDM_BIT_STREAM1_GPIO_IO_GPIO1_IO10 { + pinmux = <0x443c0198 5 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lpspi_pcs_lpspi2_pcs1: IOMUXC1_PDM_BIT_STREAM1_LPSPI_PCS_LPSPI2_PCS1 { + pinmux = <0x443c0198 2 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lptmr_alt_lptmr1_alt3: IOMUXC1_PDM_BIT_STREAM1_LPTMR_ALT_LPTMR1_ALT3 { + pinmux = <0x443c0198 4 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_nmi_glue_nmi_nmi_glue_nmi: IOMUXC1_PDM_BIT_STREAM1_NMI_GLUE_NMI_NMI_GLUE_NMI { + pinmux = <0x443c0198 1 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_PDM_BIT_STREAM1_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0198 0 0x443c043c 2 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_tpm_extclk_tpm2_extclk: IOMUXC1_PDM_BIT_STREAM1_TPM_EXTCLK_TPM2_EXTCLK { + pinmux = <0x443c0198 3 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_can_tx_can1_tx: IOMUXC1_PDM_CLK_CAN_TX_CAN1_TX { + pinmux = <0x443c0190 6 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_gpio_io_gpio1_io08: IOMUXC1_PDM_CLK_GPIO_IO_GPIO1_IO08 { + pinmux = <0x443c0190 5 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_lptmr_alt_lptmr1_alt1: IOMUXC1_PDM_CLK_LPTMR_ALT_LPTMR1_ALT1 { + pinmux = <0x443c0190 4 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_mqs_left_mqs1_left: IOMUXC1_PDM_CLK_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c0190 1 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_pdm_clk_pdm_clk: IOMUXC1_PDM_CLK_PDM_CLK_PDM_CLK { + pinmux = <0x443c0190 0 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_gpio_io_gpio1_io14: IOMUXC1_SAI1_RXD0_GPIO_IO_GPIO1_IO14 { + pinmux = <0x443c01a8 5 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpspi_sout_lpspi1_sout: IOMUXC1_SAI1_RXD0_LPSPI_SOUT_LPSPI1_SOUT { + pinmux = <0x443c01a8 2 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpuart_dsr_b_lpuart2_dsr_b: IOMUXC1_SAI1_RXD0_LPUART_DSR_B_LPUART2_DSR_B { + pinmux = <0x443c01a8 3 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_mqs_right_mqs1_right: IOMUXC1_SAI1_RXD0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c01a8 4 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_mclk_sai1_mclk: IOMUXC1_SAI1_RXD0_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c01a8 1 0x443c0448 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_rx_data_sai1_rx_data00: IOMUXC1_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA00 { + pinmux = <0x443c01a8 0 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_can_rx_can1_rx: IOMUXC1_SAI1_TXC_CAN_RX_CAN1_RX { + pinmux = <0x443c01a0 4 0x443c0360 1 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_gpio_io_gpio1_io12: IOMUXC1_SAI1_TXC_GPIO_IO_GPIO1_IO12 { + pinmux = <0x443c01a0 5 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpspi_sin_lpspi1_sin: IOMUXC1_SAI1_TXC_LPSPI_SIN_LPSPI1_SIN { + pinmux = <0x443c01a0 2 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_cts_b_lpuart2_cts_b: IOMUXC1_SAI1_TXC_LPUART_CTS_B_LPUART2_CTS_B { + pinmux = <0x443c01a0 1 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_dsr_b_lpuart1_dsr_b: IOMUXC1_SAI1_TXC_LPUART_DSR_B_LPUART1_DSR_B { + pinmux = <0x443c01a0 3 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC1_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x443c01a0 0 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_can_tx_can1_tx: IOMUXC1_SAI1_TXD0_CAN_TX_CAN1_TX { + pinmux = <0x443c01a4 4 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_gpio_io_gpio1_io13: IOMUXC1_SAI1_TXD0_GPIO_IO_GPIO1_IO13 { + pinmux = <0x443c01a4 5 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpspi_sck_lpspi1_sck: IOMUXC1_SAI1_TXD0_LPSPI_SCK_LPSPI1_SCK { + pinmux = <0x443c01a4 2 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_dtr_b_lpuart1_dtr_b: IOMUXC1_SAI1_TXD0_LPUART_DTR_B_LPUART1_DTR_B { + pinmux = <0x443c01a4 3 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_rts_b_lpuart2_rts_b: IOMUXC1_SAI1_TXD0_LPUART_RTS_B_LPUART2_RTS_B { + pinmux = <0x443c01a4 1 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_sai_tx_data_sai1_tx_data00: IOMUXC1_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA00 { + pinmux = <0x443c01a4 0 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_gpio_io_gpio1_io11: IOMUXC1_SAI1_TXFS_GPIO_IO_GPIO1_IO11 { + pinmux = <0x443c019c 5 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpspi_pcs_lpspi1_pcs0: IOMUXC1_SAI1_TXFS_LPSPI_PCS_LPSPI1_PCS0 { + pinmux = <0x443c019c 2 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpuart_dtr_b_lpuart2_dtr_b: IOMUXC1_SAI1_TXFS_LPUART_DTR_B_LPUART2_DTR_B { + pinmux = <0x443c019c 3 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_mqs_left_mqs1_left: IOMUXC1_SAI1_TXFS_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c019c 4 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_data_sai1_tx_data01: IOMUXC1_SAI1_TXFS_SAI_TX_DATA_SAI1_TX_DATA01 { + pinmux = <0x443c019c 1 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC1_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x443c019c 0 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_flexio_flexio_flexio1_flexio08: IOMUXC1_SD1_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0108 4 0x443c038c 1 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_gpio_io_gpio3_io08: IOMUXC1_SD1_CLK_GPIO_IO_GPIO3_IO08 { + pinmux = <0x443c0108 5 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC1_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x443c0108 0 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_flexio_flexio_flexio1_flexio09: IOMUXC1_SD1_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c010c 4 0x443c0390 1 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_gpio_io_gpio3_io09: IOMUXC1_SD1_CMD_GPIO_IO_GPIO3_IO09 { + pinmux = <0x443c010c 5 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC1_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x443c010c 0 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_flexio_flexio_flexio1_flexio10: IOMUXC1_SD1_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0110 4 0x443c0394 1 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_gpio_io_gpio3_io10: IOMUXC1_SD1_DATA0_GPIO_IO_GPIO3_IO10 { + pinmux = <0x443c0110 5 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC1_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x443c0110 0 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_flexio_flexio_flexio1_flexio11: IOMUXC1_SD1_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c0114 4 0x443c0398 1 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_gpio_io_gpio3_io11: IOMUXC1_SD1_DATA1_GPIO_IO_GPIO3_IO11 { + pinmux = <0x443c0114 5 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC1_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x443c0114 0 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_flexio_flexio_flexio1_flexio12: IOMUXC1_SD1_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO12 { + pinmux = <0x443c0118 4 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_gpio_io_gpio3_io12: IOMUXC1_SD1_DATA2_GPIO_IO_GPIO3_IO12 { + pinmux = <0x443c0118 5 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC1_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x443c0118 0 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexio_flexio_flexio1_flexio13: IOMUXC1_SD1_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c011c 4 0x443c039c 1 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexspi_a_ss_b_flexspi1_a_ss1_b: IOMUXC1_SD1_DATA3_FLEXSPI_A_SS_B_FLEXSPI1_A_SS1_B { + pinmux = <0x443c011c 1 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_gpio_io_gpio3_io13: IOMUXC1_SD1_DATA3_GPIO_IO_GPIO3_IO13 { + pinmux = <0x443c011c 5 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC1_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x443c011c 0 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexio_flexio_flexio1_flexio14: IOMUXC1_SD1_DATA4_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0120 4 0x443c03a0 1 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexspi_a_data_flexspi1_a_data04: IOMUXC1_SD1_DATA4_FLEXSPI_A_DATA_FLEXSPI1_A_DATA04 { + pinmux = <0x443c0120 1 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_gpio_io_gpio3_io14: IOMUXC1_SD1_DATA4_GPIO_IO_GPIO3_IO14 { + pinmux = <0x443c0120 5 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC1_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x443c0120 0 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexio_flexio_flexio1_flexio15: IOMUXC1_SD1_DATA5_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c0124 4 0x443c03a4 1 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexspi_a_data_flexspi1_a_data05: IOMUXC1_SD1_DATA5_FLEXSPI_A_DATA_FLEXSPI1_A_DATA05 { + pinmux = <0x443c0124 1 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_gpio_io_gpio3_io15: IOMUXC1_SD1_DATA5_GPIO_IO_GPIO3_IO15 { + pinmux = <0x443c0124 5 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC1_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x443c0124 0 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_reset_b_usdhc1_reset_b: IOMUXC1_SD1_DATA5_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x443c0124 2 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexio_flexio_flexio1_flexio16: IOMUXC1_SD1_DATA6_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0128 4 0x443c03a8 1 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexspi_a_data_flexspi1_a_data06: IOMUXC1_SD1_DATA6_FLEXSPI_A_DATA_FLEXSPI1_A_DATA06 { + pinmux = <0x443c0128 1 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_gpio_io_gpio3_io16: IOMUXC1_SD1_DATA6_GPIO_IO_GPIO3_IO16 { + pinmux = <0x443c0128 5 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_cd_b_usdhc1_cd_b: IOMUXC1_SD1_DATA6_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x443c0128 2 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC1_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x443c0128 0 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexio_flexio_flexio1_flexio17: IOMUXC1_SD1_DATA7_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c012c 4 0x443c03ac 1 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexspi_a_data_flexspi1_a_data07: IOMUXC1_SD1_DATA7_FLEXSPI_A_DATA_FLEXSPI1_A_DATA07 { + pinmux = <0x443c012c 1 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_gpio_io_gpio3_io17: IOMUXC1_SD1_DATA7_GPIO_IO_GPIO3_IO17 { + pinmux = <0x443c012c 5 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC1_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x443c012c 0 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_wp_usdhc1_wp: IOMUXC1_SD1_DATA7_USDHC_WP_USDHC1_WP { + pinmux = <0x443c012c 2 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexio_flexio_flexio1_flexio18: IOMUXC1_SD1_STROBE_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0130 4 0x443c03b0 1 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexspi_a_dqs_flexspi1_a_dqs: IOMUXC1_SD1_STROBE_FLEXSPI_A_DQS_FLEXSPI1_A_DQS { + pinmux = <0x443c0130 1 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_gpio_io_gpio3_io18: IOMUXC1_SD1_STROBE_GPIO_IO_GPIO3_IO18 { + pinmux = <0x443c0130 5 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC1_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x443c0130 0 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC1_SD2_CD_B_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x443c0150 1 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_flexio_flexio_flexio1_flexio00: IOMUXC1_SD2_CD_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0150 4 0x443c036c 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_gpio_io_gpio3_io00: IOMUXC1_SD2_CD_B_GPIO_IO_GPIO3_IO00 { + pinmux = <0x443c0150 5 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_i3c_scl_i3c2_scl: IOMUXC1_SD2_CD_B_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0150 2 0x443c03cc 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC1_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x443c0150 0 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe0: IOMUXC1_SD2_CLK_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE0 { + pinmux = <0x443c0154 6 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC1_SD2_CLK_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x443c0154 1 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_flexio_flexio_flexio1_flexio01: IOMUXC1_SD2_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0154 4 0x443c0370 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_gpio_io_gpio3_io01: IOMUXC1_SD2_CLK_GPIO_IO_GPIO3_IO01 { + pinmux = <0x443c0154 5 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_i3c_sda_i3c2_sda: IOMUXC1_SD2_CLK_I3C_SDA_I3C2_SDA { + pinmux = <0x443c0154 2 0x443c03d0 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC1_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x443c0154 0 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe1: IOMUXC1_SD2_CMD_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE1 { + pinmux = <0x443c0158 6 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_enet1_1588_event0_in_enet1_1588_event0_in: IOMUXC1_SD2_CMD_ENET1_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x443c0158 1 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_flexio_flexio_flexio1_flexio02: IOMUXC1_SD2_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0158 4 0x443c0374 1 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_gpio_io_gpio3_io02: IOMUXC1_SD2_CMD_GPIO_IO_GPIO3_IO02 { + pinmux = <0x443c0158 5 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_b_i3c2_pur_b: IOMUXC1_SD2_CMD_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c0158 3 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_i3c2_pur: IOMUXC1_SD2_CMD_I3C_PUR_I3C2_PUR { + pinmux = <0x443c0158 2 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC1_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x443c0158 0 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_can_tx_can2_tx: IOMUXC1_SD2_DATA0_CAN_TX_CAN2_TX { + pinmux = <0x443c015c 2 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe2: IOMUXC1_SD2_DATA0_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE2 { + pinmux = <0x443c015c 6 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_enet1_1588_event0_out_enet1_1588_event0_out: IOMUXC1_SD2_DATA0_ENET1_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x443c015c 1 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_flexio_flexio_flexio1_flexio03: IOMUXC1_SD2_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c015c 4 0x443c0378 1 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_gpio_io_gpio3_io03: IOMUXC1_SD2_DATA0_GPIO_IO_GPIO3_IO03 { + pinmux = <0x443c015c 5 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC1_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x443c015c 0 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_can_rx_can2_rx: IOMUXC1_SD2_DATA1_CAN_RX_CAN2_RX { + pinmux = <0x443c0160 2 0x443c0364 3 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_enet1_1588_event1_in_enet1_1588_event1_in: IOMUXC1_SD2_DATA1_ENET1_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x443c0160 1 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_flexio_flexio_flexio1_flexio04: IOMUXC1_SD2_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0160 4 0x443c037c 1 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_gpio_io_gpio3_io04: IOMUXC1_SD2_DATA1_GPIO_IO_GPIO3_IO04 { + pinmux = <0x443c0160 5 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC1_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x443c0160 0 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_enet1_1588_event1_out_enet1_1588_event1_out: IOMUXC1_SD2_DATA2_ENET1_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x443c0164 1 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_flexio_flexio_flexio1_flexio05: IOMUXC1_SD2_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0164 4 0x443c0380 1 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_gpio_io_gpio3_io05: IOMUXC1_SD2_DATA2_GPIO_IO_GPIO3_IO05 { + pinmux = <0x443c0164 5 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_mqs_right_mqs2_right: IOMUXC1_SD2_DATA2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0164 2 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC1_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x443c0164 0 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_flexio_flexio_flexio1_flexio06: IOMUXC1_SD2_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0168 4 0x443c0384 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_gpio_io_gpio3_io06: IOMUXC1_SD2_DATA3_GPIO_IO_GPIO3_IO06 { + pinmux = <0x443c0168 5 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_lptmr_alt_lptmr2_alt1: IOMUXC1_SD2_DATA3_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c0168 1 0x443c0408 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_mqs_left_mqs2_left: IOMUXC1_SD2_DATA3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0168 2 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC1_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x443c0168 0 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_ccmsrcgpcmix_system_reset_ccmsrcgpcmix_system_reset: IOMUXC1_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET_CCMSRCGPCMIX_SYSTEM_RESET { + pinmux = <0x443c016c 6 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_flexio_flexio_flexio1_flexio07: IOMUXC1_SD2_RESET_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c016c 4 0x443c0388 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_gpio_io_gpio3_io07: IOMUXC1_SD2_RESET_B_GPIO_IO_GPIO3_IO07 { + pinmux = <0x443c016c 5 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_lptmr_alt_lptmr2_alt2: IOMUXC1_SD2_RESET_B_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c016c 1 0x443c040c 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC1_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x443c016c 0 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0134 6 0x443c0368 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_flexio_flexio_flexio1_flexio19: IOMUXC1_SD2_VSELECT_FLEXIO_FLEXIO_FLEXIO1_FLEXIO19 { + pinmux = <0x443c0134 4 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_gpio_io_gpio3_io19: IOMUXC1_SD2_VSELECT_GPIO_IO_GPIO3_IO19 { + pinmux = <0x443c0134 5 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_lptmr_alt_lptmr2_alt3: IOMUXC1_SD2_VSELECT_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c0134 2 0x443c0410 1 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect: IOMUXC1_SD2_VSELECT_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x443c0134 0 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_wp_usdhc2_wp: IOMUXC1_SD2_VSELECT_USDHC_WP_USDHC2_WP { + pinmux = <0x443c0134 1 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexio_flexio_flexio1_flexio20: IOMUXC1_SD3_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0138 4 0x443c03b4 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexspi_a_sclk_flexspi1_a_sclk: IOMUXC1_SD3_CLK_FLEXSPI_A_SCLK_FLEXSPI1_A_SCLK { + pinmux = <0x443c0138 1 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_gpio_io_gpio3_io20: IOMUXC1_SD3_CLK_GPIO_IO_GPIO3_IO20 { + pinmux = <0x443c0138 5 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_usdhc_clk_usdhc3_clk: IOMUXC1_SD3_CLK_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0138 0 0x443c0458 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexio_flexio_flexio1_flexio21: IOMUXC1_SD3_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO21 { + pinmux = <0x443c013c 4 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexspi_a_ss_b_flexspi1_a_ss0_b: IOMUXC1_SD3_CMD_FLEXSPI_A_SS_B_FLEXSPI1_A_SS0_B { + pinmux = <0x443c013c 1 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_gpio_io_gpio3_io21: IOMUXC1_SD3_CMD_GPIO_IO_GPIO3_IO21 { + pinmux = <0x443c013c 5 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_usdhc_cmd_usdhc3_cmd: IOMUXC1_SD3_CMD_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c013c 0 0x443c045c 1 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexio_flexio_flexio1_flexio22: IOMUXC1_SD3_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0140 4 0x443c03b8 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexspi_a_data_flexspi1_a_data00: IOMUXC1_SD3_DATA0_FLEXSPI_A_DATA_FLEXSPI1_A_DATA00 { + pinmux = <0x443c0140 1 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_gpio_io_gpio3_io22: IOMUXC1_SD3_DATA0_GPIO_IO_GPIO3_IO22 { + pinmux = <0x443c0140 5 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_usdhc_data_usdhc3_data0: IOMUXC1_SD3_DATA0_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0140 0 0x443c0460 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexio_flexio_flexio1_flexio23: IOMUXC1_SD3_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c0144 4 0x443c03bc 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexspi_a_data_flexspi1_a_data01: IOMUXC1_SD3_DATA1_FLEXSPI_A_DATA_FLEXSPI1_A_DATA01 { + pinmux = <0x443c0144 1 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_gpio_io_gpio3_io23: IOMUXC1_SD3_DATA1_GPIO_IO_GPIO3_IO23 { + pinmux = <0x443c0144 5 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_usdhc_data_usdhc3_data1: IOMUXC1_SD3_DATA1_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0144 0 0x443c0464 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexio_flexio_flexio1_flexio24: IOMUXC1_SD3_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0148 4 0x443c03c0 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexspi_a_data_flexspi1_a_data02: IOMUXC1_SD3_DATA2_FLEXSPI_A_DATA_FLEXSPI1_A_DATA02 { + pinmux = <0x443c0148 1 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_gpio_io_gpio3_io24: IOMUXC1_SD3_DATA2_GPIO_IO_GPIO3_IO24 { + pinmux = <0x443c0148 5 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_usdhc_data_usdhc3_data2: IOMUXC1_SD3_DATA2_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0148 0 0x443c0468 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexio_flexio_flexio1_flexio25: IOMUXC1_SD3_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c014c 4 0x443c03c4 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexspi_a_data_flexspi1_a_data03: IOMUXC1_SD3_DATA3_FLEXSPI_A_DATA_FLEXSPI1_A_DATA03 { + pinmux = <0x443c014c 1 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_gpio_io_gpio3_io25: IOMUXC1_SD3_DATA3_GPIO_IO_GPIO3_IO25 { + pinmux = <0x443c014c 5 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_usdhc_data_usdhc3_data3: IOMUXC1_SD3_DATA3_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c014c 0 0x443c046c 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_gpio_io_gpio1_io04: IOMUXC1_UART1_RXD_GPIO_IO_GPIO1_IO04 { + pinmux = <0x443c0180 5 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpspi_sin_lpspi2_sin: IOMUXC1_UART1_RXD_LPSPI_SIN_LPSPI2_SIN { + pinmux = <0x443c0180 2 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx: IOMUXC1_UART1_RXD_LPUART_RX_LPUART1_RX { + pinmux = <0x443c0180 0 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_s400_uart_rx_s400_uart_rx: IOMUXC1_UART1_RXD_S400_UART_RX_S400_UART_RX { + pinmux = <0x443c0180 1 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_tpm_ch_tpm1_ch0: IOMUXC1_UART1_RXD_TPM_CH_TPM1_CH0 { + pinmux = <0x443c0180 3 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_gpio_io_gpio1_io05: IOMUXC1_UART1_TXD_GPIO_IO_GPIO1_IO05 { + pinmux = <0x443c0184 5 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpspi_pcs_lpspi2_pcs0: IOMUXC1_UART1_TXD_LPSPI_PCS_LPSPI2_PCS0 { + pinmux = <0x443c0184 2 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx: IOMUXC1_UART1_TXD_LPUART_TX_LPUART1_TX { + pinmux = <0x443c0184 0 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_s400_uart_tx_s400_uart_tx: IOMUXC1_UART1_TXD_S400_UART_TX_S400_UART_TX { + pinmux = <0x443c0184 1 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_tpm_ch_tpm1_ch1: IOMUXC1_UART1_TXD_TPM_CH_TPM1_CH1 { + pinmux = <0x443c0184 3 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_gpio_io_gpio1_io06: IOMUXC1_UART2_RXD_GPIO_IO_GPIO1_IO06 { + pinmux = <0x443c0188 5 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpspi_sout_lpspi2_sout: IOMUXC1_UART2_RXD_LPSPI_SOUT_LPSPI2_SOUT { + pinmux = <0x443c0188 2 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_cts_b_lpuart1_cts_b: IOMUXC1_UART2_RXD_LPUART_CTS_B_LPUART1_CTS_B { + pinmux = <0x443c0188 1 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx: IOMUXC1_UART2_RXD_LPUART_RX_LPUART2_RX { + pinmux = <0x443c0188 0 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_sai_mclk_sai1_mclk: IOMUXC1_UART2_RXD_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c0188 4 0x443c0448 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_tpm_ch_tpm1_ch2: IOMUXC1_UART2_RXD_TPM_CH_TPM1_CH2 { + pinmux = <0x443c0188 3 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_gpio_io_gpio1_io07: IOMUXC1_UART2_TXD_GPIO_IO_GPIO1_IO07 { + pinmux = <0x443c018c 5 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpspi_sck_lpspi2_sck: IOMUXC1_UART2_TXD_LPSPI_SCK_LPSPI2_SCK { + pinmux = <0x443c018c 2 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_rts_b_lpuart1_rts_b: IOMUXC1_UART2_TXD_LPUART_RTS_B_LPUART1_RTS_B { + pinmux = <0x443c018c 1 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx: IOMUXC1_UART2_TXD_LPUART_TX_LPUART2_TX { + pinmux = <0x443c018c 0 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_tpm_ch_tpm1_ch3: IOMUXC1_UART2_TXD_TPM_CH_TPM1_CH3 { + pinmux = <0x443c018c 3 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_gpio_io_gpio1_io15: IOMUXC1_WDOG_ANY_GPIO_IO_GPIO1_IO15 { + pinmux = <0x443c01ac 5 0x0 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_wdog_wdog_any_wdog1_wdog_any: IOMUXC1_WDOG_ANY_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x443c01ac 0 0x0 0 0x443c035c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx9351xvvxm-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx9351xvvxm-pinctrl.dtsi new file mode 100644 index 000000000..04267cf48 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx9351xvvxm-pinctrl.dtsi @@ -0,0 +1,1831 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX9351XVVXM + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc1_ccm_clko1_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko1: IOMUXC1_CCM_CLKO1_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO1 { + pinmux = <0x443c0088 0 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_flexio_flexio_flexio1_flexio26: IOMUXC1_CCM_CLKO1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO26 { + pinmux = <0x443c0088 4 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_gpio_io_gpio3_io26: IOMUXC1_CCM_CLKO1_GPIO_IO_GPIO3_IO26 { + pinmux = <0x443c0088 5 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko2: IOMUXC1_CCM_CLKO2_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO2 { + pinmux = <0x443c008c 0 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_flexio_flexio_flexio1_flexio27: IOMUXC1_CCM_CLKO2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c008c 4 0x443c03c8 1 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_gpio_io_gpio3_io27: IOMUXC1_CCM_CLKO2_GPIO_IO_GPIO3_IO27 { + pinmux = <0x443c008c 5 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko3: IOMUXC1_CCM_CLKO3_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO3 { + pinmux = <0x443c0090 0 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_flexio_flexio_flexio2_flexio28: IOMUXC1_CCM_CLKO3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO28 { + pinmux = <0x443c0090 4 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_gpio_io_gpio4_io28: IOMUXC1_CCM_CLKO3_GPIO_IO_GPIO4_IO28 { + pinmux = <0x443c0090 5 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko4: IOMUXC1_CCM_CLKO4_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO4 { + pinmux = <0x443c0094 0 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_flexio_flexio_flexio2_flexio29: IOMUXC1_CCM_CLKO4_FLEXIO_FLEXIO_FLEXIO2_FLEXIO29 { + pinmux = <0x443c0094 4 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_gpio_io_gpio4_io29: IOMUXC1_CCM_CLKO4_GPIO_IO_GPIO4_IO29 { + pinmux = <0x443c0094 5 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_flexio_flexio_flexio1_flexio30: IOMUXC1_DAP_TCLK_SWCLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO30 { + pinmux = <0x443c0008 4 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30: IOMUXC1_DAP_TCLK_SWCLK_GPIO_IO_GPIO3_IO30 { + pinmux = <0x443c0008 5 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_jtag_mux_tck_jtag_mux_tck: IOMUXC1_DAP_TCLK_SWCLK_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0008 0 0x443c03d4 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_DAP_TCLK_SWCLK_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0008 6 0x443c042c 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_can_tx_can2_tx: IOMUXC1_DAP_TDI_CAN_TX_CAN2_TX { + pinmux = <0x443c0000 3 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_flexio_flexio_flexio2_flexio30: IOMUXC1_DAP_TDI_FLEXIO_FLEXIO_FLEXIO2_FLEXIO30 { + pinmux = <0x443c0000 4 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_gpio_io_gpio3_io28: IOMUXC1_DAP_TDI_GPIO_IO_GPIO3_IO28 { + pinmux = <0x443c0000 5 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_DAP_TDI_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0000 0 0x443c03d8 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_lpuart_rx_lpuart5_rx: IOMUXC1_DAP_TDI_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0000 6 0x443c0430 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_mqs_left_mqs2_left: IOMUXC1_DAP_TDI_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0000 1 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_can_rx_can2_rx: IOMUXC1_DAP_TDO_TRACESWO_CAN_RX_CAN2_RX { + pinmux = <0x443c000c 3 0x443c0364 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_flexio_flexio_flexio1_flexio31: IOMUXC1_DAP_TDO_TRACESWO_FLEXIO_FLEXIO_FLEXIO1_FLEXIO31 { + pinmux = <0x443c000c 4 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31: IOMUXC1_DAP_TDO_TRACESWO_GPIO_IO_GPIO3_IO31 { + pinmux = <0x443c000c 5 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_DAP_TDO_TRACESWO_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c000c 0 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_lpuart_tx_lpuart5_tx: IOMUXC1_DAP_TDO_TRACESWO_LPUART_TX_LPUART5_TX { + pinmux = <0x443c000c 6 0x443c0434 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_mqs_right_mqs2_right: IOMUXC1_DAP_TDO_TRACESWO_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c000c 1 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_flexio_flexio_flexio2_flexio31: IOMUXC1_DAP_TMS_SWDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO31 { + pinmux = <0x443c0004 4 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29: IOMUXC1_DAP_TMS_SWDIO_GPIO_IO_GPIO3_IO29 { + pinmux = <0x443c0004 5 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_jtag_mux_tms_jtag_mux_tms: IOMUXC1_DAP_TMS_SWDIO_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c0004 0 0x443c03dc 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_DAP_TMS_SWDIO_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c0004 6 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC1_ENET1_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x443c0098 0 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_flexio_flexio_flexio2_flexio00: IOMUXC1_ENET1_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO00 { + pinmux = <0x443c0098 4 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_gpio_io_gpio4_io00: IOMUXC1_ENET1_MDC_GPIO_IO_GPIO4_IO00 { + pinmux = <0x443c0098 5 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_hsiomix_otg_id_hsiomix_otg_id1: IOMUXC1_ENET1_MDC_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID1 { + pinmux = <0x443c0098 3 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_i3c_scl_i3c2_scl: IOMUXC1_ENET1_MDC_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0098 2 0x443c03cc 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_lpuart_dcb_b_lpuart3_dcb_b: IOMUXC1_ENET1_MDC_LPUART_DCB_B_LPUART3_DCB_B { + pinmux = <0x443c0098 1 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC1_ENET1_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x443c009c 0 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_flexio_flexio_flexio2_flexio01: IOMUXC1_ENET1_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO01 { + pinmux = <0x443c009c 4 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_gpio_io_gpio4_io01: IOMUXC1_ENET1_MDIO_GPIO_IO_GPIO4_IO01 { + pinmux = <0x443c009c 5 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_hsiomix_otg_pwr_hsiomix_otg_pwr1: IOMUXC1_ENET1_MDIO_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR1 { + pinmux = <0x443c009c 3 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_i3c_sda_i3c2_sda: IOMUXC1_ENET1_MDIO_I3C_SDA_I3C2_SDA { + pinmux = <0x443c009c 2 0x443c03d0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_lpuart_rin_b_lpuart3_rin_b: IOMUXC1_ENET1_MDIO_LPUART_RIN_B_LPUART3_RIN_B { + pinmux = <0x443c009c 1 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC1_ENET1_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x443c00c0 0 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_flexio_flexio_flexio2_flexio10: IOMUXC1_ENET1_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO10 { + pinmux = <0x443c00c0 4 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_gpio_io_gpio4_io10: IOMUXC1_ENET1_RD0_GPIO_IO_GPIO4_IO10 { + pinmux = <0x443c00c0 5 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_lpuart_rx_lpuart3_rx: IOMUXC1_ENET1_RD0_LPUART_RX_LPUART3_RX { + pinmux = <0x443c00c0 1 0x443c0418 1 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC1_ENET1_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x443c00c4 0 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_flexio_flexio_flexio2_flexio11: IOMUXC1_ENET1_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO11 { + pinmux = <0x443c00c4 4 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_gpio_io_gpio4_io11: IOMUXC1_ENET1_RD1_GPIO_IO_GPIO4_IO11 { + pinmux = <0x443c00c4 5 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lptmr_alt_lptmr2_alt1: IOMUXC1_ENET1_RD1_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c00c4 3 0x443c0408 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_ENET1_RD1_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c00c4 1 0x443c0414 1 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC1_ENET1_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x443c00c8 0 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_flexio_flexio_flexio2_flexio12: IOMUXC1_ENET1_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO12 { + pinmux = <0x443c00c8 4 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_gpio_io_gpio4_io12: IOMUXC1_ENET1_RD2_GPIO_IO_GPIO4_IO12 { + pinmux = <0x443c00c8 5 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_lptmr_alt_lptmr2_alt2: IOMUXC1_ENET1_RD2_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c00c8 3 0x443c040c 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC1_ENET1_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x443c00cc 0 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_flexio_flexio_flexio2_flexio13: IOMUXC1_ENET1_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO13 { + pinmux = <0x443c00cc 4 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_gpio_io_gpio4_io13: IOMUXC1_ENET1_RD3_GPIO_IO_GPIO4_IO13 { + pinmux = <0x443c00cc 5 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_lptmr_alt_lptmr2_alt3: IOMUXC1_ENET1_RD3_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c00cc 3 0x443c0410 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_ccm_enet_qos_clock_generate_rx_clk_ccm_enet_qos_clock_generate_rx_clk: IOMUXC1_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK { + pinmux = <0x443c00bc 0 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC1_ENET1_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x443c00bc 1 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_flexio_flexio_flexio2_flexio09: IOMUXC1_ENET1_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO09 { + pinmux = <0x443c00bc 4 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_gpio_io_gpio4_io09: IOMUXC1_ENET1_RXC_GPIO_IO_GPIO4_IO09 { + pinmux = <0x443c00bc 5 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC1_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x443c00b8 0 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_flexio_flexio_flexio2_flexio08: IOMUXC1_ENET1_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO08 { + pinmux = <0x443c00b8 4 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08: IOMUXC1_ENET1_RX_CTL_GPIO_IO_GPIO4_IO08 { + pinmux = <0x443c00b8 5 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_hsiomix_otg_pwr_hsiomix_otg_pwr2: IOMUXC1_ENET1_RX_CTL_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR2 { + pinmux = <0x443c00b8 3 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_lpuart_dsr_b_lpuart3_dsr_b: IOMUXC1_ENET1_RX_CTL_LPUART_DSR_B_LPUART3_DSR_B { + pinmux = <0x443c00b8 1 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC1_ENET1_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x443c00ac 0 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_flexio_flexio_flexio2_flexio05: IOMUXC1_ENET1_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO05 { + pinmux = <0x443c00ac 4 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_gpio_io_gpio4_io05: IOMUXC1_ENET1_TD0_GPIO_IO_GPIO4_IO05 { + pinmux = <0x443c00ac 5 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_lpuart_tx_lpuart3_tx: IOMUXC1_ENET1_TD0_LPUART_TX_LPUART3_TX { + pinmux = <0x443c00ac 1 0x443c041c 1 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC1_ENET1_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x443c00a8 0 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_flexio_flexio_flexio2_flexio04: IOMUXC1_ENET1_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO04 { + pinmux = <0x443c00a8 4 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_gpio_io_gpio4_io04: IOMUXC1_ENET1_TD1_GPIO_IO_GPIO4_IO04 { + pinmux = <0x443c00a8 5 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_hsiomix_otg_oc_hsiomix_otg_oc1: IOMUXC1_ENET1_TD1_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC1 { + pinmux = <0x443c00a8 3 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_b_i3c2_pur_b: IOMUXC1_ENET1_TD1_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c00a8 6 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_i3c2_pur: IOMUXC1_ENET1_TD1_I3C_PUR_I3C2_PUR { + pinmux = <0x443c00a8 2 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_ENET1_TD1_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c00a8 1 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_can_rx_can2_rx: IOMUXC1_ENET1_TD2_CAN_RX_CAN2_RX { + pinmux = <0x443c00a4 2 0x443c0364 2 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_ccm_enet_qos_clock_generate_ref_clk_ccm_enet_qos_clock_generate_ref_clk: IOMUXC1_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK { + pinmux = <0x443c00a4 1 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC1_ENET1_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x443c00a4 0 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_flexio_flexio_flexio2_flexio03: IOMUXC1_ENET1_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO03 { + pinmux = <0x443c00a4 4 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_gpio_io_gpio4_io03: IOMUXC1_ENET1_TD2_GPIO_IO_GPIO4_IO03 { + pinmux = <0x443c00a4 5 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_hsiomix_otg_oc_hsiomix_otg_oc2: IOMUXC1_ENET1_TD2_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC2 { + pinmux = <0x443c00a4 3 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_can_tx_can2_tx: IOMUXC1_ENET1_TD3_CAN_TX_CAN2_TX { + pinmux = <0x443c00a0 2 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC1_ENET1_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x443c00a0 0 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_flexio_flexio_flexio2_flexio02: IOMUXC1_ENET1_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO02 { + pinmux = <0x443c00a0 4 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_gpio_io_gpio4_io02: IOMUXC1_ENET1_TD3_GPIO_IO_GPIO4_IO02 { + pinmux = <0x443c00a0 5 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_hsiomix_otg_id_hsiomix_otg_id2: IOMUXC1_ENET1_TD3_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID2 { + pinmux = <0x443c00a0 3 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_ccm_enet_qos_clock_generate_tx_clk_ccm_enet_qos_clock_generate_tx_clk: IOMUXC1_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK { + pinmux = <0x443c00b4 0 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC1_ENET1_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x443c00b4 1 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_flexio_flexio_flexio2_flexio07: IOMUXC1_ENET1_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO07 { + pinmux = <0x443c00b4 4 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_gpio_io_gpio4_io07: IOMUXC1_ENET1_TXC_GPIO_IO_GPIO4_IO07 { + pinmux = <0x443c00b4 5 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC1_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x443c00b0 0 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_flexio_flexio_flexio2_flexio06: IOMUXC1_ENET1_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO06 { + pinmux = <0x443c00b0 4 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06: IOMUXC1_ENET1_TX_CTL_GPIO_IO_GPIO4_IO06 { + pinmux = <0x443c00b0 5 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_lpuart_dtr_b_lpuart3_dtr_b: IOMUXC1_ENET1_TX_CTL_LPUART_DTR_B_LPUART3_DTR_B { + pinmux = <0x443c00b0 1 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_enet_mdc_enet1_mdc: IOMUXC1_ENET2_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x443c00d0 0 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_flexio_flexio_flexio2_flexio14: IOMUXC1_ENET2_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO14 { + pinmux = <0x443c00d0 4 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_gpio_io_gpio4_io14: IOMUXC1_ENET2_MDC_GPIO_IO_GPIO4_IO14 { + pinmux = <0x443c00d0 5 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_lpuart_dcb_b_lpuart4_dcb_b: IOMUXC1_ENET2_MDC_LPUART_DCB_B_LPUART4_DCB_B { + pinmux = <0x443c00d0 1 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_sai_rx_sync_sai2_rx_sync: IOMUXC1_ENET2_MDC_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x443c00d0 2 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_enet_mdio_enet1_mdio: IOMUXC1_ENET2_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x443c00d4 0 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_flexio_flexio_flexio2_flexio15: IOMUXC1_ENET2_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO15 { + pinmux = <0x443c00d4 4 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_gpio_io_gpio4_io15: IOMUXC1_ENET2_MDIO_GPIO_IO_GPIO4_IO15 { + pinmux = <0x443c00d4 5 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_lpuart_rin_b_lpuart4_rin_b: IOMUXC1_ENET2_MDIO_LPUART_RIN_B_LPUART4_RIN_B { + pinmux = <0x443c00d4 1 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_sai_rx_bclk_sai2_rx_bclk: IOMUXC1_ENET2_MDIO_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x443c00d4 2 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC1_ENET2_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x443c00f8 0 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_flexio_flexio_flexio2_flexio24: IOMUXC1_ENET2_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO24 { + pinmux = <0x443c00f8 4 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_gpio_io_gpio4_io24: IOMUXC1_ENET2_RD0_GPIO_IO_GPIO4_IO24 { + pinmux = <0x443c00f8 5 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_lpuart_rx_lpuart4_rx: IOMUXC1_ENET2_RD0_LPUART_RX_LPUART4_RX { + pinmux = <0x443c00f8 1 0x443c0424 1 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_sai_tx_data_sai2_tx_data02: IOMUXC1_ENET2_RD0_SAI_TX_DATA_SAI2_TX_DATA02 { + pinmux = <0x443c00f8 2 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC1_ENET2_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x443c00fc 0 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_flexio_flexio_flexio2_flexio25: IOMUXC1_ENET2_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO25 { + pinmux = <0x443c00fc 4 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_gpio_io_gpio4_io25: IOMUXC1_ENET2_RD1_GPIO_IO_GPIO4_IO25 { + pinmux = <0x443c00fc 5 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_sai_tx_data_sai2_tx_data03: IOMUXC1_ENET2_RD1_SAI_TX_DATA_SAI2_TX_DATA03 { + pinmux = <0x443c00fc 2 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_spdif_in_spdif_in: IOMUXC1_ENET2_RD1_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c00fc 1 0x443c0454 1 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC1_ENET2_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x443c0100 0 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_flexio_flexio_flexio2_flexio26: IOMUXC1_ENET2_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO26 { + pinmux = <0x443c0100 4 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_gpio_io_gpio4_io26: IOMUXC1_ENET2_RD2_GPIO_IO_GPIO4_IO26 { + pinmux = <0x443c0100 5 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_ENET2_RD2_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0100 1 0x443c0420 1 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_mqs_right_mqs2_right: IOMUXC1_ENET2_RD2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0100 3 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_sai_mclk_sai2_mclk: IOMUXC1_ENET2_RD2_SAI_MCLK_SAI2_MCLK { + pinmux = <0x443c0100 2 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC1_ENET2_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x443c0104 0 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_flexio_flexio_flexio2_flexio27: IOMUXC1_ENET2_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO27 { + pinmux = <0x443c0104 4 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_gpio_io_gpio4_io27: IOMUXC1_ENET2_RD3_GPIO_IO_GPIO4_IO27 { + pinmux = <0x443c0104 5 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_mqs_left_mqs2_left: IOMUXC1_ENET2_RD3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0104 3 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_in_spdif_in: IOMUXC1_ENET2_RD3_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0104 2 0x443c0454 2 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_out_spdif_out: IOMUXC1_ENET2_RD3_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c0104 1 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC1_ENET2_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x443c00f4 0 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rx_er_enet1_rx_er: IOMUXC1_ENET2_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x443c00f4 1 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_flexio_flexio_flexio2_flexio23: IOMUXC1_ENET2_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO23 { + pinmux = <0x443c00f4 4 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_gpio_io_gpio4_io23: IOMUXC1_ENET2_RXC_GPIO_IO_GPIO4_IO23 { + pinmux = <0x443c00f4 5 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_sai_tx_data_sai2_tx_data01: IOMUXC1_ENET2_RXC_SAI_TX_DATA_SAI2_TX_DATA01 { + pinmux = <0x443c00f4 2 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC1_ENET2_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x443c00f0 0 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_flexio_flexio_flexio2_flexio22: IOMUXC1_ENET2_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO22 { + pinmux = <0x443c00f0 4 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22: IOMUXC1_ENET2_RX_CTL_GPIO_IO_GPIO4_IO22 { + pinmux = <0x443c00f0 5 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_lpuart_dsr_b_lpuart4_dsr_b: IOMUXC1_ENET2_RX_CTL_LPUART_DSR_B_LPUART4_DSR_B { + pinmux = <0x443c00f0 1 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_sai_tx_data_sai2_tx_data00: IOMUXC1_ENET2_RX_CTL_SAI_TX_DATA_SAI2_TX_DATA00 { + pinmux = <0x443c00f0 2 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC1_ENET2_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x443c00e4 0 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_flexio_flexio_flexio2_flexio19: IOMUXC1_ENET2_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO19 { + pinmux = <0x443c00e4 4 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_gpio_io_gpio4_io19: IOMUXC1_ENET2_TD0_GPIO_IO_GPIO4_IO19 { + pinmux = <0x443c00e4 5 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_lpuart_tx_lpuart4_tx: IOMUXC1_ENET2_TD0_LPUART_TX_LPUART4_TX { + pinmux = <0x443c00e4 1 0x443c0428 1 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_sai_rx_data_sai2_rx_data03: IOMUXC1_ENET2_TD0_SAI_RX_DATA_SAI2_RX_DATA03 { + pinmux = <0x443c00e4 2 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC1_ENET2_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x443c00e0 0 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_flexio_flexio_flexio2_flexio18: IOMUXC1_ENET2_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO18 { + pinmux = <0x443c00e0 4 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_gpio_io_gpio4_io18: IOMUXC1_ENET2_TD1_GPIO_IO_GPIO4_IO18 { + pinmux = <0x443c00e0 5 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_ENET2_TD1_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c00e0 1 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_sai_rx_data_sai2_rx_data02: IOMUXC1_ENET2_TD1_SAI_RX_DATA_SAI2_RX_DATA02 { + pinmux = <0x443c00e0 2 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC1_ENET2_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x443c00dc 0 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_tx_clk_enet1_tx_clk: IOMUXC1_ENET2_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x443c00dc 1 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_flexio_flexio_flexio2_flexio17: IOMUXC1_ENET2_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO17 { + pinmux = <0x443c00dc 4 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_gpio_io_gpio4_io17: IOMUXC1_ENET2_TD2_GPIO_IO_GPIO4_IO17 { + pinmux = <0x443c00dc 5 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_sai_rx_data_sai2_rx_data01: IOMUXC1_ENET2_TD2_SAI_RX_DATA_SAI2_RX_DATA01 { + pinmux = <0x443c00dc 2 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC1_ENET2_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x443c00d8 0 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_flexio_flexio_flexio2_flexio16: IOMUXC1_ENET2_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO16 { + pinmux = <0x443c00d8 4 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_gpio_io_gpio4_io16: IOMUXC1_ENET2_TD3_GPIO_IO_GPIO4_IO16 { + pinmux = <0x443c00d8 5 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_sai_rx_data_sai2_rx_data00: IOMUXC1_ENET2_TD3_SAI_RX_DATA_SAI2_RX_DATA00 { + pinmux = <0x443c00d8 2 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC1_ENET2_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x443c00ec 0 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_tx_er_enet1_tx_er: IOMUXC1_ENET2_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x443c00ec 1 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_flexio_flexio_flexio2_flexio21: IOMUXC1_ENET2_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO21 { + pinmux = <0x443c00ec 4 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_gpio_io_gpio4_io21: IOMUXC1_ENET2_TXC_GPIO_IO_GPIO4_IO21 { + pinmux = <0x443c00ec 5 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC1_ENET2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x443c00ec 2 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC1_ENET2_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x443c00e8 0 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_flexio_flexio_flexio2_flexio20: IOMUXC1_ENET2_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO20 { + pinmux = <0x443c00e8 4 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20: IOMUXC1_ENET2_TX_CTL_GPIO_IO_GPIO4_IO20 { + pinmux = <0x443c00e8 5 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_lpuart_dtr_b_lpuart4_dtr_b: IOMUXC1_ENET2_TX_CTL_LPUART_DTR_B_LPUART4_DTR_B { + pinmux = <0x443c00e8 1 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_sai_tx_sync_sai2_tx_sync: IOMUXC1_ENET2_TX_CTL_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x443c00e8 2 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_flexio_flexio_flexio1_flexio00: IOMUXC1_GPIO_IO00_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0010 7 0x443c036c 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_gpio_io_gpio2_io00: IOMUXC1_GPIO_IO00_GPIO_IO_GPIO2_IO00 { + pinmux = <0x443c0010 0 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0010 1 0x443c03e4 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0010 6 0x443c03ec 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpspi_pcs_lpspi6_pcs0: IOMUXC1_GPIO_IO00_LPSPI_PCS_LPSPI6_PCS0 { + pinmux = <0x443c0010 4 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpuart_tx_lpuart5_tx: IOMUXC1_GPIO_IO00_LPUART_TX_LPUART5_TX { + pinmux = <0x443c0010 5 0x443c0434 1 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_cam_clk_mediamix_cam_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_CAM_CLK_MEDIAMIX_CAM_CLK { + pinmux = <0x443c0010 2 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_disp_clk_mediamix_disp_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_DISP_CLK_MEDIAMIX_DISP_CLK { + pinmux = <0x443c0010 3 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_flexio_flexio_flexio1_flexio01: IOMUXC1_GPIO_IO01_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0014 7 0x443c0370 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_gpio_io_gpio2_io01: IOMUXC1_GPIO_IO01_GPIO_IO_GPIO2_IO01 { + pinmux = <0x443c0014 0 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0014 1 0x443c03e0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c0014 6 0x443c03e8 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpspi_sin_lpspi6_sin: IOMUXC1_GPIO_IO01_LPSPI_SIN_LPSPI6_SIN { + pinmux = <0x443c0014 4 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpuart_rx_lpuart5_rx: IOMUXC1_GPIO_IO01_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0014 5 0x443c0430 1 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_cam_data_mediamix_cam_data00: IOMUXC1_GPIO_IO01_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA00 { + pinmux = <0x443c0014 2 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_disp_de_mediamix_disp_de: IOMUXC1_GPIO_IO01_MEDIAMIX_DISP_DE_MEDIAMIX_DISP_DE { + pinmux = <0x443c0014 3 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_flexio_flexio_flexio1_flexio02: IOMUXC1_GPIO_IO02_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0018 7 0x443c0374 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_gpio_io_gpio2_io02: IOMUXC1_GPIO_IO02_GPIO_IO_GPIO2_IO02 { + pinmux = <0x443c0018 0 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C4_SDA { + pinmux = <0x443c0018 1 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0018 6 0x443c03f4 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpspi_sout_lpspi6_sout: IOMUXC1_GPIO_IO02_LPSPI_SOUT_LPSPI6_SOUT { + pinmux = <0x443c0018 4 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_GPIO_IO02_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0018 5 0x443c042c 1 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_cam_vsync_mediamix_cam_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_CAM_VSYNC_MEDIAMIX_CAM_VSYNC { + pinmux = <0x443c0018 2 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_disp_vsync_mediamix_disp_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_DISP_VSYNC_MEDIAMIX_DISP_VSYNC { + pinmux = <0x443c0018 3 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_flexio_flexio_flexio1_flexio03: IOMUXC1_GPIO_IO03_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c001c 7 0x443c0378 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_gpio_io_gpio2_io03: IOMUXC1_GPIO_IO03_GPIO_IO_GPIO2_IO03 { + pinmux = <0x443c001c 0 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C4_SCL { + pinmux = <0x443c001c 1 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c001c 6 0x443c03f0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpspi_sck_lpspi6_sck: IOMUXC1_GPIO_IO03_LPSPI_SCK_LPSPI6_SCK { + pinmux = <0x443c001c 4 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_GPIO_IO03_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c001c 5 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_cam_hsync_mediamix_cam_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_CAM_HSYNC_MEDIAMIX_CAM_HSYNC { + pinmux = <0x443c001c 2 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_disp_hsync_mediamix_disp_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_DISP_HSYNC_MEDIAMIX_DISP_HSYNC { + pinmux = <0x443c001c 3 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_flexio_flexio_flexio1_flexio04: IOMUXC1_GPIO_IO04_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0020 7 0x443c037c 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_gpio_io_gpio2_io04: IOMUXC1_GPIO_IO04_GPIO_IO_GPIO2_IO04 { + pinmux = <0x443c0020 0 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO04_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0020 6 0x443c03f4 1 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpspi_pcs_lpspi7_pcs0: IOMUXC1_GPIO_IO04_LPSPI_PCS_LPSPI7_PCS0 { + pinmux = <0x443c0020 4 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpuart_tx_lpuart6_tx: IOMUXC1_GPIO_IO04_LPUART_TX_LPUART6_TX { + pinmux = <0x443c0020 5 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_mediamix_disp_data_mediamix_disp_data00: IOMUXC1_GPIO_IO04_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA00 { + pinmux = <0x443c0020 3 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO04_PDM_CLK_PDM_CLK { + pinmux = <0x443c0020 2 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_tpm_ch_tpm3_ch0: IOMUXC1_GPIO_IO04_TPM_CH_TPM3_CH0 { + pinmux = <0x443c0020 1 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_flexio_flexio_flexio1_flexio05: IOMUXC1_GPIO_IO05_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0024 7 0x443c0380 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_gpio_io_gpio2_io05: IOMUXC1_GPIO_IO05_GPIO_IO_GPIO2_IO05 { + pinmux = <0x443c0024 0 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO05_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c0024 6 0x443c03f0 1 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpspi_sin_lpspi7_sin: IOMUXC1_GPIO_IO05_LPSPI_SIN_LPSPI7_SIN { + pinmux = <0x443c0024 4 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpuart_rx_lpuart6_rx: IOMUXC1_GPIO_IO05_LPUART_RX_LPUART6_RX { + pinmux = <0x443c0024 5 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_mediamix_disp_data_mediamix_disp_data01: IOMUXC1_GPIO_IO05_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA01 { + pinmux = <0x443c0024 3 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO05_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0024 2 0x443c0438 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_tpm_ch_tpm4_ch0: IOMUXC1_GPIO_IO05_TPM_CH_TPM4_CH0 { + pinmux = <0x443c0024 1 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_flexio_flexio_flexio1_flexio06: IOMUXC1_GPIO_IO06_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0028 7 0x443c0384 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_gpio_io_gpio2_io06: IOMUXC1_GPIO_IO06_GPIO_IO_GPIO2_IO06 { + pinmux = <0x443c0028 0 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO06_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0028 6 0x443c03fc 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpspi_sout_lpspi7_sout: IOMUXC1_GPIO_IO06_LPSPI_SOUT_LPSPI7_SOUT { + pinmux = <0x443c0028 4 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpuart_cts_b_lpuart6_cts_b: IOMUXC1_GPIO_IO06_LPUART_CTS_B_LPUART6_CTS_B { + pinmux = <0x443c0028 5 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_mediamix_disp_data_mediamix_disp_data02: IOMUXC1_GPIO_IO06_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA02 { + pinmux = <0x443c0028 3 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO06_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0028 2 0x443c043c 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_tpm_ch_tpm5_ch0: IOMUXC1_GPIO_IO06_TPM_CH_TPM5_CH0 { + pinmux = <0x443c0028 1 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_flexio_flexio_flexio1_flexio07: IOMUXC1_GPIO_IO07_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c002c 7 0x443c0388 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_gpio_io_gpio2_io07: IOMUXC1_GPIO_IO07_GPIO_IO_GPIO2_IO07 { + pinmux = <0x443c002c 0 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO07_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c002c 6 0x443c03f8 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1: IOMUXC1_GPIO_IO07_LPSPI_PCS_LPSPI3_PCS1 { + pinmux = <0x443c002c 1 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_sck_lpspi7_sck: IOMUXC1_GPIO_IO07_LPSPI_SCK_LPSPI7_SCK { + pinmux = <0x443c002c 4 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpuart_rts_b_lpuart6_rts_b: IOMUXC1_GPIO_IO07_LPUART_RTS_B_LPUART6_RTS_B { + pinmux = <0x443c002c 5 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_cam_data_mediamix_cam_data01: IOMUXC1_GPIO_IO07_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA01 { + pinmux = <0x443c002c 2 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_disp_data_mediamix_disp_data03: IOMUXC1_GPIO_IO07_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA03 { + pinmux = <0x443c002c 3 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_flexio_flexio_flexio1_flexio08: IOMUXC1_GPIO_IO08_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0030 7 0x443c038c 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_gpio_io_gpio2_io08: IOMUXC1_GPIO_IO08_GPIO_IO_GPIO2_IO08 { + pinmux = <0x443c0030 0 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO08_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0030 6 0x443c03fc 1 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0: IOMUXC1_GPIO_IO08_LPSPI_PCS_LPSPI3_PCS0 { + pinmux = <0x443c0030 1 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpuart_tx_lpuart7_tx: IOMUXC1_GPIO_IO08_LPUART_TX_LPUART7_TX { + pinmux = <0x443c0030 5 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_cam_data_mediamix_cam_data02: IOMUXC1_GPIO_IO08_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA02 { + pinmux = <0x443c0030 2 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_disp_data_mediamix_disp_data04: IOMUXC1_GPIO_IO08_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA04 { + pinmux = <0x443c0030 3 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_tpm_ch_tpm6_ch0: IOMUXC1_GPIO_IO08_TPM_CH_TPM6_CH0 { + pinmux = <0x443c0030 4 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_flexio_flexio_flexio1_flexio09: IOMUXC1_GPIO_IO09_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c0034 7 0x443c0390 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_gpio_io_gpio2_io09: IOMUXC1_GPIO_IO09_GPIO_IO_GPIO2_IO09 { + pinmux = <0x443c0034 0 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO09_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c0034 6 0x443c03f8 1 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin: IOMUXC1_GPIO_IO09_LPSPI_SIN_LPSPI3_SIN { + pinmux = <0x443c0034 1 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpuart_rx_lpuart7_rx: IOMUXC1_GPIO_IO09_LPUART_RX_LPUART7_RX { + pinmux = <0x443c0034 5 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_cam_data_mediamix_cam_data03: IOMUXC1_GPIO_IO09_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA03 { + pinmux = <0x443c0034 2 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_disp_data_mediamix_disp_data05: IOMUXC1_GPIO_IO09_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA05 { + pinmux = <0x443c0034 3 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_tpm_extclk_tpm3_extclk: IOMUXC1_GPIO_IO09_TPM_EXTCLK_TPM3_EXTCLK { + pinmux = <0x443c0034 4 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_flexio_flexio_flexio1_flexio10: IOMUXC1_GPIO_IO10_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0038 7 0x443c0394 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_gpio_io_gpio2_io10: IOMUXC1_GPIO_IO10_GPIO_IO_GPIO2_IO10 { + pinmux = <0x443c0038 0 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO10_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0038 6 0x443c0404 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout: IOMUXC1_GPIO_IO10_LPSPI_SOUT_LPSPI3_SOUT { + pinmux = <0x443c0038 1 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpuart_cts_b_lpuart7_cts_b: IOMUXC1_GPIO_IO10_LPUART_CTS_B_LPUART7_CTS_B { + pinmux = <0x443c0038 5 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_cam_data_mediamix_cam_data04: IOMUXC1_GPIO_IO10_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA04 { + pinmux = <0x443c0038 2 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_disp_data_mediamix_disp_data06: IOMUXC1_GPIO_IO10_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA06 { + pinmux = <0x443c0038 3 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_tpm_extclk_tpm4_extclk: IOMUXC1_GPIO_IO10_TPM_EXTCLK_TPM4_EXTCLK { + pinmux = <0x443c0038 4 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_flexio_flexio_flexio1_flexio11: IOMUXC1_GPIO_IO11_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c003c 7 0x443c0398 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_gpio_io_gpio2_io11: IOMUXC1_GPIO_IO11_GPIO_IO_GPIO2_IO11 { + pinmux = <0x443c003c 0 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO11_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c003c 6 0x443c0400 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck: IOMUXC1_GPIO_IO11_LPSPI_SCK_LPSPI3_SCK { + pinmux = <0x443c003c 1 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpuart_rts_b_lpuart7_rts_b: IOMUXC1_GPIO_IO11_LPUART_RTS_B_LPUART7_RTS_B { + pinmux = <0x443c003c 5 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_cam_data_mediamix_cam_data05: IOMUXC1_GPIO_IO11_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA05 { + pinmux = <0x443c003c 2 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_disp_data_mediamix_disp_data07: IOMUXC1_GPIO_IO11_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA07 { + pinmux = <0x443c003c 3 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_tpm_extclk_tpm5_extclk: IOMUXC1_GPIO_IO11_TPM_EXTCLK_TPM5_EXTCLK { + pinmux = <0x443c003c 4 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_gpio_io_gpio2_io12: IOMUXC1_GPIO_IO12_GPIO_IO_GPIO2_IO12 { + pinmux = <0x443c0040 0 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO12_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0040 6 0x443c0404 1 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpspi_pcs_lpspi8_pcs0: IOMUXC1_GPIO_IO12_LPSPI_PCS_LPSPI8_PCS0 { + pinmux = <0x443c0040 4 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpuart_tx_lpuart8_tx: IOMUXC1_GPIO_IO12_LPUART_TX_LPUART8_TX { + pinmux = <0x443c0040 5 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_mediamix_disp_data_mediamix_disp_data08: IOMUXC1_GPIO_IO12_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA08 { + pinmux = <0x443c0040 3 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO12_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0040 2 0x443c0440 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO12_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c0040 7 0x443c0450 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_tpm_ch_tpm3_ch2: IOMUXC1_GPIO_IO12_TPM_CH_TPM3_CH2 { + pinmux = <0x443c0040 1 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_flexio_flexio_flexio1_flexio13: IOMUXC1_GPIO_IO13_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c0044 7 0x443c039c 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_gpio_io_gpio2_io13: IOMUXC1_GPIO_IO13_GPIO_IO_GPIO2_IO13 { + pinmux = <0x443c0044 0 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO13_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c0044 6 0x443c0400 1 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpspi_sin_lpspi8_sin: IOMUXC1_GPIO_IO13_LPSPI_SIN_LPSPI8_SIN { + pinmux = <0x443c0044 4 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpuart_rx_lpuart8_rx: IOMUXC1_GPIO_IO13_LPUART_RX_LPUART8_RX { + pinmux = <0x443c0044 5 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_mediamix_disp_data_mediamix_disp_data09: IOMUXC1_GPIO_IO13_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA09 { + pinmux = <0x443c0044 3 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO13_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c0044 2 0x443c0444 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_tpm_ch_tpm4_ch2: IOMUXC1_GPIO_IO13_TPM_CH_TPM4_CH2 { + pinmux = <0x443c0044 1 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_flexio_flexio_flexio1_flexio14: IOMUXC1_GPIO_IO14_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0048 7 0x443c03a0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_gpio_io_gpio2_io14: IOMUXC1_GPIO_IO14_GPIO_IO_GPIO2_IO14 { + pinmux = <0x443c0048 0 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpspi_sout_lpspi8_sout: IOMUXC1_GPIO_IO14_LPSPI_SOUT_LPSPI8_SOUT { + pinmux = <0x443c0048 4 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_cts_b_lpuart8_cts_b: IOMUXC1_GPIO_IO14_LPUART_CTS_B_LPUART8_CTS_B { + pinmux = <0x443c0048 5 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart3_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART3_TX { + pinmux = <0x443c0048 1 0x443c041c 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart4_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART4_TX { + pinmux = <0x443c0048 6 0x443c0428 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_cam_data_mediamix_cam_data06: IOMUXC1_GPIO_IO14_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA06 { + pinmux = <0x443c0048 2 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_disp_data_mediamix_disp_data10: IOMUXC1_GPIO_IO14_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA10 { + pinmux = <0x443c0048 3 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_flexio_flexio_flexio1_flexio15: IOMUXC1_GPIO_IO15_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c004c 7 0x443c03a4 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_gpio_io_gpio2_io15: IOMUXC1_GPIO_IO15_GPIO_IO_GPIO2_IO15 { + pinmux = <0x443c004c 0 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpspi_sck_lpspi8_sck: IOMUXC1_GPIO_IO15_LPSPI_SCK_LPSPI8_SCK { + pinmux = <0x443c004c 4 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rts_b_lpuart8_rts_b: IOMUXC1_GPIO_IO15_LPUART_RTS_B_LPUART8_RTS_B { + pinmux = <0x443c004c 5 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart3_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART3_RX { + pinmux = <0x443c004c 1 0x443c0418 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart4_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART4_RX { + pinmux = <0x443c004c 6 0x443c0424 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_cam_data_mediamix_cam_data07: IOMUXC1_GPIO_IO15_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA07 { + pinmux = <0x443c004c 2 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_disp_data_mediamix_disp_data11: IOMUXC1_GPIO_IO15_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA11 { + pinmux = <0x443c004c 3 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_flexio_flexio_flexio1_flexio16: IOMUXC1_GPIO_IO16_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0050 7 0x443c03a8 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_gpio_io_gpio2_io16: IOMUXC1_GPIO_IO16_GPIO_IO_GPIO2_IO16 { + pinmux = <0x443c0050 0 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpspi_pcs_lpspi4_pcs2: IOMUXC1_GPIO_IO16_LPSPI_PCS_LPSPI4_PCS2 { + pinmux = <0x443c0050 5 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c0050 4 0x443c0414 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0050 6 0x443c0420 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_mediamix_disp_data_mediamix_disp_data12: IOMUXC1_GPIO_IO16_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA12 { + pinmux = <0x443c0050 3 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO16_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0050 2 0x443c0440 1 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk: IOMUXC1_GPIO_IO16_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x443c0050 1 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_flexio_flexio_flexio1_flexio17: IOMUXC1_GPIO_IO17_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c0054 7 0x443c03ac 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_gpio_io_gpio2_io17: IOMUXC1_GPIO_IO17_GPIO_IO_GPIO2_IO17 { + pinmux = <0x443c0054 0 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpspi_pcs_lpspi4_pcs1: IOMUXC1_GPIO_IO17_LPSPI_PCS_LPSPI4_PCS1 { + pinmux = <0x443c0054 5 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c0054 4 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c0054 6 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_cam_data_mediamix_cam_data08: IOMUXC1_GPIO_IO17_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA08 { + pinmux = <0x443c0054 2 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_disp_data_mediamix_disp_data13: IOMUXC1_GPIO_IO17_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA13 { + pinmux = <0x443c0054 3 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_sai_mclk_sai3_mclk: IOMUXC1_GPIO_IO17_SAI_MCLK_SAI3_MCLK { + pinmux = <0x443c0054 1 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_flexio_flexio_flexio1_flexio18: IOMUXC1_GPIO_IO18_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0058 7 0x443c03b0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_gpio_io_gpio2_io18: IOMUXC1_GPIO_IO18_GPIO_IO_GPIO2_IO18 { + pinmux = <0x443c0058 0 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi4_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI4_PCS0 { + pinmux = <0x443c0058 5 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi5_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI5_PCS0 { + pinmux = <0x443c0058 4 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_cam_data_mediamix_cam_data09: IOMUXC1_GPIO_IO18_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA09 { + pinmux = <0x443c0058 2 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_disp_data_mediamix_disp_data14: IOMUXC1_GPIO_IO18_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA14 { + pinmux = <0x443c0058 3 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO18_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0058 1 0x443c044c 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_tpm_ch_tpm5_ch2: IOMUXC1_GPIO_IO18_TPM_CH_TPM5_CH2 { + pinmux = <0x443c0058 6 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_gpio_io_gpio2_io19: IOMUXC1_GPIO_IO19_GPIO_IO_GPIO2_IO19 { + pinmux = <0x443c005c 0 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi4_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI4_SIN { + pinmux = <0x443c005c 5 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi5_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI5_SIN { + pinmux = <0x443c005c 4 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_mediamix_disp_data_mediamix_disp_data15: IOMUXC1_GPIO_IO19_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA15 { + pinmux = <0x443c005c 3 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO19_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c005c 2 0x443c0444 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO19_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c005c 1 0x443c0450 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO19_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c005c 7 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_tpm_ch_tpm6_ch2: IOMUXC1_GPIO_IO19_TPM_CH_TPM6_CH2 { + pinmux = <0x443c005c 6 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_flexio_flexio_flexio1_flexio20: IOMUXC1_GPIO_IO20_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0060 7 0x443c03b4 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_gpio_io_gpio2_io20: IOMUXC1_GPIO_IO20_GPIO_IO_GPIO2_IO20 { + pinmux = <0x443c0060 0 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi4_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI4_SOUT { + pinmux = <0x443c0060 5 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi5_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI5_SOUT { + pinmux = <0x443c0060 4 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_mediamix_disp_data_mediamix_disp_data16: IOMUXC1_GPIO_IO20_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA16 { + pinmux = <0x443c0060 3 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO20_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0060 2 0x443c0438 1 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data00: IOMUXC1_GPIO_IO20_SAI_RX_DATA_SAI3_RX_DATA00 { + pinmux = <0x443c0060 1 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_tpm_ch_tpm3_ch1: IOMUXC1_GPIO_IO20_TPM_CH_TPM3_CH1 { + pinmux = <0x443c0060 6 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_gpio_io_gpio2_io21: IOMUXC1_GPIO_IO21_GPIO_IO_GPIO2_IO21 { + pinmux = <0x443c0064 0 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi4_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI4_SCK { + pinmux = <0x443c0064 5 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi5_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI5_SCK { + pinmux = <0x443c0064 4 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_mediamix_disp_data_mediamix_disp_data17: IOMUXC1_GPIO_IO21_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA17 { + pinmux = <0x443c0064 3 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO21_PDM_CLK_PDM_CLK { + pinmux = <0x443c0064 2 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO21_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0064 7 0x443c044c 1 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO21_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c0064 1 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_tpm_ch_tpm4_ch1: IOMUXC1_GPIO_IO21_TPM_CH_TPM4_CH1 { + pinmux = <0x443c0064 6 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_flexio_flexio_flexio1_flexio22: IOMUXC1_GPIO_IO22_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0068 7 0x443c03b8 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_gpio_io_gpio2_io22: IOMUXC1_GPIO_IO22_GPIO_IO_GPIO2_IO22 { + pinmux = <0x443c0068 0 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO22_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0068 6 0x443c03ec 1 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_mediamix_disp_data_mediamix_disp_data18: IOMUXC1_GPIO_IO22_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA18 { + pinmux = <0x443c0068 3 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_spdif_in_spdif_in: IOMUXC1_GPIO_IO22_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0068 2 0x443c0454 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_ch_tpm5_ch1: IOMUXC1_GPIO_IO22_TPM_CH_TPM5_CH1 { + pinmux = <0x443c0068 4 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_extclk_tpm6_extclk: IOMUXC1_GPIO_IO22_TPM_EXTCLK_TPM6_EXTCLK { + pinmux = <0x443c0068 5 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_usdhc_clk_usdhc3_clk: IOMUXC1_GPIO_IO22_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0068 1 0x443c0458 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_flexio_flexio_flexio1_flexio23: IOMUXC1_GPIO_IO23_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c006c 7 0x443c03bc 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_gpio_io_gpio2_io23: IOMUXC1_GPIO_IO23_GPIO_IO_GPIO2_IO23 { + pinmux = <0x443c006c 0 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO23_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c006c 6 0x443c03e8 1 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_mediamix_disp_data_mediamix_disp_data19: IOMUXC1_GPIO_IO23_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA19 { + pinmux = <0x443c006c 3 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_spdif_out_spdif_out: IOMUXC1_GPIO_IO23_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c006c 2 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_tpm_ch_tpm6_ch1: IOMUXC1_GPIO_IO23_TPM_CH_TPM6_CH1 { + pinmux = <0x443c006c 4 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_usdhc_cmd_usdhc3_cmd: IOMUXC1_GPIO_IO23_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c006c 1 0x443c045c 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_flexio_flexio_flexio1_flexio24: IOMUXC1_GPIO_IO24_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0070 7 0x443c03c0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_gpio_io_gpio2_io24: IOMUXC1_GPIO_IO24_GPIO_IO_GPIO2_IO24 { + pinmux = <0x443c0070 0 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_GPIO_IO24_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c0070 5 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_lpspi_pcs_lpspi6_pcs1: IOMUXC1_GPIO_IO24_LPSPI_PCS_LPSPI6_PCS1 { + pinmux = <0x443c0070 6 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_mediamix_disp_data_mediamix_disp_data20: IOMUXC1_GPIO_IO24_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA20 { + pinmux = <0x443c0070 3 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_tpm_ch_tpm3_ch3: IOMUXC1_GPIO_IO24_TPM_CH_TPM3_CH3 { + pinmux = <0x443c0070 4 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_usdhc_data_usdhc3_data0: IOMUXC1_GPIO_IO24_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0070 1 0x443c0460 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_can_tx_can2_tx: IOMUXC1_GPIO_IO25_CAN_TX_CAN2_TX { + pinmux = <0x443c0074 2 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_flexio_flexio_flexio1_flexio25: IOMUXC1_GPIO_IO25_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c0074 7 0x443c03c4 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_gpio_io_gpio2_io25: IOMUXC1_GPIO_IO25_GPIO_IO_GPIO2_IO25 { + pinmux = <0x443c0074 0 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_jtag_mux_tck_jtag_mux_tck: IOMUXC1_GPIO_IO25_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0074 5 0x443c03d4 1 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_lpspi_pcs_lpspi7_pcs1: IOMUXC1_GPIO_IO25_LPSPI_PCS_LPSPI7_PCS1 { + pinmux = <0x443c0074 6 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_mediamix_disp_data_mediamix_disp_data21: IOMUXC1_GPIO_IO25_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA21 { + pinmux = <0x443c0074 3 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_tpm_ch_tpm4_ch3: IOMUXC1_GPIO_IO25_TPM_CH_TPM4_CH3 { + pinmux = <0x443c0074 4 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_usdhc_data_usdhc3_data1: IOMUXC1_GPIO_IO25_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0074 1 0x443c0464 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_gpio_io_gpio2_io26: IOMUXC1_GPIO_IO26_GPIO_IO_GPIO2_IO26 { + pinmux = <0x443c0078 0 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_GPIO_IO26_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0078 5 0x443c03d8 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_lpspi_pcs_lpspi8_pcs1: IOMUXC1_GPIO_IO26_LPSPI_PCS_LPSPI8_PCS1 { + pinmux = <0x443c0078 6 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_mediamix_disp_data_mediamix_disp_data22: IOMUXC1_GPIO_IO26_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA22 { + pinmux = <0x443c0078 3 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO26_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0078 2 0x443c043c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync: IOMUXC1_GPIO_IO26_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x443c0078 7 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_tpm_ch_tpm5_ch3: IOMUXC1_GPIO_IO26_TPM_CH_TPM5_CH3 { + pinmux = <0x443c0078 4 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_usdhc_data_usdhc3_data2: IOMUXC1_GPIO_IO26_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0078 1 0x443c0468 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_can_rx_can2_rx: IOMUXC1_GPIO_IO27_CAN_RX_CAN2_RX { + pinmux = <0x443c007c 2 0x443c0364 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_flexio_flexio_flexio1_flexio27: IOMUXC1_GPIO_IO27_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c007c 7 0x443c03c8 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_gpio_io_gpio2_io27: IOMUXC1_GPIO_IO27_GPIO_IO_GPIO2_IO27 { + pinmux = <0x443c007c 0 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_jtag_mux_tms_jtag_mux_tms: IOMUXC1_GPIO_IO27_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c007c 5 0x443c03dc 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_lpspi_pcs_lpspi5_pcs1: IOMUXC1_GPIO_IO27_LPSPI_PCS_LPSPI5_PCS1 { + pinmux = <0x443c007c 6 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_mediamix_disp_data_mediamix_disp_data23: IOMUXC1_GPIO_IO27_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA23 { + pinmux = <0x443c007c 3 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_tpm_ch_tpm6_ch3: IOMUXC1_GPIO_IO27_TPM_CH_TPM6_CH3 { + pinmux = <0x443c007c 4 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_usdhc_data_usdhc3_data3: IOMUXC1_GPIO_IO27_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c007c 1 0x443c046c 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_flexio_flexio_flexio1_flexio28: IOMUXC1_GPIO_IO28_FLEXIO_FLEXIO_FLEXIO1_FLEXIO28 { + pinmux = <0x443c0080 7 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_gpio_io_gpio2_io28: IOMUXC1_GPIO_IO28_GPIO_IO_GPIO2_IO28 { + pinmux = <0x443c0080 0 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO28_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0080 1 0x443c03e4 1 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_flexio_flexio_flexio1_flexio29: IOMUXC1_GPIO_IO29_FLEXIO_FLEXIO_FLEXIO1_FLEXIO29 { + pinmux = <0x443c0084 7 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_gpio_io_gpio2_io29: IOMUXC1_GPIO_IO29_GPIO_IO_GPIO2_IO29 { + pinmux = <0x443c0084 0 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO29_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0084 1 0x443c03e0 1 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_gpio_io_gpio1_io00: IOMUXC1_I2C1_SCL_GPIO_IO_GPIO1_IO00 { + pinmux = <0x443c0170 5 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_i3c_scl_i3c1_scl: IOMUXC1_I2C1_SCL_I3C_SCL_I3C1_SCL { + pinmux = <0x443c0170 1 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl: IOMUXC1_I2C1_SCL_LPI2C_SCL_LPI2C1_SCL { + pinmux = <0x443c0170 0 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpuart_dcb_b_lpuart1_dcb_b: IOMUXC1_I2C1_SCL_LPUART_DCB_B_LPUART1_DCB_B { + pinmux = <0x443c0170 2 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_tpm_ch_tpm2_ch0: IOMUXC1_I2C1_SCL_TPM_CH_TPM2_CH0 { + pinmux = <0x443c0170 3 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_gpio_io_gpio1_io01: IOMUXC1_I2C1_SDA_GPIO_IO_GPIO1_IO01 { + pinmux = <0x443c0174 5 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_i3c_sda_i3c1_sda: IOMUXC1_I2C1_SDA_I3C_SDA_I3C1_SDA { + pinmux = <0x443c0174 1 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda: IOMUXC1_I2C1_SDA_LPI2C_SDA_LPI2C1_SDA { + pinmux = <0x443c0174 0 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpuart_rin_b_lpuart1_rin_b: IOMUXC1_I2C1_SDA_LPUART_RIN_B_LPUART1_RIN_B { + pinmux = <0x443c0174 2 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_tpm_ch_tpm2_ch1: IOMUXC1_I2C1_SDA_TPM_CH_TPM2_CH1 { + pinmux = <0x443c0174 3 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_gpio_io_gpio1_io02: IOMUXC1_I2C2_SCL_GPIO_IO_GPIO1_IO02 { + pinmux = <0x443c0178 5 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_b_i3c1_pur_b: IOMUXC1_I2C2_SCL_I3C_PUR_B_I3C1_PUR_B { + pinmux = <0x443c0178 6 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_i3c1_pur: IOMUXC1_I2C2_SCL_I3C_PUR_I3C1_PUR { + pinmux = <0x443c0178 1 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl: IOMUXC1_I2C2_SCL_LPI2C_SCL_LPI2C2_SCL { + pinmux = <0x443c0178 0 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpuart_dcb_b_lpuart2_dcb_b: IOMUXC1_I2C2_SCL_LPUART_DCB_B_LPUART2_DCB_B { + pinmux = <0x443c0178 2 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_sai_rx_sync_sai1_rx_sync: IOMUXC1_I2C2_SCL_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x443c0178 4 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_tpm_ch_tpm2_ch2: IOMUXC1_I2C2_SCL_TPM_CH_TPM2_CH2 { + pinmux = <0x443c0178 3 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_gpio_io_gpio1_io03: IOMUXC1_I2C2_SDA_GPIO_IO_GPIO1_IO03 { + pinmux = <0x443c017c 5 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda: IOMUXC1_I2C2_SDA_LPI2C_SDA_LPI2C2_SDA { + pinmux = <0x443c017c 0 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpuart_rin_b_lpuart2_rin_b: IOMUXC1_I2C2_SDA_LPUART_RIN_B_LPUART2_RIN_B { + pinmux = <0x443c017c 2 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_sai_rx_bclk_sai1_rx_bclk: IOMUXC1_I2C2_SDA_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x443c017c 4 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_tpm_ch_tpm2_ch3: IOMUXC1_I2C2_SDA_TPM_CH_TPM2_CH3 { + pinmux = <0x443c017c 3 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_can_rx_can1_rx: IOMUXC1_PDM_BIT_STREAM0_CAN_RX_CAN1_RX { + pinmux = <0x443c0194 6 0x443c0360 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09: IOMUXC1_PDM_BIT_STREAM0_GPIO_IO_GPIO1_IO09 { + pinmux = <0x443c0194 5 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lpspi_pcs_lpspi1_pcs1: IOMUXC1_PDM_BIT_STREAM0_LPSPI_PCS_LPSPI1_PCS1 { + pinmux = <0x443c0194 2 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lptmr_alt_lptmr1_alt2: IOMUXC1_PDM_BIT_STREAM0_LPTMR_ALT_LPTMR1_ALT2 { + pinmux = <0x443c0194 4 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_mqs_right_mqs1_right: IOMUXC1_PDM_BIT_STREAM0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c0194 1 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_PDM_BIT_STREAM0_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0194 0 0x443c0438 2 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_tpm_extclk_tpm1_extclk: IOMUXC1_PDM_BIT_STREAM0_TPM_EXTCLK_TPM1_EXTCLK { + pinmux = <0x443c0194 3 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0198 6 0x443c0368 1 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10: IOMUXC1_PDM_BIT_STREAM1_GPIO_IO_GPIO1_IO10 { + pinmux = <0x443c0198 5 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lpspi_pcs_lpspi2_pcs1: IOMUXC1_PDM_BIT_STREAM1_LPSPI_PCS_LPSPI2_PCS1 { + pinmux = <0x443c0198 2 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lptmr_alt_lptmr1_alt3: IOMUXC1_PDM_BIT_STREAM1_LPTMR_ALT_LPTMR1_ALT3 { + pinmux = <0x443c0198 4 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_nmi_glue_nmi_nmi_glue_nmi: IOMUXC1_PDM_BIT_STREAM1_NMI_GLUE_NMI_NMI_GLUE_NMI { + pinmux = <0x443c0198 1 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_PDM_BIT_STREAM1_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0198 0 0x443c043c 2 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_tpm_extclk_tpm2_extclk: IOMUXC1_PDM_BIT_STREAM1_TPM_EXTCLK_TPM2_EXTCLK { + pinmux = <0x443c0198 3 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_can_tx_can1_tx: IOMUXC1_PDM_CLK_CAN_TX_CAN1_TX { + pinmux = <0x443c0190 6 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_gpio_io_gpio1_io08: IOMUXC1_PDM_CLK_GPIO_IO_GPIO1_IO08 { + pinmux = <0x443c0190 5 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_lptmr_alt_lptmr1_alt1: IOMUXC1_PDM_CLK_LPTMR_ALT_LPTMR1_ALT1 { + pinmux = <0x443c0190 4 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_mqs_left_mqs1_left: IOMUXC1_PDM_CLK_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c0190 1 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_pdm_clk_pdm_clk: IOMUXC1_PDM_CLK_PDM_CLK_PDM_CLK { + pinmux = <0x443c0190 0 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_gpio_io_gpio1_io14: IOMUXC1_SAI1_RXD0_GPIO_IO_GPIO1_IO14 { + pinmux = <0x443c01a8 5 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpspi_sout_lpspi1_sout: IOMUXC1_SAI1_RXD0_LPSPI_SOUT_LPSPI1_SOUT { + pinmux = <0x443c01a8 2 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpuart_dsr_b_lpuart2_dsr_b: IOMUXC1_SAI1_RXD0_LPUART_DSR_B_LPUART2_DSR_B { + pinmux = <0x443c01a8 3 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_mqs_right_mqs1_right: IOMUXC1_SAI1_RXD0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c01a8 4 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_mclk_sai1_mclk: IOMUXC1_SAI1_RXD0_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c01a8 1 0x443c0448 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_rx_data_sai1_rx_data00: IOMUXC1_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA00 { + pinmux = <0x443c01a8 0 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_can_rx_can1_rx: IOMUXC1_SAI1_TXC_CAN_RX_CAN1_RX { + pinmux = <0x443c01a0 4 0x443c0360 1 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_gpio_io_gpio1_io12: IOMUXC1_SAI1_TXC_GPIO_IO_GPIO1_IO12 { + pinmux = <0x443c01a0 5 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpspi_sin_lpspi1_sin: IOMUXC1_SAI1_TXC_LPSPI_SIN_LPSPI1_SIN { + pinmux = <0x443c01a0 2 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_cts_b_lpuart2_cts_b: IOMUXC1_SAI1_TXC_LPUART_CTS_B_LPUART2_CTS_B { + pinmux = <0x443c01a0 1 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_dsr_b_lpuart1_dsr_b: IOMUXC1_SAI1_TXC_LPUART_DSR_B_LPUART1_DSR_B { + pinmux = <0x443c01a0 3 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC1_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x443c01a0 0 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_can_tx_can1_tx: IOMUXC1_SAI1_TXD0_CAN_TX_CAN1_TX { + pinmux = <0x443c01a4 4 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_gpio_io_gpio1_io13: IOMUXC1_SAI1_TXD0_GPIO_IO_GPIO1_IO13 { + pinmux = <0x443c01a4 5 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpspi_sck_lpspi1_sck: IOMUXC1_SAI1_TXD0_LPSPI_SCK_LPSPI1_SCK { + pinmux = <0x443c01a4 2 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_dtr_b_lpuart1_dtr_b: IOMUXC1_SAI1_TXD0_LPUART_DTR_B_LPUART1_DTR_B { + pinmux = <0x443c01a4 3 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_rts_b_lpuart2_rts_b: IOMUXC1_SAI1_TXD0_LPUART_RTS_B_LPUART2_RTS_B { + pinmux = <0x443c01a4 1 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_sai_tx_data_sai1_tx_data00: IOMUXC1_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA00 { + pinmux = <0x443c01a4 0 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_gpio_io_gpio1_io11: IOMUXC1_SAI1_TXFS_GPIO_IO_GPIO1_IO11 { + pinmux = <0x443c019c 5 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpspi_pcs_lpspi1_pcs0: IOMUXC1_SAI1_TXFS_LPSPI_PCS_LPSPI1_PCS0 { + pinmux = <0x443c019c 2 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpuart_dtr_b_lpuart2_dtr_b: IOMUXC1_SAI1_TXFS_LPUART_DTR_B_LPUART2_DTR_B { + pinmux = <0x443c019c 3 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_mqs_left_mqs1_left: IOMUXC1_SAI1_TXFS_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c019c 4 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_data_sai1_tx_data01: IOMUXC1_SAI1_TXFS_SAI_TX_DATA_SAI1_TX_DATA01 { + pinmux = <0x443c019c 1 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC1_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x443c019c 0 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_flexio_flexio_flexio1_flexio08: IOMUXC1_SD1_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0108 4 0x443c038c 1 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_gpio_io_gpio3_io08: IOMUXC1_SD1_CLK_GPIO_IO_GPIO3_IO08 { + pinmux = <0x443c0108 5 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC1_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x443c0108 0 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_flexio_flexio_flexio1_flexio09: IOMUXC1_SD1_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c010c 4 0x443c0390 1 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_gpio_io_gpio3_io09: IOMUXC1_SD1_CMD_GPIO_IO_GPIO3_IO09 { + pinmux = <0x443c010c 5 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC1_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x443c010c 0 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_flexio_flexio_flexio1_flexio10: IOMUXC1_SD1_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0110 4 0x443c0394 1 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_gpio_io_gpio3_io10: IOMUXC1_SD1_DATA0_GPIO_IO_GPIO3_IO10 { + pinmux = <0x443c0110 5 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC1_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x443c0110 0 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_flexio_flexio_flexio1_flexio11: IOMUXC1_SD1_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c0114 4 0x443c0398 1 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_gpio_io_gpio3_io11: IOMUXC1_SD1_DATA1_GPIO_IO_GPIO3_IO11 { + pinmux = <0x443c0114 5 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC1_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x443c0114 0 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_flexio_flexio_flexio1_flexio12: IOMUXC1_SD1_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO12 { + pinmux = <0x443c0118 4 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_gpio_io_gpio3_io12: IOMUXC1_SD1_DATA2_GPIO_IO_GPIO3_IO12 { + pinmux = <0x443c0118 5 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC1_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x443c0118 0 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexio_flexio_flexio1_flexio13: IOMUXC1_SD1_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c011c 4 0x443c039c 1 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexspi_a_ss_b_flexspi1_a_ss1_b: IOMUXC1_SD1_DATA3_FLEXSPI_A_SS_B_FLEXSPI1_A_SS1_B { + pinmux = <0x443c011c 1 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_gpio_io_gpio3_io13: IOMUXC1_SD1_DATA3_GPIO_IO_GPIO3_IO13 { + pinmux = <0x443c011c 5 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC1_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x443c011c 0 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexio_flexio_flexio1_flexio14: IOMUXC1_SD1_DATA4_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0120 4 0x443c03a0 1 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexspi_a_data_flexspi1_a_data04: IOMUXC1_SD1_DATA4_FLEXSPI_A_DATA_FLEXSPI1_A_DATA04 { + pinmux = <0x443c0120 1 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_gpio_io_gpio3_io14: IOMUXC1_SD1_DATA4_GPIO_IO_GPIO3_IO14 { + pinmux = <0x443c0120 5 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC1_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x443c0120 0 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexio_flexio_flexio1_flexio15: IOMUXC1_SD1_DATA5_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c0124 4 0x443c03a4 1 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexspi_a_data_flexspi1_a_data05: IOMUXC1_SD1_DATA5_FLEXSPI_A_DATA_FLEXSPI1_A_DATA05 { + pinmux = <0x443c0124 1 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_gpio_io_gpio3_io15: IOMUXC1_SD1_DATA5_GPIO_IO_GPIO3_IO15 { + pinmux = <0x443c0124 5 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC1_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x443c0124 0 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_reset_b_usdhc1_reset_b: IOMUXC1_SD1_DATA5_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x443c0124 2 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexio_flexio_flexio1_flexio16: IOMUXC1_SD1_DATA6_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0128 4 0x443c03a8 1 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexspi_a_data_flexspi1_a_data06: IOMUXC1_SD1_DATA6_FLEXSPI_A_DATA_FLEXSPI1_A_DATA06 { + pinmux = <0x443c0128 1 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_gpio_io_gpio3_io16: IOMUXC1_SD1_DATA6_GPIO_IO_GPIO3_IO16 { + pinmux = <0x443c0128 5 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_cd_b_usdhc1_cd_b: IOMUXC1_SD1_DATA6_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x443c0128 2 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC1_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x443c0128 0 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexio_flexio_flexio1_flexio17: IOMUXC1_SD1_DATA7_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c012c 4 0x443c03ac 1 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexspi_a_data_flexspi1_a_data07: IOMUXC1_SD1_DATA7_FLEXSPI_A_DATA_FLEXSPI1_A_DATA07 { + pinmux = <0x443c012c 1 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_gpio_io_gpio3_io17: IOMUXC1_SD1_DATA7_GPIO_IO_GPIO3_IO17 { + pinmux = <0x443c012c 5 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC1_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x443c012c 0 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_wp_usdhc1_wp: IOMUXC1_SD1_DATA7_USDHC_WP_USDHC1_WP { + pinmux = <0x443c012c 2 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexio_flexio_flexio1_flexio18: IOMUXC1_SD1_STROBE_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0130 4 0x443c03b0 1 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexspi_a_dqs_flexspi1_a_dqs: IOMUXC1_SD1_STROBE_FLEXSPI_A_DQS_FLEXSPI1_A_DQS { + pinmux = <0x443c0130 1 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_gpio_io_gpio3_io18: IOMUXC1_SD1_STROBE_GPIO_IO_GPIO3_IO18 { + pinmux = <0x443c0130 5 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC1_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x443c0130 0 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC1_SD2_CD_B_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x443c0150 1 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_flexio_flexio_flexio1_flexio00: IOMUXC1_SD2_CD_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0150 4 0x443c036c 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_gpio_io_gpio3_io00: IOMUXC1_SD2_CD_B_GPIO_IO_GPIO3_IO00 { + pinmux = <0x443c0150 5 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_i3c_scl_i3c2_scl: IOMUXC1_SD2_CD_B_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0150 2 0x443c03cc 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC1_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x443c0150 0 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe0: IOMUXC1_SD2_CLK_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE0 { + pinmux = <0x443c0154 6 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC1_SD2_CLK_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x443c0154 1 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_flexio_flexio_flexio1_flexio01: IOMUXC1_SD2_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0154 4 0x443c0370 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_gpio_io_gpio3_io01: IOMUXC1_SD2_CLK_GPIO_IO_GPIO3_IO01 { + pinmux = <0x443c0154 5 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_i3c_sda_i3c2_sda: IOMUXC1_SD2_CLK_I3C_SDA_I3C2_SDA { + pinmux = <0x443c0154 2 0x443c03d0 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC1_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x443c0154 0 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe1: IOMUXC1_SD2_CMD_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE1 { + pinmux = <0x443c0158 6 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_enet1_1588_event0_in_enet1_1588_event0_in: IOMUXC1_SD2_CMD_ENET1_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x443c0158 1 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_flexio_flexio_flexio1_flexio02: IOMUXC1_SD2_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0158 4 0x443c0374 1 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_gpio_io_gpio3_io02: IOMUXC1_SD2_CMD_GPIO_IO_GPIO3_IO02 { + pinmux = <0x443c0158 5 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_b_i3c2_pur_b: IOMUXC1_SD2_CMD_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c0158 3 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_i3c2_pur: IOMUXC1_SD2_CMD_I3C_PUR_I3C2_PUR { + pinmux = <0x443c0158 2 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC1_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x443c0158 0 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_can_tx_can2_tx: IOMUXC1_SD2_DATA0_CAN_TX_CAN2_TX { + pinmux = <0x443c015c 2 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe2: IOMUXC1_SD2_DATA0_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE2 { + pinmux = <0x443c015c 6 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_enet1_1588_event0_out_enet1_1588_event0_out: IOMUXC1_SD2_DATA0_ENET1_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x443c015c 1 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_flexio_flexio_flexio1_flexio03: IOMUXC1_SD2_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c015c 4 0x443c0378 1 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_gpio_io_gpio3_io03: IOMUXC1_SD2_DATA0_GPIO_IO_GPIO3_IO03 { + pinmux = <0x443c015c 5 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC1_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x443c015c 0 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_can_rx_can2_rx: IOMUXC1_SD2_DATA1_CAN_RX_CAN2_RX { + pinmux = <0x443c0160 2 0x443c0364 3 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_enet1_1588_event1_in_enet1_1588_event1_in: IOMUXC1_SD2_DATA1_ENET1_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x443c0160 1 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_flexio_flexio_flexio1_flexio04: IOMUXC1_SD2_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0160 4 0x443c037c 1 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_gpio_io_gpio3_io04: IOMUXC1_SD2_DATA1_GPIO_IO_GPIO3_IO04 { + pinmux = <0x443c0160 5 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC1_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x443c0160 0 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_enet1_1588_event1_out_enet1_1588_event1_out: IOMUXC1_SD2_DATA2_ENET1_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x443c0164 1 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_flexio_flexio_flexio1_flexio05: IOMUXC1_SD2_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0164 4 0x443c0380 1 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_gpio_io_gpio3_io05: IOMUXC1_SD2_DATA2_GPIO_IO_GPIO3_IO05 { + pinmux = <0x443c0164 5 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_mqs_right_mqs2_right: IOMUXC1_SD2_DATA2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0164 2 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC1_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x443c0164 0 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_flexio_flexio_flexio1_flexio06: IOMUXC1_SD2_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0168 4 0x443c0384 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_gpio_io_gpio3_io06: IOMUXC1_SD2_DATA3_GPIO_IO_GPIO3_IO06 { + pinmux = <0x443c0168 5 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_lptmr_alt_lptmr2_alt1: IOMUXC1_SD2_DATA3_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c0168 1 0x443c0408 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_mqs_left_mqs2_left: IOMUXC1_SD2_DATA3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0168 2 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC1_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x443c0168 0 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_ccmsrcgpcmix_system_reset_ccmsrcgpcmix_system_reset: IOMUXC1_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET_CCMSRCGPCMIX_SYSTEM_RESET { + pinmux = <0x443c016c 6 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_flexio_flexio_flexio1_flexio07: IOMUXC1_SD2_RESET_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c016c 4 0x443c0388 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_gpio_io_gpio3_io07: IOMUXC1_SD2_RESET_B_GPIO_IO_GPIO3_IO07 { + pinmux = <0x443c016c 5 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_lptmr_alt_lptmr2_alt2: IOMUXC1_SD2_RESET_B_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c016c 1 0x443c040c 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC1_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x443c016c 0 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0134 6 0x443c0368 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_flexio_flexio_flexio1_flexio19: IOMUXC1_SD2_VSELECT_FLEXIO_FLEXIO_FLEXIO1_FLEXIO19 { + pinmux = <0x443c0134 4 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_gpio_io_gpio3_io19: IOMUXC1_SD2_VSELECT_GPIO_IO_GPIO3_IO19 { + pinmux = <0x443c0134 5 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_lptmr_alt_lptmr2_alt3: IOMUXC1_SD2_VSELECT_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c0134 2 0x443c0410 1 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect: IOMUXC1_SD2_VSELECT_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x443c0134 0 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_wp_usdhc2_wp: IOMUXC1_SD2_VSELECT_USDHC_WP_USDHC2_WP { + pinmux = <0x443c0134 1 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexio_flexio_flexio1_flexio20: IOMUXC1_SD3_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0138 4 0x443c03b4 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexspi_a_sclk_flexspi1_a_sclk: IOMUXC1_SD3_CLK_FLEXSPI_A_SCLK_FLEXSPI1_A_SCLK { + pinmux = <0x443c0138 1 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_gpio_io_gpio3_io20: IOMUXC1_SD3_CLK_GPIO_IO_GPIO3_IO20 { + pinmux = <0x443c0138 5 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_usdhc_clk_usdhc3_clk: IOMUXC1_SD3_CLK_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0138 0 0x443c0458 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexio_flexio_flexio1_flexio21: IOMUXC1_SD3_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO21 { + pinmux = <0x443c013c 4 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexspi_a_ss_b_flexspi1_a_ss0_b: IOMUXC1_SD3_CMD_FLEXSPI_A_SS_B_FLEXSPI1_A_SS0_B { + pinmux = <0x443c013c 1 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_gpio_io_gpio3_io21: IOMUXC1_SD3_CMD_GPIO_IO_GPIO3_IO21 { + pinmux = <0x443c013c 5 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_usdhc_cmd_usdhc3_cmd: IOMUXC1_SD3_CMD_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c013c 0 0x443c045c 1 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexio_flexio_flexio1_flexio22: IOMUXC1_SD3_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0140 4 0x443c03b8 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexspi_a_data_flexspi1_a_data00: IOMUXC1_SD3_DATA0_FLEXSPI_A_DATA_FLEXSPI1_A_DATA00 { + pinmux = <0x443c0140 1 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_gpio_io_gpio3_io22: IOMUXC1_SD3_DATA0_GPIO_IO_GPIO3_IO22 { + pinmux = <0x443c0140 5 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_usdhc_data_usdhc3_data0: IOMUXC1_SD3_DATA0_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0140 0 0x443c0460 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexio_flexio_flexio1_flexio23: IOMUXC1_SD3_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c0144 4 0x443c03bc 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexspi_a_data_flexspi1_a_data01: IOMUXC1_SD3_DATA1_FLEXSPI_A_DATA_FLEXSPI1_A_DATA01 { + pinmux = <0x443c0144 1 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_gpio_io_gpio3_io23: IOMUXC1_SD3_DATA1_GPIO_IO_GPIO3_IO23 { + pinmux = <0x443c0144 5 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_usdhc_data_usdhc3_data1: IOMUXC1_SD3_DATA1_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0144 0 0x443c0464 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexio_flexio_flexio1_flexio24: IOMUXC1_SD3_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0148 4 0x443c03c0 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexspi_a_data_flexspi1_a_data02: IOMUXC1_SD3_DATA2_FLEXSPI_A_DATA_FLEXSPI1_A_DATA02 { + pinmux = <0x443c0148 1 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_gpio_io_gpio3_io24: IOMUXC1_SD3_DATA2_GPIO_IO_GPIO3_IO24 { + pinmux = <0x443c0148 5 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_usdhc_data_usdhc3_data2: IOMUXC1_SD3_DATA2_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0148 0 0x443c0468 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexio_flexio_flexio1_flexio25: IOMUXC1_SD3_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c014c 4 0x443c03c4 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexspi_a_data_flexspi1_a_data03: IOMUXC1_SD3_DATA3_FLEXSPI_A_DATA_FLEXSPI1_A_DATA03 { + pinmux = <0x443c014c 1 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_gpio_io_gpio3_io25: IOMUXC1_SD3_DATA3_GPIO_IO_GPIO3_IO25 { + pinmux = <0x443c014c 5 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_usdhc_data_usdhc3_data3: IOMUXC1_SD3_DATA3_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c014c 0 0x443c046c 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_gpio_io_gpio1_io04: IOMUXC1_UART1_RXD_GPIO_IO_GPIO1_IO04 { + pinmux = <0x443c0180 5 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpspi_sin_lpspi2_sin: IOMUXC1_UART1_RXD_LPSPI_SIN_LPSPI2_SIN { + pinmux = <0x443c0180 2 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx: IOMUXC1_UART1_RXD_LPUART_RX_LPUART1_RX { + pinmux = <0x443c0180 0 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_s400_uart_rx_s400_uart_rx: IOMUXC1_UART1_RXD_S400_UART_RX_S400_UART_RX { + pinmux = <0x443c0180 1 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_tpm_ch_tpm1_ch0: IOMUXC1_UART1_RXD_TPM_CH_TPM1_CH0 { + pinmux = <0x443c0180 3 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_gpio_io_gpio1_io05: IOMUXC1_UART1_TXD_GPIO_IO_GPIO1_IO05 { + pinmux = <0x443c0184 5 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpspi_pcs_lpspi2_pcs0: IOMUXC1_UART1_TXD_LPSPI_PCS_LPSPI2_PCS0 { + pinmux = <0x443c0184 2 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx: IOMUXC1_UART1_TXD_LPUART_TX_LPUART1_TX { + pinmux = <0x443c0184 0 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_s400_uart_tx_s400_uart_tx: IOMUXC1_UART1_TXD_S400_UART_TX_S400_UART_TX { + pinmux = <0x443c0184 1 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_tpm_ch_tpm1_ch1: IOMUXC1_UART1_TXD_TPM_CH_TPM1_CH1 { + pinmux = <0x443c0184 3 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_gpio_io_gpio1_io06: IOMUXC1_UART2_RXD_GPIO_IO_GPIO1_IO06 { + pinmux = <0x443c0188 5 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpspi_sout_lpspi2_sout: IOMUXC1_UART2_RXD_LPSPI_SOUT_LPSPI2_SOUT { + pinmux = <0x443c0188 2 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_cts_b_lpuart1_cts_b: IOMUXC1_UART2_RXD_LPUART_CTS_B_LPUART1_CTS_B { + pinmux = <0x443c0188 1 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx: IOMUXC1_UART2_RXD_LPUART_RX_LPUART2_RX { + pinmux = <0x443c0188 0 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_sai_mclk_sai1_mclk: IOMUXC1_UART2_RXD_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c0188 4 0x443c0448 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_tpm_ch_tpm1_ch2: IOMUXC1_UART2_RXD_TPM_CH_TPM1_CH2 { + pinmux = <0x443c0188 3 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_gpio_io_gpio1_io07: IOMUXC1_UART2_TXD_GPIO_IO_GPIO1_IO07 { + pinmux = <0x443c018c 5 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpspi_sck_lpspi2_sck: IOMUXC1_UART2_TXD_LPSPI_SCK_LPSPI2_SCK { + pinmux = <0x443c018c 2 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_rts_b_lpuart1_rts_b: IOMUXC1_UART2_TXD_LPUART_RTS_B_LPUART1_RTS_B { + pinmux = <0x443c018c 1 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx: IOMUXC1_UART2_TXD_LPUART_TX_LPUART2_TX { + pinmux = <0x443c018c 0 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_tpm_ch_tpm1_ch3: IOMUXC1_UART2_TXD_TPM_CH_TPM1_CH3 { + pinmux = <0x443c018c 3 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_gpio_io_gpio1_io15: IOMUXC1_WDOG_ANY_GPIO_IO_GPIO1_IO15 { + pinmux = <0x443c01ac 5 0x0 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_wdog_wdog_any_wdog1_wdog_any: IOMUXC1_WDOG_ANY_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x443c01ac 0 0x0 0 0x443c035c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx9352avtxm-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx9352avtxm-pinctrl.dtsi new file mode 100644 index 000000000..8c040b9dc --- /dev/null +++ b/dts/nxp/nxp_imx/mimx9352avtxm-pinctrl.dtsi @@ -0,0 +1,1831 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX9352AVTXM + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc1_ccm_clko1_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko1: IOMUXC1_CCM_CLKO1_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO1 { + pinmux = <0x443c0088 0 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_flexio_flexio_flexio1_flexio26: IOMUXC1_CCM_CLKO1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO26 { + pinmux = <0x443c0088 4 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_gpio_io_gpio3_io26: IOMUXC1_CCM_CLKO1_GPIO_IO_GPIO3_IO26 { + pinmux = <0x443c0088 5 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko2: IOMUXC1_CCM_CLKO2_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO2 { + pinmux = <0x443c008c 0 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_flexio_flexio_flexio1_flexio27: IOMUXC1_CCM_CLKO2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c008c 4 0x443c03c8 1 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_gpio_io_gpio3_io27: IOMUXC1_CCM_CLKO2_GPIO_IO_GPIO3_IO27 { + pinmux = <0x443c008c 5 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko3: IOMUXC1_CCM_CLKO3_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO3 { + pinmux = <0x443c0090 0 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_flexio_flexio_flexio2_flexio28: IOMUXC1_CCM_CLKO3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO28 { + pinmux = <0x443c0090 4 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_gpio_io_gpio4_io28: IOMUXC1_CCM_CLKO3_GPIO_IO_GPIO4_IO28 { + pinmux = <0x443c0090 5 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko4: IOMUXC1_CCM_CLKO4_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO4 { + pinmux = <0x443c0094 0 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_flexio_flexio_flexio2_flexio29: IOMUXC1_CCM_CLKO4_FLEXIO_FLEXIO_FLEXIO2_FLEXIO29 { + pinmux = <0x443c0094 4 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_gpio_io_gpio4_io29: IOMUXC1_CCM_CLKO4_GPIO_IO_GPIO4_IO29 { + pinmux = <0x443c0094 5 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_flexio_flexio_flexio1_flexio30: IOMUXC1_DAP_TCLK_SWCLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO30 { + pinmux = <0x443c0008 4 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30: IOMUXC1_DAP_TCLK_SWCLK_GPIO_IO_GPIO3_IO30 { + pinmux = <0x443c0008 5 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_jtag_mux_tck_jtag_mux_tck: IOMUXC1_DAP_TCLK_SWCLK_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0008 0 0x443c03d4 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_DAP_TCLK_SWCLK_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0008 6 0x443c042c 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_can_tx_can2_tx: IOMUXC1_DAP_TDI_CAN_TX_CAN2_TX { + pinmux = <0x443c0000 3 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_flexio_flexio_flexio2_flexio30: IOMUXC1_DAP_TDI_FLEXIO_FLEXIO_FLEXIO2_FLEXIO30 { + pinmux = <0x443c0000 4 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_gpio_io_gpio3_io28: IOMUXC1_DAP_TDI_GPIO_IO_GPIO3_IO28 { + pinmux = <0x443c0000 5 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_DAP_TDI_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0000 0 0x443c03d8 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_lpuart_rx_lpuart5_rx: IOMUXC1_DAP_TDI_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0000 6 0x443c0430 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_mqs_left_mqs2_left: IOMUXC1_DAP_TDI_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0000 1 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_can_rx_can2_rx: IOMUXC1_DAP_TDO_TRACESWO_CAN_RX_CAN2_RX { + pinmux = <0x443c000c 3 0x443c0364 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_flexio_flexio_flexio1_flexio31: IOMUXC1_DAP_TDO_TRACESWO_FLEXIO_FLEXIO_FLEXIO1_FLEXIO31 { + pinmux = <0x443c000c 4 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31: IOMUXC1_DAP_TDO_TRACESWO_GPIO_IO_GPIO3_IO31 { + pinmux = <0x443c000c 5 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_DAP_TDO_TRACESWO_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c000c 0 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_lpuart_tx_lpuart5_tx: IOMUXC1_DAP_TDO_TRACESWO_LPUART_TX_LPUART5_TX { + pinmux = <0x443c000c 6 0x443c0434 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_mqs_right_mqs2_right: IOMUXC1_DAP_TDO_TRACESWO_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c000c 1 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_flexio_flexio_flexio2_flexio31: IOMUXC1_DAP_TMS_SWDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO31 { + pinmux = <0x443c0004 4 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29: IOMUXC1_DAP_TMS_SWDIO_GPIO_IO_GPIO3_IO29 { + pinmux = <0x443c0004 5 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_jtag_mux_tms_jtag_mux_tms: IOMUXC1_DAP_TMS_SWDIO_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c0004 0 0x443c03dc 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_DAP_TMS_SWDIO_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c0004 6 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC1_ENET1_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x443c0098 0 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_flexio_flexio_flexio2_flexio00: IOMUXC1_ENET1_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO00 { + pinmux = <0x443c0098 4 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_gpio_io_gpio4_io00: IOMUXC1_ENET1_MDC_GPIO_IO_GPIO4_IO00 { + pinmux = <0x443c0098 5 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_hsiomix_otg_id_hsiomix_otg_id1: IOMUXC1_ENET1_MDC_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID1 { + pinmux = <0x443c0098 3 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_i3c_scl_i3c2_scl: IOMUXC1_ENET1_MDC_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0098 2 0x443c03cc 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_lpuart_dcb_b_lpuart3_dcb_b: IOMUXC1_ENET1_MDC_LPUART_DCB_B_LPUART3_DCB_B { + pinmux = <0x443c0098 1 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC1_ENET1_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x443c009c 0 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_flexio_flexio_flexio2_flexio01: IOMUXC1_ENET1_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO01 { + pinmux = <0x443c009c 4 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_gpio_io_gpio4_io01: IOMUXC1_ENET1_MDIO_GPIO_IO_GPIO4_IO01 { + pinmux = <0x443c009c 5 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_hsiomix_otg_pwr_hsiomix_otg_pwr1: IOMUXC1_ENET1_MDIO_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR1 { + pinmux = <0x443c009c 3 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_i3c_sda_i3c2_sda: IOMUXC1_ENET1_MDIO_I3C_SDA_I3C2_SDA { + pinmux = <0x443c009c 2 0x443c03d0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_lpuart_rin_b_lpuart3_rin_b: IOMUXC1_ENET1_MDIO_LPUART_RIN_B_LPUART3_RIN_B { + pinmux = <0x443c009c 1 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC1_ENET1_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x443c00c0 0 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_flexio_flexio_flexio2_flexio10: IOMUXC1_ENET1_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO10 { + pinmux = <0x443c00c0 4 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_gpio_io_gpio4_io10: IOMUXC1_ENET1_RD0_GPIO_IO_GPIO4_IO10 { + pinmux = <0x443c00c0 5 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_lpuart_rx_lpuart3_rx: IOMUXC1_ENET1_RD0_LPUART_RX_LPUART3_RX { + pinmux = <0x443c00c0 1 0x443c0418 1 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC1_ENET1_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x443c00c4 0 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_flexio_flexio_flexio2_flexio11: IOMUXC1_ENET1_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO11 { + pinmux = <0x443c00c4 4 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_gpio_io_gpio4_io11: IOMUXC1_ENET1_RD1_GPIO_IO_GPIO4_IO11 { + pinmux = <0x443c00c4 5 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lptmr_alt_lptmr2_alt1: IOMUXC1_ENET1_RD1_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c00c4 3 0x443c0408 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_ENET1_RD1_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c00c4 1 0x443c0414 1 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC1_ENET1_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x443c00c8 0 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_flexio_flexio_flexio2_flexio12: IOMUXC1_ENET1_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO12 { + pinmux = <0x443c00c8 4 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_gpio_io_gpio4_io12: IOMUXC1_ENET1_RD2_GPIO_IO_GPIO4_IO12 { + pinmux = <0x443c00c8 5 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_lptmr_alt_lptmr2_alt2: IOMUXC1_ENET1_RD2_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c00c8 3 0x443c040c 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC1_ENET1_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x443c00cc 0 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_flexio_flexio_flexio2_flexio13: IOMUXC1_ENET1_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO13 { + pinmux = <0x443c00cc 4 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_gpio_io_gpio4_io13: IOMUXC1_ENET1_RD3_GPIO_IO_GPIO4_IO13 { + pinmux = <0x443c00cc 5 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_lptmr_alt_lptmr2_alt3: IOMUXC1_ENET1_RD3_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c00cc 3 0x443c0410 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_ccm_enet_qos_clock_generate_rx_clk_ccm_enet_qos_clock_generate_rx_clk: IOMUXC1_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK { + pinmux = <0x443c00bc 0 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC1_ENET1_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x443c00bc 1 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_flexio_flexio_flexio2_flexio09: IOMUXC1_ENET1_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO09 { + pinmux = <0x443c00bc 4 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_gpio_io_gpio4_io09: IOMUXC1_ENET1_RXC_GPIO_IO_GPIO4_IO09 { + pinmux = <0x443c00bc 5 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC1_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x443c00b8 0 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_flexio_flexio_flexio2_flexio08: IOMUXC1_ENET1_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO08 { + pinmux = <0x443c00b8 4 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08: IOMUXC1_ENET1_RX_CTL_GPIO_IO_GPIO4_IO08 { + pinmux = <0x443c00b8 5 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_hsiomix_otg_pwr_hsiomix_otg_pwr2: IOMUXC1_ENET1_RX_CTL_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR2 { + pinmux = <0x443c00b8 3 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_lpuart_dsr_b_lpuart3_dsr_b: IOMUXC1_ENET1_RX_CTL_LPUART_DSR_B_LPUART3_DSR_B { + pinmux = <0x443c00b8 1 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC1_ENET1_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x443c00ac 0 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_flexio_flexio_flexio2_flexio05: IOMUXC1_ENET1_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO05 { + pinmux = <0x443c00ac 4 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_gpio_io_gpio4_io05: IOMUXC1_ENET1_TD0_GPIO_IO_GPIO4_IO05 { + pinmux = <0x443c00ac 5 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_lpuart_tx_lpuart3_tx: IOMUXC1_ENET1_TD0_LPUART_TX_LPUART3_TX { + pinmux = <0x443c00ac 1 0x443c041c 1 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC1_ENET1_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x443c00a8 0 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_flexio_flexio_flexio2_flexio04: IOMUXC1_ENET1_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO04 { + pinmux = <0x443c00a8 4 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_gpio_io_gpio4_io04: IOMUXC1_ENET1_TD1_GPIO_IO_GPIO4_IO04 { + pinmux = <0x443c00a8 5 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_hsiomix_otg_oc_hsiomix_otg_oc1: IOMUXC1_ENET1_TD1_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC1 { + pinmux = <0x443c00a8 3 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_b_i3c2_pur_b: IOMUXC1_ENET1_TD1_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c00a8 6 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_i3c2_pur: IOMUXC1_ENET1_TD1_I3C_PUR_I3C2_PUR { + pinmux = <0x443c00a8 2 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_ENET1_TD1_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c00a8 1 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_can_rx_can2_rx: IOMUXC1_ENET1_TD2_CAN_RX_CAN2_RX { + pinmux = <0x443c00a4 2 0x443c0364 2 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_ccm_enet_qos_clock_generate_ref_clk_ccm_enet_qos_clock_generate_ref_clk: IOMUXC1_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK { + pinmux = <0x443c00a4 1 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC1_ENET1_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x443c00a4 0 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_flexio_flexio_flexio2_flexio03: IOMUXC1_ENET1_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO03 { + pinmux = <0x443c00a4 4 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_gpio_io_gpio4_io03: IOMUXC1_ENET1_TD2_GPIO_IO_GPIO4_IO03 { + pinmux = <0x443c00a4 5 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_hsiomix_otg_oc_hsiomix_otg_oc2: IOMUXC1_ENET1_TD2_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC2 { + pinmux = <0x443c00a4 3 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_can_tx_can2_tx: IOMUXC1_ENET1_TD3_CAN_TX_CAN2_TX { + pinmux = <0x443c00a0 2 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC1_ENET1_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x443c00a0 0 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_flexio_flexio_flexio2_flexio02: IOMUXC1_ENET1_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO02 { + pinmux = <0x443c00a0 4 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_gpio_io_gpio4_io02: IOMUXC1_ENET1_TD3_GPIO_IO_GPIO4_IO02 { + pinmux = <0x443c00a0 5 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_hsiomix_otg_id_hsiomix_otg_id2: IOMUXC1_ENET1_TD3_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID2 { + pinmux = <0x443c00a0 3 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_ccm_enet_qos_clock_generate_tx_clk_ccm_enet_qos_clock_generate_tx_clk: IOMUXC1_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK { + pinmux = <0x443c00b4 0 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC1_ENET1_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x443c00b4 1 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_flexio_flexio_flexio2_flexio07: IOMUXC1_ENET1_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO07 { + pinmux = <0x443c00b4 4 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_gpio_io_gpio4_io07: IOMUXC1_ENET1_TXC_GPIO_IO_GPIO4_IO07 { + pinmux = <0x443c00b4 5 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC1_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x443c00b0 0 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_flexio_flexio_flexio2_flexio06: IOMUXC1_ENET1_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO06 { + pinmux = <0x443c00b0 4 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06: IOMUXC1_ENET1_TX_CTL_GPIO_IO_GPIO4_IO06 { + pinmux = <0x443c00b0 5 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_lpuart_dtr_b_lpuart3_dtr_b: IOMUXC1_ENET1_TX_CTL_LPUART_DTR_B_LPUART3_DTR_B { + pinmux = <0x443c00b0 1 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_enet_mdc_enet1_mdc: IOMUXC1_ENET2_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x443c00d0 0 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_flexio_flexio_flexio2_flexio14: IOMUXC1_ENET2_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO14 { + pinmux = <0x443c00d0 4 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_gpio_io_gpio4_io14: IOMUXC1_ENET2_MDC_GPIO_IO_GPIO4_IO14 { + pinmux = <0x443c00d0 5 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_lpuart_dcb_b_lpuart4_dcb_b: IOMUXC1_ENET2_MDC_LPUART_DCB_B_LPUART4_DCB_B { + pinmux = <0x443c00d0 1 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_sai_rx_sync_sai2_rx_sync: IOMUXC1_ENET2_MDC_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x443c00d0 2 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_enet_mdio_enet1_mdio: IOMUXC1_ENET2_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x443c00d4 0 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_flexio_flexio_flexio2_flexio15: IOMUXC1_ENET2_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO15 { + pinmux = <0x443c00d4 4 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_gpio_io_gpio4_io15: IOMUXC1_ENET2_MDIO_GPIO_IO_GPIO4_IO15 { + pinmux = <0x443c00d4 5 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_lpuart_rin_b_lpuart4_rin_b: IOMUXC1_ENET2_MDIO_LPUART_RIN_B_LPUART4_RIN_B { + pinmux = <0x443c00d4 1 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_sai_rx_bclk_sai2_rx_bclk: IOMUXC1_ENET2_MDIO_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x443c00d4 2 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC1_ENET2_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x443c00f8 0 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_flexio_flexio_flexio2_flexio24: IOMUXC1_ENET2_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO24 { + pinmux = <0x443c00f8 4 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_gpio_io_gpio4_io24: IOMUXC1_ENET2_RD0_GPIO_IO_GPIO4_IO24 { + pinmux = <0x443c00f8 5 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_lpuart_rx_lpuart4_rx: IOMUXC1_ENET2_RD0_LPUART_RX_LPUART4_RX { + pinmux = <0x443c00f8 1 0x443c0424 1 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_sai_tx_data_sai2_tx_data02: IOMUXC1_ENET2_RD0_SAI_TX_DATA_SAI2_TX_DATA02 { + pinmux = <0x443c00f8 2 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC1_ENET2_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x443c00fc 0 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_flexio_flexio_flexio2_flexio25: IOMUXC1_ENET2_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO25 { + pinmux = <0x443c00fc 4 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_gpio_io_gpio4_io25: IOMUXC1_ENET2_RD1_GPIO_IO_GPIO4_IO25 { + pinmux = <0x443c00fc 5 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_sai_tx_data_sai2_tx_data03: IOMUXC1_ENET2_RD1_SAI_TX_DATA_SAI2_TX_DATA03 { + pinmux = <0x443c00fc 2 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_spdif_in_spdif_in: IOMUXC1_ENET2_RD1_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c00fc 1 0x443c0454 1 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC1_ENET2_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x443c0100 0 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_flexio_flexio_flexio2_flexio26: IOMUXC1_ENET2_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO26 { + pinmux = <0x443c0100 4 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_gpio_io_gpio4_io26: IOMUXC1_ENET2_RD2_GPIO_IO_GPIO4_IO26 { + pinmux = <0x443c0100 5 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_ENET2_RD2_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0100 1 0x443c0420 1 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_mqs_right_mqs2_right: IOMUXC1_ENET2_RD2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0100 3 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_sai_mclk_sai2_mclk: IOMUXC1_ENET2_RD2_SAI_MCLK_SAI2_MCLK { + pinmux = <0x443c0100 2 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC1_ENET2_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x443c0104 0 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_flexio_flexio_flexio2_flexio27: IOMUXC1_ENET2_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO27 { + pinmux = <0x443c0104 4 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_gpio_io_gpio4_io27: IOMUXC1_ENET2_RD3_GPIO_IO_GPIO4_IO27 { + pinmux = <0x443c0104 5 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_mqs_left_mqs2_left: IOMUXC1_ENET2_RD3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0104 3 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_in_spdif_in: IOMUXC1_ENET2_RD3_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0104 2 0x443c0454 2 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_out_spdif_out: IOMUXC1_ENET2_RD3_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c0104 1 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC1_ENET2_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x443c00f4 0 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rx_er_enet1_rx_er: IOMUXC1_ENET2_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x443c00f4 1 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_flexio_flexio_flexio2_flexio23: IOMUXC1_ENET2_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO23 { + pinmux = <0x443c00f4 4 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_gpio_io_gpio4_io23: IOMUXC1_ENET2_RXC_GPIO_IO_GPIO4_IO23 { + pinmux = <0x443c00f4 5 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_sai_tx_data_sai2_tx_data01: IOMUXC1_ENET2_RXC_SAI_TX_DATA_SAI2_TX_DATA01 { + pinmux = <0x443c00f4 2 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC1_ENET2_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x443c00f0 0 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_flexio_flexio_flexio2_flexio22: IOMUXC1_ENET2_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO22 { + pinmux = <0x443c00f0 4 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22: IOMUXC1_ENET2_RX_CTL_GPIO_IO_GPIO4_IO22 { + pinmux = <0x443c00f0 5 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_lpuart_dsr_b_lpuart4_dsr_b: IOMUXC1_ENET2_RX_CTL_LPUART_DSR_B_LPUART4_DSR_B { + pinmux = <0x443c00f0 1 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_sai_tx_data_sai2_tx_data00: IOMUXC1_ENET2_RX_CTL_SAI_TX_DATA_SAI2_TX_DATA00 { + pinmux = <0x443c00f0 2 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC1_ENET2_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x443c00e4 0 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_flexio_flexio_flexio2_flexio19: IOMUXC1_ENET2_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO19 { + pinmux = <0x443c00e4 4 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_gpio_io_gpio4_io19: IOMUXC1_ENET2_TD0_GPIO_IO_GPIO4_IO19 { + pinmux = <0x443c00e4 5 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_lpuart_tx_lpuart4_tx: IOMUXC1_ENET2_TD0_LPUART_TX_LPUART4_TX { + pinmux = <0x443c00e4 1 0x443c0428 1 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_sai_rx_data_sai2_rx_data03: IOMUXC1_ENET2_TD0_SAI_RX_DATA_SAI2_RX_DATA03 { + pinmux = <0x443c00e4 2 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC1_ENET2_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x443c00e0 0 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_flexio_flexio_flexio2_flexio18: IOMUXC1_ENET2_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO18 { + pinmux = <0x443c00e0 4 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_gpio_io_gpio4_io18: IOMUXC1_ENET2_TD1_GPIO_IO_GPIO4_IO18 { + pinmux = <0x443c00e0 5 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_ENET2_TD1_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c00e0 1 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_sai_rx_data_sai2_rx_data02: IOMUXC1_ENET2_TD1_SAI_RX_DATA_SAI2_RX_DATA02 { + pinmux = <0x443c00e0 2 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC1_ENET2_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x443c00dc 0 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_tx_clk_enet1_tx_clk: IOMUXC1_ENET2_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x443c00dc 1 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_flexio_flexio_flexio2_flexio17: IOMUXC1_ENET2_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO17 { + pinmux = <0x443c00dc 4 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_gpio_io_gpio4_io17: IOMUXC1_ENET2_TD2_GPIO_IO_GPIO4_IO17 { + pinmux = <0x443c00dc 5 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_sai_rx_data_sai2_rx_data01: IOMUXC1_ENET2_TD2_SAI_RX_DATA_SAI2_RX_DATA01 { + pinmux = <0x443c00dc 2 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC1_ENET2_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x443c00d8 0 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_flexio_flexio_flexio2_flexio16: IOMUXC1_ENET2_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO16 { + pinmux = <0x443c00d8 4 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_gpio_io_gpio4_io16: IOMUXC1_ENET2_TD3_GPIO_IO_GPIO4_IO16 { + pinmux = <0x443c00d8 5 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_sai_rx_data_sai2_rx_data00: IOMUXC1_ENET2_TD3_SAI_RX_DATA_SAI2_RX_DATA00 { + pinmux = <0x443c00d8 2 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC1_ENET2_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x443c00ec 0 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_tx_er_enet1_tx_er: IOMUXC1_ENET2_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x443c00ec 1 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_flexio_flexio_flexio2_flexio21: IOMUXC1_ENET2_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO21 { + pinmux = <0x443c00ec 4 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_gpio_io_gpio4_io21: IOMUXC1_ENET2_TXC_GPIO_IO_GPIO4_IO21 { + pinmux = <0x443c00ec 5 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC1_ENET2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x443c00ec 2 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC1_ENET2_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x443c00e8 0 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_flexio_flexio_flexio2_flexio20: IOMUXC1_ENET2_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO20 { + pinmux = <0x443c00e8 4 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20: IOMUXC1_ENET2_TX_CTL_GPIO_IO_GPIO4_IO20 { + pinmux = <0x443c00e8 5 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_lpuart_dtr_b_lpuart4_dtr_b: IOMUXC1_ENET2_TX_CTL_LPUART_DTR_B_LPUART4_DTR_B { + pinmux = <0x443c00e8 1 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_sai_tx_sync_sai2_tx_sync: IOMUXC1_ENET2_TX_CTL_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x443c00e8 2 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_flexio_flexio_flexio1_flexio00: IOMUXC1_GPIO_IO00_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0010 7 0x443c036c 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_gpio_io_gpio2_io00: IOMUXC1_GPIO_IO00_GPIO_IO_GPIO2_IO00 { + pinmux = <0x443c0010 0 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0010 1 0x443c03e4 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0010 6 0x443c03ec 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpspi_pcs_lpspi6_pcs0: IOMUXC1_GPIO_IO00_LPSPI_PCS_LPSPI6_PCS0 { + pinmux = <0x443c0010 4 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpuart_tx_lpuart5_tx: IOMUXC1_GPIO_IO00_LPUART_TX_LPUART5_TX { + pinmux = <0x443c0010 5 0x443c0434 1 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_cam_clk_mediamix_cam_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_CAM_CLK_MEDIAMIX_CAM_CLK { + pinmux = <0x443c0010 2 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_disp_clk_mediamix_disp_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_DISP_CLK_MEDIAMIX_DISP_CLK { + pinmux = <0x443c0010 3 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_flexio_flexio_flexio1_flexio01: IOMUXC1_GPIO_IO01_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0014 7 0x443c0370 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_gpio_io_gpio2_io01: IOMUXC1_GPIO_IO01_GPIO_IO_GPIO2_IO01 { + pinmux = <0x443c0014 0 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0014 1 0x443c03e0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c0014 6 0x443c03e8 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpspi_sin_lpspi6_sin: IOMUXC1_GPIO_IO01_LPSPI_SIN_LPSPI6_SIN { + pinmux = <0x443c0014 4 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpuart_rx_lpuart5_rx: IOMUXC1_GPIO_IO01_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0014 5 0x443c0430 1 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_cam_data_mediamix_cam_data00: IOMUXC1_GPIO_IO01_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA00 { + pinmux = <0x443c0014 2 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_disp_de_mediamix_disp_de: IOMUXC1_GPIO_IO01_MEDIAMIX_DISP_DE_MEDIAMIX_DISP_DE { + pinmux = <0x443c0014 3 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_flexio_flexio_flexio1_flexio02: IOMUXC1_GPIO_IO02_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0018 7 0x443c0374 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_gpio_io_gpio2_io02: IOMUXC1_GPIO_IO02_GPIO_IO_GPIO2_IO02 { + pinmux = <0x443c0018 0 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C4_SDA { + pinmux = <0x443c0018 1 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0018 6 0x443c03f4 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpspi_sout_lpspi6_sout: IOMUXC1_GPIO_IO02_LPSPI_SOUT_LPSPI6_SOUT { + pinmux = <0x443c0018 4 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_GPIO_IO02_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0018 5 0x443c042c 1 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_cam_vsync_mediamix_cam_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_CAM_VSYNC_MEDIAMIX_CAM_VSYNC { + pinmux = <0x443c0018 2 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_disp_vsync_mediamix_disp_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_DISP_VSYNC_MEDIAMIX_DISP_VSYNC { + pinmux = <0x443c0018 3 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_flexio_flexio_flexio1_flexio03: IOMUXC1_GPIO_IO03_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c001c 7 0x443c0378 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_gpio_io_gpio2_io03: IOMUXC1_GPIO_IO03_GPIO_IO_GPIO2_IO03 { + pinmux = <0x443c001c 0 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C4_SCL { + pinmux = <0x443c001c 1 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c001c 6 0x443c03f0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpspi_sck_lpspi6_sck: IOMUXC1_GPIO_IO03_LPSPI_SCK_LPSPI6_SCK { + pinmux = <0x443c001c 4 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_GPIO_IO03_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c001c 5 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_cam_hsync_mediamix_cam_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_CAM_HSYNC_MEDIAMIX_CAM_HSYNC { + pinmux = <0x443c001c 2 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_disp_hsync_mediamix_disp_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_DISP_HSYNC_MEDIAMIX_DISP_HSYNC { + pinmux = <0x443c001c 3 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_flexio_flexio_flexio1_flexio04: IOMUXC1_GPIO_IO04_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0020 7 0x443c037c 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_gpio_io_gpio2_io04: IOMUXC1_GPIO_IO04_GPIO_IO_GPIO2_IO04 { + pinmux = <0x443c0020 0 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO04_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0020 6 0x443c03f4 1 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpspi_pcs_lpspi7_pcs0: IOMUXC1_GPIO_IO04_LPSPI_PCS_LPSPI7_PCS0 { + pinmux = <0x443c0020 4 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpuart_tx_lpuart6_tx: IOMUXC1_GPIO_IO04_LPUART_TX_LPUART6_TX { + pinmux = <0x443c0020 5 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_mediamix_disp_data_mediamix_disp_data00: IOMUXC1_GPIO_IO04_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA00 { + pinmux = <0x443c0020 3 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO04_PDM_CLK_PDM_CLK { + pinmux = <0x443c0020 2 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_tpm_ch_tpm3_ch0: IOMUXC1_GPIO_IO04_TPM_CH_TPM3_CH0 { + pinmux = <0x443c0020 1 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_flexio_flexio_flexio1_flexio05: IOMUXC1_GPIO_IO05_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0024 7 0x443c0380 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_gpio_io_gpio2_io05: IOMUXC1_GPIO_IO05_GPIO_IO_GPIO2_IO05 { + pinmux = <0x443c0024 0 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO05_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c0024 6 0x443c03f0 1 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpspi_sin_lpspi7_sin: IOMUXC1_GPIO_IO05_LPSPI_SIN_LPSPI7_SIN { + pinmux = <0x443c0024 4 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpuart_rx_lpuart6_rx: IOMUXC1_GPIO_IO05_LPUART_RX_LPUART6_RX { + pinmux = <0x443c0024 5 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_mediamix_disp_data_mediamix_disp_data01: IOMUXC1_GPIO_IO05_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA01 { + pinmux = <0x443c0024 3 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO05_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0024 2 0x443c0438 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_tpm_ch_tpm4_ch0: IOMUXC1_GPIO_IO05_TPM_CH_TPM4_CH0 { + pinmux = <0x443c0024 1 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_flexio_flexio_flexio1_flexio06: IOMUXC1_GPIO_IO06_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0028 7 0x443c0384 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_gpio_io_gpio2_io06: IOMUXC1_GPIO_IO06_GPIO_IO_GPIO2_IO06 { + pinmux = <0x443c0028 0 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO06_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0028 6 0x443c03fc 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpspi_sout_lpspi7_sout: IOMUXC1_GPIO_IO06_LPSPI_SOUT_LPSPI7_SOUT { + pinmux = <0x443c0028 4 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpuart_cts_b_lpuart6_cts_b: IOMUXC1_GPIO_IO06_LPUART_CTS_B_LPUART6_CTS_B { + pinmux = <0x443c0028 5 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_mediamix_disp_data_mediamix_disp_data02: IOMUXC1_GPIO_IO06_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA02 { + pinmux = <0x443c0028 3 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO06_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0028 2 0x443c043c 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_tpm_ch_tpm5_ch0: IOMUXC1_GPIO_IO06_TPM_CH_TPM5_CH0 { + pinmux = <0x443c0028 1 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_flexio_flexio_flexio1_flexio07: IOMUXC1_GPIO_IO07_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c002c 7 0x443c0388 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_gpio_io_gpio2_io07: IOMUXC1_GPIO_IO07_GPIO_IO_GPIO2_IO07 { + pinmux = <0x443c002c 0 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO07_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c002c 6 0x443c03f8 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1: IOMUXC1_GPIO_IO07_LPSPI_PCS_LPSPI3_PCS1 { + pinmux = <0x443c002c 1 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_sck_lpspi7_sck: IOMUXC1_GPIO_IO07_LPSPI_SCK_LPSPI7_SCK { + pinmux = <0x443c002c 4 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpuart_rts_b_lpuart6_rts_b: IOMUXC1_GPIO_IO07_LPUART_RTS_B_LPUART6_RTS_B { + pinmux = <0x443c002c 5 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_cam_data_mediamix_cam_data01: IOMUXC1_GPIO_IO07_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA01 { + pinmux = <0x443c002c 2 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_disp_data_mediamix_disp_data03: IOMUXC1_GPIO_IO07_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA03 { + pinmux = <0x443c002c 3 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_flexio_flexio_flexio1_flexio08: IOMUXC1_GPIO_IO08_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0030 7 0x443c038c 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_gpio_io_gpio2_io08: IOMUXC1_GPIO_IO08_GPIO_IO_GPIO2_IO08 { + pinmux = <0x443c0030 0 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO08_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0030 6 0x443c03fc 1 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0: IOMUXC1_GPIO_IO08_LPSPI_PCS_LPSPI3_PCS0 { + pinmux = <0x443c0030 1 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpuart_tx_lpuart7_tx: IOMUXC1_GPIO_IO08_LPUART_TX_LPUART7_TX { + pinmux = <0x443c0030 5 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_cam_data_mediamix_cam_data02: IOMUXC1_GPIO_IO08_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA02 { + pinmux = <0x443c0030 2 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_disp_data_mediamix_disp_data04: IOMUXC1_GPIO_IO08_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA04 { + pinmux = <0x443c0030 3 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_tpm_ch_tpm6_ch0: IOMUXC1_GPIO_IO08_TPM_CH_TPM6_CH0 { + pinmux = <0x443c0030 4 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_flexio_flexio_flexio1_flexio09: IOMUXC1_GPIO_IO09_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c0034 7 0x443c0390 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_gpio_io_gpio2_io09: IOMUXC1_GPIO_IO09_GPIO_IO_GPIO2_IO09 { + pinmux = <0x443c0034 0 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO09_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c0034 6 0x443c03f8 1 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin: IOMUXC1_GPIO_IO09_LPSPI_SIN_LPSPI3_SIN { + pinmux = <0x443c0034 1 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpuart_rx_lpuart7_rx: IOMUXC1_GPIO_IO09_LPUART_RX_LPUART7_RX { + pinmux = <0x443c0034 5 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_cam_data_mediamix_cam_data03: IOMUXC1_GPIO_IO09_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA03 { + pinmux = <0x443c0034 2 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_disp_data_mediamix_disp_data05: IOMUXC1_GPIO_IO09_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA05 { + pinmux = <0x443c0034 3 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_tpm_extclk_tpm3_extclk: IOMUXC1_GPIO_IO09_TPM_EXTCLK_TPM3_EXTCLK { + pinmux = <0x443c0034 4 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_flexio_flexio_flexio1_flexio10: IOMUXC1_GPIO_IO10_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0038 7 0x443c0394 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_gpio_io_gpio2_io10: IOMUXC1_GPIO_IO10_GPIO_IO_GPIO2_IO10 { + pinmux = <0x443c0038 0 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO10_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0038 6 0x443c0404 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout: IOMUXC1_GPIO_IO10_LPSPI_SOUT_LPSPI3_SOUT { + pinmux = <0x443c0038 1 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpuart_cts_b_lpuart7_cts_b: IOMUXC1_GPIO_IO10_LPUART_CTS_B_LPUART7_CTS_B { + pinmux = <0x443c0038 5 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_cam_data_mediamix_cam_data04: IOMUXC1_GPIO_IO10_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA04 { + pinmux = <0x443c0038 2 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_disp_data_mediamix_disp_data06: IOMUXC1_GPIO_IO10_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA06 { + pinmux = <0x443c0038 3 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_tpm_extclk_tpm4_extclk: IOMUXC1_GPIO_IO10_TPM_EXTCLK_TPM4_EXTCLK { + pinmux = <0x443c0038 4 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_flexio_flexio_flexio1_flexio11: IOMUXC1_GPIO_IO11_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c003c 7 0x443c0398 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_gpio_io_gpio2_io11: IOMUXC1_GPIO_IO11_GPIO_IO_GPIO2_IO11 { + pinmux = <0x443c003c 0 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO11_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c003c 6 0x443c0400 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck: IOMUXC1_GPIO_IO11_LPSPI_SCK_LPSPI3_SCK { + pinmux = <0x443c003c 1 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpuart_rts_b_lpuart7_rts_b: IOMUXC1_GPIO_IO11_LPUART_RTS_B_LPUART7_RTS_B { + pinmux = <0x443c003c 5 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_cam_data_mediamix_cam_data05: IOMUXC1_GPIO_IO11_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA05 { + pinmux = <0x443c003c 2 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_disp_data_mediamix_disp_data07: IOMUXC1_GPIO_IO11_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA07 { + pinmux = <0x443c003c 3 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_tpm_extclk_tpm5_extclk: IOMUXC1_GPIO_IO11_TPM_EXTCLK_TPM5_EXTCLK { + pinmux = <0x443c003c 4 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_gpio_io_gpio2_io12: IOMUXC1_GPIO_IO12_GPIO_IO_GPIO2_IO12 { + pinmux = <0x443c0040 0 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO12_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0040 6 0x443c0404 1 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpspi_pcs_lpspi8_pcs0: IOMUXC1_GPIO_IO12_LPSPI_PCS_LPSPI8_PCS0 { + pinmux = <0x443c0040 4 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpuart_tx_lpuart8_tx: IOMUXC1_GPIO_IO12_LPUART_TX_LPUART8_TX { + pinmux = <0x443c0040 5 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_mediamix_disp_data_mediamix_disp_data08: IOMUXC1_GPIO_IO12_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA08 { + pinmux = <0x443c0040 3 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO12_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0040 2 0x443c0440 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO12_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c0040 7 0x443c0450 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_tpm_ch_tpm3_ch2: IOMUXC1_GPIO_IO12_TPM_CH_TPM3_CH2 { + pinmux = <0x443c0040 1 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_flexio_flexio_flexio1_flexio13: IOMUXC1_GPIO_IO13_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c0044 7 0x443c039c 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_gpio_io_gpio2_io13: IOMUXC1_GPIO_IO13_GPIO_IO_GPIO2_IO13 { + pinmux = <0x443c0044 0 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO13_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c0044 6 0x443c0400 1 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpspi_sin_lpspi8_sin: IOMUXC1_GPIO_IO13_LPSPI_SIN_LPSPI8_SIN { + pinmux = <0x443c0044 4 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpuart_rx_lpuart8_rx: IOMUXC1_GPIO_IO13_LPUART_RX_LPUART8_RX { + pinmux = <0x443c0044 5 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_mediamix_disp_data_mediamix_disp_data09: IOMUXC1_GPIO_IO13_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA09 { + pinmux = <0x443c0044 3 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO13_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c0044 2 0x443c0444 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_tpm_ch_tpm4_ch2: IOMUXC1_GPIO_IO13_TPM_CH_TPM4_CH2 { + pinmux = <0x443c0044 1 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_flexio_flexio_flexio1_flexio14: IOMUXC1_GPIO_IO14_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0048 7 0x443c03a0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_gpio_io_gpio2_io14: IOMUXC1_GPIO_IO14_GPIO_IO_GPIO2_IO14 { + pinmux = <0x443c0048 0 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpspi_sout_lpspi8_sout: IOMUXC1_GPIO_IO14_LPSPI_SOUT_LPSPI8_SOUT { + pinmux = <0x443c0048 4 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_cts_b_lpuart8_cts_b: IOMUXC1_GPIO_IO14_LPUART_CTS_B_LPUART8_CTS_B { + pinmux = <0x443c0048 5 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart3_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART3_TX { + pinmux = <0x443c0048 1 0x443c041c 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart4_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART4_TX { + pinmux = <0x443c0048 6 0x443c0428 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_cam_data_mediamix_cam_data06: IOMUXC1_GPIO_IO14_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA06 { + pinmux = <0x443c0048 2 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_disp_data_mediamix_disp_data10: IOMUXC1_GPIO_IO14_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA10 { + pinmux = <0x443c0048 3 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_flexio_flexio_flexio1_flexio15: IOMUXC1_GPIO_IO15_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c004c 7 0x443c03a4 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_gpio_io_gpio2_io15: IOMUXC1_GPIO_IO15_GPIO_IO_GPIO2_IO15 { + pinmux = <0x443c004c 0 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpspi_sck_lpspi8_sck: IOMUXC1_GPIO_IO15_LPSPI_SCK_LPSPI8_SCK { + pinmux = <0x443c004c 4 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rts_b_lpuart8_rts_b: IOMUXC1_GPIO_IO15_LPUART_RTS_B_LPUART8_RTS_B { + pinmux = <0x443c004c 5 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart3_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART3_RX { + pinmux = <0x443c004c 1 0x443c0418 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart4_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART4_RX { + pinmux = <0x443c004c 6 0x443c0424 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_cam_data_mediamix_cam_data07: IOMUXC1_GPIO_IO15_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA07 { + pinmux = <0x443c004c 2 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_disp_data_mediamix_disp_data11: IOMUXC1_GPIO_IO15_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA11 { + pinmux = <0x443c004c 3 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_flexio_flexio_flexio1_flexio16: IOMUXC1_GPIO_IO16_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0050 7 0x443c03a8 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_gpio_io_gpio2_io16: IOMUXC1_GPIO_IO16_GPIO_IO_GPIO2_IO16 { + pinmux = <0x443c0050 0 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpspi_pcs_lpspi4_pcs2: IOMUXC1_GPIO_IO16_LPSPI_PCS_LPSPI4_PCS2 { + pinmux = <0x443c0050 5 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c0050 4 0x443c0414 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0050 6 0x443c0420 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_mediamix_disp_data_mediamix_disp_data12: IOMUXC1_GPIO_IO16_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA12 { + pinmux = <0x443c0050 3 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO16_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0050 2 0x443c0440 1 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk: IOMUXC1_GPIO_IO16_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x443c0050 1 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_flexio_flexio_flexio1_flexio17: IOMUXC1_GPIO_IO17_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c0054 7 0x443c03ac 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_gpio_io_gpio2_io17: IOMUXC1_GPIO_IO17_GPIO_IO_GPIO2_IO17 { + pinmux = <0x443c0054 0 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpspi_pcs_lpspi4_pcs1: IOMUXC1_GPIO_IO17_LPSPI_PCS_LPSPI4_PCS1 { + pinmux = <0x443c0054 5 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c0054 4 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c0054 6 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_cam_data_mediamix_cam_data08: IOMUXC1_GPIO_IO17_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA08 { + pinmux = <0x443c0054 2 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_disp_data_mediamix_disp_data13: IOMUXC1_GPIO_IO17_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA13 { + pinmux = <0x443c0054 3 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_sai_mclk_sai3_mclk: IOMUXC1_GPIO_IO17_SAI_MCLK_SAI3_MCLK { + pinmux = <0x443c0054 1 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_flexio_flexio_flexio1_flexio18: IOMUXC1_GPIO_IO18_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0058 7 0x443c03b0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_gpio_io_gpio2_io18: IOMUXC1_GPIO_IO18_GPIO_IO_GPIO2_IO18 { + pinmux = <0x443c0058 0 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi4_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI4_PCS0 { + pinmux = <0x443c0058 5 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi5_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI5_PCS0 { + pinmux = <0x443c0058 4 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_cam_data_mediamix_cam_data09: IOMUXC1_GPIO_IO18_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA09 { + pinmux = <0x443c0058 2 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_disp_data_mediamix_disp_data14: IOMUXC1_GPIO_IO18_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA14 { + pinmux = <0x443c0058 3 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO18_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0058 1 0x443c044c 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_tpm_ch_tpm5_ch2: IOMUXC1_GPIO_IO18_TPM_CH_TPM5_CH2 { + pinmux = <0x443c0058 6 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_gpio_io_gpio2_io19: IOMUXC1_GPIO_IO19_GPIO_IO_GPIO2_IO19 { + pinmux = <0x443c005c 0 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi4_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI4_SIN { + pinmux = <0x443c005c 5 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi5_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI5_SIN { + pinmux = <0x443c005c 4 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_mediamix_disp_data_mediamix_disp_data15: IOMUXC1_GPIO_IO19_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA15 { + pinmux = <0x443c005c 3 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO19_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c005c 2 0x443c0444 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO19_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c005c 1 0x443c0450 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO19_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c005c 7 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_tpm_ch_tpm6_ch2: IOMUXC1_GPIO_IO19_TPM_CH_TPM6_CH2 { + pinmux = <0x443c005c 6 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_flexio_flexio_flexio1_flexio20: IOMUXC1_GPIO_IO20_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0060 7 0x443c03b4 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_gpio_io_gpio2_io20: IOMUXC1_GPIO_IO20_GPIO_IO_GPIO2_IO20 { + pinmux = <0x443c0060 0 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi4_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI4_SOUT { + pinmux = <0x443c0060 5 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi5_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI5_SOUT { + pinmux = <0x443c0060 4 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_mediamix_disp_data_mediamix_disp_data16: IOMUXC1_GPIO_IO20_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA16 { + pinmux = <0x443c0060 3 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO20_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0060 2 0x443c0438 1 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data00: IOMUXC1_GPIO_IO20_SAI_RX_DATA_SAI3_RX_DATA00 { + pinmux = <0x443c0060 1 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_tpm_ch_tpm3_ch1: IOMUXC1_GPIO_IO20_TPM_CH_TPM3_CH1 { + pinmux = <0x443c0060 6 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_gpio_io_gpio2_io21: IOMUXC1_GPIO_IO21_GPIO_IO_GPIO2_IO21 { + pinmux = <0x443c0064 0 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi4_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI4_SCK { + pinmux = <0x443c0064 5 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi5_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI5_SCK { + pinmux = <0x443c0064 4 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_mediamix_disp_data_mediamix_disp_data17: IOMUXC1_GPIO_IO21_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA17 { + pinmux = <0x443c0064 3 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO21_PDM_CLK_PDM_CLK { + pinmux = <0x443c0064 2 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO21_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0064 7 0x443c044c 1 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO21_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c0064 1 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_tpm_ch_tpm4_ch1: IOMUXC1_GPIO_IO21_TPM_CH_TPM4_CH1 { + pinmux = <0x443c0064 6 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_flexio_flexio_flexio1_flexio22: IOMUXC1_GPIO_IO22_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0068 7 0x443c03b8 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_gpio_io_gpio2_io22: IOMUXC1_GPIO_IO22_GPIO_IO_GPIO2_IO22 { + pinmux = <0x443c0068 0 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO22_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0068 6 0x443c03ec 1 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_mediamix_disp_data_mediamix_disp_data18: IOMUXC1_GPIO_IO22_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA18 { + pinmux = <0x443c0068 3 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_spdif_in_spdif_in: IOMUXC1_GPIO_IO22_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0068 2 0x443c0454 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_ch_tpm5_ch1: IOMUXC1_GPIO_IO22_TPM_CH_TPM5_CH1 { + pinmux = <0x443c0068 4 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_extclk_tpm6_extclk: IOMUXC1_GPIO_IO22_TPM_EXTCLK_TPM6_EXTCLK { + pinmux = <0x443c0068 5 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_usdhc_clk_usdhc3_clk: IOMUXC1_GPIO_IO22_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0068 1 0x443c0458 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_flexio_flexio_flexio1_flexio23: IOMUXC1_GPIO_IO23_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c006c 7 0x443c03bc 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_gpio_io_gpio2_io23: IOMUXC1_GPIO_IO23_GPIO_IO_GPIO2_IO23 { + pinmux = <0x443c006c 0 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO23_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c006c 6 0x443c03e8 1 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_mediamix_disp_data_mediamix_disp_data19: IOMUXC1_GPIO_IO23_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA19 { + pinmux = <0x443c006c 3 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_spdif_out_spdif_out: IOMUXC1_GPIO_IO23_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c006c 2 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_tpm_ch_tpm6_ch1: IOMUXC1_GPIO_IO23_TPM_CH_TPM6_CH1 { + pinmux = <0x443c006c 4 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_usdhc_cmd_usdhc3_cmd: IOMUXC1_GPIO_IO23_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c006c 1 0x443c045c 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_flexio_flexio_flexio1_flexio24: IOMUXC1_GPIO_IO24_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0070 7 0x443c03c0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_gpio_io_gpio2_io24: IOMUXC1_GPIO_IO24_GPIO_IO_GPIO2_IO24 { + pinmux = <0x443c0070 0 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_GPIO_IO24_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c0070 5 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_lpspi_pcs_lpspi6_pcs1: IOMUXC1_GPIO_IO24_LPSPI_PCS_LPSPI6_PCS1 { + pinmux = <0x443c0070 6 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_mediamix_disp_data_mediamix_disp_data20: IOMUXC1_GPIO_IO24_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA20 { + pinmux = <0x443c0070 3 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_tpm_ch_tpm3_ch3: IOMUXC1_GPIO_IO24_TPM_CH_TPM3_CH3 { + pinmux = <0x443c0070 4 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_usdhc_data_usdhc3_data0: IOMUXC1_GPIO_IO24_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0070 1 0x443c0460 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_can_tx_can2_tx: IOMUXC1_GPIO_IO25_CAN_TX_CAN2_TX { + pinmux = <0x443c0074 2 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_flexio_flexio_flexio1_flexio25: IOMUXC1_GPIO_IO25_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c0074 7 0x443c03c4 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_gpio_io_gpio2_io25: IOMUXC1_GPIO_IO25_GPIO_IO_GPIO2_IO25 { + pinmux = <0x443c0074 0 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_jtag_mux_tck_jtag_mux_tck: IOMUXC1_GPIO_IO25_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0074 5 0x443c03d4 1 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_lpspi_pcs_lpspi7_pcs1: IOMUXC1_GPIO_IO25_LPSPI_PCS_LPSPI7_PCS1 { + pinmux = <0x443c0074 6 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_mediamix_disp_data_mediamix_disp_data21: IOMUXC1_GPIO_IO25_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA21 { + pinmux = <0x443c0074 3 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_tpm_ch_tpm4_ch3: IOMUXC1_GPIO_IO25_TPM_CH_TPM4_CH3 { + pinmux = <0x443c0074 4 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_usdhc_data_usdhc3_data1: IOMUXC1_GPIO_IO25_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0074 1 0x443c0464 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_gpio_io_gpio2_io26: IOMUXC1_GPIO_IO26_GPIO_IO_GPIO2_IO26 { + pinmux = <0x443c0078 0 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_GPIO_IO26_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0078 5 0x443c03d8 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_lpspi_pcs_lpspi8_pcs1: IOMUXC1_GPIO_IO26_LPSPI_PCS_LPSPI8_PCS1 { + pinmux = <0x443c0078 6 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_mediamix_disp_data_mediamix_disp_data22: IOMUXC1_GPIO_IO26_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA22 { + pinmux = <0x443c0078 3 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO26_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0078 2 0x443c043c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync: IOMUXC1_GPIO_IO26_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x443c0078 7 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_tpm_ch_tpm5_ch3: IOMUXC1_GPIO_IO26_TPM_CH_TPM5_CH3 { + pinmux = <0x443c0078 4 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_usdhc_data_usdhc3_data2: IOMUXC1_GPIO_IO26_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0078 1 0x443c0468 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_can_rx_can2_rx: IOMUXC1_GPIO_IO27_CAN_RX_CAN2_RX { + pinmux = <0x443c007c 2 0x443c0364 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_flexio_flexio_flexio1_flexio27: IOMUXC1_GPIO_IO27_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c007c 7 0x443c03c8 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_gpio_io_gpio2_io27: IOMUXC1_GPIO_IO27_GPIO_IO_GPIO2_IO27 { + pinmux = <0x443c007c 0 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_jtag_mux_tms_jtag_mux_tms: IOMUXC1_GPIO_IO27_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c007c 5 0x443c03dc 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_lpspi_pcs_lpspi5_pcs1: IOMUXC1_GPIO_IO27_LPSPI_PCS_LPSPI5_PCS1 { + pinmux = <0x443c007c 6 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_mediamix_disp_data_mediamix_disp_data23: IOMUXC1_GPIO_IO27_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA23 { + pinmux = <0x443c007c 3 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_tpm_ch_tpm6_ch3: IOMUXC1_GPIO_IO27_TPM_CH_TPM6_CH3 { + pinmux = <0x443c007c 4 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_usdhc_data_usdhc3_data3: IOMUXC1_GPIO_IO27_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c007c 1 0x443c046c 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_flexio_flexio_flexio1_flexio28: IOMUXC1_GPIO_IO28_FLEXIO_FLEXIO_FLEXIO1_FLEXIO28 { + pinmux = <0x443c0080 7 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_gpio_io_gpio2_io28: IOMUXC1_GPIO_IO28_GPIO_IO_GPIO2_IO28 { + pinmux = <0x443c0080 0 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO28_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0080 1 0x443c03e4 1 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_flexio_flexio_flexio1_flexio29: IOMUXC1_GPIO_IO29_FLEXIO_FLEXIO_FLEXIO1_FLEXIO29 { + pinmux = <0x443c0084 7 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_gpio_io_gpio2_io29: IOMUXC1_GPIO_IO29_GPIO_IO_GPIO2_IO29 { + pinmux = <0x443c0084 0 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO29_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0084 1 0x443c03e0 1 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_gpio_io_gpio1_io00: IOMUXC1_I2C1_SCL_GPIO_IO_GPIO1_IO00 { + pinmux = <0x443c0170 5 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_i3c_scl_i3c1_scl: IOMUXC1_I2C1_SCL_I3C_SCL_I3C1_SCL { + pinmux = <0x443c0170 1 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl: IOMUXC1_I2C1_SCL_LPI2C_SCL_LPI2C1_SCL { + pinmux = <0x443c0170 0 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpuart_dcb_b_lpuart1_dcb_b: IOMUXC1_I2C1_SCL_LPUART_DCB_B_LPUART1_DCB_B { + pinmux = <0x443c0170 2 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_tpm_ch_tpm2_ch0: IOMUXC1_I2C1_SCL_TPM_CH_TPM2_CH0 { + pinmux = <0x443c0170 3 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_gpio_io_gpio1_io01: IOMUXC1_I2C1_SDA_GPIO_IO_GPIO1_IO01 { + pinmux = <0x443c0174 5 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_i3c_sda_i3c1_sda: IOMUXC1_I2C1_SDA_I3C_SDA_I3C1_SDA { + pinmux = <0x443c0174 1 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda: IOMUXC1_I2C1_SDA_LPI2C_SDA_LPI2C1_SDA { + pinmux = <0x443c0174 0 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpuart_rin_b_lpuart1_rin_b: IOMUXC1_I2C1_SDA_LPUART_RIN_B_LPUART1_RIN_B { + pinmux = <0x443c0174 2 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_tpm_ch_tpm2_ch1: IOMUXC1_I2C1_SDA_TPM_CH_TPM2_CH1 { + pinmux = <0x443c0174 3 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_gpio_io_gpio1_io02: IOMUXC1_I2C2_SCL_GPIO_IO_GPIO1_IO02 { + pinmux = <0x443c0178 5 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_b_i3c1_pur_b: IOMUXC1_I2C2_SCL_I3C_PUR_B_I3C1_PUR_B { + pinmux = <0x443c0178 6 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_i3c1_pur: IOMUXC1_I2C2_SCL_I3C_PUR_I3C1_PUR { + pinmux = <0x443c0178 1 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl: IOMUXC1_I2C2_SCL_LPI2C_SCL_LPI2C2_SCL { + pinmux = <0x443c0178 0 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpuart_dcb_b_lpuart2_dcb_b: IOMUXC1_I2C2_SCL_LPUART_DCB_B_LPUART2_DCB_B { + pinmux = <0x443c0178 2 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_sai_rx_sync_sai1_rx_sync: IOMUXC1_I2C2_SCL_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x443c0178 4 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_tpm_ch_tpm2_ch2: IOMUXC1_I2C2_SCL_TPM_CH_TPM2_CH2 { + pinmux = <0x443c0178 3 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_gpio_io_gpio1_io03: IOMUXC1_I2C2_SDA_GPIO_IO_GPIO1_IO03 { + pinmux = <0x443c017c 5 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda: IOMUXC1_I2C2_SDA_LPI2C_SDA_LPI2C2_SDA { + pinmux = <0x443c017c 0 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpuart_rin_b_lpuart2_rin_b: IOMUXC1_I2C2_SDA_LPUART_RIN_B_LPUART2_RIN_B { + pinmux = <0x443c017c 2 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_sai_rx_bclk_sai1_rx_bclk: IOMUXC1_I2C2_SDA_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x443c017c 4 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_tpm_ch_tpm2_ch3: IOMUXC1_I2C2_SDA_TPM_CH_TPM2_CH3 { + pinmux = <0x443c017c 3 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_can_rx_can1_rx: IOMUXC1_PDM_BIT_STREAM0_CAN_RX_CAN1_RX { + pinmux = <0x443c0194 6 0x443c0360 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09: IOMUXC1_PDM_BIT_STREAM0_GPIO_IO_GPIO1_IO09 { + pinmux = <0x443c0194 5 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lpspi_pcs_lpspi1_pcs1: IOMUXC1_PDM_BIT_STREAM0_LPSPI_PCS_LPSPI1_PCS1 { + pinmux = <0x443c0194 2 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lptmr_alt_lptmr1_alt2: IOMUXC1_PDM_BIT_STREAM0_LPTMR_ALT_LPTMR1_ALT2 { + pinmux = <0x443c0194 4 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_mqs_right_mqs1_right: IOMUXC1_PDM_BIT_STREAM0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c0194 1 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_PDM_BIT_STREAM0_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0194 0 0x443c0438 2 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_tpm_extclk_tpm1_extclk: IOMUXC1_PDM_BIT_STREAM0_TPM_EXTCLK_TPM1_EXTCLK { + pinmux = <0x443c0194 3 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0198 6 0x443c0368 1 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10: IOMUXC1_PDM_BIT_STREAM1_GPIO_IO_GPIO1_IO10 { + pinmux = <0x443c0198 5 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lpspi_pcs_lpspi2_pcs1: IOMUXC1_PDM_BIT_STREAM1_LPSPI_PCS_LPSPI2_PCS1 { + pinmux = <0x443c0198 2 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lptmr_alt_lptmr1_alt3: IOMUXC1_PDM_BIT_STREAM1_LPTMR_ALT_LPTMR1_ALT3 { + pinmux = <0x443c0198 4 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_nmi_glue_nmi_nmi_glue_nmi: IOMUXC1_PDM_BIT_STREAM1_NMI_GLUE_NMI_NMI_GLUE_NMI { + pinmux = <0x443c0198 1 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_PDM_BIT_STREAM1_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0198 0 0x443c043c 2 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_tpm_extclk_tpm2_extclk: IOMUXC1_PDM_BIT_STREAM1_TPM_EXTCLK_TPM2_EXTCLK { + pinmux = <0x443c0198 3 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_can_tx_can1_tx: IOMUXC1_PDM_CLK_CAN_TX_CAN1_TX { + pinmux = <0x443c0190 6 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_gpio_io_gpio1_io08: IOMUXC1_PDM_CLK_GPIO_IO_GPIO1_IO08 { + pinmux = <0x443c0190 5 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_lptmr_alt_lptmr1_alt1: IOMUXC1_PDM_CLK_LPTMR_ALT_LPTMR1_ALT1 { + pinmux = <0x443c0190 4 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_mqs_left_mqs1_left: IOMUXC1_PDM_CLK_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c0190 1 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_pdm_clk_pdm_clk: IOMUXC1_PDM_CLK_PDM_CLK_PDM_CLK { + pinmux = <0x443c0190 0 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_gpio_io_gpio1_io14: IOMUXC1_SAI1_RXD0_GPIO_IO_GPIO1_IO14 { + pinmux = <0x443c01a8 5 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpspi_sout_lpspi1_sout: IOMUXC1_SAI1_RXD0_LPSPI_SOUT_LPSPI1_SOUT { + pinmux = <0x443c01a8 2 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpuart_dsr_b_lpuart2_dsr_b: IOMUXC1_SAI1_RXD0_LPUART_DSR_B_LPUART2_DSR_B { + pinmux = <0x443c01a8 3 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_mqs_right_mqs1_right: IOMUXC1_SAI1_RXD0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c01a8 4 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_mclk_sai1_mclk: IOMUXC1_SAI1_RXD0_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c01a8 1 0x443c0448 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_rx_data_sai1_rx_data00: IOMUXC1_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA00 { + pinmux = <0x443c01a8 0 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_can_rx_can1_rx: IOMUXC1_SAI1_TXC_CAN_RX_CAN1_RX { + pinmux = <0x443c01a0 4 0x443c0360 1 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_gpio_io_gpio1_io12: IOMUXC1_SAI1_TXC_GPIO_IO_GPIO1_IO12 { + pinmux = <0x443c01a0 5 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpspi_sin_lpspi1_sin: IOMUXC1_SAI1_TXC_LPSPI_SIN_LPSPI1_SIN { + pinmux = <0x443c01a0 2 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_cts_b_lpuart2_cts_b: IOMUXC1_SAI1_TXC_LPUART_CTS_B_LPUART2_CTS_B { + pinmux = <0x443c01a0 1 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_dsr_b_lpuart1_dsr_b: IOMUXC1_SAI1_TXC_LPUART_DSR_B_LPUART1_DSR_B { + pinmux = <0x443c01a0 3 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC1_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x443c01a0 0 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_can_tx_can1_tx: IOMUXC1_SAI1_TXD0_CAN_TX_CAN1_TX { + pinmux = <0x443c01a4 4 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_gpio_io_gpio1_io13: IOMUXC1_SAI1_TXD0_GPIO_IO_GPIO1_IO13 { + pinmux = <0x443c01a4 5 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpspi_sck_lpspi1_sck: IOMUXC1_SAI1_TXD0_LPSPI_SCK_LPSPI1_SCK { + pinmux = <0x443c01a4 2 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_dtr_b_lpuart1_dtr_b: IOMUXC1_SAI1_TXD0_LPUART_DTR_B_LPUART1_DTR_B { + pinmux = <0x443c01a4 3 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_rts_b_lpuart2_rts_b: IOMUXC1_SAI1_TXD0_LPUART_RTS_B_LPUART2_RTS_B { + pinmux = <0x443c01a4 1 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_sai_tx_data_sai1_tx_data00: IOMUXC1_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA00 { + pinmux = <0x443c01a4 0 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_gpio_io_gpio1_io11: IOMUXC1_SAI1_TXFS_GPIO_IO_GPIO1_IO11 { + pinmux = <0x443c019c 5 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpspi_pcs_lpspi1_pcs0: IOMUXC1_SAI1_TXFS_LPSPI_PCS_LPSPI1_PCS0 { + pinmux = <0x443c019c 2 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpuart_dtr_b_lpuart2_dtr_b: IOMUXC1_SAI1_TXFS_LPUART_DTR_B_LPUART2_DTR_B { + pinmux = <0x443c019c 3 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_mqs_left_mqs1_left: IOMUXC1_SAI1_TXFS_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c019c 4 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_data_sai1_tx_data01: IOMUXC1_SAI1_TXFS_SAI_TX_DATA_SAI1_TX_DATA01 { + pinmux = <0x443c019c 1 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC1_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x443c019c 0 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_flexio_flexio_flexio1_flexio08: IOMUXC1_SD1_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0108 4 0x443c038c 1 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_gpio_io_gpio3_io08: IOMUXC1_SD1_CLK_GPIO_IO_GPIO3_IO08 { + pinmux = <0x443c0108 5 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC1_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x443c0108 0 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_flexio_flexio_flexio1_flexio09: IOMUXC1_SD1_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c010c 4 0x443c0390 1 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_gpio_io_gpio3_io09: IOMUXC1_SD1_CMD_GPIO_IO_GPIO3_IO09 { + pinmux = <0x443c010c 5 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC1_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x443c010c 0 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_flexio_flexio_flexio1_flexio10: IOMUXC1_SD1_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0110 4 0x443c0394 1 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_gpio_io_gpio3_io10: IOMUXC1_SD1_DATA0_GPIO_IO_GPIO3_IO10 { + pinmux = <0x443c0110 5 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC1_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x443c0110 0 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_flexio_flexio_flexio1_flexio11: IOMUXC1_SD1_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c0114 4 0x443c0398 1 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_gpio_io_gpio3_io11: IOMUXC1_SD1_DATA1_GPIO_IO_GPIO3_IO11 { + pinmux = <0x443c0114 5 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC1_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x443c0114 0 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_flexio_flexio_flexio1_flexio12: IOMUXC1_SD1_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO12 { + pinmux = <0x443c0118 4 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_gpio_io_gpio3_io12: IOMUXC1_SD1_DATA2_GPIO_IO_GPIO3_IO12 { + pinmux = <0x443c0118 5 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC1_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x443c0118 0 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexio_flexio_flexio1_flexio13: IOMUXC1_SD1_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c011c 4 0x443c039c 1 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexspi_a_ss_b_flexspi1_a_ss1_b: IOMUXC1_SD1_DATA3_FLEXSPI_A_SS_B_FLEXSPI1_A_SS1_B { + pinmux = <0x443c011c 1 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_gpio_io_gpio3_io13: IOMUXC1_SD1_DATA3_GPIO_IO_GPIO3_IO13 { + pinmux = <0x443c011c 5 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC1_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x443c011c 0 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexio_flexio_flexio1_flexio14: IOMUXC1_SD1_DATA4_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0120 4 0x443c03a0 1 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexspi_a_data_flexspi1_a_data04: IOMUXC1_SD1_DATA4_FLEXSPI_A_DATA_FLEXSPI1_A_DATA04 { + pinmux = <0x443c0120 1 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_gpio_io_gpio3_io14: IOMUXC1_SD1_DATA4_GPIO_IO_GPIO3_IO14 { + pinmux = <0x443c0120 5 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC1_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x443c0120 0 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexio_flexio_flexio1_flexio15: IOMUXC1_SD1_DATA5_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c0124 4 0x443c03a4 1 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexspi_a_data_flexspi1_a_data05: IOMUXC1_SD1_DATA5_FLEXSPI_A_DATA_FLEXSPI1_A_DATA05 { + pinmux = <0x443c0124 1 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_gpio_io_gpio3_io15: IOMUXC1_SD1_DATA5_GPIO_IO_GPIO3_IO15 { + pinmux = <0x443c0124 5 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC1_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x443c0124 0 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_reset_b_usdhc1_reset_b: IOMUXC1_SD1_DATA5_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x443c0124 2 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexio_flexio_flexio1_flexio16: IOMUXC1_SD1_DATA6_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0128 4 0x443c03a8 1 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexspi_a_data_flexspi1_a_data06: IOMUXC1_SD1_DATA6_FLEXSPI_A_DATA_FLEXSPI1_A_DATA06 { + pinmux = <0x443c0128 1 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_gpio_io_gpio3_io16: IOMUXC1_SD1_DATA6_GPIO_IO_GPIO3_IO16 { + pinmux = <0x443c0128 5 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_cd_b_usdhc1_cd_b: IOMUXC1_SD1_DATA6_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x443c0128 2 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC1_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x443c0128 0 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexio_flexio_flexio1_flexio17: IOMUXC1_SD1_DATA7_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c012c 4 0x443c03ac 1 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexspi_a_data_flexspi1_a_data07: IOMUXC1_SD1_DATA7_FLEXSPI_A_DATA_FLEXSPI1_A_DATA07 { + pinmux = <0x443c012c 1 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_gpio_io_gpio3_io17: IOMUXC1_SD1_DATA7_GPIO_IO_GPIO3_IO17 { + pinmux = <0x443c012c 5 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC1_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x443c012c 0 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_wp_usdhc1_wp: IOMUXC1_SD1_DATA7_USDHC_WP_USDHC1_WP { + pinmux = <0x443c012c 2 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexio_flexio_flexio1_flexio18: IOMUXC1_SD1_STROBE_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0130 4 0x443c03b0 1 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexspi_a_dqs_flexspi1_a_dqs: IOMUXC1_SD1_STROBE_FLEXSPI_A_DQS_FLEXSPI1_A_DQS { + pinmux = <0x443c0130 1 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_gpio_io_gpio3_io18: IOMUXC1_SD1_STROBE_GPIO_IO_GPIO3_IO18 { + pinmux = <0x443c0130 5 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC1_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x443c0130 0 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC1_SD2_CD_B_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x443c0150 1 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_flexio_flexio_flexio1_flexio00: IOMUXC1_SD2_CD_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0150 4 0x443c036c 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_gpio_io_gpio3_io00: IOMUXC1_SD2_CD_B_GPIO_IO_GPIO3_IO00 { + pinmux = <0x443c0150 5 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_i3c_scl_i3c2_scl: IOMUXC1_SD2_CD_B_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0150 2 0x443c03cc 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC1_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x443c0150 0 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe0: IOMUXC1_SD2_CLK_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE0 { + pinmux = <0x443c0154 6 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC1_SD2_CLK_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x443c0154 1 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_flexio_flexio_flexio1_flexio01: IOMUXC1_SD2_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0154 4 0x443c0370 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_gpio_io_gpio3_io01: IOMUXC1_SD2_CLK_GPIO_IO_GPIO3_IO01 { + pinmux = <0x443c0154 5 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_i3c_sda_i3c2_sda: IOMUXC1_SD2_CLK_I3C_SDA_I3C2_SDA { + pinmux = <0x443c0154 2 0x443c03d0 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC1_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x443c0154 0 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe1: IOMUXC1_SD2_CMD_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE1 { + pinmux = <0x443c0158 6 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_enet1_1588_event0_in_enet1_1588_event0_in: IOMUXC1_SD2_CMD_ENET1_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x443c0158 1 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_flexio_flexio_flexio1_flexio02: IOMUXC1_SD2_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0158 4 0x443c0374 1 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_gpio_io_gpio3_io02: IOMUXC1_SD2_CMD_GPIO_IO_GPIO3_IO02 { + pinmux = <0x443c0158 5 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_b_i3c2_pur_b: IOMUXC1_SD2_CMD_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c0158 3 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_i3c2_pur: IOMUXC1_SD2_CMD_I3C_PUR_I3C2_PUR { + pinmux = <0x443c0158 2 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC1_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x443c0158 0 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_can_tx_can2_tx: IOMUXC1_SD2_DATA0_CAN_TX_CAN2_TX { + pinmux = <0x443c015c 2 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe2: IOMUXC1_SD2_DATA0_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE2 { + pinmux = <0x443c015c 6 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_enet1_1588_event0_out_enet1_1588_event0_out: IOMUXC1_SD2_DATA0_ENET1_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x443c015c 1 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_flexio_flexio_flexio1_flexio03: IOMUXC1_SD2_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c015c 4 0x443c0378 1 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_gpio_io_gpio3_io03: IOMUXC1_SD2_DATA0_GPIO_IO_GPIO3_IO03 { + pinmux = <0x443c015c 5 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC1_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x443c015c 0 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_can_rx_can2_rx: IOMUXC1_SD2_DATA1_CAN_RX_CAN2_RX { + pinmux = <0x443c0160 2 0x443c0364 3 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_enet1_1588_event1_in_enet1_1588_event1_in: IOMUXC1_SD2_DATA1_ENET1_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x443c0160 1 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_flexio_flexio_flexio1_flexio04: IOMUXC1_SD2_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0160 4 0x443c037c 1 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_gpio_io_gpio3_io04: IOMUXC1_SD2_DATA1_GPIO_IO_GPIO3_IO04 { + pinmux = <0x443c0160 5 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC1_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x443c0160 0 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_enet1_1588_event1_out_enet1_1588_event1_out: IOMUXC1_SD2_DATA2_ENET1_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x443c0164 1 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_flexio_flexio_flexio1_flexio05: IOMUXC1_SD2_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0164 4 0x443c0380 1 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_gpio_io_gpio3_io05: IOMUXC1_SD2_DATA2_GPIO_IO_GPIO3_IO05 { + pinmux = <0x443c0164 5 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_mqs_right_mqs2_right: IOMUXC1_SD2_DATA2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0164 2 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC1_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x443c0164 0 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_flexio_flexio_flexio1_flexio06: IOMUXC1_SD2_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0168 4 0x443c0384 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_gpio_io_gpio3_io06: IOMUXC1_SD2_DATA3_GPIO_IO_GPIO3_IO06 { + pinmux = <0x443c0168 5 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_lptmr_alt_lptmr2_alt1: IOMUXC1_SD2_DATA3_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c0168 1 0x443c0408 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_mqs_left_mqs2_left: IOMUXC1_SD2_DATA3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0168 2 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC1_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x443c0168 0 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_ccmsrcgpcmix_system_reset_ccmsrcgpcmix_system_reset: IOMUXC1_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET_CCMSRCGPCMIX_SYSTEM_RESET { + pinmux = <0x443c016c 6 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_flexio_flexio_flexio1_flexio07: IOMUXC1_SD2_RESET_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c016c 4 0x443c0388 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_gpio_io_gpio3_io07: IOMUXC1_SD2_RESET_B_GPIO_IO_GPIO3_IO07 { + pinmux = <0x443c016c 5 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_lptmr_alt_lptmr2_alt2: IOMUXC1_SD2_RESET_B_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c016c 1 0x443c040c 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC1_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x443c016c 0 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0134 6 0x443c0368 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_flexio_flexio_flexio1_flexio19: IOMUXC1_SD2_VSELECT_FLEXIO_FLEXIO_FLEXIO1_FLEXIO19 { + pinmux = <0x443c0134 4 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_gpio_io_gpio3_io19: IOMUXC1_SD2_VSELECT_GPIO_IO_GPIO3_IO19 { + pinmux = <0x443c0134 5 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_lptmr_alt_lptmr2_alt3: IOMUXC1_SD2_VSELECT_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c0134 2 0x443c0410 1 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect: IOMUXC1_SD2_VSELECT_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x443c0134 0 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_wp_usdhc2_wp: IOMUXC1_SD2_VSELECT_USDHC_WP_USDHC2_WP { + pinmux = <0x443c0134 1 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexio_flexio_flexio1_flexio20: IOMUXC1_SD3_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0138 4 0x443c03b4 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexspi_a_sclk_flexspi1_a_sclk: IOMUXC1_SD3_CLK_FLEXSPI_A_SCLK_FLEXSPI1_A_SCLK { + pinmux = <0x443c0138 1 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_gpio_io_gpio3_io20: IOMUXC1_SD3_CLK_GPIO_IO_GPIO3_IO20 { + pinmux = <0x443c0138 5 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_usdhc_clk_usdhc3_clk: IOMUXC1_SD3_CLK_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0138 0 0x443c0458 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexio_flexio_flexio1_flexio21: IOMUXC1_SD3_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO21 { + pinmux = <0x443c013c 4 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexspi_a_ss_b_flexspi1_a_ss0_b: IOMUXC1_SD3_CMD_FLEXSPI_A_SS_B_FLEXSPI1_A_SS0_B { + pinmux = <0x443c013c 1 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_gpio_io_gpio3_io21: IOMUXC1_SD3_CMD_GPIO_IO_GPIO3_IO21 { + pinmux = <0x443c013c 5 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_usdhc_cmd_usdhc3_cmd: IOMUXC1_SD3_CMD_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c013c 0 0x443c045c 1 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexio_flexio_flexio1_flexio22: IOMUXC1_SD3_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0140 4 0x443c03b8 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexspi_a_data_flexspi1_a_data00: IOMUXC1_SD3_DATA0_FLEXSPI_A_DATA_FLEXSPI1_A_DATA00 { + pinmux = <0x443c0140 1 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_gpio_io_gpio3_io22: IOMUXC1_SD3_DATA0_GPIO_IO_GPIO3_IO22 { + pinmux = <0x443c0140 5 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_usdhc_data_usdhc3_data0: IOMUXC1_SD3_DATA0_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0140 0 0x443c0460 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexio_flexio_flexio1_flexio23: IOMUXC1_SD3_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c0144 4 0x443c03bc 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexspi_a_data_flexspi1_a_data01: IOMUXC1_SD3_DATA1_FLEXSPI_A_DATA_FLEXSPI1_A_DATA01 { + pinmux = <0x443c0144 1 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_gpio_io_gpio3_io23: IOMUXC1_SD3_DATA1_GPIO_IO_GPIO3_IO23 { + pinmux = <0x443c0144 5 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_usdhc_data_usdhc3_data1: IOMUXC1_SD3_DATA1_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0144 0 0x443c0464 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexio_flexio_flexio1_flexio24: IOMUXC1_SD3_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0148 4 0x443c03c0 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexspi_a_data_flexspi1_a_data02: IOMUXC1_SD3_DATA2_FLEXSPI_A_DATA_FLEXSPI1_A_DATA02 { + pinmux = <0x443c0148 1 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_gpio_io_gpio3_io24: IOMUXC1_SD3_DATA2_GPIO_IO_GPIO3_IO24 { + pinmux = <0x443c0148 5 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_usdhc_data_usdhc3_data2: IOMUXC1_SD3_DATA2_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0148 0 0x443c0468 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexio_flexio_flexio1_flexio25: IOMUXC1_SD3_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c014c 4 0x443c03c4 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexspi_a_data_flexspi1_a_data03: IOMUXC1_SD3_DATA3_FLEXSPI_A_DATA_FLEXSPI1_A_DATA03 { + pinmux = <0x443c014c 1 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_gpio_io_gpio3_io25: IOMUXC1_SD3_DATA3_GPIO_IO_GPIO3_IO25 { + pinmux = <0x443c014c 5 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_usdhc_data_usdhc3_data3: IOMUXC1_SD3_DATA3_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c014c 0 0x443c046c 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_gpio_io_gpio1_io04: IOMUXC1_UART1_RXD_GPIO_IO_GPIO1_IO04 { + pinmux = <0x443c0180 5 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpspi_sin_lpspi2_sin: IOMUXC1_UART1_RXD_LPSPI_SIN_LPSPI2_SIN { + pinmux = <0x443c0180 2 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx: IOMUXC1_UART1_RXD_LPUART_RX_LPUART1_RX { + pinmux = <0x443c0180 0 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_s400_uart_rx_s400_uart_rx: IOMUXC1_UART1_RXD_S400_UART_RX_S400_UART_RX { + pinmux = <0x443c0180 1 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_tpm_ch_tpm1_ch0: IOMUXC1_UART1_RXD_TPM_CH_TPM1_CH0 { + pinmux = <0x443c0180 3 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_gpio_io_gpio1_io05: IOMUXC1_UART1_TXD_GPIO_IO_GPIO1_IO05 { + pinmux = <0x443c0184 5 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpspi_pcs_lpspi2_pcs0: IOMUXC1_UART1_TXD_LPSPI_PCS_LPSPI2_PCS0 { + pinmux = <0x443c0184 2 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx: IOMUXC1_UART1_TXD_LPUART_TX_LPUART1_TX { + pinmux = <0x443c0184 0 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_s400_uart_tx_s400_uart_tx: IOMUXC1_UART1_TXD_S400_UART_TX_S400_UART_TX { + pinmux = <0x443c0184 1 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_tpm_ch_tpm1_ch1: IOMUXC1_UART1_TXD_TPM_CH_TPM1_CH1 { + pinmux = <0x443c0184 3 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_gpio_io_gpio1_io06: IOMUXC1_UART2_RXD_GPIO_IO_GPIO1_IO06 { + pinmux = <0x443c0188 5 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpspi_sout_lpspi2_sout: IOMUXC1_UART2_RXD_LPSPI_SOUT_LPSPI2_SOUT { + pinmux = <0x443c0188 2 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_cts_b_lpuart1_cts_b: IOMUXC1_UART2_RXD_LPUART_CTS_B_LPUART1_CTS_B { + pinmux = <0x443c0188 1 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx: IOMUXC1_UART2_RXD_LPUART_RX_LPUART2_RX { + pinmux = <0x443c0188 0 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_sai_mclk_sai1_mclk: IOMUXC1_UART2_RXD_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c0188 4 0x443c0448 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_tpm_ch_tpm1_ch2: IOMUXC1_UART2_RXD_TPM_CH_TPM1_CH2 { + pinmux = <0x443c0188 3 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_gpio_io_gpio1_io07: IOMUXC1_UART2_TXD_GPIO_IO_GPIO1_IO07 { + pinmux = <0x443c018c 5 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpspi_sck_lpspi2_sck: IOMUXC1_UART2_TXD_LPSPI_SCK_LPSPI2_SCK { + pinmux = <0x443c018c 2 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_rts_b_lpuart1_rts_b: IOMUXC1_UART2_TXD_LPUART_RTS_B_LPUART1_RTS_B { + pinmux = <0x443c018c 1 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx: IOMUXC1_UART2_TXD_LPUART_TX_LPUART2_TX { + pinmux = <0x443c018c 0 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_tpm_ch_tpm1_ch3: IOMUXC1_UART2_TXD_TPM_CH_TPM1_CH3 { + pinmux = <0x443c018c 3 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_gpio_io_gpio1_io15: IOMUXC1_WDOG_ANY_GPIO_IO_GPIO1_IO15 { + pinmux = <0x443c01ac 5 0x0 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_wdog_wdog_any_wdog1_wdog_any: IOMUXC1_WDOG_ANY_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x443c01ac 0 0x0 0 0x443c035c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx9352cvvxm-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx9352cvvxm-pinctrl.dtsi new file mode 100644 index 000000000..ae525cae0 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx9352cvvxm-pinctrl.dtsi @@ -0,0 +1,1831 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX9352CVVXM + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc1_ccm_clko1_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko1: IOMUXC1_CCM_CLKO1_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO1 { + pinmux = <0x443c0088 0 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_flexio_flexio_flexio1_flexio26: IOMUXC1_CCM_CLKO1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO26 { + pinmux = <0x443c0088 4 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_gpio_io_gpio3_io26: IOMUXC1_CCM_CLKO1_GPIO_IO_GPIO3_IO26 { + pinmux = <0x443c0088 5 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko2: IOMUXC1_CCM_CLKO2_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO2 { + pinmux = <0x443c008c 0 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_flexio_flexio_flexio1_flexio27: IOMUXC1_CCM_CLKO2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c008c 4 0x443c03c8 1 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_gpio_io_gpio3_io27: IOMUXC1_CCM_CLKO2_GPIO_IO_GPIO3_IO27 { + pinmux = <0x443c008c 5 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko3: IOMUXC1_CCM_CLKO3_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO3 { + pinmux = <0x443c0090 0 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_flexio_flexio_flexio2_flexio28: IOMUXC1_CCM_CLKO3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO28 { + pinmux = <0x443c0090 4 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_gpio_io_gpio4_io28: IOMUXC1_CCM_CLKO3_GPIO_IO_GPIO4_IO28 { + pinmux = <0x443c0090 5 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko4: IOMUXC1_CCM_CLKO4_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO4 { + pinmux = <0x443c0094 0 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_flexio_flexio_flexio2_flexio29: IOMUXC1_CCM_CLKO4_FLEXIO_FLEXIO_FLEXIO2_FLEXIO29 { + pinmux = <0x443c0094 4 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_gpio_io_gpio4_io29: IOMUXC1_CCM_CLKO4_GPIO_IO_GPIO4_IO29 { + pinmux = <0x443c0094 5 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_flexio_flexio_flexio1_flexio30: IOMUXC1_DAP_TCLK_SWCLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO30 { + pinmux = <0x443c0008 4 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30: IOMUXC1_DAP_TCLK_SWCLK_GPIO_IO_GPIO3_IO30 { + pinmux = <0x443c0008 5 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_jtag_mux_tck_jtag_mux_tck: IOMUXC1_DAP_TCLK_SWCLK_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0008 0 0x443c03d4 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_DAP_TCLK_SWCLK_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0008 6 0x443c042c 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_can_tx_can2_tx: IOMUXC1_DAP_TDI_CAN_TX_CAN2_TX { + pinmux = <0x443c0000 3 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_flexio_flexio_flexio2_flexio30: IOMUXC1_DAP_TDI_FLEXIO_FLEXIO_FLEXIO2_FLEXIO30 { + pinmux = <0x443c0000 4 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_gpio_io_gpio3_io28: IOMUXC1_DAP_TDI_GPIO_IO_GPIO3_IO28 { + pinmux = <0x443c0000 5 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_DAP_TDI_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0000 0 0x443c03d8 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_lpuart_rx_lpuart5_rx: IOMUXC1_DAP_TDI_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0000 6 0x443c0430 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_mqs_left_mqs2_left: IOMUXC1_DAP_TDI_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0000 1 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_can_rx_can2_rx: IOMUXC1_DAP_TDO_TRACESWO_CAN_RX_CAN2_RX { + pinmux = <0x443c000c 3 0x443c0364 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_flexio_flexio_flexio1_flexio31: IOMUXC1_DAP_TDO_TRACESWO_FLEXIO_FLEXIO_FLEXIO1_FLEXIO31 { + pinmux = <0x443c000c 4 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31: IOMUXC1_DAP_TDO_TRACESWO_GPIO_IO_GPIO3_IO31 { + pinmux = <0x443c000c 5 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_DAP_TDO_TRACESWO_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c000c 0 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_lpuart_tx_lpuart5_tx: IOMUXC1_DAP_TDO_TRACESWO_LPUART_TX_LPUART5_TX { + pinmux = <0x443c000c 6 0x443c0434 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_mqs_right_mqs2_right: IOMUXC1_DAP_TDO_TRACESWO_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c000c 1 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_flexio_flexio_flexio2_flexio31: IOMUXC1_DAP_TMS_SWDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO31 { + pinmux = <0x443c0004 4 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29: IOMUXC1_DAP_TMS_SWDIO_GPIO_IO_GPIO3_IO29 { + pinmux = <0x443c0004 5 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_jtag_mux_tms_jtag_mux_tms: IOMUXC1_DAP_TMS_SWDIO_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c0004 0 0x443c03dc 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_DAP_TMS_SWDIO_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c0004 6 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC1_ENET1_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x443c0098 0 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_flexio_flexio_flexio2_flexio00: IOMUXC1_ENET1_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO00 { + pinmux = <0x443c0098 4 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_gpio_io_gpio4_io00: IOMUXC1_ENET1_MDC_GPIO_IO_GPIO4_IO00 { + pinmux = <0x443c0098 5 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_hsiomix_otg_id_hsiomix_otg_id1: IOMUXC1_ENET1_MDC_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID1 { + pinmux = <0x443c0098 3 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_i3c_scl_i3c2_scl: IOMUXC1_ENET1_MDC_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0098 2 0x443c03cc 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_lpuart_dcb_b_lpuart3_dcb_b: IOMUXC1_ENET1_MDC_LPUART_DCB_B_LPUART3_DCB_B { + pinmux = <0x443c0098 1 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC1_ENET1_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x443c009c 0 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_flexio_flexio_flexio2_flexio01: IOMUXC1_ENET1_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO01 { + pinmux = <0x443c009c 4 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_gpio_io_gpio4_io01: IOMUXC1_ENET1_MDIO_GPIO_IO_GPIO4_IO01 { + pinmux = <0x443c009c 5 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_hsiomix_otg_pwr_hsiomix_otg_pwr1: IOMUXC1_ENET1_MDIO_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR1 { + pinmux = <0x443c009c 3 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_i3c_sda_i3c2_sda: IOMUXC1_ENET1_MDIO_I3C_SDA_I3C2_SDA { + pinmux = <0x443c009c 2 0x443c03d0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_lpuart_rin_b_lpuart3_rin_b: IOMUXC1_ENET1_MDIO_LPUART_RIN_B_LPUART3_RIN_B { + pinmux = <0x443c009c 1 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC1_ENET1_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x443c00c0 0 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_flexio_flexio_flexio2_flexio10: IOMUXC1_ENET1_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO10 { + pinmux = <0x443c00c0 4 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_gpio_io_gpio4_io10: IOMUXC1_ENET1_RD0_GPIO_IO_GPIO4_IO10 { + pinmux = <0x443c00c0 5 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_lpuart_rx_lpuart3_rx: IOMUXC1_ENET1_RD0_LPUART_RX_LPUART3_RX { + pinmux = <0x443c00c0 1 0x443c0418 1 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC1_ENET1_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x443c00c4 0 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_flexio_flexio_flexio2_flexio11: IOMUXC1_ENET1_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO11 { + pinmux = <0x443c00c4 4 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_gpio_io_gpio4_io11: IOMUXC1_ENET1_RD1_GPIO_IO_GPIO4_IO11 { + pinmux = <0x443c00c4 5 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lptmr_alt_lptmr2_alt1: IOMUXC1_ENET1_RD1_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c00c4 3 0x443c0408 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_ENET1_RD1_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c00c4 1 0x443c0414 1 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC1_ENET1_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x443c00c8 0 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_flexio_flexio_flexio2_flexio12: IOMUXC1_ENET1_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO12 { + pinmux = <0x443c00c8 4 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_gpio_io_gpio4_io12: IOMUXC1_ENET1_RD2_GPIO_IO_GPIO4_IO12 { + pinmux = <0x443c00c8 5 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_lptmr_alt_lptmr2_alt2: IOMUXC1_ENET1_RD2_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c00c8 3 0x443c040c 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC1_ENET1_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x443c00cc 0 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_flexio_flexio_flexio2_flexio13: IOMUXC1_ENET1_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO13 { + pinmux = <0x443c00cc 4 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_gpio_io_gpio4_io13: IOMUXC1_ENET1_RD3_GPIO_IO_GPIO4_IO13 { + pinmux = <0x443c00cc 5 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_lptmr_alt_lptmr2_alt3: IOMUXC1_ENET1_RD3_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c00cc 3 0x443c0410 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_ccm_enet_qos_clock_generate_rx_clk_ccm_enet_qos_clock_generate_rx_clk: IOMUXC1_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK { + pinmux = <0x443c00bc 0 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC1_ENET1_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x443c00bc 1 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_flexio_flexio_flexio2_flexio09: IOMUXC1_ENET1_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO09 { + pinmux = <0x443c00bc 4 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_gpio_io_gpio4_io09: IOMUXC1_ENET1_RXC_GPIO_IO_GPIO4_IO09 { + pinmux = <0x443c00bc 5 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC1_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x443c00b8 0 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_flexio_flexio_flexio2_flexio08: IOMUXC1_ENET1_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO08 { + pinmux = <0x443c00b8 4 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08: IOMUXC1_ENET1_RX_CTL_GPIO_IO_GPIO4_IO08 { + pinmux = <0x443c00b8 5 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_hsiomix_otg_pwr_hsiomix_otg_pwr2: IOMUXC1_ENET1_RX_CTL_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR2 { + pinmux = <0x443c00b8 3 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_lpuart_dsr_b_lpuart3_dsr_b: IOMUXC1_ENET1_RX_CTL_LPUART_DSR_B_LPUART3_DSR_B { + pinmux = <0x443c00b8 1 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC1_ENET1_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x443c00ac 0 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_flexio_flexio_flexio2_flexio05: IOMUXC1_ENET1_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO05 { + pinmux = <0x443c00ac 4 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_gpio_io_gpio4_io05: IOMUXC1_ENET1_TD0_GPIO_IO_GPIO4_IO05 { + pinmux = <0x443c00ac 5 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_lpuart_tx_lpuart3_tx: IOMUXC1_ENET1_TD0_LPUART_TX_LPUART3_TX { + pinmux = <0x443c00ac 1 0x443c041c 1 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC1_ENET1_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x443c00a8 0 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_flexio_flexio_flexio2_flexio04: IOMUXC1_ENET1_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO04 { + pinmux = <0x443c00a8 4 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_gpio_io_gpio4_io04: IOMUXC1_ENET1_TD1_GPIO_IO_GPIO4_IO04 { + pinmux = <0x443c00a8 5 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_hsiomix_otg_oc_hsiomix_otg_oc1: IOMUXC1_ENET1_TD1_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC1 { + pinmux = <0x443c00a8 3 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_b_i3c2_pur_b: IOMUXC1_ENET1_TD1_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c00a8 6 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_i3c2_pur: IOMUXC1_ENET1_TD1_I3C_PUR_I3C2_PUR { + pinmux = <0x443c00a8 2 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_ENET1_TD1_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c00a8 1 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_can_rx_can2_rx: IOMUXC1_ENET1_TD2_CAN_RX_CAN2_RX { + pinmux = <0x443c00a4 2 0x443c0364 2 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_ccm_enet_qos_clock_generate_ref_clk_ccm_enet_qos_clock_generate_ref_clk: IOMUXC1_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK { + pinmux = <0x443c00a4 1 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC1_ENET1_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x443c00a4 0 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_flexio_flexio_flexio2_flexio03: IOMUXC1_ENET1_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO03 { + pinmux = <0x443c00a4 4 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_gpio_io_gpio4_io03: IOMUXC1_ENET1_TD2_GPIO_IO_GPIO4_IO03 { + pinmux = <0x443c00a4 5 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_hsiomix_otg_oc_hsiomix_otg_oc2: IOMUXC1_ENET1_TD2_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC2 { + pinmux = <0x443c00a4 3 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_can_tx_can2_tx: IOMUXC1_ENET1_TD3_CAN_TX_CAN2_TX { + pinmux = <0x443c00a0 2 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC1_ENET1_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x443c00a0 0 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_flexio_flexio_flexio2_flexio02: IOMUXC1_ENET1_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO02 { + pinmux = <0x443c00a0 4 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_gpio_io_gpio4_io02: IOMUXC1_ENET1_TD3_GPIO_IO_GPIO4_IO02 { + pinmux = <0x443c00a0 5 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_hsiomix_otg_id_hsiomix_otg_id2: IOMUXC1_ENET1_TD3_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID2 { + pinmux = <0x443c00a0 3 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_ccm_enet_qos_clock_generate_tx_clk_ccm_enet_qos_clock_generate_tx_clk: IOMUXC1_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK { + pinmux = <0x443c00b4 0 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC1_ENET1_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x443c00b4 1 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_flexio_flexio_flexio2_flexio07: IOMUXC1_ENET1_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO07 { + pinmux = <0x443c00b4 4 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_gpio_io_gpio4_io07: IOMUXC1_ENET1_TXC_GPIO_IO_GPIO4_IO07 { + pinmux = <0x443c00b4 5 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC1_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x443c00b0 0 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_flexio_flexio_flexio2_flexio06: IOMUXC1_ENET1_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO06 { + pinmux = <0x443c00b0 4 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06: IOMUXC1_ENET1_TX_CTL_GPIO_IO_GPIO4_IO06 { + pinmux = <0x443c00b0 5 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_lpuart_dtr_b_lpuart3_dtr_b: IOMUXC1_ENET1_TX_CTL_LPUART_DTR_B_LPUART3_DTR_B { + pinmux = <0x443c00b0 1 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_enet_mdc_enet1_mdc: IOMUXC1_ENET2_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x443c00d0 0 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_flexio_flexio_flexio2_flexio14: IOMUXC1_ENET2_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO14 { + pinmux = <0x443c00d0 4 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_gpio_io_gpio4_io14: IOMUXC1_ENET2_MDC_GPIO_IO_GPIO4_IO14 { + pinmux = <0x443c00d0 5 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_lpuart_dcb_b_lpuart4_dcb_b: IOMUXC1_ENET2_MDC_LPUART_DCB_B_LPUART4_DCB_B { + pinmux = <0x443c00d0 1 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_sai_rx_sync_sai2_rx_sync: IOMUXC1_ENET2_MDC_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x443c00d0 2 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_enet_mdio_enet1_mdio: IOMUXC1_ENET2_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x443c00d4 0 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_flexio_flexio_flexio2_flexio15: IOMUXC1_ENET2_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO15 { + pinmux = <0x443c00d4 4 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_gpio_io_gpio4_io15: IOMUXC1_ENET2_MDIO_GPIO_IO_GPIO4_IO15 { + pinmux = <0x443c00d4 5 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_lpuart_rin_b_lpuart4_rin_b: IOMUXC1_ENET2_MDIO_LPUART_RIN_B_LPUART4_RIN_B { + pinmux = <0x443c00d4 1 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_sai_rx_bclk_sai2_rx_bclk: IOMUXC1_ENET2_MDIO_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x443c00d4 2 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC1_ENET2_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x443c00f8 0 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_flexio_flexio_flexio2_flexio24: IOMUXC1_ENET2_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO24 { + pinmux = <0x443c00f8 4 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_gpio_io_gpio4_io24: IOMUXC1_ENET2_RD0_GPIO_IO_GPIO4_IO24 { + pinmux = <0x443c00f8 5 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_lpuart_rx_lpuart4_rx: IOMUXC1_ENET2_RD0_LPUART_RX_LPUART4_RX { + pinmux = <0x443c00f8 1 0x443c0424 1 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_sai_tx_data_sai2_tx_data02: IOMUXC1_ENET2_RD0_SAI_TX_DATA_SAI2_TX_DATA02 { + pinmux = <0x443c00f8 2 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC1_ENET2_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x443c00fc 0 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_flexio_flexio_flexio2_flexio25: IOMUXC1_ENET2_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO25 { + pinmux = <0x443c00fc 4 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_gpio_io_gpio4_io25: IOMUXC1_ENET2_RD1_GPIO_IO_GPIO4_IO25 { + pinmux = <0x443c00fc 5 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_sai_tx_data_sai2_tx_data03: IOMUXC1_ENET2_RD1_SAI_TX_DATA_SAI2_TX_DATA03 { + pinmux = <0x443c00fc 2 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_spdif_in_spdif_in: IOMUXC1_ENET2_RD1_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c00fc 1 0x443c0454 1 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC1_ENET2_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x443c0100 0 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_flexio_flexio_flexio2_flexio26: IOMUXC1_ENET2_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO26 { + pinmux = <0x443c0100 4 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_gpio_io_gpio4_io26: IOMUXC1_ENET2_RD2_GPIO_IO_GPIO4_IO26 { + pinmux = <0x443c0100 5 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_ENET2_RD2_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0100 1 0x443c0420 1 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_mqs_right_mqs2_right: IOMUXC1_ENET2_RD2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0100 3 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_sai_mclk_sai2_mclk: IOMUXC1_ENET2_RD2_SAI_MCLK_SAI2_MCLK { + pinmux = <0x443c0100 2 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC1_ENET2_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x443c0104 0 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_flexio_flexio_flexio2_flexio27: IOMUXC1_ENET2_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO27 { + pinmux = <0x443c0104 4 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_gpio_io_gpio4_io27: IOMUXC1_ENET2_RD3_GPIO_IO_GPIO4_IO27 { + pinmux = <0x443c0104 5 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_mqs_left_mqs2_left: IOMUXC1_ENET2_RD3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0104 3 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_in_spdif_in: IOMUXC1_ENET2_RD3_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0104 2 0x443c0454 2 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_out_spdif_out: IOMUXC1_ENET2_RD3_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c0104 1 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC1_ENET2_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x443c00f4 0 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rx_er_enet1_rx_er: IOMUXC1_ENET2_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x443c00f4 1 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_flexio_flexio_flexio2_flexio23: IOMUXC1_ENET2_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO23 { + pinmux = <0x443c00f4 4 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_gpio_io_gpio4_io23: IOMUXC1_ENET2_RXC_GPIO_IO_GPIO4_IO23 { + pinmux = <0x443c00f4 5 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_sai_tx_data_sai2_tx_data01: IOMUXC1_ENET2_RXC_SAI_TX_DATA_SAI2_TX_DATA01 { + pinmux = <0x443c00f4 2 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC1_ENET2_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x443c00f0 0 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_flexio_flexio_flexio2_flexio22: IOMUXC1_ENET2_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO22 { + pinmux = <0x443c00f0 4 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22: IOMUXC1_ENET2_RX_CTL_GPIO_IO_GPIO4_IO22 { + pinmux = <0x443c00f0 5 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_lpuart_dsr_b_lpuart4_dsr_b: IOMUXC1_ENET2_RX_CTL_LPUART_DSR_B_LPUART4_DSR_B { + pinmux = <0x443c00f0 1 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_sai_tx_data_sai2_tx_data00: IOMUXC1_ENET2_RX_CTL_SAI_TX_DATA_SAI2_TX_DATA00 { + pinmux = <0x443c00f0 2 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC1_ENET2_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x443c00e4 0 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_flexio_flexio_flexio2_flexio19: IOMUXC1_ENET2_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO19 { + pinmux = <0x443c00e4 4 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_gpio_io_gpio4_io19: IOMUXC1_ENET2_TD0_GPIO_IO_GPIO4_IO19 { + pinmux = <0x443c00e4 5 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_lpuart_tx_lpuart4_tx: IOMUXC1_ENET2_TD0_LPUART_TX_LPUART4_TX { + pinmux = <0x443c00e4 1 0x443c0428 1 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_sai_rx_data_sai2_rx_data03: IOMUXC1_ENET2_TD0_SAI_RX_DATA_SAI2_RX_DATA03 { + pinmux = <0x443c00e4 2 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC1_ENET2_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x443c00e0 0 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_flexio_flexio_flexio2_flexio18: IOMUXC1_ENET2_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO18 { + pinmux = <0x443c00e0 4 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_gpio_io_gpio4_io18: IOMUXC1_ENET2_TD1_GPIO_IO_GPIO4_IO18 { + pinmux = <0x443c00e0 5 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_ENET2_TD1_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c00e0 1 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_sai_rx_data_sai2_rx_data02: IOMUXC1_ENET2_TD1_SAI_RX_DATA_SAI2_RX_DATA02 { + pinmux = <0x443c00e0 2 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC1_ENET2_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x443c00dc 0 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_tx_clk_enet1_tx_clk: IOMUXC1_ENET2_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x443c00dc 1 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_flexio_flexio_flexio2_flexio17: IOMUXC1_ENET2_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO17 { + pinmux = <0x443c00dc 4 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_gpio_io_gpio4_io17: IOMUXC1_ENET2_TD2_GPIO_IO_GPIO4_IO17 { + pinmux = <0x443c00dc 5 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_sai_rx_data_sai2_rx_data01: IOMUXC1_ENET2_TD2_SAI_RX_DATA_SAI2_RX_DATA01 { + pinmux = <0x443c00dc 2 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC1_ENET2_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x443c00d8 0 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_flexio_flexio_flexio2_flexio16: IOMUXC1_ENET2_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO16 { + pinmux = <0x443c00d8 4 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_gpio_io_gpio4_io16: IOMUXC1_ENET2_TD3_GPIO_IO_GPIO4_IO16 { + pinmux = <0x443c00d8 5 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_sai_rx_data_sai2_rx_data00: IOMUXC1_ENET2_TD3_SAI_RX_DATA_SAI2_RX_DATA00 { + pinmux = <0x443c00d8 2 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC1_ENET2_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x443c00ec 0 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_tx_er_enet1_tx_er: IOMUXC1_ENET2_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x443c00ec 1 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_flexio_flexio_flexio2_flexio21: IOMUXC1_ENET2_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO21 { + pinmux = <0x443c00ec 4 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_gpio_io_gpio4_io21: IOMUXC1_ENET2_TXC_GPIO_IO_GPIO4_IO21 { + pinmux = <0x443c00ec 5 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC1_ENET2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x443c00ec 2 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC1_ENET2_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x443c00e8 0 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_flexio_flexio_flexio2_flexio20: IOMUXC1_ENET2_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO20 { + pinmux = <0x443c00e8 4 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20: IOMUXC1_ENET2_TX_CTL_GPIO_IO_GPIO4_IO20 { + pinmux = <0x443c00e8 5 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_lpuart_dtr_b_lpuart4_dtr_b: IOMUXC1_ENET2_TX_CTL_LPUART_DTR_B_LPUART4_DTR_B { + pinmux = <0x443c00e8 1 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_sai_tx_sync_sai2_tx_sync: IOMUXC1_ENET2_TX_CTL_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x443c00e8 2 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_flexio_flexio_flexio1_flexio00: IOMUXC1_GPIO_IO00_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0010 7 0x443c036c 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_gpio_io_gpio2_io00: IOMUXC1_GPIO_IO00_GPIO_IO_GPIO2_IO00 { + pinmux = <0x443c0010 0 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0010 1 0x443c03e4 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0010 6 0x443c03ec 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpspi_pcs_lpspi6_pcs0: IOMUXC1_GPIO_IO00_LPSPI_PCS_LPSPI6_PCS0 { + pinmux = <0x443c0010 4 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpuart_tx_lpuart5_tx: IOMUXC1_GPIO_IO00_LPUART_TX_LPUART5_TX { + pinmux = <0x443c0010 5 0x443c0434 1 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_cam_clk_mediamix_cam_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_CAM_CLK_MEDIAMIX_CAM_CLK { + pinmux = <0x443c0010 2 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_disp_clk_mediamix_disp_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_DISP_CLK_MEDIAMIX_DISP_CLK { + pinmux = <0x443c0010 3 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_flexio_flexio_flexio1_flexio01: IOMUXC1_GPIO_IO01_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0014 7 0x443c0370 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_gpio_io_gpio2_io01: IOMUXC1_GPIO_IO01_GPIO_IO_GPIO2_IO01 { + pinmux = <0x443c0014 0 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0014 1 0x443c03e0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c0014 6 0x443c03e8 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpspi_sin_lpspi6_sin: IOMUXC1_GPIO_IO01_LPSPI_SIN_LPSPI6_SIN { + pinmux = <0x443c0014 4 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpuart_rx_lpuart5_rx: IOMUXC1_GPIO_IO01_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0014 5 0x443c0430 1 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_cam_data_mediamix_cam_data00: IOMUXC1_GPIO_IO01_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA00 { + pinmux = <0x443c0014 2 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_disp_de_mediamix_disp_de: IOMUXC1_GPIO_IO01_MEDIAMIX_DISP_DE_MEDIAMIX_DISP_DE { + pinmux = <0x443c0014 3 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_flexio_flexio_flexio1_flexio02: IOMUXC1_GPIO_IO02_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0018 7 0x443c0374 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_gpio_io_gpio2_io02: IOMUXC1_GPIO_IO02_GPIO_IO_GPIO2_IO02 { + pinmux = <0x443c0018 0 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C4_SDA { + pinmux = <0x443c0018 1 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0018 6 0x443c03f4 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpspi_sout_lpspi6_sout: IOMUXC1_GPIO_IO02_LPSPI_SOUT_LPSPI6_SOUT { + pinmux = <0x443c0018 4 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_GPIO_IO02_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0018 5 0x443c042c 1 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_cam_vsync_mediamix_cam_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_CAM_VSYNC_MEDIAMIX_CAM_VSYNC { + pinmux = <0x443c0018 2 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_disp_vsync_mediamix_disp_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_DISP_VSYNC_MEDIAMIX_DISP_VSYNC { + pinmux = <0x443c0018 3 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_flexio_flexio_flexio1_flexio03: IOMUXC1_GPIO_IO03_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c001c 7 0x443c0378 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_gpio_io_gpio2_io03: IOMUXC1_GPIO_IO03_GPIO_IO_GPIO2_IO03 { + pinmux = <0x443c001c 0 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C4_SCL { + pinmux = <0x443c001c 1 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c001c 6 0x443c03f0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpspi_sck_lpspi6_sck: IOMUXC1_GPIO_IO03_LPSPI_SCK_LPSPI6_SCK { + pinmux = <0x443c001c 4 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_GPIO_IO03_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c001c 5 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_cam_hsync_mediamix_cam_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_CAM_HSYNC_MEDIAMIX_CAM_HSYNC { + pinmux = <0x443c001c 2 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_disp_hsync_mediamix_disp_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_DISP_HSYNC_MEDIAMIX_DISP_HSYNC { + pinmux = <0x443c001c 3 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_flexio_flexio_flexio1_flexio04: IOMUXC1_GPIO_IO04_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0020 7 0x443c037c 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_gpio_io_gpio2_io04: IOMUXC1_GPIO_IO04_GPIO_IO_GPIO2_IO04 { + pinmux = <0x443c0020 0 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO04_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0020 6 0x443c03f4 1 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpspi_pcs_lpspi7_pcs0: IOMUXC1_GPIO_IO04_LPSPI_PCS_LPSPI7_PCS0 { + pinmux = <0x443c0020 4 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpuart_tx_lpuart6_tx: IOMUXC1_GPIO_IO04_LPUART_TX_LPUART6_TX { + pinmux = <0x443c0020 5 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_mediamix_disp_data_mediamix_disp_data00: IOMUXC1_GPIO_IO04_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA00 { + pinmux = <0x443c0020 3 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO04_PDM_CLK_PDM_CLK { + pinmux = <0x443c0020 2 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_tpm_ch_tpm3_ch0: IOMUXC1_GPIO_IO04_TPM_CH_TPM3_CH0 { + pinmux = <0x443c0020 1 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_flexio_flexio_flexio1_flexio05: IOMUXC1_GPIO_IO05_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0024 7 0x443c0380 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_gpio_io_gpio2_io05: IOMUXC1_GPIO_IO05_GPIO_IO_GPIO2_IO05 { + pinmux = <0x443c0024 0 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO05_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c0024 6 0x443c03f0 1 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpspi_sin_lpspi7_sin: IOMUXC1_GPIO_IO05_LPSPI_SIN_LPSPI7_SIN { + pinmux = <0x443c0024 4 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpuart_rx_lpuart6_rx: IOMUXC1_GPIO_IO05_LPUART_RX_LPUART6_RX { + pinmux = <0x443c0024 5 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_mediamix_disp_data_mediamix_disp_data01: IOMUXC1_GPIO_IO05_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA01 { + pinmux = <0x443c0024 3 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO05_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0024 2 0x443c0438 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_tpm_ch_tpm4_ch0: IOMUXC1_GPIO_IO05_TPM_CH_TPM4_CH0 { + pinmux = <0x443c0024 1 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_flexio_flexio_flexio1_flexio06: IOMUXC1_GPIO_IO06_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0028 7 0x443c0384 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_gpio_io_gpio2_io06: IOMUXC1_GPIO_IO06_GPIO_IO_GPIO2_IO06 { + pinmux = <0x443c0028 0 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO06_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0028 6 0x443c03fc 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpspi_sout_lpspi7_sout: IOMUXC1_GPIO_IO06_LPSPI_SOUT_LPSPI7_SOUT { + pinmux = <0x443c0028 4 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpuart_cts_b_lpuart6_cts_b: IOMUXC1_GPIO_IO06_LPUART_CTS_B_LPUART6_CTS_B { + pinmux = <0x443c0028 5 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_mediamix_disp_data_mediamix_disp_data02: IOMUXC1_GPIO_IO06_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA02 { + pinmux = <0x443c0028 3 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO06_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0028 2 0x443c043c 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_tpm_ch_tpm5_ch0: IOMUXC1_GPIO_IO06_TPM_CH_TPM5_CH0 { + pinmux = <0x443c0028 1 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_flexio_flexio_flexio1_flexio07: IOMUXC1_GPIO_IO07_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c002c 7 0x443c0388 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_gpio_io_gpio2_io07: IOMUXC1_GPIO_IO07_GPIO_IO_GPIO2_IO07 { + pinmux = <0x443c002c 0 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO07_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c002c 6 0x443c03f8 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1: IOMUXC1_GPIO_IO07_LPSPI_PCS_LPSPI3_PCS1 { + pinmux = <0x443c002c 1 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_sck_lpspi7_sck: IOMUXC1_GPIO_IO07_LPSPI_SCK_LPSPI7_SCK { + pinmux = <0x443c002c 4 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpuart_rts_b_lpuart6_rts_b: IOMUXC1_GPIO_IO07_LPUART_RTS_B_LPUART6_RTS_B { + pinmux = <0x443c002c 5 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_cam_data_mediamix_cam_data01: IOMUXC1_GPIO_IO07_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA01 { + pinmux = <0x443c002c 2 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_disp_data_mediamix_disp_data03: IOMUXC1_GPIO_IO07_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA03 { + pinmux = <0x443c002c 3 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_flexio_flexio_flexio1_flexio08: IOMUXC1_GPIO_IO08_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0030 7 0x443c038c 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_gpio_io_gpio2_io08: IOMUXC1_GPIO_IO08_GPIO_IO_GPIO2_IO08 { + pinmux = <0x443c0030 0 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO08_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0030 6 0x443c03fc 1 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0: IOMUXC1_GPIO_IO08_LPSPI_PCS_LPSPI3_PCS0 { + pinmux = <0x443c0030 1 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpuart_tx_lpuart7_tx: IOMUXC1_GPIO_IO08_LPUART_TX_LPUART7_TX { + pinmux = <0x443c0030 5 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_cam_data_mediamix_cam_data02: IOMUXC1_GPIO_IO08_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA02 { + pinmux = <0x443c0030 2 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_disp_data_mediamix_disp_data04: IOMUXC1_GPIO_IO08_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA04 { + pinmux = <0x443c0030 3 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_tpm_ch_tpm6_ch0: IOMUXC1_GPIO_IO08_TPM_CH_TPM6_CH0 { + pinmux = <0x443c0030 4 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_flexio_flexio_flexio1_flexio09: IOMUXC1_GPIO_IO09_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c0034 7 0x443c0390 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_gpio_io_gpio2_io09: IOMUXC1_GPIO_IO09_GPIO_IO_GPIO2_IO09 { + pinmux = <0x443c0034 0 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO09_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c0034 6 0x443c03f8 1 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin: IOMUXC1_GPIO_IO09_LPSPI_SIN_LPSPI3_SIN { + pinmux = <0x443c0034 1 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpuart_rx_lpuart7_rx: IOMUXC1_GPIO_IO09_LPUART_RX_LPUART7_RX { + pinmux = <0x443c0034 5 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_cam_data_mediamix_cam_data03: IOMUXC1_GPIO_IO09_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA03 { + pinmux = <0x443c0034 2 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_disp_data_mediamix_disp_data05: IOMUXC1_GPIO_IO09_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA05 { + pinmux = <0x443c0034 3 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_tpm_extclk_tpm3_extclk: IOMUXC1_GPIO_IO09_TPM_EXTCLK_TPM3_EXTCLK { + pinmux = <0x443c0034 4 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_flexio_flexio_flexio1_flexio10: IOMUXC1_GPIO_IO10_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0038 7 0x443c0394 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_gpio_io_gpio2_io10: IOMUXC1_GPIO_IO10_GPIO_IO_GPIO2_IO10 { + pinmux = <0x443c0038 0 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO10_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0038 6 0x443c0404 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout: IOMUXC1_GPIO_IO10_LPSPI_SOUT_LPSPI3_SOUT { + pinmux = <0x443c0038 1 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpuart_cts_b_lpuart7_cts_b: IOMUXC1_GPIO_IO10_LPUART_CTS_B_LPUART7_CTS_B { + pinmux = <0x443c0038 5 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_cam_data_mediamix_cam_data04: IOMUXC1_GPIO_IO10_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA04 { + pinmux = <0x443c0038 2 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_disp_data_mediamix_disp_data06: IOMUXC1_GPIO_IO10_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA06 { + pinmux = <0x443c0038 3 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_tpm_extclk_tpm4_extclk: IOMUXC1_GPIO_IO10_TPM_EXTCLK_TPM4_EXTCLK { + pinmux = <0x443c0038 4 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_flexio_flexio_flexio1_flexio11: IOMUXC1_GPIO_IO11_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c003c 7 0x443c0398 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_gpio_io_gpio2_io11: IOMUXC1_GPIO_IO11_GPIO_IO_GPIO2_IO11 { + pinmux = <0x443c003c 0 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO11_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c003c 6 0x443c0400 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck: IOMUXC1_GPIO_IO11_LPSPI_SCK_LPSPI3_SCK { + pinmux = <0x443c003c 1 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpuart_rts_b_lpuart7_rts_b: IOMUXC1_GPIO_IO11_LPUART_RTS_B_LPUART7_RTS_B { + pinmux = <0x443c003c 5 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_cam_data_mediamix_cam_data05: IOMUXC1_GPIO_IO11_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA05 { + pinmux = <0x443c003c 2 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_disp_data_mediamix_disp_data07: IOMUXC1_GPIO_IO11_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA07 { + pinmux = <0x443c003c 3 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_tpm_extclk_tpm5_extclk: IOMUXC1_GPIO_IO11_TPM_EXTCLK_TPM5_EXTCLK { + pinmux = <0x443c003c 4 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_gpio_io_gpio2_io12: IOMUXC1_GPIO_IO12_GPIO_IO_GPIO2_IO12 { + pinmux = <0x443c0040 0 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO12_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0040 6 0x443c0404 1 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpspi_pcs_lpspi8_pcs0: IOMUXC1_GPIO_IO12_LPSPI_PCS_LPSPI8_PCS0 { + pinmux = <0x443c0040 4 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpuart_tx_lpuart8_tx: IOMUXC1_GPIO_IO12_LPUART_TX_LPUART8_TX { + pinmux = <0x443c0040 5 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_mediamix_disp_data_mediamix_disp_data08: IOMUXC1_GPIO_IO12_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA08 { + pinmux = <0x443c0040 3 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO12_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0040 2 0x443c0440 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO12_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c0040 7 0x443c0450 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_tpm_ch_tpm3_ch2: IOMUXC1_GPIO_IO12_TPM_CH_TPM3_CH2 { + pinmux = <0x443c0040 1 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_flexio_flexio_flexio1_flexio13: IOMUXC1_GPIO_IO13_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c0044 7 0x443c039c 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_gpio_io_gpio2_io13: IOMUXC1_GPIO_IO13_GPIO_IO_GPIO2_IO13 { + pinmux = <0x443c0044 0 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO13_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c0044 6 0x443c0400 1 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpspi_sin_lpspi8_sin: IOMUXC1_GPIO_IO13_LPSPI_SIN_LPSPI8_SIN { + pinmux = <0x443c0044 4 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpuart_rx_lpuart8_rx: IOMUXC1_GPIO_IO13_LPUART_RX_LPUART8_RX { + pinmux = <0x443c0044 5 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_mediamix_disp_data_mediamix_disp_data09: IOMUXC1_GPIO_IO13_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA09 { + pinmux = <0x443c0044 3 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO13_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c0044 2 0x443c0444 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_tpm_ch_tpm4_ch2: IOMUXC1_GPIO_IO13_TPM_CH_TPM4_CH2 { + pinmux = <0x443c0044 1 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_flexio_flexio_flexio1_flexio14: IOMUXC1_GPIO_IO14_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0048 7 0x443c03a0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_gpio_io_gpio2_io14: IOMUXC1_GPIO_IO14_GPIO_IO_GPIO2_IO14 { + pinmux = <0x443c0048 0 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpspi_sout_lpspi8_sout: IOMUXC1_GPIO_IO14_LPSPI_SOUT_LPSPI8_SOUT { + pinmux = <0x443c0048 4 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_cts_b_lpuart8_cts_b: IOMUXC1_GPIO_IO14_LPUART_CTS_B_LPUART8_CTS_B { + pinmux = <0x443c0048 5 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart3_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART3_TX { + pinmux = <0x443c0048 1 0x443c041c 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart4_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART4_TX { + pinmux = <0x443c0048 6 0x443c0428 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_cam_data_mediamix_cam_data06: IOMUXC1_GPIO_IO14_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA06 { + pinmux = <0x443c0048 2 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_disp_data_mediamix_disp_data10: IOMUXC1_GPIO_IO14_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA10 { + pinmux = <0x443c0048 3 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_flexio_flexio_flexio1_flexio15: IOMUXC1_GPIO_IO15_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c004c 7 0x443c03a4 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_gpio_io_gpio2_io15: IOMUXC1_GPIO_IO15_GPIO_IO_GPIO2_IO15 { + pinmux = <0x443c004c 0 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpspi_sck_lpspi8_sck: IOMUXC1_GPIO_IO15_LPSPI_SCK_LPSPI8_SCK { + pinmux = <0x443c004c 4 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rts_b_lpuart8_rts_b: IOMUXC1_GPIO_IO15_LPUART_RTS_B_LPUART8_RTS_B { + pinmux = <0x443c004c 5 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart3_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART3_RX { + pinmux = <0x443c004c 1 0x443c0418 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart4_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART4_RX { + pinmux = <0x443c004c 6 0x443c0424 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_cam_data_mediamix_cam_data07: IOMUXC1_GPIO_IO15_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA07 { + pinmux = <0x443c004c 2 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_disp_data_mediamix_disp_data11: IOMUXC1_GPIO_IO15_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA11 { + pinmux = <0x443c004c 3 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_flexio_flexio_flexio1_flexio16: IOMUXC1_GPIO_IO16_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0050 7 0x443c03a8 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_gpio_io_gpio2_io16: IOMUXC1_GPIO_IO16_GPIO_IO_GPIO2_IO16 { + pinmux = <0x443c0050 0 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpspi_pcs_lpspi4_pcs2: IOMUXC1_GPIO_IO16_LPSPI_PCS_LPSPI4_PCS2 { + pinmux = <0x443c0050 5 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c0050 4 0x443c0414 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0050 6 0x443c0420 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_mediamix_disp_data_mediamix_disp_data12: IOMUXC1_GPIO_IO16_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA12 { + pinmux = <0x443c0050 3 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO16_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0050 2 0x443c0440 1 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk: IOMUXC1_GPIO_IO16_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x443c0050 1 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_flexio_flexio_flexio1_flexio17: IOMUXC1_GPIO_IO17_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c0054 7 0x443c03ac 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_gpio_io_gpio2_io17: IOMUXC1_GPIO_IO17_GPIO_IO_GPIO2_IO17 { + pinmux = <0x443c0054 0 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpspi_pcs_lpspi4_pcs1: IOMUXC1_GPIO_IO17_LPSPI_PCS_LPSPI4_PCS1 { + pinmux = <0x443c0054 5 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c0054 4 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c0054 6 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_cam_data_mediamix_cam_data08: IOMUXC1_GPIO_IO17_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA08 { + pinmux = <0x443c0054 2 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_disp_data_mediamix_disp_data13: IOMUXC1_GPIO_IO17_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA13 { + pinmux = <0x443c0054 3 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_sai_mclk_sai3_mclk: IOMUXC1_GPIO_IO17_SAI_MCLK_SAI3_MCLK { + pinmux = <0x443c0054 1 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_flexio_flexio_flexio1_flexio18: IOMUXC1_GPIO_IO18_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0058 7 0x443c03b0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_gpio_io_gpio2_io18: IOMUXC1_GPIO_IO18_GPIO_IO_GPIO2_IO18 { + pinmux = <0x443c0058 0 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi4_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI4_PCS0 { + pinmux = <0x443c0058 5 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi5_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI5_PCS0 { + pinmux = <0x443c0058 4 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_cam_data_mediamix_cam_data09: IOMUXC1_GPIO_IO18_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA09 { + pinmux = <0x443c0058 2 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_disp_data_mediamix_disp_data14: IOMUXC1_GPIO_IO18_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA14 { + pinmux = <0x443c0058 3 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO18_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0058 1 0x443c044c 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_tpm_ch_tpm5_ch2: IOMUXC1_GPIO_IO18_TPM_CH_TPM5_CH2 { + pinmux = <0x443c0058 6 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_gpio_io_gpio2_io19: IOMUXC1_GPIO_IO19_GPIO_IO_GPIO2_IO19 { + pinmux = <0x443c005c 0 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi4_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI4_SIN { + pinmux = <0x443c005c 5 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi5_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI5_SIN { + pinmux = <0x443c005c 4 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_mediamix_disp_data_mediamix_disp_data15: IOMUXC1_GPIO_IO19_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA15 { + pinmux = <0x443c005c 3 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO19_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c005c 2 0x443c0444 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO19_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c005c 1 0x443c0450 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO19_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c005c 7 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_tpm_ch_tpm6_ch2: IOMUXC1_GPIO_IO19_TPM_CH_TPM6_CH2 { + pinmux = <0x443c005c 6 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_flexio_flexio_flexio1_flexio20: IOMUXC1_GPIO_IO20_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0060 7 0x443c03b4 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_gpio_io_gpio2_io20: IOMUXC1_GPIO_IO20_GPIO_IO_GPIO2_IO20 { + pinmux = <0x443c0060 0 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi4_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI4_SOUT { + pinmux = <0x443c0060 5 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi5_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI5_SOUT { + pinmux = <0x443c0060 4 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_mediamix_disp_data_mediamix_disp_data16: IOMUXC1_GPIO_IO20_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA16 { + pinmux = <0x443c0060 3 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO20_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0060 2 0x443c0438 1 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data00: IOMUXC1_GPIO_IO20_SAI_RX_DATA_SAI3_RX_DATA00 { + pinmux = <0x443c0060 1 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_tpm_ch_tpm3_ch1: IOMUXC1_GPIO_IO20_TPM_CH_TPM3_CH1 { + pinmux = <0x443c0060 6 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_gpio_io_gpio2_io21: IOMUXC1_GPIO_IO21_GPIO_IO_GPIO2_IO21 { + pinmux = <0x443c0064 0 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi4_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI4_SCK { + pinmux = <0x443c0064 5 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi5_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI5_SCK { + pinmux = <0x443c0064 4 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_mediamix_disp_data_mediamix_disp_data17: IOMUXC1_GPIO_IO21_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA17 { + pinmux = <0x443c0064 3 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO21_PDM_CLK_PDM_CLK { + pinmux = <0x443c0064 2 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO21_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0064 7 0x443c044c 1 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO21_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c0064 1 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_tpm_ch_tpm4_ch1: IOMUXC1_GPIO_IO21_TPM_CH_TPM4_CH1 { + pinmux = <0x443c0064 6 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_flexio_flexio_flexio1_flexio22: IOMUXC1_GPIO_IO22_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0068 7 0x443c03b8 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_gpio_io_gpio2_io22: IOMUXC1_GPIO_IO22_GPIO_IO_GPIO2_IO22 { + pinmux = <0x443c0068 0 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO22_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0068 6 0x443c03ec 1 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_mediamix_disp_data_mediamix_disp_data18: IOMUXC1_GPIO_IO22_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA18 { + pinmux = <0x443c0068 3 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_spdif_in_spdif_in: IOMUXC1_GPIO_IO22_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0068 2 0x443c0454 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_ch_tpm5_ch1: IOMUXC1_GPIO_IO22_TPM_CH_TPM5_CH1 { + pinmux = <0x443c0068 4 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_extclk_tpm6_extclk: IOMUXC1_GPIO_IO22_TPM_EXTCLK_TPM6_EXTCLK { + pinmux = <0x443c0068 5 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_usdhc_clk_usdhc3_clk: IOMUXC1_GPIO_IO22_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0068 1 0x443c0458 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_flexio_flexio_flexio1_flexio23: IOMUXC1_GPIO_IO23_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c006c 7 0x443c03bc 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_gpio_io_gpio2_io23: IOMUXC1_GPIO_IO23_GPIO_IO_GPIO2_IO23 { + pinmux = <0x443c006c 0 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO23_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c006c 6 0x443c03e8 1 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_mediamix_disp_data_mediamix_disp_data19: IOMUXC1_GPIO_IO23_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA19 { + pinmux = <0x443c006c 3 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_spdif_out_spdif_out: IOMUXC1_GPIO_IO23_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c006c 2 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_tpm_ch_tpm6_ch1: IOMUXC1_GPIO_IO23_TPM_CH_TPM6_CH1 { + pinmux = <0x443c006c 4 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_usdhc_cmd_usdhc3_cmd: IOMUXC1_GPIO_IO23_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c006c 1 0x443c045c 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_flexio_flexio_flexio1_flexio24: IOMUXC1_GPIO_IO24_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0070 7 0x443c03c0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_gpio_io_gpio2_io24: IOMUXC1_GPIO_IO24_GPIO_IO_GPIO2_IO24 { + pinmux = <0x443c0070 0 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_GPIO_IO24_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c0070 5 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_lpspi_pcs_lpspi6_pcs1: IOMUXC1_GPIO_IO24_LPSPI_PCS_LPSPI6_PCS1 { + pinmux = <0x443c0070 6 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_mediamix_disp_data_mediamix_disp_data20: IOMUXC1_GPIO_IO24_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA20 { + pinmux = <0x443c0070 3 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_tpm_ch_tpm3_ch3: IOMUXC1_GPIO_IO24_TPM_CH_TPM3_CH3 { + pinmux = <0x443c0070 4 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_usdhc_data_usdhc3_data0: IOMUXC1_GPIO_IO24_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0070 1 0x443c0460 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_can_tx_can2_tx: IOMUXC1_GPIO_IO25_CAN_TX_CAN2_TX { + pinmux = <0x443c0074 2 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_flexio_flexio_flexio1_flexio25: IOMUXC1_GPIO_IO25_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c0074 7 0x443c03c4 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_gpio_io_gpio2_io25: IOMUXC1_GPIO_IO25_GPIO_IO_GPIO2_IO25 { + pinmux = <0x443c0074 0 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_jtag_mux_tck_jtag_mux_tck: IOMUXC1_GPIO_IO25_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0074 5 0x443c03d4 1 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_lpspi_pcs_lpspi7_pcs1: IOMUXC1_GPIO_IO25_LPSPI_PCS_LPSPI7_PCS1 { + pinmux = <0x443c0074 6 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_mediamix_disp_data_mediamix_disp_data21: IOMUXC1_GPIO_IO25_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA21 { + pinmux = <0x443c0074 3 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_tpm_ch_tpm4_ch3: IOMUXC1_GPIO_IO25_TPM_CH_TPM4_CH3 { + pinmux = <0x443c0074 4 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_usdhc_data_usdhc3_data1: IOMUXC1_GPIO_IO25_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0074 1 0x443c0464 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_gpio_io_gpio2_io26: IOMUXC1_GPIO_IO26_GPIO_IO_GPIO2_IO26 { + pinmux = <0x443c0078 0 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_GPIO_IO26_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0078 5 0x443c03d8 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_lpspi_pcs_lpspi8_pcs1: IOMUXC1_GPIO_IO26_LPSPI_PCS_LPSPI8_PCS1 { + pinmux = <0x443c0078 6 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_mediamix_disp_data_mediamix_disp_data22: IOMUXC1_GPIO_IO26_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA22 { + pinmux = <0x443c0078 3 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO26_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0078 2 0x443c043c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync: IOMUXC1_GPIO_IO26_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x443c0078 7 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_tpm_ch_tpm5_ch3: IOMUXC1_GPIO_IO26_TPM_CH_TPM5_CH3 { + pinmux = <0x443c0078 4 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_usdhc_data_usdhc3_data2: IOMUXC1_GPIO_IO26_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0078 1 0x443c0468 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_can_rx_can2_rx: IOMUXC1_GPIO_IO27_CAN_RX_CAN2_RX { + pinmux = <0x443c007c 2 0x443c0364 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_flexio_flexio_flexio1_flexio27: IOMUXC1_GPIO_IO27_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c007c 7 0x443c03c8 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_gpio_io_gpio2_io27: IOMUXC1_GPIO_IO27_GPIO_IO_GPIO2_IO27 { + pinmux = <0x443c007c 0 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_jtag_mux_tms_jtag_mux_tms: IOMUXC1_GPIO_IO27_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c007c 5 0x443c03dc 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_lpspi_pcs_lpspi5_pcs1: IOMUXC1_GPIO_IO27_LPSPI_PCS_LPSPI5_PCS1 { + pinmux = <0x443c007c 6 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_mediamix_disp_data_mediamix_disp_data23: IOMUXC1_GPIO_IO27_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA23 { + pinmux = <0x443c007c 3 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_tpm_ch_tpm6_ch3: IOMUXC1_GPIO_IO27_TPM_CH_TPM6_CH3 { + pinmux = <0x443c007c 4 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_usdhc_data_usdhc3_data3: IOMUXC1_GPIO_IO27_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c007c 1 0x443c046c 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_flexio_flexio_flexio1_flexio28: IOMUXC1_GPIO_IO28_FLEXIO_FLEXIO_FLEXIO1_FLEXIO28 { + pinmux = <0x443c0080 7 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_gpio_io_gpio2_io28: IOMUXC1_GPIO_IO28_GPIO_IO_GPIO2_IO28 { + pinmux = <0x443c0080 0 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO28_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0080 1 0x443c03e4 1 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_flexio_flexio_flexio1_flexio29: IOMUXC1_GPIO_IO29_FLEXIO_FLEXIO_FLEXIO1_FLEXIO29 { + pinmux = <0x443c0084 7 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_gpio_io_gpio2_io29: IOMUXC1_GPIO_IO29_GPIO_IO_GPIO2_IO29 { + pinmux = <0x443c0084 0 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO29_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0084 1 0x443c03e0 1 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_gpio_io_gpio1_io00: IOMUXC1_I2C1_SCL_GPIO_IO_GPIO1_IO00 { + pinmux = <0x443c0170 5 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_i3c_scl_i3c1_scl: IOMUXC1_I2C1_SCL_I3C_SCL_I3C1_SCL { + pinmux = <0x443c0170 1 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl: IOMUXC1_I2C1_SCL_LPI2C_SCL_LPI2C1_SCL { + pinmux = <0x443c0170 0 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpuart_dcb_b_lpuart1_dcb_b: IOMUXC1_I2C1_SCL_LPUART_DCB_B_LPUART1_DCB_B { + pinmux = <0x443c0170 2 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_tpm_ch_tpm2_ch0: IOMUXC1_I2C1_SCL_TPM_CH_TPM2_CH0 { + pinmux = <0x443c0170 3 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_gpio_io_gpio1_io01: IOMUXC1_I2C1_SDA_GPIO_IO_GPIO1_IO01 { + pinmux = <0x443c0174 5 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_i3c_sda_i3c1_sda: IOMUXC1_I2C1_SDA_I3C_SDA_I3C1_SDA { + pinmux = <0x443c0174 1 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda: IOMUXC1_I2C1_SDA_LPI2C_SDA_LPI2C1_SDA { + pinmux = <0x443c0174 0 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpuart_rin_b_lpuart1_rin_b: IOMUXC1_I2C1_SDA_LPUART_RIN_B_LPUART1_RIN_B { + pinmux = <0x443c0174 2 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_tpm_ch_tpm2_ch1: IOMUXC1_I2C1_SDA_TPM_CH_TPM2_CH1 { + pinmux = <0x443c0174 3 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_gpio_io_gpio1_io02: IOMUXC1_I2C2_SCL_GPIO_IO_GPIO1_IO02 { + pinmux = <0x443c0178 5 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_b_i3c1_pur_b: IOMUXC1_I2C2_SCL_I3C_PUR_B_I3C1_PUR_B { + pinmux = <0x443c0178 6 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_i3c1_pur: IOMUXC1_I2C2_SCL_I3C_PUR_I3C1_PUR { + pinmux = <0x443c0178 1 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl: IOMUXC1_I2C2_SCL_LPI2C_SCL_LPI2C2_SCL { + pinmux = <0x443c0178 0 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpuart_dcb_b_lpuart2_dcb_b: IOMUXC1_I2C2_SCL_LPUART_DCB_B_LPUART2_DCB_B { + pinmux = <0x443c0178 2 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_sai_rx_sync_sai1_rx_sync: IOMUXC1_I2C2_SCL_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x443c0178 4 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_tpm_ch_tpm2_ch2: IOMUXC1_I2C2_SCL_TPM_CH_TPM2_CH2 { + pinmux = <0x443c0178 3 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_gpio_io_gpio1_io03: IOMUXC1_I2C2_SDA_GPIO_IO_GPIO1_IO03 { + pinmux = <0x443c017c 5 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda: IOMUXC1_I2C2_SDA_LPI2C_SDA_LPI2C2_SDA { + pinmux = <0x443c017c 0 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpuart_rin_b_lpuart2_rin_b: IOMUXC1_I2C2_SDA_LPUART_RIN_B_LPUART2_RIN_B { + pinmux = <0x443c017c 2 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_sai_rx_bclk_sai1_rx_bclk: IOMUXC1_I2C2_SDA_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x443c017c 4 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_tpm_ch_tpm2_ch3: IOMUXC1_I2C2_SDA_TPM_CH_TPM2_CH3 { + pinmux = <0x443c017c 3 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_can_rx_can1_rx: IOMUXC1_PDM_BIT_STREAM0_CAN_RX_CAN1_RX { + pinmux = <0x443c0194 6 0x443c0360 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09: IOMUXC1_PDM_BIT_STREAM0_GPIO_IO_GPIO1_IO09 { + pinmux = <0x443c0194 5 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lpspi_pcs_lpspi1_pcs1: IOMUXC1_PDM_BIT_STREAM0_LPSPI_PCS_LPSPI1_PCS1 { + pinmux = <0x443c0194 2 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lptmr_alt_lptmr1_alt2: IOMUXC1_PDM_BIT_STREAM0_LPTMR_ALT_LPTMR1_ALT2 { + pinmux = <0x443c0194 4 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_mqs_right_mqs1_right: IOMUXC1_PDM_BIT_STREAM0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c0194 1 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_PDM_BIT_STREAM0_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0194 0 0x443c0438 2 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_tpm_extclk_tpm1_extclk: IOMUXC1_PDM_BIT_STREAM0_TPM_EXTCLK_TPM1_EXTCLK { + pinmux = <0x443c0194 3 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0198 6 0x443c0368 1 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10: IOMUXC1_PDM_BIT_STREAM1_GPIO_IO_GPIO1_IO10 { + pinmux = <0x443c0198 5 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lpspi_pcs_lpspi2_pcs1: IOMUXC1_PDM_BIT_STREAM1_LPSPI_PCS_LPSPI2_PCS1 { + pinmux = <0x443c0198 2 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lptmr_alt_lptmr1_alt3: IOMUXC1_PDM_BIT_STREAM1_LPTMR_ALT_LPTMR1_ALT3 { + pinmux = <0x443c0198 4 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_nmi_glue_nmi_nmi_glue_nmi: IOMUXC1_PDM_BIT_STREAM1_NMI_GLUE_NMI_NMI_GLUE_NMI { + pinmux = <0x443c0198 1 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_PDM_BIT_STREAM1_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0198 0 0x443c043c 2 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_tpm_extclk_tpm2_extclk: IOMUXC1_PDM_BIT_STREAM1_TPM_EXTCLK_TPM2_EXTCLK { + pinmux = <0x443c0198 3 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_can_tx_can1_tx: IOMUXC1_PDM_CLK_CAN_TX_CAN1_TX { + pinmux = <0x443c0190 6 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_gpio_io_gpio1_io08: IOMUXC1_PDM_CLK_GPIO_IO_GPIO1_IO08 { + pinmux = <0x443c0190 5 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_lptmr_alt_lptmr1_alt1: IOMUXC1_PDM_CLK_LPTMR_ALT_LPTMR1_ALT1 { + pinmux = <0x443c0190 4 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_mqs_left_mqs1_left: IOMUXC1_PDM_CLK_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c0190 1 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_pdm_clk_pdm_clk: IOMUXC1_PDM_CLK_PDM_CLK_PDM_CLK { + pinmux = <0x443c0190 0 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_gpio_io_gpio1_io14: IOMUXC1_SAI1_RXD0_GPIO_IO_GPIO1_IO14 { + pinmux = <0x443c01a8 5 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpspi_sout_lpspi1_sout: IOMUXC1_SAI1_RXD0_LPSPI_SOUT_LPSPI1_SOUT { + pinmux = <0x443c01a8 2 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpuart_dsr_b_lpuart2_dsr_b: IOMUXC1_SAI1_RXD0_LPUART_DSR_B_LPUART2_DSR_B { + pinmux = <0x443c01a8 3 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_mqs_right_mqs1_right: IOMUXC1_SAI1_RXD0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c01a8 4 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_mclk_sai1_mclk: IOMUXC1_SAI1_RXD0_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c01a8 1 0x443c0448 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_rx_data_sai1_rx_data00: IOMUXC1_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA00 { + pinmux = <0x443c01a8 0 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_can_rx_can1_rx: IOMUXC1_SAI1_TXC_CAN_RX_CAN1_RX { + pinmux = <0x443c01a0 4 0x443c0360 1 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_gpio_io_gpio1_io12: IOMUXC1_SAI1_TXC_GPIO_IO_GPIO1_IO12 { + pinmux = <0x443c01a0 5 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpspi_sin_lpspi1_sin: IOMUXC1_SAI1_TXC_LPSPI_SIN_LPSPI1_SIN { + pinmux = <0x443c01a0 2 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_cts_b_lpuart2_cts_b: IOMUXC1_SAI1_TXC_LPUART_CTS_B_LPUART2_CTS_B { + pinmux = <0x443c01a0 1 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_dsr_b_lpuart1_dsr_b: IOMUXC1_SAI1_TXC_LPUART_DSR_B_LPUART1_DSR_B { + pinmux = <0x443c01a0 3 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC1_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x443c01a0 0 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_can_tx_can1_tx: IOMUXC1_SAI1_TXD0_CAN_TX_CAN1_TX { + pinmux = <0x443c01a4 4 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_gpio_io_gpio1_io13: IOMUXC1_SAI1_TXD0_GPIO_IO_GPIO1_IO13 { + pinmux = <0x443c01a4 5 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpspi_sck_lpspi1_sck: IOMUXC1_SAI1_TXD0_LPSPI_SCK_LPSPI1_SCK { + pinmux = <0x443c01a4 2 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_dtr_b_lpuart1_dtr_b: IOMUXC1_SAI1_TXD0_LPUART_DTR_B_LPUART1_DTR_B { + pinmux = <0x443c01a4 3 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_rts_b_lpuart2_rts_b: IOMUXC1_SAI1_TXD0_LPUART_RTS_B_LPUART2_RTS_B { + pinmux = <0x443c01a4 1 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_sai_tx_data_sai1_tx_data00: IOMUXC1_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA00 { + pinmux = <0x443c01a4 0 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_gpio_io_gpio1_io11: IOMUXC1_SAI1_TXFS_GPIO_IO_GPIO1_IO11 { + pinmux = <0x443c019c 5 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpspi_pcs_lpspi1_pcs0: IOMUXC1_SAI1_TXFS_LPSPI_PCS_LPSPI1_PCS0 { + pinmux = <0x443c019c 2 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpuart_dtr_b_lpuart2_dtr_b: IOMUXC1_SAI1_TXFS_LPUART_DTR_B_LPUART2_DTR_B { + pinmux = <0x443c019c 3 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_mqs_left_mqs1_left: IOMUXC1_SAI1_TXFS_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c019c 4 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_data_sai1_tx_data01: IOMUXC1_SAI1_TXFS_SAI_TX_DATA_SAI1_TX_DATA01 { + pinmux = <0x443c019c 1 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC1_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x443c019c 0 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_flexio_flexio_flexio1_flexio08: IOMUXC1_SD1_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0108 4 0x443c038c 1 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_gpio_io_gpio3_io08: IOMUXC1_SD1_CLK_GPIO_IO_GPIO3_IO08 { + pinmux = <0x443c0108 5 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC1_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x443c0108 0 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_flexio_flexio_flexio1_flexio09: IOMUXC1_SD1_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c010c 4 0x443c0390 1 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_gpio_io_gpio3_io09: IOMUXC1_SD1_CMD_GPIO_IO_GPIO3_IO09 { + pinmux = <0x443c010c 5 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC1_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x443c010c 0 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_flexio_flexio_flexio1_flexio10: IOMUXC1_SD1_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0110 4 0x443c0394 1 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_gpio_io_gpio3_io10: IOMUXC1_SD1_DATA0_GPIO_IO_GPIO3_IO10 { + pinmux = <0x443c0110 5 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC1_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x443c0110 0 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_flexio_flexio_flexio1_flexio11: IOMUXC1_SD1_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c0114 4 0x443c0398 1 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_gpio_io_gpio3_io11: IOMUXC1_SD1_DATA1_GPIO_IO_GPIO3_IO11 { + pinmux = <0x443c0114 5 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC1_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x443c0114 0 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_flexio_flexio_flexio1_flexio12: IOMUXC1_SD1_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO12 { + pinmux = <0x443c0118 4 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_gpio_io_gpio3_io12: IOMUXC1_SD1_DATA2_GPIO_IO_GPIO3_IO12 { + pinmux = <0x443c0118 5 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC1_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x443c0118 0 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexio_flexio_flexio1_flexio13: IOMUXC1_SD1_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c011c 4 0x443c039c 1 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexspi_a_ss_b_flexspi1_a_ss1_b: IOMUXC1_SD1_DATA3_FLEXSPI_A_SS_B_FLEXSPI1_A_SS1_B { + pinmux = <0x443c011c 1 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_gpio_io_gpio3_io13: IOMUXC1_SD1_DATA3_GPIO_IO_GPIO3_IO13 { + pinmux = <0x443c011c 5 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC1_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x443c011c 0 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexio_flexio_flexio1_flexio14: IOMUXC1_SD1_DATA4_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0120 4 0x443c03a0 1 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexspi_a_data_flexspi1_a_data04: IOMUXC1_SD1_DATA4_FLEXSPI_A_DATA_FLEXSPI1_A_DATA04 { + pinmux = <0x443c0120 1 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_gpio_io_gpio3_io14: IOMUXC1_SD1_DATA4_GPIO_IO_GPIO3_IO14 { + pinmux = <0x443c0120 5 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC1_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x443c0120 0 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexio_flexio_flexio1_flexio15: IOMUXC1_SD1_DATA5_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c0124 4 0x443c03a4 1 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexspi_a_data_flexspi1_a_data05: IOMUXC1_SD1_DATA5_FLEXSPI_A_DATA_FLEXSPI1_A_DATA05 { + pinmux = <0x443c0124 1 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_gpio_io_gpio3_io15: IOMUXC1_SD1_DATA5_GPIO_IO_GPIO3_IO15 { + pinmux = <0x443c0124 5 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC1_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x443c0124 0 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_reset_b_usdhc1_reset_b: IOMUXC1_SD1_DATA5_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x443c0124 2 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexio_flexio_flexio1_flexio16: IOMUXC1_SD1_DATA6_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0128 4 0x443c03a8 1 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexspi_a_data_flexspi1_a_data06: IOMUXC1_SD1_DATA6_FLEXSPI_A_DATA_FLEXSPI1_A_DATA06 { + pinmux = <0x443c0128 1 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_gpio_io_gpio3_io16: IOMUXC1_SD1_DATA6_GPIO_IO_GPIO3_IO16 { + pinmux = <0x443c0128 5 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_cd_b_usdhc1_cd_b: IOMUXC1_SD1_DATA6_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x443c0128 2 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC1_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x443c0128 0 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexio_flexio_flexio1_flexio17: IOMUXC1_SD1_DATA7_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c012c 4 0x443c03ac 1 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexspi_a_data_flexspi1_a_data07: IOMUXC1_SD1_DATA7_FLEXSPI_A_DATA_FLEXSPI1_A_DATA07 { + pinmux = <0x443c012c 1 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_gpio_io_gpio3_io17: IOMUXC1_SD1_DATA7_GPIO_IO_GPIO3_IO17 { + pinmux = <0x443c012c 5 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC1_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x443c012c 0 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_wp_usdhc1_wp: IOMUXC1_SD1_DATA7_USDHC_WP_USDHC1_WP { + pinmux = <0x443c012c 2 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexio_flexio_flexio1_flexio18: IOMUXC1_SD1_STROBE_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0130 4 0x443c03b0 1 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexspi_a_dqs_flexspi1_a_dqs: IOMUXC1_SD1_STROBE_FLEXSPI_A_DQS_FLEXSPI1_A_DQS { + pinmux = <0x443c0130 1 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_gpio_io_gpio3_io18: IOMUXC1_SD1_STROBE_GPIO_IO_GPIO3_IO18 { + pinmux = <0x443c0130 5 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC1_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x443c0130 0 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC1_SD2_CD_B_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x443c0150 1 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_flexio_flexio_flexio1_flexio00: IOMUXC1_SD2_CD_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0150 4 0x443c036c 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_gpio_io_gpio3_io00: IOMUXC1_SD2_CD_B_GPIO_IO_GPIO3_IO00 { + pinmux = <0x443c0150 5 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_i3c_scl_i3c2_scl: IOMUXC1_SD2_CD_B_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0150 2 0x443c03cc 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC1_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x443c0150 0 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe0: IOMUXC1_SD2_CLK_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE0 { + pinmux = <0x443c0154 6 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC1_SD2_CLK_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x443c0154 1 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_flexio_flexio_flexio1_flexio01: IOMUXC1_SD2_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0154 4 0x443c0370 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_gpio_io_gpio3_io01: IOMUXC1_SD2_CLK_GPIO_IO_GPIO3_IO01 { + pinmux = <0x443c0154 5 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_i3c_sda_i3c2_sda: IOMUXC1_SD2_CLK_I3C_SDA_I3C2_SDA { + pinmux = <0x443c0154 2 0x443c03d0 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC1_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x443c0154 0 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe1: IOMUXC1_SD2_CMD_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE1 { + pinmux = <0x443c0158 6 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_enet1_1588_event0_in_enet1_1588_event0_in: IOMUXC1_SD2_CMD_ENET1_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x443c0158 1 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_flexio_flexio_flexio1_flexio02: IOMUXC1_SD2_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0158 4 0x443c0374 1 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_gpio_io_gpio3_io02: IOMUXC1_SD2_CMD_GPIO_IO_GPIO3_IO02 { + pinmux = <0x443c0158 5 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_b_i3c2_pur_b: IOMUXC1_SD2_CMD_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c0158 3 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_i3c2_pur: IOMUXC1_SD2_CMD_I3C_PUR_I3C2_PUR { + pinmux = <0x443c0158 2 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC1_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x443c0158 0 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_can_tx_can2_tx: IOMUXC1_SD2_DATA0_CAN_TX_CAN2_TX { + pinmux = <0x443c015c 2 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe2: IOMUXC1_SD2_DATA0_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE2 { + pinmux = <0x443c015c 6 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_enet1_1588_event0_out_enet1_1588_event0_out: IOMUXC1_SD2_DATA0_ENET1_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x443c015c 1 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_flexio_flexio_flexio1_flexio03: IOMUXC1_SD2_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c015c 4 0x443c0378 1 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_gpio_io_gpio3_io03: IOMUXC1_SD2_DATA0_GPIO_IO_GPIO3_IO03 { + pinmux = <0x443c015c 5 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC1_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x443c015c 0 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_can_rx_can2_rx: IOMUXC1_SD2_DATA1_CAN_RX_CAN2_RX { + pinmux = <0x443c0160 2 0x443c0364 3 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_enet1_1588_event1_in_enet1_1588_event1_in: IOMUXC1_SD2_DATA1_ENET1_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x443c0160 1 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_flexio_flexio_flexio1_flexio04: IOMUXC1_SD2_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0160 4 0x443c037c 1 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_gpio_io_gpio3_io04: IOMUXC1_SD2_DATA1_GPIO_IO_GPIO3_IO04 { + pinmux = <0x443c0160 5 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC1_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x443c0160 0 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_enet1_1588_event1_out_enet1_1588_event1_out: IOMUXC1_SD2_DATA2_ENET1_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x443c0164 1 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_flexio_flexio_flexio1_flexio05: IOMUXC1_SD2_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0164 4 0x443c0380 1 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_gpio_io_gpio3_io05: IOMUXC1_SD2_DATA2_GPIO_IO_GPIO3_IO05 { + pinmux = <0x443c0164 5 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_mqs_right_mqs2_right: IOMUXC1_SD2_DATA2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0164 2 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC1_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x443c0164 0 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_flexio_flexio_flexio1_flexio06: IOMUXC1_SD2_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0168 4 0x443c0384 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_gpio_io_gpio3_io06: IOMUXC1_SD2_DATA3_GPIO_IO_GPIO3_IO06 { + pinmux = <0x443c0168 5 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_lptmr_alt_lptmr2_alt1: IOMUXC1_SD2_DATA3_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c0168 1 0x443c0408 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_mqs_left_mqs2_left: IOMUXC1_SD2_DATA3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0168 2 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC1_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x443c0168 0 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_ccmsrcgpcmix_system_reset_ccmsrcgpcmix_system_reset: IOMUXC1_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET_CCMSRCGPCMIX_SYSTEM_RESET { + pinmux = <0x443c016c 6 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_flexio_flexio_flexio1_flexio07: IOMUXC1_SD2_RESET_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c016c 4 0x443c0388 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_gpio_io_gpio3_io07: IOMUXC1_SD2_RESET_B_GPIO_IO_GPIO3_IO07 { + pinmux = <0x443c016c 5 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_lptmr_alt_lptmr2_alt2: IOMUXC1_SD2_RESET_B_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c016c 1 0x443c040c 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC1_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x443c016c 0 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0134 6 0x443c0368 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_flexio_flexio_flexio1_flexio19: IOMUXC1_SD2_VSELECT_FLEXIO_FLEXIO_FLEXIO1_FLEXIO19 { + pinmux = <0x443c0134 4 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_gpio_io_gpio3_io19: IOMUXC1_SD2_VSELECT_GPIO_IO_GPIO3_IO19 { + pinmux = <0x443c0134 5 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_lptmr_alt_lptmr2_alt3: IOMUXC1_SD2_VSELECT_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c0134 2 0x443c0410 1 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect: IOMUXC1_SD2_VSELECT_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x443c0134 0 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_wp_usdhc2_wp: IOMUXC1_SD2_VSELECT_USDHC_WP_USDHC2_WP { + pinmux = <0x443c0134 1 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexio_flexio_flexio1_flexio20: IOMUXC1_SD3_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0138 4 0x443c03b4 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexspi_a_sclk_flexspi1_a_sclk: IOMUXC1_SD3_CLK_FLEXSPI_A_SCLK_FLEXSPI1_A_SCLK { + pinmux = <0x443c0138 1 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_gpio_io_gpio3_io20: IOMUXC1_SD3_CLK_GPIO_IO_GPIO3_IO20 { + pinmux = <0x443c0138 5 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_usdhc_clk_usdhc3_clk: IOMUXC1_SD3_CLK_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0138 0 0x443c0458 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexio_flexio_flexio1_flexio21: IOMUXC1_SD3_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO21 { + pinmux = <0x443c013c 4 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexspi_a_ss_b_flexspi1_a_ss0_b: IOMUXC1_SD3_CMD_FLEXSPI_A_SS_B_FLEXSPI1_A_SS0_B { + pinmux = <0x443c013c 1 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_gpio_io_gpio3_io21: IOMUXC1_SD3_CMD_GPIO_IO_GPIO3_IO21 { + pinmux = <0x443c013c 5 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_usdhc_cmd_usdhc3_cmd: IOMUXC1_SD3_CMD_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c013c 0 0x443c045c 1 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexio_flexio_flexio1_flexio22: IOMUXC1_SD3_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0140 4 0x443c03b8 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexspi_a_data_flexspi1_a_data00: IOMUXC1_SD3_DATA0_FLEXSPI_A_DATA_FLEXSPI1_A_DATA00 { + pinmux = <0x443c0140 1 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_gpio_io_gpio3_io22: IOMUXC1_SD3_DATA0_GPIO_IO_GPIO3_IO22 { + pinmux = <0x443c0140 5 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_usdhc_data_usdhc3_data0: IOMUXC1_SD3_DATA0_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0140 0 0x443c0460 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexio_flexio_flexio1_flexio23: IOMUXC1_SD3_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c0144 4 0x443c03bc 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexspi_a_data_flexspi1_a_data01: IOMUXC1_SD3_DATA1_FLEXSPI_A_DATA_FLEXSPI1_A_DATA01 { + pinmux = <0x443c0144 1 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_gpio_io_gpio3_io23: IOMUXC1_SD3_DATA1_GPIO_IO_GPIO3_IO23 { + pinmux = <0x443c0144 5 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_usdhc_data_usdhc3_data1: IOMUXC1_SD3_DATA1_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0144 0 0x443c0464 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexio_flexio_flexio1_flexio24: IOMUXC1_SD3_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0148 4 0x443c03c0 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexspi_a_data_flexspi1_a_data02: IOMUXC1_SD3_DATA2_FLEXSPI_A_DATA_FLEXSPI1_A_DATA02 { + pinmux = <0x443c0148 1 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_gpio_io_gpio3_io24: IOMUXC1_SD3_DATA2_GPIO_IO_GPIO3_IO24 { + pinmux = <0x443c0148 5 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_usdhc_data_usdhc3_data2: IOMUXC1_SD3_DATA2_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0148 0 0x443c0468 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexio_flexio_flexio1_flexio25: IOMUXC1_SD3_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c014c 4 0x443c03c4 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexspi_a_data_flexspi1_a_data03: IOMUXC1_SD3_DATA3_FLEXSPI_A_DATA_FLEXSPI1_A_DATA03 { + pinmux = <0x443c014c 1 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_gpio_io_gpio3_io25: IOMUXC1_SD3_DATA3_GPIO_IO_GPIO3_IO25 { + pinmux = <0x443c014c 5 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_usdhc_data_usdhc3_data3: IOMUXC1_SD3_DATA3_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c014c 0 0x443c046c 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_gpio_io_gpio1_io04: IOMUXC1_UART1_RXD_GPIO_IO_GPIO1_IO04 { + pinmux = <0x443c0180 5 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpspi_sin_lpspi2_sin: IOMUXC1_UART1_RXD_LPSPI_SIN_LPSPI2_SIN { + pinmux = <0x443c0180 2 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx: IOMUXC1_UART1_RXD_LPUART_RX_LPUART1_RX { + pinmux = <0x443c0180 0 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_s400_uart_rx_s400_uart_rx: IOMUXC1_UART1_RXD_S400_UART_RX_S400_UART_RX { + pinmux = <0x443c0180 1 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_tpm_ch_tpm1_ch0: IOMUXC1_UART1_RXD_TPM_CH_TPM1_CH0 { + pinmux = <0x443c0180 3 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_gpio_io_gpio1_io05: IOMUXC1_UART1_TXD_GPIO_IO_GPIO1_IO05 { + pinmux = <0x443c0184 5 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpspi_pcs_lpspi2_pcs0: IOMUXC1_UART1_TXD_LPSPI_PCS_LPSPI2_PCS0 { + pinmux = <0x443c0184 2 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx: IOMUXC1_UART1_TXD_LPUART_TX_LPUART1_TX { + pinmux = <0x443c0184 0 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_s400_uart_tx_s400_uart_tx: IOMUXC1_UART1_TXD_S400_UART_TX_S400_UART_TX { + pinmux = <0x443c0184 1 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_tpm_ch_tpm1_ch1: IOMUXC1_UART1_TXD_TPM_CH_TPM1_CH1 { + pinmux = <0x443c0184 3 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_gpio_io_gpio1_io06: IOMUXC1_UART2_RXD_GPIO_IO_GPIO1_IO06 { + pinmux = <0x443c0188 5 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpspi_sout_lpspi2_sout: IOMUXC1_UART2_RXD_LPSPI_SOUT_LPSPI2_SOUT { + pinmux = <0x443c0188 2 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_cts_b_lpuart1_cts_b: IOMUXC1_UART2_RXD_LPUART_CTS_B_LPUART1_CTS_B { + pinmux = <0x443c0188 1 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx: IOMUXC1_UART2_RXD_LPUART_RX_LPUART2_RX { + pinmux = <0x443c0188 0 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_sai_mclk_sai1_mclk: IOMUXC1_UART2_RXD_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c0188 4 0x443c0448 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_tpm_ch_tpm1_ch2: IOMUXC1_UART2_RXD_TPM_CH_TPM1_CH2 { + pinmux = <0x443c0188 3 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_gpio_io_gpio1_io07: IOMUXC1_UART2_TXD_GPIO_IO_GPIO1_IO07 { + pinmux = <0x443c018c 5 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpspi_sck_lpspi2_sck: IOMUXC1_UART2_TXD_LPSPI_SCK_LPSPI2_SCK { + pinmux = <0x443c018c 2 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_rts_b_lpuart1_rts_b: IOMUXC1_UART2_TXD_LPUART_RTS_B_LPUART1_RTS_B { + pinmux = <0x443c018c 1 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx: IOMUXC1_UART2_TXD_LPUART_TX_LPUART2_TX { + pinmux = <0x443c018c 0 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_tpm_ch_tpm1_ch3: IOMUXC1_UART2_TXD_TPM_CH_TPM1_CH3 { + pinmux = <0x443c018c 3 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_gpio_io_gpio1_io15: IOMUXC1_WDOG_ANY_GPIO_IO_GPIO1_IO15 { + pinmux = <0x443c01ac 5 0x0 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_wdog_wdog_any_wdog1_wdog_any: IOMUXC1_WDOG_ANY_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x443c01ac 0 0x0 0 0x443c035c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx9352dvvxm-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx9352dvvxm-pinctrl.dtsi new file mode 100644 index 000000000..e633af737 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx9352dvvxm-pinctrl.dtsi @@ -0,0 +1,1831 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX9352DVVXM + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc1_ccm_clko1_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko1: IOMUXC1_CCM_CLKO1_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO1 { + pinmux = <0x443c0088 0 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_flexio_flexio_flexio1_flexio26: IOMUXC1_CCM_CLKO1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO26 { + pinmux = <0x443c0088 4 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_gpio_io_gpio3_io26: IOMUXC1_CCM_CLKO1_GPIO_IO_GPIO3_IO26 { + pinmux = <0x443c0088 5 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko2: IOMUXC1_CCM_CLKO2_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO2 { + pinmux = <0x443c008c 0 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_flexio_flexio_flexio1_flexio27: IOMUXC1_CCM_CLKO2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c008c 4 0x443c03c8 1 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_gpio_io_gpio3_io27: IOMUXC1_CCM_CLKO2_GPIO_IO_GPIO3_IO27 { + pinmux = <0x443c008c 5 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko3: IOMUXC1_CCM_CLKO3_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO3 { + pinmux = <0x443c0090 0 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_flexio_flexio_flexio2_flexio28: IOMUXC1_CCM_CLKO3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO28 { + pinmux = <0x443c0090 4 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_gpio_io_gpio4_io28: IOMUXC1_CCM_CLKO3_GPIO_IO_GPIO4_IO28 { + pinmux = <0x443c0090 5 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko4: IOMUXC1_CCM_CLKO4_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO4 { + pinmux = <0x443c0094 0 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_flexio_flexio_flexio2_flexio29: IOMUXC1_CCM_CLKO4_FLEXIO_FLEXIO_FLEXIO2_FLEXIO29 { + pinmux = <0x443c0094 4 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_gpio_io_gpio4_io29: IOMUXC1_CCM_CLKO4_GPIO_IO_GPIO4_IO29 { + pinmux = <0x443c0094 5 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_flexio_flexio_flexio1_flexio30: IOMUXC1_DAP_TCLK_SWCLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO30 { + pinmux = <0x443c0008 4 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30: IOMUXC1_DAP_TCLK_SWCLK_GPIO_IO_GPIO3_IO30 { + pinmux = <0x443c0008 5 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_jtag_mux_tck_jtag_mux_tck: IOMUXC1_DAP_TCLK_SWCLK_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0008 0 0x443c03d4 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_DAP_TCLK_SWCLK_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0008 6 0x443c042c 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_can_tx_can2_tx: IOMUXC1_DAP_TDI_CAN_TX_CAN2_TX { + pinmux = <0x443c0000 3 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_flexio_flexio_flexio2_flexio30: IOMUXC1_DAP_TDI_FLEXIO_FLEXIO_FLEXIO2_FLEXIO30 { + pinmux = <0x443c0000 4 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_gpio_io_gpio3_io28: IOMUXC1_DAP_TDI_GPIO_IO_GPIO3_IO28 { + pinmux = <0x443c0000 5 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_DAP_TDI_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0000 0 0x443c03d8 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_lpuart_rx_lpuart5_rx: IOMUXC1_DAP_TDI_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0000 6 0x443c0430 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_mqs_left_mqs2_left: IOMUXC1_DAP_TDI_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0000 1 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_can_rx_can2_rx: IOMUXC1_DAP_TDO_TRACESWO_CAN_RX_CAN2_RX { + pinmux = <0x443c000c 3 0x443c0364 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_flexio_flexio_flexio1_flexio31: IOMUXC1_DAP_TDO_TRACESWO_FLEXIO_FLEXIO_FLEXIO1_FLEXIO31 { + pinmux = <0x443c000c 4 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31: IOMUXC1_DAP_TDO_TRACESWO_GPIO_IO_GPIO3_IO31 { + pinmux = <0x443c000c 5 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_DAP_TDO_TRACESWO_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c000c 0 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_lpuart_tx_lpuart5_tx: IOMUXC1_DAP_TDO_TRACESWO_LPUART_TX_LPUART5_TX { + pinmux = <0x443c000c 6 0x443c0434 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_mqs_right_mqs2_right: IOMUXC1_DAP_TDO_TRACESWO_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c000c 1 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_flexio_flexio_flexio2_flexio31: IOMUXC1_DAP_TMS_SWDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO31 { + pinmux = <0x443c0004 4 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29: IOMUXC1_DAP_TMS_SWDIO_GPIO_IO_GPIO3_IO29 { + pinmux = <0x443c0004 5 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_jtag_mux_tms_jtag_mux_tms: IOMUXC1_DAP_TMS_SWDIO_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c0004 0 0x443c03dc 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_DAP_TMS_SWDIO_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c0004 6 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC1_ENET1_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x443c0098 0 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_flexio_flexio_flexio2_flexio00: IOMUXC1_ENET1_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO00 { + pinmux = <0x443c0098 4 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_gpio_io_gpio4_io00: IOMUXC1_ENET1_MDC_GPIO_IO_GPIO4_IO00 { + pinmux = <0x443c0098 5 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_hsiomix_otg_id_hsiomix_otg_id1: IOMUXC1_ENET1_MDC_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID1 { + pinmux = <0x443c0098 3 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_i3c_scl_i3c2_scl: IOMUXC1_ENET1_MDC_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0098 2 0x443c03cc 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_lpuart_dcb_b_lpuart3_dcb_b: IOMUXC1_ENET1_MDC_LPUART_DCB_B_LPUART3_DCB_B { + pinmux = <0x443c0098 1 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC1_ENET1_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x443c009c 0 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_flexio_flexio_flexio2_flexio01: IOMUXC1_ENET1_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO01 { + pinmux = <0x443c009c 4 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_gpio_io_gpio4_io01: IOMUXC1_ENET1_MDIO_GPIO_IO_GPIO4_IO01 { + pinmux = <0x443c009c 5 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_hsiomix_otg_pwr_hsiomix_otg_pwr1: IOMUXC1_ENET1_MDIO_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR1 { + pinmux = <0x443c009c 3 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_i3c_sda_i3c2_sda: IOMUXC1_ENET1_MDIO_I3C_SDA_I3C2_SDA { + pinmux = <0x443c009c 2 0x443c03d0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_lpuart_rin_b_lpuart3_rin_b: IOMUXC1_ENET1_MDIO_LPUART_RIN_B_LPUART3_RIN_B { + pinmux = <0x443c009c 1 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC1_ENET1_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x443c00c0 0 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_flexio_flexio_flexio2_flexio10: IOMUXC1_ENET1_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO10 { + pinmux = <0x443c00c0 4 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_gpio_io_gpio4_io10: IOMUXC1_ENET1_RD0_GPIO_IO_GPIO4_IO10 { + pinmux = <0x443c00c0 5 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_lpuart_rx_lpuart3_rx: IOMUXC1_ENET1_RD0_LPUART_RX_LPUART3_RX { + pinmux = <0x443c00c0 1 0x443c0418 1 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC1_ENET1_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x443c00c4 0 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_flexio_flexio_flexio2_flexio11: IOMUXC1_ENET1_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO11 { + pinmux = <0x443c00c4 4 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_gpio_io_gpio4_io11: IOMUXC1_ENET1_RD1_GPIO_IO_GPIO4_IO11 { + pinmux = <0x443c00c4 5 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lptmr_alt_lptmr2_alt1: IOMUXC1_ENET1_RD1_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c00c4 3 0x443c0408 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_ENET1_RD1_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c00c4 1 0x443c0414 1 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC1_ENET1_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x443c00c8 0 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_flexio_flexio_flexio2_flexio12: IOMUXC1_ENET1_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO12 { + pinmux = <0x443c00c8 4 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_gpio_io_gpio4_io12: IOMUXC1_ENET1_RD2_GPIO_IO_GPIO4_IO12 { + pinmux = <0x443c00c8 5 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_lptmr_alt_lptmr2_alt2: IOMUXC1_ENET1_RD2_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c00c8 3 0x443c040c 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC1_ENET1_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x443c00cc 0 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_flexio_flexio_flexio2_flexio13: IOMUXC1_ENET1_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO13 { + pinmux = <0x443c00cc 4 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_gpio_io_gpio4_io13: IOMUXC1_ENET1_RD3_GPIO_IO_GPIO4_IO13 { + pinmux = <0x443c00cc 5 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_lptmr_alt_lptmr2_alt3: IOMUXC1_ENET1_RD3_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c00cc 3 0x443c0410 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_ccm_enet_qos_clock_generate_rx_clk_ccm_enet_qos_clock_generate_rx_clk: IOMUXC1_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK { + pinmux = <0x443c00bc 0 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC1_ENET1_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x443c00bc 1 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_flexio_flexio_flexio2_flexio09: IOMUXC1_ENET1_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO09 { + pinmux = <0x443c00bc 4 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_gpio_io_gpio4_io09: IOMUXC1_ENET1_RXC_GPIO_IO_GPIO4_IO09 { + pinmux = <0x443c00bc 5 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC1_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x443c00b8 0 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_flexio_flexio_flexio2_flexio08: IOMUXC1_ENET1_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO08 { + pinmux = <0x443c00b8 4 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08: IOMUXC1_ENET1_RX_CTL_GPIO_IO_GPIO4_IO08 { + pinmux = <0x443c00b8 5 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_hsiomix_otg_pwr_hsiomix_otg_pwr2: IOMUXC1_ENET1_RX_CTL_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR2 { + pinmux = <0x443c00b8 3 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_lpuart_dsr_b_lpuart3_dsr_b: IOMUXC1_ENET1_RX_CTL_LPUART_DSR_B_LPUART3_DSR_B { + pinmux = <0x443c00b8 1 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC1_ENET1_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x443c00ac 0 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_flexio_flexio_flexio2_flexio05: IOMUXC1_ENET1_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO05 { + pinmux = <0x443c00ac 4 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_gpio_io_gpio4_io05: IOMUXC1_ENET1_TD0_GPIO_IO_GPIO4_IO05 { + pinmux = <0x443c00ac 5 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_lpuart_tx_lpuart3_tx: IOMUXC1_ENET1_TD0_LPUART_TX_LPUART3_TX { + pinmux = <0x443c00ac 1 0x443c041c 1 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC1_ENET1_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x443c00a8 0 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_flexio_flexio_flexio2_flexio04: IOMUXC1_ENET1_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO04 { + pinmux = <0x443c00a8 4 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_gpio_io_gpio4_io04: IOMUXC1_ENET1_TD1_GPIO_IO_GPIO4_IO04 { + pinmux = <0x443c00a8 5 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_hsiomix_otg_oc_hsiomix_otg_oc1: IOMUXC1_ENET1_TD1_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC1 { + pinmux = <0x443c00a8 3 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_b_i3c2_pur_b: IOMUXC1_ENET1_TD1_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c00a8 6 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_i3c2_pur: IOMUXC1_ENET1_TD1_I3C_PUR_I3C2_PUR { + pinmux = <0x443c00a8 2 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_ENET1_TD1_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c00a8 1 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_can_rx_can2_rx: IOMUXC1_ENET1_TD2_CAN_RX_CAN2_RX { + pinmux = <0x443c00a4 2 0x443c0364 2 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_ccm_enet_qos_clock_generate_ref_clk_ccm_enet_qos_clock_generate_ref_clk: IOMUXC1_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK { + pinmux = <0x443c00a4 1 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC1_ENET1_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x443c00a4 0 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_flexio_flexio_flexio2_flexio03: IOMUXC1_ENET1_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO03 { + pinmux = <0x443c00a4 4 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_gpio_io_gpio4_io03: IOMUXC1_ENET1_TD2_GPIO_IO_GPIO4_IO03 { + pinmux = <0x443c00a4 5 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_hsiomix_otg_oc_hsiomix_otg_oc2: IOMUXC1_ENET1_TD2_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC2 { + pinmux = <0x443c00a4 3 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_can_tx_can2_tx: IOMUXC1_ENET1_TD3_CAN_TX_CAN2_TX { + pinmux = <0x443c00a0 2 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC1_ENET1_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x443c00a0 0 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_flexio_flexio_flexio2_flexio02: IOMUXC1_ENET1_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO02 { + pinmux = <0x443c00a0 4 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_gpio_io_gpio4_io02: IOMUXC1_ENET1_TD3_GPIO_IO_GPIO4_IO02 { + pinmux = <0x443c00a0 5 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_hsiomix_otg_id_hsiomix_otg_id2: IOMUXC1_ENET1_TD3_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID2 { + pinmux = <0x443c00a0 3 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_ccm_enet_qos_clock_generate_tx_clk_ccm_enet_qos_clock_generate_tx_clk: IOMUXC1_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK { + pinmux = <0x443c00b4 0 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC1_ENET1_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x443c00b4 1 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_flexio_flexio_flexio2_flexio07: IOMUXC1_ENET1_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO07 { + pinmux = <0x443c00b4 4 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_gpio_io_gpio4_io07: IOMUXC1_ENET1_TXC_GPIO_IO_GPIO4_IO07 { + pinmux = <0x443c00b4 5 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC1_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x443c00b0 0 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_flexio_flexio_flexio2_flexio06: IOMUXC1_ENET1_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO06 { + pinmux = <0x443c00b0 4 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06: IOMUXC1_ENET1_TX_CTL_GPIO_IO_GPIO4_IO06 { + pinmux = <0x443c00b0 5 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_lpuart_dtr_b_lpuart3_dtr_b: IOMUXC1_ENET1_TX_CTL_LPUART_DTR_B_LPUART3_DTR_B { + pinmux = <0x443c00b0 1 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_enet_mdc_enet1_mdc: IOMUXC1_ENET2_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x443c00d0 0 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_flexio_flexio_flexio2_flexio14: IOMUXC1_ENET2_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO14 { + pinmux = <0x443c00d0 4 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_gpio_io_gpio4_io14: IOMUXC1_ENET2_MDC_GPIO_IO_GPIO4_IO14 { + pinmux = <0x443c00d0 5 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_lpuart_dcb_b_lpuart4_dcb_b: IOMUXC1_ENET2_MDC_LPUART_DCB_B_LPUART4_DCB_B { + pinmux = <0x443c00d0 1 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_sai_rx_sync_sai2_rx_sync: IOMUXC1_ENET2_MDC_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x443c00d0 2 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_enet_mdio_enet1_mdio: IOMUXC1_ENET2_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x443c00d4 0 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_flexio_flexio_flexio2_flexio15: IOMUXC1_ENET2_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO15 { + pinmux = <0x443c00d4 4 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_gpio_io_gpio4_io15: IOMUXC1_ENET2_MDIO_GPIO_IO_GPIO4_IO15 { + pinmux = <0x443c00d4 5 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_lpuart_rin_b_lpuart4_rin_b: IOMUXC1_ENET2_MDIO_LPUART_RIN_B_LPUART4_RIN_B { + pinmux = <0x443c00d4 1 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_sai_rx_bclk_sai2_rx_bclk: IOMUXC1_ENET2_MDIO_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x443c00d4 2 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC1_ENET2_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x443c00f8 0 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_flexio_flexio_flexio2_flexio24: IOMUXC1_ENET2_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO24 { + pinmux = <0x443c00f8 4 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_gpio_io_gpio4_io24: IOMUXC1_ENET2_RD0_GPIO_IO_GPIO4_IO24 { + pinmux = <0x443c00f8 5 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_lpuart_rx_lpuart4_rx: IOMUXC1_ENET2_RD0_LPUART_RX_LPUART4_RX { + pinmux = <0x443c00f8 1 0x443c0424 1 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_sai_tx_data_sai2_tx_data02: IOMUXC1_ENET2_RD0_SAI_TX_DATA_SAI2_TX_DATA02 { + pinmux = <0x443c00f8 2 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC1_ENET2_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x443c00fc 0 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_flexio_flexio_flexio2_flexio25: IOMUXC1_ENET2_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO25 { + pinmux = <0x443c00fc 4 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_gpio_io_gpio4_io25: IOMUXC1_ENET2_RD1_GPIO_IO_GPIO4_IO25 { + pinmux = <0x443c00fc 5 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_sai_tx_data_sai2_tx_data03: IOMUXC1_ENET2_RD1_SAI_TX_DATA_SAI2_TX_DATA03 { + pinmux = <0x443c00fc 2 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_spdif_in_spdif_in: IOMUXC1_ENET2_RD1_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c00fc 1 0x443c0454 1 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC1_ENET2_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x443c0100 0 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_flexio_flexio_flexio2_flexio26: IOMUXC1_ENET2_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO26 { + pinmux = <0x443c0100 4 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_gpio_io_gpio4_io26: IOMUXC1_ENET2_RD2_GPIO_IO_GPIO4_IO26 { + pinmux = <0x443c0100 5 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_ENET2_RD2_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0100 1 0x443c0420 1 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_mqs_right_mqs2_right: IOMUXC1_ENET2_RD2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0100 3 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_sai_mclk_sai2_mclk: IOMUXC1_ENET2_RD2_SAI_MCLK_SAI2_MCLK { + pinmux = <0x443c0100 2 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC1_ENET2_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x443c0104 0 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_flexio_flexio_flexio2_flexio27: IOMUXC1_ENET2_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO27 { + pinmux = <0x443c0104 4 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_gpio_io_gpio4_io27: IOMUXC1_ENET2_RD3_GPIO_IO_GPIO4_IO27 { + pinmux = <0x443c0104 5 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_mqs_left_mqs2_left: IOMUXC1_ENET2_RD3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0104 3 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_in_spdif_in: IOMUXC1_ENET2_RD3_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0104 2 0x443c0454 2 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_out_spdif_out: IOMUXC1_ENET2_RD3_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c0104 1 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC1_ENET2_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x443c00f4 0 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rx_er_enet1_rx_er: IOMUXC1_ENET2_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x443c00f4 1 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_flexio_flexio_flexio2_flexio23: IOMUXC1_ENET2_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO23 { + pinmux = <0x443c00f4 4 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_gpio_io_gpio4_io23: IOMUXC1_ENET2_RXC_GPIO_IO_GPIO4_IO23 { + pinmux = <0x443c00f4 5 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_sai_tx_data_sai2_tx_data01: IOMUXC1_ENET2_RXC_SAI_TX_DATA_SAI2_TX_DATA01 { + pinmux = <0x443c00f4 2 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC1_ENET2_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x443c00f0 0 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_flexio_flexio_flexio2_flexio22: IOMUXC1_ENET2_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO22 { + pinmux = <0x443c00f0 4 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22: IOMUXC1_ENET2_RX_CTL_GPIO_IO_GPIO4_IO22 { + pinmux = <0x443c00f0 5 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_lpuart_dsr_b_lpuart4_dsr_b: IOMUXC1_ENET2_RX_CTL_LPUART_DSR_B_LPUART4_DSR_B { + pinmux = <0x443c00f0 1 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_sai_tx_data_sai2_tx_data00: IOMUXC1_ENET2_RX_CTL_SAI_TX_DATA_SAI2_TX_DATA00 { + pinmux = <0x443c00f0 2 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC1_ENET2_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x443c00e4 0 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_flexio_flexio_flexio2_flexio19: IOMUXC1_ENET2_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO19 { + pinmux = <0x443c00e4 4 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_gpio_io_gpio4_io19: IOMUXC1_ENET2_TD0_GPIO_IO_GPIO4_IO19 { + pinmux = <0x443c00e4 5 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_lpuart_tx_lpuart4_tx: IOMUXC1_ENET2_TD0_LPUART_TX_LPUART4_TX { + pinmux = <0x443c00e4 1 0x443c0428 1 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_sai_rx_data_sai2_rx_data03: IOMUXC1_ENET2_TD0_SAI_RX_DATA_SAI2_RX_DATA03 { + pinmux = <0x443c00e4 2 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC1_ENET2_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x443c00e0 0 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_flexio_flexio_flexio2_flexio18: IOMUXC1_ENET2_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO18 { + pinmux = <0x443c00e0 4 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_gpio_io_gpio4_io18: IOMUXC1_ENET2_TD1_GPIO_IO_GPIO4_IO18 { + pinmux = <0x443c00e0 5 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_ENET2_TD1_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c00e0 1 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_sai_rx_data_sai2_rx_data02: IOMUXC1_ENET2_TD1_SAI_RX_DATA_SAI2_RX_DATA02 { + pinmux = <0x443c00e0 2 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC1_ENET2_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x443c00dc 0 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_tx_clk_enet1_tx_clk: IOMUXC1_ENET2_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x443c00dc 1 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_flexio_flexio_flexio2_flexio17: IOMUXC1_ENET2_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO17 { + pinmux = <0x443c00dc 4 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_gpio_io_gpio4_io17: IOMUXC1_ENET2_TD2_GPIO_IO_GPIO4_IO17 { + pinmux = <0x443c00dc 5 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_sai_rx_data_sai2_rx_data01: IOMUXC1_ENET2_TD2_SAI_RX_DATA_SAI2_RX_DATA01 { + pinmux = <0x443c00dc 2 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC1_ENET2_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x443c00d8 0 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_flexio_flexio_flexio2_flexio16: IOMUXC1_ENET2_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO16 { + pinmux = <0x443c00d8 4 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_gpio_io_gpio4_io16: IOMUXC1_ENET2_TD3_GPIO_IO_GPIO4_IO16 { + pinmux = <0x443c00d8 5 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_sai_rx_data_sai2_rx_data00: IOMUXC1_ENET2_TD3_SAI_RX_DATA_SAI2_RX_DATA00 { + pinmux = <0x443c00d8 2 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC1_ENET2_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x443c00ec 0 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_tx_er_enet1_tx_er: IOMUXC1_ENET2_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x443c00ec 1 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_flexio_flexio_flexio2_flexio21: IOMUXC1_ENET2_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO21 { + pinmux = <0x443c00ec 4 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_gpio_io_gpio4_io21: IOMUXC1_ENET2_TXC_GPIO_IO_GPIO4_IO21 { + pinmux = <0x443c00ec 5 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC1_ENET2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x443c00ec 2 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC1_ENET2_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x443c00e8 0 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_flexio_flexio_flexio2_flexio20: IOMUXC1_ENET2_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO20 { + pinmux = <0x443c00e8 4 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20: IOMUXC1_ENET2_TX_CTL_GPIO_IO_GPIO4_IO20 { + pinmux = <0x443c00e8 5 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_lpuart_dtr_b_lpuart4_dtr_b: IOMUXC1_ENET2_TX_CTL_LPUART_DTR_B_LPUART4_DTR_B { + pinmux = <0x443c00e8 1 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_sai_tx_sync_sai2_tx_sync: IOMUXC1_ENET2_TX_CTL_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x443c00e8 2 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_flexio_flexio_flexio1_flexio00: IOMUXC1_GPIO_IO00_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0010 7 0x443c036c 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_gpio_io_gpio2_io00: IOMUXC1_GPIO_IO00_GPIO_IO_GPIO2_IO00 { + pinmux = <0x443c0010 0 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0010 1 0x443c03e4 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0010 6 0x443c03ec 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpspi_pcs_lpspi6_pcs0: IOMUXC1_GPIO_IO00_LPSPI_PCS_LPSPI6_PCS0 { + pinmux = <0x443c0010 4 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpuart_tx_lpuart5_tx: IOMUXC1_GPIO_IO00_LPUART_TX_LPUART5_TX { + pinmux = <0x443c0010 5 0x443c0434 1 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_cam_clk_mediamix_cam_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_CAM_CLK_MEDIAMIX_CAM_CLK { + pinmux = <0x443c0010 2 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_disp_clk_mediamix_disp_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_DISP_CLK_MEDIAMIX_DISP_CLK { + pinmux = <0x443c0010 3 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_flexio_flexio_flexio1_flexio01: IOMUXC1_GPIO_IO01_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0014 7 0x443c0370 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_gpio_io_gpio2_io01: IOMUXC1_GPIO_IO01_GPIO_IO_GPIO2_IO01 { + pinmux = <0x443c0014 0 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0014 1 0x443c03e0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c0014 6 0x443c03e8 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpspi_sin_lpspi6_sin: IOMUXC1_GPIO_IO01_LPSPI_SIN_LPSPI6_SIN { + pinmux = <0x443c0014 4 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpuart_rx_lpuart5_rx: IOMUXC1_GPIO_IO01_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0014 5 0x443c0430 1 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_cam_data_mediamix_cam_data00: IOMUXC1_GPIO_IO01_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA00 { + pinmux = <0x443c0014 2 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_disp_de_mediamix_disp_de: IOMUXC1_GPIO_IO01_MEDIAMIX_DISP_DE_MEDIAMIX_DISP_DE { + pinmux = <0x443c0014 3 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_flexio_flexio_flexio1_flexio02: IOMUXC1_GPIO_IO02_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0018 7 0x443c0374 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_gpio_io_gpio2_io02: IOMUXC1_GPIO_IO02_GPIO_IO_GPIO2_IO02 { + pinmux = <0x443c0018 0 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C4_SDA { + pinmux = <0x443c0018 1 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0018 6 0x443c03f4 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpspi_sout_lpspi6_sout: IOMUXC1_GPIO_IO02_LPSPI_SOUT_LPSPI6_SOUT { + pinmux = <0x443c0018 4 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_GPIO_IO02_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0018 5 0x443c042c 1 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_cam_vsync_mediamix_cam_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_CAM_VSYNC_MEDIAMIX_CAM_VSYNC { + pinmux = <0x443c0018 2 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_disp_vsync_mediamix_disp_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_DISP_VSYNC_MEDIAMIX_DISP_VSYNC { + pinmux = <0x443c0018 3 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_flexio_flexio_flexio1_flexio03: IOMUXC1_GPIO_IO03_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c001c 7 0x443c0378 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_gpio_io_gpio2_io03: IOMUXC1_GPIO_IO03_GPIO_IO_GPIO2_IO03 { + pinmux = <0x443c001c 0 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C4_SCL { + pinmux = <0x443c001c 1 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c001c 6 0x443c03f0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpspi_sck_lpspi6_sck: IOMUXC1_GPIO_IO03_LPSPI_SCK_LPSPI6_SCK { + pinmux = <0x443c001c 4 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_GPIO_IO03_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c001c 5 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_cam_hsync_mediamix_cam_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_CAM_HSYNC_MEDIAMIX_CAM_HSYNC { + pinmux = <0x443c001c 2 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_disp_hsync_mediamix_disp_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_DISP_HSYNC_MEDIAMIX_DISP_HSYNC { + pinmux = <0x443c001c 3 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_flexio_flexio_flexio1_flexio04: IOMUXC1_GPIO_IO04_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0020 7 0x443c037c 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_gpio_io_gpio2_io04: IOMUXC1_GPIO_IO04_GPIO_IO_GPIO2_IO04 { + pinmux = <0x443c0020 0 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO04_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0020 6 0x443c03f4 1 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpspi_pcs_lpspi7_pcs0: IOMUXC1_GPIO_IO04_LPSPI_PCS_LPSPI7_PCS0 { + pinmux = <0x443c0020 4 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpuart_tx_lpuart6_tx: IOMUXC1_GPIO_IO04_LPUART_TX_LPUART6_TX { + pinmux = <0x443c0020 5 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_mediamix_disp_data_mediamix_disp_data00: IOMUXC1_GPIO_IO04_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA00 { + pinmux = <0x443c0020 3 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO04_PDM_CLK_PDM_CLK { + pinmux = <0x443c0020 2 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_tpm_ch_tpm3_ch0: IOMUXC1_GPIO_IO04_TPM_CH_TPM3_CH0 { + pinmux = <0x443c0020 1 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_flexio_flexio_flexio1_flexio05: IOMUXC1_GPIO_IO05_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0024 7 0x443c0380 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_gpio_io_gpio2_io05: IOMUXC1_GPIO_IO05_GPIO_IO_GPIO2_IO05 { + pinmux = <0x443c0024 0 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO05_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c0024 6 0x443c03f0 1 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpspi_sin_lpspi7_sin: IOMUXC1_GPIO_IO05_LPSPI_SIN_LPSPI7_SIN { + pinmux = <0x443c0024 4 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpuart_rx_lpuart6_rx: IOMUXC1_GPIO_IO05_LPUART_RX_LPUART6_RX { + pinmux = <0x443c0024 5 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_mediamix_disp_data_mediamix_disp_data01: IOMUXC1_GPIO_IO05_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA01 { + pinmux = <0x443c0024 3 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO05_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0024 2 0x443c0438 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_tpm_ch_tpm4_ch0: IOMUXC1_GPIO_IO05_TPM_CH_TPM4_CH0 { + pinmux = <0x443c0024 1 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_flexio_flexio_flexio1_flexio06: IOMUXC1_GPIO_IO06_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0028 7 0x443c0384 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_gpio_io_gpio2_io06: IOMUXC1_GPIO_IO06_GPIO_IO_GPIO2_IO06 { + pinmux = <0x443c0028 0 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO06_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0028 6 0x443c03fc 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpspi_sout_lpspi7_sout: IOMUXC1_GPIO_IO06_LPSPI_SOUT_LPSPI7_SOUT { + pinmux = <0x443c0028 4 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpuart_cts_b_lpuart6_cts_b: IOMUXC1_GPIO_IO06_LPUART_CTS_B_LPUART6_CTS_B { + pinmux = <0x443c0028 5 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_mediamix_disp_data_mediamix_disp_data02: IOMUXC1_GPIO_IO06_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA02 { + pinmux = <0x443c0028 3 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO06_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0028 2 0x443c043c 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_tpm_ch_tpm5_ch0: IOMUXC1_GPIO_IO06_TPM_CH_TPM5_CH0 { + pinmux = <0x443c0028 1 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_flexio_flexio_flexio1_flexio07: IOMUXC1_GPIO_IO07_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c002c 7 0x443c0388 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_gpio_io_gpio2_io07: IOMUXC1_GPIO_IO07_GPIO_IO_GPIO2_IO07 { + pinmux = <0x443c002c 0 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO07_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c002c 6 0x443c03f8 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1: IOMUXC1_GPIO_IO07_LPSPI_PCS_LPSPI3_PCS1 { + pinmux = <0x443c002c 1 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_sck_lpspi7_sck: IOMUXC1_GPIO_IO07_LPSPI_SCK_LPSPI7_SCK { + pinmux = <0x443c002c 4 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpuart_rts_b_lpuart6_rts_b: IOMUXC1_GPIO_IO07_LPUART_RTS_B_LPUART6_RTS_B { + pinmux = <0x443c002c 5 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_cam_data_mediamix_cam_data01: IOMUXC1_GPIO_IO07_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA01 { + pinmux = <0x443c002c 2 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_disp_data_mediamix_disp_data03: IOMUXC1_GPIO_IO07_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA03 { + pinmux = <0x443c002c 3 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_flexio_flexio_flexio1_flexio08: IOMUXC1_GPIO_IO08_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0030 7 0x443c038c 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_gpio_io_gpio2_io08: IOMUXC1_GPIO_IO08_GPIO_IO_GPIO2_IO08 { + pinmux = <0x443c0030 0 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO08_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0030 6 0x443c03fc 1 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0: IOMUXC1_GPIO_IO08_LPSPI_PCS_LPSPI3_PCS0 { + pinmux = <0x443c0030 1 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpuart_tx_lpuart7_tx: IOMUXC1_GPIO_IO08_LPUART_TX_LPUART7_TX { + pinmux = <0x443c0030 5 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_cam_data_mediamix_cam_data02: IOMUXC1_GPIO_IO08_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA02 { + pinmux = <0x443c0030 2 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_disp_data_mediamix_disp_data04: IOMUXC1_GPIO_IO08_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA04 { + pinmux = <0x443c0030 3 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_tpm_ch_tpm6_ch0: IOMUXC1_GPIO_IO08_TPM_CH_TPM6_CH0 { + pinmux = <0x443c0030 4 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_flexio_flexio_flexio1_flexio09: IOMUXC1_GPIO_IO09_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c0034 7 0x443c0390 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_gpio_io_gpio2_io09: IOMUXC1_GPIO_IO09_GPIO_IO_GPIO2_IO09 { + pinmux = <0x443c0034 0 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO09_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c0034 6 0x443c03f8 1 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin: IOMUXC1_GPIO_IO09_LPSPI_SIN_LPSPI3_SIN { + pinmux = <0x443c0034 1 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpuart_rx_lpuart7_rx: IOMUXC1_GPIO_IO09_LPUART_RX_LPUART7_RX { + pinmux = <0x443c0034 5 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_cam_data_mediamix_cam_data03: IOMUXC1_GPIO_IO09_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA03 { + pinmux = <0x443c0034 2 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_disp_data_mediamix_disp_data05: IOMUXC1_GPIO_IO09_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA05 { + pinmux = <0x443c0034 3 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_tpm_extclk_tpm3_extclk: IOMUXC1_GPIO_IO09_TPM_EXTCLK_TPM3_EXTCLK { + pinmux = <0x443c0034 4 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_flexio_flexio_flexio1_flexio10: IOMUXC1_GPIO_IO10_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0038 7 0x443c0394 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_gpio_io_gpio2_io10: IOMUXC1_GPIO_IO10_GPIO_IO_GPIO2_IO10 { + pinmux = <0x443c0038 0 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO10_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0038 6 0x443c0404 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout: IOMUXC1_GPIO_IO10_LPSPI_SOUT_LPSPI3_SOUT { + pinmux = <0x443c0038 1 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpuart_cts_b_lpuart7_cts_b: IOMUXC1_GPIO_IO10_LPUART_CTS_B_LPUART7_CTS_B { + pinmux = <0x443c0038 5 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_cam_data_mediamix_cam_data04: IOMUXC1_GPIO_IO10_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA04 { + pinmux = <0x443c0038 2 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_disp_data_mediamix_disp_data06: IOMUXC1_GPIO_IO10_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA06 { + pinmux = <0x443c0038 3 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_tpm_extclk_tpm4_extclk: IOMUXC1_GPIO_IO10_TPM_EXTCLK_TPM4_EXTCLK { + pinmux = <0x443c0038 4 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_flexio_flexio_flexio1_flexio11: IOMUXC1_GPIO_IO11_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c003c 7 0x443c0398 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_gpio_io_gpio2_io11: IOMUXC1_GPIO_IO11_GPIO_IO_GPIO2_IO11 { + pinmux = <0x443c003c 0 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO11_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c003c 6 0x443c0400 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck: IOMUXC1_GPIO_IO11_LPSPI_SCK_LPSPI3_SCK { + pinmux = <0x443c003c 1 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpuart_rts_b_lpuart7_rts_b: IOMUXC1_GPIO_IO11_LPUART_RTS_B_LPUART7_RTS_B { + pinmux = <0x443c003c 5 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_cam_data_mediamix_cam_data05: IOMUXC1_GPIO_IO11_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA05 { + pinmux = <0x443c003c 2 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_disp_data_mediamix_disp_data07: IOMUXC1_GPIO_IO11_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA07 { + pinmux = <0x443c003c 3 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_tpm_extclk_tpm5_extclk: IOMUXC1_GPIO_IO11_TPM_EXTCLK_TPM5_EXTCLK { + pinmux = <0x443c003c 4 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_gpio_io_gpio2_io12: IOMUXC1_GPIO_IO12_GPIO_IO_GPIO2_IO12 { + pinmux = <0x443c0040 0 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO12_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0040 6 0x443c0404 1 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpspi_pcs_lpspi8_pcs0: IOMUXC1_GPIO_IO12_LPSPI_PCS_LPSPI8_PCS0 { + pinmux = <0x443c0040 4 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpuart_tx_lpuart8_tx: IOMUXC1_GPIO_IO12_LPUART_TX_LPUART8_TX { + pinmux = <0x443c0040 5 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_mediamix_disp_data_mediamix_disp_data08: IOMUXC1_GPIO_IO12_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA08 { + pinmux = <0x443c0040 3 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO12_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0040 2 0x443c0440 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO12_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c0040 7 0x443c0450 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_tpm_ch_tpm3_ch2: IOMUXC1_GPIO_IO12_TPM_CH_TPM3_CH2 { + pinmux = <0x443c0040 1 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_flexio_flexio_flexio1_flexio13: IOMUXC1_GPIO_IO13_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c0044 7 0x443c039c 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_gpio_io_gpio2_io13: IOMUXC1_GPIO_IO13_GPIO_IO_GPIO2_IO13 { + pinmux = <0x443c0044 0 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO13_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c0044 6 0x443c0400 1 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpspi_sin_lpspi8_sin: IOMUXC1_GPIO_IO13_LPSPI_SIN_LPSPI8_SIN { + pinmux = <0x443c0044 4 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpuart_rx_lpuart8_rx: IOMUXC1_GPIO_IO13_LPUART_RX_LPUART8_RX { + pinmux = <0x443c0044 5 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_mediamix_disp_data_mediamix_disp_data09: IOMUXC1_GPIO_IO13_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA09 { + pinmux = <0x443c0044 3 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO13_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c0044 2 0x443c0444 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_tpm_ch_tpm4_ch2: IOMUXC1_GPIO_IO13_TPM_CH_TPM4_CH2 { + pinmux = <0x443c0044 1 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_flexio_flexio_flexio1_flexio14: IOMUXC1_GPIO_IO14_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0048 7 0x443c03a0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_gpio_io_gpio2_io14: IOMUXC1_GPIO_IO14_GPIO_IO_GPIO2_IO14 { + pinmux = <0x443c0048 0 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpspi_sout_lpspi8_sout: IOMUXC1_GPIO_IO14_LPSPI_SOUT_LPSPI8_SOUT { + pinmux = <0x443c0048 4 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_cts_b_lpuart8_cts_b: IOMUXC1_GPIO_IO14_LPUART_CTS_B_LPUART8_CTS_B { + pinmux = <0x443c0048 5 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart3_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART3_TX { + pinmux = <0x443c0048 1 0x443c041c 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart4_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART4_TX { + pinmux = <0x443c0048 6 0x443c0428 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_cam_data_mediamix_cam_data06: IOMUXC1_GPIO_IO14_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA06 { + pinmux = <0x443c0048 2 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_disp_data_mediamix_disp_data10: IOMUXC1_GPIO_IO14_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA10 { + pinmux = <0x443c0048 3 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_flexio_flexio_flexio1_flexio15: IOMUXC1_GPIO_IO15_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c004c 7 0x443c03a4 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_gpio_io_gpio2_io15: IOMUXC1_GPIO_IO15_GPIO_IO_GPIO2_IO15 { + pinmux = <0x443c004c 0 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpspi_sck_lpspi8_sck: IOMUXC1_GPIO_IO15_LPSPI_SCK_LPSPI8_SCK { + pinmux = <0x443c004c 4 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rts_b_lpuart8_rts_b: IOMUXC1_GPIO_IO15_LPUART_RTS_B_LPUART8_RTS_B { + pinmux = <0x443c004c 5 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart3_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART3_RX { + pinmux = <0x443c004c 1 0x443c0418 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart4_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART4_RX { + pinmux = <0x443c004c 6 0x443c0424 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_cam_data_mediamix_cam_data07: IOMUXC1_GPIO_IO15_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA07 { + pinmux = <0x443c004c 2 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_disp_data_mediamix_disp_data11: IOMUXC1_GPIO_IO15_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA11 { + pinmux = <0x443c004c 3 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_flexio_flexio_flexio1_flexio16: IOMUXC1_GPIO_IO16_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0050 7 0x443c03a8 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_gpio_io_gpio2_io16: IOMUXC1_GPIO_IO16_GPIO_IO_GPIO2_IO16 { + pinmux = <0x443c0050 0 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpspi_pcs_lpspi4_pcs2: IOMUXC1_GPIO_IO16_LPSPI_PCS_LPSPI4_PCS2 { + pinmux = <0x443c0050 5 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c0050 4 0x443c0414 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0050 6 0x443c0420 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_mediamix_disp_data_mediamix_disp_data12: IOMUXC1_GPIO_IO16_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA12 { + pinmux = <0x443c0050 3 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO16_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0050 2 0x443c0440 1 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk: IOMUXC1_GPIO_IO16_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x443c0050 1 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_flexio_flexio_flexio1_flexio17: IOMUXC1_GPIO_IO17_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c0054 7 0x443c03ac 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_gpio_io_gpio2_io17: IOMUXC1_GPIO_IO17_GPIO_IO_GPIO2_IO17 { + pinmux = <0x443c0054 0 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpspi_pcs_lpspi4_pcs1: IOMUXC1_GPIO_IO17_LPSPI_PCS_LPSPI4_PCS1 { + pinmux = <0x443c0054 5 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c0054 4 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c0054 6 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_cam_data_mediamix_cam_data08: IOMUXC1_GPIO_IO17_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA08 { + pinmux = <0x443c0054 2 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_disp_data_mediamix_disp_data13: IOMUXC1_GPIO_IO17_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA13 { + pinmux = <0x443c0054 3 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_sai_mclk_sai3_mclk: IOMUXC1_GPIO_IO17_SAI_MCLK_SAI3_MCLK { + pinmux = <0x443c0054 1 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_flexio_flexio_flexio1_flexio18: IOMUXC1_GPIO_IO18_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0058 7 0x443c03b0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_gpio_io_gpio2_io18: IOMUXC1_GPIO_IO18_GPIO_IO_GPIO2_IO18 { + pinmux = <0x443c0058 0 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi4_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI4_PCS0 { + pinmux = <0x443c0058 5 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi5_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI5_PCS0 { + pinmux = <0x443c0058 4 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_cam_data_mediamix_cam_data09: IOMUXC1_GPIO_IO18_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA09 { + pinmux = <0x443c0058 2 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_disp_data_mediamix_disp_data14: IOMUXC1_GPIO_IO18_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA14 { + pinmux = <0x443c0058 3 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO18_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0058 1 0x443c044c 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_tpm_ch_tpm5_ch2: IOMUXC1_GPIO_IO18_TPM_CH_TPM5_CH2 { + pinmux = <0x443c0058 6 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_gpio_io_gpio2_io19: IOMUXC1_GPIO_IO19_GPIO_IO_GPIO2_IO19 { + pinmux = <0x443c005c 0 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi4_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI4_SIN { + pinmux = <0x443c005c 5 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi5_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI5_SIN { + pinmux = <0x443c005c 4 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_mediamix_disp_data_mediamix_disp_data15: IOMUXC1_GPIO_IO19_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA15 { + pinmux = <0x443c005c 3 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO19_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c005c 2 0x443c0444 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO19_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c005c 1 0x443c0450 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO19_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c005c 7 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_tpm_ch_tpm6_ch2: IOMUXC1_GPIO_IO19_TPM_CH_TPM6_CH2 { + pinmux = <0x443c005c 6 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_flexio_flexio_flexio1_flexio20: IOMUXC1_GPIO_IO20_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0060 7 0x443c03b4 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_gpio_io_gpio2_io20: IOMUXC1_GPIO_IO20_GPIO_IO_GPIO2_IO20 { + pinmux = <0x443c0060 0 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi4_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI4_SOUT { + pinmux = <0x443c0060 5 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi5_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI5_SOUT { + pinmux = <0x443c0060 4 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_mediamix_disp_data_mediamix_disp_data16: IOMUXC1_GPIO_IO20_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA16 { + pinmux = <0x443c0060 3 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO20_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0060 2 0x443c0438 1 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data00: IOMUXC1_GPIO_IO20_SAI_RX_DATA_SAI3_RX_DATA00 { + pinmux = <0x443c0060 1 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_tpm_ch_tpm3_ch1: IOMUXC1_GPIO_IO20_TPM_CH_TPM3_CH1 { + pinmux = <0x443c0060 6 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_gpio_io_gpio2_io21: IOMUXC1_GPIO_IO21_GPIO_IO_GPIO2_IO21 { + pinmux = <0x443c0064 0 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi4_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI4_SCK { + pinmux = <0x443c0064 5 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi5_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI5_SCK { + pinmux = <0x443c0064 4 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_mediamix_disp_data_mediamix_disp_data17: IOMUXC1_GPIO_IO21_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA17 { + pinmux = <0x443c0064 3 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO21_PDM_CLK_PDM_CLK { + pinmux = <0x443c0064 2 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO21_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0064 7 0x443c044c 1 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO21_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c0064 1 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_tpm_ch_tpm4_ch1: IOMUXC1_GPIO_IO21_TPM_CH_TPM4_CH1 { + pinmux = <0x443c0064 6 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_flexio_flexio_flexio1_flexio22: IOMUXC1_GPIO_IO22_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0068 7 0x443c03b8 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_gpio_io_gpio2_io22: IOMUXC1_GPIO_IO22_GPIO_IO_GPIO2_IO22 { + pinmux = <0x443c0068 0 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO22_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0068 6 0x443c03ec 1 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_mediamix_disp_data_mediamix_disp_data18: IOMUXC1_GPIO_IO22_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA18 { + pinmux = <0x443c0068 3 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_spdif_in_spdif_in: IOMUXC1_GPIO_IO22_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0068 2 0x443c0454 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_ch_tpm5_ch1: IOMUXC1_GPIO_IO22_TPM_CH_TPM5_CH1 { + pinmux = <0x443c0068 4 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_extclk_tpm6_extclk: IOMUXC1_GPIO_IO22_TPM_EXTCLK_TPM6_EXTCLK { + pinmux = <0x443c0068 5 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_usdhc_clk_usdhc3_clk: IOMUXC1_GPIO_IO22_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0068 1 0x443c0458 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_flexio_flexio_flexio1_flexio23: IOMUXC1_GPIO_IO23_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c006c 7 0x443c03bc 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_gpio_io_gpio2_io23: IOMUXC1_GPIO_IO23_GPIO_IO_GPIO2_IO23 { + pinmux = <0x443c006c 0 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO23_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c006c 6 0x443c03e8 1 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_mediamix_disp_data_mediamix_disp_data19: IOMUXC1_GPIO_IO23_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA19 { + pinmux = <0x443c006c 3 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_spdif_out_spdif_out: IOMUXC1_GPIO_IO23_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c006c 2 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_tpm_ch_tpm6_ch1: IOMUXC1_GPIO_IO23_TPM_CH_TPM6_CH1 { + pinmux = <0x443c006c 4 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_usdhc_cmd_usdhc3_cmd: IOMUXC1_GPIO_IO23_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c006c 1 0x443c045c 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_flexio_flexio_flexio1_flexio24: IOMUXC1_GPIO_IO24_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0070 7 0x443c03c0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_gpio_io_gpio2_io24: IOMUXC1_GPIO_IO24_GPIO_IO_GPIO2_IO24 { + pinmux = <0x443c0070 0 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_GPIO_IO24_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c0070 5 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_lpspi_pcs_lpspi6_pcs1: IOMUXC1_GPIO_IO24_LPSPI_PCS_LPSPI6_PCS1 { + pinmux = <0x443c0070 6 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_mediamix_disp_data_mediamix_disp_data20: IOMUXC1_GPIO_IO24_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA20 { + pinmux = <0x443c0070 3 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_tpm_ch_tpm3_ch3: IOMUXC1_GPIO_IO24_TPM_CH_TPM3_CH3 { + pinmux = <0x443c0070 4 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_usdhc_data_usdhc3_data0: IOMUXC1_GPIO_IO24_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0070 1 0x443c0460 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_can_tx_can2_tx: IOMUXC1_GPIO_IO25_CAN_TX_CAN2_TX { + pinmux = <0x443c0074 2 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_flexio_flexio_flexio1_flexio25: IOMUXC1_GPIO_IO25_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c0074 7 0x443c03c4 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_gpio_io_gpio2_io25: IOMUXC1_GPIO_IO25_GPIO_IO_GPIO2_IO25 { + pinmux = <0x443c0074 0 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_jtag_mux_tck_jtag_mux_tck: IOMUXC1_GPIO_IO25_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0074 5 0x443c03d4 1 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_lpspi_pcs_lpspi7_pcs1: IOMUXC1_GPIO_IO25_LPSPI_PCS_LPSPI7_PCS1 { + pinmux = <0x443c0074 6 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_mediamix_disp_data_mediamix_disp_data21: IOMUXC1_GPIO_IO25_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA21 { + pinmux = <0x443c0074 3 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_tpm_ch_tpm4_ch3: IOMUXC1_GPIO_IO25_TPM_CH_TPM4_CH3 { + pinmux = <0x443c0074 4 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_usdhc_data_usdhc3_data1: IOMUXC1_GPIO_IO25_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0074 1 0x443c0464 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_gpio_io_gpio2_io26: IOMUXC1_GPIO_IO26_GPIO_IO_GPIO2_IO26 { + pinmux = <0x443c0078 0 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_GPIO_IO26_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0078 5 0x443c03d8 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_lpspi_pcs_lpspi8_pcs1: IOMUXC1_GPIO_IO26_LPSPI_PCS_LPSPI8_PCS1 { + pinmux = <0x443c0078 6 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_mediamix_disp_data_mediamix_disp_data22: IOMUXC1_GPIO_IO26_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA22 { + pinmux = <0x443c0078 3 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO26_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0078 2 0x443c043c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync: IOMUXC1_GPIO_IO26_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x443c0078 7 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_tpm_ch_tpm5_ch3: IOMUXC1_GPIO_IO26_TPM_CH_TPM5_CH3 { + pinmux = <0x443c0078 4 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_usdhc_data_usdhc3_data2: IOMUXC1_GPIO_IO26_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0078 1 0x443c0468 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_can_rx_can2_rx: IOMUXC1_GPIO_IO27_CAN_RX_CAN2_RX { + pinmux = <0x443c007c 2 0x443c0364 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_flexio_flexio_flexio1_flexio27: IOMUXC1_GPIO_IO27_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c007c 7 0x443c03c8 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_gpio_io_gpio2_io27: IOMUXC1_GPIO_IO27_GPIO_IO_GPIO2_IO27 { + pinmux = <0x443c007c 0 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_jtag_mux_tms_jtag_mux_tms: IOMUXC1_GPIO_IO27_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c007c 5 0x443c03dc 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_lpspi_pcs_lpspi5_pcs1: IOMUXC1_GPIO_IO27_LPSPI_PCS_LPSPI5_PCS1 { + pinmux = <0x443c007c 6 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_mediamix_disp_data_mediamix_disp_data23: IOMUXC1_GPIO_IO27_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA23 { + pinmux = <0x443c007c 3 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_tpm_ch_tpm6_ch3: IOMUXC1_GPIO_IO27_TPM_CH_TPM6_CH3 { + pinmux = <0x443c007c 4 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_usdhc_data_usdhc3_data3: IOMUXC1_GPIO_IO27_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c007c 1 0x443c046c 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_flexio_flexio_flexio1_flexio28: IOMUXC1_GPIO_IO28_FLEXIO_FLEXIO_FLEXIO1_FLEXIO28 { + pinmux = <0x443c0080 7 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_gpio_io_gpio2_io28: IOMUXC1_GPIO_IO28_GPIO_IO_GPIO2_IO28 { + pinmux = <0x443c0080 0 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO28_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0080 1 0x443c03e4 1 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_flexio_flexio_flexio1_flexio29: IOMUXC1_GPIO_IO29_FLEXIO_FLEXIO_FLEXIO1_FLEXIO29 { + pinmux = <0x443c0084 7 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_gpio_io_gpio2_io29: IOMUXC1_GPIO_IO29_GPIO_IO_GPIO2_IO29 { + pinmux = <0x443c0084 0 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO29_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0084 1 0x443c03e0 1 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_gpio_io_gpio1_io00: IOMUXC1_I2C1_SCL_GPIO_IO_GPIO1_IO00 { + pinmux = <0x443c0170 5 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_i3c_scl_i3c1_scl: IOMUXC1_I2C1_SCL_I3C_SCL_I3C1_SCL { + pinmux = <0x443c0170 1 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl: IOMUXC1_I2C1_SCL_LPI2C_SCL_LPI2C1_SCL { + pinmux = <0x443c0170 0 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpuart_dcb_b_lpuart1_dcb_b: IOMUXC1_I2C1_SCL_LPUART_DCB_B_LPUART1_DCB_B { + pinmux = <0x443c0170 2 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_tpm_ch_tpm2_ch0: IOMUXC1_I2C1_SCL_TPM_CH_TPM2_CH0 { + pinmux = <0x443c0170 3 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_gpio_io_gpio1_io01: IOMUXC1_I2C1_SDA_GPIO_IO_GPIO1_IO01 { + pinmux = <0x443c0174 5 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_i3c_sda_i3c1_sda: IOMUXC1_I2C1_SDA_I3C_SDA_I3C1_SDA { + pinmux = <0x443c0174 1 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda: IOMUXC1_I2C1_SDA_LPI2C_SDA_LPI2C1_SDA { + pinmux = <0x443c0174 0 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpuart_rin_b_lpuart1_rin_b: IOMUXC1_I2C1_SDA_LPUART_RIN_B_LPUART1_RIN_B { + pinmux = <0x443c0174 2 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_tpm_ch_tpm2_ch1: IOMUXC1_I2C1_SDA_TPM_CH_TPM2_CH1 { + pinmux = <0x443c0174 3 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_gpio_io_gpio1_io02: IOMUXC1_I2C2_SCL_GPIO_IO_GPIO1_IO02 { + pinmux = <0x443c0178 5 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_b_i3c1_pur_b: IOMUXC1_I2C2_SCL_I3C_PUR_B_I3C1_PUR_B { + pinmux = <0x443c0178 6 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_i3c1_pur: IOMUXC1_I2C2_SCL_I3C_PUR_I3C1_PUR { + pinmux = <0x443c0178 1 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl: IOMUXC1_I2C2_SCL_LPI2C_SCL_LPI2C2_SCL { + pinmux = <0x443c0178 0 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpuart_dcb_b_lpuart2_dcb_b: IOMUXC1_I2C2_SCL_LPUART_DCB_B_LPUART2_DCB_B { + pinmux = <0x443c0178 2 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_sai_rx_sync_sai1_rx_sync: IOMUXC1_I2C2_SCL_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x443c0178 4 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_tpm_ch_tpm2_ch2: IOMUXC1_I2C2_SCL_TPM_CH_TPM2_CH2 { + pinmux = <0x443c0178 3 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_gpio_io_gpio1_io03: IOMUXC1_I2C2_SDA_GPIO_IO_GPIO1_IO03 { + pinmux = <0x443c017c 5 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda: IOMUXC1_I2C2_SDA_LPI2C_SDA_LPI2C2_SDA { + pinmux = <0x443c017c 0 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpuart_rin_b_lpuart2_rin_b: IOMUXC1_I2C2_SDA_LPUART_RIN_B_LPUART2_RIN_B { + pinmux = <0x443c017c 2 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_sai_rx_bclk_sai1_rx_bclk: IOMUXC1_I2C2_SDA_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x443c017c 4 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_tpm_ch_tpm2_ch3: IOMUXC1_I2C2_SDA_TPM_CH_TPM2_CH3 { + pinmux = <0x443c017c 3 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_can_rx_can1_rx: IOMUXC1_PDM_BIT_STREAM0_CAN_RX_CAN1_RX { + pinmux = <0x443c0194 6 0x443c0360 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09: IOMUXC1_PDM_BIT_STREAM0_GPIO_IO_GPIO1_IO09 { + pinmux = <0x443c0194 5 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lpspi_pcs_lpspi1_pcs1: IOMUXC1_PDM_BIT_STREAM0_LPSPI_PCS_LPSPI1_PCS1 { + pinmux = <0x443c0194 2 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lptmr_alt_lptmr1_alt2: IOMUXC1_PDM_BIT_STREAM0_LPTMR_ALT_LPTMR1_ALT2 { + pinmux = <0x443c0194 4 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_mqs_right_mqs1_right: IOMUXC1_PDM_BIT_STREAM0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c0194 1 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_PDM_BIT_STREAM0_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0194 0 0x443c0438 2 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_tpm_extclk_tpm1_extclk: IOMUXC1_PDM_BIT_STREAM0_TPM_EXTCLK_TPM1_EXTCLK { + pinmux = <0x443c0194 3 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0198 6 0x443c0368 1 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10: IOMUXC1_PDM_BIT_STREAM1_GPIO_IO_GPIO1_IO10 { + pinmux = <0x443c0198 5 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lpspi_pcs_lpspi2_pcs1: IOMUXC1_PDM_BIT_STREAM1_LPSPI_PCS_LPSPI2_PCS1 { + pinmux = <0x443c0198 2 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lptmr_alt_lptmr1_alt3: IOMUXC1_PDM_BIT_STREAM1_LPTMR_ALT_LPTMR1_ALT3 { + pinmux = <0x443c0198 4 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_nmi_glue_nmi_nmi_glue_nmi: IOMUXC1_PDM_BIT_STREAM1_NMI_GLUE_NMI_NMI_GLUE_NMI { + pinmux = <0x443c0198 1 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_PDM_BIT_STREAM1_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0198 0 0x443c043c 2 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_tpm_extclk_tpm2_extclk: IOMUXC1_PDM_BIT_STREAM1_TPM_EXTCLK_TPM2_EXTCLK { + pinmux = <0x443c0198 3 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_can_tx_can1_tx: IOMUXC1_PDM_CLK_CAN_TX_CAN1_TX { + pinmux = <0x443c0190 6 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_gpio_io_gpio1_io08: IOMUXC1_PDM_CLK_GPIO_IO_GPIO1_IO08 { + pinmux = <0x443c0190 5 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_lptmr_alt_lptmr1_alt1: IOMUXC1_PDM_CLK_LPTMR_ALT_LPTMR1_ALT1 { + pinmux = <0x443c0190 4 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_mqs_left_mqs1_left: IOMUXC1_PDM_CLK_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c0190 1 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_pdm_clk_pdm_clk: IOMUXC1_PDM_CLK_PDM_CLK_PDM_CLK { + pinmux = <0x443c0190 0 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_gpio_io_gpio1_io14: IOMUXC1_SAI1_RXD0_GPIO_IO_GPIO1_IO14 { + pinmux = <0x443c01a8 5 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpspi_sout_lpspi1_sout: IOMUXC1_SAI1_RXD0_LPSPI_SOUT_LPSPI1_SOUT { + pinmux = <0x443c01a8 2 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpuart_dsr_b_lpuart2_dsr_b: IOMUXC1_SAI1_RXD0_LPUART_DSR_B_LPUART2_DSR_B { + pinmux = <0x443c01a8 3 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_mqs_right_mqs1_right: IOMUXC1_SAI1_RXD0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c01a8 4 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_mclk_sai1_mclk: IOMUXC1_SAI1_RXD0_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c01a8 1 0x443c0448 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_rx_data_sai1_rx_data00: IOMUXC1_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA00 { + pinmux = <0x443c01a8 0 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_can_rx_can1_rx: IOMUXC1_SAI1_TXC_CAN_RX_CAN1_RX { + pinmux = <0x443c01a0 4 0x443c0360 1 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_gpio_io_gpio1_io12: IOMUXC1_SAI1_TXC_GPIO_IO_GPIO1_IO12 { + pinmux = <0x443c01a0 5 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpspi_sin_lpspi1_sin: IOMUXC1_SAI1_TXC_LPSPI_SIN_LPSPI1_SIN { + pinmux = <0x443c01a0 2 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_cts_b_lpuart2_cts_b: IOMUXC1_SAI1_TXC_LPUART_CTS_B_LPUART2_CTS_B { + pinmux = <0x443c01a0 1 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_dsr_b_lpuart1_dsr_b: IOMUXC1_SAI1_TXC_LPUART_DSR_B_LPUART1_DSR_B { + pinmux = <0x443c01a0 3 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC1_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x443c01a0 0 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_can_tx_can1_tx: IOMUXC1_SAI1_TXD0_CAN_TX_CAN1_TX { + pinmux = <0x443c01a4 4 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_gpio_io_gpio1_io13: IOMUXC1_SAI1_TXD0_GPIO_IO_GPIO1_IO13 { + pinmux = <0x443c01a4 5 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpspi_sck_lpspi1_sck: IOMUXC1_SAI1_TXD0_LPSPI_SCK_LPSPI1_SCK { + pinmux = <0x443c01a4 2 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_dtr_b_lpuart1_dtr_b: IOMUXC1_SAI1_TXD0_LPUART_DTR_B_LPUART1_DTR_B { + pinmux = <0x443c01a4 3 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_rts_b_lpuart2_rts_b: IOMUXC1_SAI1_TXD0_LPUART_RTS_B_LPUART2_RTS_B { + pinmux = <0x443c01a4 1 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_sai_tx_data_sai1_tx_data00: IOMUXC1_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA00 { + pinmux = <0x443c01a4 0 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_gpio_io_gpio1_io11: IOMUXC1_SAI1_TXFS_GPIO_IO_GPIO1_IO11 { + pinmux = <0x443c019c 5 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpspi_pcs_lpspi1_pcs0: IOMUXC1_SAI1_TXFS_LPSPI_PCS_LPSPI1_PCS0 { + pinmux = <0x443c019c 2 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpuart_dtr_b_lpuart2_dtr_b: IOMUXC1_SAI1_TXFS_LPUART_DTR_B_LPUART2_DTR_B { + pinmux = <0x443c019c 3 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_mqs_left_mqs1_left: IOMUXC1_SAI1_TXFS_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c019c 4 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_data_sai1_tx_data01: IOMUXC1_SAI1_TXFS_SAI_TX_DATA_SAI1_TX_DATA01 { + pinmux = <0x443c019c 1 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC1_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x443c019c 0 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_flexio_flexio_flexio1_flexio08: IOMUXC1_SD1_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0108 4 0x443c038c 1 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_gpio_io_gpio3_io08: IOMUXC1_SD1_CLK_GPIO_IO_GPIO3_IO08 { + pinmux = <0x443c0108 5 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC1_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x443c0108 0 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_flexio_flexio_flexio1_flexio09: IOMUXC1_SD1_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c010c 4 0x443c0390 1 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_gpio_io_gpio3_io09: IOMUXC1_SD1_CMD_GPIO_IO_GPIO3_IO09 { + pinmux = <0x443c010c 5 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC1_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x443c010c 0 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_flexio_flexio_flexio1_flexio10: IOMUXC1_SD1_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0110 4 0x443c0394 1 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_gpio_io_gpio3_io10: IOMUXC1_SD1_DATA0_GPIO_IO_GPIO3_IO10 { + pinmux = <0x443c0110 5 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC1_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x443c0110 0 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_flexio_flexio_flexio1_flexio11: IOMUXC1_SD1_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c0114 4 0x443c0398 1 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_gpio_io_gpio3_io11: IOMUXC1_SD1_DATA1_GPIO_IO_GPIO3_IO11 { + pinmux = <0x443c0114 5 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC1_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x443c0114 0 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_flexio_flexio_flexio1_flexio12: IOMUXC1_SD1_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO12 { + pinmux = <0x443c0118 4 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_gpio_io_gpio3_io12: IOMUXC1_SD1_DATA2_GPIO_IO_GPIO3_IO12 { + pinmux = <0x443c0118 5 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC1_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x443c0118 0 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexio_flexio_flexio1_flexio13: IOMUXC1_SD1_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c011c 4 0x443c039c 1 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexspi_a_ss_b_flexspi1_a_ss1_b: IOMUXC1_SD1_DATA3_FLEXSPI_A_SS_B_FLEXSPI1_A_SS1_B { + pinmux = <0x443c011c 1 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_gpio_io_gpio3_io13: IOMUXC1_SD1_DATA3_GPIO_IO_GPIO3_IO13 { + pinmux = <0x443c011c 5 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC1_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x443c011c 0 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexio_flexio_flexio1_flexio14: IOMUXC1_SD1_DATA4_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0120 4 0x443c03a0 1 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexspi_a_data_flexspi1_a_data04: IOMUXC1_SD1_DATA4_FLEXSPI_A_DATA_FLEXSPI1_A_DATA04 { + pinmux = <0x443c0120 1 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_gpio_io_gpio3_io14: IOMUXC1_SD1_DATA4_GPIO_IO_GPIO3_IO14 { + pinmux = <0x443c0120 5 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC1_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x443c0120 0 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexio_flexio_flexio1_flexio15: IOMUXC1_SD1_DATA5_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c0124 4 0x443c03a4 1 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexspi_a_data_flexspi1_a_data05: IOMUXC1_SD1_DATA5_FLEXSPI_A_DATA_FLEXSPI1_A_DATA05 { + pinmux = <0x443c0124 1 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_gpio_io_gpio3_io15: IOMUXC1_SD1_DATA5_GPIO_IO_GPIO3_IO15 { + pinmux = <0x443c0124 5 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC1_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x443c0124 0 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_reset_b_usdhc1_reset_b: IOMUXC1_SD1_DATA5_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x443c0124 2 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexio_flexio_flexio1_flexio16: IOMUXC1_SD1_DATA6_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0128 4 0x443c03a8 1 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexspi_a_data_flexspi1_a_data06: IOMUXC1_SD1_DATA6_FLEXSPI_A_DATA_FLEXSPI1_A_DATA06 { + pinmux = <0x443c0128 1 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_gpio_io_gpio3_io16: IOMUXC1_SD1_DATA6_GPIO_IO_GPIO3_IO16 { + pinmux = <0x443c0128 5 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_cd_b_usdhc1_cd_b: IOMUXC1_SD1_DATA6_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x443c0128 2 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC1_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x443c0128 0 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexio_flexio_flexio1_flexio17: IOMUXC1_SD1_DATA7_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c012c 4 0x443c03ac 1 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexspi_a_data_flexspi1_a_data07: IOMUXC1_SD1_DATA7_FLEXSPI_A_DATA_FLEXSPI1_A_DATA07 { + pinmux = <0x443c012c 1 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_gpio_io_gpio3_io17: IOMUXC1_SD1_DATA7_GPIO_IO_GPIO3_IO17 { + pinmux = <0x443c012c 5 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC1_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x443c012c 0 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_wp_usdhc1_wp: IOMUXC1_SD1_DATA7_USDHC_WP_USDHC1_WP { + pinmux = <0x443c012c 2 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexio_flexio_flexio1_flexio18: IOMUXC1_SD1_STROBE_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0130 4 0x443c03b0 1 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexspi_a_dqs_flexspi1_a_dqs: IOMUXC1_SD1_STROBE_FLEXSPI_A_DQS_FLEXSPI1_A_DQS { + pinmux = <0x443c0130 1 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_gpio_io_gpio3_io18: IOMUXC1_SD1_STROBE_GPIO_IO_GPIO3_IO18 { + pinmux = <0x443c0130 5 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC1_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x443c0130 0 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC1_SD2_CD_B_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x443c0150 1 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_flexio_flexio_flexio1_flexio00: IOMUXC1_SD2_CD_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0150 4 0x443c036c 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_gpio_io_gpio3_io00: IOMUXC1_SD2_CD_B_GPIO_IO_GPIO3_IO00 { + pinmux = <0x443c0150 5 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_i3c_scl_i3c2_scl: IOMUXC1_SD2_CD_B_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0150 2 0x443c03cc 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC1_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x443c0150 0 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe0: IOMUXC1_SD2_CLK_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE0 { + pinmux = <0x443c0154 6 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC1_SD2_CLK_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x443c0154 1 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_flexio_flexio_flexio1_flexio01: IOMUXC1_SD2_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0154 4 0x443c0370 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_gpio_io_gpio3_io01: IOMUXC1_SD2_CLK_GPIO_IO_GPIO3_IO01 { + pinmux = <0x443c0154 5 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_i3c_sda_i3c2_sda: IOMUXC1_SD2_CLK_I3C_SDA_I3C2_SDA { + pinmux = <0x443c0154 2 0x443c03d0 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC1_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x443c0154 0 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe1: IOMUXC1_SD2_CMD_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE1 { + pinmux = <0x443c0158 6 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_enet1_1588_event0_in_enet1_1588_event0_in: IOMUXC1_SD2_CMD_ENET1_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x443c0158 1 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_flexio_flexio_flexio1_flexio02: IOMUXC1_SD2_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0158 4 0x443c0374 1 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_gpio_io_gpio3_io02: IOMUXC1_SD2_CMD_GPIO_IO_GPIO3_IO02 { + pinmux = <0x443c0158 5 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_b_i3c2_pur_b: IOMUXC1_SD2_CMD_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c0158 3 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_i3c2_pur: IOMUXC1_SD2_CMD_I3C_PUR_I3C2_PUR { + pinmux = <0x443c0158 2 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC1_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x443c0158 0 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_can_tx_can2_tx: IOMUXC1_SD2_DATA0_CAN_TX_CAN2_TX { + pinmux = <0x443c015c 2 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe2: IOMUXC1_SD2_DATA0_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE2 { + pinmux = <0x443c015c 6 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_enet1_1588_event0_out_enet1_1588_event0_out: IOMUXC1_SD2_DATA0_ENET1_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x443c015c 1 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_flexio_flexio_flexio1_flexio03: IOMUXC1_SD2_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c015c 4 0x443c0378 1 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_gpio_io_gpio3_io03: IOMUXC1_SD2_DATA0_GPIO_IO_GPIO3_IO03 { + pinmux = <0x443c015c 5 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC1_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x443c015c 0 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_can_rx_can2_rx: IOMUXC1_SD2_DATA1_CAN_RX_CAN2_RX { + pinmux = <0x443c0160 2 0x443c0364 3 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_enet1_1588_event1_in_enet1_1588_event1_in: IOMUXC1_SD2_DATA1_ENET1_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x443c0160 1 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_flexio_flexio_flexio1_flexio04: IOMUXC1_SD2_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0160 4 0x443c037c 1 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_gpio_io_gpio3_io04: IOMUXC1_SD2_DATA1_GPIO_IO_GPIO3_IO04 { + pinmux = <0x443c0160 5 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC1_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x443c0160 0 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_enet1_1588_event1_out_enet1_1588_event1_out: IOMUXC1_SD2_DATA2_ENET1_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x443c0164 1 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_flexio_flexio_flexio1_flexio05: IOMUXC1_SD2_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0164 4 0x443c0380 1 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_gpio_io_gpio3_io05: IOMUXC1_SD2_DATA2_GPIO_IO_GPIO3_IO05 { + pinmux = <0x443c0164 5 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_mqs_right_mqs2_right: IOMUXC1_SD2_DATA2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0164 2 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC1_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x443c0164 0 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_flexio_flexio_flexio1_flexio06: IOMUXC1_SD2_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0168 4 0x443c0384 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_gpio_io_gpio3_io06: IOMUXC1_SD2_DATA3_GPIO_IO_GPIO3_IO06 { + pinmux = <0x443c0168 5 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_lptmr_alt_lptmr2_alt1: IOMUXC1_SD2_DATA3_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c0168 1 0x443c0408 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_mqs_left_mqs2_left: IOMUXC1_SD2_DATA3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0168 2 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC1_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x443c0168 0 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_ccmsrcgpcmix_system_reset_ccmsrcgpcmix_system_reset: IOMUXC1_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET_CCMSRCGPCMIX_SYSTEM_RESET { + pinmux = <0x443c016c 6 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_flexio_flexio_flexio1_flexio07: IOMUXC1_SD2_RESET_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c016c 4 0x443c0388 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_gpio_io_gpio3_io07: IOMUXC1_SD2_RESET_B_GPIO_IO_GPIO3_IO07 { + pinmux = <0x443c016c 5 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_lptmr_alt_lptmr2_alt2: IOMUXC1_SD2_RESET_B_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c016c 1 0x443c040c 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC1_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x443c016c 0 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0134 6 0x443c0368 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_flexio_flexio_flexio1_flexio19: IOMUXC1_SD2_VSELECT_FLEXIO_FLEXIO_FLEXIO1_FLEXIO19 { + pinmux = <0x443c0134 4 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_gpio_io_gpio3_io19: IOMUXC1_SD2_VSELECT_GPIO_IO_GPIO3_IO19 { + pinmux = <0x443c0134 5 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_lptmr_alt_lptmr2_alt3: IOMUXC1_SD2_VSELECT_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c0134 2 0x443c0410 1 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect: IOMUXC1_SD2_VSELECT_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x443c0134 0 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_wp_usdhc2_wp: IOMUXC1_SD2_VSELECT_USDHC_WP_USDHC2_WP { + pinmux = <0x443c0134 1 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexio_flexio_flexio1_flexio20: IOMUXC1_SD3_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0138 4 0x443c03b4 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexspi_a_sclk_flexspi1_a_sclk: IOMUXC1_SD3_CLK_FLEXSPI_A_SCLK_FLEXSPI1_A_SCLK { + pinmux = <0x443c0138 1 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_gpio_io_gpio3_io20: IOMUXC1_SD3_CLK_GPIO_IO_GPIO3_IO20 { + pinmux = <0x443c0138 5 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_usdhc_clk_usdhc3_clk: IOMUXC1_SD3_CLK_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0138 0 0x443c0458 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexio_flexio_flexio1_flexio21: IOMUXC1_SD3_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO21 { + pinmux = <0x443c013c 4 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexspi_a_ss_b_flexspi1_a_ss0_b: IOMUXC1_SD3_CMD_FLEXSPI_A_SS_B_FLEXSPI1_A_SS0_B { + pinmux = <0x443c013c 1 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_gpio_io_gpio3_io21: IOMUXC1_SD3_CMD_GPIO_IO_GPIO3_IO21 { + pinmux = <0x443c013c 5 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_usdhc_cmd_usdhc3_cmd: IOMUXC1_SD3_CMD_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c013c 0 0x443c045c 1 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexio_flexio_flexio1_flexio22: IOMUXC1_SD3_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0140 4 0x443c03b8 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexspi_a_data_flexspi1_a_data00: IOMUXC1_SD3_DATA0_FLEXSPI_A_DATA_FLEXSPI1_A_DATA00 { + pinmux = <0x443c0140 1 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_gpio_io_gpio3_io22: IOMUXC1_SD3_DATA0_GPIO_IO_GPIO3_IO22 { + pinmux = <0x443c0140 5 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_usdhc_data_usdhc3_data0: IOMUXC1_SD3_DATA0_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0140 0 0x443c0460 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexio_flexio_flexio1_flexio23: IOMUXC1_SD3_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c0144 4 0x443c03bc 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexspi_a_data_flexspi1_a_data01: IOMUXC1_SD3_DATA1_FLEXSPI_A_DATA_FLEXSPI1_A_DATA01 { + pinmux = <0x443c0144 1 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_gpio_io_gpio3_io23: IOMUXC1_SD3_DATA1_GPIO_IO_GPIO3_IO23 { + pinmux = <0x443c0144 5 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_usdhc_data_usdhc3_data1: IOMUXC1_SD3_DATA1_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0144 0 0x443c0464 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexio_flexio_flexio1_flexio24: IOMUXC1_SD3_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0148 4 0x443c03c0 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexspi_a_data_flexspi1_a_data02: IOMUXC1_SD3_DATA2_FLEXSPI_A_DATA_FLEXSPI1_A_DATA02 { + pinmux = <0x443c0148 1 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_gpio_io_gpio3_io24: IOMUXC1_SD3_DATA2_GPIO_IO_GPIO3_IO24 { + pinmux = <0x443c0148 5 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_usdhc_data_usdhc3_data2: IOMUXC1_SD3_DATA2_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0148 0 0x443c0468 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexio_flexio_flexio1_flexio25: IOMUXC1_SD3_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c014c 4 0x443c03c4 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexspi_a_data_flexspi1_a_data03: IOMUXC1_SD3_DATA3_FLEXSPI_A_DATA_FLEXSPI1_A_DATA03 { + pinmux = <0x443c014c 1 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_gpio_io_gpio3_io25: IOMUXC1_SD3_DATA3_GPIO_IO_GPIO3_IO25 { + pinmux = <0x443c014c 5 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_usdhc_data_usdhc3_data3: IOMUXC1_SD3_DATA3_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c014c 0 0x443c046c 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_gpio_io_gpio1_io04: IOMUXC1_UART1_RXD_GPIO_IO_GPIO1_IO04 { + pinmux = <0x443c0180 5 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpspi_sin_lpspi2_sin: IOMUXC1_UART1_RXD_LPSPI_SIN_LPSPI2_SIN { + pinmux = <0x443c0180 2 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx: IOMUXC1_UART1_RXD_LPUART_RX_LPUART1_RX { + pinmux = <0x443c0180 0 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_s400_uart_rx_s400_uart_rx: IOMUXC1_UART1_RXD_S400_UART_RX_S400_UART_RX { + pinmux = <0x443c0180 1 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_tpm_ch_tpm1_ch0: IOMUXC1_UART1_RXD_TPM_CH_TPM1_CH0 { + pinmux = <0x443c0180 3 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_gpio_io_gpio1_io05: IOMUXC1_UART1_TXD_GPIO_IO_GPIO1_IO05 { + pinmux = <0x443c0184 5 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpspi_pcs_lpspi2_pcs0: IOMUXC1_UART1_TXD_LPSPI_PCS_LPSPI2_PCS0 { + pinmux = <0x443c0184 2 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx: IOMUXC1_UART1_TXD_LPUART_TX_LPUART1_TX { + pinmux = <0x443c0184 0 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_s400_uart_tx_s400_uart_tx: IOMUXC1_UART1_TXD_S400_UART_TX_S400_UART_TX { + pinmux = <0x443c0184 1 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_tpm_ch_tpm1_ch1: IOMUXC1_UART1_TXD_TPM_CH_TPM1_CH1 { + pinmux = <0x443c0184 3 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_gpio_io_gpio1_io06: IOMUXC1_UART2_RXD_GPIO_IO_GPIO1_IO06 { + pinmux = <0x443c0188 5 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpspi_sout_lpspi2_sout: IOMUXC1_UART2_RXD_LPSPI_SOUT_LPSPI2_SOUT { + pinmux = <0x443c0188 2 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_cts_b_lpuart1_cts_b: IOMUXC1_UART2_RXD_LPUART_CTS_B_LPUART1_CTS_B { + pinmux = <0x443c0188 1 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx: IOMUXC1_UART2_RXD_LPUART_RX_LPUART2_RX { + pinmux = <0x443c0188 0 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_sai_mclk_sai1_mclk: IOMUXC1_UART2_RXD_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c0188 4 0x443c0448 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_tpm_ch_tpm1_ch2: IOMUXC1_UART2_RXD_TPM_CH_TPM1_CH2 { + pinmux = <0x443c0188 3 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_gpio_io_gpio1_io07: IOMUXC1_UART2_TXD_GPIO_IO_GPIO1_IO07 { + pinmux = <0x443c018c 5 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpspi_sck_lpspi2_sck: IOMUXC1_UART2_TXD_LPSPI_SCK_LPSPI2_SCK { + pinmux = <0x443c018c 2 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_rts_b_lpuart1_rts_b: IOMUXC1_UART2_TXD_LPUART_RTS_B_LPUART1_RTS_B { + pinmux = <0x443c018c 1 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx: IOMUXC1_UART2_TXD_LPUART_TX_LPUART2_TX { + pinmux = <0x443c018c 0 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_tpm_ch_tpm1_ch3: IOMUXC1_UART2_TXD_TPM_CH_TPM1_CH3 { + pinmux = <0x443c018c 3 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_gpio_io_gpio1_io15: IOMUXC1_WDOG_ANY_GPIO_IO_GPIO1_IO15 { + pinmux = <0x443c01ac 5 0x0 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_wdog_wdog_any_wdog1_wdog_any: IOMUXC1_WDOG_ANY_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x443c01ac 0 0x0 0 0x443c035c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx9352xvvxm-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx9352xvvxm-pinctrl.dtsi new file mode 100644 index 000000000..fb5e8820e --- /dev/null +++ b/dts/nxp/nxp_imx/mimx9352xvvxm-pinctrl.dtsi @@ -0,0 +1,1831 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX9352XVVXM + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc1_ccm_clko1_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko1: IOMUXC1_CCM_CLKO1_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO1 { + pinmux = <0x443c0088 0 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_flexio_flexio_flexio1_flexio26: IOMUXC1_CCM_CLKO1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO26 { + pinmux = <0x443c0088 4 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko1_gpio_io_gpio3_io26: IOMUXC1_CCM_CLKO1_GPIO_IO_GPIO3_IO26 { + pinmux = <0x443c0088 5 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko2: IOMUXC1_CCM_CLKO2_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO2 { + pinmux = <0x443c008c 0 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_flexio_flexio_flexio1_flexio27: IOMUXC1_CCM_CLKO2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c008c 4 0x443c03c8 1 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko2_gpio_io_gpio3_io27: IOMUXC1_CCM_CLKO2_GPIO_IO_GPIO3_IO27 { + pinmux = <0x443c008c 5 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko3: IOMUXC1_CCM_CLKO3_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO3 { + pinmux = <0x443c0090 0 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_flexio_flexio_flexio2_flexio28: IOMUXC1_CCM_CLKO3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO28 { + pinmux = <0x443c0090 4 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko3_gpio_io_gpio4_io28: IOMUXC1_CCM_CLKO3_GPIO_IO_GPIO4_IO28 { + pinmux = <0x443c0090 5 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko4: IOMUXC1_CCM_CLKO4_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO4 { + pinmux = <0x443c0094 0 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_flexio_flexio_flexio2_flexio29: IOMUXC1_CCM_CLKO4_FLEXIO_FLEXIO_FLEXIO2_FLEXIO29 { + pinmux = <0x443c0094 4 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_ccm_clko4_gpio_io_gpio4_io29: IOMUXC1_CCM_CLKO4_GPIO_IO_GPIO4_IO29 { + pinmux = <0x443c0094 5 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_flexio_flexio_flexio1_flexio30: IOMUXC1_DAP_TCLK_SWCLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO30 { + pinmux = <0x443c0008 4 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30: IOMUXC1_DAP_TCLK_SWCLK_GPIO_IO_GPIO3_IO30 { + pinmux = <0x443c0008 5 0x0 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_jtag_mux_tck_jtag_mux_tck: IOMUXC1_DAP_TCLK_SWCLK_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0008 0 0x443c03d4 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tclk_swclk_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_DAP_TCLK_SWCLK_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0008 6 0x443c042c 0 0x443c01b8>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_can_tx_can2_tx: IOMUXC1_DAP_TDI_CAN_TX_CAN2_TX { + pinmux = <0x443c0000 3 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_flexio_flexio_flexio2_flexio30: IOMUXC1_DAP_TDI_FLEXIO_FLEXIO_FLEXIO2_FLEXIO30 { + pinmux = <0x443c0000 4 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_gpio_io_gpio3_io28: IOMUXC1_DAP_TDI_GPIO_IO_GPIO3_IO28 { + pinmux = <0x443c0000 5 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_DAP_TDI_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0000 0 0x443c03d8 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_lpuart_rx_lpuart5_rx: IOMUXC1_DAP_TDI_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0000 6 0x443c0430 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdi_mqs_left_mqs2_left: IOMUXC1_DAP_TDI_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0000 1 0x0 0 0x443c01b0>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_can_rx_can2_rx: IOMUXC1_DAP_TDO_TRACESWO_CAN_RX_CAN2_RX { + pinmux = <0x443c000c 3 0x443c0364 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_flexio_flexio_flexio1_flexio31: IOMUXC1_DAP_TDO_TRACESWO_FLEXIO_FLEXIO_FLEXIO1_FLEXIO31 { + pinmux = <0x443c000c 4 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31: IOMUXC1_DAP_TDO_TRACESWO_GPIO_IO_GPIO3_IO31 { + pinmux = <0x443c000c 5 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_DAP_TDO_TRACESWO_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c000c 0 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_lpuart_tx_lpuart5_tx: IOMUXC1_DAP_TDO_TRACESWO_LPUART_TX_LPUART5_TX { + pinmux = <0x443c000c 6 0x443c0434 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tdo_traceswo_mqs_right_mqs2_right: IOMUXC1_DAP_TDO_TRACESWO_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c000c 1 0x0 0 0x443c01bc>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_flexio_flexio_flexio2_flexio31: IOMUXC1_DAP_TMS_SWDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO31 { + pinmux = <0x443c0004 4 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29: IOMUXC1_DAP_TMS_SWDIO_GPIO_IO_GPIO3_IO29 { + pinmux = <0x443c0004 5 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_jtag_mux_tms_jtag_mux_tms: IOMUXC1_DAP_TMS_SWDIO_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c0004 0 0x443c03dc 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_dap_tms_swdio_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_DAP_TMS_SWDIO_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c0004 6 0x0 0 0x443c01b4>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_enet_qos_mdc_enet_qos_mdc: IOMUXC1_ENET1_MDC_ENET_QOS_MDC_ENET_QOS_MDC { + pinmux = <0x443c0098 0 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_flexio_flexio_flexio2_flexio00: IOMUXC1_ENET1_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO00 { + pinmux = <0x443c0098 4 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_gpio_io_gpio4_io00: IOMUXC1_ENET1_MDC_GPIO_IO_GPIO4_IO00 { + pinmux = <0x443c0098 5 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_hsiomix_otg_id_hsiomix_otg_id1: IOMUXC1_ENET1_MDC_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID1 { + pinmux = <0x443c0098 3 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_i3c_scl_i3c2_scl: IOMUXC1_ENET1_MDC_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0098 2 0x443c03cc 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdc_lpuart_dcb_b_lpuart3_dcb_b: IOMUXC1_ENET1_MDC_LPUART_DCB_B_LPUART3_DCB_B { + pinmux = <0x443c0098 1 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_enet_qos_mdio_enet_qos_mdio: IOMUXC1_ENET1_MDIO_ENET_QOS_MDIO_ENET_QOS_MDIO { + pinmux = <0x443c009c 0 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_flexio_flexio_flexio2_flexio01: IOMUXC1_ENET1_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO01 { + pinmux = <0x443c009c 4 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_gpio_io_gpio4_io01: IOMUXC1_ENET1_MDIO_GPIO_IO_GPIO4_IO01 { + pinmux = <0x443c009c 5 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_hsiomix_otg_pwr_hsiomix_otg_pwr1: IOMUXC1_ENET1_MDIO_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR1 { + pinmux = <0x443c009c 3 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_i3c_sda_i3c2_sda: IOMUXC1_ENET1_MDIO_I3C_SDA_I3C2_SDA { + pinmux = <0x443c009c 2 0x443c03d0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_mdio_lpuart_rin_b_lpuart3_rin_b: IOMUXC1_ENET1_MDIO_LPUART_RIN_B_LPUART3_RIN_B { + pinmux = <0x443c009c 1 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_enet_qos_rgmii_rd_enet_qos_rgmii_rd0: IOMUXC1_ENET1_RD0_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD0 { + pinmux = <0x443c00c0 0 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_flexio_flexio_flexio2_flexio10: IOMUXC1_ENET1_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO10 { + pinmux = <0x443c00c0 4 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_gpio_io_gpio4_io10: IOMUXC1_ENET1_RD0_GPIO_IO_GPIO4_IO10 { + pinmux = <0x443c00c0 5 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd0_lpuart_rx_lpuart3_rx: IOMUXC1_ENET1_RD0_LPUART_RX_LPUART3_RX { + pinmux = <0x443c00c0 1 0x443c0418 1 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_enet_qos_rgmii_rd_enet_qos_rgmii_rd1: IOMUXC1_ENET1_RD1_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD1 { + pinmux = <0x443c00c4 0 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_flexio_flexio_flexio2_flexio11: IOMUXC1_ENET1_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO11 { + pinmux = <0x443c00c4 4 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_gpio_io_gpio4_io11: IOMUXC1_ENET1_RD1_GPIO_IO_GPIO4_IO11 { + pinmux = <0x443c00c4 5 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lptmr_alt_lptmr2_alt1: IOMUXC1_ENET1_RD1_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c00c4 3 0x443c0408 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd1_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_ENET1_RD1_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c00c4 1 0x443c0414 1 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_enet_qos_rgmii_rd_enet_qos_rgmii_rd2: IOMUXC1_ENET1_RD2_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD2 { + pinmux = <0x443c00c8 0 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_flexio_flexio_flexio2_flexio12: IOMUXC1_ENET1_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO12 { + pinmux = <0x443c00c8 4 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_gpio_io_gpio4_io12: IOMUXC1_ENET1_RD2_GPIO_IO_GPIO4_IO12 { + pinmux = <0x443c00c8 5 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd2_lptmr_alt_lptmr2_alt2: IOMUXC1_ENET1_RD2_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c00c8 3 0x443c040c 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_enet_qos_rgmii_rd_enet_qos_rgmii_rd3: IOMUXC1_ENET1_RD3_ENET_QOS_RGMII_RD_ENET_QOS_RGMII_RD3 { + pinmux = <0x443c00cc 0 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_flexio_flexio_flexio2_flexio13: IOMUXC1_ENET1_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO13 { + pinmux = <0x443c00cc 4 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_gpio_io_gpio4_io13: IOMUXC1_ENET1_RD3_GPIO_IO_GPIO4_IO13 { + pinmux = <0x443c00cc 5 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rd3_lptmr_alt_lptmr2_alt3: IOMUXC1_ENET1_RD3_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c00cc 3 0x443c0410 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_ccm_enet_qos_clock_generate_rx_clk_ccm_enet_qos_clock_generate_rx_clk: IOMUXC1_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK { + pinmux = <0x443c00bc 0 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_enet_qos_rx_er_enet_qos_rx_er: IOMUXC1_ENET1_RXC_ENET_QOS_RX_ER_ENET_QOS_RX_ER { + pinmux = <0x443c00bc 1 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_flexio_flexio_flexio2_flexio09: IOMUXC1_ENET1_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO09 { + pinmux = <0x443c00bc 4 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rxc_gpio_io_gpio4_io09: IOMUXC1_ENET1_RXC_GPIO_IO_GPIO4_IO09 { + pinmux = <0x443c00bc 5 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_enet_qos_rgmii_rx_ctl_enet_qos_rgmii_rx_ctl: IOMUXC1_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL_ENET_QOS_RGMII_RX_CTL { + pinmux = <0x443c00b8 0 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_flexio_flexio_flexio2_flexio08: IOMUXC1_ENET1_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO08 { + pinmux = <0x443c00b8 4 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08: IOMUXC1_ENET1_RX_CTL_GPIO_IO_GPIO4_IO08 { + pinmux = <0x443c00b8 5 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_hsiomix_otg_pwr_hsiomix_otg_pwr2: IOMUXC1_ENET1_RX_CTL_HSIOMIX_OTG_PWR_HSIOMIX_OTG_PWR2 { + pinmux = <0x443c00b8 3 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_rx_ctl_lpuart_dsr_b_lpuart3_dsr_b: IOMUXC1_ENET1_RX_CTL_LPUART_DSR_B_LPUART3_DSR_B { + pinmux = <0x443c00b8 1 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_enet_qos_rgmii_td_enet_qos_rgmii_td0: IOMUXC1_ENET1_TD0_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD0 { + pinmux = <0x443c00ac 0 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_flexio_flexio_flexio2_flexio05: IOMUXC1_ENET1_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO05 { + pinmux = <0x443c00ac 4 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_gpio_io_gpio4_io05: IOMUXC1_ENET1_TD0_GPIO_IO_GPIO4_IO05 { + pinmux = <0x443c00ac 5 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td0_lpuart_tx_lpuart3_tx: IOMUXC1_ENET1_TD0_LPUART_TX_LPUART3_TX { + pinmux = <0x443c00ac 1 0x443c041c 1 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_enet_qos_rgmii_td_enet_qos_rgmii_td1: IOMUXC1_ENET1_TD1_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD1 { + pinmux = <0x443c00a8 0 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_flexio_flexio_flexio2_flexio04: IOMUXC1_ENET1_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO04 { + pinmux = <0x443c00a8 4 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_gpio_io_gpio4_io04: IOMUXC1_ENET1_TD1_GPIO_IO_GPIO4_IO04 { + pinmux = <0x443c00a8 5 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_hsiomix_otg_oc_hsiomix_otg_oc1: IOMUXC1_ENET1_TD1_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC1 { + pinmux = <0x443c00a8 3 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_b_i3c2_pur_b: IOMUXC1_ENET1_TD1_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c00a8 6 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_i3c_pur_i3c2_pur: IOMUXC1_ENET1_TD1_I3C_PUR_I3C2_PUR { + pinmux = <0x443c00a8 2 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td1_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_ENET1_TD1_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c00a8 1 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_can_rx_can2_rx: IOMUXC1_ENET1_TD2_CAN_RX_CAN2_RX { + pinmux = <0x443c00a4 2 0x443c0364 2 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_ccm_enet_qos_clock_generate_ref_clk_ccm_enet_qos_clock_generate_ref_clk: IOMUXC1_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK { + pinmux = <0x443c00a4 1 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_enet_qos_rgmii_td_enet_qos_rgmii_td2: IOMUXC1_ENET1_TD2_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD2 { + pinmux = <0x443c00a4 0 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_flexio_flexio_flexio2_flexio03: IOMUXC1_ENET1_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO03 { + pinmux = <0x443c00a4 4 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_gpio_io_gpio4_io03: IOMUXC1_ENET1_TD2_GPIO_IO_GPIO4_IO03 { + pinmux = <0x443c00a4 5 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td2_hsiomix_otg_oc_hsiomix_otg_oc2: IOMUXC1_ENET1_TD2_HSIOMIX_OTG_OC_HSIOMIX_OTG_OC2 { + pinmux = <0x443c00a4 3 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_can_tx_can2_tx: IOMUXC1_ENET1_TD3_CAN_TX_CAN2_TX { + pinmux = <0x443c00a0 2 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_enet_qos_rgmii_td_enet_qos_rgmii_td3: IOMUXC1_ENET1_TD3_ENET_QOS_RGMII_TD_ENET_QOS_RGMII_TD3 { + pinmux = <0x443c00a0 0 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_flexio_flexio_flexio2_flexio02: IOMUXC1_ENET1_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO02 { + pinmux = <0x443c00a0 4 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_gpio_io_gpio4_io02: IOMUXC1_ENET1_TD3_GPIO_IO_GPIO4_IO02 { + pinmux = <0x443c00a0 5 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_td3_hsiomix_otg_id_hsiomix_otg_id2: IOMUXC1_ENET1_TD3_HSIOMIX_OTG_ID_HSIOMIX_OTG_ID2 { + pinmux = <0x443c00a0 3 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_ccm_enet_qos_clock_generate_tx_clk_ccm_enet_qos_clock_generate_tx_clk: IOMUXC1_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK { + pinmux = <0x443c00b4 0 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_enet_qos_tx_er_enet_qos_tx_er: IOMUXC1_ENET1_TXC_ENET_QOS_TX_ER_ENET_QOS_TX_ER { + pinmux = <0x443c00b4 1 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_flexio_flexio_flexio2_flexio07: IOMUXC1_ENET1_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO07 { + pinmux = <0x443c00b4 4 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_txc_gpio_io_gpio4_io07: IOMUXC1_ENET1_TXC_GPIO_IO_GPIO4_IO07 { + pinmux = <0x443c00b4 5 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_enet_qos_rgmii_tx_ctl_enet_qos_rgmii_tx_ctl: IOMUXC1_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL_ENET_QOS_RGMII_TX_CTL { + pinmux = <0x443c00b0 0 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_flexio_flexio_flexio2_flexio06: IOMUXC1_ENET1_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO06 { + pinmux = <0x443c00b0 4 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06: IOMUXC1_ENET1_TX_CTL_GPIO_IO_GPIO4_IO06 { + pinmux = <0x443c00b0 5 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet1_tx_ctl_lpuart_dtr_b_lpuart3_dtr_b: IOMUXC1_ENET1_TX_CTL_LPUART_DTR_B_LPUART3_DTR_B { + pinmux = <0x443c00b0 1 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_enet_mdc_enet1_mdc: IOMUXC1_ENET2_MDC_ENET_MDC_ENET1_MDC { + pinmux = <0x443c00d0 0 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_flexio_flexio_flexio2_flexio14: IOMUXC1_ENET2_MDC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO14 { + pinmux = <0x443c00d0 4 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_gpio_io_gpio4_io14: IOMUXC1_ENET2_MDC_GPIO_IO_GPIO4_IO14 { + pinmux = <0x443c00d0 5 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_lpuart_dcb_b_lpuart4_dcb_b: IOMUXC1_ENET2_MDC_LPUART_DCB_B_LPUART4_DCB_B { + pinmux = <0x443c00d0 1 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdc_sai_rx_sync_sai2_rx_sync: IOMUXC1_ENET2_MDC_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x443c00d0 2 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_enet_mdio_enet1_mdio: IOMUXC1_ENET2_MDIO_ENET_MDIO_ENET1_MDIO { + pinmux = <0x443c00d4 0 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_flexio_flexio_flexio2_flexio15: IOMUXC1_ENET2_MDIO_FLEXIO_FLEXIO_FLEXIO2_FLEXIO15 { + pinmux = <0x443c00d4 4 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_gpio_io_gpio4_io15: IOMUXC1_ENET2_MDIO_GPIO_IO_GPIO4_IO15 { + pinmux = <0x443c00d4 5 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_lpuart_rin_b_lpuart4_rin_b: IOMUXC1_ENET2_MDIO_LPUART_RIN_B_LPUART4_RIN_B { + pinmux = <0x443c00d4 1 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_mdio_sai_rx_bclk_sai2_rx_bclk: IOMUXC1_ENET2_MDIO_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x443c00d4 2 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0: IOMUXC1_ENET2_RD0_ENET_RGMII_RD_ENET1_RGMII_RD0 { + pinmux = <0x443c00f8 0 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_flexio_flexio_flexio2_flexio24: IOMUXC1_ENET2_RD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO24 { + pinmux = <0x443c00f8 4 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_gpio_io_gpio4_io24: IOMUXC1_ENET2_RD0_GPIO_IO_GPIO4_IO24 { + pinmux = <0x443c00f8 5 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_lpuart_rx_lpuart4_rx: IOMUXC1_ENET2_RD0_LPUART_RX_LPUART4_RX { + pinmux = <0x443c00f8 1 0x443c0424 1 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd0_sai_tx_data_sai2_tx_data02: IOMUXC1_ENET2_RD0_SAI_TX_DATA_SAI2_TX_DATA02 { + pinmux = <0x443c00f8 2 0x0 0 0x443c02a8>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1: IOMUXC1_ENET2_RD1_ENET_RGMII_RD_ENET1_RGMII_RD1 { + pinmux = <0x443c00fc 0 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_flexio_flexio_flexio2_flexio25: IOMUXC1_ENET2_RD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO25 { + pinmux = <0x443c00fc 4 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_gpio_io_gpio4_io25: IOMUXC1_ENET2_RD1_GPIO_IO_GPIO4_IO25 { + pinmux = <0x443c00fc 5 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_sai_tx_data_sai2_tx_data03: IOMUXC1_ENET2_RD1_SAI_TX_DATA_SAI2_TX_DATA03 { + pinmux = <0x443c00fc 2 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd1_spdif_in_spdif_in: IOMUXC1_ENET2_RD1_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c00fc 1 0x443c0454 1 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2: IOMUXC1_ENET2_RD2_ENET_RGMII_RD_ENET1_RGMII_RD2 { + pinmux = <0x443c0100 0 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_flexio_flexio_flexio2_flexio26: IOMUXC1_ENET2_RD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO26 { + pinmux = <0x443c0100 4 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_gpio_io_gpio4_io26: IOMUXC1_ENET2_RD2_GPIO_IO_GPIO4_IO26 { + pinmux = <0x443c0100 5 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_ENET2_RD2_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0100 1 0x443c0420 1 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_mqs_right_mqs2_right: IOMUXC1_ENET2_RD2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0100 3 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd2_sai_mclk_sai2_mclk: IOMUXC1_ENET2_RD2_SAI_MCLK_SAI2_MCLK { + pinmux = <0x443c0100 2 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3: IOMUXC1_ENET2_RD3_ENET_RGMII_RD_ENET1_RGMII_RD3 { + pinmux = <0x443c0104 0 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_flexio_flexio_flexio2_flexio27: IOMUXC1_ENET2_RD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO27 { + pinmux = <0x443c0104 4 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_gpio_io_gpio4_io27: IOMUXC1_ENET2_RD3_GPIO_IO_GPIO4_IO27 { + pinmux = <0x443c0104 5 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_mqs_left_mqs2_left: IOMUXC1_ENET2_RD3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0104 3 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_in_spdif_in: IOMUXC1_ENET2_RD3_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0104 2 0x443c0454 2 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rd3_spdif_out_spdif_out: IOMUXC1_ENET2_RD3_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c0104 1 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc: IOMUXC1_ENET2_RXC_ENET_RGMII_RXC_ENET1_RGMII_RXC { + pinmux = <0x443c00f4 0 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_enet_rx_er_enet1_rx_er: IOMUXC1_ENET2_RXC_ENET_RX_ER_ENET1_RX_ER { + pinmux = <0x443c00f4 1 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_flexio_flexio_flexio2_flexio23: IOMUXC1_ENET2_RXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO23 { + pinmux = <0x443c00f4 4 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_gpio_io_gpio4_io23: IOMUXC1_ENET2_RXC_GPIO_IO_GPIO4_IO23 { + pinmux = <0x443c00f4 5 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rxc_sai_tx_data_sai2_tx_data01: IOMUXC1_ENET2_RXC_SAI_TX_DATA_SAI2_TX_DATA01 { + pinmux = <0x443c00f4 2 0x0 0 0x443c02a4>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl: IOMUXC1_ENET2_RX_CTL_ENET_RGMII_RX_CTL_ENET1_RGMII_RX_CTL { + pinmux = <0x443c00f0 0 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_flexio_flexio_flexio2_flexio22: IOMUXC1_ENET2_RX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO22 { + pinmux = <0x443c00f0 4 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22: IOMUXC1_ENET2_RX_CTL_GPIO_IO_GPIO4_IO22 { + pinmux = <0x443c00f0 5 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_lpuart_dsr_b_lpuart4_dsr_b: IOMUXC1_ENET2_RX_CTL_LPUART_DSR_B_LPUART4_DSR_B { + pinmux = <0x443c00f0 1 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_rx_ctl_sai_tx_data_sai2_tx_data00: IOMUXC1_ENET2_RX_CTL_SAI_TX_DATA_SAI2_TX_DATA00 { + pinmux = <0x443c00f0 2 0x0 0 0x443c02a0>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0: IOMUXC1_ENET2_TD0_ENET_RGMII_TD_ENET1_RGMII_TD0 { + pinmux = <0x443c00e4 0 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_flexio_flexio_flexio2_flexio19: IOMUXC1_ENET2_TD0_FLEXIO_FLEXIO_FLEXIO2_FLEXIO19 { + pinmux = <0x443c00e4 4 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_gpio_io_gpio4_io19: IOMUXC1_ENET2_TD0_GPIO_IO_GPIO4_IO19 { + pinmux = <0x443c00e4 5 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_lpuart_tx_lpuart4_tx: IOMUXC1_ENET2_TD0_LPUART_TX_LPUART4_TX { + pinmux = <0x443c00e4 1 0x443c0428 1 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td0_sai_rx_data_sai2_rx_data03: IOMUXC1_ENET2_TD0_SAI_RX_DATA_SAI2_RX_DATA03 { + pinmux = <0x443c00e4 2 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1: IOMUXC1_ENET2_TD1_ENET_RGMII_TD_ENET1_RGMII_TD1 { + pinmux = <0x443c00e0 0 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_flexio_flexio_flexio2_flexio18: IOMUXC1_ENET2_TD1_FLEXIO_FLEXIO_FLEXIO2_FLEXIO18 { + pinmux = <0x443c00e0 4 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_gpio_io_gpio4_io18: IOMUXC1_ENET2_TD1_GPIO_IO_GPIO4_IO18 { + pinmux = <0x443c00e0 5 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_ENET2_TD1_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c00e0 1 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td1_sai_rx_data_sai2_rx_data02: IOMUXC1_ENET2_TD1_SAI_RX_DATA_SAI2_RX_DATA02 { + pinmux = <0x443c00e0 2 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2: IOMUXC1_ENET2_TD2_ENET_RGMII_TD_ENET1_RGMII_TD2 { + pinmux = <0x443c00dc 0 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_enet_tx_clk_enet1_tx_clk: IOMUXC1_ENET2_TD2_ENET_TX_CLK_ENET1_TX_CLK { + pinmux = <0x443c00dc 1 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_flexio_flexio_flexio2_flexio17: IOMUXC1_ENET2_TD2_FLEXIO_FLEXIO_FLEXIO2_FLEXIO17 { + pinmux = <0x443c00dc 4 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_gpio_io_gpio4_io17: IOMUXC1_ENET2_TD2_GPIO_IO_GPIO4_IO17 { + pinmux = <0x443c00dc 5 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td2_sai_rx_data_sai2_rx_data01: IOMUXC1_ENET2_TD2_SAI_RX_DATA_SAI2_RX_DATA01 { + pinmux = <0x443c00dc 2 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3: IOMUXC1_ENET2_TD3_ENET_RGMII_TD_ENET1_RGMII_TD3 { + pinmux = <0x443c00d8 0 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_flexio_flexio_flexio2_flexio16: IOMUXC1_ENET2_TD3_FLEXIO_FLEXIO_FLEXIO2_FLEXIO16 { + pinmux = <0x443c00d8 4 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_gpio_io_gpio4_io16: IOMUXC1_ENET2_TD3_GPIO_IO_GPIO4_IO16 { + pinmux = <0x443c00d8 5 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_td3_sai_rx_data_sai2_rx_data00: IOMUXC1_ENET2_TD3_SAI_RX_DATA_SAI2_RX_DATA00 { + pinmux = <0x443c00d8 2 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc: IOMUXC1_ENET2_TXC_ENET_RGMII_TXC_ENET1_RGMII_TXC { + pinmux = <0x443c00ec 0 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_enet_tx_er_enet1_tx_er: IOMUXC1_ENET2_TXC_ENET_TX_ER_ENET1_TX_ER { + pinmux = <0x443c00ec 1 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_flexio_flexio_flexio2_flexio21: IOMUXC1_ENET2_TXC_FLEXIO_FLEXIO_FLEXIO2_FLEXIO21 { + pinmux = <0x443c00ec 4 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_gpio_io_gpio4_io21: IOMUXC1_ENET2_TXC_GPIO_IO_GPIO4_IO21 { + pinmux = <0x443c00ec 5 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC1_ENET2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x443c00ec 2 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl: IOMUXC1_ENET2_TX_CTL_ENET_RGMII_TX_CTL_ENET1_RGMII_TX_CTL { + pinmux = <0x443c00e8 0 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_flexio_flexio_flexio2_flexio20: IOMUXC1_ENET2_TX_CTL_FLEXIO_FLEXIO_FLEXIO2_FLEXIO20 { + pinmux = <0x443c00e8 4 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20: IOMUXC1_ENET2_TX_CTL_GPIO_IO_GPIO4_IO20 { + pinmux = <0x443c00e8 5 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_lpuart_dtr_b_lpuart4_dtr_b: IOMUXC1_ENET2_TX_CTL_LPUART_DTR_B_LPUART4_DTR_B { + pinmux = <0x443c00e8 1 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_enet2_tx_ctl_sai_tx_sync_sai2_tx_sync: IOMUXC1_ENET2_TX_CTL_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x443c00e8 2 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_flexio_flexio_flexio1_flexio00: IOMUXC1_GPIO_IO00_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0010 7 0x443c036c 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_gpio_io_gpio2_io00: IOMUXC1_GPIO_IO00_GPIO_IO_GPIO2_IO00 { + pinmux = <0x443c0010 0 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0010 1 0x443c03e4 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO00_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0010 6 0x443c03ec 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpspi_pcs_lpspi6_pcs0: IOMUXC1_GPIO_IO00_LPSPI_PCS_LPSPI6_PCS0 { + pinmux = <0x443c0010 4 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_lpuart_tx_lpuart5_tx: IOMUXC1_GPIO_IO00_LPUART_TX_LPUART5_TX { + pinmux = <0x443c0010 5 0x443c0434 1 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_cam_clk_mediamix_cam_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_CAM_CLK_MEDIAMIX_CAM_CLK { + pinmux = <0x443c0010 2 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io00_mediamix_disp_clk_mediamix_disp_clk: IOMUXC1_GPIO_IO00_MEDIAMIX_DISP_CLK_MEDIAMIX_DISP_CLK { + pinmux = <0x443c0010 3 0x0 0 0x443c01c0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_flexio_flexio_flexio1_flexio01: IOMUXC1_GPIO_IO01_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0014 7 0x443c0370 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_gpio_io_gpio2_io01: IOMUXC1_GPIO_IO01_GPIO_IO_GPIO2_IO01 { + pinmux = <0x443c0014 0 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0014 1 0x443c03e0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO01_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c0014 6 0x443c03e8 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpspi_sin_lpspi6_sin: IOMUXC1_GPIO_IO01_LPSPI_SIN_LPSPI6_SIN { + pinmux = <0x443c0014 4 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_lpuart_rx_lpuart5_rx: IOMUXC1_GPIO_IO01_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0014 5 0x443c0430 1 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_cam_data_mediamix_cam_data00: IOMUXC1_GPIO_IO01_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA00 { + pinmux = <0x443c0014 2 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io01_mediamix_disp_de_mediamix_disp_de: IOMUXC1_GPIO_IO01_MEDIAMIX_DISP_DE_MEDIAMIX_DISP_DE { + pinmux = <0x443c0014 3 0x0 0 0x443c01c4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_flexio_flexio_flexio1_flexio02: IOMUXC1_GPIO_IO02_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0018 7 0x443c0374 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_gpio_io_gpio2_io02: IOMUXC1_GPIO_IO02_GPIO_IO_GPIO2_IO02 { + pinmux = <0x443c0018 0 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C4_SDA { + pinmux = <0x443c0018 1 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO02_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0018 6 0x443c03f4 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpspi_sout_lpspi6_sout: IOMUXC1_GPIO_IO02_LPSPI_SOUT_LPSPI6_SOUT { + pinmux = <0x443c0018 4 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_lpuart_cts_b_lpuart5_cts_b: IOMUXC1_GPIO_IO02_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0018 5 0x443c042c 1 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_cam_vsync_mediamix_cam_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_CAM_VSYNC_MEDIAMIX_CAM_VSYNC { + pinmux = <0x443c0018 2 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io02_mediamix_disp_vsync_mediamix_disp_vsync: IOMUXC1_GPIO_IO02_MEDIAMIX_DISP_VSYNC_MEDIAMIX_DISP_VSYNC { + pinmux = <0x443c0018 3 0x0 0 0x443c01c8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_flexio_flexio_flexio1_flexio03: IOMUXC1_GPIO_IO03_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c001c 7 0x443c0378 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_gpio_io_gpio2_io03: IOMUXC1_GPIO_IO03_GPIO_IO_GPIO2_IO03 { + pinmux = <0x443c001c 0 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C4_SCL { + pinmux = <0x443c001c 1 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO03_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c001c 6 0x443c03f0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpspi_sck_lpspi6_sck: IOMUXC1_GPIO_IO03_LPSPI_SCK_LPSPI6_SCK { + pinmux = <0x443c001c 4 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_lpuart_rts_b_lpuart5_rts_b: IOMUXC1_GPIO_IO03_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c001c 5 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_cam_hsync_mediamix_cam_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_CAM_HSYNC_MEDIAMIX_CAM_HSYNC { + pinmux = <0x443c001c 2 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io03_mediamix_disp_hsync_mediamix_disp_hsync: IOMUXC1_GPIO_IO03_MEDIAMIX_DISP_HSYNC_MEDIAMIX_DISP_HSYNC { + pinmux = <0x443c001c 3 0x0 0 0x443c01cc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_flexio_flexio_flexio1_flexio04: IOMUXC1_GPIO_IO04_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0020 7 0x443c037c 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_gpio_io_gpio2_io04: IOMUXC1_GPIO_IO04_GPIO_IO_GPIO2_IO04 { + pinmux = <0x443c0020 0 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpi2c_sda_lpi2c6_sda: IOMUXC1_GPIO_IO04_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0020 6 0x443c03f4 1 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpspi_pcs_lpspi7_pcs0: IOMUXC1_GPIO_IO04_LPSPI_PCS_LPSPI7_PCS0 { + pinmux = <0x443c0020 4 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_lpuart_tx_lpuart6_tx: IOMUXC1_GPIO_IO04_LPUART_TX_LPUART6_TX { + pinmux = <0x443c0020 5 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_mediamix_disp_data_mediamix_disp_data00: IOMUXC1_GPIO_IO04_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA00 { + pinmux = <0x443c0020 3 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO04_PDM_CLK_PDM_CLK { + pinmux = <0x443c0020 2 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io04_tpm_ch_tpm3_ch0: IOMUXC1_GPIO_IO04_TPM_CH_TPM3_CH0 { + pinmux = <0x443c0020 1 0x0 0 0x443c01d0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_flexio_flexio_flexio1_flexio05: IOMUXC1_GPIO_IO05_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0024 7 0x443c0380 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_gpio_io_gpio2_io05: IOMUXC1_GPIO_IO05_GPIO_IO_GPIO2_IO05 { + pinmux = <0x443c0024 0 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpi2c_scl_lpi2c6_scl: IOMUXC1_GPIO_IO05_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c0024 6 0x443c03f0 1 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpspi_sin_lpspi7_sin: IOMUXC1_GPIO_IO05_LPSPI_SIN_LPSPI7_SIN { + pinmux = <0x443c0024 4 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_lpuart_rx_lpuart6_rx: IOMUXC1_GPIO_IO05_LPUART_RX_LPUART6_RX { + pinmux = <0x443c0024 5 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_mediamix_disp_data_mediamix_disp_data01: IOMUXC1_GPIO_IO05_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA01 { + pinmux = <0x443c0024 3 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO05_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0024 2 0x443c0438 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io05_tpm_ch_tpm4_ch0: IOMUXC1_GPIO_IO05_TPM_CH_TPM4_CH0 { + pinmux = <0x443c0024 1 0x0 0 0x443c01d4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_flexio_flexio_flexio1_flexio06: IOMUXC1_GPIO_IO06_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0028 7 0x443c0384 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_gpio_io_gpio2_io06: IOMUXC1_GPIO_IO06_GPIO_IO_GPIO2_IO06 { + pinmux = <0x443c0028 0 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO06_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0028 6 0x443c03fc 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpspi_sout_lpspi7_sout: IOMUXC1_GPIO_IO06_LPSPI_SOUT_LPSPI7_SOUT { + pinmux = <0x443c0028 4 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_lpuart_cts_b_lpuart6_cts_b: IOMUXC1_GPIO_IO06_LPUART_CTS_B_LPUART6_CTS_B { + pinmux = <0x443c0028 5 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_mediamix_disp_data_mediamix_disp_data02: IOMUXC1_GPIO_IO06_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA02 { + pinmux = <0x443c0028 3 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO06_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0028 2 0x443c043c 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io06_tpm_ch_tpm5_ch0: IOMUXC1_GPIO_IO06_TPM_CH_TPM5_CH0 { + pinmux = <0x443c0028 1 0x0 0 0x443c01d8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_flexio_flexio_flexio1_flexio07: IOMUXC1_GPIO_IO07_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c002c 7 0x443c0388 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_gpio_io_gpio2_io07: IOMUXC1_GPIO_IO07_GPIO_IO_GPIO2_IO07 { + pinmux = <0x443c002c 0 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO07_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c002c 6 0x443c03f8 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1: IOMUXC1_GPIO_IO07_LPSPI_PCS_LPSPI3_PCS1 { + pinmux = <0x443c002c 1 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpspi_sck_lpspi7_sck: IOMUXC1_GPIO_IO07_LPSPI_SCK_LPSPI7_SCK { + pinmux = <0x443c002c 4 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_lpuart_rts_b_lpuart6_rts_b: IOMUXC1_GPIO_IO07_LPUART_RTS_B_LPUART6_RTS_B { + pinmux = <0x443c002c 5 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_cam_data_mediamix_cam_data01: IOMUXC1_GPIO_IO07_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA01 { + pinmux = <0x443c002c 2 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io07_mediamix_disp_data_mediamix_disp_data03: IOMUXC1_GPIO_IO07_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA03 { + pinmux = <0x443c002c 3 0x0 0 0x443c01dc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_flexio_flexio_flexio1_flexio08: IOMUXC1_GPIO_IO08_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0030 7 0x443c038c 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_gpio_io_gpio2_io08: IOMUXC1_GPIO_IO08_GPIO_IO_GPIO2_IO08 { + pinmux = <0x443c0030 0 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpi2c_sda_lpi2c7_sda: IOMUXC1_GPIO_IO08_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0030 6 0x443c03fc 1 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0: IOMUXC1_GPIO_IO08_LPSPI_PCS_LPSPI3_PCS0 { + pinmux = <0x443c0030 1 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_lpuart_tx_lpuart7_tx: IOMUXC1_GPIO_IO08_LPUART_TX_LPUART7_TX { + pinmux = <0x443c0030 5 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_cam_data_mediamix_cam_data02: IOMUXC1_GPIO_IO08_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA02 { + pinmux = <0x443c0030 2 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_mediamix_disp_data_mediamix_disp_data04: IOMUXC1_GPIO_IO08_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA04 { + pinmux = <0x443c0030 3 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io08_tpm_ch_tpm6_ch0: IOMUXC1_GPIO_IO08_TPM_CH_TPM6_CH0 { + pinmux = <0x443c0030 4 0x0 0 0x443c01e0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_flexio_flexio_flexio1_flexio09: IOMUXC1_GPIO_IO09_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c0034 7 0x443c0390 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_gpio_io_gpio2_io09: IOMUXC1_GPIO_IO09_GPIO_IO_GPIO2_IO09 { + pinmux = <0x443c0034 0 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpi2c_scl_lpi2c7_scl: IOMUXC1_GPIO_IO09_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c0034 6 0x443c03f8 1 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin: IOMUXC1_GPIO_IO09_LPSPI_SIN_LPSPI3_SIN { + pinmux = <0x443c0034 1 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_lpuart_rx_lpuart7_rx: IOMUXC1_GPIO_IO09_LPUART_RX_LPUART7_RX { + pinmux = <0x443c0034 5 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_cam_data_mediamix_cam_data03: IOMUXC1_GPIO_IO09_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA03 { + pinmux = <0x443c0034 2 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_mediamix_disp_data_mediamix_disp_data05: IOMUXC1_GPIO_IO09_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA05 { + pinmux = <0x443c0034 3 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io09_tpm_extclk_tpm3_extclk: IOMUXC1_GPIO_IO09_TPM_EXTCLK_TPM3_EXTCLK { + pinmux = <0x443c0034 4 0x0 0 0x443c01e4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_flexio_flexio_flexio1_flexio10: IOMUXC1_GPIO_IO10_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0038 7 0x443c0394 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_gpio_io_gpio2_io10: IOMUXC1_GPIO_IO10_GPIO_IO_GPIO2_IO10 { + pinmux = <0x443c0038 0 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO10_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0038 6 0x443c0404 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout: IOMUXC1_GPIO_IO10_LPSPI_SOUT_LPSPI3_SOUT { + pinmux = <0x443c0038 1 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_lpuart_cts_b_lpuart7_cts_b: IOMUXC1_GPIO_IO10_LPUART_CTS_B_LPUART7_CTS_B { + pinmux = <0x443c0038 5 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_cam_data_mediamix_cam_data04: IOMUXC1_GPIO_IO10_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA04 { + pinmux = <0x443c0038 2 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_mediamix_disp_data_mediamix_disp_data06: IOMUXC1_GPIO_IO10_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA06 { + pinmux = <0x443c0038 3 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io10_tpm_extclk_tpm4_extclk: IOMUXC1_GPIO_IO10_TPM_EXTCLK_TPM4_EXTCLK { + pinmux = <0x443c0038 4 0x0 0 0x443c01e8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_flexio_flexio_flexio1_flexio11: IOMUXC1_GPIO_IO11_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c003c 7 0x443c0398 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_gpio_io_gpio2_io11: IOMUXC1_GPIO_IO11_GPIO_IO_GPIO2_IO11 { + pinmux = <0x443c003c 0 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO11_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c003c 6 0x443c0400 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck: IOMUXC1_GPIO_IO11_LPSPI_SCK_LPSPI3_SCK { + pinmux = <0x443c003c 1 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_lpuart_rts_b_lpuart7_rts_b: IOMUXC1_GPIO_IO11_LPUART_RTS_B_LPUART7_RTS_B { + pinmux = <0x443c003c 5 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_cam_data_mediamix_cam_data05: IOMUXC1_GPIO_IO11_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA05 { + pinmux = <0x443c003c 2 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_mediamix_disp_data_mediamix_disp_data07: IOMUXC1_GPIO_IO11_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA07 { + pinmux = <0x443c003c 3 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io11_tpm_extclk_tpm5_extclk: IOMUXC1_GPIO_IO11_TPM_EXTCLK_TPM5_EXTCLK { + pinmux = <0x443c003c 4 0x0 0 0x443c01ec>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_gpio_io_gpio2_io12: IOMUXC1_GPIO_IO12_GPIO_IO_GPIO2_IO12 { + pinmux = <0x443c0040 0 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpi2c_sda_lpi2c8_sda: IOMUXC1_GPIO_IO12_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0040 6 0x443c0404 1 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpspi_pcs_lpspi8_pcs0: IOMUXC1_GPIO_IO12_LPSPI_PCS_LPSPI8_PCS0 { + pinmux = <0x443c0040 4 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_lpuart_tx_lpuart8_tx: IOMUXC1_GPIO_IO12_LPUART_TX_LPUART8_TX { + pinmux = <0x443c0040 5 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_mediamix_disp_data_mediamix_disp_data08: IOMUXC1_GPIO_IO12_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA08 { + pinmux = <0x443c0040 3 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO12_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0040 2 0x443c0440 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO12_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c0040 7 0x443c0450 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io12_tpm_ch_tpm3_ch2: IOMUXC1_GPIO_IO12_TPM_CH_TPM3_CH2 { + pinmux = <0x443c0040 1 0x0 0 0x443c01f0>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_flexio_flexio_flexio1_flexio13: IOMUXC1_GPIO_IO13_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c0044 7 0x443c039c 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_gpio_io_gpio2_io13: IOMUXC1_GPIO_IO13_GPIO_IO_GPIO2_IO13 { + pinmux = <0x443c0044 0 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpi2c_scl_lpi2c8_scl: IOMUXC1_GPIO_IO13_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c0044 6 0x443c0400 1 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpspi_sin_lpspi8_sin: IOMUXC1_GPIO_IO13_LPSPI_SIN_LPSPI8_SIN { + pinmux = <0x443c0044 4 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_lpuart_rx_lpuart8_rx: IOMUXC1_GPIO_IO13_LPUART_RX_LPUART8_RX { + pinmux = <0x443c0044 5 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_mediamix_disp_data_mediamix_disp_data09: IOMUXC1_GPIO_IO13_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA09 { + pinmux = <0x443c0044 3 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO13_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c0044 2 0x443c0444 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io13_tpm_ch_tpm4_ch2: IOMUXC1_GPIO_IO13_TPM_CH_TPM4_CH2 { + pinmux = <0x443c0044 1 0x0 0 0x443c01f4>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_flexio_flexio_flexio1_flexio14: IOMUXC1_GPIO_IO14_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0048 7 0x443c03a0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_gpio_io_gpio2_io14: IOMUXC1_GPIO_IO14_GPIO_IO_GPIO2_IO14 { + pinmux = <0x443c0048 0 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpspi_sout_lpspi8_sout: IOMUXC1_GPIO_IO14_LPSPI_SOUT_LPSPI8_SOUT { + pinmux = <0x443c0048 4 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_cts_b_lpuart8_cts_b: IOMUXC1_GPIO_IO14_LPUART_CTS_B_LPUART8_CTS_B { + pinmux = <0x443c0048 5 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart3_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART3_TX { + pinmux = <0x443c0048 1 0x443c041c 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_lpuart_tx_lpuart4_tx: IOMUXC1_GPIO_IO14_LPUART_TX_LPUART4_TX { + pinmux = <0x443c0048 6 0x443c0428 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_cam_data_mediamix_cam_data06: IOMUXC1_GPIO_IO14_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA06 { + pinmux = <0x443c0048 2 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io14_mediamix_disp_data_mediamix_disp_data10: IOMUXC1_GPIO_IO14_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA10 { + pinmux = <0x443c0048 3 0x0 0 0x443c01f8>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_flexio_flexio_flexio1_flexio15: IOMUXC1_GPIO_IO15_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c004c 7 0x443c03a4 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_gpio_io_gpio2_io15: IOMUXC1_GPIO_IO15_GPIO_IO_GPIO2_IO15 { + pinmux = <0x443c004c 0 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpspi_sck_lpspi8_sck: IOMUXC1_GPIO_IO15_LPSPI_SCK_LPSPI8_SCK { + pinmux = <0x443c004c 4 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rts_b_lpuart8_rts_b: IOMUXC1_GPIO_IO15_LPUART_RTS_B_LPUART8_RTS_B { + pinmux = <0x443c004c 5 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart3_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART3_RX { + pinmux = <0x443c004c 1 0x443c0418 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_lpuart_rx_lpuart4_rx: IOMUXC1_GPIO_IO15_LPUART_RX_LPUART4_RX { + pinmux = <0x443c004c 6 0x443c0424 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_cam_data_mediamix_cam_data07: IOMUXC1_GPIO_IO15_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA07 { + pinmux = <0x443c004c 2 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io15_mediamix_disp_data_mediamix_disp_data11: IOMUXC1_GPIO_IO15_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA11 { + pinmux = <0x443c004c 3 0x0 0 0x443c01fc>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_flexio_flexio_flexio1_flexio16: IOMUXC1_GPIO_IO16_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0050 7 0x443c03a8 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_gpio_io_gpio2_io16: IOMUXC1_GPIO_IO16_GPIO_IO_GPIO2_IO16 { + pinmux = <0x443c0050 0 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpspi_pcs_lpspi4_pcs2: IOMUXC1_GPIO_IO16_LPSPI_PCS_LPSPI4_PCS2 { + pinmux = <0x443c0050 5 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart3_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c0050 4 0x443c0414 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_lpuart_cts_b_lpuart4_cts_b: IOMUXC1_GPIO_IO16_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0050 6 0x443c0420 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_mediamix_disp_data_mediamix_disp_data12: IOMUXC1_GPIO_IO16_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA12 { + pinmux = <0x443c0050 3 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_pdm_bit_stream_pdm_bit_stream02: IOMUXC1_GPIO_IO16_PDM_BIT_STREAM_PDM_BIT_STREAM02 { + pinmux = <0x443c0050 2 0x443c0440 1 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk: IOMUXC1_GPIO_IO16_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x443c0050 1 0x0 0 0x443c0200>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_flexio_flexio_flexio1_flexio17: IOMUXC1_GPIO_IO17_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c0054 7 0x443c03ac 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_gpio_io_gpio2_io17: IOMUXC1_GPIO_IO17_GPIO_IO_GPIO2_IO17 { + pinmux = <0x443c0054 0 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpspi_pcs_lpspi4_pcs1: IOMUXC1_GPIO_IO17_LPSPI_PCS_LPSPI4_PCS1 { + pinmux = <0x443c0054 5 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart3_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c0054 4 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_lpuart_rts_b_lpuart4_rts_b: IOMUXC1_GPIO_IO17_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c0054 6 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_cam_data_mediamix_cam_data08: IOMUXC1_GPIO_IO17_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA08 { + pinmux = <0x443c0054 2 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_mediamix_disp_data_mediamix_disp_data13: IOMUXC1_GPIO_IO17_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA13 { + pinmux = <0x443c0054 3 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io17_sai_mclk_sai3_mclk: IOMUXC1_GPIO_IO17_SAI_MCLK_SAI3_MCLK { + pinmux = <0x443c0054 1 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_flexio_flexio_flexio1_flexio18: IOMUXC1_GPIO_IO18_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0058 7 0x443c03b0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_gpio_io_gpio2_io18: IOMUXC1_GPIO_IO18_GPIO_IO_GPIO2_IO18 { + pinmux = <0x443c0058 0 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi4_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI4_PCS0 { + pinmux = <0x443c0058 5 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_lpspi_pcs_lpspi5_pcs0: IOMUXC1_GPIO_IO18_LPSPI_PCS_LPSPI5_PCS0 { + pinmux = <0x443c0058 4 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_cam_data_mediamix_cam_data09: IOMUXC1_GPIO_IO18_MEDIAMIX_CAM_DATA_MEDIAMIX_CAM_DATA09 { + pinmux = <0x443c0058 2 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_mediamix_disp_data_mediamix_disp_data14: IOMUXC1_GPIO_IO18_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA14 { + pinmux = <0x443c0058 3 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO18_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0058 1 0x443c044c 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io18_tpm_ch_tpm5_ch2: IOMUXC1_GPIO_IO18_TPM_CH_TPM5_CH2 { + pinmux = <0x443c0058 6 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_gpio_io_gpio2_io19: IOMUXC1_GPIO_IO19_GPIO_IO_GPIO2_IO19 { + pinmux = <0x443c005c 0 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi4_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI4_SIN { + pinmux = <0x443c005c 5 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_lpspi_sin_lpspi5_sin: IOMUXC1_GPIO_IO19_LPSPI_SIN_LPSPI5_SIN { + pinmux = <0x443c005c 4 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_mediamix_disp_data_mediamix_disp_data15: IOMUXC1_GPIO_IO19_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA15 { + pinmux = <0x443c005c 3 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_pdm_bit_stream_pdm_bit_stream03: IOMUXC1_GPIO_IO19_PDM_BIT_STREAM_PDM_BIT_STREAM03 { + pinmux = <0x443c005c 2 0x443c0444 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_rx_sync_sai3_rx_sync: IOMUXC1_GPIO_IO19_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c005c 1 0x443c0450 1 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO19_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c005c 7 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io19_tpm_ch_tpm6_ch2: IOMUXC1_GPIO_IO19_TPM_CH_TPM6_CH2 { + pinmux = <0x443c005c 6 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_flexio_flexio_flexio1_flexio20: IOMUXC1_GPIO_IO20_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0060 7 0x443c03b4 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_gpio_io_gpio2_io20: IOMUXC1_GPIO_IO20_GPIO_IO_GPIO2_IO20 { + pinmux = <0x443c0060 0 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi4_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI4_SOUT { + pinmux = <0x443c0060 5 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_lpspi_sout_lpspi5_sout: IOMUXC1_GPIO_IO20_LPSPI_SOUT_LPSPI5_SOUT { + pinmux = <0x443c0060 4 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_mediamix_disp_data_mediamix_disp_data16: IOMUXC1_GPIO_IO20_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA16 { + pinmux = <0x443c0060 3 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_GPIO_IO20_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0060 2 0x443c0438 1 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data00: IOMUXC1_GPIO_IO20_SAI_RX_DATA_SAI3_RX_DATA00 { + pinmux = <0x443c0060 1 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io20_tpm_ch_tpm3_ch1: IOMUXC1_GPIO_IO20_TPM_CH_TPM3_CH1 { + pinmux = <0x443c0060 6 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_gpio_io_gpio2_io21: IOMUXC1_GPIO_IO21_GPIO_IO_GPIO2_IO21 { + pinmux = <0x443c0064 0 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi4_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI4_SCK { + pinmux = <0x443c0064 5 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_lpspi_sck_lpspi5_sck: IOMUXC1_GPIO_IO21_LPSPI_SCK_LPSPI5_SCK { + pinmux = <0x443c0064 4 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_mediamix_disp_data_mediamix_disp_data17: IOMUXC1_GPIO_IO21_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA17 { + pinmux = <0x443c0064 3 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_pdm_clk_pdm_clk: IOMUXC1_GPIO_IO21_PDM_CLK_PDM_CLK { + pinmux = <0x443c0064 2 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_rx_bclk_sai3_rx_bclk: IOMUXC1_GPIO_IO21_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0064 7 0x443c044c 1 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_sai_tx_data_sai3_tx_data00: IOMUXC1_GPIO_IO21_SAI_TX_DATA_SAI3_TX_DATA00 { + pinmux = <0x443c0064 1 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io21_tpm_ch_tpm4_ch1: IOMUXC1_GPIO_IO21_TPM_CH_TPM4_CH1 { + pinmux = <0x443c0064 6 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_flexio_flexio_flexio1_flexio22: IOMUXC1_GPIO_IO22_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0068 7 0x443c03b8 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_gpio_io_gpio2_io22: IOMUXC1_GPIO_IO22_GPIO_IO_GPIO2_IO22 { + pinmux = <0x443c0068 0 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_lpi2c_sda_lpi2c5_sda: IOMUXC1_GPIO_IO22_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0068 6 0x443c03ec 1 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_mediamix_disp_data_mediamix_disp_data18: IOMUXC1_GPIO_IO22_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA18 { + pinmux = <0x443c0068 3 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_spdif_in_spdif_in: IOMUXC1_GPIO_IO22_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0068 2 0x443c0454 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_ch_tpm5_ch1: IOMUXC1_GPIO_IO22_TPM_CH_TPM5_CH1 { + pinmux = <0x443c0068 4 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_tpm_extclk_tpm6_extclk: IOMUXC1_GPIO_IO22_TPM_EXTCLK_TPM6_EXTCLK { + pinmux = <0x443c0068 5 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io22_usdhc_clk_usdhc3_clk: IOMUXC1_GPIO_IO22_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0068 1 0x443c0458 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_flexio_flexio_flexio1_flexio23: IOMUXC1_GPIO_IO23_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c006c 7 0x443c03bc 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_gpio_io_gpio2_io23: IOMUXC1_GPIO_IO23_GPIO_IO_GPIO2_IO23 { + pinmux = <0x443c006c 0 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_lpi2c_scl_lpi2c5_scl: IOMUXC1_GPIO_IO23_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c006c 6 0x443c03e8 1 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_mediamix_disp_data_mediamix_disp_data19: IOMUXC1_GPIO_IO23_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA19 { + pinmux = <0x443c006c 3 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_spdif_out_spdif_out: IOMUXC1_GPIO_IO23_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c006c 2 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_tpm_ch_tpm6_ch1: IOMUXC1_GPIO_IO23_TPM_CH_TPM6_CH1 { + pinmux = <0x443c006c 4 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io23_usdhc_cmd_usdhc3_cmd: IOMUXC1_GPIO_IO23_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c006c 1 0x443c045c 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_flexio_flexio_flexio1_flexio24: IOMUXC1_GPIO_IO24_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0070 7 0x443c03c0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_gpio_io_gpio2_io24: IOMUXC1_GPIO_IO24_GPIO_IO_GPIO2_IO24 { + pinmux = <0x443c0070 0 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_jtag_mux_tdo_jtag_mux_tdo: IOMUXC1_GPIO_IO24_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c0070 5 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_lpspi_pcs_lpspi6_pcs1: IOMUXC1_GPIO_IO24_LPSPI_PCS_LPSPI6_PCS1 { + pinmux = <0x443c0070 6 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_mediamix_disp_data_mediamix_disp_data20: IOMUXC1_GPIO_IO24_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA20 { + pinmux = <0x443c0070 3 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_tpm_ch_tpm3_ch3: IOMUXC1_GPIO_IO24_TPM_CH_TPM3_CH3 { + pinmux = <0x443c0070 4 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io24_usdhc_data_usdhc3_data0: IOMUXC1_GPIO_IO24_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0070 1 0x443c0460 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_can_tx_can2_tx: IOMUXC1_GPIO_IO25_CAN_TX_CAN2_TX { + pinmux = <0x443c0074 2 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_flexio_flexio_flexio1_flexio25: IOMUXC1_GPIO_IO25_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c0074 7 0x443c03c4 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_gpio_io_gpio2_io25: IOMUXC1_GPIO_IO25_GPIO_IO_GPIO2_IO25 { + pinmux = <0x443c0074 0 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_jtag_mux_tck_jtag_mux_tck: IOMUXC1_GPIO_IO25_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0074 5 0x443c03d4 1 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_lpspi_pcs_lpspi7_pcs1: IOMUXC1_GPIO_IO25_LPSPI_PCS_LPSPI7_PCS1 { + pinmux = <0x443c0074 6 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_mediamix_disp_data_mediamix_disp_data21: IOMUXC1_GPIO_IO25_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA21 { + pinmux = <0x443c0074 3 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_tpm_ch_tpm4_ch3: IOMUXC1_GPIO_IO25_TPM_CH_TPM4_CH3 { + pinmux = <0x443c0074 4 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io25_usdhc_data_usdhc3_data1: IOMUXC1_GPIO_IO25_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0074 1 0x443c0464 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_gpio_io_gpio2_io26: IOMUXC1_GPIO_IO26_GPIO_IO_GPIO2_IO26 { + pinmux = <0x443c0078 0 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_jtag_mux_tdi_jtag_mux_tdi: IOMUXC1_GPIO_IO26_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0078 5 0x443c03d8 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_lpspi_pcs_lpspi8_pcs1: IOMUXC1_GPIO_IO26_LPSPI_PCS_LPSPI8_PCS1 { + pinmux = <0x443c0078 6 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_mediamix_disp_data_mediamix_disp_data22: IOMUXC1_GPIO_IO26_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA22 { + pinmux = <0x443c0078 3 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_GPIO_IO26_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0078 2 0x443c043c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync: IOMUXC1_GPIO_IO26_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x443c0078 7 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_tpm_ch_tpm5_ch3: IOMUXC1_GPIO_IO26_TPM_CH_TPM5_CH3 { + pinmux = <0x443c0078 4 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io26_usdhc_data_usdhc3_data2: IOMUXC1_GPIO_IO26_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0078 1 0x443c0468 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_can_rx_can2_rx: IOMUXC1_GPIO_IO27_CAN_RX_CAN2_RX { + pinmux = <0x443c007c 2 0x443c0364 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_flexio_flexio_flexio1_flexio27: IOMUXC1_GPIO_IO27_FLEXIO_FLEXIO_FLEXIO1_FLEXIO27 { + pinmux = <0x443c007c 7 0x443c03c8 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_gpio_io_gpio2_io27: IOMUXC1_GPIO_IO27_GPIO_IO_GPIO2_IO27 { + pinmux = <0x443c007c 0 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_jtag_mux_tms_jtag_mux_tms: IOMUXC1_GPIO_IO27_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c007c 5 0x443c03dc 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_lpspi_pcs_lpspi5_pcs1: IOMUXC1_GPIO_IO27_LPSPI_PCS_LPSPI5_PCS1 { + pinmux = <0x443c007c 6 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_mediamix_disp_data_mediamix_disp_data23: IOMUXC1_GPIO_IO27_MEDIAMIX_DISP_DATA_MEDIAMIX_DISP_DATA23 { + pinmux = <0x443c007c 3 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_tpm_ch_tpm6_ch3: IOMUXC1_GPIO_IO27_TPM_CH_TPM6_CH3 { + pinmux = <0x443c007c 4 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io27_usdhc_data_usdhc3_data3: IOMUXC1_GPIO_IO27_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c007c 1 0x443c046c 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_flexio_flexio_flexio1_flexio28: IOMUXC1_GPIO_IO28_FLEXIO_FLEXIO_FLEXIO1_FLEXIO28 { + pinmux = <0x443c0080 7 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_gpio_io_gpio2_io28: IOMUXC1_GPIO_IO28_GPIO_IO_GPIO2_IO28 { + pinmux = <0x443c0080 0 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io28_lpi2c_sda_lpi2c3_sda: IOMUXC1_GPIO_IO28_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0080 1 0x443c03e4 1 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_flexio_flexio_flexio1_flexio29: IOMUXC1_GPIO_IO29_FLEXIO_FLEXIO_FLEXIO1_FLEXIO29 { + pinmux = <0x443c0084 7 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_gpio_io_gpio2_io29: IOMUXC1_GPIO_IO29_GPIO_IO_GPIO2_IO29 { + pinmux = <0x443c0084 0 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_gpio_io29_lpi2c_scl_lpi2c3_scl: IOMUXC1_GPIO_IO29_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0084 1 0x443c03e0 1 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_gpio_io_gpio1_io00: IOMUXC1_I2C1_SCL_GPIO_IO_GPIO1_IO00 { + pinmux = <0x443c0170 5 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_i3c_scl_i3c1_scl: IOMUXC1_I2C1_SCL_I3C_SCL_I3C1_SCL { + pinmux = <0x443c0170 1 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl: IOMUXC1_I2C1_SCL_LPI2C_SCL_LPI2C1_SCL { + pinmux = <0x443c0170 0 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_lpuart_dcb_b_lpuart1_dcb_b: IOMUXC1_I2C1_SCL_LPUART_DCB_B_LPUART1_DCB_B { + pinmux = <0x443c0170 2 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_scl_tpm_ch_tpm2_ch0: IOMUXC1_I2C1_SCL_TPM_CH_TPM2_CH0 { + pinmux = <0x443c0170 3 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_gpio_io_gpio1_io01: IOMUXC1_I2C1_SDA_GPIO_IO_GPIO1_IO01 { + pinmux = <0x443c0174 5 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_i3c_sda_i3c1_sda: IOMUXC1_I2C1_SDA_I3C_SDA_I3C1_SDA { + pinmux = <0x443c0174 1 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda: IOMUXC1_I2C1_SDA_LPI2C_SDA_LPI2C1_SDA { + pinmux = <0x443c0174 0 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_lpuart_rin_b_lpuart1_rin_b: IOMUXC1_I2C1_SDA_LPUART_RIN_B_LPUART1_RIN_B { + pinmux = <0x443c0174 2 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c1_sda_tpm_ch_tpm2_ch1: IOMUXC1_I2C1_SDA_TPM_CH_TPM2_CH1 { + pinmux = <0x443c0174 3 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_gpio_io_gpio1_io02: IOMUXC1_I2C2_SCL_GPIO_IO_GPIO1_IO02 { + pinmux = <0x443c0178 5 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_b_i3c1_pur_b: IOMUXC1_I2C2_SCL_I3C_PUR_B_I3C1_PUR_B { + pinmux = <0x443c0178 6 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_i3c_pur_i3c1_pur: IOMUXC1_I2C2_SCL_I3C_PUR_I3C1_PUR { + pinmux = <0x443c0178 1 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl: IOMUXC1_I2C2_SCL_LPI2C_SCL_LPI2C2_SCL { + pinmux = <0x443c0178 0 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_lpuart_dcb_b_lpuart2_dcb_b: IOMUXC1_I2C2_SCL_LPUART_DCB_B_LPUART2_DCB_B { + pinmux = <0x443c0178 2 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_sai_rx_sync_sai1_rx_sync: IOMUXC1_I2C2_SCL_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x443c0178 4 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_scl_tpm_ch_tpm2_ch2: IOMUXC1_I2C2_SCL_TPM_CH_TPM2_CH2 { + pinmux = <0x443c0178 3 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_gpio_io_gpio1_io03: IOMUXC1_I2C2_SDA_GPIO_IO_GPIO1_IO03 { + pinmux = <0x443c017c 5 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda: IOMUXC1_I2C2_SDA_LPI2C_SDA_LPI2C2_SDA { + pinmux = <0x443c017c 0 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_lpuart_rin_b_lpuart2_rin_b: IOMUXC1_I2C2_SDA_LPUART_RIN_B_LPUART2_RIN_B { + pinmux = <0x443c017c 2 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_sai_rx_bclk_sai1_rx_bclk: IOMUXC1_I2C2_SDA_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x443c017c 4 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_i2c2_sda_tpm_ch_tpm2_ch3: IOMUXC1_I2C2_SDA_TPM_CH_TPM2_CH3 { + pinmux = <0x443c017c 3 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_can_rx_can1_rx: IOMUXC1_PDM_BIT_STREAM0_CAN_RX_CAN1_RX { + pinmux = <0x443c0194 6 0x443c0360 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09: IOMUXC1_PDM_BIT_STREAM0_GPIO_IO_GPIO1_IO09 { + pinmux = <0x443c0194 5 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lpspi_pcs_lpspi1_pcs1: IOMUXC1_PDM_BIT_STREAM0_LPSPI_PCS_LPSPI1_PCS1 { + pinmux = <0x443c0194 2 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_lptmr_alt_lptmr1_alt2: IOMUXC1_PDM_BIT_STREAM0_LPTMR_ALT_LPTMR1_ALT2 { + pinmux = <0x443c0194 4 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_mqs_right_mqs1_right: IOMUXC1_PDM_BIT_STREAM0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c0194 1 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_pdm_bit_stream_pdm_bit_stream00: IOMUXC1_PDM_BIT_STREAM0_PDM_BIT_STREAM_PDM_BIT_STREAM00 { + pinmux = <0x443c0194 0 0x443c0438 2 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream0_tpm_extclk_tpm1_extclk: IOMUXC1_PDM_BIT_STREAM0_TPM_EXTCLK_TPM1_EXTCLK { + pinmux = <0x443c0194 3 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0198 6 0x443c0368 1 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10: IOMUXC1_PDM_BIT_STREAM1_GPIO_IO_GPIO1_IO10 { + pinmux = <0x443c0198 5 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lpspi_pcs_lpspi2_pcs1: IOMUXC1_PDM_BIT_STREAM1_LPSPI_PCS_LPSPI2_PCS1 { + pinmux = <0x443c0198 2 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_lptmr_alt_lptmr1_alt3: IOMUXC1_PDM_BIT_STREAM1_LPTMR_ALT_LPTMR1_ALT3 { + pinmux = <0x443c0198 4 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_nmi_glue_nmi_nmi_glue_nmi: IOMUXC1_PDM_BIT_STREAM1_NMI_GLUE_NMI_NMI_GLUE_NMI { + pinmux = <0x443c0198 1 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_pdm_bit_stream_pdm_bit_stream01: IOMUXC1_PDM_BIT_STREAM1_PDM_BIT_STREAM_PDM_BIT_STREAM01 { + pinmux = <0x443c0198 0 0x443c043c 2 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_bit_stream1_tpm_extclk_tpm2_extclk: IOMUXC1_PDM_BIT_STREAM1_TPM_EXTCLK_TPM2_EXTCLK { + pinmux = <0x443c0198 3 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_can_tx_can1_tx: IOMUXC1_PDM_CLK_CAN_TX_CAN1_TX { + pinmux = <0x443c0190 6 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_gpio_io_gpio1_io08: IOMUXC1_PDM_CLK_GPIO_IO_GPIO1_IO08 { + pinmux = <0x443c0190 5 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_lptmr_alt_lptmr1_alt1: IOMUXC1_PDM_CLK_LPTMR_ALT_LPTMR1_ALT1 { + pinmux = <0x443c0190 4 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_mqs_left_mqs1_left: IOMUXC1_PDM_CLK_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c0190 1 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_pdm_clk_pdm_clk_pdm_clk: IOMUXC1_PDM_CLK_PDM_CLK_PDM_CLK { + pinmux = <0x443c0190 0 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_gpio_io_gpio1_io14: IOMUXC1_SAI1_RXD0_GPIO_IO_GPIO1_IO14 { + pinmux = <0x443c01a8 5 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpspi_sout_lpspi1_sout: IOMUXC1_SAI1_RXD0_LPSPI_SOUT_LPSPI1_SOUT { + pinmux = <0x443c01a8 2 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_lpuart_dsr_b_lpuart2_dsr_b: IOMUXC1_SAI1_RXD0_LPUART_DSR_B_LPUART2_DSR_B { + pinmux = <0x443c01a8 3 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_mqs_right_mqs1_right: IOMUXC1_SAI1_RXD0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c01a8 4 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_mclk_sai1_mclk: IOMUXC1_SAI1_RXD0_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c01a8 1 0x443c0448 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_rxd0_sai_rx_data_sai1_rx_data00: IOMUXC1_SAI1_RXD0_SAI_RX_DATA_SAI1_RX_DATA00 { + pinmux = <0x443c01a8 0 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_can_rx_can1_rx: IOMUXC1_SAI1_TXC_CAN_RX_CAN1_RX { + pinmux = <0x443c01a0 4 0x443c0360 1 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_gpio_io_gpio1_io12: IOMUXC1_SAI1_TXC_GPIO_IO_GPIO1_IO12 { + pinmux = <0x443c01a0 5 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpspi_sin_lpspi1_sin: IOMUXC1_SAI1_TXC_LPSPI_SIN_LPSPI1_SIN { + pinmux = <0x443c01a0 2 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_cts_b_lpuart2_cts_b: IOMUXC1_SAI1_TXC_LPUART_CTS_B_LPUART2_CTS_B { + pinmux = <0x443c01a0 1 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_lpuart_dsr_b_lpuart1_dsr_b: IOMUXC1_SAI1_TXC_LPUART_DSR_B_LPUART1_DSR_B { + pinmux = <0x443c01a0 3 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC1_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x443c01a0 0 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_can_tx_can1_tx: IOMUXC1_SAI1_TXD0_CAN_TX_CAN1_TX { + pinmux = <0x443c01a4 4 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_gpio_io_gpio1_io13: IOMUXC1_SAI1_TXD0_GPIO_IO_GPIO1_IO13 { + pinmux = <0x443c01a4 5 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpspi_sck_lpspi1_sck: IOMUXC1_SAI1_TXD0_LPSPI_SCK_LPSPI1_SCK { + pinmux = <0x443c01a4 2 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_dtr_b_lpuart1_dtr_b: IOMUXC1_SAI1_TXD0_LPUART_DTR_B_LPUART1_DTR_B { + pinmux = <0x443c01a4 3 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_lpuart_rts_b_lpuart2_rts_b: IOMUXC1_SAI1_TXD0_LPUART_RTS_B_LPUART2_RTS_B { + pinmux = <0x443c01a4 1 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txd0_sai_tx_data_sai1_tx_data00: IOMUXC1_SAI1_TXD0_SAI_TX_DATA_SAI1_TX_DATA00 { + pinmux = <0x443c01a4 0 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_gpio_io_gpio1_io11: IOMUXC1_SAI1_TXFS_GPIO_IO_GPIO1_IO11 { + pinmux = <0x443c019c 5 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpspi_pcs_lpspi1_pcs0: IOMUXC1_SAI1_TXFS_LPSPI_PCS_LPSPI1_PCS0 { + pinmux = <0x443c019c 2 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_lpuart_dtr_b_lpuart2_dtr_b: IOMUXC1_SAI1_TXFS_LPUART_DTR_B_LPUART2_DTR_B { + pinmux = <0x443c019c 3 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_mqs_left_mqs1_left: IOMUXC1_SAI1_TXFS_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c019c 4 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_data_sai1_tx_data01: IOMUXC1_SAI1_TXFS_SAI_TX_DATA_SAI1_TX_DATA01 { + pinmux = <0x443c019c 1 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC1_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x443c019c 0 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_flexio_flexio_flexio1_flexio08: IOMUXC1_SD1_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO08 { + pinmux = <0x443c0108 4 0x443c038c 1 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_gpio_io_gpio3_io08: IOMUXC1_SD1_CLK_GPIO_IO_GPIO3_IO08 { + pinmux = <0x443c0108 5 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC1_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x443c0108 0 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_flexio_flexio_flexio1_flexio09: IOMUXC1_SD1_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO09 { + pinmux = <0x443c010c 4 0x443c0390 1 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_gpio_io_gpio3_io09: IOMUXC1_SD1_CMD_GPIO_IO_GPIO3_IO09 { + pinmux = <0x443c010c 5 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC1_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x443c010c 0 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_flexio_flexio_flexio1_flexio10: IOMUXC1_SD1_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO10 { + pinmux = <0x443c0110 4 0x443c0394 1 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_gpio_io_gpio3_io10: IOMUXC1_SD1_DATA0_GPIO_IO_GPIO3_IO10 { + pinmux = <0x443c0110 5 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC1_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x443c0110 0 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_flexio_flexio_flexio1_flexio11: IOMUXC1_SD1_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO11 { + pinmux = <0x443c0114 4 0x443c0398 1 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_gpio_io_gpio3_io11: IOMUXC1_SD1_DATA1_GPIO_IO_GPIO3_IO11 { + pinmux = <0x443c0114 5 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC1_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x443c0114 0 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_flexio_flexio_flexio1_flexio12: IOMUXC1_SD1_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO12 { + pinmux = <0x443c0118 4 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_gpio_io_gpio3_io12: IOMUXC1_SD1_DATA2_GPIO_IO_GPIO3_IO12 { + pinmux = <0x443c0118 5 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC1_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x443c0118 0 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexio_flexio_flexio1_flexio13: IOMUXC1_SD1_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO13 { + pinmux = <0x443c011c 4 0x443c039c 1 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_flexspi_a_ss_b_flexspi1_a_ss1_b: IOMUXC1_SD1_DATA3_FLEXSPI_A_SS_B_FLEXSPI1_A_SS1_B { + pinmux = <0x443c011c 1 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_gpio_io_gpio3_io13: IOMUXC1_SD1_DATA3_GPIO_IO_GPIO3_IO13 { + pinmux = <0x443c011c 5 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC1_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x443c011c 0 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexio_flexio_flexio1_flexio14: IOMUXC1_SD1_DATA4_FLEXIO_FLEXIO_FLEXIO1_FLEXIO14 { + pinmux = <0x443c0120 4 0x443c03a0 1 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_flexspi_a_data_flexspi1_a_data04: IOMUXC1_SD1_DATA4_FLEXSPI_A_DATA_FLEXSPI1_A_DATA04 { + pinmux = <0x443c0120 1 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_gpio_io_gpio3_io14: IOMUXC1_SD1_DATA4_GPIO_IO_GPIO3_IO14 { + pinmux = <0x443c0120 5 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC1_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x443c0120 0 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexio_flexio_flexio1_flexio15: IOMUXC1_SD1_DATA5_FLEXIO_FLEXIO_FLEXIO1_FLEXIO15 { + pinmux = <0x443c0124 4 0x443c03a4 1 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_flexspi_a_data_flexspi1_a_data05: IOMUXC1_SD1_DATA5_FLEXSPI_A_DATA_FLEXSPI1_A_DATA05 { + pinmux = <0x443c0124 1 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_gpio_io_gpio3_io15: IOMUXC1_SD1_DATA5_GPIO_IO_GPIO3_IO15 { + pinmux = <0x443c0124 5 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC1_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x443c0124 0 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data5_usdhc_reset_b_usdhc1_reset_b: IOMUXC1_SD1_DATA5_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x443c0124 2 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexio_flexio_flexio1_flexio16: IOMUXC1_SD1_DATA6_FLEXIO_FLEXIO_FLEXIO1_FLEXIO16 { + pinmux = <0x443c0128 4 0x443c03a8 1 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_flexspi_a_data_flexspi1_a_data06: IOMUXC1_SD1_DATA6_FLEXSPI_A_DATA_FLEXSPI1_A_DATA06 { + pinmux = <0x443c0128 1 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_gpio_io_gpio3_io16: IOMUXC1_SD1_DATA6_GPIO_IO_GPIO3_IO16 { + pinmux = <0x443c0128 5 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_cd_b_usdhc1_cd_b: IOMUXC1_SD1_DATA6_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x443c0128 2 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC1_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x443c0128 0 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexio_flexio_flexio1_flexio17: IOMUXC1_SD1_DATA7_FLEXIO_FLEXIO_FLEXIO1_FLEXIO17 { + pinmux = <0x443c012c 4 0x443c03ac 1 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_flexspi_a_data_flexspi1_a_data07: IOMUXC1_SD1_DATA7_FLEXSPI_A_DATA_FLEXSPI1_A_DATA07 { + pinmux = <0x443c012c 1 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_gpio_io_gpio3_io17: IOMUXC1_SD1_DATA7_GPIO_IO_GPIO3_IO17 { + pinmux = <0x443c012c 5 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC1_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x443c012c 0 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_data7_usdhc_wp_usdhc1_wp: IOMUXC1_SD1_DATA7_USDHC_WP_USDHC1_WP { + pinmux = <0x443c012c 2 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexio_flexio_flexio1_flexio18: IOMUXC1_SD1_STROBE_FLEXIO_FLEXIO_FLEXIO1_FLEXIO18 { + pinmux = <0x443c0130 4 0x443c03b0 1 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_flexspi_a_dqs_flexspi1_a_dqs: IOMUXC1_SD1_STROBE_FLEXSPI_A_DQS_FLEXSPI1_A_DQS { + pinmux = <0x443c0130 1 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_gpio_io_gpio3_io18: IOMUXC1_SD1_STROBE_GPIO_IO_GPIO3_IO18 { + pinmux = <0x443c0130 5 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC1_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x443c0130 0 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_enet_qos_1588_event0_in_enet_qos_1588_event0_in: IOMUXC1_SD2_CD_B_ENET_QOS_1588_EVENT0_IN_ENET_QOS_1588_EVENT0_IN { + pinmux = <0x443c0150 1 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_flexio_flexio_flexio1_flexio00: IOMUXC1_SD2_CD_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO00 { + pinmux = <0x443c0150 4 0x443c036c 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_gpio_io_gpio3_io00: IOMUXC1_SD2_CD_B_GPIO_IO_GPIO3_IO00 { + pinmux = <0x443c0150 5 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_i3c_scl_i3c2_scl: IOMUXC1_SD2_CD_B_I3C_SCL_I3C2_SCL { + pinmux = <0x443c0150 2 0x443c03cc 1 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC1_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x443c0150 0 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe0: IOMUXC1_SD2_CLK_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE0 { + pinmux = <0x443c0154 6 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_enet_qos_1588_event0_out_enet_qos_1588_event0_out: IOMUXC1_SD2_CLK_ENET_QOS_1588_EVENT0_OUT_ENET_QOS_1588_EVENT0_OUT { + pinmux = <0x443c0154 1 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_flexio_flexio_flexio1_flexio01: IOMUXC1_SD2_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO01 { + pinmux = <0x443c0154 4 0x443c0370 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_gpio_io_gpio3_io01: IOMUXC1_SD2_CLK_GPIO_IO_GPIO3_IO01 { + pinmux = <0x443c0154 5 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_i3c_sda_i3c2_sda: IOMUXC1_SD2_CLK_I3C_SDA_I3C2_SDA { + pinmux = <0x443c0154 2 0x443c03d0 1 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC1_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x443c0154 0 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe1: IOMUXC1_SD2_CMD_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE1 { + pinmux = <0x443c0158 6 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_enet1_1588_event0_in_enet1_1588_event0_in: IOMUXC1_SD2_CMD_ENET1_1588_EVENT0_IN_ENET1_1588_EVENT0_IN { + pinmux = <0x443c0158 1 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_flexio_flexio_flexio1_flexio02: IOMUXC1_SD2_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO02 { + pinmux = <0x443c0158 4 0x443c0374 1 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_gpio_io_gpio3_io02: IOMUXC1_SD2_CMD_GPIO_IO_GPIO3_IO02 { + pinmux = <0x443c0158 5 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_b_i3c2_pur_b: IOMUXC1_SD2_CMD_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c0158 3 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_i3c_pur_i3c2_pur: IOMUXC1_SD2_CMD_I3C_PUR_I3C2_PUR { + pinmux = <0x443c0158 2 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC1_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x443c0158 0 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_can_tx_can2_tx: IOMUXC1_SD2_DATA0_CAN_TX_CAN2_TX { + pinmux = <0x443c015c 2 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe2: IOMUXC1_SD2_DATA0_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE2 { + pinmux = <0x443c015c 6 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_enet1_1588_event0_out_enet1_1588_event0_out: IOMUXC1_SD2_DATA0_ENET1_1588_EVENT0_OUT_ENET1_1588_EVENT0_OUT { + pinmux = <0x443c015c 1 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_flexio_flexio_flexio1_flexio03: IOMUXC1_SD2_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO03 { + pinmux = <0x443c015c 4 0x443c0378 1 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_gpio_io_gpio3_io03: IOMUXC1_SD2_DATA0_GPIO_IO_GPIO3_IO03 { + pinmux = <0x443c015c 5 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC1_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x443c015c 0 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_can_rx_can2_rx: IOMUXC1_SD2_DATA1_CAN_RX_CAN2_RX { + pinmux = <0x443c0160 2 0x443c0364 3 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_enet1_1588_event1_in_enet1_1588_event1_in: IOMUXC1_SD2_DATA1_ENET1_1588_EVENT1_IN_ENET1_1588_EVENT1_IN { + pinmux = <0x443c0160 1 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_flexio_flexio_flexio1_flexio04: IOMUXC1_SD2_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO04 { + pinmux = <0x443c0160 4 0x443c037c 1 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_gpio_io_gpio3_io04: IOMUXC1_SD2_DATA1_GPIO_IO_GPIO3_IO04 { + pinmux = <0x443c0160 5 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC1_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x443c0160 0 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_enet1_1588_event1_out_enet1_1588_event1_out: IOMUXC1_SD2_DATA2_ENET1_1588_EVENT1_OUT_ENET1_1588_EVENT1_OUT { + pinmux = <0x443c0164 1 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_flexio_flexio_flexio1_flexio05: IOMUXC1_SD2_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO05 { + pinmux = <0x443c0164 4 0x443c0380 1 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_gpio_io_gpio3_io05: IOMUXC1_SD2_DATA2_GPIO_IO_GPIO3_IO05 { + pinmux = <0x443c0164 5 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_mqs_right_mqs2_right: IOMUXC1_SD2_DATA2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0164 2 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC1_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x443c0164 0 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_flexio_flexio_flexio1_flexio06: IOMUXC1_SD2_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO06 { + pinmux = <0x443c0168 4 0x443c0384 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_gpio_io_gpio3_io06: IOMUXC1_SD2_DATA3_GPIO_IO_GPIO3_IO06 { + pinmux = <0x443c0168 5 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_lptmr_alt_lptmr2_alt1: IOMUXC1_SD2_DATA3_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c0168 1 0x443c0408 1 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_mqs_left_mqs2_left: IOMUXC1_SD2_DATA3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0168 2 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC1_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x443c0168 0 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_ccmsrcgpcmix_system_reset_ccmsrcgpcmix_system_reset: IOMUXC1_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET_CCMSRCGPCMIX_SYSTEM_RESET { + pinmux = <0x443c016c 6 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_flexio_flexio_flexio1_flexio07: IOMUXC1_SD2_RESET_B_FLEXIO_FLEXIO_FLEXIO1_FLEXIO07 { + pinmux = <0x443c016c 4 0x443c0388 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_gpio_io_gpio3_io07: IOMUXC1_SD2_RESET_B_GPIO_IO_GPIO3_IO07 { + pinmux = <0x443c016c 5 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_lptmr_alt_lptmr2_alt2: IOMUXC1_SD2_RESET_B_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c016c 1 0x443c040c 1 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC1_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x443c016c 0 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_ccmsrcgpcmix_ext_clk_ccmsrcgpcmix_ext_clk1: IOMUXC1_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK_CCMSRCGPCMIX_EXT_CLK1 { + pinmux = <0x443c0134 6 0x443c0368 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_flexio_flexio_flexio1_flexio19: IOMUXC1_SD2_VSELECT_FLEXIO_FLEXIO_FLEXIO1_FLEXIO19 { + pinmux = <0x443c0134 4 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_gpio_io_gpio3_io19: IOMUXC1_SD2_VSELECT_GPIO_IO_GPIO3_IO19 { + pinmux = <0x443c0134 5 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_lptmr_alt_lptmr2_alt3: IOMUXC1_SD2_VSELECT_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c0134 2 0x443c0410 1 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect: IOMUXC1_SD2_VSELECT_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x443c0134 0 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd2_vselect_usdhc_wp_usdhc2_wp: IOMUXC1_SD2_VSELECT_USDHC_WP_USDHC2_WP { + pinmux = <0x443c0134 1 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexio_flexio_flexio1_flexio20: IOMUXC1_SD3_CLK_FLEXIO_FLEXIO_FLEXIO1_FLEXIO20 { + pinmux = <0x443c0138 4 0x443c03b4 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_flexspi_a_sclk_flexspi1_a_sclk: IOMUXC1_SD3_CLK_FLEXSPI_A_SCLK_FLEXSPI1_A_SCLK { + pinmux = <0x443c0138 1 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_gpio_io_gpio3_io20: IOMUXC1_SD3_CLK_GPIO_IO_GPIO3_IO20 { + pinmux = <0x443c0138 5 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_clk_usdhc_clk_usdhc3_clk: IOMUXC1_SD3_CLK_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0138 0 0x443c0458 1 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexio_flexio_flexio1_flexio21: IOMUXC1_SD3_CMD_FLEXIO_FLEXIO_FLEXIO1_FLEXIO21 { + pinmux = <0x443c013c 4 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_flexspi_a_ss_b_flexspi1_a_ss0_b: IOMUXC1_SD3_CMD_FLEXSPI_A_SS_B_FLEXSPI1_A_SS0_B { + pinmux = <0x443c013c 1 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_gpio_io_gpio3_io21: IOMUXC1_SD3_CMD_GPIO_IO_GPIO3_IO21 { + pinmux = <0x443c013c 5 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_cmd_usdhc_cmd_usdhc3_cmd: IOMUXC1_SD3_CMD_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c013c 0 0x443c045c 1 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexio_flexio_flexio1_flexio22: IOMUXC1_SD3_DATA0_FLEXIO_FLEXIO_FLEXIO1_FLEXIO22 { + pinmux = <0x443c0140 4 0x443c03b8 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_flexspi_a_data_flexspi1_a_data00: IOMUXC1_SD3_DATA0_FLEXSPI_A_DATA_FLEXSPI1_A_DATA00 { + pinmux = <0x443c0140 1 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_gpio_io_gpio3_io22: IOMUXC1_SD3_DATA0_GPIO_IO_GPIO3_IO22 { + pinmux = <0x443c0140 5 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data0_usdhc_data_usdhc3_data0: IOMUXC1_SD3_DATA0_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0140 0 0x443c0460 1 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexio_flexio_flexio1_flexio23: IOMUXC1_SD3_DATA1_FLEXIO_FLEXIO_FLEXIO1_FLEXIO23 { + pinmux = <0x443c0144 4 0x443c03bc 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_flexspi_a_data_flexspi1_a_data01: IOMUXC1_SD3_DATA1_FLEXSPI_A_DATA_FLEXSPI1_A_DATA01 { + pinmux = <0x443c0144 1 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_gpio_io_gpio3_io23: IOMUXC1_SD3_DATA1_GPIO_IO_GPIO3_IO23 { + pinmux = <0x443c0144 5 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data1_usdhc_data_usdhc3_data1: IOMUXC1_SD3_DATA1_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0144 0 0x443c0464 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexio_flexio_flexio1_flexio24: IOMUXC1_SD3_DATA2_FLEXIO_FLEXIO_FLEXIO1_FLEXIO24 { + pinmux = <0x443c0148 4 0x443c03c0 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_flexspi_a_data_flexspi1_a_data02: IOMUXC1_SD3_DATA2_FLEXSPI_A_DATA_FLEXSPI1_A_DATA02 { + pinmux = <0x443c0148 1 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_gpio_io_gpio3_io24: IOMUXC1_SD3_DATA2_GPIO_IO_GPIO3_IO24 { + pinmux = <0x443c0148 5 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data2_usdhc_data_usdhc3_data2: IOMUXC1_SD3_DATA2_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0148 0 0x443c0468 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexio_flexio_flexio1_flexio25: IOMUXC1_SD3_DATA3_FLEXIO_FLEXIO_FLEXIO1_FLEXIO25 { + pinmux = <0x443c014c 4 0x443c03c4 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_flexspi_a_data_flexspi1_a_data03: IOMUXC1_SD3_DATA3_FLEXSPI_A_DATA_FLEXSPI1_A_DATA03 { + pinmux = <0x443c014c 1 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_gpio_io_gpio3_io25: IOMUXC1_SD3_DATA3_GPIO_IO_GPIO3_IO25 { + pinmux = <0x443c014c 5 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_sd3_data3_usdhc_data_usdhc3_data3: IOMUXC1_SD3_DATA3_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c014c 0 0x443c046c 1 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_gpio_io_gpio1_io04: IOMUXC1_UART1_RXD_GPIO_IO_GPIO1_IO04 { + pinmux = <0x443c0180 5 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpspi_sin_lpspi2_sin: IOMUXC1_UART1_RXD_LPSPI_SIN_LPSPI2_SIN { + pinmux = <0x443c0180 2 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx: IOMUXC1_UART1_RXD_LPUART_RX_LPUART1_RX { + pinmux = <0x443c0180 0 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_s400_uart_rx_s400_uart_rx: IOMUXC1_UART1_RXD_S400_UART_RX_S400_UART_RX { + pinmux = <0x443c0180 1 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_rxd_tpm_ch_tpm1_ch0: IOMUXC1_UART1_RXD_TPM_CH_TPM1_CH0 { + pinmux = <0x443c0180 3 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_gpio_io_gpio1_io05: IOMUXC1_UART1_TXD_GPIO_IO_GPIO1_IO05 { + pinmux = <0x443c0184 5 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpspi_pcs_lpspi2_pcs0: IOMUXC1_UART1_TXD_LPSPI_PCS_LPSPI2_PCS0 { + pinmux = <0x443c0184 2 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx: IOMUXC1_UART1_TXD_LPUART_TX_LPUART1_TX { + pinmux = <0x443c0184 0 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_s400_uart_tx_s400_uart_tx: IOMUXC1_UART1_TXD_S400_UART_TX_S400_UART_TX { + pinmux = <0x443c0184 1 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart1_txd_tpm_ch_tpm1_ch1: IOMUXC1_UART1_TXD_TPM_CH_TPM1_CH1 { + pinmux = <0x443c0184 3 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_gpio_io_gpio1_io06: IOMUXC1_UART2_RXD_GPIO_IO_GPIO1_IO06 { + pinmux = <0x443c0188 5 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpspi_sout_lpspi2_sout: IOMUXC1_UART2_RXD_LPSPI_SOUT_LPSPI2_SOUT { + pinmux = <0x443c0188 2 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_cts_b_lpuart1_cts_b: IOMUXC1_UART2_RXD_LPUART_CTS_B_LPUART1_CTS_B { + pinmux = <0x443c0188 1 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx: IOMUXC1_UART2_RXD_LPUART_RX_LPUART2_RX { + pinmux = <0x443c0188 0 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_sai_mclk_sai1_mclk: IOMUXC1_UART2_RXD_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c0188 4 0x443c0448 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_rxd_tpm_ch_tpm1_ch2: IOMUXC1_UART2_RXD_TPM_CH_TPM1_CH2 { + pinmux = <0x443c0188 3 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_gpio_io_gpio1_io07: IOMUXC1_UART2_TXD_GPIO_IO_GPIO1_IO07 { + pinmux = <0x443c018c 5 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpspi_sck_lpspi2_sck: IOMUXC1_UART2_TXD_LPSPI_SCK_LPSPI2_SCK { + pinmux = <0x443c018c 2 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_rts_b_lpuart1_rts_b: IOMUXC1_UART2_TXD_LPUART_RTS_B_LPUART1_RTS_B { + pinmux = <0x443c018c 1 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx: IOMUXC1_UART2_TXD_LPUART_TX_LPUART2_TX { + pinmux = <0x443c018c 0 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_uart2_txd_tpm_ch_tpm1_ch3: IOMUXC1_UART2_TXD_TPM_CH_TPM1_CH3 { + pinmux = <0x443c018c 3 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_gpio_io_gpio1_io15: IOMUXC1_WDOG_ANY_GPIO_IO_GPIO1_IO15 { + pinmux = <0x443c01ac 5 0x0 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc1_wdog_any_wdog_wdog_any_wdog1_wdog_any: IOMUXC1_WDOG_ANY_WDOG_WDOG_ANY_WDOG1_WDOG_ANY { + pinmux = <0x443c01ac 0 0x0 0 0x443c035c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/mimx9596cvtxn-pinctrl.dtsi b/dts/nxp/nxp_imx/mimx9596cvtxn-pinctrl.dtsi new file mode 100644 index 000000000..38aba2f26 --- /dev/null +++ b/dts/nxp/nxp_imx/mimx9596cvtxn-pinctrl.dtsi @@ -0,0 +1,2167 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMX9596CVTXN + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_ccm_clko1_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko1: IOMUXC_CCM_CLKO1_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO1 { + pinmux = <0x443c00a8 0 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko1_flexio_flexio_bit_flexio1_flexio_bit26: IOMUXC_CCM_CLKO1_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT26 { + pinmux = <0x443c00a8 4 0x443c0458 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko1_gpio_io_bit_gpio3_io_bit26: IOMUXC_CCM_CLKO1_GPIO_IO_BIT_GPIO3_IO_BIT26 { + pinmux = <0x443c00a8 5 0x0 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko1_netc_tmr_1588_trig1_netc_tmr_1588_trig1: IOMUXC_CCM_CLKO1_NETC_TMR_1588_TRIG1_NETC_TMR_1588_TRIG1 { + pinmux = <0x443c00a8 1 0x443c0434 0 0x443c02ac>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko2_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko2: IOMUXC_CCM_CLKO2_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO2 { + pinmux = <0x443c00ac 0 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko2_flexio_flexio_bit_flexio1_flexio_bit27: IOMUXC_CCM_CLKO2_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT27 { + pinmux = <0x443c00ac 4 0x443c045c 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko2_gpio_io_bit_gpio3_io_bit27: IOMUXC_CCM_CLKO2_GPIO_IO_BIT_GPIO3_IO_BIT27 { + pinmux = <0x443c00ac 5 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko2_netc_tmr_1588_pp1_netc_tmr_1588_pp1: IOMUXC_CCM_CLKO2_NETC_TMR_1588_PP1_NETC_TMR_1588_PP1 { + pinmux = <0x443c00ac 1 0x0 0 0x443c02b0>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko3_can_tx_can3_tx: IOMUXC_CCM_CLKO3_CAN_TX_CAN3_TX { + pinmux = <0x443c00b0 2 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko3_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko3: IOMUXC_CCM_CLKO3_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO3 { + pinmux = <0x443c00b0 0 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko3_flexio_flexio_bit_flexio2_flexio_bit28: IOMUXC_CCM_CLKO3_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT28 { + pinmux = <0x443c00b0 4 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko3_gpio_io_bit_gpio4_io_bit28: IOMUXC_CCM_CLKO3_GPIO_IO_BIT_GPIO4_IO_BIT28 { + pinmux = <0x443c00b0 5 0x0 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko3_netc_tmr_1588_trig2_netc_tmr_1588_trig2: IOMUXC_CCM_CLKO3_NETC_TMR_1588_TRIG2_NETC_TMR_1588_TRIG2 { + pinmux = <0x443c00b0 1 0x443c0438 0 0x443c02b4>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko4_can_rx_can3_rx: IOMUXC_CCM_CLKO4_CAN_RX_CAN3_RX { + pinmux = <0x443c00b4 2 0x443c0448 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko4_ccmsrcgpcmix_clko_ccmsrcgpcmix_clko4: IOMUXC_CCM_CLKO4_CCMSRCGPCMIX_CLKO_CCMSRCGPCMIX_CLKO4 { + pinmux = <0x443c00b4 0 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko4_flexio_flexio_bit_flexio2_flexio_bit29: IOMUXC_CCM_CLKO4_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT29 { + pinmux = <0x443c00b4 4 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko4_gpio_io_bit_gpio4_io_bit29: IOMUXC_CCM_CLKO4_GPIO_IO_BIT_GPIO4_IO_BIT29 { + pinmux = <0x443c00b4 5 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc_ccm_clko4_netc_tmr_1588_pp2_netc_tmr_1588_pp2: IOMUXC_CCM_CLKO4_NETC_TMR_1588_PP2_NETC_TMR_1588_PP2 { + pinmux = <0x443c00b4 1 0x0 0 0x443c02b8>; + }; + /omit-if-no-ref/ iomuxc_dap_tclk_swclk_can_rx_can4_rx: IOMUXC_DAP_TCLK_SWCLK_CAN_RX_CAN4_RX { + pinmux = <0x443c0008 2 0x443c044c 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc_dap_tclk_swclk_flexio_flexio_bit_flexio1_flexio_bit30: IOMUXC_DAP_TCLK_SWCLK_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT30 { + pinmux = <0x443c0008 4 0x443c0460 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc_dap_tclk_swclk_gpio_io_bit_gpio3_io_bit30: IOMUXC_DAP_TCLK_SWCLK_GPIO_IO_BIT_GPIO3_IO_BIT30 { + pinmux = <0x443c0008 5 0x0 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc_dap_tclk_swclk_jtag_mux_tck_jtag_mux_tck: IOMUXC_DAP_TCLK_SWCLK_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0008 0 0x443c060c 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc_dap_tclk_swclk_lpuart_cts_b_lpuart5_cts_b: IOMUXC_DAP_TCLK_SWCLK_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0008 6 0x443c056c 0 0x443c020c>; + }; + /omit-if-no-ref/ iomuxc_dap_tdi_can_tx_can2_tx: IOMUXC_DAP_TDI_CAN_TX_CAN2_TX { + pinmux = <0x443c0000 3 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc_dap_tdi_flexio_flexio_bit_flexio2_flexio_bit30: IOMUXC_DAP_TDI_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT30 { + pinmux = <0x443c0000 4 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc_dap_tdi_gpio_io_bit_gpio3_io_bit28: IOMUXC_DAP_TDI_GPIO_IO_BIT_GPIO3_IO_BIT28 { + pinmux = <0x443c0000 5 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc_dap_tdi_jtag_mux_tdi_jtag_mux_tdi: IOMUXC_DAP_TDI_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0000 0 0x443c0610 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc_dap_tdi_lpuart_rx_lpuart5_rx: IOMUXC_DAP_TDI_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0000 6 0x443c0570 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc_dap_tdi_mqs_left_mqs2_left: IOMUXC_DAP_TDI_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0000 1 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc_dap_tdi_netc_tmr_1588_alarm1_netc_tmr_1588_alarm1: IOMUXC_DAP_TDI_NETC_TMR_1588_ALARM1_NETC_TMR_1588_ALARM1 { + pinmux = <0x443c0000 2 0x0 0 0x443c0204>; + }; + /omit-if-no-ref/ iomuxc_dap_tdo_traceswo_can_rx_can2_rx: IOMUXC_DAP_TDO_TRACESWO_CAN_RX_CAN2_RX { + pinmux = <0x443c000c 3 0x443c0444 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc_dap_tdo_traceswo_flexio_flexio_bit_flexio1_flexio_bit31: IOMUXC_DAP_TDO_TRACESWO_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT31 { + pinmux = <0x443c000c 4 0x443c0464 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc_dap_tdo_traceswo_gpio_io_bit_gpio3_io_bit31: IOMUXC_DAP_TDO_TRACESWO_GPIO_IO_BIT_GPIO3_IO_BIT31 { + pinmux = <0x443c000c 5 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc_dap_tdo_traceswo_jtag_mux_tdo_jtag_mux_tdo: IOMUXC_DAP_TDO_TRACESWO_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c000c 0 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc_dap_tdo_traceswo_lpuart_tx_lpuart5_tx: IOMUXC_DAP_TDO_TRACESWO_LPUART_TX_LPUART5_TX { + pinmux = <0x443c000c 6 0x443c0574 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc_dap_tdo_traceswo_mqs_right_mqs2_right: IOMUXC_DAP_TDO_TRACESWO_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c000c 1 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc_dap_tdo_traceswo_netc_tmr_1588_alarm2_netc_tmr_1588_alarm2: IOMUXC_DAP_TDO_TRACESWO_NETC_TMR_1588_ALARM2_NETC_TMR_1588_ALARM2 { + pinmux = <0x443c000c 2 0x0 0 0x443c0210>; + }; + /omit-if-no-ref/ iomuxc_dap_tms_swdio_can_tx_can4_tx: IOMUXC_DAP_TMS_SWDIO_CAN_TX_CAN4_TX { + pinmux = <0x443c0004 2 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc_dap_tms_swdio_flexio_flexio_bit_flexio2_flexio_bit31: IOMUXC_DAP_TMS_SWDIO_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT31 { + pinmux = <0x443c0004 4 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc_dap_tms_swdio_gpio_io_bit_gpio3_io_bit29: IOMUXC_DAP_TMS_SWDIO_GPIO_IO_BIT_GPIO3_IO_BIT29 { + pinmux = <0x443c0004 5 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc_dap_tms_swdio_jtag_mux_tms_jtag_mux_tms: IOMUXC_DAP_TMS_SWDIO_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c0004 0 0x443c0614 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc_dap_tms_swdio_lpuart_rts_b_lpuart5_rts_b: IOMUXC_DAP_TMS_SWDIO_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c0004 6 0x0 0 0x443c0208>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdc_flexio_flexio_bit_flexio2_flexio_bit0: IOMUXC_ENET1_MDC_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT0 { + pinmux = <0x443c00b8 4 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdc_gpio_io_bit_gpio4_io_bit0: IOMUXC_ENET1_MDC_GPIO_IO_BIT_GPIO4_IO_BIT0 { + pinmux = <0x443c00b8 5 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdc_i3c_scl_i3c2_scl: IOMUXC_ENET1_MDC_I3C_SCL_I3C2_SCL { + pinmux = <0x443c00b8 2 0x443c04f8 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdc_lpuart_dcd_b_lpuart3_dcd_b: IOMUXC_ENET1_MDC_LPUART_DCD_B_LPUART3_DCD_B { + pinmux = <0x443c00b8 1 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdc_netc_mdc_netc_mdc: IOMUXC_ENET1_MDC_NETC_MDC_NETC_MDC { + pinmux = <0x443c00b8 0 0x443c0424 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdc_usb_otg_id_usb1_otg_id: IOMUXC_ENET1_MDC_USB_OTG_ID_USB1_OTG_ID { + pinmux = <0x443c00b8 3 0x0 0 0x443c02bc>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdio_flexio_flexio_bit_flexio2_flexio_bit1: IOMUXC_ENET1_MDIO_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT1 { + pinmux = <0x443c00bc 4 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdio_gpio_io_bit_gpio4_io_bit1: IOMUXC_ENET1_MDIO_GPIO_IO_BIT_GPIO4_IO_BIT1 { + pinmux = <0x443c00bc 5 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdio_i3c_sda_i3c2_sda: IOMUXC_ENET1_MDIO_I3C_SDA_I3C2_SDA { + pinmux = <0x443c00bc 2 0x443c04fc 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdio_lpuart_rin_b_lpuart3_rin_b: IOMUXC_ENET1_MDIO_LPUART_RIN_B_LPUART3_RIN_B { + pinmux = <0x443c00bc 1 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdio_netc_mdio_netc_mdio: IOMUXC_ENET1_MDIO_NETC_MDIO_NETC_MDIO { + pinmux = <0x443c00bc 0 0x443c0428 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc_enet1_mdio_usb_otg_pwr_usb1_otg_pwr: IOMUXC_ENET1_MDIO_USB_OTG_PWR_USB1_OTG_PWR { + pinmux = <0x443c00bc 3 0x0 0 0x443c02c0>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd0_eth_rgmii_rd_eth0_rgmii_rd0: IOMUXC_ENET1_RD0_ETH_RGMII_RD_ETH0_RGMII_RD0 { + pinmux = <0x443c00e0 0 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd0_eth_rmii_rxd_eth0_rmii_rxd0: IOMUXC_ENET1_RD0_ETH_RMII_RXD_ETH0_RMII_RXD0 { + pinmux = <0x443c00e0 2 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd0_flexio_flexio_bit_flexio2_flexio_bit10: IOMUXC_ENET1_RD0_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT10 { + pinmux = <0x443c00e0 4 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd0_gpio_io_bit_gpio4_io_bit10: IOMUXC_ENET1_RD0_GPIO_IO_BIT_GPIO4_IO_BIT10 { + pinmux = <0x443c00e0 5 0x0 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd0_lpuart_rx_lpuart3_rx: IOMUXC_ENET1_RD0_LPUART_RX_LPUART3_RX { + pinmux = <0x443c00e0 1 0x443c0558 0 0x443c02e4>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd1_eth_rgmii_rd_eth0_rgmii_rd1: IOMUXC_ENET1_RD1_ETH_RGMII_RD_ETH0_RGMII_RD1 { + pinmux = <0x443c00e4 0 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd1_eth_rmii_rxd_eth0_rmii_rxd1: IOMUXC_ENET1_RD1_ETH_RMII_RXD_ETH0_RMII_RXD1 { + pinmux = <0x443c00e4 2 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd1_flexio_flexio_bit_flexio2_flexio_bit11: IOMUXC_ENET1_RD1_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT11 { + pinmux = <0x443c00e4 4 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd1_gpio_io_bit_gpio4_io_bit11: IOMUXC_ENET1_RD1_GPIO_IO_BIT_GPIO4_IO_BIT11 { + pinmux = <0x443c00e4 5 0x0 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd1_lptmr_alt_lptmr2_alt1: IOMUXC_ENET1_RD1_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c00e4 3 0x443c0548 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd1_lpuart_cts_b_lpuart3_cts_b: IOMUXC_ENET1_RD1_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c00e4 1 0x443c0554 0 0x443c02e8>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd2_eth_rgmii_rd_eth0_rgmii_rd2: IOMUXC_ENET1_RD2_ETH_RGMII_RD_ETH0_RGMII_RD2 { + pinmux = <0x443c00e8 0 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd2_eth_rmii_rx_er_eth0_rmii_rx_er: IOMUXC_ENET1_RD2_ETH_RMII_RX_ER_ETH0_RMII_RX_ER { + pinmux = <0x443c00e8 2 0x443c042c 1 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd2_flexio_flexio_bit_flexio2_flexio_bit12: IOMUXC_ENET1_RD2_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT12 { + pinmux = <0x443c00e8 4 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd2_gpio_io_bit_gpio4_io_bit12: IOMUXC_ENET1_RD2_GPIO_IO_BIT_GPIO4_IO_BIT12 { + pinmux = <0x443c00e8 5 0x0 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd2_lptmr_alt_lptmr2_alt2: IOMUXC_ENET1_RD2_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c00e8 3 0x443c054c 0 0x443c02ec>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd3_eth_rgmii_rd_eth0_rgmii_rd3: IOMUXC_ENET1_RD3_ETH_RGMII_RD_ETH0_RGMII_RD3 { + pinmux = <0x443c00ec 0 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd3_flexio_flexio_bit_flexio2_flexio_bit13: IOMUXC_ENET1_RD3_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT13 { + pinmux = <0x443c00ec 4 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd3_gpio_io_bit_gpio4_io_bit13: IOMUXC_ENET1_RD3_GPIO_IO_BIT_GPIO4_IO_BIT13 { + pinmux = <0x443c00ec 5 0x0 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc_enet1_rd3_lptmr_alt_lptmr2_alt3: IOMUXC_ENET1_RD3_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c00ec 3 0x443c0550 0 0x443c02f0>; + }; + /omit-if-no-ref/ iomuxc_enet1_rxc_eth_rgmii_rx_clk_eth0_rgmii_rx_clk: IOMUXC_ENET1_RXC_ETH_RGMII_RX_CLK_ETH0_RGMII_RX_CLK { + pinmux = <0x443c00dc 0 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc_enet1_rxc_eth_rmii_rx_er_eth0_rmii_rx_er: IOMUXC_ENET1_RXC_ETH_RMII_RX_ER_ETH0_RMII_RX_ER { + pinmux = <0x443c00dc 1 0x443c042c 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc_enet1_rxc_flexio_flexio_bit_flexio2_flexio_bit9: IOMUXC_ENET1_RXC_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT9 { + pinmux = <0x443c00dc 4 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc_enet1_rxc_gpio_io_bit_gpio4_io_bit9: IOMUXC_ENET1_RXC_GPIO_IO_BIT_GPIO4_IO_BIT9 { + pinmux = <0x443c00dc 5 0x0 0 0x443c02e0>; + }; + /omit-if-no-ref/ iomuxc_enet1_rx_ctl_eth_rgmii_rx_ctl_eth0_rgmii_rx_ctl: IOMUXC_ENET1_RX_CTL_ETH_RGMII_RX_CTL_ETH0_RGMII_RX_CTL { + pinmux = <0x443c00d8 0 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc_enet1_rx_ctl_eth_rmii_crs_dv_eth0_rmii_crs_dv: IOMUXC_ENET1_RX_CTL_ETH_RMII_CRS_DV_ETH0_RMII_CRS_DV { + pinmux = <0x443c00d8 2 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc_enet1_rx_ctl_flexio_flexio_bit_flexio2_flexio_bit8: IOMUXC_ENET1_RX_CTL_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT8 { + pinmux = <0x443c00d8 4 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc_enet1_rx_ctl_gpio_io_bit_gpio4_io_bit8: IOMUXC_ENET1_RX_CTL_GPIO_IO_BIT_GPIO4_IO_BIT8 { + pinmux = <0x443c00d8 5 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc_enet1_rx_ctl_lpuart_dsr_b_lpuart3_dsr_b: IOMUXC_ENET1_RX_CTL_LPUART_DSR_B_LPUART3_DSR_B { + pinmux = <0x443c00d8 1 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc_enet1_rx_ctl_usb_otg_pwr_usb2_otg_pwr: IOMUXC_ENET1_RX_CTL_USB_OTG_PWR_USB2_OTG_PWR { + pinmux = <0x443c00d8 3 0x0 0 0x443c02dc>; + }; + /omit-if-no-ref/ iomuxc_enet1_td0_eth_rgmii_td_eth0_rgmii_td0: IOMUXC_ENET1_TD0_ETH_RGMII_TD_ETH0_RGMII_TD0 { + pinmux = <0x443c00cc 0 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc_enet1_td0_eth_rmii_txd_eth0_rmii_txd0: IOMUXC_ENET1_TD0_ETH_RMII_TXD_ETH0_RMII_TXD0 { + pinmux = <0x443c00cc 2 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc_enet1_td0_flexio_flexio_bit_flexio2_flexio_bit5: IOMUXC_ENET1_TD0_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT5 { + pinmux = <0x443c00cc 4 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc_enet1_td0_gpio_io_bit_gpio4_io_bit5: IOMUXC_ENET1_TD0_GPIO_IO_BIT_GPIO4_IO_BIT5 { + pinmux = <0x443c00cc 5 0x0 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc_enet1_td0_lpuart_tx_lpuart3_tx: IOMUXC_ENET1_TD0_LPUART_TX_LPUART3_TX { + pinmux = <0x443c00cc 1 0x443c055c 0 0x443c02d0>; + }; + /omit-if-no-ref/ iomuxc_enet1_td1_eth_rgmii_td_eth0_rgmii_td1: IOMUXC_ENET1_TD1_ETH_RGMII_TD_ETH0_RGMII_TD1 { + pinmux = <0x443c00c8 0 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc_enet1_td1_eth_rmii_txd_eth0_rmii_txd1: IOMUXC_ENET1_TD1_ETH_RMII_TXD_ETH0_RMII_TXD1 { + pinmux = <0x443c00c8 7 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc_enet1_td1_flexio_flexio_bit_flexio2_flexio_bit4: IOMUXC_ENET1_TD1_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT4 { + pinmux = <0x443c00c8 4 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc_enet1_td1_gpio_io_bit_gpio4_io_bit4: IOMUXC_ENET1_TD1_GPIO_IO_BIT_GPIO4_IO_BIT4 { + pinmux = <0x443c00c8 5 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc_enet1_td1_i3c_pur_b_i3c2_pur_b: IOMUXC_ENET1_TD1_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c00c8 6 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc_enet1_td1_i3c_pur_i3c2_pur: IOMUXC_ENET1_TD1_I3C_PUR_I3C2_PUR { + pinmux = <0x443c00c8 2 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc_enet1_td1_lpuart_rts_b_lpuart3_rts_b: IOMUXC_ENET1_TD1_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c00c8 1 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc_enet1_td1_usb_otg_oc_usb1_otg_oc: IOMUXC_ENET1_TD1_USB_OTG_OC_USB1_OTG_OC { + pinmux = <0x443c00c8 3 0x0 0 0x443c02cc>; + }; + /omit-if-no-ref/ iomuxc_enet1_td2_can_rx_can2_rx: IOMUXC_ENET1_TD2_CAN_RX_CAN2_RX { + pinmux = <0x443c00c4 2 0x443c0444 1 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc_enet1_td2_eth_rgmii_td_eth0_rgmii_td2: IOMUXC_ENET1_TD2_ETH_RGMII_TD_ETH0_RGMII_TD2 { + pinmux = <0x443c00c4 0 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc_enet1_td2_eth_rmii_ref_clk_eth0_rmii_ref50_clk: IOMUXC_ENET1_TD2_ETH_RMII_REF_CLK_ETH0_RMII_REF50_CLK { + pinmux = <0x443c00c4 1 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc_enet1_td2_flexio_flexio_bit_flexio2_flexio_bit3: IOMUXC_ENET1_TD2_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT3 { + pinmux = <0x443c00c4 4 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc_enet1_td2_gpio_io_bit_gpio4_io_bit3: IOMUXC_ENET1_TD2_GPIO_IO_BIT_GPIO4_IO_BIT3 { + pinmux = <0x443c00c4 5 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc_enet1_td2_usb_otg_oc_usb2_otg_oc: IOMUXC_ENET1_TD2_USB_OTG_OC_USB2_OTG_OC { + pinmux = <0x443c00c4 3 0x0 0 0x443c02c8>; + }; + /omit-if-no-ref/ iomuxc_enet1_td3_can_tx_can2_tx: IOMUXC_ENET1_TD3_CAN_TX_CAN2_TX { + pinmux = <0x443c00c0 2 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc_enet1_td3_eth_rgmii_td_eth0_rgmii_td3: IOMUXC_ENET1_TD3_ETH_RGMII_TD_ETH0_RGMII_TD3 { + pinmux = <0x443c00c0 0 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc_enet1_td3_flexio_flexio_bit_flexio2_flexio_bit2: IOMUXC_ENET1_TD3_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT2 { + pinmux = <0x443c00c0 4 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc_enet1_td3_gpio_io_bit_gpio4_io_bit2: IOMUXC_ENET1_TD3_GPIO_IO_BIT_GPIO4_IO_BIT2 { + pinmux = <0x443c00c0 5 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc_enet1_td3_usb_otg_id_usb2_otg_id: IOMUXC_ENET1_TD3_USB_OTG_ID_USB2_OTG_ID { + pinmux = <0x443c00c0 3 0x0 0 0x443c02c4>; + }; + /omit-if-no-ref/ iomuxc_enet1_txc_enet_clk_root_enet_clk_root: IOMUXC_ENET1_TXC_ENET_CLK_ROOT_ENET_CLK_ROOT { + pinmux = <0x443c00d4 1 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc_enet1_txc_eth_rgmii_tx_clk_eth0_rgmii_tx_clk: IOMUXC_ENET1_TXC_ETH_RGMII_TX_CLK_ETH0_RGMII_TX_CLK { + pinmux = <0x443c00d4 0 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc_enet1_txc_flexio_flexio_bit_flexio2_flexio_bit7: IOMUXC_ENET1_TXC_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT7 { + pinmux = <0x443c00d4 4 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc_enet1_txc_gpio_io_bit_gpio4_io_bit7: IOMUXC_ENET1_TXC_GPIO_IO_BIT_GPIO4_IO_BIT7 { + pinmux = <0x443c00d4 5 0x0 0 0x443c02d8>; + }; + /omit-if-no-ref/ iomuxc_enet1_tx_ctl_eth_rgmii_tx_ctl_eth0_rgmii_tx_ctl: IOMUXC_ENET1_TX_CTL_ETH_RGMII_TX_CTL_ETH0_RGMII_TX_CTL { + pinmux = <0x443c00d0 0 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc_enet1_tx_ctl_eth_rmii_tx_en_eth0_rmii_tx_en: IOMUXC_ENET1_TX_CTL_ETH_RMII_TX_EN_ETH0_RMII_TX_EN { + pinmux = <0x443c00d0 2 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc_enet1_tx_ctl_flexio_flexio_bit_flexio2_flexio_bit6: IOMUXC_ENET1_TX_CTL_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT6 { + pinmux = <0x443c00d0 4 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc_enet1_tx_ctl_gpio_io_bit_gpio4_io_bit6: IOMUXC_ENET1_TX_CTL_GPIO_IO_BIT_GPIO4_IO_BIT6 { + pinmux = <0x443c00d0 5 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc_enet1_tx_ctl_lpuart_dtr_b_lpuart3_dtr_b: IOMUXC_ENET1_TX_CTL_LPUART_DTR_B_LPUART3_DTR_B { + pinmux = <0x443c00d0 1 0x0 0 0x443c02d4>; + }; + /omit-if-no-ref/ iomuxc_enet2_mdc_flexio_flexio_bit_flexio2_flexio_bit14: IOMUXC_ENET2_MDC_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT14 { + pinmux = <0x443c00f0 4 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc_enet2_mdc_gpio_io_bit_gpio4_io_bit14: IOMUXC_ENET2_MDC_GPIO_IO_BIT_GPIO4_IO_BIT14 { + pinmux = <0x443c00f0 5 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc_enet2_mdc_lpuart_dcd_b_lpuart4_dcd_b: IOMUXC_ENET2_MDC_LPUART_DCD_B_LPUART4_DCD_B { + pinmux = <0x443c00f0 1 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc_enet2_mdc_netc_mdc_netc_mdc: IOMUXC_ENET2_MDC_NETC_MDC_NETC_MDC { + pinmux = <0x443c00f0 0 0x443c0424 1 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc_enet2_mdc_sai_rx_sync_sai2_rx_sync: IOMUXC_ENET2_MDC_SAI_RX_SYNC_SAI2_RX_SYNC { + pinmux = <0x443c00f0 2 0x0 0 0x443c02f4>; + }; + /omit-if-no-ref/ iomuxc_enet2_mdio_flexio_flexio_bit_flexio2_flexio_bit15: IOMUXC_ENET2_MDIO_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT15 { + pinmux = <0x443c00f4 4 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc_enet2_mdio_gpio_io_bit_gpio4_io_bit15: IOMUXC_ENET2_MDIO_GPIO_IO_BIT_GPIO4_IO_BIT15 { + pinmux = <0x443c00f4 5 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc_enet2_mdio_lpuart_rin_b_lpuart4_rin_b: IOMUXC_ENET2_MDIO_LPUART_RIN_B_LPUART4_RIN_B { + pinmux = <0x443c00f4 1 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc_enet2_mdio_netc_mdio_netc_mdio: IOMUXC_ENET2_MDIO_NETC_MDIO_NETC_MDIO { + pinmux = <0x443c00f4 0 0x443c0428 1 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc_enet2_mdio_sai_rx_bclk_sai2_rx_bclk: IOMUXC_ENET2_MDIO_SAI_RX_BCLK_SAI2_RX_BCLK { + pinmux = <0x443c00f4 2 0x0 0 0x443c02f8>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd0_eth_rgmii_rd_eth1_rgmii_rd0: IOMUXC_ENET2_RD0_ETH_RGMII_RD_ETH1_RGMII_RD0 { + pinmux = <0x443c0118 0 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd0_eth_rmii_rxd_eth1_rmii_rxd0: IOMUXC_ENET2_RD0_ETH_RMII_RXD_ETH1_RMII_RXD0 { + pinmux = <0x443c0118 6 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd0_flexio_flexio_bit_flexio2_flexio_bit24: IOMUXC_ENET2_RD0_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT24 { + pinmux = <0x443c0118 4 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd0_gpio_io_bit_gpio4_io_bit24: IOMUXC_ENET2_RD0_GPIO_IO_BIT_GPIO4_IO_BIT24 { + pinmux = <0x443c0118 5 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd0_lpuart_rx_lpuart4_rx: IOMUXC_ENET2_RD0_LPUART_RX_LPUART4_RX { + pinmux = <0x443c0118 1 0x443c0564 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd0_sai_rx_bclk_sai4_rx_bclk: IOMUXC_ENET2_RD0_SAI_RX_BCLK_SAI4_RX_BCLK { + pinmux = <0x443c0118 3 0x443c0594 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd0_sai_tx_data_bit_sai2_tx_data_bit2: IOMUXC_ENET2_RD0_SAI_TX_DATA_BIT_SAI2_TX_DATA_BIT2 { + pinmux = <0x443c0118 2 0x0 0 0x443c031c>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd1_eth_rgmii_rd_eth1_rgmii_rd1: IOMUXC_ENET2_RD1_ETH_RGMII_RD_ETH1_RGMII_RD1 { + pinmux = <0x443c011c 0 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd1_eth_rmii_rxd_eth1_rmii_rxd1: IOMUXC_ENET2_RD1_ETH_RMII_RXD_ETH1_RMII_RXD1 { + pinmux = <0x443c011c 6 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd1_flexio_flexio_bit_flexio2_flexio_bit25: IOMUXC_ENET2_RD1_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT25 { + pinmux = <0x443c011c 4 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd1_gpio_io_bit_gpio4_io_bit25: IOMUXC_ENET2_RD1_GPIO_IO_BIT_GPIO4_IO_BIT25 { + pinmux = <0x443c011c 5 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd1_sai_rx_data_bit_sai4_rx_data_bit0: IOMUXC_ENET2_RD1_SAI_RX_DATA_BIT_SAI4_RX_DATA_BIT0 { + pinmux = <0x443c011c 3 0x443c0598 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd1_sai_tx_data_bit_sai2_tx_data_bit3: IOMUXC_ENET2_RD1_SAI_TX_DATA_BIT_SAI2_TX_DATA_BIT3 { + pinmux = <0x443c011c 2 0x0 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd1_spdif_in_spdif_in: IOMUXC_ENET2_RD1_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c011c 1 0x443c0454 0 0x443c0320>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd2_eth_rgmii_rd_eth1_rgmii_rd2: IOMUXC_ENET2_RD2_ETH_RGMII_RD_ETH1_RGMII_RD2 { + pinmux = <0x443c0120 0 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd2_eth_rmii_rx_er_eth1_rmii_rx_er: IOMUXC_ENET2_RD2_ETH_RMII_RX_ER_ETH1_RMII_RX_ER { + pinmux = <0x443c0120 6 0x443c0430 1 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd2_flexio_flexio_bit_flexio2_flexio_bit26: IOMUXC_ENET2_RD2_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT26 { + pinmux = <0x443c0120 4 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd2_gpio_io_bit_gpio4_io_bit26: IOMUXC_ENET2_RD2_GPIO_IO_BIT_GPIO4_IO_BIT26 { + pinmux = <0x443c0120 5 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd2_lpuart_cts_b_lpuart4_cts_b: IOMUXC_ENET2_RD2_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0120 1 0x443c0560 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd2_mqs_right_mqs2_right: IOMUXC_ENET2_RD2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c0120 3 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd2_sai_mclk_sai2_mclk: IOMUXC_ENET2_RD2_SAI_MCLK_SAI2_MCLK { + pinmux = <0x443c0120 2 0x0 0 0x443c0324>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd3_eth_rgmii_rd_eth1_rgmii_rd3: IOMUXC_ENET2_RD3_ETH_RGMII_RD_ETH1_RGMII_RD3 { + pinmux = <0x443c0124 0 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd3_flexio_flexio_bit_flexio2_flexio_bit27: IOMUXC_ENET2_RD3_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT27 { + pinmux = <0x443c0124 4 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd3_gpio_io_bit_gpio4_io_bit27: IOMUXC_ENET2_RD3_GPIO_IO_BIT_GPIO4_IO_BIT27 { + pinmux = <0x443c0124 5 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd3_mqs_left_mqs2_left: IOMUXC_ENET2_RD3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c0124 3 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd3_spdif_in_spdif_in: IOMUXC_ENET2_RD3_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0124 2 0x443c0454 1 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc_enet2_rd3_spdif_out_spdif_out: IOMUXC_ENET2_RD3_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c0124 1 0x0 0 0x443c0328>; + }; + /omit-if-no-ref/ iomuxc_enet2_rxc_eth_rgmii_rx_clk_eth1_rgmii_rx_clk: IOMUXC_ENET2_RXC_ETH_RGMII_RX_CLK_ETH1_RGMII_RX_CLK { + pinmux = <0x443c0114 0 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc_enet2_rxc_eth_rmii_rx_er_eth1_rmii_rx_er: IOMUXC_ENET2_RXC_ETH_RMII_RX_ER_ETH1_RMII_RX_ER { + pinmux = <0x443c0114 1 0x443c0430 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc_enet2_rxc_flexio_flexio_bit_flexio2_flexio_bit23: IOMUXC_ENET2_RXC_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT23 { + pinmux = <0x443c0114 4 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc_enet2_rxc_gpio_io_bit_gpio4_io_bit23: IOMUXC_ENET2_RXC_GPIO_IO_BIT_GPIO4_IO_BIT23 { + pinmux = <0x443c0114 5 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc_enet2_rxc_sai_rx_sync_sai4_rx_sync: IOMUXC_ENET2_RXC_SAI_RX_SYNC_SAI4_RX_SYNC { + pinmux = <0x443c0114 3 0x443c059c 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc_enet2_rxc_sai_tx_data_bit_sai2_tx_data_bit1: IOMUXC_ENET2_RXC_SAI_TX_DATA_BIT_SAI2_TX_DATA_BIT1 { + pinmux = <0x443c0114 2 0x0 0 0x443c0318>; + }; + /omit-if-no-ref/ iomuxc_enet2_rx_ctl_eth_rgmii_rx_ctl_eth1_rgmii_rx_ctl: IOMUXC_ENET2_RX_CTL_ETH_RGMII_RX_CTL_ETH1_RGMII_RX_CTL { + pinmux = <0x443c0110 0 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc_enet2_rx_ctl_eth_rmii_crs_dv_eth1_rmii_crs_dv: IOMUXC_ENET2_RX_CTL_ETH_RMII_CRS_DV_ETH1_RMII_CRS_DV { + pinmux = <0x443c0110 6 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc_enet2_rx_ctl_flexio_flexio_bit_flexio2_flexio_bit22: IOMUXC_ENET2_RX_CTL_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT22 { + pinmux = <0x443c0110 4 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc_enet2_rx_ctl_gpio_io_bit_gpio4_io_bit22: IOMUXC_ENET2_RX_CTL_GPIO_IO_BIT_GPIO4_IO_BIT22 { + pinmux = <0x443c0110 5 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc_enet2_rx_ctl_lpuart_dsr_b_lpuart4_dsr_b: IOMUXC_ENET2_RX_CTL_LPUART_DSR_B_LPUART4_DSR_B { + pinmux = <0x443c0110 1 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc_enet2_rx_ctl_sai_tx_data_bit_sai2_tx_data_bit0: IOMUXC_ENET2_RX_CTL_SAI_TX_DATA_BIT_SAI2_TX_DATA_BIT0 { + pinmux = <0x443c0110 2 0x0 0 0x443c0314>; + }; + /omit-if-no-ref/ iomuxc_enet2_td0_eth_rgmii_td_eth1_rgmii_td0: IOMUXC_ENET2_TD0_ETH_RGMII_TD_ETH1_RGMII_TD0 { + pinmux = <0x443c0104 0 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc_enet2_td0_eth_rmii_txd_eth1_rmii_txd0: IOMUXC_ENET2_TD0_ETH_RMII_TXD_ETH1_RMII_TXD0 { + pinmux = <0x443c0104 6 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc_enet2_td0_flexio_flexio_bit_flexio2_flexio_bit19: IOMUXC_ENET2_TD0_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT19 { + pinmux = <0x443c0104 4 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc_enet2_td0_gpio_io_bit_gpio4_io_bit19: IOMUXC_ENET2_TD0_GPIO_IO_BIT_GPIO4_IO_BIT19 { + pinmux = <0x443c0104 5 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc_enet2_td0_lpuart_tx_lpuart4_tx: IOMUXC_ENET2_TD0_LPUART_TX_LPUART4_TX { + pinmux = <0x443c0104 1 0x443c0568 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc_enet2_td0_sai_rx_data_bit_sai2_rx_data_bit3: IOMUXC_ENET2_TD0_SAI_RX_DATA_BIT_SAI2_RX_DATA_BIT3 { + pinmux = <0x443c0104 2 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc_enet2_td0_sai_tx_data_bit_sai4_tx_data_bit0: IOMUXC_ENET2_TD0_SAI_TX_DATA_BIT_SAI4_TX_DATA_BIT0 { + pinmux = <0x443c0104 3 0x0 0 0x443c0308>; + }; + /omit-if-no-ref/ iomuxc_enet2_td1_eth_rgmii_td_eth1_rgmii_td1: IOMUXC_ENET2_TD1_ETH_RGMII_TD_ETH1_RGMII_TD1 { + pinmux = <0x443c0100 0 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc_enet2_td1_eth_rmii_txd_eth1_rmii_txd1: IOMUXC_ENET2_TD1_ETH_RMII_TXD_ETH1_RMII_TXD1 { + pinmux = <0x443c0100 6 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc_enet2_td1_flexio_flexio_bit_flexio2_flexio_bit18: IOMUXC_ENET2_TD1_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT18 { + pinmux = <0x443c0100 4 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc_enet2_td1_gpio_io_bit_gpio4_io_bit18: IOMUXC_ENET2_TD1_GPIO_IO_BIT_GPIO4_IO_BIT18 { + pinmux = <0x443c0100 5 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc_enet2_td1_lpuart_rts_b_lpuart4_rts_b: IOMUXC_ENET2_TD1_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c0100 1 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc_enet2_td1_sai_rx_data_bit_sai2_rx_data_bit2: IOMUXC_ENET2_TD1_SAI_RX_DATA_BIT_SAI2_RX_DATA_BIT2 { + pinmux = <0x443c0100 2 0x0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc_enet2_td1_sai_tx_bclk_sai4_tx_bclk: IOMUXC_ENET2_TD1_SAI_TX_BCLK_SAI4_TX_BCLK { + pinmux = <0x443c0100 3 0x443c05a0 0 0x443c0304>; + }; + /omit-if-no-ref/ iomuxc_enet2_td2_eth_rgmii_td_eth1_rgmii_td2: IOMUXC_ENET2_TD2_ETH_RGMII_TD_ETH1_RGMII_TD2 { + pinmux = <0x443c00fc 0 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc_enet2_td2_eth_rmii_ref_clk_eth1_rmii_ref50_clk: IOMUXC_ENET2_TD2_ETH_RMII_REF_CLK_ETH1_RMII_REF50_CLK { + pinmux = <0x443c00fc 1 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc_enet2_td2_flexio_flexio_bit_flexio2_flexio_bit17: IOMUXC_ENET2_TD2_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT17 { + pinmux = <0x443c00fc 4 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc_enet2_td2_gpio_io_bit_gpio4_io_bit17: IOMUXC_ENET2_TD2_GPIO_IO_BIT_GPIO4_IO_BIT17 { + pinmux = <0x443c00fc 5 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc_enet2_td2_sai_rx_data_bit_sai2_rx_data_bit1: IOMUXC_ENET2_TD2_SAI_RX_DATA_BIT_SAI2_RX_DATA_BIT1 { + pinmux = <0x443c00fc 2 0x0 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc_enet2_td2_sai_tx_sync_sai4_tx_sync: IOMUXC_ENET2_TD2_SAI_TX_SYNC_SAI4_TX_SYNC { + pinmux = <0x443c00fc 3 0x443c05a4 0 0x443c0300>; + }; + /omit-if-no-ref/ iomuxc_enet2_td3_eth_rgmii_td_eth1_rgmii_td3: IOMUXC_ENET2_TD3_ETH_RGMII_TD_ETH1_RGMII_TD3 { + pinmux = <0x443c00f8 0 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc_enet2_td3_flexio_flexio_bit_flexio2_flexio_bit16: IOMUXC_ENET2_TD3_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT16 { + pinmux = <0x443c00f8 4 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc_enet2_td3_gpio_io_bit_gpio4_io_bit16: IOMUXC_ENET2_TD3_GPIO_IO_BIT_GPIO4_IO_BIT16 { + pinmux = <0x443c00f8 5 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc_enet2_td3_sai_rx_data_bit_sai2_rx_data_bit0: IOMUXC_ENET2_TD3_SAI_RX_DATA_BIT_SAI2_RX_DATA_BIT0 { + pinmux = <0x443c00f8 2 0x0 0 0x443c02fc>; + }; + /omit-if-no-ref/ iomuxc_enet2_txc_enet_clk_root_enet_clk_root: IOMUXC_ENET2_TXC_ENET_CLK_ROOT_ENET_CLK_ROOT { + pinmux = <0x443c010c 1 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc_enet2_txc_eth_rgmii_tx_clk_eth1_rgmii_tx_clk: IOMUXC_ENET2_TXC_ETH_RGMII_TX_CLK_ETH1_RGMII_TX_CLK { + pinmux = <0x443c010c 0 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc_enet2_txc_flexio_flexio_bit_flexio2_flexio_bit21: IOMUXC_ENET2_TXC_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT21 { + pinmux = <0x443c010c 4 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc_enet2_txc_gpio_io_bit_gpio4_io_bit21: IOMUXC_ENET2_TXC_GPIO_IO_BIT_GPIO4_IO_BIT21 { + pinmux = <0x443c010c 5 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc_enet2_txc_sai_tx_bclk_sai2_tx_bclk: IOMUXC_ENET2_TXC_SAI_TX_BCLK_SAI2_TX_BCLK { + pinmux = <0x443c010c 2 0x0 0 0x443c0310>; + }; + /omit-if-no-ref/ iomuxc_enet2_tx_ctl_eth_rgmii_tx_ctl_eth1_rgmii_tx_ctl: IOMUXC_ENET2_TX_CTL_ETH_RGMII_TX_CTL_ETH1_RGMII_TX_CTL { + pinmux = <0x443c0108 0 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc_enet2_tx_ctl_eth_rmii_tx_en_eth1_rmii_tx_en: IOMUXC_ENET2_TX_CTL_ETH_RMII_TX_EN_ETH1_RMII_TX_EN { + pinmux = <0x443c0108 3 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc_enet2_tx_ctl_flexio_flexio_bit_flexio2_flexio_bit20: IOMUXC_ENET2_TX_CTL_FLEXIO_FLEXIO_BIT_FLEXIO2_FLEXIO_BIT20 { + pinmux = <0x443c0108 4 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc_enet2_tx_ctl_gpio_io_bit_gpio4_io_bit20: IOMUXC_ENET2_TX_CTL_GPIO_IO_BIT_GPIO4_IO_BIT20 { + pinmux = <0x443c0108 5 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc_enet2_tx_ctl_lpuart_dtr_b_lpuart4_dtr_b: IOMUXC_ENET2_TX_CTL_LPUART_DTR_B_LPUART4_DTR_B { + pinmux = <0x443c0108 1 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc_enet2_tx_ctl_sai_tx_sync_sai2_tx_sync: IOMUXC_ENET2_TX_CTL_SAI_TX_SYNC_SAI2_TX_SYNC { + pinmux = <0x443c0108 2 0x0 0 0x443c030c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io00_flexio_flexio_bit_flexio1_flexio_bit0: IOMUXC_GPIO_IO00_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT0 { + pinmux = <0x443c0010 7 0x443c0468 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc_gpio_io00_gpio_io_bit_gpio2_io_bit0: IOMUXC_GPIO_IO00_GPIO_IO_BIT_GPIO2_IO_BIT0 { + pinmux = <0x443c0010 0 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc_gpio_io00_lpi2c_sda_lpi2c3_sda: IOMUXC_GPIO_IO00_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0010 1 0x443c0504 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc_gpio_io00_lpi2c_sda_lpi2c5_sda: IOMUXC_GPIO_IO00_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0010 6 0x443c0514 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc_gpio_io00_lpspi_pcs_lpspi6_pcs0: IOMUXC_GPIO_IO00_LPSPI_PCS_LPSPI6_PCS0 { + pinmux = <0x443c0010 4 0x0 0 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc_gpio_io00_lpuart_tx_lpuart5_tx: IOMUXC_GPIO_IO00_LPUART_TX_LPUART5_TX { + pinmux = <0x443c0010 5 0x443c0574 1 0x443c0214>; + }; + /omit-if-no-ref/ iomuxc_gpio_io01_flexio_flexio_bit_flexio1_flexio_bit1: IOMUXC_GPIO_IO01_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT1 { + pinmux = <0x443c0014 7 0x443c046c 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc_gpio_io01_gpio_io_bit_gpio2_io_bit1: IOMUXC_GPIO_IO01_GPIO_IO_BIT_GPIO2_IO_BIT1 { + pinmux = <0x443c0014 0 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc_gpio_io01_lpi2c_scl_lpi2c3_scl: IOMUXC_GPIO_IO01_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0014 1 0x443c0500 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc_gpio_io01_lpi2c_scl_lpi2c5_scl: IOMUXC_GPIO_IO01_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c0014 6 0x443c0510 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc_gpio_io01_lpspi_sin_lpspi6_sin: IOMUXC_GPIO_IO01_LPSPI_SIN_LPSPI6_SIN { + pinmux = <0x443c0014 4 0x0 0 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc_gpio_io01_lpuart_rx_lpuart5_rx: IOMUXC_GPIO_IO01_LPUART_RX_LPUART5_RX { + pinmux = <0x443c0014 5 0x443c0570 1 0x443c0218>; + }; + /omit-if-no-ref/ iomuxc_gpio_io02_flexio_flexio_bit_flexio1_flexio_bit2: IOMUXC_GPIO_IO02_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT2 { + pinmux = <0x443c0018 7 0x443c0470 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io02_gpio_io_bit_gpio2_io_bit2: IOMUXC_GPIO_IO02_GPIO_IO_BIT_GPIO2_IO_BIT2 { + pinmux = <0x443c0018 0 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io02_lpi2c_sda_lpi2c4_sda: IOMUXC_GPIO_IO02_LPI2C_SDA_LPI2C4_SDA { + pinmux = <0x443c0018 1 0x443c050c 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io02_lpi2c_sda_lpi2c6_sda: IOMUXC_GPIO_IO02_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0018 6 0x443c051c 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io02_lpspi_sout_lpspi6_sout: IOMUXC_GPIO_IO02_LPSPI_SOUT_LPSPI6_SOUT { + pinmux = <0x443c0018 4 0x0 0 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io02_lpuart_cts_b_lpuart5_cts_b: IOMUXC_GPIO_IO02_LPUART_CTS_B_LPUART5_CTS_B { + pinmux = <0x443c0018 5 0x443c056c 1 0x443c021c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io03_flexio_flexio_bit_flexio1_flexio_bit3: IOMUXC_GPIO_IO03_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT3 { + pinmux = <0x443c001c 7 0x443c0474 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc_gpio_io03_gpio_io_bit_gpio2_io_bit3: IOMUXC_GPIO_IO03_GPIO_IO_BIT_GPIO2_IO_BIT3 { + pinmux = <0x443c001c 0 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc_gpio_io03_lpi2c_scl_lpi2c4_scl: IOMUXC_GPIO_IO03_LPI2C_SCL_LPI2C4_SCL { + pinmux = <0x443c001c 1 0x443c0508 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc_gpio_io03_lpi2c_scl_lpi2c6_scl: IOMUXC_GPIO_IO03_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c001c 6 0x443c0518 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc_gpio_io03_lpspi_sck_lpspi6_sck: IOMUXC_GPIO_IO03_LPSPI_SCK_LPSPI6_SCK { + pinmux = <0x443c001c 4 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc_gpio_io03_lpuart_rts_b_lpuart5_rts_b: IOMUXC_GPIO_IO03_LPUART_RTS_B_LPUART5_RTS_B { + pinmux = <0x443c001c 5 0x0 0 0x443c0220>; + }; + /omit-if-no-ref/ iomuxc_gpio_io04_can_tx_can4_tx: IOMUXC_GPIO_IO04_CAN_TX_CAN4_TX { + pinmux = <0x443c0020 3 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc_gpio_io04_flexio_flexio_bit_flexio1_flexio_bit4: IOMUXC_GPIO_IO04_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT4 { + pinmux = <0x443c0020 7 0x443c0478 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc_gpio_io04_gpio_io_bit_gpio2_io_bit4: IOMUXC_GPIO_IO04_GPIO_IO_BIT_GPIO2_IO_BIT4 { + pinmux = <0x443c0020 0 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc_gpio_io04_lpi2c_sda_lpi2c6_sda: IOMUXC_GPIO_IO04_LPI2C_SDA_LPI2C6_SDA { + pinmux = <0x443c0020 6 0x443c051c 1 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc_gpio_io04_lpspi_pcs_lpspi7_pcs0: IOMUXC_GPIO_IO04_LPSPI_PCS_LPSPI7_PCS0 { + pinmux = <0x443c0020 4 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc_gpio_io04_lpuart_tx_lpuart6_tx: IOMUXC_GPIO_IO04_LPUART_TX_LPUART6_TX { + pinmux = <0x443c0020 5 0x443c0580 1 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc_gpio_io04_pdm_clk_pdm_clk: IOMUXC_GPIO_IO04_PDM_CLK_PDM_CLK { + pinmux = <0x443c0020 2 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc_gpio_io04_tpm_ch_tpm3_ch0: IOMUXC_GPIO_IO04_TPM_CH_TPM3_CH0 { + pinmux = <0x443c0020 1 0x0 0 0x443c0224>; + }; + /omit-if-no-ref/ iomuxc_gpio_io05_can_rx_can4_rx: IOMUXC_GPIO_IO05_CAN_RX_CAN4_RX { + pinmux = <0x443c0024 3 0x443c044c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc_gpio_io05_flexio_flexio_bit_flexio1_flexio_bit5: IOMUXC_GPIO_IO05_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT5 { + pinmux = <0x443c0024 7 0x443c047c 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc_gpio_io05_gpio_io_bit_gpio2_io_bit5: IOMUXC_GPIO_IO05_GPIO_IO_BIT_GPIO2_IO_BIT5 { + pinmux = <0x443c0024 0 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc_gpio_io05_lpi2c_scl_lpi2c6_scl: IOMUXC_GPIO_IO05_LPI2C_SCL_LPI2C6_SCL { + pinmux = <0x443c0024 6 0x443c0518 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc_gpio_io05_lpspi_sin_lpspi7_sin: IOMUXC_GPIO_IO05_LPSPI_SIN_LPSPI7_SIN { + pinmux = <0x443c0024 4 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc_gpio_io05_lpuart_rx_lpuart6_rx: IOMUXC_GPIO_IO05_LPUART_RX_LPUART6_RX { + pinmux = <0x443c0024 5 0x443c057c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc_gpio_io05_pdm_bit_stream_bit_pdm_bit_stream_bit0: IOMUXC_GPIO_IO05_PDM_BIT_STREAM_BIT_PDM_BIT_STREAM_BIT0 { + pinmux = <0x443c0024 2 0x443c040c 1 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc_gpio_io05_tpm_ch_tpm4_ch0: IOMUXC_GPIO_IO05_TPM_CH_TPM4_CH0 { + pinmux = <0x443c0024 1 0x0 0 0x443c0228>; + }; + /omit-if-no-ref/ iomuxc_gpio_io06_flexio_flexio_bit_flexio1_flexio_bit6: IOMUXC_GPIO_IO06_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT6 { + pinmux = <0x443c0028 7 0x443c0480 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io06_gpio_io_bit_gpio2_io_bit6: IOMUXC_GPIO_IO06_GPIO_IO_BIT_GPIO2_IO_BIT6 { + pinmux = <0x443c0028 0 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io06_lpi2c_sda_lpi2c7_sda: IOMUXC_GPIO_IO06_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0028 6 0x443c0524 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io06_lpspi_sout_lpspi7_sout: IOMUXC_GPIO_IO06_LPSPI_SOUT_LPSPI7_SOUT { + pinmux = <0x443c0028 4 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io06_lpuart_cts_b_lpuart6_cts_b: IOMUXC_GPIO_IO06_LPUART_CTS_B_LPUART6_CTS_B { + pinmux = <0x443c0028 5 0x443c0578 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io06_pdm_bit_stream_bit_pdm_bit_stream_bit1: IOMUXC_GPIO_IO06_PDM_BIT_STREAM_BIT_PDM_BIT_STREAM_BIT1 { + pinmux = <0x443c0028 2 0x443c0410 1 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io06_tpm_ch_tpm5_ch0: IOMUXC_GPIO_IO06_TPM_CH_TPM5_CH0 { + pinmux = <0x443c0028 1 0x0 0 0x443c022c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io07_flexio_flexio_bit_flexio1_flexio_bit7: IOMUXC_GPIO_IO07_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT7 { + pinmux = <0x443c002c 7 0x443c0484 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc_gpio_io07_gpio_io_bit_gpio2_io_bit7: IOMUXC_GPIO_IO07_GPIO_IO_BIT_GPIO2_IO_BIT7 { + pinmux = <0x443c002c 0 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc_gpio_io07_lpi2c_scl_lpi2c7_scl: IOMUXC_GPIO_IO07_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c002c 6 0x443c0520 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc_gpio_io07_lpspi_pcs_lpspi3_pcs1: IOMUXC_GPIO_IO07_LPSPI_PCS_LPSPI3_PCS1 { + pinmux = <0x443c002c 1 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc_gpio_io07_lpspi_sck_lpspi7_sck: IOMUXC_GPIO_IO07_LPSPI_SCK_LPSPI7_SCK { + pinmux = <0x443c002c 4 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc_gpio_io07_lpuart_rts_b_lpuart6_rts_b: IOMUXC_GPIO_IO07_LPUART_RTS_B_LPUART6_RTS_B { + pinmux = <0x443c002c 5 0x0 0 0x443c0230>; + }; + /omit-if-no-ref/ iomuxc_gpio_io08_flexio_flexio_bit_flexio1_flexio_bit8: IOMUXC_GPIO_IO08_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT8 { + pinmux = <0x443c0030 7 0x443c0488 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc_gpio_io08_gpio_io_bit_gpio2_io_bit8: IOMUXC_GPIO_IO08_GPIO_IO_BIT_GPIO2_IO_BIT8 { + pinmux = <0x443c0030 0 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc_gpio_io08_lpi2c_sda_lpi2c7_sda: IOMUXC_GPIO_IO08_LPI2C_SDA_LPI2C7_SDA { + pinmux = <0x443c0030 6 0x443c0524 1 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc_gpio_io08_lpspi_pcs_lpspi3_pcs0: IOMUXC_GPIO_IO08_LPSPI_PCS_LPSPI3_PCS0 { + pinmux = <0x443c0030 1 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc_gpio_io08_lpuart_tx_lpuart7_tx: IOMUXC_GPIO_IO08_LPUART_TX_LPUART7_TX { + pinmux = <0x443c0030 5 0x443c0588 1 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc_gpio_io08_tpm_ch_tpm6_ch0: IOMUXC_GPIO_IO08_TPM_CH_TPM6_CH0 { + pinmux = <0x443c0030 4 0x0 0 0x443c0234>; + }; + /omit-if-no-ref/ iomuxc_gpio_io09_flexio_flexio_bit_flexio1_flexio_bit9: IOMUXC_GPIO_IO09_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT9 { + pinmux = <0x443c0034 7 0x443c048c 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc_gpio_io09_gpio_io_bit_gpio2_io_bit9: IOMUXC_GPIO_IO09_GPIO_IO_BIT_GPIO2_IO_BIT9 { + pinmux = <0x443c0034 0 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc_gpio_io09_lpi2c_scl_lpi2c7_scl: IOMUXC_GPIO_IO09_LPI2C_SCL_LPI2C7_SCL { + pinmux = <0x443c0034 6 0x443c0520 1 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc_gpio_io09_lpspi_sin_lpspi3_sin: IOMUXC_GPIO_IO09_LPSPI_SIN_LPSPI3_SIN { + pinmux = <0x443c0034 1 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc_gpio_io09_lpuart_rx_lpuart7_rx: IOMUXC_GPIO_IO09_LPUART_RX_LPUART7_RX { + pinmux = <0x443c0034 5 0x443c0584 1 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc_gpio_io09_tpm_extclk_tpm3_extclk: IOMUXC_GPIO_IO09_TPM_EXTCLK_TPM3_EXTCLK { + pinmux = <0x443c0034 4 0x0 0 0x443c0238>; + }; + /omit-if-no-ref/ iomuxc_gpio_io10_flexio_flexio_bit_flexio1_flexio_bit10: IOMUXC_GPIO_IO10_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT10 { + pinmux = <0x443c0038 7 0x443c0490 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io10_gpio_io_bit_gpio2_io_bit10: IOMUXC_GPIO_IO10_GPIO_IO_BIT_GPIO2_IO_BIT10 { + pinmux = <0x443c0038 0 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io10_lpi2c_sda_lpi2c8_sda: IOMUXC_GPIO_IO10_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0038 6 0x443c052c 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io10_lpspi_sout_lpspi3_sout: IOMUXC_GPIO_IO10_LPSPI_SOUT_LPSPI3_SOUT { + pinmux = <0x443c0038 1 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io10_lpuart_cts_b_lpuart7_cts_b: IOMUXC_GPIO_IO10_LPUART_CTS_B_LPUART7_CTS_B { + pinmux = <0x443c0038 5 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io10_tpm_extclk_tpm4_extclk: IOMUXC_GPIO_IO10_TPM_EXTCLK_TPM4_EXTCLK { + pinmux = <0x443c0038 4 0x0 0 0x443c023c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io11_flexio_flexio_bit_flexio1_flexio_bit11: IOMUXC_GPIO_IO11_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT11 { + pinmux = <0x443c003c 7 0x443c0494 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc_gpio_io11_gpio_io_bit_gpio2_io_bit11: IOMUXC_GPIO_IO11_GPIO_IO_BIT_GPIO2_IO_BIT11 { + pinmux = <0x443c003c 0 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc_gpio_io11_lpi2c_scl_lpi2c8_scl: IOMUXC_GPIO_IO11_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c003c 6 0x443c0528 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc_gpio_io11_lpspi_sck_lpspi3_sck: IOMUXC_GPIO_IO11_LPSPI_SCK_LPSPI3_SCK { + pinmux = <0x443c003c 1 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc_gpio_io11_lpuart_rts_b_lpuart7_rts_b: IOMUXC_GPIO_IO11_LPUART_RTS_B_LPUART7_RTS_B { + pinmux = <0x443c003c 5 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc_gpio_io11_tpm_extclk_tpm5_extclk: IOMUXC_GPIO_IO11_TPM_EXTCLK_TPM5_EXTCLK { + pinmux = <0x443c003c 4 0x0 0 0x443c0240>; + }; + /omit-if-no-ref/ iomuxc_gpio_io12_flexio_flexio_bit_flexio1_flexio_bit12: IOMUXC_GPIO_IO12_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT12 { + pinmux = <0x443c0040 3 0x443c0498 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc_gpio_io12_gpio_io_bit_gpio2_io_bit12: IOMUXC_GPIO_IO12_GPIO_IO_BIT_GPIO2_IO_BIT12 { + pinmux = <0x443c0040 0 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc_gpio_io12_lpi2c_sda_lpi2c8_sda: IOMUXC_GPIO_IO12_LPI2C_SDA_LPI2C8_SDA { + pinmux = <0x443c0040 6 0x443c052c 1 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc_gpio_io12_lpspi_pcs_lpspi8_pcs0: IOMUXC_GPIO_IO12_LPSPI_PCS_LPSPI8_PCS0 { + pinmux = <0x443c0040 4 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc_gpio_io12_lpuart_tx_lpuart8_tx: IOMUXC_GPIO_IO12_LPUART_TX_LPUART8_TX { + pinmux = <0x443c0040 5 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc_gpio_io12_pdm_bit_stream_bit_pdm_bit_stream_bit2: IOMUXC_GPIO_IO12_PDM_BIT_STREAM_BIT_PDM_BIT_STREAM_BIT2 { + pinmux = <0x443c0040 2 0x443c0414 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc_gpio_io12_sai_rx_sync_sai3_rx_sync: IOMUXC_GPIO_IO12_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c0040 7 0x443c0590 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc_gpio_io12_tpm_ch_tpm3_ch2: IOMUXC_GPIO_IO12_TPM_CH_TPM3_CH2 { + pinmux = <0x443c0040 1 0x0 0 0x443c0244>; + }; + /omit-if-no-ref/ iomuxc_gpio_io13_flexio_flexio_bit_flexio1_flexio_bit13: IOMUXC_GPIO_IO13_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT13 { + pinmux = <0x443c0044 7 0x443c049c 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc_gpio_io13_gpio_io_bit_gpio2_io_bit13: IOMUXC_GPIO_IO13_GPIO_IO_BIT_GPIO2_IO_BIT13 { + pinmux = <0x443c0044 0 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc_gpio_io13_lpi2c_scl_lpi2c8_scl: IOMUXC_GPIO_IO13_LPI2C_SCL_LPI2C8_SCL { + pinmux = <0x443c0044 6 0x443c0528 1 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc_gpio_io13_lpspi_sin_lpspi8_sin: IOMUXC_GPIO_IO13_LPSPI_SIN_LPSPI8_SIN { + pinmux = <0x443c0044 4 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc_gpio_io13_lpuart_rx_lpuart8_rx: IOMUXC_GPIO_IO13_LPUART_RX_LPUART8_RX { + pinmux = <0x443c0044 5 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc_gpio_io13_pdm_bit_stream_bit_pdm_bit_stream_bit3: IOMUXC_GPIO_IO13_PDM_BIT_STREAM_BIT_PDM_BIT_STREAM_BIT3 { + pinmux = <0x443c0044 2 0x443c0418 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc_gpio_io13_tpm_ch_tpm4_ch2: IOMUXC_GPIO_IO13_TPM_CH_TPM4_CH2 { + pinmux = <0x443c0044 1 0x0 0 0x443c0248>; + }; + /omit-if-no-ref/ iomuxc_gpio_io14_flexio_flexio_bit_flexio1_flexio_bit14: IOMUXC_GPIO_IO14_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT14 { + pinmux = <0x443c0048 7 0x443c04a0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io14_gpio_io_bit_gpio2_io_bit14: IOMUXC_GPIO_IO14_GPIO_IO_BIT_GPIO2_IO_BIT14 { + pinmux = <0x443c0048 0 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io14_lpspi_sout_lpspi8_sout: IOMUXC_GPIO_IO14_LPSPI_SOUT_LPSPI8_SOUT { + pinmux = <0x443c0048 4 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io14_lpuart_cts_b_lpuart8_cts_b: IOMUXC_GPIO_IO14_LPUART_CTS_B_LPUART8_CTS_B { + pinmux = <0x443c0048 5 0x0 0 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io14_lpuart_tx_lpuart3_tx: IOMUXC_GPIO_IO14_LPUART_TX_LPUART3_TX { + pinmux = <0x443c0048 1 0x443c055c 1 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io14_lpuart_tx_lpuart4_tx: IOMUXC_GPIO_IO14_LPUART_TX_LPUART4_TX { + pinmux = <0x443c0048 6 0x443c0568 1 0x443c024c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io15_flexio_flexio_bit_flexio1_flexio_bit15: IOMUXC_GPIO_IO15_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT15 { + pinmux = <0x443c004c 7 0x443c04a4 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc_gpio_io15_gpio_io_bit_gpio2_io_bit15: IOMUXC_GPIO_IO15_GPIO_IO_BIT_GPIO2_IO_BIT15 { + pinmux = <0x443c004c 0 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc_gpio_io15_lpspi_sck_lpspi8_sck: IOMUXC_GPIO_IO15_LPSPI_SCK_LPSPI8_SCK { + pinmux = <0x443c004c 4 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc_gpio_io15_lpuart_rts_b_lpuart8_rts_b: IOMUXC_GPIO_IO15_LPUART_RTS_B_LPUART8_RTS_B { + pinmux = <0x443c004c 5 0x0 0 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc_gpio_io15_lpuart_rx_lpuart3_rx: IOMUXC_GPIO_IO15_LPUART_RX_LPUART3_RX { + pinmux = <0x443c004c 1 0x443c0558 1 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc_gpio_io15_lpuart_rx_lpuart4_rx: IOMUXC_GPIO_IO15_LPUART_RX_LPUART4_RX { + pinmux = <0x443c004c 6 0x443c0564 1 0x443c0250>; + }; + /omit-if-no-ref/ iomuxc_gpio_io16_flexio_flexio_bit_flexio1_flexio_bit16: IOMUXC_GPIO_IO16_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT16 { + pinmux = <0x443c0050 7 0x443c04a8 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc_gpio_io16_gpio_io_bit_gpio2_io_bit16: IOMUXC_GPIO_IO16_GPIO_IO_BIT_GPIO2_IO_BIT16 { + pinmux = <0x443c0050 0 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc_gpio_io16_lpspi_pcs_lpspi4_pcs2: IOMUXC_GPIO_IO16_LPSPI_PCS_LPSPI4_PCS2 { + pinmux = <0x443c0050 5 0x443c0538 1 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc_gpio_io16_lpuart_cts_b_lpuart3_cts_b: IOMUXC_GPIO_IO16_LPUART_CTS_B_LPUART3_CTS_B { + pinmux = <0x443c0050 4 0x443c0554 1 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc_gpio_io16_lpuart_cts_b_lpuart4_cts_b: IOMUXC_GPIO_IO16_LPUART_CTS_B_LPUART4_CTS_B { + pinmux = <0x443c0050 6 0x443c0560 1 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc_gpio_io16_pdm_bit_stream_bit_pdm_bit_stream_bit2: IOMUXC_GPIO_IO16_PDM_BIT_STREAM_BIT_PDM_BIT_STREAM_BIT2 { + pinmux = <0x443c0050 2 0x443c0414 1 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc_gpio_io16_sai_tx_bclk_sai3_tx_bclk: IOMUXC_GPIO_IO16_SAI_TX_BCLK_SAI3_TX_BCLK { + pinmux = <0x443c0050 1 0x0 0 0x443c0254>; + }; + /omit-if-no-ref/ iomuxc_gpio_io17_flexio_flexio_bit_flexio1_flexio_bit17: IOMUXC_GPIO_IO17_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT17 { + pinmux = <0x443c0054 7 0x443c04ac 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc_gpio_io17_gpio_io_bit_gpio2_io_bit17: IOMUXC_GPIO_IO17_GPIO_IO_BIT_GPIO2_IO_BIT17 { + pinmux = <0x443c0054 0 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc_gpio_io17_lpspi_pcs_lpspi4_pcs1: IOMUXC_GPIO_IO17_LPSPI_PCS_LPSPI4_PCS1 { + pinmux = <0x443c0054 5 0x443c0534 1 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc_gpio_io17_lpuart_rts_b_lpuart3_rts_b: IOMUXC_GPIO_IO17_LPUART_RTS_B_LPUART3_RTS_B { + pinmux = <0x443c0054 4 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc_gpio_io17_lpuart_rts_b_lpuart4_rts_b: IOMUXC_GPIO_IO17_LPUART_RTS_B_LPUART4_RTS_B { + pinmux = <0x443c0054 6 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc_gpio_io17_sai_mclk_sai3_mclk: IOMUXC_GPIO_IO17_SAI_MCLK_SAI3_MCLK { + pinmux = <0x443c0054 1 0x0 0 0x443c0258>; + }; + /omit-if-no-ref/ iomuxc_gpio_io18_flexio_flexio_bit_flexio1_flexio_bit18: IOMUXC_GPIO_IO18_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT18 { + pinmux = <0x443c0058 7 0x443c04b0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io18_gpio_io_bit_gpio2_io_bit18: IOMUXC_GPIO_IO18_GPIO_IO_BIT_GPIO2_IO_BIT18 { + pinmux = <0x443c0058 0 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io18_lpspi_pcs_lpspi4_pcs0: IOMUXC_GPIO_IO18_LPSPI_PCS_LPSPI4_PCS0 { + pinmux = <0x443c0058 5 0x443c0530 1 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io18_lpspi_pcs_lpspi5_pcs0: IOMUXC_GPIO_IO18_LPSPI_PCS_LPSPI5_PCS0 { + pinmux = <0x443c0058 4 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io18_sai_rx_bclk_sai3_rx_bclk: IOMUXC_GPIO_IO18_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0058 1 0x443c058c 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io18_tpm_ch_tpm5_ch2: IOMUXC_GPIO_IO18_TPM_CH_TPM5_CH2 { + pinmux = <0x443c0058 6 0x0 0 0x443c025c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io19_flexio_flexio_bit_flexio1_flexio_bit19: IOMUXC_GPIO_IO19_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT19 { + pinmux = <0x443c005c 3 0x443c04b4 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc_gpio_io19_gpio_io_bit_gpio2_io_bit19: IOMUXC_GPIO_IO19_GPIO_IO_BIT_GPIO2_IO_BIT19 { + pinmux = <0x443c005c 0 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc_gpio_io19_lpspi_sin_lpspi4_sin: IOMUXC_GPIO_IO19_LPSPI_SIN_LPSPI4_SIN { + pinmux = <0x443c005c 5 0x443c0540 1 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc_gpio_io19_lpspi_sin_lpspi5_sin: IOMUXC_GPIO_IO19_LPSPI_SIN_LPSPI5_SIN { + pinmux = <0x443c005c 4 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc_gpio_io19_pdm_bit_stream_bit_pdm_bit_stream_bit3: IOMUXC_GPIO_IO19_PDM_BIT_STREAM_BIT_PDM_BIT_STREAM_BIT3 { + pinmux = <0x443c005c 2 0x443c0418 1 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc_gpio_io19_sai_rx_sync_sai3_rx_sync: IOMUXC_GPIO_IO19_SAI_RX_SYNC_SAI3_RX_SYNC { + pinmux = <0x443c005c 1 0x443c0590 1 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc_gpio_io19_sai_tx_data_bit_sai3_tx_data_bit0: IOMUXC_GPIO_IO19_SAI_TX_DATA_BIT_SAI3_TX_DATA_BIT0 { + pinmux = <0x443c005c 7 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc_gpio_io19_tpm_ch_tpm6_ch2: IOMUXC_GPIO_IO19_TPM_CH_TPM6_CH2 { + pinmux = <0x443c005c 6 0x0 0 0x443c0260>; + }; + /omit-if-no-ref/ iomuxc_gpio_io20_flexio_flexio_bit_flexio1_flexio_bit20: IOMUXC_GPIO_IO20_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT20 { + pinmux = <0x443c0060 7 0x443c04b8 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc_gpio_io20_gpio_io_bit_gpio2_io_bit20: IOMUXC_GPIO_IO20_GPIO_IO_BIT_GPIO2_IO_BIT20 { + pinmux = <0x443c0060 0 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc_gpio_io20_lpspi_sout_lpspi4_sout: IOMUXC_GPIO_IO20_LPSPI_SOUT_LPSPI4_SOUT { + pinmux = <0x443c0060 5 0x443c0544 1 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc_gpio_io20_lpspi_sout_lpspi5_sout: IOMUXC_GPIO_IO20_LPSPI_SOUT_LPSPI5_SOUT { + pinmux = <0x443c0060 4 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc_gpio_io20_pdm_bit_stream_bit_pdm_bit_stream_bit0: IOMUXC_GPIO_IO20_PDM_BIT_STREAM_BIT_PDM_BIT_STREAM_BIT0 { + pinmux = <0x443c0060 2 0x443c040c 2 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc_gpio_io20_sai_rx_data_bit_sai3_rx_data_bit0: IOMUXC_GPIO_IO20_SAI_RX_DATA_BIT_SAI3_RX_DATA_BIT0 { + pinmux = <0x443c0060 1 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc_gpio_io20_tpm_ch_tpm3_ch1: IOMUXC_GPIO_IO20_TPM_CH_TPM3_CH1 { + pinmux = <0x443c0060 6 0x0 0 0x443c0264>; + }; + /omit-if-no-ref/ iomuxc_gpio_io21_flexio_flexio_bit_flexio1_flexio_bit21: IOMUXC_GPIO_IO21_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT21 { + pinmux = <0x443c0064 3 0x443c04bc 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc_gpio_io21_gpio_io_bit_gpio2_io_bit21: IOMUXC_GPIO_IO21_GPIO_IO_BIT_GPIO2_IO_BIT21 { + pinmux = <0x443c0064 0 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc_gpio_io21_lpspi_sck_lpspi4_sck: IOMUXC_GPIO_IO21_LPSPI_SCK_LPSPI4_SCK { + pinmux = <0x443c0064 5 0x443c053c 1 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc_gpio_io21_lpspi_sck_lpspi5_sck: IOMUXC_GPIO_IO21_LPSPI_SCK_LPSPI5_SCK { + pinmux = <0x443c0064 4 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc_gpio_io21_pdm_clk_pdm_clk: IOMUXC_GPIO_IO21_PDM_CLK_PDM_CLK { + pinmux = <0x443c0064 2 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc_gpio_io21_sai_rx_bclk_sai3_rx_bclk: IOMUXC_GPIO_IO21_SAI_RX_BCLK_SAI3_RX_BCLK { + pinmux = <0x443c0064 7 0x443c058c 1 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc_gpio_io21_sai_tx_data_bit_sai3_tx_data_bit0: IOMUXC_GPIO_IO21_SAI_TX_DATA_BIT_SAI3_TX_DATA_BIT0 { + pinmux = <0x443c0064 1 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc_gpio_io21_tpm_ch_tpm4_ch1: IOMUXC_GPIO_IO21_TPM_CH_TPM4_CH1 { + pinmux = <0x443c0064 6 0x0 0 0x443c0268>; + }; + /omit-if-no-ref/ iomuxc_gpio_io22_can_tx_can5_tx: IOMUXC_GPIO_IO22_CAN_TX_CAN5_TX { + pinmux = <0x443c0068 3 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io22_flexio_flexio_bit_flexio1_flexio_bit22: IOMUXC_GPIO_IO22_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT22 { + pinmux = <0x443c0068 7 0x443c04c0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io22_gpio_io_bit_gpio2_io_bit22: IOMUXC_GPIO_IO22_GPIO_IO_BIT_GPIO2_IO_BIT22 { + pinmux = <0x443c0068 0 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io22_lpi2c_sda_lpi2c5_sda: IOMUXC_GPIO_IO22_LPI2C_SDA_LPI2C5_SDA { + pinmux = <0x443c0068 6 0x443c0514 1 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io22_spdif_in_spdif_in: IOMUXC_GPIO_IO22_SPDIF_IN_SPDIF_IN { + pinmux = <0x443c0068 2 0x443c0454 2 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io22_tpm_ch_tpm5_ch1: IOMUXC_GPIO_IO22_TPM_CH_TPM5_CH1 { + pinmux = <0x443c0068 4 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io22_tpm_extclk_tpm6_extclk: IOMUXC_GPIO_IO22_TPM_EXTCLK_TPM6_EXTCLK { + pinmux = <0x443c0068 5 0x0 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io22_usdhc_clk_usdhc3_clk: IOMUXC_GPIO_IO22_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0068 1 0x443c05c8 0 0x443c026c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io23_can_rx_can5_rx: IOMUXC_GPIO_IO23_CAN_RX_CAN5_RX { + pinmux = <0x443c006c 3 0x443c0450 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc_gpio_io23_flexio_flexio_bit_flexio1_flexio_bit23: IOMUXC_GPIO_IO23_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT23 { + pinmux = <0x443c006c 7 0x443c04c4 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc_gpio_io23_gpio_io_bit_gpio2_io_bit23: IOMUXC_GPIO_IO23_GPIO_IO_BIT_GPIO2_IO_BIT23 { + pinmux = <0x443c006c 0 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc_gpio_io23_lpi2c_scl_lpi2c5_scl: IOMUXC_GPIO_IO23_LPI2C_SCL_LPI2C5_SCL { + pinmux = <0x443c006c 6 0x443c0510 1 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc_gpio_io23_spdif_out_spdif_out: IOMUXC_GPIO_IO23_SPDIF_OUT_SPDIF_OUT { + pinmux = <0x443c006c 2 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc_gpio_io23_tpm_ch_tpm6_ch1: IOMUXC_GPIO_IO23_TPM_CH_TPM6_CH1 { + pinmux = <0x443c006c 4 0x0 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc_gpio_io23_usdhc_cmd_usdhc3_cmd: IOMUXC_GPIO_IO23_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c006c 1 0x443c05cc 0 0x443c0270>; + }; + /omit-if-no-ref/ iomuxc_gpio_io24_flexio_flexio_bit_flexio1_flexio_bit24: IOMUXC_GPIO_IO24_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT24 { + pinmux = <0x443c0070 7 0x443c04c8 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc_gpio_io24_gpio_io_bit_gpio2_io_bit24: IOMUXC_GPIO_IO24_GPIO_IO_BIT_GPIO2_IO_BIT24 { + pinmux = <0x443c0070 0 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc_gpio_io24_jtag_mux_tdo_jtag_mux_tdo: IOMUXC_GPIO_IO24_JTAG_MUX_TDO_JTAG_MUX_TDO { + pinmux = <0x443c0070 5 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc_gpio_io24_lpspi_pcs_lpspi6_pcs1: IOMUXC_GPIO_IO24_LPSPI_PCS_LPSPI6_PCS1 { + pinmux = <0x443c0070 6 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc_gpio_io24_tpm_ch_tpm3_ch3: IOMUXC_GPIO_IO24_TPM_CH_TPM3_CH3 { + pinmux = <0x443c0070 4 0x0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc_gpio_io24_usdhc_data_usdhc3_data0: IOMUXC_GPIO_IO24_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0070 1 0x443c05d0 0 0x443c0274>; + }; + /omit-if-no-ref/ iomuxc_gpio_io25_can_tx_can2_tx: IOMUXC_GPIO_IO25_CAN_TX_CAN2_TX { + pinmux = <0x443c0074 2 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc_gpio_io25_flexio_flexio_bit_flexio1_flexio_bit25: IOMUXC_GPIO_IO25_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT25 { + pinmux = <0x443c0074 7 0x443c04cc 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc_gpio_io25_gpio_io_bit_gpio2_io_bit25: IOMUXC_GPIO_IO25_GPIO_IO_BIT_GPIO2_IO_BIT25 { + pinmux = <0x443c0074 0 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc_gpio_io25_jtag_mux_tck_jtag_mux_tck: IOMUXC_GPIO_IO25_JTAG_MUX_TCK_JTAG_MUX_TCK { + pinmux = <0x443c0074 5 0x443c060c 1 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc_gpio_io25_lpspi_pcs_lpspi7_pcs1: IOMUXC_GPIO_IO25_LPSPI_PCS_LPSPI7_PCS1 { + pinmux = <0x443c0074 6 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc_gpio_io25_tpm_ch_tpm4_ch3: IOMUXC_GPIO_IO25_TPM_CH_TPM4_CH3 { + pinmux = <0x443c0074 4 0x0 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc_gpio_io25_usdhc_data_usdhc3_data1: IOMUXC_GPIO_IO25_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0074 1 0x443c05d4 0 0x443c0278>; + }; + /omit-if-no-ref/ iomuxc_gpio_io26_flexio_flexio_bit_flexio1_flexio_bit26: IOMUXC_GPIO_IO26_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT26 { + pinmux = <0x443c0078 3 0x443c0458 1 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io26_gpio_io_bit_gpio2_io_bit26: IOMUXC_GPIO_IO26_GPIO_IO_BIT_GPIO2_IO_BIT26 { + pinmux = <0x443c0078 0 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io26_jtag_mux_tdi_jtag_mux_tdi: IOMUXC_GPIO_IO26_JTAG_MUX_TDI_JTAG_MUX_TDI { + pinmux = <0x443c0078 5 0x443c0610 1 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io26_lpspi_pcs_lpspi8_pcs1: IOMUXC_GPIO_IO26_LPSPI_PCS_LPSPI8_PCS1 { + pinmux = <0x443c0078 6 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io26_pdm_bit_stream_bit_pdm_bit_stream_bit1: IOMUXC_GPIO_IO26_PDM_BIT_STREAM_BIT_PDM_BIT_STREAM_BIT1 { + pinmux = <0x443c0078 2 0x443c0410 2 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io26_sai_tx_sync_sai3_tx_sync: IOMUXC_GPIO_IO26_SAI_TX_SYNC_SAI3_TX_SYNC { + pinmux = <0x443c0078 7 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io26_tpm_ch_tpm5_ch3: IOMUXC_GPIO_IO26_TPM_CH_TPM5_CH3 { + pinmux = <0x443c0078 4 0x0 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io26_usdhc_data_usdhc3_data2: IOMUXC_GPIO_IO26_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0078 1 0x443c05d8 0 0x443c027c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io27_can_rx_can2_rx: IOMUXC_GPIO_IO27_CAN_RX_CAN2_RX { + pinmux = <0x443c007c 2 0x443c0444 2 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc_gpio_io27_flexio_flexio_bit_flexio1_flexio_bit27: IOMUXC_GPIO_IO27_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT27 { + pinmux = <0x443c007c 7 0x443c045c 1 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc_gpio_io27_gpio_io_bit_gpio2_io_bit27: IOMUXC_GPIO_IO27_GPIO_IO_BIT_GPIO2_IO_BIT27 { + pinmux = <0x443c007c 0 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc_gpio_io27_jtag_mux_tms_jtag_mux_tms: IOMUXC_GPIO_IO27_JTAG_MUX_TMS_JTAG_MUX_TMS { + pinmux = <0x443c007c 5 0x443c0614 1 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc_gpio_io27_lpspi_pcs_lpspi5_pcs1: IOMUXC_GPIO_IO27_LPSPI_PCS_LPSPI5_PCS1 { + pinmux = <0x443c007c 6 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc_gpio_io27_tpm_ch_tpm6_ch3: IOMUXC_GPIO_IO27_TPM_CH_TPM6_CH3 { + pinmux = <0x443c007c 4 0x0 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc_gpio_io27_usdhc_data_usdhc3_data3: IOMUXC_GPIO_IO27_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c007c 1 0x443c05dc 0 0x443c0280>; + }; + /omit-if-no-ref/ iomuxc_gpio_io28_can_tx_can3_tx: IOMUXC_GPIO_IO28_CAN_TX_CAN3_TX { + pinmux = <0x443c0080 2 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc_gpio_io28_flexio_flexio_bit_flexio1_flexio_bit28: IOMUXC_GPIO_IO28_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT28 { + pinmux = <0x443c0080 7 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc_gpio_io28_gpio_io_bit_gpio2_io_bit28: IOMUXC_GPIO_IO28_GPIO_IO_BIT_GPIO2_IO_BIT28 { + pinmux = <0x443c0080 0 0x0 0 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc_gpio_io28_lpi2c_sda_lpi2c3_sda: IOMUXC_GPIO_IO28_LPI2C_SDA_LPI2C3_SDA { + pinmux = <0x443c0080 1 0x443c0504 1 0x443c0284>; + }; + /omit-if-no-ref/ iomuxc_gpio_io29_can_rx_can3_rx: IOMUXC_GPIO_IO29_CAN_RX_CAN3_RX { + pinmux = <0x443c0084 2 0x443c0448 1 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc_gpio_io29_flexio_flexio_bit_flexio1_flexio_bit29: IOMUXC_GPIO_IO29_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT29 { + pinmux = <0x443c0084 7 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc_gpio_io29_gpio_io_bit_gpio2_io_bit29: IOMUXC_GPIO_IO29_GPIO_IO_BIT_GPIO2_IO_BIT29 { + pinmux = <0x443c0084 0 0x0 0 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc_gpio_io29_lpi2c_scl_lpi2c3_scl: IOMUXC_GPIO_IO29_LPI2C_SCL_LPI2C3_SCL { + pinmux = <0x443c0084 1 0x443c0500 1 0x443c0288>; + }; + /omit-if-no-ref/ iomuxc_gpio_io30_can_tx_can5_tx: IOMUXC_GPIO_IO30_CAN_TX_CAN5_TX { + pinmux = <0x443c0088 2 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io30_flexio_flexio_bit_flexio1_flexio_bit30: IOMUXC_GPIO_IO30_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT30 { + pinmux = <0x443c0088 7 0x443c0460 1 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io30_gpio_io_bit_gpio2_io_bit30: IOMUXC_GPIO_IO30_GPIO_IO_BIT_GPIO2_IO_BIT30 { + pinmux = <0x443c0088 0 0x0 0 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io30_lpi2c_sda_lpi2c4_sda: IOMUXC_GPIO_IO30_LPI2C_SDA_LPI2C4_SDA { + pinmux = <0x443c0088 1 0x443c050c 1 0x443c028c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io31_can_rx_can5_rx: IOMUXC_GPIO_IO31_CAN_RX_CAN5_RX { + pinmux = <0x443c008c 2 0x443c0450 1 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc_gpio_io31_flexio_flexio_bit_flexio1_flexio_bit31: IOMUXC_GPIO_IO31_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT31 { + pinmux = <0x443c008c 7 0x443c0464 1 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc_gpio_io31_gpio_io_bit_gpio2_io_bit31: IOMUXC_GPIO_IO31_GPIO_IO_BIT_GPIO2_IO_BIT31 { + pinmux = <0x443c008c 0 0x0 0 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc_gpio_io31_lpi2c_scl_lpi2c4_scl: IOMUXC_GPIO_IO31_LPI2C_SCL_LPI2C4_SCL { + pinmux = <0x443c008c 1 0x443c0508 1 0x443c0290>; + }; + /omit-if-no-ref/ iomuxc_gpio_io32_gpio_io_bit_gpio5_io_bit12: IOMUXC_GPIO_IO32_GPIO_IO_BIT_GPIO5_IO_BIT12 { + pinmux = <0x443c0090 0 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc_gpio_io32_lpspi_pcs_lpspi4_pcs2: IOMUXC_GPIO_IO32_LPSPI_PCS_LPSPI4_PCS2 { + pinmux = <0x443c0090 4 0x443c0538 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc_gpio_io32_lpuart_tx_lpuart6_tx: IOMUXC_GPIO_IO32_LPUART_TX_LPUART6_TX { + pinmux = <0x443c0090 2 0x443c0580 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc_gpio_io32_pcie_clkreq_b_pcie1_clkreq_b: IOMUXC_GPIO_IO32_PCIE_CLKREQ_B_PCIE1_CLKREQ_B { + pinmux = <0x443c0090 1 0x0 0 0x443c0294>; + }; + /omit-if-no-ref/ iomuxc_gpio_io33_gpio_io_bit_gpio5_io_bit13: IOMUXC_GPIO_IO33_GPIO_IO_BIT_GPIO5_IO_BIT13 { + pinmux = <0x443c0094 0 0x0 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc_gpio_io33_lpspi_pcs_lpspi4_pcs1: IOMUXC_GPIO_IO33_LPSPI_PCS_LPSPI4_PCS1 { + pinmux = <0x443c0094 4 0x443c0534 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc_gpio_io33_lpuart_rx_lpuart6_rx: IOMUXC_GPIO_IO33_LPUART_RX_LPUART6_RX { + pinmux = <0x443c0094 2 0x443c057c 0 0x443c0298>; + }; + /omit-if-no-ref/ iomuxc_gpio_io34_gpio_io_bit_gpio5_io_bit14: IOMUXC_GPIO_IO34_GPIO_IO_BIT_GPIO5_IO_BIT14 { + pinmux = <0x443c0098 0 0x0 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io34_lpspi_pcs_lpspi4_pcs0: IOMUXC_GPIO_IO34_LPSPI_PCS_LPSPI4_PCS0 { + pinmux = <0x443c0098 4 0x443c0530 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc_gpio_io34_lpuart_cts_b_lpuart6_cts_b: IOMUXC_GPIO_IO34_LPUART_CTS_B_LPUART6_CTS_B { + pinmux = <0x443c0098 2 0x443c0578 0 0x443c029c>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_gpio_io_bit_gpio1_io_bit0: IOMUXC_I2C1_SCL_GPIO_IO_BIT_GPIO1_IO_BIT0 { + pinmux = <0x443c01c0 5 0x0 0 0x443c03c4>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_i3c_scl_i3c1_scl: IOMUXC_I2C1_SCL_I3C_SCL_I3C1_SCL { + pinmux = <0x443c01c0 1 0x0 0 0x443c03c4>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_lpi2c_scl_lpi2c1_scl: IOMUXC_I2C1_SCL_LPI2C_SCL_LPI2C1_SCL { + pinmux = <0x443c01c0 0 0x0 0 0x443c03c4>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_lpuart_dcd_b_lpuart1_dcd_b: IOMUXC_I2C1_SCL_LPUART_DCD_B_LPUART1_DCD_B { + pinmux = <0x443c01c0 2 0x0 0 0x443c03c4>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_tpm_ch_tpm2_ch0: IOMUXC_I2C1_SCL_TPM_CH_TPM2_CH0 { + pinmux = <0x443c01c0 3 0x0 0 0x443c03c4>; + }; + /omit-if-no-ref/ iomuxc_i2c1_scl_uart_rx_uart_rx: IOMUXC_I2C1_SCL_UART_RX_UART_RX { + pinmux = <0x443c01c0 4 0x0 0 0x443c03c4>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_gpio_io_bit_gpio1_io_bit1: IOMUXC_I2C1_SDA_GPIO_IO_BIT_GPIO1_IO_BIT1 { + pinmux = <0x443c01c4 5 0x0 0 0x443c03c8>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_i3c_sda_i3c1_sda: IOMUXC_I2C1_SDA_I3C_SDA_I3C1_SDA { + pinmux = <0x443c01c4 1 0x0 0 0x443c03c8>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_lpi2c_sda_lpi2c1_sda: IOMUXC_I2C1_SDA_LPI2C_SDA_LPI2C1_SDA { + pinmux = <0x443c01c4 0 0x0 0 0x443c03c8>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_lpuart_rin_b_lpuart1_rin_b: IOMUXC_I2C1_SDA_LPUART_RIN_B_LPUART1_RIN_B { + pinmux = <0x443c01c4 2 0x0 0 0x443c03c8>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_tpm_ch_tpm2_ch1: IOMUXC_I2C1_SDA_TPM_CH_TPM2_CH1 { + pinmux = <0x443c01c4 3 0x0 0 0x443c03c8>; + }; + /omit-if-no-ref/ iomuxc_i2c1_sda_uart_tx_uart_tx: IOMUXC_I2C1_SDA_UART_TX_UART_TX { + pinmux = <0x443c01c4 4 0x0 0 0x443c03c8>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_gpio_io_bit_gpio1_io_bit2: IOMUXC_I2C2_SCL_GPIO_IO_BIT_GPIO1_IO_BIT2 { + pinmux = <0x443c01c8 5 0x0 0 0x443c03cc>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i3c_pur_b_i3c1_pur_b: IOMUXC_I2C2_SCL_I3C_PUR_B_I3C1_PUR_B { + pinmux = <0x443c01c8 6 0x0 0 0x443c03cc>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_i3c_pur_i3c1_pur: IOMUXC_I2C2_SCL_I3C_PUR_I3C1_PUR { + pinmux = <0x443c01c8 1 0x0 0 0x443c03cc>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_lpi2c_scl_lpi2c2_scl: IOMUXC_I2C2_SCL_LPI2C_SCL_LPI2C2_SCL { + pinmux = <0x443c01c8 0 0x0 0 0x443c03cc>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_lpuart_dcd_b_lpuart2_dcd_b: IOMUXC_I2C2_SCL_LPUART_DCD_B_LPUART2_DCD_B { + pinmux = <0x443c01c8 2 0x0 0 0x443c03cc>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_sai_rx_sync_sai1_rx_sync: IOMUXC_I2C2_SCL_SAI_RX_SYNC_SAI1_RX_SYNC { + pinmux = <0x443c01c8 4 0x0 0 0x443c03cc>; + }; + /omit-if-no-ref/ iomuxc_i2c2_scl_tpm_ch_tpm2_ch2: IOMUXC_I2C2_SCL_TPM_CH_TPM2_CH2 { + pinmux = <0x443c01c8 3 0x0 0 0x443c03cc>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_gpio_io_bit_gpio1_io_bit3: IOMUXC_I2C2_SDA_GPIO_IO_BIT_GPIO1_IO_BIT3 { + pinmux = <0x443c01cc 5 0x0 0 0x443c03d0>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_lpi2c_sda_lpi2c2_sda: IOMUXC_I2C2_SDA_LPI2C_SDA_LPI2C2_SDA { + pinmux = <0x443c01cc 0 0x0 0 0x443c03d0>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_lpuart_rin_b_lpuart2_rin_b: IOMUXC_I2C2_SDA_LPUART_RIN_B_LPUART2_RIN_B { + pinmux = <0x443c01cc 2 0x0 0 0x443c03d0>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_sai_rx_bclk_sai1_rx_bclk: IOMUXC_I2C2_SDA_SAI_RX_BCLK_SAI1_RX_BCLK { + pinmux = <0x443c01cc 4 0x0 0 0x443c03d0>; + }; + /omit-if-no-ref/ iomuxc_i2c2_sda_tpm_ch_tpm2_ch3: IOMUXC_I2C2_SDA_TPM_CH_TPM2_CH3 { + pinmux = <0x443c01cc 3 0x0 0 0x443c03d0>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream0_can_rx_can1_rx: IOMUXC_PDM_BIT_STREAM0_CAN_RX_CAN1_RX { + pinmux = <0x443c01e4 6 0x443c0408 0 0x443c03e8>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream0_gpio_io_bit_gpio1_io_bit9: IOMUXC_PDM_BIT_STREAM0_GPIO_IO_BIT_GPIO1_IO_BIT9 { + pinmux = <0x443c01e4 5 0x0 0 0x443c03e8>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream0_lpspi_pcs_lpspi1_pcs1: IOMUXC_PDM_BIT_STREAM0_LPSPI_PCS_LPSPI1_PCS1 { + pinmux = <0x443c01e4 2 0x0 0 0x443c03e8>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream0_lptmr_alt_lptmr1_alt2: IOMUXC_PDM_BIT_STREAM0_LPTMR_ALT_LPTMR1_ALT2 { + pinmux = <0x443c01e4 4 0x0 0 0x443c03e8>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream0_mqs_right_mqs1_right: IOMUXC_PDM_BIT_STREAM0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c01e4 1 0x0 0 0x443c03e8>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream0_pdm_bit_stream_bit_pdm_bit_stream_bit0: IOMUXC_PDM_BIT_STREAM0_PDM_BIT_STREAM_BIT_PDM_BIT_STREAM_BIT0 { + pinmux = <0x443c01e4 0 0x443c040c 0 0x443c03e8>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream0_tpm_extclk_tpm1_extclk: IOMUXC_PDM_BIT_STREAM0_TPM_EXTCLK_TPM1_EXTCLK { + pinmux = <0x443c01e4 3 0x0 0 0x443c03e8>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream1_ext_clk_ext_clk1: IOMUXC_PDM_BIT_STREAM1_EXT_CLK_EXT_CLK1 { + pinmux = <0x443c01e8 6 0x443c0420 0 0x443c03ec>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream1_gpio_io_bit_gpio1_io_bit10: IOMUXC_PDM_BIT_STREAM1_GPIO_IO_BIT_GPIO1_IO_BIT10 { + pinmux = <0x443c01e8 5 0x0 0 0x443c03ec>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream1_lpspi_pcs_lpspi2_pcs1: IOMUXC_PDM_BIT_STREAM1_LPSPI_PCS_LPSPI2_PCS1 { + pinmux = <0x443c01e8 2 0x0 0 0x443c03ec>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream1_lptmr_alt_lptmr1_alt3: IOMUXC_PDM_BIT_STREAM1_LPTMR_ALT_LPTMR1_ALT3 { + pinmux = <0x443c01e8 4 0x0 0 0x443c03ec>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream1_nmi_glue_nmi_nmi_glue_nmi: IOMUXC_PDM_BIT_STREAM1_NMI_GLUE_NMI_NMI_GLUE_NMI { + pinmux = <0x443c01e8 1 0x0 0 0x443c03ec>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream1_pdm_bit_stream_bit_pdm_bit_stream_bit1: IOMUXC_PDM_BIT_STREAM1_PDM_BIT_STREAM_BIT_PDM_BIT_STREAM_BIT1 { + pinmux = <0x443c01e8 0 0x443c0410 0 0x443c03ec>; + }; + /omit-if-no-ref/ iomuxc_pdm_bit_stream1_tpm_extclk_tpm2_extclk: IOMUXC_PDM_BIT_STREAM1_TPM_EXTCLK_TPM2_EXTCLK { + pinmux = <0x443c01e8 3 0x0 0 0x443c03ec>; + }; + /omit-if-no-ref/ iomuxc_pdm_clk_can_tx_can1_tx: IOMUXC_PDM_CLK_CAN_TX_CAN1_TX { + pinmux = <0x443c01e0 6 0x0 0 0x443c03e4>; + }; + /omit-if-no-ref/ iomuxc_pdm_clk_gpio_io_bit_gpio1_io_bit8: IOMUXC_PDM_CLK_GPIO_IO_BIT_GPIO1_IO_BIT8 { + pinmux = <0x443c01e0 5 0x0 0 0x443c03e4>; + }; + /omit-if-no-ref/ iomuxc_pdm_clk_lptmr_alt_lptmr1_alt1: IOMUXC_PDM_CLK_LPTMR_ALT_LPTMR1_ALT1 { + pinmux = <0x443c01e0 4 0x0 0 0x443c03e4>; + }; + /omit-if-no-ref/ iomuxc_pdm_clk_mqs_left_mqs1_left: IOMUXC_PDM_CLK_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c01e0 1 0x0 0 0x443c03e4>; + }; + /omit-if-no-ref/ iomuxc_pdm_clk_pdm_clk_pdm_clk: IOMUXC_PDM_CLK_PDM_CLK_PDM_CLK { + pinmux = <0x443c01e0 0 0x0 0 0x443c03e4>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_gpio_io_bit_gpio1_io_bit14: IOMUXC_SAI1_RXD0_GPIO_IO_BIT_GPIO1_IO_BIT14 { + pinmux = <0x443c01f8 5 0x0 0 0x443c03fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_lpspi_sout_lpspi1_sout: IOMUXC_SAI1_RXD0_LPSPI_SOUT_LPSPI1_SOUT { + pinmux = <0x443c01f8 2 0x0 0 0x443c03fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_lpuart_dsr_b_lpuart2_dsr_b: IOMUXC_SAI1_RXD0_LPUART_DSR_B_LPUART2_DSR_B { + pinmux = <0x443c01f8 3 0x0 0 0x443c03fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_mqs_right_mqs1_right: IOMUXC_SAI1_RXD0_MQS_RIGHT_MQS1_RIGHT { + pinmux = <0x443c01f8 4 0x0 0 0x443c03fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_mclk_sai1_mclk: IOMUXC_SAI1_RXD0_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c01f8 1 0x443c041c 1 0x443c03fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_rxd0_sai_rx_data_bit_sai1_rx_data_bit0: IOMUXC_SAI1_RXD0_SAI_RX_DATA_BIT_SAI1_RX_DATA_BIT0 { + pinmux = <0x443c01f8 0 0x0 0 0x443c03fc>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_can_rx_can1_rx: IOMUXC_SAI1_TXC_CAN_RX_CAN1_RX { + pinmux = <0x443c01f0 4 0x443c0408 1 0x443c03f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_gpio_io_bit_gpio1_io_bit12: IOMUXC_SAI1_TXC_GPIO_IO_BIT_GPIO1_IO_BIT12 { + pinmux = <0x443c01f0 5 0x0 0 0x443c03f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_lpspi_sin_lpspi1_sin: IOMUXC_SAI1_TXC_LPSPI_SIN_LPSPI1_SIN { + pinmux = <0x443c01f0 2 0x0 0 0x443c03f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_lpuart_cts_b_lpuart2_cts_b: IOMUXC_SAI1_TXC_LPUART_CTS_B_LPUART2_CTS_B { + pinmux = <0x443c01f0 1 0x0 0 0x443c03f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_lpuart_dsr_b_lpuart1_dsr_b: IOMUXC_SAI1_TXC_LPUART_DSR_B_LPUART1_DSR_B { + pinmux = <0x443c01f0 3 0x0 0 0x443c03f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txc_sai_tx_bclk_sai1_tx_bclk: IOMUXC_SAI1_TXC_SAI_TX_BCLK_SAI1_TX_BCLK { + pinmux = <0x443c01f0 0 0x0 0 0x443c03f4>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_can_tx_can1_tx: IOMUXC_SAI1_TXD0_CAN_TX_CAN1_TX { + pinmux = <0x443c01f4 4 0x0 0 0x443c03f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_gpio_io_bit_gpio1_io_bit13: IOMUXC_SAI1_TXD0_GPIO_IO_BIT_GPIO1_IO_BIT13 { + pinmux = <0x443c01f4 5 0x0 0 0x443c03f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_lpspi_sck_lpspi1_sck: IOMUXC_SAI1_TXD0_LPSPI_SCK_LPSPI1_SCK { + pinmux = <0x443c01f4 2 0x0 0 0x443c03f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_lpuart_dtr_b_lpuart1_dtr_b: IOMUXC_SAI1_TXD0_LPUART_DTR_B_LPUART1_DTR_B { + pinmux = <0x443c01f4 3 0x0 0 0x443c03f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_lpuart_rts_b_lpuart2_rts_b: IOMUXC_SAI1_TXD0_LPUART_RTS_B_LPUART2_RTS_B { + pinmux = <0x443c01f4 1 0x0 0 0x443c03f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txd0_sai_tx_data_bit_sai1_tx_data_bit0: IOMUXC_SAI1_TXD0_SAI_TX_DATA_BIT_SAI1_TX_DATA_BIT0 { + pinmux = <0x443c01f4 0 0x0 0 0x443c03f8>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_gpio_io_bit_gpio1_io_bit11: IOMUXC_SAI1_TXFS_GPIO_IO_BIT_GPIO1_IO_BIT11 { + pinmux = <0x443c01ec 5 0x0 0 0x443c03f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_lpspi_pcs_lpspi1_pcs0: IOMUXC_SAI1_TXFS_LPSPI_PCS_LPSPI1_PCS0 { + pinmux = <0x443c01ec 2 0x0 0 0x443c03f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_lpuart_dtr_b_lpuart2_dtr_b: IOMUXC_SAI1_TXFS_LPUART_DTR_B_LPUART2_DTR_B { + pinmux = <0x443c01ec 3 0x0 0 0x443c03f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_mqs_left_mqs1_left: IOMUXC_SAI1_TXFS_MQS_LEFT_MQS1_LEFT { + pinmux = <0x443c01ec 4 0x0 0 0x443c03f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_data_bit_sai1_tx_data_bit1: IOMUXC_SAI1_TXFS_SAI_TX_DATA_BIT_SAI1_TX_DATA_BIT1 { + pinmux = <0x443c01ec 1 0x0 0 0x443c03f0>; + }; + /omit-if-no-ref/ iomuxc_sai1_txfs_sai_tx_sync_sai1_tx_sync: IOMUXC_SAI1_TXFS_SAI_TX_SYNC_SAI1_TX_SYNC { + pinmux = <0x443c01ec 0 0x0 0 0x443c03f0>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_flexio_flexio_bit_flexio1_flexio_bit8: IOMUXC_SD1_CLK_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT8 { + pinmux = <0x443c0128 4 0x443c0488 1 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_gpio_io_bit_gpio3_io_bit8: IOMUXC_SD1_CLK_GPIO_IO_BIT_GPIO3_IO_BIT8 { + pinmux = <0x443c0128 5 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_clk_usdhc_clk_usdhc1_clk: IOMUXC_SD1_CLK_USDHC_CLK_USDHC1_CLK { + pinmux = <0x443c0128 0 0x0 0 0x443c032c>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_flexio_flexio_bit_flexio1_flexio_bit9: IOMUXC_SD1_CMD_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT9 { + pinmux = <0x443c012c 4 0x443c048c 1 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_gpio_io_bit_gpio3_io_bit9: IOMUXC_SD1_CMD_GPIO_IO_BIT_GPIO3_IO_BIT9 { + pinmux = <0x443c012c 5 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc_sd1_cmd_usdhc_cmd_usdhc1_cmd: IOMUXC_SD1_CMD_USDHC_CMD_USDHC1_CMD { + pinmux = <0x443c012c 0 0x0 0 0x443c0330>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_flexio_flexio_bit_flexio1_flexio_bit10: IOMUXC_SD1_DATA0_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT10 { + pinmux = <0x443c0130 4 0x443c0490 1 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_gpio_io_bit_gpio3_io_bit10: IOMUXC_SD1_DATA0_GPIO_IO_BIT_GPIO3_IO_BIT10 { + pinmux = <0x443c0130 5 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc_sd1_data0_usdhc_data_usdhc1_data0: IOMUXC_SD1_DATA0_USDHC_DATA_USDHC1_DATA0 { + pinmux = <0x443c0130 0 0x0 0 0x443c0334>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_flexio_flexio_bit_flexio1_flexio_bit11: IOMUXC_SD1_DATA1_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT11 { + pinmux = <0x443c0134 4 0x443c0494 1 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_gpio_io_bit_gpio3_io_bit11: IOMUXC_SD1_DATA1_GPIO_IO_BIT_GPIO3_IO_BIT11 { + pinmux = <0x443c0134 5 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc_sd1_data1_usdhc_data_usdhc1_data1: IOMUXC_SD1_DATA1_USDHC_DATA_USDHC1_DATA1 { + pinmux = <0x443c0134 0 0x0 0 0x443c0338>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_flexio_flexio_bit_flexio1_flexio_bit12: IOMUXC_SD1_DATA2_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT12 { + pinmux = <0x443c0138 4 0x443c0498 1 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_gpio_io_bit_gpio3_io_bit12: IOMUXC_SD1_DATA2_GPIO_IO_BIT_GPIO3_IO_BIT12 { + pinmux = <0x443c0138 5 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_pmic_ready_pmic_ready: IOMUXC_SD1_DATA2_PMIC_READY_PMIC_READY { + pinmux = <0x443c0138 6 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data2_usdhc_data_usdhc1_data2: IOMUXC_SD1_DATA2_USDHC_DATA_USDHC1_DATA2 { + pinmux = <0x443c0138 0 0x0 0 0x443c033c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_flexio_flexio_bit_flexio1_flexio_bit13: IOMUXC_SD1_DATA3_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT13 { + pinmux = <0x443c013c 4 0x443c049c 1 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_flexspi_a_ss_b_flexspi1_a_ss1_b: IOMUXC_SD1_DATA3_FLEXSPI_A_SS_B_FLEXSPI1_A_SS1_B { + pinmux = <0x443c013c 1 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_gpio_io_bit_gpio3_io_bit13: IOMUXC_SD1_DATA3_GPIO_IO_BIT_GPIO3_IO_BIT13 { + pinmux = <0x443c013c 5 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc_sd1_data3_usdhc_data_usdhc1_data3: IOMUXC_SD1_DATA3_USDHC_DATA_USDHC1_DATA3 { + pinmux = <0x443c013c 0 0x0 0 0x443c0340>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_flexio_flexio_bit_flexio1_flexio_bit14: IOMUXC_SD1_DATA4_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT14 { + pinmux = <0x443c0140 4 0x443c04a0 1 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_flexspi_a_data_bit_flexspi1_a_data_bit4: IOMUXC_SD1_DATA4_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT4 { + pinmux = <0x443c0140 1 0x443c04e4 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_gpio_io_bit_gpio3_io_bit14: IOMUXC_SD1_DATA4_GPIO_IO_BIT_GPIO3_IO_BIT14 { + pinmux = <0x443c0140 5 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_usdhc_data_usdhc1_data4: IOMUXC_SD1_DATA4_USDHC_DATA_USDHC1_DATA4 { + pinmux = <0x443c0140 0 0x0 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc_sd1_data4_xspi_data_bit_xspi_data_bit4: IOMUXC_SD1_DATA4_XSPI_DATA_BIT_XSPI_DATA_BIT4 { + pinmux = <0x443c0140 6 0x443c05fc 0 0x443c0344>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_flexio_flexio_bit_flexio1_flexio_bit15: IOMUXC_SD1_DATA5_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT15 { + pinmux = <0x443c0144 4 0x443c04a4 1 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_flexspi_a_data_bit_flexspi1_a_data_bit5: IOMUXC_SD1_DATA5_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT5 { + pinmux = <0x443c0144 1 0x443c04e8 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_gpio_io_bit_gpio3_io_bit15: IOMUXC_SD1_DATA5_GPIO_IO_BIT_GPIO3_IO_BIT15 { + pinmux = <0x443c0144 5 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_data_usdhc1_data5: IOMUXC_SD1_DATA5_USDHC_DATA_USDHC1_DATA5 { + pinmux = <0x443c0144 0 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_usdhc_reset_b_usdhc1_reset_b: IOMUXC_SD1_DATA5_USDHC_RESET_B_USDHC1_RESET_B { + pinmux = <0x443c0144 2 0x0 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc_sd1_data5_xspi_data_bit_xspi_data_bit5: IOMUXC_SD1_DATA5_XSPI_DATA_BIT_XSPI_DATA_BIT5 { + pinmux = <0x443c0144 6 0x443c0600 0 0x443c0348>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_flexio_flexio_bit_flexio1_flexio_bit16: IOMUXC_SD1_DATA6_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT16 { + pinmux = <0x443c0148 4 0x443c04a8 1 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_flexspi_a_data_bit_flexspi1_a_data_bit6: IOMUXC_SD1_DATA6_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT6 { + pinmux = <0x443c0148 1 0x443c04ec 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_gpio_io_bit_gpio3_io_bit16: IOMUXC_SD1_DATA6_GPIO_IO_BIT_GPIO3_IO_BIT16 { + pinmux = <0x443c0148 5 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_cd_b_usdhc1_cd_b: IOMUXC_SD1_DATA6_USDHC_CD_B_USDHC1_CD_B { + pinmux = <0x443c0148 2 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_usdhc_data_usdhc1_data6: IOMUXC_SD1_DATA6_USDHC_DATA_USDHC1_DATA6 { + pinmux = <0x443c0148 0 0x0 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data6_xspi_data_bit_xspi_data_bit6: IOMUXC_SD1_DATA6_XSPI_DATA_BIT_XSPI_DATA_BIT6 { + pinmux = <0x443c0148 6 0x443c0604 0 0x443c034c>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_flexio_flexio_bit_flexio1_flexio_bit17: IOMUXC_SD1_DATA7_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT17 { + pinmux = <0x443c014c 4 0x443c04ac 1 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_flexspi_a_data_bit_flexspi1_a_data_bit7: IOMUXC_SD1_DATA7_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT7 { + pinmux = <0x443c014c 1 0x443c04f0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_gpio_io_bit_gpio3_io_bit17: IOMUXC_SD1_DATA7_GPIO_IO_BIT_GPIO3_IO_BIT17 { + pinmux = <0x443c014c 5 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_data_usdhc1_data7: IOMUXC_SD1_DATA7_USDHC_DATA_USDHC1_DATA7 { + pinmux = <0x443c014c 0 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_usdhc_wp_usdhc1_wp: IOMUXC_SD1_DATA7_USDHC_WP_USDHC1_WP { + pinmux = <0x443c014c 2 0x0 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc_sd1_data7_xspi_data_bit_xspi_data_bit7: IOMUXC_SD1_DATA7_XSPI_DATA_BIT_XSPI_DATA_BIT7 { + pinmux = <0x443c014c 6 0x443c0608 0 0x443c0350>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_flexio_flexio_bit_flexio1_flexio_bit18: IOMUXC_SD1_STROBE_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT18 { + pinmux = <0x443c0150 4 0x443c04b0 1 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_flexspi_a_dqs_flexspi1_a_dqs: IOMUXC_SD1_STROBE_FLEXSPI_A_DQS_FLEXSPI1_A_DQS { + pinmux = <0x443c0150 1 0x443c04d0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_gpio_io_bit_gpio3_io_bit18: IOMUXC_SD1_STROBE_GPIO_IO_BIT_GPIO3_IO_BIT18 { + pinmux = <0x443c0150 5 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_usdhc_strobe_usdhc1_strobe: IOMUXC_SD1_STROBE_USDHC_STROBE_USDHC1_STROBE { + pinmux = <0x443c0150 0 0x0 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc_sd1_strobe_xspi_dqs_xspi_dqs: IOMUXC_SD1_STROBE_XSPI_DQS_XSPI_DQS { + pinmux = <0x443c0150 6 0x443c05e4 0 0x443c0354>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_flexio_flexio_bit_flexio1_flexio_bit0: IOMUXC_SD2_CD_B_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT0 { + pinmux = <0x443c01a0 4 0x443c0468 1 0x443c03a4>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_gpio_io_bit_gpio3_io_bit0: IOMUXC_SD2_CD_B_GPIO_IO_BIT_GPIO3_IO_BIT0 { + pinmux = <0x443c01a0 5 0x0 0 0x443c03a4>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_i3c_scl_i3c2_scl: IOMUXC_SD2_CD_B_I3C_SCL_I3C2_SCL { + pinmux = <0x443c01a0 2 0x443c04f8 1 0x443c03a4>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_netc_tmr_1588_trig1_netc_tmr_1588_trig1: IOMUXC_SD2_CD_B_NETC_TMR_1588_TRIG1_NETC_TMR_1588_TRIG1 { + pinmux = <0x443c01a0 1 0x443c0434 1 0x443c03a4>; + }; + /omit-if-no-ref/ iomuxc_sd2_cd_b_usdhc_cd_b_usdhc2_cd_b: IOMUXC_SD2_CD_B_USDHC_CD_B_USDHC2_CD_B { + pinmux = <0x443c01a0 0 0x0 0 0x443c03a4>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe0: IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE0 { + pinmux = <0x443c01a4 6 0x0 0 0x443c03a8>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_flexio_flexio_bit_flexio1_flexio_bit1: IOMUXC_SD2_CLK_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT1 { + pinmux = <0x443c01a4 4 0x443c046c 1 0x443c03a8>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_gpio_io_bit_gpio3_io_bit1: IOMUXC_SD2_CLK_GPIO_IO_BIT_GPIO3_IO_BIT1 { + pinmux = <0x443c01a4 5 0x0 0 0x443c03a8>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_i3c_sda_i3c2_sda: IOMUXC_SD2_CLK_I3C_SDA_I3C2_SDA { + pinmux = <0x443c01a4 2 0x443c04fc 1 0x443c03a8>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_netc_tmr_1588_pp1_netc_tmr_1588_pp1: IOMUXC_SD2_CLK_NETC_TMR_1588_PP1_NETC_TMR_1588_PP1 { + pinmux = <0x443c01a4 1 0x0 0 0x443c03a8>; + }; + /omit-if-no-ref/ iomuxc_sd2_clk_usdhc_clk_usdhc2_clk: IOMUXC_SD2_CLK_USDHC_CLK_USDHC2_CLK { + pinmux = <0x443c01a4 0 0x0 0 0x443c03a8>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe1: IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE1 { + pinmux = <0x443c01a8 6 0x0 0 0x443c03ac>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_flexio_flexio_bit_flexio1_flexio_bit2: IOMUXC_SD2_CMD_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT2 { + pinmux = <0x443c01a8 4 0x443c0470 1 0x443c03ac>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_gpio_io_bit_gpio3_io_bit2: IOMUXC_SD2_CMD_GPIO_IO_BIT_GPIO3_IO_BIT2 { + pinmux = <0x443c01a8 5 0x0 0 0x443c03ac>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_i3c_pur_b_i3c2_pur_b: IOMUXC_SD2_CMD_I3C_PUR_B_I3C2_PUR_B { + pinmux = <0x443c01a8 3 0x0 0 0x443c03ac>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_i3c_pur_i3c2_pur: IOMUXC_SD2_CMD_I3C_PUR_I3C2_PUR { + pinmux = <0x443c01a8 2 0x0 0 0x443c03ac>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_netc_tmr_1588_trig2_netc_tmr_1588_trig2: IOMUXC_SD2_CMD_NETC_TMR_1588_TRIG2_NETC_TMR_1588_TRIG2 { + pinmux = <0x443c01a8 1 0x443c0438 1 0x443c03ac>; + }; + /omit-if-no-ref/ iomuxc_sd2_cmd_usdhc_cmd_usdhc2_cmd: IOMUXC_SD2_CMD_USDHC_CMD_USDHC2_CMD { + pinmux = <0x443c01a8 0 0x0 0 0x443c03ac>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_can_tx_can2_tx: IOMUXC_SD2_DATA0_CAN_TX_CAN2_TX { + pinmux = <0x443c01ac 2 0x0 0 0x443c03b0>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_ccmsrcgpcmix_observe_ccmsrcgpcmix_observe2: IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE_CCMSRCGPCMIX_OBSERVE2 { + pinmux = <0x443c01ac 6 0x0 0 0x443c03b0>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_flexio_flexio_bit_flexio1_flexio_bit3: IOMUXC_SD2_DATA0_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT3 { + pinmux = <0x443c01ac 4 0x443c0474 1 0x443c03b0>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_gpio_io_bit_gpio3_io_bit3: IOMUXC_SD2_DATA0_GPIO_IO_BIT_GPIO3_IO_BIT3 { + pinmux = <0x443c01ac 5 0x0 0 0x443c03b0>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_netc_tmr_1588_pp2_netc_tmr_1588_pp2: IOMUXC_SD2_DATA0_NETC_TMR_1588_PP2_NETC_TMR_1588_PP2 { + pinmux = <0x443c01ac 1 0x0 0 0x443c03b0>; + }; + /omit-if-no-ref/ iomuxc_sd2_data0_usdhc_data_usdhc2_data0: IOMUXC_SD2_DATA0_USDHC_DATA_USDHC2_DATA0 { + pinmux = <0x443c01ac 0 0x0 0 0x443c03b0>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_can_rx_can2_rx: IOMUXC_SD2_DATA1_CAN_RX_CAN2_RX { + pinmux = <0x443c01b0 2 0x443c0444 3 0x443c03b4>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_flexio_flexio_bit_flexio1_flexio_bit4: IOMUXC_SD2_DATA1_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT4 { + pinmux = <0x443c01b0 4 0x443c0478 1 0x443c03b4>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_gpio_io_bit_gpio3_io_bit4: IOMUXC_SD2_DATA1_GPIO_IO_BIT_GPIO3_IO_BIT4 { + pinmux = <0x443c01b0 5 0x0 0 0x443c03b4>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_netc_tmr_1588_clk_netc_tmr_1588_clk: IOMUXC_SD2_DATA1_NETC_TMR_1588_CLK_NETC_TMR_1588_CLK { + pinmux = <0x443c01b0 1 0x0 0 0x443c03b4>; + }; + /omit-if-no-ref/ iomuxc_sd2_data1_usdhc_data_usdhc2_data1: IOMUXC_SD2_DATA1_USDHC_DATA_USDHC2_DATA1 { + pinmux = <0x443c01b0 0 0x0 0 0x443c03b4>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_flexio_flexio_bit_flexio1_flexio_bit5: IOMUXC_SD2_DATA2_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT5 { + pinmux = <0x443c01b4 4 0x443c047c 1 0x443c03b8>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_gpio_io_bit_gpio3_io_bit5: IOMUXC_SD2_DATA2_GPIO_IO_BIT_GPIO3_IO_BIT5 { + pinmux = <0x443c01b4 5 0x0 0 0x443c03b8>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_mqs_right_mqs2_right: IOMUXC_SD2_DATA2_MQS_RIGHT_MQS2_RIGHT { + pinmux = <0x443c01b4 2 0x0 0 0x443c03b8>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_netc_tmr_1588_pp3_netc_tmr_1588_pp3: IOMUXC_SD2_DATA2_NETC_TMR_1588_PP3_NETC_TMR_1588_PP3 { + pinmux = <0x443c01b4 1 0x0 0 0x443c03b8>; + }; + /omit-if-no-ref/ iomuxc_sd2_data2_usdhc_data_usdhc2_data2: IOMUXC_SD2_DATA2_USDHC_DATA_USDHC2_DATA2 { + pinmux = <0x443c01b4 0 0x0 0 0x443c03b8>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_flexio_flexio_bit_flexio1_flexio_bit6: IOMUXC_SD2_DATA3_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT6 { + pinmux = <0x443c01b8 4 0x443c0480 1 0x443c03bc>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_gpio_io_bit_gpio3_io_bit6: IOMUXC_SD2_DATA3_GPIO_IO_BIT_GPIO3_IO_BIT6 { + pinmux = <0x443c01b8 5 0x0 0 0x443c03bc>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_lptmr_alt_lptmr2_alt1: IOMUXC_SD2_DATA3_LPTMR_ALT_LPTMR2_ALT1 { + pinmux = <0x443c01b8 1 0x443c0548 1 0x443c03bc>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_mqs_left_mqs2_left: IOMUXC_SD2_DATA3_MQS_LEFT_MQS2_LEFT { + pinmux = <0x443c01b8 2 0x0 0 0x443c03bc>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_netc_tmr_1588_alarm1_netc_tmr_1588_alarm1: IOMUXC_SD2_DATA3_NETC_TMR_1588_ALARM1_NETC_TMR_1588_ALARM1 { + pinmux = <0x443c01b8 3 0x0 0 0x443c03bc>; + }; + /omit-if-no-ref/ iomuxc_sd2_data3_usdhc_data_usdhc2_data3: IOMUXC_SD2_DATA3_USDHC_DATA_USDHC2_DATA3 { + pinmux = <0x443c01b8 0 0x0 0 0x443c03bc>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_flexio_flexio_bit_flexio1_flexio_bit7: IOMUXC_SD2_RESET_B_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT7 { + pinmux = <0x443c01bc 4 0x443c0484 1 0x443c03c0>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_gpio_io_bit_gpio3_io_bit7: IOMUXC_SD2_RESET_B_GPIO_IO_BIT_GPIO3_IO_BIT7 { + pinmux = <0x443c01bc 5 0x0 0 0x443c03c0>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_lptmr_alt_lptmr2_alt2: IOMUXC_SD2_RESET_B_LPTMR_ALT_LPTMR2_ALT2 { + pinmux = <0x443c01bc 1 0x443c054c 1 0x443c03c0>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_netc_tmr_1588_gclk_netc_tmr_1588_gclk: IOMUXC_SD2_RESET_B_NETC_TMR_1588_GCLK_NETC_TMR_1588_GCLK { + pinmux = <0x443c01bc 3 0x0 0 0x443c03c0>; + }; + /omit-if-no-ref/ iomuxc_sd2_reset_b_usdhc_reset_b_usdhc2_reset_b: IOMUXC_SD2_RESET_B_USDHC_RESET_B_USDHC2_RESET_B { + pinmux = <0x443c01bc 0 0x0 0 0x443c03c0>; + }; + /omit-if-no-ref/ iomuxc_sd2_vselect_ext_clk_ext_clk1: IOMUXC_SD2_VSELECT_EXT_CLK_EXT_CLK1 { + pinmux = <0x443c0154 6 0x443c0420 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc_sd2_vselect_flexio_flexio_bit_flexio1_flexio_bit19: IOMUXC_SD2_VSELECT_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT19 { + pinmux = <0x443c0154 4 0x443c04b4 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc_sd2_vselect_gpio_io_bit_gpio3_io_bit19: IOMUXC_SD2_VSELECT_GPIO_IO_BIT_GPIO3_IO_BIT19 { + pinmux = <0x443c0154 5 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc_sd2_vselect_lptmr_alt_lptmr2_alt3: IOMUXC_SD2_VSELECT_LPTMR_ALT_LPTMR2_ALT3 { + pinmux = <0x443c0154 2 0x443c0550 1 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc_sd2_vselect_usdhc_vselect_usdhc2_vselect: IOMUXC_SD2_VSELECT_USDHC_VSELECT_USDHC2_VSELECT { + pinmux = <0x443c0154 0 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc_sd2_vselect_usdhc_wp_usdhc2_wp: IOMUXC_SD2_VSELECT_USDHC_WP_USDHC2_WP { + pinmux = <0x443c0154 1 0x0 0 0x443c0358>; + }; + /omit-if-no-ref/ iomuxc_sd3_clk_flexio_flexio_bit_flexio1_flexio_bit20: IOMUXC_SD3_CLK_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT20 { + pinmux = <0x443c0158 4 0x443c04b8 1 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc_sd3_clk_flexspi_a_sclk_flexspi1_a_sclk: IOMUXC_SD3_CLK_FLEXSPI_A_SCLK_FLEXSPI1_A_SCLK { + pinmux = <0x443c0158 1 0x443c04f4 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc_sd3_clk_gpio_io_bit_gpio3_io_bit20: IOMUXC_SD3_CLK_GPIO_IO_BIT_GPIO3_IO_BIT20 { + pinmux = <0x443c0158 5 0x0 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc_sd3_clk_sai_rx_data_bit_sai5_rx_data_bit0: IOMUXC_SD3_CLK_SAI_RX_DATA_BIT_SAI5_RX_DATA_BIT0 { + pinmux = <0x443c0158 3 0x443c05ac 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc_sd3_clk_sai_tx_data_bit_sai5_tx_data_bit1: IOMUXC_SD3_CLK_SAI_TX_DATA_BIT_SAI5_TX_DATA_BIT1 { + pinmux = <0x443c0158 2 0x0 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc_sd3_clk_usdhc_clk_usdhc3_clk: IOMUXC_SD3_CLK_USDHC_CLK_USDHC3_CLK { + pinmux = <0x443c0158 0 0x443c05c8 1 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc_sd3_clk_xspi_clk_xspi_clk: IOMUXC_SD3_CLK_XSPI_CLK_XSPI_CLK { + pinmux = <0x443c0158 6 0x443c05e8 0 0x443c035c>; + }; + /omit-if-no-ref/ iomuxc_sd3_cmd_flexio_flexio_bit_flexio1_flexio_bit21: IOMUXC_SD3_CMD_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT21 { + pinmux = <0x443c015c 4 0x443c04bc 1 0x443c0360>; + }; + /omit-if-no-ref/ iomuxc_sd3_cmd_flexspi_a_ss_b_flexspi1_a_ss0_b: IOMUXC_SD3_CMD_FLEXSPI_A_SS_B_FLEXSPI1_A_SS0_B { + pinmux = <0x443c015c 1 0x0 0 0x443c0360>; + }; + /omit-if-no-ref/ iomuxc_sd3_cmd_gpio_io_bit_gpio3_io_bit21: IOMUXC_SD3_CMD_GPIO_IO_BIT_GPIO3_IO_BIT21 { + pinmux = <0x443c015c 5 0x0 0 0x443c0360>; + }; + /omit-if-no-ref/ iomuxc_sd3_cmd_sai_rx_sync_sai5_rx_sync: IOMUXC_SD3_CMD_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x443c015c 3 0x443c05bc 0 0x443c0360>; + }; + /omit-if-no-ref/ iomuxc_sd3_cmd_sai_tx_data_bit_sai5_tx_data_bit2: IOMUXC_SD3_CMD_SAI_TX_DATA_BIT_SAI5_TX_DATA_BIT2 { + pinmux = <0x443c015c 2 0x0 0 0x443c0360>; + }; + /omit-if-no-ref/ iomuxc_sd3_cmd_usdhc_cmd_usdhc3_cmd: IOMUXC_SD3_CMD_USDHC_CMD_USDHC3_CMD { + pinmux = <0x443c015c 0 0x443c05cc 1 0x443c0360>; + }; + /omit-if-no-ref/ iomuxc_sd3_cmd_xspi_cs_xspi_cs: IOMUXC_SD3_CMD_XSPI_CS_XSPI_CS { + pinmux = <0x443c015c 6 0x443c05e0 0 0x443c0360>; + }; + /omit-if-no-ref/ iomuxc_sd3_data0_flexio_flexio_bit_flexio1_flexio_bit22: IOMUXC_SD3_DATA0_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT22 { + pinmux = <0x443c0160 4 0x443c04c0 1 0x443c0364>; + }; + /omit-if-no-ref/ iomuxc_sd3_data0_flexspi_a_data_bit_flexspi1_a_data_bit0: IOMUXC_SD3_DATA0_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT0 { + pinmux = <0x443c0160 1 0x443c04d4 0 0x443c0364>; + }; + /omit-if-no-ref/ iomuxc_sd3_data0_gpio_io_bit_gpio3_io_bit22: IOMUXC_SD3_DATA0_GPIO_IO_BIT_GPIO3_IO_BIT22 { + pinmux = <0x443c0160 5 0x0 0 0x443c0364>; + }; + /omit-if-no-ref/ iomuxc_sd3_data0_sai_rx_bclk_sai5_rx_bclk: IOMUXC_SD3_DATA0_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x443c0160 3 0x443c05a8 0 0x443c0364>; + }; + /omit-if-no-ref/ iomuxc_sd3_data0_sai_tx_data_bit_sai5_tx_data_bit3: IOMUXC_SD3_DATA0_SAI_TX_DATA_BIT_SAI5_TX_DATA_BIT3 { + pinmux = <0x443c0160 2 0x0 0 0x443c0364>; + }; + /omit-if-no-ref/ iomuxc_sd3_data0_usdhc_data_usdhc3_data0: IOMUXC_SD3_DATA0_USDHC_DATA_USDHC3_DATA0 { + pinmux = <0x443c0160 0 0x443c05d0 1 0x443c0364>; + }; + /omit-if-no-ref/ iomuxc_sd3_data0_xspi_data_bit_xspi_data_bit0: IOMUXC_SD3_DATA0_XSPI_DATA_BIT_XSPI_DATA_BIT0 { + pinmux = <0x443c0160 6 0x443c05ec 0 0x443c0364>; + }; + /omit-if-no-ref/ iomuxc_sd3_data1_flexio_flexio_bit_flexio1_flexio_bit23: IOMUXC_SD3_DATA1_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT23 { + pinmux = <0x443c0164 4 0x443c04c4 1 0x443c0368>; + }; + /omit-if-no-ref/ iomuxc_sd3_data1_flexspi_a_data_bit_flexspi1_a_data_bit1: IOMUXC_SD3_DATA1_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT1 { + pinmux = <0x443c0164 1 0x443c04d8 0 0x443c0368>; + }; + /omit-if-no-ref/ iomuxc_sd3_data1_gpio_io_bit_gpio3_io_bit23: IOMUXC_SD3_DATA1_GPIO_IO_BIT_GPIO3_IO_BIT23 { + pinmux = <0x443c0164 5 0x0 0 0x443c0368>; + }; + /omit-if-no-ref/ iomuxc_sd3_data1_sai_rx_data_bit_sai5_rx_data_bit1: IOMUXC_SD3_DATA1_SAI_RX_DATA_BIT_SAI5_RX_DATA_BIT1 { + pinmux = <0x443c0164 2 0x443c05b0 0 0x443c0368>; + }; + /omit-if-no-ref/ iomuxc_sd3_data1_sai_tx_data_bit_sai5_tx_data_bit0: IOMUXC_SD3_DATA1_SAI_TX_DATA_BIT_SAI5_TX_DATA_BIT0 { + pinmux = <0x443c0164 3 0x0 0 0x443c0368>; + }; + /omit-if-no-ref/ iomuxc_sd3_data1_usdhc_data_usdhc3_data1: IOMUXC_SD3_DATA1_USDHC_DATA_USDHC3_DATA1 { + pinmux = <0x443c0164 0 0x443c05d4 1 0x443c0368>; + }; + /omit-if-no-ref/ iomuxc_sd3_data1_xspi_data_bit_xspi_data_bit1: IOMUXC_SD3_DATA1_XSPI_DATA_BIT_XSPI_DATA_BIT1 { + pinmux = <0x443c0164 6 0x443c05f0 0 0x443c0368>; + }; + /omit-if-no-ref/ iomuxc_sd3_data2_flexio_flexio_bit_flexio1_flexio_bit24: IOMUXC_SD3_DATA2_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT24 { + pinmux = <0x443c0168 4 0x443c04c8 1 0x443c036c>; + }; + /omit-if-no-ref/ iomuxc_sd3_data2_flexspi_a_data_bit_flexspi1_a_data_bit2: IOMUXC_SD3_DATA2_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT2 { + pinmux = <0x443c0168 1 0x443c04dc 0 0x443c036c>; + }; + /omit-if-no-ref/ iomuxc_sd3_data2_gpio_io_bit_gpio3_io_bit24: IOMUXC_SD3_DATA2_GPIO_IO_BIT_GPIO3_IO_BIT24 { + pinmux = <0x443c0168 5 0x0 0 0x443c036c>; + }; + /omit-if-no-ref/ iomuxc_sd3_data2_sai_rx_data_bit_sai5_rx_data_bit2: IOMUXC_SD3_DATA2_SAI_RX_DATA_BIT_SAI5_RX_DATA_BIT2 { + pinmux = <0x443c0168 2 0x443c05b4 0 0x443c036c>; + }; + /omit-if-no-ref/ iomuxc_sd3_data2_sai_tx_sync_sai5_tx_sync: IOMUXC_SD3_DATA2_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x443c0168 3 0x443c05c4 0 0x443c036c>; + }; + /omit-if-no-ref/ iomuxc_sd3_data2_usdhc_data_usdhc3_data2: IOMUXC_SD3_DATA2_USDHC_DATA_USDHC3_DATA2 { + pinmux = <0x443c0168 0 0x443c05d8 1 0x443c036c>; + }; + /omit-if-no-ref/ iomuxc_sd3_data2_xspi_data_bit_xspi_data_bit2: IOMUXC_SD3_DATA2_XSPI_DATA_BIT_XSPI_DATA_BIT2 { + pinmux = <0x443c0168 6 0x443c05f4 0 0x443c036c>; + }; + /omit-if-no-ref/ iomuxc_sd3_data3_flexio_flexio_bit_flexio1_flexio_bit25: IOMUXC_SD3_DATA3_FLEXIO_FLEXIO_BIT_FLEXIO1_FLEXIO_BIT25 { + pinmux = <0x443c016c 4 0x443c04cc 1 0x443c0370>; + }; + /omit-if-no-ref/ iomuxc_sd3_data3_flexspi_a_data_bit_flexspi1_a_data_bit3: IOMUXC_SD3_DATA3_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT3 { + pinmux = <0x443c016c 1 0x443c04e0 0 0x443c0370>; + }; + /omit-if-no-ref/ iomuxc_sd3_data3_gpio_io_bit_gpio3_io_bit25: IOMUXC_SD3_DATA3_GPIO_IO_BIT_GPIO3_IO_BIT25 { + pinmux = <0x443c016c 5 0x0 0 0x443c0370>; + }; + /omit-if-no-ref/ iomuxc_sd3_data3_sai_rx_data_bit_sai5_rx_data_bit3: IOMUXC_SD3_DATA3_SAI_RX_DATA_BIT_SAI5_RX_DATA_BIT3 { + pinmux = <0x443c016c 2 0x443c05b8 0 0x443c0370>; + }; + /omit-if-no-ref/ iomuxc_sd3_data3_sai_tx_bclk_sai5_tx_bclk: IOMUXC_SD3_DATA3_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x443c016c 3 0x443c05c0 0 0x443c0370>; + }; + /omit-if-no-ref/ iomuxc_sd3_data3_usdhc_data_usdhc3_data3: IOMUXC_SD3_DATA3_USDHC_DATA_USDHC3_DATA3 { + pinmux = <0x443c016c 0 0x443c05dc 1 0x443c0370>; + }; + /omit-if-no-ref/ iomuxc_sd3_data3_xspi_data_bit_xspi_data_bit3: IOMUXC_SD3_DATA3_XSPI_DATA_BIT_XSPI_DATA_BIT3 { + pinmux = <0x443c016c 6 0x443c05f8 0 0x443c0370>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_gpio_io_bit_gpio1_io_bit4: IOMUXC_UART1_RXD_GPIO_IO_BIT_GPIO1_IO_BIT4 { + pinmux = <0x443c01d0 5 0x0 0 0x443c03d4>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_lpspi_sin_lpspi2_sin: IOMUXC_UART1_RXD_LPSPI_SIN_LPSPI2_SIN { + pinmux = <0x443c01d0 2 0x0 0 0x443c03d4>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx: IOMUXC_UART1_RXD_LPUART_RX_LPUART1_RX { + pinmux = <0x443c01d0 0 0x0 0 0x443c03d4>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_s400_uart_rx_s400_uart_rx: IOMUXC_UART1_RXD_S400_UART_RX_S400_UART_RX { + pinmux = <0x443c01d0 1 0x0 0 0x443c03d4>; + }; + /omit-if-no-ref/ iomuxc_uart1_rxd_tpm_ch_tpm1_ch0: IOMUXC_UART1_RXD_TPM_CH_TPM1_CH0 { + pinmux = <0x443c01d0 3 0x0 0 0x443c03d4>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_gpio_io_bit_gpio1_io_bit5: IOMUXC_UART1_TXD_GPIO_IO_BIT_GPIO1_IO_BIT5 { + pinmux = <0x443c01d4 5 0x0 0 0x443c03d8>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_lpspi_pcs_lpspi2_pcs0: IOMUXC_UART1_TXD_LPSPI_PCS_LPSPI2_PCS0 { + pinmux = <0x443c01d4 2 0x0 0 0x443c03d8>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_lpuart_tx_lpuart1_tx: IOMUXC_UART1_TXD_LPUART_TX_LPUART1_TX { + pinmux = <0x443c01d4 0 0x0 0 0x443c03d8>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_s400_uart_tx_s400_uart_tx: IOMUXC_UART1_TXD_S400_UART_TX_S400_UART_TX { + pinmux = <0x443c01d4 1 0x0 0 0x443c03d8>; + }; + /omit-if-no-ref/ iomuxc_uart1_txd_tpm_ch_tpm1_ch1: IOMUXC_UART1_TXD_TPM_CH_TPM1_CH1 { + pinmux = <0x443c01d4 3 0x0 0 0x443c03d8>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_gpio_io_bit_gpio1_io_bit6: IOMUXC_UART2_RXD_GPIO_IO_BIT_GPIO1_IO_BIT6 { + pinmux = <0x443c01d8 5 0x0 0 0x443c03dc>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_lpspi_sout_lpspi2_sout: IOMUXC_UART2_RXD_LPSPI_SOUT_LPSPI2_SOUT { + pinmux = <0x443c01d8 2 0x0 0 0x443c03dc>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_lpuart_cts_b_lpuart1_cts_b: IOMUXC_UART2_RXD_LPUART_CTS_B_LPUART1_CTS_B { + pinmux = <0x443c01d8 1 0x0 0 0x443c03dc>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_lpuart_rx_lpuart2_rx: IOMUXC_UART2_RXD_LPUART_RX_LPUART2_RX { + pinmux = <0x443c01d8 0 0x0 0 0x443c03dc>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_sai_mclk_sai1_mclk: IOMUXC_UART2_RXD_SAI_MCLK_SAI1_MCLK { + pinmux = <0x443c01d8 4 0x443c041c 0 0x443c03dc>; + }; + /omit-if-no-ref/ iomuxc_uart2_rxd_tpm_ch_tpm1_ch2: IOMUXC_UART2_RXD_TPM_CH_TPM1_CH2 { + pinmux = <0x443c01d8 3 0x0 0 0x443c03dc>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_gpio_io_bit_gpio1_io_bit7: IOMUXC_UART2_TXD_GPIO_IO_BIT_GPIO1_IO_BIT7 { + pinmux = <0x443c01dc 5 0x0 0 0x443c03e0>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_lpspi_sck_lpspi2_sck: IOMUXC_UART2_TXD_LPSPI_SCK_LPSPI2_SCK { + pinmux = <0x443c01dc 2 0x0 0 0x443c03e0>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_lpuart_rts_b_lpuart1_rts_b: IOMUXC_UART2_TXD_LPUART_RTS_B_LPUART1_RTS_B { + pinmux = <0x443c01dc 1 0x0 0 0x443c03e0>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_lpuart_tx_lpuart2_tx: IOMUXC_UART2_TXD_LPUART_TX_LPUART2_TX { + pinmux = <0x443c01dc 0 0x0 0 0x443c03e0>; + }; + /omit-if-no-ref/ iomuxc_uart2_txd_tpm_ch_tpm1_ch3: IOMUXC_UART2_TXD_TPM_CH_TPM1_CH3 { + pinmux = <0x443c01dc 3 0x0 0 0x443c03e0>; + }; + /omit-if-no-ref/ iomuxc_wdog_any_fccu_eout_fccu_eout1: IOMUXC_WDOG_ANY_FCCU_EOUT_FCCU_EOUT1 { + pinmux = <0x443c01fc 1 0x0 0 0x443c0400>; + }; + /omit-if-no-ref/ iomuxc_wdog_any_gpio_io_bit_gpio1_io_bit15: IOMUXC_WDOG_ANY_GPIO_IO_BIT_GPIO1_IO_BIT15 { + pinmux = <0x443c01fc 5 0x0 0 0x443c0400>; + }; + /omit-if-no-ref/ iomuxc_wdog_any_wdog_any_wdog_any: IOMUXC_WDOG_ANY_WDOG_ANY_WDOG_ANY { + pinmux = <0x443c01fc 0 0x0 0 0x443c0400>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data0_flexspi_a_data_bit_flexspi1_a_data_bit0: IOMUXC_XSPI1_DATA0_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT0 { + pinmux = <0x443c0170 0 0x443c04d4 1 0x443c0374>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data0_gpio_io_bit_gpio5_io_bit0: IOMUXC_XSPI1_DATA0_GPIO_IO_BIT_GPIO5_IO_BIT0 { + pinmux = <0x443c0170 5 0x0 0 0x443c0374>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data0_sai_rx_data_bit_sai4_rx_data_bit1: IOMUXC_XSPI1_DATA0_SAI_RX_DATA_BIT_SAI4_RX_DATA_BIT1 { + pinmux = <0x443c0170 3 0x0 0 0x443c0374>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data0_sai_tx_bclk_sai4_tx_bclk: IOMUXC_XSPI1_DATA0_SAI_TX_BCLK_SAI4_TX_BCLK { + pinmux = <0x443c0170 2 0x443c05a0 1 0x443c0374>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data0_sai_tx_data_bit_sai2_tx_data_bit4: IOMUXC_XSPI1_DATA0_SAI_TX_DATA_BIT_SAI2_TX_DATA_BIT4 { + pinmux = <0x443c0170 1 0x0 0 0x443c0374>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data0_xspi_data_bit_xspi_data_bit0: IOMUXC_XSPI1_DATA0_XSPI_DATA_BIT_XSPI_DATA_BIT0 { + pinmux = <0x443c0170 4 0x443c05ec 1 0x443c0374>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data1_flexspi_a_data_bit_flexspi1_a_data_bit1: IOMUXC_XSPI1_DATA1_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT1 { + pinmux = <0x443c0174 0 0x443c04d8 1 0x443c0378>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data1_gpio_io_bit_gpio5_io_bit1: IOMUXC_XSPI1_DATA1_GPIO_IO_BIT_GPIO5_IO_BIT1 { + pinmux = <0x443c0174 5 0x0 0 0x443c0378>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data1_sai_tx_data_bit_sai2_tx_data_bit5: IOMUXC_XSPI1_DATA1_SAI_TX_DATA_BIT_SAI2_TX_DATA_BIT5 { + pinmux = <0x443c0174 1 0x0 0 0x443c0378>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data1_sai_tx_data_bit_sai4_tx_data_bit1: IOMUXC_XSPI1_DATA1_SAI_TX_DATA_BIT_SAI4_TX_DATA_BIT1 { + pinmux = <0x443c0174 3 0x0 0 0x443c0378>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data1_sai_tx_sync_sai4_tx_sync: IOMUXC_XSPI1_DATA1_SAI_TX_SYNC_SAI4_TX_SYNC { + pinmux = <0x443c0174 2 0x443c05a4 1 0x443c0378>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data1_xspi_data_bit_xspi_data_bit1: IOMUXC_XSPI1_DATA1_XSPI_DATA_BIT_XSPI_DATA_BIT1 { + pinmux = <0x443c0174 4 0x443c05f0 1 0x443c0378>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data2_flexspi_a_data_bit_flexspi1_a_data_bit2: IOMUXC_XSPI1_DATA2_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT2 { + pinmux = <0x443c0178 0 0x443c04dc 1 0x443c037c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data2_gpio_io_bit_gpio5_io_bit2: IOMUXC_XSPI1_DATA2_GPIO_IO_BIT_GPIO5_IO_BIT2 { + pinmux = <0x443c0178 5 0x0 0 0x443c037c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data2_sai_tx_data_bit_sai2_tx_data_bit6: IOMUXC_XSPI1_DATA2_SAI_TX_DATA_BIT_SAI2_TX_DATA_BIT6 { + pinmux = <0x443c0178 1 0x0 0 0x443c037c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data2_sai_tx_data_bit_sai4_tx_data_bit0: IOMUXC_XSPI1_DATA2_SAI_TX_DATA_BIT_SAI4_TX_DATA_BIT0 { + pinmux = <0x443c0178 2 0x0 0 0x443c037c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data2_xspi_data_bit_xspi_data_bit2: IOMUXC_XSPI1_DATA2_XSPI_DATA_BIT_XSPI_DATA_BIT2 { + pinmux = <0x443c0178 4 0x443c05f4 1 0x443c037c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data3_flexspi_a_data_bit_flexspi1_a_data_bit3: IOMUXC_XSPI1_DATA3_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT3 { + pinmux = <0x443c017c 0 0x443c04e0 1 0x443c0380>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data3_gpio_io_bit_gpio5_io_bit3: IOMUXC_XSPI1_DATA3_GPIO_IO_BIT_GPIO5_IO_BIT3 { + pinmux = <0x443c017c 5 0x0 0 0x443c0380>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data3_sai_rx_data_bit_sai4_rx_data_bit0: IOMUXC_XSPI1_DATA3_SAI_RX_DATA_BIT_SAI4_RX_DATA_BIT0 { + pinmux = <0x443c017c 2 0x443c0598 1 0x443c0380>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data3_sai_tx_data_bit_sai2_tx_data_bit7: IOMUXC_XSPI1_DATA3_SAI_TX_DATA_BIT_SAI2_TX_DATA_BIT7 { + pinmux = <0x443c017c 1 0x0 0 0x443c0380>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data3_xspi_data_bit_xspi_data_bit3: IOMUXC_XSPI1_DATA3_XSPI_DATA_BIT_XSPI_DATA_BIT3 { + pinmux = <0x443c017c 4 0x443c05f8 1 0x443c0380>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data4_flexspi_a_data_bit_flexspi1_a_data_bit4: IOMUXC_XSPI1_DATA4_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT4 { + pinmux = <0x443c0180 0 0x443c04e4 1 0x443c0384>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data4_gpio_io_bit_gpio5_io_bit4: IOMUXC_XSPI1_DATA4_GPIO_IO_BIT_GPIO5_IO_BIT4 { + pinmux = <0x443c0180 5 0x0 0 0x443c0384>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data4_sai_rx_data_bit_sai5_rx_data_bit1: IOMUXC_XSPI1_DATA4_SAI_RX_DATA_BIT_SAI5_RX_DATA_BIT1 { + pinmux = <0x443c0180 2 0x443c05b0 1 0x443c0384>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data4_sai_tx_data_bit_sai5_tx_data_bit0: IOMUXC_XSPI1_DATA4_SAI_TX_DATA_BIT_SAI5_TX_DATA_BIT0 { + pinmux = <0x443c0180 1 0x0 0 0x443c0384>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data4_xspi_data_bit_xspi_data_bit4: IOMUXC_XSPI1_DATA4_XSPI_DATA_BIT_XSPI_DATA_BIT4 { + pinmux = <0x443c0180 4 0x443c05fc 1 0x443c0384>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data5_flexspi_a_data_bit_flexspi1_a_data_bit5: IOMUXC_XSPI1_DATA5_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT5 { + pinmux = <0x443c0184 0 0x443c04e8 1 0x443c0388>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data5_gpio_io_bit_gpio5_io_bit5: IOMUXC_XSPI1_DATA5_GPIO_IO_BIT_GPIO5_IO_BIT5 { + pinmux = <0x443c0184 5 0x0 0 0x443c0388>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data5_sai_rx_data_bit_sai2_rx_data_bit6: IOMUXC_XSPI1_DATA5_SAI_RX_DATA_BIT_SAI2_RX_DATA_BIT6 { + pinmux = <0x443c0184 3 0x443c043c 0 0x443c0388>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data5_sai_rx_data_bit_sai5_rx_data_bit2: IOMUXC_XSPI1_DATA5_SAI_RX_DATA_BIT_SAI5_RX_DATA_BIT2 { + pinmux = <0x443c0184 2 0x443c05b4 1 0x443c0388>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data5_sai_tx_sync_sai5_tx_sync: IOMUXC_XSPI1_DATA5_SAI_TX_SYNC_SAI5_TX_SYNC { + pinmux = <0x443c0184 1 0x443c05c4 1 0x443c0388>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data5_xspi_data_bit_xspi_data_bit5: IOMUXC_XSPI1_DATA5_XSPI_DATA_BIT_XSPI_DATA_BIT5 { + pinmux = <0x443c0184 4 0x443c0600 1 0x443c0388>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data6_flexspi_a_data_bit_flexspi1_a_data_bit6: IOMUXC_XSPI1_DATA6_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT6 { + pinmux = <0x443c0188 0 0x443c04ec 1 0x443c038c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data6_gpio_io_bit_gpio5_io_bit6: IOMUXC_XSPI1_DATA6_GPIO_IO_BIT_GPIO5_IO_BIT6 { + pinmux = <0x443c0188 5 0x0 0 0x443c038c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data6_sai_rx_data_bit_sai2_rx_data_bit7: IOMUXC_XSPI1_DATA6_SAI_RX_DATA_BIT_SAI2_RX_DATA_BIT7 { + pinmux = <0x443c0188 3 0x443c0440 0 0x443c038c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data6_sai_rx_data_bit_sai5_rx_data_bit3: IOMUXC_XSPI1_DATA6_SAI_RX_DATA_BIT_SAI5_RX_DATA_BIT3 { + pinmux = <0x443c0188 2 0x443c05b8 1 0x443c038c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data6_sai_tx_bclk_sai5_tx_bclk: IOMUXC_XSPI1_DATA6_SAI_TX_BCLK_SAI5_TX_BCLK { + pinmux = <0x443c0188 1 0x443c05c0 1 0x443c038c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data6_xspi_data_bit_xspi_data_bit6: IOMUXC_XSPI1_DATA6_XSPI_DATA_BIT_XSPI_DATA_BIT6 { + pinmux = <0x443c0188 4 0x443c0604 1 0x443c038c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data7_flexspi_a_data_bit_flexspi1_a_data_bit7: IOMUXC_XSPI1_DATA7_FLEXSPI_A_DATA_BIT_FLEXSPI1_A_DATA_BIT7 { + pinmux = <0x443c018c 0 0x443c04f0 1 0x443c0390>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data7_gpio_io_bit_gpio5_io_bit7: IOMUXC_XSPI1_DATA7_GPIO_IO_BIT_GPIO5_IO_BIT7 { + pinmux = <0x443c018c 5 0x0 0 0x443c0390>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data7_sai_rx_data_bit_sai5_rx_data_bit0: IOMUXC_XSPI1_DATA7_SAI_RX_DATA_BIT_SAI5_RX_DATA_BIT0 { + pinmux = <0x443c018c 1 0x443c05ac 1 0x443c0390>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data7_sai_tx_data_bit_sai5_tx_data_bit1: IOMUXC_XSPI1_DATA7_SAI_TX_DATA_BIT_SAI5_TX_DATA_BIT1 { + pinmux = <0x443c018c 2 0x0 0 0x443c0390>; + }; + /omit-if-no-ref/ iomuxc_xspi1_data7_xspi_data_bit_xspi_data_bit7: IOMUXC_XSPI1_DATA7_XSPI_DATA_BIT_XSPI_DATA_BIT7 { + pinmux = <0x443c018c 4 0x443c0608 1 0x443c0390>; + }; + /omit-if-no-ref/ iomuxc_xspi1_dqs_flexspi_a_dqs_flexspi1_a_dqs: IOMUXC_XSPI1_DQS_FLEXSPI_A_DQS_FLEXSPI1_A_DQS { + pinmux = <0x443c0190 0 0x443c04d0 1 0x443c0394>; + }; + /omit-if-no-ref/ iomuxc_xspi1_dqs_gpio_io_bit_gpio5_io_bit8: IOMUXC_XSPI1_DQS_GPIO_IO_BIT_GPIO5_IO_BIT8 { + pinmux = <0x443c0190 5 0x0 0 0x443c0394>; + }; + /omit-if-no-ref/ iomuxc_xspi1_dqs_sai_rx_data_bit_sai2_rx_data_bit6: IOMUXC_XSPI1_DQS_SAI_RX_DATA_BIT_SAI2_RX_DATA_BIT6 { + pinmux = <0x443c0190 3 0x443c043c 1 0x443c0394>; + }; + /omit-if-no-ref/ iomuxc_xspi1_dqs_sai_rx_sync_sai5_rx_sync: IOMUXC_XSPI1_DQS_SAI_RX_SYNC_SAI5_RX_SYNC { + pinmux = <0x443c0190 1 0x443c05bc 1 0x443c0394>; + }; + /omit-if-no-ref/ iomuxc_xspi1_dqs_sai_tx_data_bit_sai5_tx_data_bit2: IOMUXC_XSPI1_DQS_SAI_TX_DATA_BIT_SAI5_TX_DATA_BIT2 { + pinmux = <0x443c0190 2 0x0 0 0x443c0394>; + }; + /omit-if-no-ref/ iomuxc_xspi1_dqs_xspi_dqs_xspi_dqs: IOMUXC_XSPI1_DQS_XSPI_DQS_XSPI_DQS { + pinmux = <0x443c0190 4 0x443c05e4 1 0x443c0394>; + }; + /omit-if-no-ref/ iomuxc_xspi1_sclk_earc_dc_hpd_in_earc_dc_hpd_in: IOMUXC_XSPI1_SCLK_EARC_DC_HPD_IN_EARC_DC_HPD_IN { + pinmux = <0x443c0194 3 0x0 0 0x443c0398>; + }; + /omit-if-no-ref/ iomuxc_xspi1_sclk_flexspi_a_sclk_flexspi1_a_sclk: IOMUXC_XSPI1_SCLK_FLEXSPI_A_SCLK_FLEXSPI1_A_SCLK { + pinmux = <0x443c0194 0 0x443c04f4 1 0x443c0398>; + }; + /omit-if-no-ref/ iomuxc_xspi1_sclk_gpio_io_bit_gpio5_io_bit9: IOMUXC_XSPI1_SCLK_GPIO_IO_BIT_GPIO5_IO_BIT9 { + pinmux = <0x443c0194 5 0x0 0 0x443c0398>; + }; + /omit-if-no-ref/ iomuxc_xspi1_sclk_sai_rx_data_bit_sai2_rx_data_bit4: IOMUXC_XSPI1_SCLK_SAI_RX_DATA_BIT_SAI2_RX_DATA_BIT4 { + pinmux = <0x443c0194 1 0x0 0 0x443c0398>; + }; + /omit-if-no-ref/ iomuxc_xspi1_sclk_sai_rx_sync_sai4_rx_sync: IOMUXC_XSPI1_SCLK_SAI_RX_SYNC_SAI4_RX_SYNC { + pinmux = <0x443c0194 2 0x443c059c 1 0x443c0398>; + }; + /omit-if-no-ref/ iomuxc_xspi1_sclk_xspi_clk_xspi_clk: IOMUXC_XSPI1_SCLK_XSPI_CLK_XSPI_CLK { + pinmux = <0x443c0194 4 0x443c05e8 1 0x443c0398>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss0_b_earc_cec_out_earc_cec_out: IOMUXC_XSPI1_SS0_B_EARC_CEC_OUT_EARC_CEC_OUT { + pinmux = <0x443c0198 3 0x0 0 0x443c039c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss0_b_flexspi_a_ss_b_flexspi1_a_ss0_b: IOMUXC_XSPI1_SS0_B_FLEXSPI_A_SS_B_FLEXSPI1_A_SS0_B { + pinmux = <0x443c0198 0 0x0 0 0x443c039c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss0_b_gpio_io_bit_gpio5_io_bit10: IOMUXC_XSPI1_SS0_B_GPIO_IO_BIT_GPIO5_IO_BIT10 { + pinmux = <0x443c0198 5 0x0 0 0x443c039c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss0_b_sai_rx_bclk_sai4_rx_bclk: IOMUXC_XSPI1_SS0_B_SAI_RX_BCLK_SAI4_RX_BCLK { + pinmux = <0x443c0198 2 0x443c0594 1 0x443c039c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss0_b_sai_rx_data_bit_sai2_rx_data_bit5: IOMUXC_XSPI1_SS0_B_SAI_RX_DATA_BIT_SAI2_RX_DATA_BIT5 { + pinmux = <0x443c0198 1 0x0 0 0x443c039c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss0_b_xspi_cs_xspi_cs: IOMUXC_XSPI1_SS0_B_XSPI_CS_XSPI_CS { + pinmux = <0x443c0198 4 0x443c05e0 1 0x443c039c>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss1_b_flexspi_a_ss_b_flexspi1_a_ss1_b: IOMUXC_XSPI1_SS1_B_FLEXSPI_A_SS_B_FLEXSPI1_A_SS1_B { + pinmux = <0x443c019c 0 0x0 0 0x443c03a0>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss1_b_gpio_io_bit_gpio5_io_bit11: IOMUXC_XSPI1_SS1_B_GPIO_IO_BIT_GPIO5_IO_BIT11 { + pinmux = <0x443c019c 5 0x0 0 0x443c03a0>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss1_b_sai_rx_bclk_sai5_rx_bclk: IOMUXC_XSPI1_SS1_B_SAI_RX_BCLK_SAI5_RX_BCLK { + pinmux = <0x443c019c 1 0x443c05a8 1 0x443c03a0>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss1_b_sai_rx_data_bit_sai2_rx_data_bit7: IOMUXC_XSPI1_SS1_B_SAI_RX_DATA_BIT_SAI2_RX_DATA_BIT7 { + pinmux = <0x443c019c 3 0x443c0440 1 0x443c03a0>; + }; + /omit-if-no-ref/ iomuxc_xspi1_ss1_b_sai_tx_data_bit_sai5_tx_data_bit3: IOMUXC_XSPI1_SS1_B_SAI_TX_DATA_BIT_SAI5_TX_DATA_BIT3 { + pinmux = <0x443c019c 2 0x0 0 0x443c03a0>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/MIMXRT533SFAWC-pinctrl.h b/dts/nxp/nxp_imx/rt/MIMXRT533SFAWC-pinctrl.h new file mode 100644 index 000000000..d89200d99 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/MIMXRT533SFAWC-pinctrl.h @@ -0,0 +1,4882 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from MIMXRT533SFAWC/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MIMXRT533SFAWC_ +#define _ZEPHYR_DTS_BINDING_MIMXRT533SFAWC_ + +#define IOPCTL_MUX(offset, mux) \ + ((((offset) & 0xFFF) << 20) | \ + (((mux) & 0xF) << 0)) + +#define CTIMER0_MATCH0_PIO0_0 IOPCTL_MUX(0, 4) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG33_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG34_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG35_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG36_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG33_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG34_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG35_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG36_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define FC0_SCK_PIO0_0 IOPCTL_MUX(0, 1) /* PIO0_0 */ +#define GPIO_INT_BMAT_PIO0_0 IOPCTL_MUX(0, 6) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define I2S_BRIDGE_CLK_IN_PIO0_0 IOPCTL_MUX(0, 5) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOPCTL_MUX(0, 8) /* PIO0_0 */ +#define SMARTDMA_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define CTIMER0_MATCH1_PIO0_1 IOPCTL_MUX(1, 4) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG33_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG34_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG35_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG36_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG33_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG34_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG35_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG36_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_1 IOPCTL_MUX(1, 1) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define I2S_BRIDGE_WS_IN_PIO0_1 IOPCTL_MUX(1, 5) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOPCTL_MUX(1, 8) /* PIO0_1 */ +#define SMARTDMA_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define CTIMER0_MATCH2_PIO0_2 IOPCTL_MUX(2, 4) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG33_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG34_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG35_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG36_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG33_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG34_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG35_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG36_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_2 IOPCTL_MUX(2, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define I2S_BRIDGE_DATA_IN_PIO0_2 IOPCTL_MUX(2, 5) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOPCTL_MUX(2, 8) /* PIO0_2 */ +#define SMARTDMA_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define CTIMER0_MATCH3_PIO0_3 IOPCTL_MUX(3, 4) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG33_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG34_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG35_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG36_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG33_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG34_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG35_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG36_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define FC0_CTS_SDA_SSEL0_PIO0_3 IOPCTL_MUX(3, 1) /* PIO0_3 */ +#define FC1_SSEL2_PIO0_3 IOPCTL_MUX(3, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOPCTL_MUX(3, 8) /* PIO0_3 */ +#define SMARTDMA_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define CMP0_OUT_PIO0_4 IOPCTL_MUX(4, 7) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG33_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG34_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG35_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG36_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG33_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG34_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG35_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG36_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define FC0_RTS_SCL_SSEL1_PIO0_4 IOPCTL_MUX(4, 1) /* PIO0_4 */ +#define FC1_SSEL3_PIO0_4 IOPCTL_MUX(4, 5) /* PIO0_4 */ +#define FLEXIO0_TRIG0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOPCTL_MUX(4, 8) /* PIO0_4 */ +#define SMARTDMA_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define ADC0_CH0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG33_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG34_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG35_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG36_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG33_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG34_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG35_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG36_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define FC0_SSEL2_PIO0_5 IOPCTL_MUX(5, 1) /* PIO0_5 */ +#define FLEXIO0_TRIG1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_OUT0_PIO0_5 IOPCTL_MUX(5, 3) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOPCTL_MUX(5, 8) /* PIO0_5 */ +#define SMARTDMA_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define ADC0_CH8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER0_MATCH0_PIO0_6 IOPCTL_MUX(6, 4) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG33_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG34_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG35_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG36_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG33_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG34_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG35_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG36_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define FC0_SSEL3_PIO0_6 IOPCTL_MUX(6, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_OUT1_PIO0_6 IOPCTL_MUX(6, 3) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOPCTL_MUX(6, 8) /* PIO0_6 */ +#define SMARTDMA_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER1_MATCH0_PIO0_7 IOPCTL_MUX(7, 4) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG33_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG34_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG35_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG36_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG33_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG34_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG35_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG36_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOPCTL_MUX(7, 1) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_7 IOPCTL_MUX(7, 5) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SCT0_IN0_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN1_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN2_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN3_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN4_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN5_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN6_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_OUT4_PIO0_7 IOPCTL_MUX(7, 3) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOPCTL_MUX(7, 8) /* PIO0_7 */ +#define SMARTDMA_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define CTIMER1_MATCH1_PIO0_8 IOPCTL_MUX(8, 4) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG33_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG34_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG35_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG36_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG33_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG34_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG35_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG36_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_8 IOPCTL_MUX(8, 1) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define I2S_BRIDGE_WS_OUT_PIO0_8 IOPCTL_MUX(8, 5) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define SCT0_IN0_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN1_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN2_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN3_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN4_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN5_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN6_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_OUT5_PIO0_8 IOPCTL_MUX(8, 3) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOPCTL_MUX(8, 8) /* PIO0_8 */ +#define CTIMER1_MATCH2_PIO0_9 IOPCTL_MUX(9, 4) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG33_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG34_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG35_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG36_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG33_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG34_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG35_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG36_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_9 IOPCTL_MUX(9, 1) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_9 IOPCTL_MUX(9, 5) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define SCT0_IN0_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN1_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN2_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN3_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN4_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN5_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN6_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_OUT6_PIO0_9 IOPCTL_MUX(9, 3) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOPCTL_MUX(9, 8) /* PIO0_9 */ +#define CTIMER1_MATCH3_PIO0_10 IOPCTL_MUX(10, 4) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG33_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG34_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG35_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG36_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG33_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG34_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG35_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG36_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define FC0_SSEL2_PIO0_10 IOPCTL_MUX(10, 5) /* PIO0_10 */ +#define FC1_CTS_SDA_SSEL0_PIO0_10 IOPCTL_MUX(10, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define SCT0_IN0_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN1_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN2_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN3_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN4_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN5_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN6_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_OUT7_PIO0_10 IOPCTL_MUX(10, 3) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOPCTL_MUX(10, 8) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG33_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG34_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG35_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG36_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG33_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG34_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG35_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG36_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define FC0_SSEL3_PIO0_11 IOPCTL_MUX(11, 5) /* PIO0_11 */ +#define FC1_RTS_SCL_SSEL1_PIO0_11 IOPCTL_MUX(11, 1) /* PIO0_11 */ +#define FLEXIO0_TRIG2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define SCT0_IN0_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN1_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN2_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN3_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN4_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN5_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN6_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_OUT8_PIO0_11 IOPCTL_MUX(11, 3) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOPCTL_MUX(11, 8) /* PIO0_11 */ +#define ADC0_CH1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG33_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG34_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG35_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG36_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG33_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG34_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG35_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG36_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define FC1_SSEL2_PIO0_12 IOPCTL_MUX(12, 1) /* PIO0_12 */ +#define FLEXIO0_TRIG3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_OUT2_PIO0_12 IOPCTL_MUX(12, 3) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOPCTL_MUX(12, 8) /* PIO0_12 */ +#define ADC0_CH9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define CTIMER0_MATCH1_PIO0_13 IOPCTL_MUX(13, 4) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG33_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG34_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG35_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG36_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG33_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG34_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG35_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG36_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define FC1_SSEL3_PIO0_13 IOPCTL_MUX(13, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_OUT3_PIO0_13 IOPCTL_MUX(13, 3) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOPCTL_MUX(13, 8) /* PIO0_13 */ +#define CTIMER2_MATCH0_PIO0_14 IOPCTL_MUX(14, 4) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG33_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG34_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG35_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG36_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG33_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG34_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG35_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG36_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define FC2_SCK_PIO0_14 IOPCTL_MUX(14, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define I2S_BRIDGE_CLK_IN_PIO0_14 IOPCTL_MUX(14, 5) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_OUT0_PIO0_14 IOPCTL_MUX(14, 3) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOPCTL_MUX(14, 8) /* PIO0_14 */ +#define CTIMER2_MATCH1_PIO0_15 IOPCTL_MUX(15, 4) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG33_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG34_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG35_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG36_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG33_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG34_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG35_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG36_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_15 IOPCTL_MUX(15, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define I2S_BRIDGE_WS_IN_PIO0_15 IOPCTL_MUX(15, 5) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define SCT0_IN0_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN1_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN2_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN3_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN4_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN5_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN6_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_OUT1_PIO0_15 IOPCTL_MUX(15, 3) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOPCTL_MUX(15, 8) /* PIO0_15 */ +#define CTIMER2_MATCH2_PIO0_16 IOPCTL_MUX(16, 4) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG33_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG34_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG35_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG36_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG33_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG34_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG35_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG36_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_16 IOPCTL_MUX(16, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define I2S_BRIDGE_DATA_IN_PIO0_16 IOPCTL_MUX(16, 5) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define SCT0_IN0_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN1_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN2_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN3_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN4_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN5_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN6_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_OUT2_PIO0_16 IOPCTL_MUX(16, 3) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOPCTL_MUX(16, 8) /* PIO0_16 */ +#define CTIMER2_MATCH3_PIO0_17 IOPCTL_MUX(17, 4) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG33_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG34_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG35_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG36_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG33_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG34_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG35_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG36_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define FC2_CTS_SDA_SSEL0_PIO0_17 IOPCTL_MUX(17, 1) /* PIO0_17 */ +#define FC5_SSEL2_PIO0_17 IOPCTL_MUX(17, 5) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_OUT3_PIO0_17 IOPCTL_MUX(17, 3) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOPCTL_MUX(17, 8) /* PIO0_17 */ +#define CTIMER0_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG33_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG34_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG35_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG36_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG33_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG34_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG35_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG36_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define FC2_RTS_SCL_SSEL1_PIO0_18 IOPCTL_MUX(18, 1) /* PIO0_18 */ +#define FC5_SSEL3_PIO0_18 IOPCTL_MUX(18, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define SCT0_IN0_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN1_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN2_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN3_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN4_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN5_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN6_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_OUT6_PIO0_18 IOPCTL_MUX(18, 3) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOPCTL_MUX(18, 8) /* PIO0_18 */ +#define ADC0_CH2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG33_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG34_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG35_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG36_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG33_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG34_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG35_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG36_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define FC2_SSEL2_PIO0_19 IOPCTL_MUX(19, 1) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define SCT0_IN0_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN1_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN2_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN3_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN4_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN5_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN6_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_OUT4_PIO0_19 IOPCTL_MUX(19, 3) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOPCTL_MUX(19, 8) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 5) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_MATCH0_PIO0_21 IOPCTL_MUX(21, 4) /* PIO0_21 */ +#define CTIMER4_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG33_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG34_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG35_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG36_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG33_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG34_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG35_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG36_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define FC3_SCK_PIO0_21 IOPCTL_MUX(21, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_OUT5_PIO0_21 IOPCTL_MUX(21, 3) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOPCTL_MUX(21, 8) /* PIO0_21 */ +#define TRACECLK_PIO0_21 IOPCTL_MUX(21, 6) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_MATCH1_PIO0_22 IOPCTL_MUX(22, 4) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG33_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG34_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG35_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG36_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG33_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG34_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG35_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG36_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_22 IOPCTL_MUX(22, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define SCT0_IN0_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN1_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN2_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN3_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN4_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN5_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN6_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_OUT6_PIO0_22 IOPCTL_MUX(22, 3) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOPCTL_MUX(22, 8) /* PIO0_22 */ +#define SWD_TRACEDATA0_PIO0_22 IOPCTL_MUX(22, 6) /* PIO0_22 */ +#define CTIMER0_MATCH3_PIO0_23 IOPCTL_MUX(23, 5) /* PIO0_23 */ +#define CTIMER3_MATCH2_PIO0_23 IOPCTL_MUX(23, 4) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG33_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG34_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG35_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG36_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG33_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG34_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG35_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG36_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_23 IOPCTL_MUX(23, 1) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define SCT0_IN0_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN1_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN2_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN3_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN4_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN5_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN6_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_OUT8_PIO0_23 IOPCTL_MUX(23, 3) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOPCTL_MUX(23, 8) /* PIO0_23 */ +#define SWD_TRACEDATA1_PIO0_23 IOPCTL_MUX(23, 6) /* PIO0_23 */ +#define CLKOUT_PIO0_24 IOPCTL_MUX(24, 7) /* PIO0_24 */ +#define CTIMER3_MATCH3_PIO0_24 IOPCTL_MUX(24, 4) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG33_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG34_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG35_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG36_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG33_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG34_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG35_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG36_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define FC2_SSEL2_PIO0_24 IOPCTL_MUX(24, 5) /* PIO0_24 */ +#define FC3_CTS_SDA_SSEL0_PIO0_24 IOPCTL_MUX(24, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_OUT9_PIO0_24 IOPCTL_MUX(24, 3) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOPCTL_MUX(24, 8) /* PIO0_24 */ +#define SWD_TRACEDATA2_PIO0_24 IOPCTL_MUX(24, 6) /* PIO0_24 */ +#define CLKIN_PIO0_25 IOPCTL_MUX(25, 7) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG33_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG34_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG35_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG36_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG33_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG34_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG35_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG36_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define FC2_SSEL3_PIO0_25 IOPCTL_MUX(25, 5) /* PIO0_25 */ +#define FC3_RTS_SCL_SSEL1_PIO0_25 IOPCTL_MUX(25, 1) /* PIO0_25 */ +#define FREQME_IN0_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define FREQME_IN1_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOPCTL_MUX(25, 8) /* PIO0_25 */ +#define SWD_TRACEDATA3_PIO0_25 IOPCTL_MUX(25, 6) /* PIO0_25 */ +#define CTIMER4_MATCH0_PIO0_28 IOPCTL_MUX(28, 4) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG33_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG34_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG35_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG36_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG33_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG34_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG35_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG36_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define FC4_SCK_PIO0_28 IOPCTL_MUX(28, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_28 IOPCTL_MUX(28, 5) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOPCTL_MUX(28, 8) /* PIO0_28 */ +#define CTIMER4_MATCH1_PIO0_29 IOPCTL_MUX(29, 4) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG33_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG34_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG35_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG36_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG33_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG34_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG35_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG36_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_29 IOPCTL_MUX(29, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define I2S_BRIDGE_WS_OUT_PIO0_29 IOPCTL_MUX(29, 5) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOPCTL_MUX(29, 8) /* PIO0_29 */ +#define CTIMER4_MATCH2_PIO0_30 IOPCTL_MUX(30, 4) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG33_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG34_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG35_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG36_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG33_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG34_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG35_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG36_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_30 IOPCTL_MUX(30, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_30 IOPCTL_MUX(30, 5) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOPCTL_MUX(30, 8) /* PIO0_30 */ +#define CTIMER4_MATCH3_PIO0_31 IOPCTL_MUX(31, 4) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG33_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG34_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG35_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG36_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG33_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG34_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG35_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG36_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define FC3_SSEL2_PIO0_31 IOPCTL_MUX(31, 5) /* PIO0_31 */ +#define FC4_CTS_SDA_SSEL0_PIO0_31 IOPCTL_MUX(31, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define SCT0_IN0_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN1_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN2_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN3_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN4_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN5_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN6_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_OUT6_PIO0_31 IOPCTL_MUX(31, 3) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOPCTL_MUX(31, 8) /* PIO0_31 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG33_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG34_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG35_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG36_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG33_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG34_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG35_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG36_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define FC3_SSEL3_PIO1_0 IOPCTL_MUX(32, 5) /* PIO1_0 */ +#define FC4_RTS_SCL_SSEL1_PIO1_0 IOPCTL_MUX(32, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_OUT7_PIO1_0 IOPCTL_MUX(32, 3) /* PIO1_0 */ +#define SMARTDMA_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG33_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG34_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG35_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG36_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG33_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG34_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG35_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG36_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define FC5_SCK_PIO1_3 IOPCTL_MUX(35, 1) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define HS_SPI1_SCK_PIO1_3 IOPCTL_MUX(35, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG33_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG34_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG35_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG36_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG33_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG34_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG35_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG36_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define FC5_TXD_SCL_MISO_WS_PIO1_4 IOPCTL_MUX(36, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define HS_SPI1_MISO_PIO1_4 IOPCTL_MUX(36, 6) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG33_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG34_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG35_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG36_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG33_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG34_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG35_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG36_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO1_5 IOPCTL_MUX(37, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define HS_SPI1_MOSI_PIO1_5 IOPCTL_MUX(37, 6) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG33_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG34_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG35_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG36_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG33_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG34_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG35_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG36_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define FC4_SSEL2_PIO1_6 IOPCTL_MUX(38, 5) /* PIO1_6 */ +#define FC5_CTS_SDA_SSEL0_PIO1_6 IOPCTL_MUX(38, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define HS_SPI1_SSELN0_PIO1_6 IOPCTL_MUX(38, 6) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_OUT4_PIO1_6 IOPCTL_MUX(38, 3) /* PIO1_6 */ +#define SMARTDMA_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define CTIMER0_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG33_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG34_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG35_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG36_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG33_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG34_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG35_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG36_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define FC4_SSEL3_PIO1_7 IOPCTL_MUX(39, 5) /* PIO1_7 */ +#define FC5_RTS_SCL_SSEL1_PIO1_7 IOPCTL_MUX(39, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define HS_SPI1_SSELN1_PIO1_7 IOPCTL_MUX(39, 6) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_OUT5_PIO1_7 IOPCTL_MUX(39, 3) /* PIO1_7 */ +#define SMARTDMA_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define CTIMER1_MATCH3_PIO1_9 IOPCTL_MUX(41, 4) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG30_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG31_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG32_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG33_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG34_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG35_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG36_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG20_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG21_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG22_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG23_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG24_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG25_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG26_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG27_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG28_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG29_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG30_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG31_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG32_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG33_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG34_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG35_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG36_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG8_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG9_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define FC5_SSEL3_PIO1_9 IOPCTL_MUX(41, 1) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define HS_SPI1_SSELN3_PIO1_9 IOPCTL_MUX(41, 6) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define SCT0_IN0_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN1_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN2_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN3_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN4_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN5_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN6_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define UTICK0_CAPTURE1_PIO1_9 IOPCTL_MUX(41, 3) /* PIO1_9 */ +#define CTIMER2_MATCH0_PIO1_11 IOPCTL_MUX(43, 4) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG33_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG34_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG35_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG36_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG33_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG34_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG35_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG36_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define HS_SPI0_SCK_PIO1_11 IOPCTL_MUX(43, 1) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define CTIMER2_MATCH1_PIO1_12 IOPCTL_MUX(44, 4) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG33_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG34_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG35_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG36_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG33_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG34_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG35_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG36_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define HS_SPI0_MISO_PIO1_12 IOPCTL_MUX(44, 1) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define CTIMER2_MATCH2_PIO1_13 IOPCTL_MUX(45, 4) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG33_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG34_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG35_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG36_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG33_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG34_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG35_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG36_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define HS_SPI0_MOSI_PIO1_13 IOPCTL_MUX(45, 1) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define CTIMER2_MATCH3_PIO1_14 IOPCTL_MUX(46, 4) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG33_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG34_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG35_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG36_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG33_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG34_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG35_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG36_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define HS_SPI0_SSELN0_PIO1_14 IOPCTL_MUX(46, 1) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define CTIMER3_MATCH0_PIO1_15 IOPCTL_MUX(47, 4) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG33_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG34_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG35_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG36_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG33_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG34_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG35_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG36_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define HS_SPI0_SSELN1_PIO1_15 IOPCTL_MUX(47, 1) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define CTIMER3_MATCH3_PIO1_18 IOPCTL_MUX(50, 4) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG33_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG34_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG35_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG36_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG33_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG34_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG35_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG36_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define FLEXSPI0_SCLK_PIO1_18 IOPCTL_MUX(50, 1) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define SCT0_IN0_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN1_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN2_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN3_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN4_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN5_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN6_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define CLKOUT_PIO1_19 IOPCTL_MUX(51, 7) /* PIO1_19 */ +#define CTIMER4_MATCH0_PIO1_19 IOPCTL_MUX(51, 4) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG33_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG34_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG35_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG36_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG33_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG34_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG35_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG36_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define FLEXSPI0_SS0_N_PIO1_19 IOPCTL_MUX(51, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define SCT0_OUT0_PIO1_19 IOPCTL_MUX(51, 2) /* PIO1_19 */ +#define CTIMER4_MATCH1_PIO1_20 IOPCTL_MUX(52, 4) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG33_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG34_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG35_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG36_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG33_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG34_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG35_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG36_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define FLEXSPI0_DATA0_PIO1_20 IOPCTL_MUX(52, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define SCT0_IN0_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN1_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN2_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN3_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN4_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN5_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN6_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define CTIMER4_MATCH2_PIO1_21 IOPCTL_MUX(53, 4) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG33_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG34_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG35_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG36_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG33_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG34_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG35_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG36_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define FLEXSPI0_DATA1_PIO1_21 IOPCTL_MUX(53, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define SCT0_OUT1_PIO1_21 IOPCTL_MUX(53, 2) /* PIO1_21 */ +#define CTIMER4_MATCH3_PIO1_22 IOPCTL_MUX(54, 4) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG33_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG34_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG35_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG36_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG33_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG34_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG35_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG36_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define FLEXSPI0_DATA2_PIO1_22 IOPCTL_MUX(54, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define CTIMER0_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG33_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG34_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG35_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG36_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG33_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG34_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG35_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG36_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define FLEXSPI0_DATA3_PIO1_23 IOPCTL_MUX(55, 1) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define SCT0_OUT2_PIO1_23 IOPCTL_MUX(55, 2) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG33_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG34_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG35_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG36_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG33_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG34_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG35_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG36_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define FLEXSPI0_DQS_PIO1_28 IOPCTL_MUX(60, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define SCT0_IN0_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN1_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN2_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN3_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN4_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN5_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN6_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define ACMP0_ACMP_IN1_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define CTIMER0_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define FLEXIO0_TRIG1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define PIN_32KHZ_CLKOUT_PIO2_14 IOPCTL_MUX(78, 7) /* PIO2_14 */ +#define SCT0_OUT8_PIO2_14 IOPCTL_MUX(78, 2) /* PIO2_14 */ +#define SMARTDMA_SMARTDMA_PIO14_PIO2_14 IOPCTL_MUX(78, 15) /* PIO2_14 */ +#define ACMP0_ACMP_IN4_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define CLKIN_PIO2_15 IOPCTL_MUX(79, 7) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define SCT0_OUT9_PIO2_15 IOPCTL_MUX(79, 2) /* PIO2_15 */ +#define SMARTDMA_SMARTDMA_PIO15_PIO2_15 IOPCTL_MUX(79, 15) /* PIO2_15 */ +#define GPIO_INT_BMAT_PIO2_24 IOPCTL_MUX(88, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOPCTL_MUX(88, 0) /* PIO2_24 */ +#define SMARTDMA_SMARTDMA_PIO24_PIO2_24 IOPCTL_MUX(88, 15) /* PIO2_24 */ +#define SWO_PIO2_24 IOPCTL_MUX(88, 1) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOPCTL_MUX(89, 0) /* PIO2_25 */ +#define SMARTDMA_SMARTDMA_PIO25_PIO2_25 IOPCTL_MUX(89, 15) /* PIO2_25 */ +#define SWCLK_PIO2_25 IOPCTL_MUX(89, 1) /* PIO2_25 */ +#define GPIO_PIO226_PIO2_26 IOPCTL_MUX(90, 0) /* PIO2_26 */ +#define SMARTDMA_SMARTDMA_PIO26_PIO2_26 IOPCTL_MUX(90, 15) /* PIO2_26 */ +#define SWDIO_PIO2_26 IOPCTL_MUX(90, 1) /* PIO2_26 */ +#define GPIO_PIO227_PIO2_27 IOPCTL_MUX(91, 0) /* PIO2_27 */ +#define SMARTDMA_SMARTDMA_PIO27_PIO2_27 IOPCTL_MUX(91, 15) /* PIO2_27 */ +#define USB1_OVERCURRENTN_PIO2_27 IOPCTL_MUX(91, 1) /* PIO2_27 */ +#define CLKOUT_PIO2_29 IOPCTL_MUX(93, 5) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOPCTL_MUX(93, 0) /* PIO2_29 */ +#define I3C0_SCL_PIO2_29 IOPCTL_MUX(93, 1) /* PIO2_29 */ +#define SCT0_OUT0_PIO2_29 IOPCTL_MUX(93, 2) /* PIO2_29 */ +#define SMARTDMA_SMARTDMA_PIO29_PIO2_29 IOPCTL_MUX(93, 15) /* PIO2_29 */ +#define CLKIN_PIO2_30 IOPCTL_MUX(94, 5) /* PIO2_30 */ +#define CMP0_OUT_PIO2_30 IOPCTL_MUX(94, 7) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOPCTL_MUX(94, 0) /* PIO2_30 */ +#define I3C0_SDA_PIO2_30 IOPCTL_MUX(94, 1) /* PIO2_30 */ +#define SCT0_OUT3_PIO2_30 IOPCTL_MUX(94, 2) /* PIO2_30 */ +#define SMARTDMA_SMARTDMA_PIO30_PIO2_30 IOPCTL_MUX(94, 15) /* PIO2_30 */ +#define ACMP0_ACMP_IN2_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define CTIMER0_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define GPIO_PIO231_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define I3C0_PUR_PIO2_31 IOPCTL_MUX(95, 1) /* PIO2_31 */ +#define SCT0_OUT7_PIO2_31 IOPCTL_MUX(95, 2) /* PIO2_31 */ +#define SMARTDMA_SMARTDMA_PIO31_PIO2_31 IOPCTL_MUX(95, 15) /* PIO2_31 */ +#define SWO_PIO2_31 IOPCTL_MUX(95, 5) /* PIO2_31 */ +#define UTICK0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 3) /* PIO2_31 */ +#define FC6_CTS_SDA_SSEL0_PIO3_28 IOPCTL_MUX(124, 1) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOPCTL_MUX(124, 0) /* PIO3_28 */ +#define FC6_RTS_SCL_SSEL1_PIO3_29 IOPCTL_MUX(125, 1) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOPCTL_MUX(125, 0) /* PIO3_29 */ +#define FC11_SCK_PIO4_20 IOPCTL_MUX(148, 6) /* PIO4_20 */ +#define FLEXIO0_IO0_PIO4_20 IOPCTL_MUX(148, 8) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOPCTL_MUX(148, 0) /* PIO4_20 */ +#define USDHC1_USDHC_DATA6_PIO4_20 IOPCTL_MUX(148, 4) /* PIO4_20 */ +#define FC11_TXD_SCL_MISO_PIO4_21 IOPCTL_MUX(149, 6) /* PIO4_21 */ +#define FLEXIO0_IO1_PIO4_21 IOPCTL_MUX(149, 8) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOPCTL_MUX(149, 0) /* PIO4_21 */ +#define USDHC1_USDHC_DATA7_PIO4_21 IOPCTL_MUX(149, 4) /* PIO4_21 */ +#define FC11_RXD_SDA_MOSI_PIO4_22 IOPCTL_MUX(150, 6) /* PIO4_22 */ +#define FLEXIO0_IO2_PIO4_22 IOPCTL_MUX(150, 8) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOPCTL_MUX(150, 0) /* PIO4_22 */ +#define SD1_CARD_DET_N_PIO4_22 IOPCTL_MUX(150, 4) /* PIO4_22 */ +#define FC11_CTS_SDA_SSELN0_PIO4_23 IOPCTL_MUX(151, 6) /* PIO4_23 */ +#define FLEXIO0_IO3_PIO4_23 IOPCTL_MUX(151, 8) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOPCTL_MUX(151, 0) /* PIO4_23 */ +#define SD1_RESET_N_PIO4_23 IOPCTL_MUX(151, 4) /* PIO4_23 */ +#define TRACECLK_PIO4_23 IOPCTL_MUX(151, 7) /* PIO4_23 */ +#define FC11_RTS_SCL_SSELN1_PIO4_24 IOPCTL_MUX(152, 6) /* PIO4_24 */ +#define FLEXIO0_IO4_PIO4_24 IOPCTL_MUX(152, 8) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOPCTL_MUX(152, 0) /* PIO4_24 */ +#define SD1_VOLT_PIO4_24 IOPCTL_MUX(152, 4) /* PIO4_24 */ +#define SWD_TRACEDATA0_PIO4_24 IOPCTL_MUX(152, 7) /* PIO4_24 */ +#define FC11_SSELN2_PIO4_25 IOPCTL_MUX(153, 6) /* PIO4_25 */ +#define FLEXIO0_IO5_PIO4_25 IOPCTL_MUX(153, 8) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOPCTL_MUX(153, 0) /* PIO4_25 */ +#define SWD_TRACEDATA1_PIO4_25 IOPCTL_MUX(153, 7) /* PIO4_25 */ +#define FC11_SSELN3_PIO4_26 IOPCTL_MUX(154, 6) /* PIO4_26 */ +#define FLEXIO0_IO6_PIO4_26 IOPCTL_MUX(154, 8) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOPCTL_MUX(154, 0) /* PIO4_26 */ +#define SWD_TRACEDATA2_PIO4_26 IOPCTL_MUX(154, 7) /* PIO4_26 */ +#define FLEXIO0_IO7_PIO4_27 IOPCTL_MUX(155, 8) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOPCTL_MUX(155, 0) /* PIO4_27 */ +#define SWD_TRACEDATA3_PIO4_27 IOPCTL_MUX(155, 7) /* PIO4_27 */ +#define FLEXIO0_IO8_PIO4_28 IOPCTL_MUX(156, 8) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOPCTL_MUX(156, 0) /* PIO4_28 */ +#define FC12_SCK_PIO4_29 IOPCTL_MUX(157, 6) /* PIO4_29 */ +#define FLEXIO0_IO9_PIO4_29 IOPCTL_MUX(157, 8) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOPCTL_MUX(157, 0) /* PIO4_29 */ +#define FC12_TXD_SCL_MISO_PIO4_30 IOPCTL_MUX(158, 6) /* PIO4_30 */ +#define FLEXIO0_IO10_PIO4_30 IOPCTL_MUX(158, 8) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOPCTL_MUX(158, 0) /* PIO4_30 */ +#define FC12_RXD_SDA_MOSI_PIO4_31 IOPCTL_MUX(159, 6) /* PIO4_31 */ +#define FLEXIO0_IO11_PIO4_31 IOPCTL_MUX(159, 8) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOPCTL_MUX(159, 0) /* PIO4_31 */ +#define DMIC0_CLK01_PIO5_4 IOPCTL_MUX(164, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOPCTL_MUX(164, 0) /* PIO5_4 */ +#define DMIC0_DATA01_PIO5_8 IOPCTL_MUX(168, 4) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOPCTL_MUX(168, 0) /* PIO5_8 */ +#define GPIO_PIO627_PIO6_27 IOPCTL_MUX(219, 0) /* PIO6_27 */ +#define MCLK_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN0_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN1_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN2_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN3_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN4_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN5_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN6_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ + +#endif diff --git a/dts/nxp/nxp_imx/rt/MIMXRT533SFFOC-pinctrl.h b/dts/nxp/nxp_imx/rt/MIMXRT533SFFOC-pinctrl.h new file mode 100644 index 000000000..5bed9a5b3 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/MIMXRT533SFFOC-pinctrl.h @@ -0,0 +1,5843 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from MIMXRT533SFFOC/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MIMXRT533SFFOC_ +#define _ZEPHYR_DTS_BINDING_MIMXRT533SFFOC_ + +#define IOPCTL_MUX(offset, mux) \ + ((((offset) & 0xFFF) << 20) | \ + (((mux) & 0xF) << 0)) + +#define CTIMER0_MATCH0_PIO0_0 IOPCTL_MUX(0, 4) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG33_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG34_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG35_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG36_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG33_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG34_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG35_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG36_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define FC0_SCK_PIO0_0 IOPCTL_MUX(0, 1) /* PIO0_0 */ +#define GPIO_INT_BMAT_PIO0_0 IOPCTL_MUX(0, 6) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define I2S_BRIDGE_CLK_IN_PIO0_0 IOPCTL_MUX(0, 5) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOPCTL_MUX(0, 8) /* PIO0_0 */ +#define SMARTDMA_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PMIC_I2C_SDA IOPCTL_MUX(257, 0) /* PIO0_0 */ +#define PMIC_I2C_SCL IOPCTL_MUX(256, 0) /* PIO0_0 */ +#define CTIMER0_MATCH1_PIO0_1 IOPCTL_MUX(1, 4) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG33_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG34_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG35_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG36_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG33_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG34_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG35_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG36_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_1 IOPCTL_MUX(1, 1) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define I2S_BRIDGE_WS_IN_PIO0_1 IOPCTL_MUX(1, 5) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOPCTL_MUX(1, 8) /* PIO0_1 */ +#define SMARTDMA_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define CTIMER0_MATCH2_PIO0_2 IOPCTL_MUX(2, 4) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG33_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG34_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG35_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG36_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG33_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG34_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG35_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG36_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_2 IOPCTL_MUX(2, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define I2S_BRIDGE_DATA_IN_PIO0_2 IOPCTL_MUX(2, 5) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOPCTL_MUX(2, 8) /* PIO0_2 */ +#define SMARTDMA_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define CTIMER0_MATCH3_PIO0_3 IOPCTL_MUX(3, 4) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG33_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG34_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG35_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG36_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG33_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG34_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG35_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG36_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define FC0_CTS_SDA_SSEL0_PIO0_3 IOPCTL_MUX(3, 1) /* PIO0_3 */ +#define FC1_SSEL2_PIO0_3 IOPCTL_MUX(3, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOPCTL_MUX(3, 8) /* PIO0_3 */ +#define SMARTDMA_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define CMP0_OUT_PIO0_4 IOPCTL_MUX(4, 7) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG33_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG34_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG35_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG36_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG33_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG34_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG35_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG36_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define FC0_RTS_SCL_SSEL1_PIO0_4 IOPCTL_MUX(4, 1) /* PIO0_4 */ +#define FC1_SSEL3_PIO0_4 IOPCTL_MUX(4, 5) /* PIO0_4 */ +#define FLEXIO0_TRIG0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOPCTL_MUX(4, 8) /* PIO0_4 */ +#define SMARTDMA_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define ADC0_CH0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG33_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG34_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG35_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG36_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG33_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG34_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG35_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG36_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define FC0_SSEL2_PIO0_5 IOPCTL_MUX(5, 1) /* PIO0_5 */ +#define FLEXIO0_TRIG1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_OUT0_PIO0_5 IOPCTL_MUX(5, 3) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOPCTL_MUX(5, 8) /* PIO0_5 */ +#define SMARTDMA_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define ADC0_CH8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER0_MATCH0_PIO0_6 IOPCTL_MUX(6, 4) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG33_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG34_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG35_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG36_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG33_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG34_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG35_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG36_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define FC0_SSEL3_PIO0_6 IOPCTL_MUX(6, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_OUT1_PIO0_6 IOPCTL_MUX(6, 3) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOPCTL_MUX(6, 8) /* PIO0_6 */ +#define SMARTDMA_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER1_MATCH0_PIO0_7 IOPCTL_MUX(7, 4) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG33_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG34_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG35_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG36_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG33_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG34_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG35_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG36_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOPCTL_MUX(7, 1) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_7 IOPCTL_MUX(7, 5) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SCT0_IN0_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN1_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN2_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN3_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN4_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN5_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN6_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_OUT4_PIO0_7 IOPCTL_MUX(7, 3) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOPCTL_MUX(7, 8) /* PIO0_7 */ +#define SMARTDMA_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define CTIMER1_MATCH1_PIO0_8 IOPCTL_MUX(8, 4) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG33_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG34_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG35_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG36_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG33_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG34_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG35_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG36_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_8 IOPCTL_MUX(8, 1) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define I2S_BRIDGE_WS_OUT_PIO0_8 IOPCTL_MUX(8, 5) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define SCT0_IN0_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN1_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN2_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN3_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN4_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN5_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN6_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_OUT5_PIO0_8 IOPCTL_MUX(8, 3) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOPCTL_MUX(8, 8) /* PIO0_8 */ +#define CTIMER1_MATCH2_PIO0_9 IOPCTL_MUX(9, 4) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG33_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG34_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG35_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG36_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG33_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG34_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG35_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG36_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_9 IOPCTL_MUX(9, 1) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_9 IOPCTL_MUX(9, 5) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define SCT0_IN0_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN1_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN2_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN3_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN4_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN5_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN6_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_OUT6_PIO0_9 IOPCTL_MUX(9, 3) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOPCTL_MUX(9, 8) /* PIO0_9 */ +#define CTIMER1_MATCH3_PIO0_10 IOPCTL_MUX(10, 4) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG33_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG34_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG35_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG36_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG33_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG34_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG35_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG36_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define FC0_SSEL2_PIO0_10 IOPCTL_MUX(10, 5) /* PIO0_10 */ +#define FC1_CTS_SDA_SSEL0_PIO0_10 IOPCTL_MUX(10, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define SCT0_IN0_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN1_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN2_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN3_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN4_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN5_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN6_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_OUT7_PIO0_10 IOPCTL_MUX(10, 3) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOPCTL_MUX(10, 8) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG33_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG34_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG35_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG36_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG33_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG34_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG35_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG36_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define FC0_SSEL3_PIO0_11 IOPCTL_MUX(11, 5) /* PIO0_11 */ +#define FC1_RTS_SCL_SSEL1_PIO0_11 IOPCTL_MUX(11, 1) /* PIO0_11 */ +#define FLEXIO0_TRIG2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define SCT0_IN0_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN1_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN2_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN3_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN4_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN5_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN6_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_OUT8_PIO0_11 IOPCTL_MUX(11, 3) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOPCTL_MUX(11, 8) /* PIO0_11 */ +#define ADC0_CH1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG33_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG34_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG35_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG36_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG33_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG34_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG35_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG36_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define FC1_SSEL2_PIO0_12 IOPCTL_MUX(12, 1) /* PIO0_12 */ +#define FLEXIO0_TRIG3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_OUT2_PIO0_12 IOPCTL_MUX(12, 3) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOPCTL_MUX(12, 8) /* PIO0_12 */ +#define ADC0_CH9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define CTIMER0_MATCH1_PIO0_13 IOPCTL_MUX(13, 4) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG33_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG34_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG35_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG36_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG33_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG34_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG35_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG36_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define FC1_SSEL3_PIO0_13 IOPCTL_MUX(13, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_OUT3_PIO0_13 IOPCTL_MUX(13, 3) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOPCTL_MUX(13, 8) /* PIO0_13 */ +#define CTIMER2_MATCH0_PIO0_14 IOPCTL_MUX(14, 4) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG33_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG34_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG35_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG36_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG33_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG34_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG35_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG36_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define FC2_SCK_PIO0_14 IOPCTL_MUX(14, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define I2S_BRIDGE_CLK_IN_PIO0_14 IOPCTL_MUX(14, 5) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_OUT0_PIO0_14 IOPCTL_MUX(14, 3) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOPCTL_MUX(14, 8) /* PIO0_14 */ +#define CTIMER2_MATCH1_PIO0_15 IOPCTL_MUX(15, 4) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG33_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG34_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG35_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG36_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG33_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG34_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG35_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG36_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_15 IOPCTL_MUX(15, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define I2S_BRIDGE_WS_IN_PIO0_15 IOPCTL_MUX(15, 5) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define SCT0_IN0_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN1_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN2_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN3_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN4_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN5_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN6_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_OUT1_PIO0_15 IOPCTL_MUX(15, 3) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOPCTL_MUX(15, 8) /* PIO0_15 */ +#define CTIMER2_MATCH2_PIO0_16 IOPCTL_MUX(16, 4) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG33_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG34_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG35_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG36_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG33_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG34_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG35_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG36_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_16 IOPCTL_MUX(16, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define I2S_BRIDGE_DATA_IN_PIO0_16 IOPCTL_MUX(16, 5) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define SCT0_IN0_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN1_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN2_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN3_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN4_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN5_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN6_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_OUT2_PIO0_16 IOPCTL_MUX(16, 3) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOPCTL_MUX(16, 8) /* PIO0_16 */ +#define CTIMER2_MATCH3_PIO0_17 IOPCTL_MUX(17, 4) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG33_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG34_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG35_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG36_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG33_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG34_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG35_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG36_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define FC2_CTS_SDA_SSEL0_PIO0_17 IOPCTL_MUX(17, 1) /* PIO0_17 */ +#define FC5_SSEL2_PIO0_17 IOPCTL_MUX(17, 5) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_OUT3_PIO0_17 IOPCTL_MUX(17, 3) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOPCTL_MUX(17, 8) /* PIO0_17 */ +#define CTIMER0_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG33_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG34_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG35_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG36_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG33_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG34_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG35_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG36_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define FC2_RTS_SCL_SSEL1_PIO0_18 IOPCTL_MUX(18, 1) /* PIO0_18 */ +#define FC5_SSEL3_PIO0_18 IOPCTL_MUX(18, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define SCT0_IN0_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN1_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN2_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN3_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN4_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN5_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN6_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_OUT6_PIO0_18 IOPCTL_MUX(18, 3) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOPCTL_MUX(18, 8) /* PIO0_18 */ +#define ADC0_CH2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG33_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG34_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG35_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG36_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG33_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG34_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG35_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG36_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define FC2_SSEL2_PIO0_19 IOPCTL_MUX(19, 1) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define SCT0_IN0_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN1_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN2_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN3_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN4_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN5_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN6_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_OUT4_PIO0_19 IOPCTL_MUX(19, 3) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOPCTL_MUX(19, 8) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 5) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_MATCH0_PIO0_21 IOPCTL_MUX(21, 4) /* PIO0_21 */ +#define CTIMER4_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG33_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG34_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG35_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG36_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG33_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG34_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG35_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG36_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define FC3_SCK_PIO0_21 IOPCTL_MUX(21, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_OUT5_PIO0_21 IOPCTL_MUX(21, 3) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOPCTL_MUX(21, 8) /* PIO0_21 */ +#define TRACECLK_PIO0_21 IOPCTL_MUX(21, 6) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_MATCH1_PIO0_22 IOPCTL_MUX(22, 4) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG33_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG34_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG35_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG36_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG33_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG34_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG35_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG36_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_22 IOPCTL_MUX(22, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define SCT0_IN0_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN1_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN2_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN3_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN4_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN5_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN6_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_OUT6_PIO0_22 IOPCTL_MUX(22, 3) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOPCTL_MUX(22, 8) /* PIO0_22 */ +#define SWD_TRACEDATA0_PIO0_22 IOPCTL_MUX(22, 6) /* PIO0_22 */ +#define CTIMER0_MATCH3_PIO0_23 IOPCTL_MUX(23, 5) /* PIO0_23 */ +#define CTIMER3_MATCH2_PIO0_23 IOPCTL_MUX(23, 4) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG33_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG34_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG35_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG36_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG33_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG34_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG35_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG36_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_23 IOPCTL_MUX(23, 1) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define SCT0_IN0_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN1_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN2_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN3_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN4_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN5_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN6_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_OUT8_PIO0_23 IOPCTL_MUX(23, 3) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOPCTL_MUX(23, 8) /* PIO0_23 */ +#define SWD_TRACEDATA1_PIO0_23 IOPCTL_MUX(23, 6) /* PIO0_23 */ +#define CLKOUT_PIO0_24 IOPCTL_MUX(24, 7) /* PIO0_24 */ +#define CTIMER3_MATCH3_PIO0_24 IOPCTL_MUX(24, 4) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG33_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG34_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG35_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG36_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG33_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG34_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG35_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG36_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define FC2_SSEL2_PIO0_24 IOPCTL_MUX(24, 5) /* PIO0_24 */ +#define FC3_CTS_SDA_SSEL0_PIO0_24 IOPCTL_MUX(24, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_OUT9_PIO0_24 IOPCTL_MUX(24, 3) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOPCTL_MUX(24, 8) /* PIO0_24 */ +#define SWD_TRACEDATA2_PIO0_24 IOPCTL_MUX(24, 6) /* PIO0_24 */ +#define CLKIN_PIO0_25 IOPCTL_MUX(25, 7) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG33_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG34_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG35_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG36_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG33_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG34_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG35_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG36_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define FC2_SSEL3_PIO0_25 IOPCTL_MUX(25, 5) /* PIO0_25 */ +#define FC3_RTS_SCL_SSEL1_PIO0_25 IOPCTL_MUX(25, 1) /* PIO0_25 */ +#define FREQME_IN0_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define FREQME_IN1_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOPCTL_MUX(25, 8) /* PIO0_25 */ +#define SWD_TRACEDATA3_PIO0_25 IOPCTL_MUX(25, 6) /* PIO0_25 */ +#define CTIMER4_MATCH0_PIO0_28 IOPCTL_MUX(28, 4) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG33_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG34_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG35_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG36_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG33_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG34_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG35_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG36_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define FC4_SCK_PIO0_28 IOPCTL_MUX(28, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_28 IOPCTL_MUX(28, 5) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOPCTL_MUX(28, 8) /* PIO0_28 */ +#define CTIMER4_MATCH1_PIO0_29 IOPCTL_MUX(29, 4) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG33_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG34_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG35_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG36_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG33_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG34_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG35_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG36_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_29 IOPCTL_MUX(29, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define I2S_BRIDGE_WS_OUT_PIO0_29 IOPCTL_MUX(29, 5) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOPCTL_MUX(29, 8) /* PIO0_29 */ +#define CTIMER4_MATCH2_PIO0_30 IOPCTL_MUX(30, 4) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG33_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG34_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG35_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG36_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG33_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG34_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG35_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG36_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_30 IOPCTL_MUX(30, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_30 IOPCTL_MUX(30, 5) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOPCTL_MUX(30, 8) /* PIO0_30 */ +#define CTIMER4_MATCH3_PIO0_31 IOPCTL_MUX(31, 4) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG33_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG34_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG35_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG36_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG33_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG34_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG35_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG36_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define FC3_SSEL2_PIO0_31 IOPCTL_MUX(31, 5) /* PIO0_31 */ +#define FC4_CTS_SDA_SSEL0_PIO0_31 IOPCTL_MUX(31, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define SCT0_IN0_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN1_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN2_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN3_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN4_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN5_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN6_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_OUT6_PIO0_31 IOPCTL_MUX(31, 3) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOPCTL_MUX(31, 8) /* PIO0_31 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG33_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG34_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG35_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG36_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG33_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG34_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG35_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG36_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define FC3_SSEL3_PIO1_0 IOPCTL_MUX(32, 5) /* PIO1_0 */ +#define FC4_RTS_SCL_SSEL1_PIO1_0 IOPCTL_MUX(32, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_OUT7_PIO1_0 IOPCTL_MUX(32, 3) /* PIO1_0 */ +#define SMARTDMA_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG33_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG34_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG35_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG36_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG33_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG34_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG35_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG36_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define FC5_SCK_PIO1_3 IOPCTL_MUX(35, 1) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define HS_SPI1_SCK_PIO1_3 IOPCTL_MUX(35, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG33_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG34_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG35_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG36_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG33_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG34_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG35_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG36_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define FC5_TXD_SCL_MISO_WS_PIO1_4 IOPCTL_MUX(36, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define HS_SPI1_MISO_PIO1_4 IOPCTL_MUX(36, 6) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG33_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG34_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG35_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG36_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG33_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG34_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG35_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG36_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO1_5 IOPCTL_MUX(37, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define HS_SPI1_MOSI_PIO1_5 IOPCTL_MUX(37, 6) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG33_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG34_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG35_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG36_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG33_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG34_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG35_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG36_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define FC4_SSEL2_PIO1_6 IOPCTL_MUX(38, 5) /* PIO1_6 */ +#define FC5_CTS_SDA_SSEL0_PIO1_6 IOPCTL_MUX(38, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define HS_SPI1_SSELN0_PIO1_6 IOPCTL_MUX(38, 6) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_OUT4_PIO1_6 IOPCTL_MUX(38, 3) /* PIO1_6 */ +#define SMARTDMA_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define CTIMER0_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG33_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG34_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG35_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG36_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG33_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG34_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG35_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG36_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define FC4_SSEL3_PIO1_7 IOPCTL_MUX(39, 5) /* PIO1_7 */ +#define FC5_RTS_SCL_SSEL1_PIO1_7 IOPCTL_MUX(39, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define HS_SPI1_SSELN1_PIO1_7 IOPCTL_MUX(39, 6) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_OUT5_PIO1_7 IOPCTL_MUX(39, 3) /* PIO1_7 */ +#define SMARTDMA_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define CLKOUT_PIO1_10 IOPCTL_MUX(42, 7) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG30_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG31_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG32_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG33_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG34_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG35_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG36_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG20_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG21_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG22_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG23_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG24_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG25_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG26_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG27_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG28_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG29_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG30_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG31_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG32_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG33_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG34_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG35_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG36_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG8_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG9_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define FREQME_IN0_PIO1_10 IOPCTL_MUX(42, 3) /* PIO1_10 */ +#define FREQME_IN1_PIO1_10 IOPCTL_MUX(42, 3) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define MCLK_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define SCT0_IN0_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN1_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN2_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN3_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN4_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN5_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN6_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define CTIMER2_MATCH0_PIO1_11 IOPCTL_MUX(43, 4) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG33_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG34_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG35_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG36_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG33_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG34_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG35_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG36_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define HS_SPI0_SCK_PIO1_11 IOPCTL_MUX(43, 1) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define CTIMER2_MATCH1_PIO1_12 IOPCTL_MUX(44, 4) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG33_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG34_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG35_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG36_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG33_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG34_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG35_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG36_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define HS_SPI0_MISO_PIO1_12 IOPCTL_MUX(44, 1) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define CTIMER2_MATCH2_PIO1_13 IOPCTL_MUX(45, 4) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG33_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG34_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG35_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG36_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG33_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG34_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG35_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG36_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define HS_SPI0_MOSI_PIO1_13 IOPCTL_MUX(45, 1) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define CTIMER2_MATCH3_PIO1_14 IOPCTL_MUX(46, 4) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG33_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG34_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG35_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG36_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG33_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG34_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG35_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG36_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define HS_SPI0_SSELN0_PIO1_14 IOPCTL_MUX(46, 1) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define CTIMER3_MATCH0_PIO1_15 IOPCTL_MUX(47, 4) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG33_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG34_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG35_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG36_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG33_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG34_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG35_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG36_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define HS_SPI0_SSELN1_PIO1_15 IOPCTL_MUX(47, 1) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define CTIMER3_MATCH3_PIO1_18 IOPCTL_MUX(50, 4) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG33_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG34_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG35_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG36_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG33_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG34_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG35_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG36_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define FLEXSPI0_SCLK_PIO1_18 IOPCTL_MUX(50, 1) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define SCT0_IN0_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN1_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN2_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN3_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN4_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN5_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN6_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define CLKOUT_PIO1_19 IOPCTL_MUX(51, 7) /* PIO1_19 */ +#define CTIMER4_MATCH0_PIO1_19 IOPCTL_MUX(51, 4) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG33_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG34_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG35_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG36_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG33_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG34_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG35_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG36_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define FLEXSPI0_SS0_N_PIO1_19 IOPCTL_MUX(51, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define SCT0_OUT0_PIO1_19 IOPCTL_MUX(51, 2) /* PIO1_19 */ +#define CTIMER4_MATCH1_PIO1_20 IOPCTL_MUX(52, 4) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG33_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG34_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG35_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG36_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG33_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG34_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG35_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG36_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define FLEXSPI0_DATA0_PIO1_20 IOPCTL_MUX(52, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define SCT0_IN0_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN1_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN2_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN3_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN4_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN5_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN6_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define CTIMER4_MATCH2_PIO1_21 IOPCTL_MUX(53, 4) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG33_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG34_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG35_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG36_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG33_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG34_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG35_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG36_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define FLEXSPI0_DATA1_PIO1_21 IOPCTL_MUX(53, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define SCT0_OUT1_PIO1_21 IOPCTL_MUX(53, 2) /* PIO1_21 */ +#define CTIMER4_MATCH3_PIO1_22 IOPCTL_MUX(54, 4) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG33_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG34_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG35_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG36_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG33_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG34_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG35_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG36_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define FLEXSPI0_DATA2_PIO1_22 IOPCTL_MUX(54, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define CTIMER0_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG33_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG34_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG35_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG36_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG33_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG34_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG35_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG36_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define FLEXSPI0_DATA3_PIO1_23 IOPCTL_MUX(55, 1) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define SCT0_OUT2_PIO1_23 IOPCTL_MUX(55, 2) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG30_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG31_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG32_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG33_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG34_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG35_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG36_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG20_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG21_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG22_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG23_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG24_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG25_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG26_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG27_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG28_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG29_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG30_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG31_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG32_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG33_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG34_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG35_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG36_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG8_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG9_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define FLEXSPI0_DATA4_PIO1_24 IOPCTL_MUX(56, 1) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define SCT0_IN0_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN1_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN2_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN3_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN4_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN5_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN6_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG30_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG31_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG32_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG33_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG34_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG35_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG36_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG20_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG21_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG22_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG23_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG24_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG25_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG26_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG27_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG28_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG29_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG30_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG31_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG32_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG33_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG34_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG35_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG36_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG8_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG9_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define FLEXSPI0_DATA5_PIO1_25 IOPCTL_MUX(57, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define SCT0_OUT3_PIO1_25 IOPCTL_MUX(57, 2) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG30_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG31_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG32_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG33_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG34_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG35_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG36_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG20_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG21_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG22_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG23_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG24_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG25_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG26_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG27_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG28_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG29_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG30_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG31_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG32_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG33_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG34_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG35_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG36_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG8_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG9_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define FLEXSPI0_DATA6_PIO1_26 IOPCTL_MUX(58, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define SCT0_IN0_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN1_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN2_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN3_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN4_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN5_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN6_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG30_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG31_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG32_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG33_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG34_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG35_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG36_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG20_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG21_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG22_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG23_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG24_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG25_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG26_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG27_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG28_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG29_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG30_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG31_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG32_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG33_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG34_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG35_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG36_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG8_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG9_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define FLEXSPI0_DATA7_PIO1_27 IOPCTL_MUX(59, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define SCT0_OUT4_PIO1_27 IOPCTL_MUX(59, 2) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG33_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG34_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG35_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG36_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG33_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG34_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG35_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG36_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define FLEXSPI0_DQS_PIO1_28 IOPCTL_MUX(60, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define SCT0_IN0_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN1_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN2_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN3_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN4_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN5_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN6_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define CTIMER0_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG30_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG31_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG32_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG33_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG34_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG35_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG36_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG20_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG21_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG22_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG23_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG24_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG25_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG26_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG27_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG28_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG29_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG30_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG31_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG32_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG33_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG34_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG35_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG36_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG8_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG9_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define FLEXSPI0_SCLK_N_PIO1_29 IOPCTL_MUX(61, 5) /* PIO1_29 */ +#define FLEXSPI0_SS1_N_PIO1_29 IOPCTL_MUX(61, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define SCT0_OUT5_PIO1_29 IOPCTL_MUX(61, 2) /* PIO1_29 */ +#define UTICK0_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 3) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG30_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG31_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG32_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG33_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG34_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG35_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG36_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG20_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG21_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG22_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG23_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG24_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG25_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG26_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG27_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG28_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG29_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG30_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG31_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG32_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG33_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG34_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG35_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG36_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG8_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG9_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SD0_CLK_PIO1_30 IOPCTL_MUX(62, 1) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG30_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG31_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG32_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG33_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG34_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG35_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG36_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG20_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG21_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG22_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG23_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG24_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG25_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG26_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG27_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG28_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG29_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG30_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG31_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG32_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG33_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG34_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG35_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG36_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG8_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG9_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define SCT0_IN0_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN1_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN2_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN3_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN4_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN5_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN6_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SD0_CMD_PIO1_31 IOPCTL_MUX(63, 1) /* PIO1_31 */ +#define GPIO_PIO20_PIO2_0 IOPCTL_MUX(64, 0) /* PIO2_0 */ +#define SCT0_IN0_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN1_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN2_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN3_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN4_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN5_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN6_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SMARTDMA_SMARTDMA_PIO0_PIO2_0 IOPCTL_MUX(64, 15) /* PIO2_0 */ +#define USDHC0_USDHC_DATA0_PIO2_0 IOPCTL_MUX(64, 1) /* PIO2_0 */ +#define GPIO_PIO21_PIO2_1 IOPCTL_MUX(65, 0) /* PIO2_1 */ +#define SCT0_IN0_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN1_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN2_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN3_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN4_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN5_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN6_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SMARTDMA_SMARTDMA_PIO1_PIO2_1 IOPCTL_MUX(65, 15) /* PIO2_1 */ +#define USDHC0_USDHC_DATA1_PIO2_1 IOPCTL_MUX(65, 1) /* PIO2_1 */ +#define GPIO_PIO22_PIO2_2 IOPCTL_MUX(66, 0) /* PIO2_2 */ +#define SCT0_OUT0_PIO2_2 IOPCTL_MUX(66, 2) /* PIO2_2 */ +#define SMARTDMA_SMARTDMA_PIO2_PIO2_2 IOPCTL_MUX(66, 15) /* PIO2_2 */ +#define USDHC0_USDHC_DATA2_PIO2_2 IOPCTL_MUX(66, 1) /* PIO2_2 */ +#define GPIO_PIO23_PIO2_3 IOPCTL_MUX(67, 0) /* PIO2_3 */ +#define SCT0_OUT1_PIO2_3 IOPCTL_MUX(67, 2) /* PIO2_3 */ +#define SMARTDMA_SMARTDMA_PIO3_PIO2_3 IOPCTL_MUX(67, 15) /* PIO2_3 */ +#define USDHC0_USDHC_DATA3_PIO2_3 IOPCTL_MUX(67, 1) /* PIO2_3 */ +#define GPIO_PIO24_PIO2_4 IOPCTL_MUX(68, 0) /* PIO2_4 */ +#define SCT0_OUT2_PIO2_4 IOPCTL_MUX(68, 2) /* PIO2_4 */ +#define SD0_DS_PIO2_4 IOPCTL_MUX(68, 5) /* PIO2_4 */ +#define SD0_WR_PRT_PIO2_4 IOPCTL_MUX(68, 1) /* PIO2_4 */ +#define SMARTDMA_SMARTDMA_PIO4_PIO2_4 IOPCTL_MUX(68, 15) /* PIO2_4 */ +#define FC8_SCK_PIO2_5 IOPCTL_MUX(69, 5) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOPCTL_MUX(69, 0) /* PIO2_5 */ +#define SCT0_OUT3_PIO2_5 IOPCTL_MUX(69, 2) /* PIO2_5 */ +#define SMARTDMA_SMARTDMA_PIO5_PIO2_5 IOPCTL_MUX(69, 15) /* PIO2_5 */ +#define USDHC0_USDHC_DATA4_PIO2_5 IOPCTL_MUX(69, 1) /* PIO2_5 */ +#define CTIMER1_MATCH0_PIO2_6 IOPCTL_MUX(70, 4) /* PIO2_6 */ +#define FC8_TXD_SCL_MISO_WS_PIO2_6 IOPCTL_MUX(70, 5) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOPCTL_MUX(70, 0) /* PIO2_6 */ +#define SCT0_IN0_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN1_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN2_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN3_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN4_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN5_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN6_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SMARTDMA_SMARTDMA_PIO6_PIO2_6 IOPCTL_MUX(70, 15) /* PIO2_6 */ +#define USDHC0_USDHC_DATA5_PIO2_6 IOPCTL_MUX(70, 1) /* PIO2_6 */ +#define CTIMER1_MATCH1_PIO2_7 IOPCTL_MUX(71, 4) /* PIO2_7 */ +#define FC8_RXD_SDA_MOSI_DATA_PIO2_7 IOPCTL_MUX(71, 5) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOPCTL_MUX(71, 0) /* PIO2_7 */ +#define SCT0_IN0_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN1_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN2_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN3_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN4_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN5_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN6_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SMARTDMA_SMARTDMA_PIO7_PIO2_7 IOPCTL_MUX(71, 15) /* PIO2_7 */ +#define USDHC0_USDHC_DATA6_PIO2_7 IOPCTL_MUX(71, 1) /* PIO2_7 */ +#define CTIMER1_MATCH2_PIO2_8 IOPCTL_MUX(72, 4) /* PIO2_8 */ +#define FC8_CTS_SDA_SSEL0_PIO2_8 IOPCTL_MUX(72, 5) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOPCTL_MUX(72, 0) /* PIO2_8 */ +#define SCT0_OUT4_PIO2_8 IOPCTL_MUX(72, 2) /* PIO2_8 */ +#define SMARTDMA_SMARTDMA_PIO8_PIO2_8 IOPCTL_MUX(72, 15) /* PIO2_8 */ +#define USDHC0_USDHC_DATA7_PIO2_8 IOPCTL_MUX(72, 1) /* PIO2_8 */ +#define CTIMER1_MATCH3_PIO2_9 IOPCTL_MUX(73, 4) /* PIO2_9 */ +#define FC8_CTS_SDA_SSEL1_PIO2_9 IOPCTL_MUX(73, 5) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOPCTL_MUX(73, 0) /* PIO2_9 */ +#define SCT0_OUT5_PIO2_9 IOPCTL_MUX(73, 2) /* PIO2_9 */ +#define SD0_CARD_DET_N_PIO2_9 IOPCTL_MUX(73, 1) /* PIO2_9 */ +#define SMARTDMA_SMARTDMA_PIO9_PIO2_9 IOPCTL_MUX(73, 15) /* PIO2_9 */ +#define CTIMER2_MATCH0_PIO2_10 IOPCTL_MUX(74, 4) /* PIO2_10 */ +#define FC8_SSEL2_PIO2_10 IOPCTL_MUX(74, 5) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOPCTL_MUX(74, 0) /* PIO2_10 */ +#define SCT0_IN0_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN1_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN2_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN3_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN4_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN5_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN6_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SD0_RESET_N_PIO2_10 IOPCTL_MUX(74, 1) /* PIO2_10 */ +#define SMARTDMA_SMARTDMA_PIO10_PIO2_10 IOPCTL_MUX(74, 15) /* PIO2_10 */ +#define CTIMER2_MATCH1_PIO2_11 IOPCTL_MUX(75, 4) /* PIO2_11 */ +#define FC8_SSEL3_PIO2_11 IOPCTL_MUX(75, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOPCTL_MUX(75, 0) /* PIO2_11 */ +#define SCT0_IN0_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN1_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN2_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN3_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN4_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN5_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN6_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SD0_VOLT_PIO2_11 IOPCTL_MUX(75, 1) /* PIO2_11 */ +#define SMARTDMA_SMARTDMA_PIO11_PIO2_11 IOPCTL_MUX(75, 15) /* PIO2_11 */ +#define ACMP0_ACMP_IN1_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define CTIMER0_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define FLEXIO0_TRIG1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define PIN_32KHZ_CLKOUT_PIO2_14 IOPCTL_MUX(78, 7) /* PIO2_14 */ +#define SCT0_OUT8_PIO2_14 IOPCTL_MUX(78, 2) /* PIO2_14 */ +#define SMARTDMA_SMARTDMA_PIO14_PIO2_14 IOPCTL_MUX(78, 15) /* PIO2_14 */ +#define ACMP0_ACMP_IN4_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define CLKIN_PIO2_15 IOPCTL_MUX(79, 7) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define SCT0_OUT9_PIO2_15 IOPCTL_MUX(79, 2) /* PIO2_15 */ +#define SMARTDMA_SMARTDMA_PIO15_PIO2_15 IOPCTL_MUX(79, 15) /* PIO2_15 */ +#define GPIO_INT_BMAT_PIO2_24 IOPCTL_MUX(88, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOPCTL_MUX(88, 0) /* PIO2_24 */ +#define SMARTDMA_SMARTDMA_PIO24_PIO2_24 IOPCTL_MUX(88, 15) /* PIO2_24 */ +#define SWO_PIO2_24 IOPCTL_MUX(88, 1) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOPCTL_MUX(89, 0) /* PIO2_25 */ +#define SMARTDMA_SMARTDMA_PIO25_PIO2_25 IOPCTL_MUX(89, 15) /* PIO2_25 */ +#define SWCLK_PIO2_25 IOPCTL_MUX(89, 1) /* PIO2_25 */ +#define GPIO_PIO226_PIO2_26 IOPCTL_MUX(90, 0) /* PIO2_26 */ +#define SMARTDMA_SMARTDMA_PIO26_PIO2_26 IOPCTL_MUX(90, 15) /* PIO2_26 */ +#define SWDIO_PIO2_26 IOPCTL_MUX(90, 1) /* PIO2_26 */ +#define GPIO_PIO227_PIO2_27 IOPCTL_MUX(91, 0) /* PIO2_27 */ +#define SMARTDMA_SMARTDMA_PIO27_PIO2_27 IOPCTL_MUX(91, 15) /* PIO2_27 */ +#define USB1_OVERCURRENTN_PIO2_27 IOPCTL_MUX(91, 1) /* PIO2_27 */ +#define GPIO_PIO228_PIO2_28 IOPCTL_MUX(92, 0) /* PIO2_28 */ +#define SMARTDMA_SMARTDMA_PIO28_PIO2_28 IOPCTL_MUX(92, 15) /* PIO2_28 */ +#define USB1_PORTPWRN_PIO2_28 IOPCTL_MUX(92, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOPCTL_MUX(93, 5) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOPCTL_MUX(93, 0) /* PIO2_29 */ +#define I3C0_SCL_PIO2_29 IOPCTL_MUX(93, 1) /* PIO2_29 */ +#define SCT0_OUT0_PIO2_29 IOPCTL_MUX(93, 2) /* PIO2_29 */ +#define SMARTDMA_SMARTDMA_PIO29_PIO2_29 IOPCTL_MUX(93, 15) /* PIO2_29 */ +#define CLKIN_PIO2_30 IOPCTL_MUX(94, 5) /* PIO2_30 */ +#define CMP0_OUT_PIO2_30 IOPCTL_MUX(94, 7) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOPCTL_MUX(94, 0) /* PIO2_30 */ +#define I3C0_SDA_PIO2_30 IOPCTL_MUX(94, 1) /* PIO2_30 */ +#define SCT0_OUT3_PIO2_30 IOPCTL_MUX(94, 2) /* PIO2_30 */ +#define SMARTDMA_SMARTDMA_PIO30_PIO2_30 IOPCTL_MUX(94, 15) /* PIO2_30 */ +#define ACMP0_ACMP_IN2_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define CTIMER0_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define GPIO_PIO231_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define I3C0_PUR_PIO2_31 IOPCTL_MUX(95, 1) /* PIO2_31 */ +#define SCT0_OUT7_PIO2_31 IOPCTL_MUX(95, 2) /* PIO2_31 */ +#define SMARTDMA_SMARTDMA_PIO31_PIO2_31 IOPCTL_MUX(95, 15) /* PIO2_31 */ +#define SWO_PIO2_31 IOPCTL_MUX(95, 5) /* PIO2_31 */ +#define UTICK0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 3) /* PIO2_31 */ +#define DMIC0_CLK23_PIO3_1 IOPCTL_MUX(97, 1) /* PIO3_1 */ +#define DMIC0_DATA23_PIO3_1 IOPCTL_MUX(97, 2) /* PIO3_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO3_1 IOPCTL_MUX(97, 5) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOPCTL_MUX(97, 0) /* PIO3_1 */ +#define I3C1_SCL_PIO3_1 IOPCTL_MUX(97, 6) /* PIO3_1 */ +#define DMIC0_CLK45_PIO3_2 IOPCTL_MUX(98, 1) /* PIO3_2 */ +#define DMIC0_DATA45_PIO3_2 IOPCTL_MUX(98, 2) /* PIO3_2 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO3_2 IOPCTL_MUX(98, 5) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOPCTL_MUX(98, 0) /* PIO3_2 */ +#define I3C1_SDA_PIO3_2 IOPCTL_MUX(98, 6) /* PIO3_2 */ +#define CMP0_OUT_PIO3_3 IOPCTL_MUX(99, 7) /* PIO3_3 */ +#define DMIC0_CLK67_PIO3_3 IOPCTL_MUX(99, 1) /* PIO3_3 */ +#define DMIC0_DATA67_PIO3_3 IOPCTL_MUX(99, 2) /* PIO3_3 */ +#define FC0_CTS_SDA_SSEL0_PIO3_3 IOPCTL_MUX(99, 5) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOPCTL_MUX(99, 0) /* PIO3_3 */ +#define I3C1_PUR_PIO3_3 IOPCTL_MUX(99, 6) /* PIO3_3 */ +#define CTIMER0_MATCH0_PIO3_8 IOPCTL_MUX(104, 4) /* PIO3_8 */ +#define FC10_SCK_PIO3_8 IOPCTL_MUX(104, 6) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOPCTL_MUX(104, 0) /* PIO3_8 */ +#define SD1_CLK_PIO3_8 IOPCTL_MUX(104, 1) /* PIO3_8 */ +#define CTIMER0_MATCH1_PIO3_9 IOPCTL_MUX(105, 4) /* PIO3_9 */ +#define FC10_TXD_SCL_MISO_PIO3_9 IOPCTL_MUX(105, 6) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOPCTL_MUX(105, 0) /* PIO3_9 */ +#define SD1_CMD_PIO3_9 IOPCTL_MUX(105, 1) /* PIO3_9 */ +#define CTIMER0_MATCH2_PIO3_10 IOPCTL_MUX(106, 4) /* PIO3_10 */ +#define FC10_RXD_SDA_MOSI_PIO3_10 IOPCTL_MUX(106, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOPCTL_MUX(106, 0) /* PIO3_10 */ +#define USDHC1_USDHC_DATA0_PIO3_10 IOPCTL_MUX(106, 1) /* PIO3_10 */ +#define CTIMER0_MATCH3_PIO3_11 IOPCTL_MUX(107, 4) /* PIO3_11 */ +#define FC10_CTS_SDA_SSELN0_PIO3_11 IOPCTL_MUX(107, 6) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOPCTL_MUX(107, 0) /* PIO3_11 */ +#define USDHC1_USDHC_DATA1_PIO3_11 IOPCTL_MUX(107, 1) /* PIO3_11 */ +#define CTIMER0_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER0_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER0_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER0_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define FC10_RTS_SCL_SSELN1_PIO3_12 IOPCTL_MUX(108, 6) /* PIO3_12 */ +#define FLEXIO0_TRIG0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOPCTL_MUX(108, 0) /* PIO3_12 */ +#define USDHC1_USDHC_DATA2_PIO3_12 IOPCTL_MUX(108, 1) /* PIO3_12 */ +#define CTIMER0_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER0_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER0_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER0_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define FC10_SSELN2_PIO3_13 IOPCTL_MUX(109, 6) /* PIO3_13 */ +#define FLEXIO0_TRIG1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOPCTL_MUX(109, 0) /* PIO3_13 */ +#define USDHC1_USDHC_DATA3_PIO3_13 IOPCTL_MUX(109, 1) /* PIO3_13 */ +#define ACMP0_ACMP_IN5_PIO3_14 IOPCTL_MUX(110, 0) /* PIO3_14 */ +#define CTIMER3_MATCH0_PIO3_14 IOPCTL_MUX(110, 4) /* PIO3_14 */ +#define FC10_SSELN3_PIO3_14 IOPCTL_MUX(110, 6) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOPCTL_MUX(110, 0) /* PIO3_14 */ +#define SD1_DS_PIO3_14 IOPCTL_MUX(110, 5) /* PIO3_14 */ +#define SD1_WR_PRT_PIO3_14 IOPCTL_MUX(110, 1) /* PIO3_14 */ +#define CTIMER3_MATCH1_PIO3_15 IOPCTL_MUX(111, 4) /* PIO3_15 */ +#define FC5_SCK_PIO3_15 IOPCTL_MUX(111, 5) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOPCTL_MUX(111, 0) /* PIO3_15 */ +#define USDHC1_USDHC_DATA4_PIO3_15 IOPCTL_MUX(111, 1) /* PIO3_15 */ +#define CTIMER3_MATCH2_PIO3_16 IOPCTL_MUX(112, 4) /* PIO3_16 */ +#define FC5_TXD_SCL_MISO_WS_PIO3_16 IOPCTL_MUX(112, 5) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOPCTL_MUX(112, 0) /* PIO3_16 */ +#define USDHC1_USDHC_DATA5_PIO3_16 IOPCTL_MUX(112, 1) /* PIO3_16 */ +#define CTIMER3_MATCH3_PIO3_17 IOPCTL_MUX(113, 4) /* PIO3_17 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO3_17 IOPCTL_MUX(113, 5) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOPCTL_MUX(113, 0) /* PIO3_17 */ +#define USDHC1_USDHC_DATA6_PIO3_17 IOPCTL_MUX(113, 1) /* PIO3_17 */ +#define CTIMER4_MATCH0_PIO3_18 IOPCTL_MUX(114, 4) /* PIO3_18 */ +#define FC5_CTS_SDA_SSEL0_PIO3_18 IOPCTL_MUX(114, 5) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOPCTL_MUX(114, 0) /* PIO3_18 */ +#define USDHC1_USDHC_DATA7_PIO3_18 IOPCTL_MUX(114, 1) /* PIO3_18 */ +#define CTIMER4_MATCH1_PIO3_19 IOPCTL_MUX(115, 4) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOPCTL_MUX(115, 0) /* PIO3_19 */ +#define MCLK_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN0_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN1_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN2_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN3_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN4_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN5_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN6_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SD1_CARD_DET_N_PIO3_19 IOPCTL_MUX(115, 1) /* PIO3_19 */ +#define CTIMER4_MATCH2_PIO3_20 IOPCTL_MUX(116, 4) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOPCTL_MUX(116, 0) /* PIO3_20 */ +#define SD1_RESET_N_PIO3_20 IOPCTL_MUX(116, 1) /* PIO3_20 */ +#define CTIMER4_MATCH3_PIO3_21 IOPCTL_MUX(117, 4) /* PIO3_21 */ +#define GPIO_INT_BMAT_PIO3_21 IOPCTL_MUX(117, 6) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOPCTL_MUX(117, 0) /* PIO3_21 */ +#define SD1_VOLT_PIO3_21 IOPCTL_MUX(117, 1) /* PIO3_21 */ +#define FC6_SCK_PIO3_25 IOPCTL_MUX(121, 1) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOPCTL_MUX(121, 0) /* PIO3_25 */ +#define FC6_TXD_SCL_MISO_WS_PIO3_26 IOPCTL_MUX(122, 1) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOPCTL_MUX(122, 0) /* PIO3_26 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO3_27 IOPCTL_MUX(123, 1) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOPCTL_MUX(123, 0) /* PIO3_27 */ +#define FC6_CTS_SDA_SSEL0_PIO3_28 IOPCTL_MUX(124, 1) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOPCTL_MUX(124, 0) /* PIO3_28 */ +#define FC6_RTS_SCL_SSEL1_PIO3_29 IOPCTL_MUX(125, 1) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOPCTL_MUX(125, 0) /* PIO3_29 */ +#define CLKOUT_PIO4_0 IOPCTL_MUX(128, 7) /* PIO4_0 */ +#define FC7_SCK_PIO4_0 IOPCTL_MUX(128, 1) /* PIO4_0 */ +#define FREQME_IN0_PIO4_0 IOPCTL_MUX(128, 4) /* PIO4_0 */ +#define FREQME_IN1_PIO4_0 IOPCTL_MUX(128, 4) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOPCTL_MUX(128, 0) /* PIO4_0 */ +#define CLKIN_PIO4_1 IOPCTL_MUX(129, 7) /* PIO4_1 */ +#define FC7_TXD_SCL_MISO_WS_PIO4_1 IOPCTL_MUX(129, 1) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOPCTL_MUX(129, 0) /* PIO4_1 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO4_2 IOPCTL_MUX(130, 1) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOPCTL_MUX(130, 0) /* PIO4_2 */ +#define FC7_CTS_SDA_SSEL0_PIO4_3 IOPCTL_MUX(131, 1) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOPCTL_MUX(131, 0) /* PIO4_3 */ +#define FC1_SCK_PIO4_4 IOPCTL_MUX(132, 5) /* PIO4_4 */ +#define FC7_RTS_SCL_SSEL1_PIO4_4 IOPCTL_MUX(132, 1) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOPCTL_MUX(132, 0) /* PIO4_4 */ +#define FC1_TXD_SCL_MISO_WS_PIO4_5 IOPCTL_MUX(133, 5) /* PIO4_5 */ +#define FC7_SSEL2_PIO4_5 IOPCTL_MUX(133, 1) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOPCTL_MUX(133, 0) /* PIO4_5 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO4_6 IOPCTL_MUX(134, 5) /* PIO4_6 */ +#define FC7_SSEL3_PIO4_6 IOPCTL_MUX(134, 1) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOPCTL_MUX(134, 0) /* PIO4_6 */ +#define FC2_SCK_PIO4_11 IOPCTL_MUX(139, 1) /* PIO4_11 */ +#define FLEXSPI1_SCLK_PIO4_11 IOPCTL_MUX(139, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOPCTL_MUX(139, 0) /* PIO4_11 */ +#define SD1_CLK_PIO4_11 IOPCTL_MUX(139, 4) /* PIO4_11 */ +#define FC2_TXD_SCL_MISO_WS_PIO4_12 IOPCTL_MUX(140, 1) /* PIO4_12 */ +#define FLEXSPI1_DATA0_PIO4_12 IOPCTL_MUX(140, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOPCTL_MUX(140, 0) /* PIO4_12 */ +#define SD1_CMD_PIO4_12 IOPCTL_MUX(140, 4) /* PIO4_12 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO4_13 IOPCTL_MUX(141, 1) /* PIO4_13 */ +#define FLEXSPI1_DATA1_PIO4_13 IOPCTL_MUX(141, 2) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOPCTL_MUX(141, 0) /* PIO4_13 */ +#define USDHC1_USDHC_DATA0_PIO4_13 IOPCTL_MUX(141, 4) /* PIO4_13 */ +#define FC2_CTS_SDA_SSEL0_PIO4_14 IOPCTL_MUX(142, 1) /* PIO4_14 */ +#define FLEXSPI1_DATA2_PIO4_14 IOPCTL_MUX(142, 2) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOPCTL_MUX(142, 0) /* PIO4_14 */ +#define USDHC1_USDHC_DATA1_PIO4_14 IOPCTL_MUX(142, 4) /* PIO4_14 */ +#define FC2_RTS_SCL_SSEL1_PIO4_15 IOPCTL_MUX(143, 1) /* PIO4_15 */ +#define FLEXSPI1_DATA3_PIO4_15 IOPCTL_MUX(143, 2) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOPCTL_MUX(143, 0) /* PIO4_15 */ +#define USDHC1_USDHC_DATA2_PIO4_15 IOPCTL_MUX(143, 4) /* PIO4_15 */ +#define FC2_SSEL2_PIO4_16 IOPCTL_MUX(144, 1) /* PIO4_16 */ +#define FLEXSPI1_DQS_PIO4_16 IOPCTL_MUX(144, 2) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOPCTL_MUX(144, 0) /* PIO4_16 */ +#define USDHC1_USDHC_DATA3_PIO4_16 IOPCTL_MUX(144, 4) /* PIO4_16 */ +#define FC2_SSEL3_PIO4_17 IOPCTL_MUX(145, 1) /* PIO4_17 */ +#define FLEXSPI1_SCLK_N_PIO4_17 IOPCTL_MUX(145, 3) /* PIO4_17 */ +#define FLEXSPI1_SS1_N_PIO4_17 IOPCTL_MUX(145, 2) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOPCTL_MUX(145, 0) /* PIO4_17 */ +#define SD1_WR_PRT_PIO4_17 IOPCTL_MUX(145, 4) /* PIO4_17 */ +#define ADC0_CH6_PIO4_18 IOPCTL_MUX(146, 0) /* PIO4_18 */ +#define FLEXSPI1_SS0_N_PIO4_18 IOPCTL_MUX(146, 2) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOPCTL_MUX(146, 0) /* PIO4_18 */ +#define USDHC1_USDHC_DATA4_PIO4_18 IOPCTL_MUX(146, 4) /* PIO4_18 */ +#define FC11_SCK_PIO4_20 IOPCTL_MUX(148, 6) /* PIO4_20 */ +#define FLEXIO0_IO0_PIO4_20 IOPCTL_MUX(148, 8) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOPCTL_MUX(148, 0) /* PIO4_20 */ +#define USDHC1_USDHC_DATA6_PIO4_20 IOPCTL_MUX(148, 4) /* PIO4_20 */ +#define FC11_TXD_SCL_MISO_PIO4_21 IOPCTL_MUX(149, 6) /* PIO4_21 */ +#define FLEXIO0_IO1_PIO4_21 IOPCTL_MUX(149, 8) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOPCTL_MUX(149, 0) /* PIO4_21 */ +#define USDHC1_USDHC_DATA7_PIO4_21 IOPCTL_MUX(149, 4) /* PIO4_21 */ +#define FC11_RXD_SDA_MOSI_PIO4_22 IOPCTL_MUX(150, 6) /* PIO4_22 */ +#define FLEXIO0_IO2_PIO4_22 IOPCTL_MUX(150, 8) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOPCTL_MUX(150, 0) /* PIO4_22 */ +#define SD1_CARD_DET_N_PIO4_22 IOPCTL_MUX(150, 4) /* PIO4_22 */ +#define FC11_CTS_SDA_SSELN0_PIO4_23 IOPCTL_MUX(151, 6) /* PIO4_23 */ +#define FLEXIO0_IO3_PIO4_23 IOPCTL_MUX(151, 8) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOPCTL_MUX(151, 0) /* PIO4_23 */ +#define SD1_RESET_N_PIO4_23 IOPCTL_MUX(151, 4) /* PIO4_23 */ +#define TRACECLK_PIO4_23 IOPCTL_MUX(151, 7) /* PIO4_23 */ +#define FC11_RTS_SCL_SSELN1_PIO4_24 IOPCTL_MUX(152, 6) /* PIO4_24 */ +#define FLEXIO0_IO4_PIO4_24 IOPCTL_MUX(152, 8) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOPCTL_MUX(152, 0) /* PIO4_24 */ +#define SD1_VOLT_PIO4_24 IOPCTL_MUX(152, 4) /* PIO4_24 */ +#define SWD_TRACEDATA0_PIO4_24 IOPCTL_MUX(152, 7) /* PIO4_24 */ +#define FC11_SSELN2_PIO4_25 IOPCTL_MUX(153, 6) /* PIO4_25 */ +#define FLEXIO0_IO5_PIO4_25 IOPCTL_MUX(153, 8) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOPCTL_MUX(153, 0) /* PIO4_25 */ +#define SWD_TRACEDATA1_PIO4_25 IOPCTL_MUX(153, 7) /* PIO4_25 */ +#define FC11_SSELN3_PIO4_26 IOPCTL_MUX(154, 6) /* PIO4_26 */ +#define FLEXIO0_IO6_PIO4_26 IOPCTL_MUX(154, 8) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOPCTL_MUX(154, 0) /* PIO4_26 */ +#define SWD_TRACEDATA2_PIO4_26 IOPCTL_MUX(154, 7) /* PIO4_26 */ +#define FLEXIO0_IO7_PIO4_27 IOPCTL_MUX(155, 8) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOPCTL_MUX(155, 0) /* PIO4_27 */ +#define SWD_TRACEDATA3_PIO4_27 IOPCTL_MUX(155, 7) /* PIO4_27 */ +#define FLEXIO0_IO8_PIO4_28 IOPCTL_MUX(156, 8) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOPCTL_MUX(156, 0) /* PIO4_28 */ +#define FC12_SCK_PIO4_29 IOPCTL_MUX(157, 6) /* PIO4_29 */ +#define FLEXIO0_IO9_PIO4_29 IOPCTL_MUX(157, 8) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOPCTL_MUX(157, 0) /* PIO4_29 */ +#define FC12_TXD_SCL_MISO_PIO4_30 IOPCTL_MUX(158, 6) /* PIO4_30 */ +#define FLEXIO0_IO10_PIO4_30 IOPCTL_MUX(158, 8) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOPCTL_MUX(158, 0) /* PIO4_30 */ +#define FC12_RXD_SDA_MOSI_PIO4_31 IOPCTL_MUX(159, 6) /* PIO4_31 */ +#define FLEXIO0_IO11_PIO4_31 IOPCTL_MUX(159, 8) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOPCTL_MUX(159, 0) /* PIO4_31 */ +#define FC12_CTS_SDA_SSELN0_PIO5_0 IOPCTL_MUX(160, 6) /* PIO5_0 */ +#define FLEXIO0_IO12_PIO5_0 IOPCTL_MUX(160, 8) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOPCTL_MUX(160, 0) /* PIO5_0 */ +#define FC12_RTS_SCL_SSELN1_PIO5_1 IOPCTL_MUX(161, 6) /* PIO5_1 */ +#define FLEXIO0_IO13_PIO5_1 IOPCTL_MUX(161, 8) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOPCTL_MUX(161, 0) /* PIO5_1 */ +#define FC12_SSELN2_PIO5_2 IOPCTL_MUX(162, 6) /* PIO5_2 */ +#define FLEXIO0_IO14_PIO5_2 IOPCTL_MUX(162, 8) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOPCTL_MUX(162, 0) /* PIO5_2 */ +#define LOW_FREQ_CLKOUT_PIO5_2 IOPCTL_MUX(162, 7) /* PIO5_2 */ +#define FC12_SSELN3_PIO5_3 IOPCTL_MUX(163, 6) /* PIO5_3 */ +#define FLEXIO0_IO15_PIO5_3 IOPCTL_MUX(163, 8) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOPCTL_MUX(163, 0) /* PIO5_3 */ +#define LOW_FREQ_CLKOUT_N_PIO5_3 IOPCTL_MUX(163, 7) /* PIO5_3 */ +#define DMIC0_CLK01_PIO5_4 IOPCTL_MUX(164, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOPCTL_MUX(164, 0) /* PIO5_4 */ +#define DMIC0_DATA01_PIO5_8 IOPCTL_MUX(168, 4) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOPCTL_MUX(168, 0) /* PIO5_8 */ +#define FC4_CTS_SDA_SSEL0_PIO5_15 IOPCTL_MUX(175, 4) /* PIO5_15 */ +#define FLEXSPI1_DATA4_PIO5_15 IOPCTL_MUX(175, 2) /* PIO5_15 */ +#define GPIO_PIO515_PIO5_15 IOPCTL_MUX(175, 0) /* PIO5_15 */ +#define FC4_RTS_SCL_SSEL1_PIO5_16 IOPCTL_MUX(176, 4) /* PIO5_16 */ +#define FLEXSPI1_DATA5_PIO5_16 IOPCTL_MUX(176, 2) /* PIO5_16 */ +#define GPIO_PIO516_PIO5_16 IOPCTL_MUX(176, 0) /* PIO5_16 */ +#define FC4_SSEL2_PIO5_17 IOPCTL_MUX(177, 4) /* PIO5_17 */ +#define FLEXSPI1_DATA6_PIO5_17 IOPCTL_MUX(177, 2) /* PIO5_17 */ +#define GPIO_PIO517_PIO5_17 IOPCTL_MUX(177, 0) /* PIO5_17 */ +#define FC4_SSEL3_PIO5_18 IOPCTL_MUX(178, 4) /* PIO5_18 */ +#define FLEXSPI1_DATA7_PIO5_18 IOPCTL_MUX(178, 2) /* PIO5_18 */ +#define GPIO_PIO518_PIO5_18 IOPCTL_MUX(178, 0) /* PIO5_18 */ + +#endif diff --git a/dts/nxp/nxp_imx/rt/MIMXRT555SFAWC-pinctrl.h b/dts/nxp/nxp_imx/rt/MIMXRT555SFAWC-pinctrl.h new file mode 100644 index 000000000..19343bdec --- /dev/null +++ b/dts/nxp/nxp_imx/rt/MIMXRT555SFAWC-pinctrl.h @@ -0,0 +1,4905 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from MIMXRT555SFAWC/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MIMXRT555SFAWC_ +#define _ZEPHYR_DTS_BINDING_MIMXRT555SFAWC_ + +#define IOPCTL_MUX(offset, mux) \ + ((((offset) & 0xFFF) << 20) | \ + (((mux) & 0xF) << 0)) + +#define CTIMER0_MATCH0_PIO0_0 IOPCTL_MUX(0, 4) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG33_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG34_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG35_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG36_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG33_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG34_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG35_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG36_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define FC0_SCK_PIO0_0 IOPCTL_MUX(0, 1) /* PIO0_0 */ +#define GPIO_INT_BMAT_PIO0_0 IOPCTL_MUX(0, 6) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define I2S_BRIDGE_CLK_IN_PIO0_0 IOPCTL_MUX(0, 5) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOPCTL_MUX(0, 8) /* PIO0_0 */ +#define SMARTDMA_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define CTIMER0_MATCH1_PIO0_1 IOPCTL_MUX(1, 4) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG33_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG34_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG35_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG36_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG33_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG34_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG35_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG36_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_1 IOPCTL_MUX(1, 1) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define I2S_BRIDGE_WS_IN_PIO0_1 IOPCTL_MUX(1, 5) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOPCTL_MUX(1, 8) /* PIO0_1 */ +#define SMARTDMA_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define CTIMER0_MATCH2_PIO0_2 IOPCTL_MUX(2, 4) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG33_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG34_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG35_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG36_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG33_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG34_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG35_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG36_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_2 IOPCTL_MUX(2, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define I2S_BRIDGE_DATA_IN_PIO0_2 IOPCTL_MUX(2, 5) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOPCTL_MUX(2, 8) /* PIO0_2 */ +#define SMARTDMA_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define CTIMER0_MATCH3_PIO0_3 IOPCTL_MUX(3, 4) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG33_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG34_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG35_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG36_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG33_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG34_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG35_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG36_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define FC0_CTS_SDA_SSEL0_PIO0_3 IOPCTL_MUX(3, 1) /* PIO0_3 */ +#define FC1_SSEL2_PIO0_3 IOPCTL_MUX(3, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOPCTL_MUX(3, 8) /* PIO0_3 */ +#define SMARTDMA_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define CMP0_OUT_PIO0_4 IOPCTL_MUX(4, 7) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG33_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG34_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG35_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG36_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG33_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG34_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG35_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG36_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define FC0_RTS_SCL_SSEL1_PIO0_4 IOPCTL_MUX(4, 1) /* PIO0_4 */ +#define FC1_SSEL3_PIO0_4 IOPCTL_MUX(4, 5) /* PIO0_4 */ +#define FLEXIO0_TRIG0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOPCTL_MUX(4, 8) /* PIO0_4 */ +#define SMARTDMA_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define ADC0_CH0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG33_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG34_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG35_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG36_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG33_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG34_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG35_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG36_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define FC0_SSEL2_PIO0_5 IOPCTL_MUX(5, 1) /* PIO0_5 */ +#define FLEXIO0_TRIG1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_OUT0_PIO0_5 IOPCTL_MUX(5, 3) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOPCTL_MUX(5, 8) /* PIO0_5 */ +#define SMARTDMA_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define ADC0_CH8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER0_MATCH0_PIO0_6 IOPCTL_MUX(6, 4) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG33_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG34_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG35_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG36_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG33_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG34_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG35_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG36_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define FC0_SSEL3_PIO0_6 IOPCTL_MUX(6, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_OUT1_PIO0_6 IOPCTL_MUX(6, 3) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOPCTL_MUX(6, 8) /* PIO0_6 */ +#define SMARTDMA_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER1_MATCH0_PIO0_7 IOPCTL_MUX(7, 4) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG33_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG34_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG35_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG36_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG33_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG34_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG35_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG36_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOPCTL_MUX(7, 1) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_7 IOPCTL_MUX(7, 5) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SCT0_IN0_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN1_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN2_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN3_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN4_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN5_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN6_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_OUT4_PIO0_7 IOPCTL_MUX(7, 3) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOPCTL_MUX(7, 8) /* PIO0_7 */ +#define SMARTDMA_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define CTIMER1_MATCH1_PIO0_8 IOPCTL_MUX(8, 4) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG33_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG34_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG35_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG36_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG33_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG34_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG35_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG36_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_8 IOPCTL_MUX(8, 1) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define I2S_BRIDGE_WS_OUT_PIO0_8 IOPCTL_MUX(8, 5) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define SCT0_IN0_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN1_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN2_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN3_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN4_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN5_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN6_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_OUT5_PIO0_8 IOPCTL_MUX(8, 3) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOPCTL_MUX(8, 8) /* PIO0_8 */ +#define CTIMER1_MATCH2_PIO0_9 IOPCTL_MUX(9, 4) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG33_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG34_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG35_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG36_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG33_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG34_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG35_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG36_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_9 IOPCTL_MUX(9, 1) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_9 IOPCTL_MUX(9, 5) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define SCT0_IN0_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN1_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN2_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN3_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN4_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN5_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN6_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_OUT6_PIO0_9 IOPCTL_MUX(9, 3) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOPCTL_MUX(9, 8) /* PIO0_9 */ +#define CTIMER1_MATCH3_PIO0_10 IOPCTL_MUX(10, 4) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG33_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG34_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG35_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG36_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG33_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG34_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG35_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG36_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define FC0_SSEL2_PIO0_10 IOPCTL_MUX(10, 5) /* PIO0_10 */ +#define FC1_CTS_SDA_SSEL0_PIO0_10 IOPCTL_MUX(10, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define SCT0_IN0_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN1_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN2_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN3_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN4_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN5_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN6_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_OUT7_PIO0_10 IOPCTL_MUX(10, 3) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOPCTL_MUX(10, 8) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG33_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG34_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG35_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG36_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG33_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG34_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG35_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG36_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define FC0_SSEL3_PIO0_11 IOPCTL_MUX(11, 5) /* PIO0_11 */ +#define FC1_RTS_SCL_SSEL1_PIO0_11 IOPCTL_MUX(11, 1) /* PIO0_11 */ +#define FLEXIO0_TRIG2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define SCT0_IN0_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN1_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN2_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN3_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN4_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN5_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN6_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_OUT8_PIO0_11 IOPCTL_MUX(11, 3) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOPCTL_MUX(11, 8) /* PIO0_11 */ +#define ADC0_CH1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG33_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG34_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG35_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG36_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG33_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG34_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG35_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG36_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define FC1_SSEL2_PIO0_12 IOPCTL_MUX(12, 1) /* PIO0_12 */ +#define FLEXIO0_TRIG3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_OUT2_PIO0_12 IOPCTL_MUX(12, 3) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOPCTL_MUX(12, 8) /* PIO0_12 */ +#define ADC0_CH9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define CTIMER0_MATCH1_PIO0_13 IOPCTL_MUX(13, 4) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG33_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG34_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG35_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG36_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG33_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG34_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG35_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG36_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define FC1_SSEL3_PIO0_13 IOPCTL_MUX(13, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_OUT3_PIO0_13 IOPCTL_MUX(13, 3) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOPCTL_MUX(13, 8) /* PIO0_13 */ +#define CTIMER2_MATCH0_PIO0_14 IOPCTL_MUX(14, 4) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG33_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG34_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG35_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG36_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG33_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG34_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG35_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG36_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define FC2_SCK_PIO0_14 IOPCTL_MUX(14, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define I2S_BRIDGE_CLK_IN_PIO0_14 IOPCTL_MUX(14, 5) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_OUT0_PIO0_14 IOPCTL_MUX(14, 3) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOPCTL_MUX(14, 8) /* PIO0_14 */ +#define CTIMER2_MATCH1_PIO0_15 IOPCTL_MUX(15, 4) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG33_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG34_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG35_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG36_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG33_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG34_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG35_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG36_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_15 IOPCTL_MUX(15, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define I2S_BRIDGE_WS_IN_PIO0_15 IOPCTL_MUX(15, 5) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define SCT0_IN0_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN1_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN2_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN3_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN4_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN5_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN6_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_OUT1_PIO0_15 IOPCTL_MUX(15, 3) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOPCTL_MUX(15, 8) /* PIO0_15 */ +#define CTIMER2_MATCH2_PIO0_16 IOPCTL_MUX(16, 4) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG33_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG34_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG35_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG36_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG33_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG34_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG35_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG36_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_16 IOPCTL_MUX(16, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define I2S_BRIDGE_DATA_IN_PIO0_16 IOPCTL_MUX(16, 5) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define SCT0_IN0_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN1_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN2_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN3_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN4_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN5_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN6_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_OUT2_PIO0_16 IOPCTL_MUX(16, 3) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOPCTL_MUX(16, 8) /* PIO0_16 */ +#define CTIMER2_MATCH3_PIO0_17 IOPCTL_MUX(17, 4) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG33_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG34_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG35_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG36_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG33_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG34_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG35_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG36_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define FC2_CTS_SDA_SSEL0_PIO0_17 IOPCTL_MUX(17, 1) /* PIO0_17 */ +#define FC5_SSEL2_PIO0_17 IOPCTL_MUX(17, 5) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_OUT3_PIO0_17 IOPCTL_MUX(17, 3) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOPCTL_MUX(17, 8) /* PIO0_17 */ +#define CTIMER0_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG33_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG34_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG35_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG36_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG33_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG34_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG35_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG36_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define FC2_RTS_SCL_SSEL1_PIO0_18 IOPCTL_MUX(18, 1) /* PIO0_18 */ +#define FC5_SSEL3_PIO0_18 IOPCTL_MUX(18, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define SCT0_IN0_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN1_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN2_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN3_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN4_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN5_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN6_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_OUT6_PIO0_18 IOPCTL_MUX(18, 3) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOPCTL_MUX(18, 8) /* PIO0_18 */ +#define ADC0_CH2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG33_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG34_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG35_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG36_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG33_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG34_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG35_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG36_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define FC2_SSEL2_PIO0_19 IOPCTL_MUX(19, 1) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define SCT0_IN0_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN1_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN2_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN3_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN4_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN5_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN6_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_OUT4_PIO0_19 IOPCTL_MUX(19, 3) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOPCTL_MUX(19, 8) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 5) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_MATCH0_PIO0_21 IOPCTL_MUX(21, 4) /* PIO0_21 */ +#define CTIMER4_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG33_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG34_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG35_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG36_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG33_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG34_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG35_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG36_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define FC3_SCK_PIO0_21 IOPCTL_MUX(21, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_OUT5_PIO0_21 IOPCTL_MUX(21, 3) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOPCTL_MUX(21, 8) /* PIO0_21 */ +#define TRACECLK_PIO0_21 IOPCTL_MUX(21, 6) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_MATCH1_PIO0_22 IOPCTL_MUX(22, 4) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG33_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG34_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG35_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG36_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG33_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG34_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG35_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG36_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_22 IOPCTL_MUX(22, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define SCT0_IN0_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN1_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN2_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN3_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN4_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN5_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN6_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_OUT6_PIO0_22 IOPCTL_MUX(22, 3) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOPCTL_MUX(22, 8) /* PIO0_22 */ +#define SWD_TRACEDATA0_PIO0_22 IOPCTL_MUX(22, 6) /* PIO0_22 */ +#define CTIMER0_MATCH3_PIO0_23 IOPCTL_MUX(23, 5) /* PIO0_23 */ +#define CTIMER3_MATCH2_PIO0_23 IOPCTL_MUX(23, 4) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG33_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG34_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG35_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG36_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG33_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG34_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG35_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG36_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_23 IOPCTL_MUX(23, 1) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define SCT0_IN0_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN1_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN2_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN3_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN4_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN5_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN6_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_OUT8_PIO0_23 IOPCTL_MUX(23, 3) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOPCTL_MUX(23, 8) /* PIO0_23 */ +#define SWD_TRACEDATA1_PIO0_23 IOPCTL_MUX(23, 6) /* PIO0_23 */ +#define CLKOUT_PIO0_24 IOPCTL_MUX(24, 7) /* PIO0_24 */ +#define CTIMER3_MATCH3_PIO0_24 IOPCTL_MUX(24, 4) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG33_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG34_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG35_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG36_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG33_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG34_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG35_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG36_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define FC2_SSEL2_PIO0_24 IOPCTL_MUX(24, 5) /* PIO0_24 */ +#define FC3_CTS_SDA_SSEL0_PIO0_24 IOPCTL_MUX(24, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_OUT9_PIO0_24 IOPCTL_MUX(24, 3) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOPCTL_MUX(24, 8) /* PIO0_24 */ +#define SWD_TRACEDATA2_PIO0_24 IOPCTL_MUX(24, 6) /* PIO0_24 */ +#define CLKIN_PIO0_25 IOPCTL_MUX(25, 7) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG33_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG34_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG35_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG36_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG33_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG34_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG35_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG36_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define FC2_SSEL3_PIO0_25 IOPCTL_MUX(25, 5) /* PIO0_25 */ +#define FC3_RTS_SCL_SSEL1_PIO0_25 IOPCTL_MUX(25, 1) /* PIO0_25 */ +#define FREQME_IN0_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define FREQME_IN1_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOPCTL_MUX(25, 8) /* PIO0_25 */ +#define SWD_TRACEDATA3_PIO0_25 IOPCTL_MUX(25, 6) /* PIO0_25 */ +#define CTIMER4_MATCH0_PIO0_28 IOPCTL_MUX(28, 4) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG33_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG34_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG35_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG36_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG33_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG34_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG35_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG36_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define FC4_SCK_PIO0_28 IOPCTL_MUX(28, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_28 IOPCTL_MUX(28, 5) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOPCTL_MUX(28, 8) /* PIO0_28 */ +#define CTIMER4_MATCH1_PIO0_29 IOPCTL_MUX(29, 4) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG33_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG34_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG35_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG36_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG33_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG34_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG35_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG36_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_29 IOPCTL_MUX(29, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define I2S_BRIDGE_WS_OUT_PIO0_29 IOPCTL_MUX(29, 5) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOPCTL_MUX(29, 8) /* PIO0_29 */ +#define CTIMER4_MATCH2_PIO0_30 IOPCTL_MUX(30, 4) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG33_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG34_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG35_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG36_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG33_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG34_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG35_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG36_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_30 IOPCTL_MUX(30, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_30 IOPCTL_MUX(30, 5) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOPCTL_MUX(30, 8) /* PIO0_30 */ +#define CTIMER4_MATCH3_PIO0_31 IOPCTL_MUX(31, 4) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG33_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG34_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG35_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG36_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG33_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG34_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG35_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG36_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define FC3_SSEL2_PIO0_31 IOPCTL_MUX(31, 5) /* PIO0_31 */ +#define FC4_CTS_SDA_SSEL0_PIO0_31 IOPCTL_MUX(31, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define SCT0_IN0_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN1_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN2_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN3_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN4_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN5_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN6_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_OUT6_PIO0_31 IOPCTL_MUX(31, 3) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOPCTL_MUX(31, 8) /* PIO0_31 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG33_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG34_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG35_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG36_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG33_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG34_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG35_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG36_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define FC3_SSEL3_PIO1_0 IOPCTL_MUX(32, 5) /* PIO1_0 */ +#define FC4_RTS_SCL_SSEL1_PIO1_0 IOPCTL_MUX(32, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_OUT7_PIO1_0 IOPCTL_MUX(32, 3) /* PIO1_0 */ +#define SMARTDMA_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG33_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG34_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG35_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG36_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG33_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG34_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG35_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG36_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define FC5_SCK_PIO1_3 IOPCTL_MUX(35, 1) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define HS_SPI1_SCK_PIO1_3 IOPCTL_MUX(35, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG33_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG34_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG35_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG36_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG33_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG34_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG35_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG36_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define FC5_TXD_SCL_MISO_WS_PIO1_4 IOPCTL_MUX(36, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define HS_SPI1_MISO_PIO1_4 IOPCTL_MUX(36, 6) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG33_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG34_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG35_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG36_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG33_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG34_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG35_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG36_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO1_5 IOPCTL_MUX(37, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define HS_SPI1_MOSI_PIO1_5 IOPCTL_MUX(37, 6) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG33_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG34_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG35_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG36_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG33_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG34_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG35_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG36_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define FC4_SSEL2_PIO1_6 IOPCTL_MUX(38, 5) /* PIO1_6 */ +#define FC5_CTS_SDA_SSEL0_PIO1_6 IOPCTL_MUX(38, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define HS_SPI1_SSELN0_PIO1_6 IOPCTL_MUX(38, 6) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_OUT4_PIO1_6 IOPCTL_MUX(38, 3) /* PIO1_6 */ +#define SMARTDMA_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define CTIMER0_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG33_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG34_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG35_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG36_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG33_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG34_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG35_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG36_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define FC4_SSEL3_PIO1_7 IOPCTL_MUX(39, 5) /* PIO1_7 */ +#define FC5_RTS_SCL_SSEL1_PIO1_7 IOPCTL_MUX(39, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define HS_SPI1_SSELN1_PIO1_7 IOPCTL_MUX(39, 6) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_OUT5_PIO1_7 IOPCTL_MUX(39, 3) /* PIO1_7 */ +#define SMARTDMA_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define CTIMER1_MATCH3_PIO1_9 IOPCTL_MUX(41, 4) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG30_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG31_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG32_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG33_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG34_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG35_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG36_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG20_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG21_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG22_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG23_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG24_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG25_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG26_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG27_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG28_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG29_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG30_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG31_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG32_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG33_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG34_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG35_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG36_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG8_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG9_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define FC5_SSEL3_PIO1_9 IOPCTL_MUX(41, 1) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define HS_SPI1_SSELN3_PIO1_9 IOPCTL_MUX(41, 6) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define SCT0_IN0_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN1_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN2_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN3_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN4_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN5_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN6_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define UTICK0_CAPTURE1_PIO1_9 IOPCTL_MUX(41, 3) /* PIO1_9 */ +#define CTIMER2_MATCH0_PIO1_11 IOPCTL_MUX(43, 4) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG33_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG34_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG35_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG36_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG33_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG34_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG35_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG36_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define HS_SPI0_SCK_PIO1_11 IOPCTL_MUX(43, 1) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define CTIMER2_MATCH1_PIO1_12 IOPCTL_MUX(44, 4) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG33_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG34_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG35_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG36_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG33_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG34_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG35_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG36_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define HS_SPI0_MISO_PIO1_12 IOPCTL_MUX(44, 1) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define CTIMER2_MATCH2_PIO1_13 IOPCTL_MUX(45, 4) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG33_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG34_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG35_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG36_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG33_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG34_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG35_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG36_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define HS_SPI0_MOSI_PIO1_13 IOPCTL_MUX(45, 1) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define CTIMER2_MATCH3_PIO1_14 IOPCTL_MUX(46, 4) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG33_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG34_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG35_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG36_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG33_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG34_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG35_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG36_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define HS_SPI0_SSELN0_PIO1_14 IOPCTL_MUX(46, 1) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define CTIMER3_MATCH0_PIO1_15 IOPCTL_MUX(47, 4) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG33_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG34_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG35_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG36_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG33_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG34_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG35_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG36_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define HS_SPI0_SSELN1_PIO1_15 IOPCTL_MUX(47, 1) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define CTIMER3_MATCH3_PIO1_18 IOPCTL_MUX(50, 4) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG33_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG34_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG35_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG36_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG33_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG34_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG35_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG36_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define FLEXSPI0_SCLK_PIO1_18 IOPCTL_MUX(50, 1) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define SCT0_IN0_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN1_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN2_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN3_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN4_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN5_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN6_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define CLKOUT_PIO1_19 IOPCTL_MUX(51, 7) /* PIO1_19 */ +#define CTIMER4_MATCH0_PIO1_19 IOPCTL_MUX(51, 4) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG33_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG34_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG35_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG36_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG33_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG34_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG35_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG36_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define FLEXSPI0_SS0_N_PIO1_19 IOPCTL_MUX(51, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define SCT0_OUT0_PIO1_19 IOPCTL_MUX(51, 2) /* PIO1_19 */ +#define CTIMER4_MATCH1_PIO1_20 IOPCTL_MUX(52, 4) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG33_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG34_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG35_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG36_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG33_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG34_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG35_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG36_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define FLEXSPI0_DATA0_PIO1_20 IOPCTL_MUX(52, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define SCT0_IN0_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN1_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN2_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN3_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN4_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN5_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN6_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define CTIMER4_MATCH2_PIO1_21 IOPCTL_MUX(53, 4) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG33_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG34_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG35_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG36_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG33_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG34_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG35_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG36_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define FLEXSPI0_DATA1_PIO1_21 IOPCTL_MUX(53, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define SCT0_OUT1_PIO1_21 IOPCTL_MUX(53, 2) /* PIO1_21 */ +#define CTIMER4_MATCH3_PIO1_22 IOPCTL_MUX(54, 4) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG33_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG34_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG35_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG36_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG33_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG34_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG35_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG36_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define FLEXSPI0_DATA2_PIO1_22 IOPCTL_MUX(54, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define CTIMER0_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG33_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG34_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG35_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG36_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG33_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG34_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG35_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG36_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define FLEXSPI0_DATA3_PIO1_23 IOPCTL_MUX(55, 1) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define SCT0_OUT2_PIO1_23 IOPCTL_MUX(55, 2) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG33_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG34_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG35_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG36_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG33_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG34_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG35_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG36_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define FLEXSPI0_DQS_PIO1_28 IOPCTL_MUX(60, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define SCT0_IN0_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN1_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN2_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN3_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN4_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN5_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN6_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define ACMP0_ACMP_IN1_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define CTIMER0_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define FLEXIO0_TRIG1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define PIN_32KHZ_CLKOUT_PIO2_14 IOPCTL_MUX(78, 7) /* PIO2_14 */ +#define SCT0_OUT8_PIO2_14 IOPCTL_MUX(78, 2) /* PIO2_14 */ +#define SMARTDMA_SMARTDMA_PIO14_PIO2_14 IOPCTL_MUX(78, 15) /* PIO2_14 */ +#define ACMP0_ACMP_IN4_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define CLKIN_PIO2_15 IOPCTL_MUX(79, 7) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define SCT0_OUT9_PIO2_15 IOPCTL_MUX(79, 2) /* PIO2_15 */ +#define SMARTDMA_SMARTDMA_PIO15_PIO2_15 IOPCTL_MUX(79, 15) /* PIO2_15 */ +#define GPIO_INT_BMAT_PIO2_24 IOPCTL_MUX(88, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOPCTL_MUX(88, 0) /* PIO2_24 */ +#define SMARTDMA_SMARTDMA_PIO24_PIO2_24 IOPCTL_MUX(88, 15) /* PIO2_24 */ +#define SWO_PIO2_24 IOPCTL_MUX(88, 1) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOPCTL_MUX(89, 0) /* PIO2_25 */ +#define SMARTDMA_SMARTDMA_PIO25_PIO2_25 IOPCTL_MUX(89, 15) /* PIO2_25 */ +#define SWCLK_PIO2_25 IOPCTL_MUX(89, 1) /* PIO2_25 */ +#define GPIO_PIO226_PIO2_26 IOPCTL_MUX(90, 0) /* PIO2_26 */ +#define SMARTDMA_SMARTDMA_PIO26_PIO2_26 IOPCTL_MUX(90, 15) /* PIO2_26 */ +#define SWDIO_PIO2_26 IOPCTL_MUX(90, 1) /* PIO2_26 */ +#define GPIO_PIO227_PIO2_27 IOPCTL_MUX(91, 0) /* PIO2_27 */ +#define SMARTDMA_SMARTDMA_PIO27_PIO2_27 IOPCTL_MUX(91, 15) /* PIO2_27 */ +#define USB1_OVERCURRENTN_PIO2_27 IOPCTL_MUX(91, 1) /* PIO2_27 */ +#define CLKOUT_PIO2_29 IOPCTL_MUX(93, 5) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOPCTL_MUX(93, 0) /* PIO2_29 */ +#define I3C0_SCL_PIO2_29 IOPCTL_MUX(93, 1) /* PIO2_29 */ +#define SCT0_OUT0_PIO2_29 IOPCTL_MUX(93, 2) /* PIO2_29 */ +#define SMARTDMA_SMARTDMA_PIO29_PIO2_29 IOPCTL_MUX(93, 15) /* PIO2_29 */ +#define CLKIN_PIO2_30 IOPCTL_MUX(94, 5) /* PIO2_30 */ +#define CMP0_OUT_PIO2_30 IOPCTL_MUX(94, 7) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOPCTL_MUX(94, 0) /* PIO2_30 */ +#define I3C0_SDA_PIO2_30 IOPCTL_MUX(94, 1) /* PIO2_30 */ +#define SCT0_OUT3_PIO2_30 IOPCTL_MUX(94, 2) /* PIO2_30 */ +#define SMARTDMA_SMARTDMA_PIO30_PIO2_30 IOPCTL_MUX(94, 15) /* PIO2_30 */ +#define ACMP0_ACMP_IN2_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define CTIMER0_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define GPIO_PIO231_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define I3C0_PUR_PIO2_31 IOPCTL_MUX(95, 1) /* PIO2_31 */ +#define SCT0_OUT7_PIO2_31 IOPCTL_MUX(95, 2) /* PIO2_31 */ +#define SMARTDMA_SMARTDMA_PIO31_PIO2_31 IOPCTL_MUX(95, 15) /* PIO2_31 */ +#define SWO_PIO2_31 IOPCTL_MUX(95, 5) /* PIO2_31 */ +#define UTICK0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 3) /* PIO2_31 */ +#define FC6_CTS_SDA_SSEL0_PIO3_28 IOPCTL_MUX(124, 1) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOPCTL_MUX(124, 0) /* PIO3_28 */ +#define FC6_RTS_SCL_SSEL1_PIO3_29 IOPCTL_MUX(125, 1) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOPCTL_MUX(125, 0) /* PIO3_29 */ +#define DBI_CSX_PIO4_20 IOPCTL_MUX(148, 1) /* PIO4_20 */ +#define FC11_SCK_PIO4_20 IOPCTL_MUX(148, 6) /* PIO4_20 */ +#define FLEXIO0_IO0_PIO4_20 IOPCTL_MUX(148, 8) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOPCTL_MUX(148, 0) /* PIO4_20 */ +#define USDHC1_USDHC_DATA6_PIO4_20 IOPCTL_MUX(148, 4) /* PIO4_20 */ +#define DBI_DSX_PIO4_21 IOPCTL_MUX(149, 1) /* PIO4_21 */ +#define FC11_TXD_SCL_MISO_PIO4_21 IOPCTL_MUX(149, 6) /* PIO4_21 */ +#define FLEXIO0_IO1_PIO4_21 IOPCTL_MUX(149, 8) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOPCTL_MUX(149, 0) /* PIO4_21 */ +#define USDHC1_USDHC_DATA7_PIO4_21 IOPCTL_MUX(149, 4) /* PIO4_21 */ +#define FC11_RXD_SDA_MOSI_PIO4_22 IOPCTL_MUX(150, 6) /* PIO4_22 */ +#define FLEXIO0_IO2_PIO4_22 IOPCTL_MUX(150, 8) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOPCTL_MUX(150, 0) /* PIO4_22 */ +#define SD1_CARD_DET_N_PIO4_22 IOPCTL_MUX(150, 4) /* PIO4_22 */ +#define DBI_RWDX_PIO4_23 IOPCTL_MUX(151, 1) /* PIO4_23 */ +#define FC11_CTS_SDA_SSELN0_PIO4_23 IOPCTL_MUX(151, 6) /* PIO4_23 */ +#define FLEXIO0_IO3_PIO4_23 IOPCTL_MUX(151, 8) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOPCTL_MUX(151, 0) /* PIO4_23 */ +#define LCD_ENABLE_PIO4_23 IOPCTL_MUX(151, 2) /* PIO4_23 */ +#define SD1_RESET_N_PIO4_23 IOPCTL_MUX(151, 4) /* PIO4_23 */ +#define TRACECLK_PIO4_23 IOPCTL_MUX(151, 7) /* PIO4_23 */ +#define DBI_WRX_PIO4_24 IOPCTL_MUX(152, 1) /* PIO4_24 */ +#define FC11_RTS_SCL_SSELN1_PIO4_24 IOPCTL_MUX(152, 6) /* PIO4_24 */ +#define FLEXIO0_IO4_PIO4_24 IOPCTL_MUX(152, 8) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOPCTL_MUX(152, 0) /* PIO4_24 */ +#define LCD_DTCLK_PIO4_24 IOPCTL_MUX(152, 2) /* PIO4_24 */ +#define SD1_VOLT_PIO4_24 IOPCTL_MUX(152, 4) /* PIO4_24 */ +#define SWD_TRACEDATA0_PIO4_24 IOPCTL_MUX(152, 7) /* PIO4_24 */ +#define DBI_E_PIO4_25 IOPCTL_MUX(153, 1) /* PIO4_25 */ +#define FC11_SSELN2_PIO4_25 IOPCTL_MUX(153, 6) /* PIO4_25 */ +#define FLEXIO0_IO5_PIO4_25 IOPCTL_MUX(153, 8) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOPCTL_MUX(153, 0) /* PIO4_25 */ +#define LCD_HSYNC_PIO4_25 IOPCTL_MUX(153, 2) /* PIO4_25 */ +#define SWD_TRACEDATA1_PIO4_25 IOPCTL_MUX(153, 7) /* PIO4_25 */ +#define FC11_SSELN3_PIO4_26 IOPCTL_MUX(154, 6) /* PIO4_26 */ +#define FLEXIO0_IO6_PIO4_26 IOPCTL_MUX(154, 8) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOPCTL_MUX(154, 0) /* PIO4_26 */ +#define LCD_VSYNC_PIO4_26 IOPCTL_MUX(154, 1) /* PIO4_26 */ +#define SWD_TRACEDATA2_PIO4_26 IOPCTL_MUX(154, 7) /* PIO4_26 */ +#define FLEXIO0_IO7_PIO4_27 IOPCTL_MUX(155, 8) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOPCTL_MUX(155, 0) /* PIO4_27 */ +#define LCDIF_dbi_data0_PIO4_27 IOPCTL_MUX(155, 2) /* PIO4_27 */ +#define LCDIF_lcdif_data0_PIO4_27 IOPCTL_MUX(155, 1) /* PIO4_27 */ +#define SWD_TRACEDATA3_PIO4_27 IOPCTL_MUX(155, 7) /* PIO4_27 */ +#define FLEXIO0_IO8_PIO4_28 IOPCTL_MUX(156, 8) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOPCTL_MUX(156, 0) /* PIO4_28 */ +#define LCDIF_dbi_data1_PIO4_28 IOPCTL_MUX(156, 2) /* PIO4_28 */ +#define LCDIF_lcdif_data1_PIO4_28 IOPCTL_MUX(156, 1) /* PIO4_28 */ +#define FC12_SCK_PIO4_29 IOPCTL_MUX(157, 6) /* PIO4_29 */ +#define FLEXIO0_IO9_PIO4_29 IOPCTL_MUX(157, 8) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOPCTL_MUX(157, 0) /* PIO4_29 */ +#define LCDIF_dbi_data2_PIO4_29 IOPCTL_MUX(157, 2) /* PIO4_29 */ +#define LCDIF_lcdif_data2_PIO4_29 IOPCTL_MUX(157, 1) /* PIO4_29 */ +#define FC12_TXD_SCL_MISO_PIO4_30 IOPCTL_MUX(158, 6) /* PIO4_30 */ +#define FLEXIO0_IO10_PIO4_30 IOPCTL_MUX(158, 8) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOPCTL_MUX(158, 0) /* PIO4_30 */ +#define LCDIF_dbi_data3_PIO4_30 IOPCTL_MUX(158, 2) /* PIO4_30 */ +#define LCDIF_lcdif_data3_PIO4_30 IOPCTL_MUX(158, 1) /* PIO4_30 */ +#define FC12_RXD_SDA_MOSI_PIO4_31 IOPCTL_MUX(159, 6) /* PIO4_31 */ +#define FLEXIO0_IO11_PIO4_31 IOPCTL_MUX(159, 8) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOPCTL_MUX(159, 0) /* PIO4_31 */ +#define LCDIF_dbi_data4_PIO4_31 IOPCTL_MUX(159, 2) /* PIO4_31 */ +#define LCDIF_lcdif_data4_PIO4_31 IOPCTL_MUX(159, 1) /* PIO4_31 */ +#define DMIC0_CLK01_PIO5_4 IOPCTL_MUX(164, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOPCTL_MUX(164, 0) /* PIO5_4 */ +#define LCDIF_dbi_data9_PIO5_4 IOPCTL_MUX(164, 2) /* PIO5_4 */ +#define LCDIF_lcdif_data9_PIO5_4 IOPCTL_MUX(164, 1) /* PIO5_4 */ +#define DMIC0_DATA01_PIO5_8 IOPCTL_MUX(168, 4) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOPCTL_MUX(168, 0) /* PIO5_8 */ +#define LCDIF_dbi_data13_PIO5_8 IOPCTL_MUX(168, 2) /* PIO5_8 */ +#define LCDIF_lcdif_data13_PIO5_8 IOPCTL_MUX(168, 1) /* PIO5_8 */ +#define GPIO_PIO627_PIO6_27 IOPCTL_MUX(219, 0) /* PIO6_27 */ +#define MCLK_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN0_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN1_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN2_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN3_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN4_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN5_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ +#define SCT0_IN6_PIO6_27 IOPCTL_MUX(219, 1) /* PIO6_27 */ + +#endif diff --git a/dts/nxp/nxp_imx/rt/MIMXRT555SFFOC-pinctrl.h b/dts/nxp/nxp_imx/rt/MIMXRT555SFFOC-pinctrl.h new file mode 100644 index 000000000..4df861d0e --- /dev/null +++ b/dts/nxp/nxp_imx/rt/MIMXRT555SFFOC-pinctrl.h @@ -0,0 +1,5893 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from MIMXRT555SFFOC/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MIMXRT555SFFOC_ +#define _ZEPHYR_DTS_BINDING_MIMXRT555SFFOC_ + +#define IOPCTL_MUX(offset, mux) \ + ((((offset) & 0xFFF) << 20) | \ + (((mux) & 0xF) << 0)) + +#define CTIMER0_MATCH0_PIO0_0 IOPCTL_MUX(0, 4) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG33_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG34_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG35_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG36_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG33_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG34_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG35_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG36_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define FC0_SCK_PIO0_0 IOPCTL_MUX(0, 1) /* PIO0_0 */ +#define GPIO_INT_BMAT_PIO0_0 IOPCTL_MUX(0, 6) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define I2S_BRIDGE_CLK_IN_PIO0_0 IOPCTL_MUX(0, 5) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOPCTL_MUX(0, 8) /* PIO0_0 */ +#define SMARTDMA_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SMARTDMA_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PMIC_I2C_SDA IOPCTL_MUX(257, 0) /* PIO0_0 */ +#define PMIC_I2C_SCL IOPCTL_MUX(256, 0) /* PIO0_0 */ +#define CTIMER0_MATCH1_PIO0_1 IOPCTL_MUX(1, 4) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG33_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG34_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG35_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG36_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG33_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG34_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG35_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG36_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_1 IOPCTL_MUX(1, 1) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define I2S_BRIDGE_WS_IN_PIO0_1 IOPCTL_MUX(1, 5) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOPCTL_MUX(1, 8) /* PIO0_1 */ +#define SMARTDMA_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SMARTDMA_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define CTIMER0_MATCH2_PIO0_2 IOPCTL_MUX(2, 4) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG33_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG34_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG35_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG36_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG33_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG34_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG35_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG36_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_2 IOPCTL_MUX(2, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define I2S_BRIDGE_DATA_IN_PIO0_2 IOPCTL_MUX(2, 5) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOPCTL_MUX(2, 8) /* PIO0_2 */ +#define SMARTDMA_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SMARTDMA_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define CTIMER0_MATCH3_PIO0_3 IOPCTL_MUX(3, 4) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG33_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG34_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG35_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG36_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG33_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG34_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG35_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG36_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define FC0_CTS_SDA_SSEL0_PIO0_3 IOPCTL_MUX(3, 1) /* PIO0_3 */ +#define FC1_SSEL2_PIO0_3 IOPCTL_MUX(3, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOPCTL_MUX(3, 8) /* PIO0_3 */ +#define SMARTDMA_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SMARTDMA_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define CMP0_OUT_PIO0_4 IOPCTL_MUX(4, 7) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG33_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG34_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG35_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG36_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG33_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG34_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG35_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG36_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define FC0_RTS_SCL_SSEL1_PIO0_4 IOPCTL_MUX(4, 1) /* PIO0_4 */ +#define FC1_SSEL3_PIO0_4 IOPCTL_MUX(4, 5) /* PIO0_4 */ +#define FLEXIO0_TRIG0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOPCTL_MUX(4, 8) /* PIO0_4 */ +#define SMARTDMA_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SMARTDMA_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define ADC0_CH0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG33_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG34_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG35_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG36_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG33_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG34_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG35_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG36_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define FC0_SSEL2_PIO0_5 IOPCTL_MUX(5, 1) /* PIO0_5 */ +#define FLEXIO0_TRIG1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_OUT0_PIO0_5 IOPCTL_MUX(5, 3) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOPCTL_MUX(5, 8) /* PIO0_5 */ +#define SMARTDMA_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SMARTDMA_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define ADC0_CH8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER0_MATCH0_PIO0_6 IOPCTL_MUX(6, 4) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG33_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG34_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG35_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG36_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG33_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG34_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG35_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG36_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define FC0_SSEL3_PIO0_6 IOPCTL_MUX(6, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_OUT1_PIO0_6 IOPCTL_MUX(6, 3) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOPCTL_MUX(6, 8) /* PIO0_6 */ +#define SMARTDMA_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SMARTDMA_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER1_MATCH0_PIO0_7 IOPCTL_MUX(7, 4) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG33_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG34_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG35_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG36_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG33_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG34_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG35_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG36_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOPCTL_MUX(7, 1) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_7 IOPCTL_MUX(7, 5) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SCT0_IN0_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN1_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN2_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN3_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN4_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN5_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN6_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_OUT4_PIO0_7 IOPCTL_MUX(7, 3) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOPCTL_MUX(7, 8) /* PIO0_7 */ +#define SMARTDMA_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SMARTDMA_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define CTIMER1_MATCH1_PIO0_8 IOPCTL_MUX(8, 4) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG33_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG34_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG35_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG36_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG33_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG34_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG35_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG36_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_8 IOPCTL_MUX(8, 1) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define I2S_BRIDGE_WS_OUT_PIO0_8 IOPCTL_MUX(8, 5) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define SCT0_IN0_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN1_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN2_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN3_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN4_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN5_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN6_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_OUT5_PIO0_8 IOPCTL_MUX(8, 3) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOPCTL_MUX(8, 8) /* PIO0_8 */ +#define CTIMER1_MATCH2_PIO0_9 IOPCTL_MUX(9, 4) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG33_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG34_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG35_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG36_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG33_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG34_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG35_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG36_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_9 IOPCTL_MUX(9, 1) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_9 IOPCTL_MUX(9, 5) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define SCT0_IN0_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN1_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN2_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN3_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN4_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN5_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN6_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_OUT6_PIO0_9 IOPCTL_MUX(9, 3) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOPCTL_MUX(9, 8) /* PIO0_9 */ +#define CTIMER1_MATCH3_PIO0_10 IOPCTL_MUX(10, 4) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG33_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG34_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG35_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG36_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG33_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG34_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG35_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG36_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define FC0_SSEL2_PIO0_10 IOPCTL_MUX(10, 5) /* PIO0_10 */ +#define FC1_CTS_SDA_SSEL0_PIO0_10 IOPCTL_MUX(10, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define SCT0_IN0_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN1_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN2_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN3_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN4_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN5_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN6_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_OUT7_PIO0_10 IOPCTL_MUX(10, 3) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOPCTL_MUX(10, 8) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG33_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG34_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG35_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG36_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG33_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG34_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG35_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG36_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define FC0_SSEL3_PIO0_11 IOPCTL_MUX(11, 5) /* PIO0_11 */ +#define FC1_RTS_SCL_SSEL1_PIO0_11 IOPCTL_MUX(11, 1) /* PIO0_11 */ +#define FLEXIO0_TRIG2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define SCT0_IN0_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN1_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN2_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN3_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN4_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN5_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN6_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_OUT8_PIO0_11 IOPCTL_MUX(11, 3) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOPCTL_MUX(11, 8) /* PIO0_11 */ +#define ADC0_CH1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG33_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG34_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG35_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG36_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG33_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG34_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG35_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG36_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define FC1_SSEL2_PIO0_12 IOPCTL_MUX(12, 1) /* PIO0_12 */ +#define FLEXIO0_TRIG3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_OUT2_PIO0_12 IOPCTL_MUX(12, 3) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOPCTL_MUX(12, 8) /* PIO0_12 */ +#define ADC0_CH9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define CTIMER0_MATCH1_PIO0_13 IOPCTL_MUX(13, 4) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG33_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG34_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG35_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG36_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG33_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG34_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG35_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG36_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define FC1_SSEL3_PIO0_13 IOPCTL_MUX(13, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_OUT3_PIO0_13 IOPCTL_MUX(13, 3) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOPCTL_MUX(13, 8) /* PIO0_13 */ +#define CTIMER2_MATCH0_PIO0_14 IOPCTL_MUX(14, 4) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG33_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG34_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG35_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG36_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG33_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG34_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG35_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG36_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define FC2_SCK_PIO0_14 IOPCTL_MUX(14, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define I2S_BRIDGE_CLK_IN_PIO0_14 IOPCTL_MUX(14, 5) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_OUT0_PIO0_14 IOPCTL_MUX(14, 3) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOPCTL_MUX(14, 8) /* PIO0_14 */ +#define CTIMER2_MATCH1_PIO0_15 IOPCTL_MUX(15, 4) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG33_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG34_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG35_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG36_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG33_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG34_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG35_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG36_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_15 IOPCTL_MUX(15, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define I2S_BRIDGE_WS_IN_PIO0_15 IOPCTL_MUX(15, 5) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define SCT0_IN0_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN1_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN2_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN3_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN4_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN5_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN6_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_OUT1_PIO0_15 IOPCTL_MUX(15, 3) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOPCTL_MUX(15, 8) /* PIO0_15 */ +#define CTIMER2_MATCH2_PIO0_16 IOPCTL_MUX(16, 4) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG33_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG34_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG35_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG36_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG33_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG34_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG35_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG36_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_16 IOPCTL_MUX(16, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define I2S_BRIDGE_DATA_IN_PIO0_16 IOPCTL_MUX(16, 5) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define SCT0_IN0_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN1_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN2_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN3_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN4_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN5_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN6_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_OUT2_PIO0_16 IOPCTL_MUX(16, 3) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOPCTL_MUX(16, 8) /* PIO0_16 */ +#define CTIMER2_MATCH3_PIO0_17 IOPCTL_MUX(17, 4) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG33_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG34_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG35_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG36_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG33_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG34_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG35_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG36_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define FC2_CTS_SDA_SSEL0_PIO0_17 IOPCTL_MUX(17, 1) /* PIO0_17 */ +#define FC5_SSEL2_PIO0_17 IOPCTL_MUX(17, 5) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_OUT3_PIO0_17 IOPCTL_MUX(17, 3) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOPCTL_MUX(17, 8) /* PIO0_17 */ +#define CTIMER0_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG33_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG34_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG35_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG36_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG33_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG34_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG35_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG36_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define FC2_RTS_SCL_SSEL1_PIO0_18 IOPCTL_MUX(18, 1) /* PIO0_18 */ +#define FC5_SSEL3_PIO0_18 IOPCTL_MUX(18, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define SCT0_IN0_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN1_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN2_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN3_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN4_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN5_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN6_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_OUT6_PIO0_18 IOPCTL_MUX(18, 3) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOPCTL_MUX(18, 8) /* PIO0_18 */ +#define ADC0_CH2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG33_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG34_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG35_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG36_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG33_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG34_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG35_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG36_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define FC2_SSEL2_PIO0_19 IOPCTL_MUX(19, 1) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define SCT0_IN0_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN1_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN2_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN3_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN4_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN5_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN6_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_OUT4_PIO0_19 IOPCTL_MUX(19, 3) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOPCTL_MUX(19, 8) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 5) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER0_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER1_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER2_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER3_MATCH0_PIO0_21 IOPCTL_MUX(21, 4) /* PIO0_21 */ +#define CTIMER4_CAPTURE0_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE1_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE2_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define CTIMER4_CAPTURE3_PIO0_21 IOPCTL_MUX(21, 5) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG33_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG34_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG35_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG36_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG33_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG34_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG35_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG36_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define FC3_SCK_PIO0_21 IOPCTL_MUX(21, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define SCT0_IN0_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN1_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN2_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN3_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN4_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN5_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_IN6_PIO0_21 IOPCTL_MUX(21, 2) /* PIO0_21 */ +#define SCT0_OUT5_PIO0_21 IOPCTL_MUX(21, 3) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOPCTL_MUX(21, 8) /* PIO0_21 */ +#define TRACECLK_PIO0_21 IOPCTL_MUX(21, 6) /* PIO0_21 */ +#define CTIMER0_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER0_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER1_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER2_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER3_MATCH1_PIO0_22 IOPCTL_MUX(22, 4) /* PIO0_22 */ +#define CTIMER4_CAPTURE0_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE1_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE2_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define CTIMER4_CAPTURE3_PIO0_22 IOPCTL_MUX(22, 5) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG33_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG34_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG35_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG36_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG33_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG34_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG35_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG36_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_22 IOPCTL_MUX(22, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define SCT0_IN0_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN1_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN2_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN3_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN4_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN5_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_IN6_PIO0_22 IOPCTL_MUX(22, 2) /* PIO0_22 */ +#define SCT0_OUT6_PIO0_22 IOPCTL_MUX(22, 3) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOPCTL_MUX(22, 8) /* PIO0_22 */ +#define SWD_TRACEDATA0_PIO0_22 IOPCTL_MUX(22, 6) /* PIO0_22 */ +#define CTIMER0_MATCH3_PIO0_23 IOPCTL_MUX(23, 5) /* PIO0_23 */ +#define CTIMER3_MATCH2_PIO0_23 IOPCTL_MUX(23, 4) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG33_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG34_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG35_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG36_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG33_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG34_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG35_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG36_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_23 IOPCTL_MUX(23, 1) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define SCT0_IN0_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN1_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN2_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN3_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN4_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN5_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_IN6_PIO0_23 IOPCTL_MUX(23, 2) /* PIO0_23 */ +#define SCT0_OUT8_PIO0_23 IOPCTL_MUX(23, 3) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOPCTL_MUX(23, 8) /* PIO0_23 */ +#define SWD_TRACEDATA1_PIO0_23 IOPCTL_MUX(23, 6) /* PIO0_23 */ +#define CLKOUT_PIO0_24 IOPCTL_MUX(24, 7) /* PIO0_24 */ +#define CTIMER3_MATCH3_PIO0_24 IOPCTL_MUX(24, 4) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG33_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG34_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG35_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG36_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG33_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG34_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG35_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG36_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define FC2_SSEL2_PIO0_24 IOPCTL_MUX(24, 5) /* PIO0_24 */ +#define FC3_CTS_SDA_SSEL0_PIO0_24 IOPCTL_MUX(24, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define SCT0_IN0_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN1_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN2_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN3_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN4_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN5_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_IN6_PIO0_24 IOPCTL_MUX(24, 2) /* PIO0_24 */ +#define SCT0_OUT9_PIO0_24 IOPCTL_MUX(24, 3) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOPCTL_MUX(24, 8) /* PIO0_24 */ +#define SWD_TRACEDATA2_PIO0_24 IOPCTL_MUX(24, 6) /* PIO0_24 */ +#define CLKIN_PIO0_25 IOPCTL_MUX(25, 7) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG33_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG34_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG35_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG36_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG33_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG34_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG35_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG36_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define FC2_SSEL3_PIO0_25 IOPCTL_MUX(25, 5) /* PIO0_25 */ +#define FC3_RTS_SCL_SSEL1_PIO0_25 IOPCTL_MUX(25, 1) /* PIO0_25 */ +#define FREQME_IN0_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define FREQME_IN1_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOPCTL_MUX(25, 8) /* PIO0_25 */ +#define SWD_TRACEDATA3_PIO0_25 IOPCTL_MUX(25, 6) /* PIO0_25 */ +#define CTIMER4_MATCH0_PIO0_28 IOPCTL_MUX(28, 4) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG33_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG34_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG35_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG36_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG33_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG34_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG35_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG36_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define FC4_SCK_PIO0_28 IOPCTL_MUX(28, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_28 IOPCTL_MUX(28, 5) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOPCTL_MUX(28, 8) /* PIO0_28 */ +#define CTIMER4_MATCH1_PIO0_29 IOPCTL_MUX(29, 4) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG33_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG34_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG35_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG36_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG33_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG34_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG35_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG36_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_29 IOPCTL_MUX(29, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define I2S_BRIDGE_WS_OUT_PIO0_29 IOPCTL_MUX(29, 5) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOPCTL_MUX(29, 8) /* PIO0_29 */ +#define CTIMER4_MATCH2_PIO0_30 IOPCTL_MUX(30, 4) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG33_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG34_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG35_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG36_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG33_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG34_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG35_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG36_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_30 IOPCTL_MUX(30, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_30 IOPCTL_MUX(30, 5) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOPCTL_MUX(30, 8) /* PIO0_30 */ +#define CTIMER4_MATCH3_PIO0_31 IOPCTL_MUX(31, 4) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG33_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG34_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG35_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG36_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG33_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG34_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG35_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG36_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define FC3_SSEL2_PIO0_31 IOPCTL_MUX(31, 5) /* PIO0_31 */ +#define FC4_CTS_SDA_SSEL0_PIO0_31 IOPCTL_MUX(31, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define SCT0_IN0_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN1_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN2_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN3_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN4_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN5_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN6_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_OUT6_PIO0_31 IOPCTL_MUX(31, 3) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOPCTL_MUX(31, 8) /* PIO0_31 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG33_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG34_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG35_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG36_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG33_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG34_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG35_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG36_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define FC3_SSEL3_PIO1_0 IOPCTL_MUX(32, 5) /* PIO1_0 */ +#define FC4_RTS_SCL_SSEL1_PIO1_0 IOPCTL_MUX(32, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_OUT7_PIO1_0 IOPCTL_MUX(32, 3) /* PIO1_0 */ +#define SMARTDMA_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SMARTDMA_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG33_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG34_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG35_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG36_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG33_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG34_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG35_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG36_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define FC5_SCK_PIO1_3 IOPCTL_MUX(35, 1) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define HS_SPI1_SCK_PIO1_3 IOPCTL_MUX(35, 6) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define SMARTDMA_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG33_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG34_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG35_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG36_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG33_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG34_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG35_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG36_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define FC5_TXD_SCL_MISO_WS_PIO1_4 IOPCTL_MUX(36, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define HS_SPI1_MISO_PIO1_4 IOPCTL_MUX(36, 6) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define SMARTDMA_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG33_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG34_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG35_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG36_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG33_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG34_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG35_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG36_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO1_5 IOPCTL_MUX(37, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define HS_SPI1_MOSI_PIO1_5 IOPCTL_MUX(37, 6) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define SMARTDMA_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG33_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG34_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG35_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG36_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG33_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG34_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG35_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG36_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define FC4_SSEL2_PIO1_6 IOPCTL_MUX(38, 5) /* PIO1_6 */ +#define FC5_CTS_SDA_SSEL0_PIO1_6 IOPCTL_MUX(38, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define HS_SPI1_SSELN0_PIO1_6 IOPCTL_MUX(38, 6) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_OUT4_PIO1_6 IOPCTL_MUX(38, 3) /* PIO1_6 */ +#define SMARTDMA_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SMARTDMA_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define CTIMER0_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG33_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG34_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG35_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG36_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG33_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG34_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG35_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG36_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define FC4_SSEL3_PIO1_7 IOPCTL_MUX(39, 5) /* PIO1_7 */ +#define FC5_RTS_SCL_SSEL1_PIO1_7 IOPCTL_MUX(39, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define HS_SPI1_SSELN1_PIO1_7 IOPCTL_MUX(39, 6) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_OUT5_PIO1_7 IOPCTL_MUX(39, 3) /* PIO1_7 */ +#define SMARTDMA_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SMARTDMA_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define CLKOUT_PIO1_10 IOPCTL_MUX(42, 7) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG30_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG31_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG32_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG33_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG34_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG35_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG36_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG20_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG21_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG22_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG23_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG24_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG25_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG26_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG27_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG28_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG29_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG30_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG31_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG32_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG33_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG34_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG35_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG36_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG8_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG9_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define FREQME_IN0_PIO1_10 IOPCTL_MUX(42, 3) /* PIO1_10 */ +#define FREQME_IN1_PIO1_10 IOPCTL_MUX(42, 3) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define MCLK_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define SCT0_IN0_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN1_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN2_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN3_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN4_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN5_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN6_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define CTIMER2_MATCH0_PIO1_11 IOPCTL_MUX(43, 4) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG33_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG34_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG35_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG36_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG33_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG34_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG35_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG36_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define HS_SPI0_SCK_PIO1_11 IOPCTL_MUX(43, 1) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define CTIMER2_MATCH1_PIO1_12 IOPCTL_MUX(44, 4) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG33_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG34_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG35_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG36_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG33_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG34_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG35_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG36_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define HS_SPI0_MISO_PIO1_12 IOPCTL_MUX(44, 1) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define CTIMER2_MATCH2_PIO1_13 IOPCTL_MUX(45, 4) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG33_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG34_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG35_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG36_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG33_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG34_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG35_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG36_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define HS_SPI0_MOSI_PIO1_13 IOPCTL_MUX(45, 1) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define CTIMER2_MATCH3_PIO1_14 IOPCTL_MUX(46, 4) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG33_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG34_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG35_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG36_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG33_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG34_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG35_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG36_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define HS_SPI0_SSELN0_PIO1_14 IOPCTL_MUX(46, 1) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define CTIMER3_MATCH0_PIO1_15 IOPCTL_MUX(47, 4) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG33_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG34_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG35_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG36_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG33_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG34_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG35_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG36_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define HS_SPI0_SSELN1_PIO1_15 IOPCTL_MUX(47, 1) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define CTIMER3_MATCH3_PIO1_18 IOPCTL_MUX(50, 4) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG33_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG34_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG35_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG36_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG33_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG34_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG35_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG36_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define FLEXSPI0_SCLK_PIO1_18 IOPCTL_MUX(50, 1) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define SCT0_IN0_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN1_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN2_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN3_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN4_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN5_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN6_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define CLKOUT_PIO1_19 IOPCTL_MUX(51, 7) /* PIO1_19 */ +#define CTIMER4_MATCH0_PIO1_19 IOPCTL_MUX(51, 4) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG33_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG34_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG35_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG36_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG33_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG34_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG35_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG36_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define FLEXSPI0_SS0_N_PIO1_19 IOPCTL_MUX(51, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define SCT0_OUT0_PIO1_19 IOPCTL_MUX(51, 2) /* PIO1_19 */ +#define CTIMER4_MATCH1_PIO1_20 IOPCTL_MUX(52, 4) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG33_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG34_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG35_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG36_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG33_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG34_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG35_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG36_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define FLEXSPI0_DATA0_PIO1_20 IOPCTL_MUX(52, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define SCT0_IN0_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN1_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN2_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN3_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN4_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN5_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN6_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define CTIMER4_MATCH2_PIO1_21 IOPCTL_MUX(53, 4) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG33_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG34_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG35_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG36_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG33_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG34_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG35_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG36_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define FLEXSPI0_DATA1_PIO1_21 IOPCTL_MUX(53, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define SCT0_OUT1_PIO1_21 IOPCTL_MUX(53, 2) /* PIO1_21 */ +#define CTIMER4_MATCH3_PIO1_22 IOPCTL_MUX(54, 4) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG33_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG34_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG35_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG36_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG33_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG34_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG35_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG36_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define FLEXSPI0_DATA2_PIO1_22 IOPCTL_MUX(54, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define CTIMER0_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG33_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG34_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG35_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG36_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG33_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG34_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG35_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG36_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define FLEXSPI0_DATA3_PIO1_23 IOPCTL_MUX(55, 1) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define SCT0_OUT2_PIO1_23 IOPCTL_MUX(55, 2) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG30_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG31_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG32_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG33_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG34_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG35_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG36_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG20_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG21_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG22_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG23_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG24_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG25_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG26_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG27_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG28_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG29_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG30_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG31_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG32_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG33_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG34_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG35_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG36_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG8_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG9_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define FLEXSPI0_DATA4_PIO1_24 IOPCTL_MUX(56, 1) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define SCT0_IN0_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN1_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN2_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN3_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN4_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN5_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN6_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG30_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG31_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG32_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG33_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG34_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG35_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG36_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG20_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG21_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG22_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG23_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG24_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG25_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG26_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG27_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG28_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG29_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG30_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG31_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG32_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG33_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG34_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG35_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG36_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG8_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG9_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define FLEXSPI0_DATA5_PIO1_25 IOPCTL_MUX(57, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define SCT0_OUT3_PIO1_25 IOPCTL_MUX(57, 2) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG30_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG31_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG32_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG33_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG34_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG35_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG36_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG20_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG21_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG22_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG23_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG24_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG25_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG26_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG27_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG28_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG29_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG30_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG31_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG32_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG33_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG34_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG35_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG36_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG8_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG9_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define FLEXSPI0_DATA6_PIO1_26 IOPCTL_MUX(58, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define SCT0_IN0_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN1_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN2_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN3_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN4_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN5_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN6_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG30_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG31_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG32_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG33_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG34_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG35_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG36_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG20_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG21_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG22_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG23_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG24_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG25_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG26_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG27_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG28_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG29_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG30_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG31_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG32_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG33_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG34_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG35_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG36_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG8_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG9_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define FLEXSPI0_DATA7_PIO1_27 IOPCTL_MUX(59, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define SCT0_OUT4_PIO1_27 IOPCTL_MUX(59, 2) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG33_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG34_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG35_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG36_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG33_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG34_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG35_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG36_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define FLEXSPI0_DQS_PIO1_28 IOPCTL_MUX(60, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define SCT0_IN0_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN1_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN2_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN3_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN4_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN5_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN6_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define CTIMER0_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG30_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG31_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG32_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG33_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG34_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG35_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG36_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG20_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG21_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG22_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG23_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG24_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG25_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG26_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG27_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG28_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG29_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG30_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG31_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG32_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG33_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG34_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG35_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG36_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG8_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG9_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define FLEXSPI0_SCLK_N_PIO1_29 IOPCTL_MUX(61, 5) /* PIO1_29 */ +#define FLEXSPI0_SS1_N_PIO1_29 IOPCTL_MUX(61, 1) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define SCT0_OUT5_PIO1_29 IOPCTL_MUX(61, 2) /* PIO1_29 */ +#define UTICK0_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 3) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG30_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG31_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG32_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG33_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG34_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG35_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG36_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG20_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG21_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG22_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG23_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG24_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG25_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG26_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG27_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG28_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG29_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG30_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG31_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG32_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG33_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG34_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG35_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG36_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG8_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG9_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SD0_CLK_PIO1_30 IOPCTL_MUX(62, 1) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG30_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG31_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG32_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG33_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG34_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG35_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG36_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG20_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG21_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG22_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG23_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG24_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG25_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG26_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG27_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG28_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG29_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG30_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG31_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG32_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG33_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG34_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG35_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG36_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG8_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG9_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define SCT0_IN0_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN1_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN2_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN3_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN4_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN5_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN6_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SD0_CMD_PIO1_31 IOPCTL_MUX(63, 1) /* PIO1_31 */ +#define GPIO_PIO20_PIO2_0 IOPCTL_MUX(64, 0) /* PIO2_0 */ +#define SCT0_IN0_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN1_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN2_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN3_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN4_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN5_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN6_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SMARTDMA_SMARTDMA_PIO0_PIO2_0 IOPCTL_MUX(64, 15) /* PIO2_0 */ +#define USDHC0_USDHC_DATA0_PIO2_0 IOPCTL_MUX(64, 1) /* PIO2_0 */ +#define GPIO_PIO21_PIO2_1 IOPCTL_MUX(65, 0) /* PIO2_1 */ +#define SCT0_IN0_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN1_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN2_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN3_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN4_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN5_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN6_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SMARTDMA_SMARTDMA_PIO1_PIO2_1 IOPCTL_MUX(65, 15) /* PIO2_1 */ +#define USDHC0_USDHC_DATA1_PIO2_1 IOPCTL_MUX(65, 1) /* PIO2_1 */ +#define GPIO_PIO22_PIO2_2 IOPCTL_MUX(66, 0) /* PIO2_2 */ +#define SCT0_OUT0_PIO2_2 IOPCTL_MUX(66, 2) /* PIO2_2 */ +#define SMARTDMA_SMARTDMA_PIO2_PIO2_2 IOPCTL_MUX(66, 15) /* PIO2_2 */ +#define USDHC0_USDHC_DATA2_PIO2_2 IOPCTL_MUX(66, 1) /* PIO2_2 */ +#define GPIO_PIO23_PIO2_3 IOPCTL_MUX(67, 0) /* PIO2_3 */ +#define SCT0_OUT1_PIO2_3 IOPCTL_MUX(67, 2) /* PIO2_3 */ +#define SMARTDMA_SMARTDMA_PIO3_PIO2_3 IOPCTL_MUX(67, 15) /* PIO2_3 */ +#define USDHC0_USDHC_DATA3_PIO2_3 IOPCTL_MUX(67, 1) /* PIO2_3 */ +#define GPIO_PIO24_PIO2_4 IOPCTL_MUX(68, 0) /* PIO2_4 */ +#define SCT0_OUT2_PIO2_4 IOPCTL_MUX(68, 2) /* PIO2_4 */ +#define SD0_DS_PIO2_4 IOPCTL_MUX(68, 5) /* PIO2_4 */ +#define SD0_WR_PRT_PIO2_4 IOPCTL_MUX(68, 1) /* PIO2_4 */ +#define SMARTDMA_SMARTDMA_PIO4_PIO2_4 IOPCTL_MUX(68, 15) /* PIO2_4 */ +#define FC8_SCK_PIO2_5 IOPCTL_MUX(69, 5) /* PIO2_5 */ +#define GPIO_PIO25_PIO2_5 IOPCTL_MUX(69, 0) /* PIO2_5 */ +#define SCT0_OUT3_PIO2_5 IOPCTL_MUX(69, 2) /* PIO2_5 */ +#define SMARTDMA_SMARTDMA_PIO5_PIO2_5 IOPCTL_MUX(69, 15) /* PIO2_5 */ +#define USDHC0_USDHC_DATA4_PIO2_5 IOPCTL_MUX(69, 1) /* PIO2_5 */ +#define CTIMER1_MATCH0_PIO2_6 IOPCTL_MUX(70, 4) /* PIO2_6 */ +#define FC8_TXD_SCL_MISO_WS_PIO2_6 IOPCTL_MUX(70, 5) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOPCTL_MUX(70, 0) /* PIO2_6 */ +#define SCT0_IN0_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN1_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN2_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN3_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN4_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN5_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN6_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SMARTDMA_SMARTDMA_PIO6_PIO2_6 IOPCTL_MUX(70, 15) /* PIO2_6 */ +#define USDHC0_USDHC_DATA5_PIO2_6 IOPCTL_MUX(70, 1) /* PIO2_6 */ +#define CTIMER1_MATCH1_PIO2_7 IOPCTL_MUX(71, 4) /* PIO2_7 */ +#define FC8_RXD_SDA_MOSI_DATA_PIO2_7 IOPCTL_MUX(71, 5) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOPCTL_MUX(71, 0) /* PIO2_7 */ +#define SCT0_IN0_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN1_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN2_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN3_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN4_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN5_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN6_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SMARTDMA_SMARTDMA_PIO7_PIO2_7 IOPCTL_MUX(71, 15) /* PIO2_7 */ +#define USDHC0_USDHC_DATA6_PIO2_7 IOPCTL_MUX(71, 1) /* PIO2_7 */ +#define CTIMER1_MATCH2_PIO2_8 IOPCTL_MUX(72, 4) /* PIO2_8 */ +#define FC8_CTS_SDA_SSEL0_PIO2_8 IOPCTL_MUX(72, 5) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOPCTL_MUX(72, 0) /* PIO2_8 */ +#define SCT0_OUT4_PIO2_8 IOPCTL_MUX(72, 2) /* PIO2_8 */ +#define SMARTDMA_SMARTDMA_PIO8_PIO2_8 IOPCTL_MUX(72, 15) /* PIO2_8 */ +#define USDHC0_USDHC_DATA7_PIO2_8 IOPCTL_MUX(72, 1) /* PIO2_8 */ +#define CTIMER1_MATCH3_PIO2_9 IOPCTL_MUX(73, 4) /* PIO2_9 */ +#define FC8_CTS_SDA_SSEL1_PIO2_9 IOPCTL_MUX(73, 5) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOPCTL_MUX(73, 0) /* PIO2_9 */ +#define SCT0_OUT5_PIO2_9 IOPCTL_MUX(73, 2) /* PIO2_9 */ +#define SD0_CARD_DET_N_PIO2_9 IOPCTL_MUX(73, 1) /* PIO2_9 */ +#define SMARTDMA_SMARTDMA_PIO9_PIO2_9 IOPCTL_MUX(73, 15) /* PIO2_9 */ +#define CTIMER2_MATCH0_PIO2_10 IOPCTL_MUX(74, 4) /* PIO2_10 */ +#define FC8_SSEL2_PIO2_10 IOPCTL_MUX(74, 5) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOPCTL_MUX(74, 0) /* PIO2_10 */ +#define SCT0_IN0_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN1_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN2_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN3_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN4_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN5_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN6_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SD0_RESET_N_PIO2_10 IOPCTL_MUX(74, 1) /* PIO2_10 */ +#define SMARTDMA_SMARTDMA_PIO10_PIO2_10 IOPCTL_MUX(74, 15) /* PIO2_10 */ +#define CTIMER2_MATCH1_PIO2_11 IOPCTL_MUX(75, 4) /* PIO2_11 */ +#define FC8_SSEL3_PIO2_11 IOPCTL_MUX(75, 5) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOPCTL_MUX(75, 0) /* PIO2_11 */ +#define SCT0_IN0_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN1_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN2_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN3_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN4_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN5_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN6_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SD0_VOLT_PIO2_11 IOPCTL_MUX(75, 1) /* PIO2_11 */ +#define SMARTDMA_SMARTDMA_PIO11_PIO2_11 IOPCTL_MUX(75, 15) /* PIO2_11 */ +#define ACMP0_ACMP_IN1_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define CTIMER0_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define FLEXIO0_TRIG1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define PIN_32KHZ_CLKOUT_PIO2_14 IOPCTL_MUX(78, 7) /* PIO2_14 */ +#define SCT0_OUT8_PIO2_14 IOPCTL_MUX(78, 2) /* PIO2_14 */ +#define SMARTDMA_SMARTDMA_PIO14_PIO2_14 IOPCTL_MUX(78, 15) /* PIO2_14 */ +#define ACMP0_ACMP_IN4_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define CLKIN_PIO2_15 IOPCTL_MUX(79, 7) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define SCT0_OUT9_PIO2_15 IOPCTL_MUX(79, 2) /* PIO2_15 */ +#define SMARTDMA_SMARTDMA_PIO15_PIO2_15 IOPCTL_MUX(79, 15) /* PIO2_15 */ +#define GPIO_INT_BMAT_PIO2_24 IOPCTL_MUX(88, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOPCTL_MUX(88, 0) /* PIO2_24 */ +#define SMARTDMA_SMARTDMA_PIO24_PIO2_24 IOPCTL_MUX(88, 15) /* PIO2_24 */ +#define SWO_PIO2_24 IOPCTL_MUX(88, 1) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOPCTL_MUX(89, 0) /* PIO2_25 */ +#define SMARTDMA_SMARTDMA_PIO25_PIO2_25 IOPCTL_MUX(89, 15) /* PIO2_25 */ +#define SWCLK_PIO2_25 IOPCTL_MUX(89, 1) /* PIO2_25 */ +#define GPIO_PIO226_PIO2_26 IOPCTL_MUX(90, 0) /* PIO2_26 */ +#define SMARTDMA_SMARTDMA_PIO26_PIO2_26 IOPCTL_MUX(90, 15) /* PIO2_26 */ +#define SWDIO_PIO2_26 IOPCTL_MUX(90, 1) /* PIO2_26 */ +#define GPIO_PIO227_PIO2_27 IOPCTL_MUX(91, 0) /* PIO2_27 */ +#define SMARTDMA_SMARTDMA_PIO27_PIO2_27 IOPCTL_MUX(91, 15) /* PIO2_27 */ +#define USB1_OVERCURRENTN_PIO2_27 IOPCTL_MUX(91, 1) /* PIO2_27 */ +#define GPIO_PIO228_PIO2_28 IOPCTL_MUX(92, 0) /* PIO2_28 */ +#define SMARTDMA_SMARTDMA_PIO28_PIO2_28 IOPCTL_MUX(92, 15) /* PIO2_28 */ +#define USB1_PORTPWRN_PIO2_28 IOPCTL_MUX(92, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOPCTL_MUX(93, 5) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOPCTL_MUX(93, 0) /* PIO2_29 */ +#define I3C0_SCL_PIO2_29 IOPCTL_MUX(93, 1) /* PIO2_29 */ +#define SCT0_OUT0_PIO2_29 IOPCTL_MUX(93, 2) /* PIO2_29 */ +#define SMARTDMA_SMARTDMA_PIO29_PIO2_29 IOPCTL_MUX(93, 15) /* PIO2_29 */ +#define CLKIN_PIO2_30 IOPCTL_MUX(94, 5) /* PIO2_30 */ +#define CMP0_OUT_PIO2_30 IOPCTL_MUX(94, 7) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOPCTL_MUX(94, 0) /* PIO2_30 */ +#define I3C0_SDA_PIO2_30 IOPCTL_MUX(94, 1) /* PIO2_30 */ +#define SCT0_OUT3_PIO2_30 IOPCTL_MUX(94, 2) /* PIO2_30 */ +#define SMARTDMA_SMARTDMA_PIO30_PIO2_30 IOPCTL_MUX(94, 15) /* PIO2_30 */ +#define ACMP0_ACMP_IN2_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define CTIMER0_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define GPIO_PIO231_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define I3C0_PUR_PIO2_31 IOPCTL_MUX(95, 1) /* PIO2_31 */ +#define SCT0_OUT7_PIO2_31 IOPCTL_MUX(95, 2) /* PIO2_31 */ +#define SMARTDMA_SMARTDMA_PIO31_PIO2_31 IOPCTL_MUX(95, 15) /* PIO2_31 */ +#define SWO_PIO2_31 IOPCTL_MUX(95, 5) /* PIO2_31 */ +#define UTICK0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 3) /* PIO2_31 */ +#define DMIC0_CLK23_PIO3_1 IOPCTL_MUX(97, 1) /* PIO3_1 */ +#define DMIC0_DATA23_PIO3_1 IOPCTL_MUX(97, 2) /* PIO3_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO3_1 IOPCTL_MUX(97, 5) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOPCTL_MUX(97, 0) /* PIO3_1 */ +#define I3C1_SCL_PIO3_1 IOPCTL_MUX(97, 6) /* PIO3_1 */ +#define DMIC0_CLK45_PIO3_2 IOPCTL_MUX(98, 1) /* PIO3_2 */ +#define DMIC0_DATA45_PIO3_2 IOPCTL_MUX(98, 2) /* PIO3_2 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO3_2 IOPCTL_MUX(98, 5) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOPCTL_MUX(98, 0) /* PIO3_2 */ +#define I3C1_SDA_PIO3_2 IOPCTL_MUX(98, 6) /* PIO3_2 */ +#define CMP0_OUT_PIO3_3 IOPCTL_MUX(99, 7) /* PIO3_3 */ +#define DMIC0_CLK67_PIO3_3 IOPCTL_MUX(99, 1) /* PIO3_3 */ +#define DMIC0_DATA67_PIO3_3 IOPCTL_MUX(99, 2) /* PIO3_3 */ +#define FC0_CTS_SDA_SSEL0_PIO3_3 IOPCTL_MUX(99, 5) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOPCTL_MUX(99, 0) /* PIO3_3 */ +#define I3C1_PUR_PIO3_3 IOPCTL_MUX(99, 6) /* PIO3_3 */ +#define LCDIF_lcdif_data23_PIO3_3 IOPCTL_MUX(99, 3) /* PIO3_3 */ +#define CTIMER0_MATCH0_PIO3_8 IOPCTL_MUX(104, 4) /* PIO3_8 */ +#define FC10_SCK_PIO3_8 IOPCTL_MUX(104, 6) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOPCTL_MUX(104, 0) /* PIO3_8 */ +#define LCDIF_lcdif_data9_PIO3_8 IOPCTL_MUX(104, 2) /* PIO3_8 */ +#define SD1_CLK_PIO3_8 IOPCTL_MUX(104, 1) /* PIO3_8 */ +#define CTIMER0_MATCH1_PIO3_9 IOPCTL_MUX(105, 4) /* PIO3_9 */ +#define FC10_TXD_SCL_MISO_PIO3_9 IOPCTL_MUX(105, 6) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOPCTL_MUX(105, 0) /* PIO3_9 */ +#define LCDIF_lcdif_data10_PIO3_9 IOPCTL_MUX(105, 2) /* PIO3_9 */ +#define SD1_CMD_PIO3_9 IOPCTL_MUX(105, 1) /* PIO3_9 */ +#define CTIMER0_MATCH2_PIO3_10 IOPCTL_MUX(106, 4) /* PIO3_10 */ +#define FC10_RXD_SDA_MOSI_PIO3_10 IOPCTL_MUX(106, 6) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOPCTL_MUX(106, 0) /* PIO3_10 */ +#define LCDIF_lcdif_data11_PIO3_10 IOPCTL_MUX(106, 2) /* PIO3_10 */ +#define USDHC1_USDHC_DATA0_PIO3_10 IOPCTL_MUX(106, 1) /* PIO3_10 */ +#define CTIMER0_MATCH3_PIO3_11 IOPCTL_MUX(107, 4) /* PIO3_11 */ +#define FC10_CTS_SDA_SSELN0_PIO3_11 IOPCTL_MUX(107, 6) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOPCTL_MUX(107, 0) /* PIO3_11 */ +#define LCDIF_lcdif_data12_PIO3_11 IOPCTL_MUX(107, 2) /* PIO3_11 */ +#define USDHC1_USDHC_DATA1_PIO3_11 IOPCTL_MUX(107, 1) /* PIO3_11 */ +#define CTIMER0_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER0_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER0_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER0_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define FC10_RTS_SCL_SSELN1_PIO3_12 IOPCTL_MUX(108, 6) /* PIO3_12 */ +#define FLEXIO0_TRIG0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOPCTL_MUX(108, 0) /* PIO3_12 */ +#define LCDIF_lcdif_data13_PIO3_12 IOPCTL_MUX(108, 2) /* PIO3_12 */ +#define USDHC1_USDHC_DATA2_PIO3_12 IOPCTL_MUX(108, 1) /* PIO3_12 */ +#define CTIMER0_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER0_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER0_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER0_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define FC10_SSELN2_PIO3_13 IOPCTL_MUX(109, 6) /* PIO3_13 */ +#define FLEXIO0_TRIG1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOPCTL_MUX(109, 0) /* PIO3_13 */ +#define LCDIF_lcdif_data14_PIO3_13 IOPCTL_MUX(109, 2) /* PIO3_13 */ +#define USDHC1_USDHC_DATA3_PIO3_13 IOPCTL_MUX(109, 1) /* PIO3_13 */ +#define ACMP0_ACMP_IN5_PIO3_14 IOPCTL_MUX(110, 0) /* PIO3_14 */ +#define CTIMER3_MATCH0_PIO3_14 IOPCTL_MUX(110, 4) /* PIO3_14 */ +#define FC10_SSELN3_PIO3_14 IOPCTL_MUX(110, 6) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOPCTL_MUX(110, 0) /* PIO3_14 */ +#define LCDIF_lcdif_data15_PIO3_14 IOPCTL_MUX(110, 2) /* PIO3_14 */ +#define SD1_DS_PIO3_14 IOPCTL_MUX(110, 5) /* PIO3_14 */ +#define SD1_WR_PRT_PIO3_14 IOPCTL_MUX(110, 1) /* PIO3_14 */ +#define CTIMER3_MATCH1_PIO3_15 IOPCTL_MUX(111, 4) /* PIO3_15 */ +#define FC5_SCK_PIO3_15 IOPCTL_MUX(111, 5) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOPCTL_MUX(111, 0) /* PIO3_15 */ +#define LCDIF_lcdif_data16_PIO3_15 IOPCTL_MUX(111, 2) /* PIO3_15 */ +#define USDHC1_USDHC_DATA4_PIO3_15 IOPCTL_MUX(111, 1) /* PIO3_15 */ +#define CTIMER3_MATCH2_PIO3_16 IOPCTL_MUX(112, 4) /* PIO3_16 */ +#define FC5_TXD_SCL_MISO_WS_PIO3_16 IOPCTL_MUX(112, 5) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOPCTL_MUX(112, 0) /* PIO3_16 */ +#define LCDIF_lcdif_data17_PIO3_16 IOPCTL_MUX(112, 2) /* PIO3_16 */ +#define USDHC1_USDHC_DATA5_PIO3_16 IOPCTL_MUX(112, 1) /* PIO3_16 */ +#define CTIMER3_MATCH3_PIO3_17 IOPCTL_MUX(113, 4) /* PIO3_17 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO3_17 IOPCTL_MUX(113, 5) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOPCTL_MUX(113, 0) /* PIO3_17 */ +#define LCDIF_lcdif_data18_PIO3_17 IOPCTL_MUX(113, 2) /* PIO3_17 */ +#define USDHC1_USDHC_DATA6_PIO3_17 IOPCTL_MUX(113, 1) /* PIO3_17 */ +#define CTIMER4_MATCH0_PIO3_18 IOPCTL_MUX(114, 4) /* PIO3_18 */ +#define FC5_CTS_SDA_SSEL0_PIO3_18 IOPCTL_MUX(114, 5) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOPCTL_MUX(114, 0) /* PIO3_18 */ +#define LCDIF_lcdif_data19_PIO3_18 IOPCTL_MUX(114, 2) /* PIO3_18 */ +#define USDHC1_USDHC_DATA7_PIO3_18 IOPCTL_MUX(114, 1) /* PIO3_18 */ +#define CTIMER4_MATCH1_PIO3_19 IOPCTL_MUX(115, 4) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOPCTL_MUX(115, 0) /* PIO3_19 */ +#define LCDIF_lcdif_data20_PIO3_19 IOPCTL_MUX(115, 2) /* PIO3_19 */ +#define MCLK_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN0_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN1_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN2_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN3_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN4_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN5_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN6_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SD1_CARD_DET_N_PIO3_19 IOPCTL_MUX(115, 1) /* PIO3_19 */ +#define CTIMER4_MATCH2_PIO3_20 IOPCTL_MUX(116, 4) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOPCTL_MUX(116, 0) /* PIO3_20 */ +#define LCDIF_lcdif_data21_PIO3_20 IOPCTL_MUX(116, 2) /* PIO3_20 */ +#define SD1_RESET_N_PIO3_20 IOPCTL_MUX(116, 1) /* PIO3_20 */ +#define CTIMER4_MATCH3_PIO3_21 IOPCTL_MUX(117, 4) /* PIO3_21 */ +#define GPIO_INT_BMAT_PIO3_21 IOPCTL_MUX(117, 6) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOPCTL_MUX(117, 0) /* PIO3_21 */ +#define LCDIF_lcdif_data22_PIO3_21 IOPCTL_MUX(117, 2) /* PIO3_21 */ +#define SD1_VOLT_PIO3_21 IOPCTL_MUX(117, 1) /* PIO3_21 */ +#define FC6_SCK_PIO3_25 IOPCTL_MUX(121, 1) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOPCTL_MUX(121, 0) /* PIO3_25 */ +#define FC6_TXD_SCL_MISO_WS_PIO3_26 IOPCTL_MUX(122, 1) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOPCTL_MUX(122, 0) /* PIO3_26 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO3_27 IOPCTL_MUX(123, 1) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOPCTL_MUX(123, 0) /* PIO3_27 */ +#define FC6_CTS_SDA_SSEL0_PIO3_28 IOPCTL_MUX(124, 1) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOPCTL_MUX(124, 0) /* PIO3_28 */ +#define FC6_RTS_SCL_SSEL1_PIO3_29 IOPCTL_MUX(125, 1) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOPCTL_MUX(125, 0) /* PIO3_29 */ +#define CLKOUT_PIO4_0 IOPCTL_MUX(128, 7) /* PIO4_0 */ +#define FC7_SCK_PIO4_0 IOPCTL_MUX(128, 1) /* PIO4_0 */ +#define FREQME_IN0_PIO4_0 IOPCTL_MUX(128, 4) /* PIO4_0 */ +#define FREQME_IN1_PIO4_0 IOPCTL_MUX(128, 4) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOPCTL_MUX(128, 0) /* PIO4_0 */ +#define CLKIN_PIO4_1 IOPCTL_MUX(129, 7) /* PIO4_1 */ +#define FC7_TXD_SCL_MISO_WS_PIO4_1 IOPCTL_MUX(129, 1) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOPCTL_MUX(129, 0) /* PIO4_1 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO4_2 IOPCTL_MUX(130, 1) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOPCTL_MUX(130, 0) /* PIO4_2 */ +#define FC7_CTS_SDA_SSEL0_PIO4_3 IOPCTL_MUX(131, 1) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOPCTL_MUX(131, 0) /* PIO4_3 */ +#define FC1_SCK_PIO4_4 IOPCTL_MUX(132, 5) /* PIO4_4 */ +#define FC7_RTS_SCL_SSEL1_PIO4_4 IOPCTL_MUX(132, 1) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOPCTL_MUX(132, 0) /* PIO4_4 */ +#define FC1_TXD_SCL_MISO_WS_PIO4_5 IOPCTL_MUX(133, 5) /* PIO4_5 */ +#define FC7_SSEL2_PIO4_5 IOPCTL_MUX(133, 1) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOPCTL_MUX(133, 0) /* PIO4_5 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO4_6 IOPCTL_MUX(134, 5) /* PIO4_6 */ +#define FC7_SSEL3_PIO4_6 IOPCTL_MUX(134, 1) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOPCTL_MUX(134, 0) /* PIO4_6 */ +#define FC2_SCK_PIO4_11 IOPCTL_MUX(139, 1) /* PIO4_11 */ +#define FLEXSPI1_SCLK_PIO4_11 IOPCTL_MUX(139, 2) /* PIO4_11 */ +#define GPIO_PIO411_PIO4_11 IOPCTL_MUX(139, 0) /* PIO4_11 */ +#define SD1_CLK_PIO4_11 IOPCTL_MUX(139, 4) /* PIO4_11 */ +#define FC2_TXD_SCL_MISO_WS_PIO4_12 IOPCTL_MUX(140, 1) /* PIO4_12 */ +#define FLEXSPI1_DATA0_PIO4_12 IOPCTL_MUX(140, 2) /* PIO4_12 */ +#define GPIO_PIO412_PIO4_12 IOPCTL_MUX(140, 0) /* PIO4_12 */ +#define SD1_CMD_PIO4_12 IOPCTL_MUX(140, 4) /* PIO4_12 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO4_13 IOPCTL_MUX(141, 1) /* PIO4_13 */ +#define FLEXSPI1_DATA1_PIO4_13 IOPCTL_MUX(141, 2) /* PIO4_13 */ +#define GPIO_PIO413_PIO4_13 IOPCTL_MUX(141, 0) /* PIO4_13 */ +#define USDHC1_USDHC_DATA0_PIO4_13 IOPCTL_MUX(141, 4) /* PIO4_13 */ +#define FC2_CTS_SDA_SSEL0_PIO4_14 IOPCTL_MUX(142, 1) /* PIO4_14 */ +#define FLEXSPI1_DATA2_PIO4_14 IOPCTL_MUX(142, 2) /* PIO4_14 */ +#define GPIO_PIO414_PIO4_14 IOPCTL_MUX(142, 0) /* PIO4_14 */ +#define USDHC1_USDHC_DATA1_PIO4_14 IOPCTL_MUX(142, 4) /* PIO4_14 */ +#define FC2_RTS_SCL_SSEL1_PIO4_15 IOPCTL_MUX(143, 1) /* PIO4_15 */ +#define FLEXSPI1_DATA3_PIO4_15 IOPCTL_MUX(143, 2) /* PIO4_15 */ +#define GPIO_PIO415_PIO4_15 IOPCTL_MUX(143, 0) /* PIO4_15 */ +#define USDHC1_USDHC_DATA2_PIO4_15 IOPCTL_MUX(143, 4) /* PIO4_15 */ +#define FC2_SSEL2_PIO4_16 IOPCTL_MUX(144, 1) /* PIO4_16 */ +#define FLEXSPI1_DQS_PIO4_16 IOPCTL_MUX(144, 2) /* PIO4_16 */ +#define GPIO_PIO416_PIO4_16 IOPCTL_MUX(144, 0) /* PIO4_16 */ +#define USDHC1_USDHC_DATA3_PIO4_16 IOPCTL_MUX(144, 4) /* PIO4_16 */ +#define FC2_SSEL3_PIO4_17 IOPCTL_MUX(145, 1) /* PIO4_17 */ +#define FLEXSPI1_SCLK_N_PIO4_17 IOPCTL_MUX(145, 3) /* PIO4_17 */ +#define FLEXSPI1_SS1_N_PIO4_17 IOPCTL_MUX(145, 2) /* PIO4_17 */ +#define GPIO_PIO417_PIO4_17 IOPCTL_MUX(145, 0) /* PIO4_17 */ +#define SD1_WR_PRT_PIO4_17 IOPCTL_MUX(145, 4) /* PIO4_17 */ +#define ADC0_CH6_PIO4_18 IOPCTL_MUX(146, 0) /* PIO4_18 */ +#define FLEXSPI1_SS0_N_PIO4_18 IOPCTL_MUX(146, 2) /* PIO4_18 */ +#define GPIO_PIO418_PIO4_18 IOPCTL_MUX(146, 0) /* PIO4_18 */ +#define USDHC1_USDHC_DATA4_PIO4_18 IOPCTL_MUX(146, 4) /* PIO4_18 */ +#define DBI_CSX_PIO4_20 IOPCTL_MUX(148, 1) /* PIO4_20 */ +#define FC11_SCK_PIO4_20 IOPCTL_MUX(148, 6) /* PIO4_20 */ +#define FLEXIO0_IO0_PIO4_20 IOPCTL_MUX(148, 8) /* PIO4_20 */ +#define GPIO_PIO420_PIO4_20 IOPCTL_MUX(148, 0) /* PIO4_20 */ +#define USDHC1_USDHC_DATA6_PIO4_20 IOPCTL_MUX(148, 4) /* PIO4_20 */ +#define DBI_DSX_PIO4_21 IOPCTL_MUX(149, 1) /* PIO4_21 */ +#define FC11_TXD_SCL_MISO_PIO4_21 IOPCTL_MUX(149, 6) /* PIO4_21 */ +#define FLEXIO0_IO1_PIO4_21 IOPCTL_MUX(149, 8) /* PIO4_21 */ +#define GPIO_PIO421_PIO4_21 IOPCTL_MUX(149, 0) /* PIO4_21 */ +#define USDHC1_USDHC_DATA7_PIO4_21 IOPCTL_MUX(149, 4) /* PIO4_21 */ +#define FC11_RXD_SDA_MOSI_PIO4_22 IOPCTL_MUX(150, 6) /* PIO4_22 */ +#define FLEXIO0_IO2_PIO4_22 IOPCTL_MUX(150, 8) /* PIO4_22 */ +#define GPIO_PIO422_PIO4_22 IOPCTL_MUX(150, 0) /* PIO4_22 */ +#define SD1_CARD_DET_N_PIO4_22 IOPCTL_MUX(150, 4) /* PIO4_22 */ +#define DBI_RWDX_PIO4_23 IOPCTL_MUX(151, 1) /* PIO4_23 */ +#define FC11_CTS_SDA_SSELN0_PIO4_23 IOPCTL_MUX(151, 6) /* PIO4_23 */ +#define FLEXIO0_IO3_PIO4_23 IOPCTL_MUX(151, 8) /* PIO4_23 */ +#define GPIO_PIO423_PIO4_23 IOPCTL_MUX(151, 0) /* PIO4_23 */ +#define LCD_ENABLE_PIO4_23 IOPCTL_MUX(151, 2) /* PIO4_23 */ +#define SD1_RESET_N_PIO4_23 IOPCTL_MUX(151, 4) /* PIO4_23 */ +#define TRACECLK_PIO4_23 IOPCTL_MUX(151, 7) /* PIO4_23 */ +#define DBI_WRX_PIO4_24 IOPCTL_MUX(152, 1) /* PIO4_24 */ +#define FC11_RTS_SCL_SSELN1_PIO4_24 IOPCTL_MUX(152, 6) /* PIO4_24 */ +#define FLEXIO0_IO4_PIO4_24 IOPCTL_MUX(152, 8) /* PIO4_24 */ +#define GPIO_PIO424_PIO4_24 IOPCTL_MUX(152, 0) /* PIO4_24 */ +#define LCD_DTCLK_PIO4_24 IOPCTL_MUX(152, 2) /* PIO4_24 */ +#define SD1_VOLT_PIO4_24 IOPCTL_MUX(152, 4) /* PIO4_24 */ +#define SWD_TRACEDATA0_PIO4_24 IOPCTL_MUX(152, 7) /* PIO4_24 */ +#define DBI_E_PIO4_25 IOPCTL_MUX(153, 1) /* PIO4_25 */ +#define FC11_SSELN2_PIO4_25 IOPCTL_MUX(153, 6) /* PIO4_25 */ +#define FLEXIO0_IO5_PIO4_25 IOPCTL_MUX(153, 8) /* PIO4_25 */ +#define GPIO_PIO425_PIO4_25 IOPCTL_MUX(153, 0) /* PIO4_25 */ +#define LCD_HSYNC_PIO4_25 IOPCTL_MUX(153, 2) /* PIO4_25 */ +#define SWD_TRACEDATA1_PIO4_25 IOPCTL_MUX(153, 7) /* PIO4_25 */ +#define FC11_SSELN3_PIO4_26 IOPCTL_MUX(154, 6) /* PIO4_26 */ +#define FLEXIO0_IO6_PIO4_26 IOPCTL_MUX(154, 8) /* PIO4_26 */ +#define GPIO_PIO426_PIO4_26 IOPCTL_MUX(154, 0) /* PIO4_26 */ +#define LCD_VSYNC_PIO4_26 IOPCTL_MUX(154, 1) /* PIO4_26 */ +#define SWD_TRACEDATA2_PIO4_26 IOPCTL_MUX(154, 7) /* PIO4_26 */ +#define FLEXIO0_IO7_PIO4_27 IOPCTL_MUX(155, 8) /* PIO4_27 */ +#define GPIO_PIO427_PIO4_27 IOPCTL_MUX(155, 0) /* PIO4_27 */ +#define LCDIF_dbi_data0_PIO4_27 IOPCTL_MUX(155, 2) /* PIO4_27 */ +#define LCDIF_lcdif_data0_PIO4_27 IOPCTL_MUX(155, 1) /* PIO4_27 */ +#define SWD_TRACEDATA3_PIO4_27 IOPCTL_MUX(155, 7) /* PIO4_27 */ +#define FLEXIO0_IO8_PIO4_28 IOPCTL_MUX(156, 8) /* PIO4_28 */ +#define GPIO_PIO428_PIO4_28 IOPCTL_MUX(156, 0) /* PIO4_28 */ +#define LCDIF_dbi_data1_PIO4_28 IOPCTL_MUX(156, 2) /* PIO4_28 */ +#define LCDIF_lcdif_data1_PIO4_28 IOPCTL_MUX(156, 1) /* PIO4_28 */ +#define FC12_SCK_PIO4_29 IOPCTL_MUX(157, 6) /* PIO4_29 */ +#define FLEXIO0_IO9_PIO4_29 IOPCTL_MUX(157, 8) /* PIO4_29 */ +#define GPIO_PIO429_PIO4_29 IOPCTL_MUX(157, 0) /* PIO4_29 */ +#define LCDIF_dbi_data2_PIO4_29 IOPCTL_MUX(157, 2) /* PIO4_29 */ +#define LCDIF_lcdif_data2_PIO4_29 IOPCTL_MUX(157, 1) /* PIO4_29 */ +#define FC12_TXD_SCL_MISO_PIO4_30 IOPCTL_MUX(158, 6) /* PIO4_30 */ +#define FLEXIO0_IO10_PIO4_30 IOPCTL_MUX(158, 8) /* PIO4_30 */ +#define GPIO_PIO430_PIO4_30 IOPCTL_MUX(158, 0) /* PIO4_30 */ +#define LCDIF_dbi_data3_PIO4_30 IOPCTL_MUX(158, 2) /* PIO4_30 */ +#define LCDIF_lcdif_data3_PIO4_30 IOPCTL_MUX(158, 1) /* PIO4_30 */ +#define FC12_RXD_SDA_MOSI_PIO4_31 IOPCTL_MUX(159, 6) /* PIO4_31 */ +#define FLEXIO0_IO11_PIO4_31 IOPCTL_MUX(159, 8) /* PIO4_31 */ +#define GPIO_PIO431_PIO4_31 IOPCTL_MUX(159, 0) /* PIO4_31 */ +#define LCDIF_dbi_data4_PIO4_31 IOPCTL_MUX(159, 2) /* PIO4_31 */ +#define LCDIF_lcdif_data4_PIO4_31 IOPCTL_MUX(159, 1) /* PIO4_31 */ +#define FC12_CTS_SDA_SSELN0_PIO5_0 IOPCTL_MUX(160, 6) /* PIO5_0 */ +#define FLEXIO0_IO12_PIO5_0 IOPCTL_MUX(160, 8) /* PIO5_0 */ +#define GPIO_PIO50_PIO5_0 IOPCTL_MUX(160, 0) /* PIO5_0 */ +#define LCDIF_dbi_data5_PIO5_0 IOPCTL_MUX(160, 2) /* PIO5_0 */ +#define LCDIF_lcdif_data5_PIO5_0 IOPCTL_MUX(160, 1) /* PIO5_0 */ +#define FC12_RTS_SCL_SSELN1_PIO5_1 IOPCTL_MUX(161, 6) /* PIO5_1 */ +#define FLEXIO0_IO13_PIO5_1 IOPCTL_MUX(161, 8) /* PIO5_1 */ +#define GPIO_PIO51_PIO5_1 IOPCTL_MUX(161, 0) /* PIO5_1 */ +#define LCDIF_dbi_data6_PIO5_1 IOPCTL_MUX(161, 2) /* PIO5_1 */ +#define LCDIF_lcdif_data6_PIO5_1 IOPCTL_MUX(161, 1) /* PIO5_1 */ +#define FC12_SSELN2_PIO5_2 IOPCTL_MUX(162, 6) /* PIO5_2 */ +#define FLEXIO0_IO14_PIO5_2 IOPCTL_MUX(162, 8) /* PIO5_2 */ +#define GPIO_PIO52_PIO5_2 IOPCTL_MUX(162, 0) /* PIO5_2 */ +#define LCDIF_dbi_data7_PIO5_2 IOPCTL_MUX(162, 2) /* PIO5_2 */ +#define LCDIF_lcdif_data7_PIO5_2 IOPCTL_MUX(162, 1) /* PIO5_2 */ +#define LOW_FREQ_CLKOUT_PIO5_2 IOPCTL_MUX(162, 7) /* PIO5_2 */ +#define FC12_SSELN3_PIO5_3 IOPCTL_MUX(163, 6) /* PIO5_3 */ +#define FLEXIO0_IO15_PIO5_3 IOPCTL_MUX(163, 8) /* PIO5_3 */ +#define GPIO_PIO53_PIO5_3 IOPCTL_MUX(163, 0) /* PIO5_3 */ +#define LCDIF_dbi_data8_PIO5_3 IOPCTL_MUX(163, 2) /* PIO5_3 */ +#define LCDIF_lcdif_data8_PIO5_3 IOPCTL_MUX(163, 1) /* PIO5_3 */ +#define LOW_FREQ_CLKOUT_N_PIO5_3 IOPCTL_MUX(163, 7) /* PIO5_3 */ +#define DMIC0_CLK01_PIO5_4 IOPCTL_MUX(164, 4) /* PIO5_4 */ +#define GPIO_PIO54_PIO5_4 IOPCTL_MUX(164, 0) /* PIO5_4 */ +#define LCDIF_dbi_data9_PIO5_4 IOPCTL_MUX(164, 2) /* PIO5_4 */ +#define LCDIF_lcdif_data9_PIO5_4 IOPCTL_MUX(164, 1) /* PIO5_4 */ +#define DMIC0_DATA01_PIO5_8 IOPCTL_MUX(168, 4) /* PIO5_8 */ +#define GPIO_PIO58_PIO5_8 IOPCTL_MUX(168, 0) /* PIO5_8 */ +#define LCDIF_dbi_data13_PIO5_8 IOPCTL_MUX(168, 2) /* PIO5_8 */ +#define LCDIF_lcdif_data13_PIO5_8 IOPCTL_MUX(168, 1) /* PIO5_8 */ +#define FC4_CTS_SDA_SSEL0_PIO5_15 IOPCTL_MUX(175, 4) /* PIO5_15 */ +#define FLEXSPI1_DATA4_PIO5_15 IOPCTL_MUX(175, 2) /* PIO5_15 */ +#define GPIO_PIO515_PIO5_15 IOPCTL_MUX(175, 0) /* PIO5_15 */ +#define LCDIF_lcdif_data20_PIO5_15 IOPCTL_MUX(175, 1) /* PIO5_15 */ +#define FC4_RTS_SCL_SSEL1_PIO5_16 IOPCTL_MUX(176, 4) /* PIO5_16 */ +#define FLEXSPI1_DATA5_PIO5_16 IOPCTL_MUX(176, 2) /* PIO5_16 */ +#define GPIO_PIO516_PIO5_16 IOPCTL_MUX(176, 0) /* PIO5_16 */ +#define LCDIF_lcdif_data21_PIO5_16 IOPCTL_MUX(176, 1) /* PIO5_16 */ +#define FC4_SSEL2_PIO5_17 IOPCTL_MUX(177, 4) /* PIO5_17 */ +#define FLEXSPI1_DATA6_PIO5_17 IOPCTL_MUX(177, 2) /* PIO5_17 */ +#define GPIO_PIO517_PIO5_17 IOPCTL_MUX(177, 0) /* PIO5_17 */ +#define LCDIF_lcdif_data22_PIO5_17 IOPCTL_MUX(177, 1) /* PIO5_17 */ +#define FC4_SSEL3_PIO5_18 IOPCTL_MUX(178, 4) /* PIO5_18 */ +#define FLEXSPI1_DATA7_PIO5_18 IOPCTL_MUX(178, 2) /* PIO5_18 */ +#define GPIO_PIO518_PIO5_18 IOPCTL_MUX(178, 0) /* PIO5_18 */ +#define LCDIF_lcdif_data23_PIO5_18 IOPCTL_MUX(178, 1) /* PIO5_18 */ + +#endif diff --git a/dts/nxp/nxp_imx/rt/MIMXRT633SFAWBR-pinctrl.h b/dts/nxp/nxp_imx/rt/MIMXRT633SFAWBR-pinctrl.h new file mode 100644 index 000000000..8c3f502eb --- /dev/null +++ b/dts/nxp/nxp_imx/rt/MIMXRT633SFAWBR-pinctrl.h @@ -0,0 +1,4290 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from MIMXRT633SFAWBR/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MIMXRT633SFAWBR_ +#define _ZEPHYR_DTS_BINDING_MIMXRT633SFAWBR_ + +#define IOPCTL_MUX(offset, mux) \ + ((((offset) & 0xFFF) << 20) | \ + (((mux) & 0xF) << 0)) + +#define CTIMER0_MATCH0_PIO0_0 IOPCTL_MUX(0, 4) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define FC0_SCK_PIO0_0 IOPCTL_MUX(0, 1) /* PIO0_0 */ +#define GPIO_INT_BMAT_PIO0_0 IOPCTL_MUX(0, 6) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define I2S_BRIDGE_CLK_IN_PIO0_0 IOPCTL_MUX(0, 5) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOPCTL_MUX(0, 8) /* PIO0_0 */ +#define CTIMER0_MATCH1_PIO0_1 IOPCTL_MUX(1, 4) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_1 IOPCTL_MUX(1, 1) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define I2S_BRIDGE_WS_IN_PIO0_1 IOPCTL_MUX(1, 5) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOPCTL_MUX(1, 8) /* PIO0_1 */ +#define CTIMER0_MATCH2_PIO0_2 IOPCTL_MUX(2, 4) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_2 IOPCTL_MUX(2, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define I2S_BRIDGE_DATA_IN_PIO0_2 IOPCTL_MUX(2, 5) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOPCTL_MUX(2, 8) /* PIO0_2 */ +#define CTIMER0_MATCH3_PIO0_3 IOPCTL_MUX(3, 4) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define FC0_CTS_SDA_SSEL0_PIO0_3 IOPCTL_MUX(3, 1) /* PIO0_3 */ +#define FC1_SSEL2_PIO0_3 IOPCTL_MUX(3, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOPCTL_MUX(3, 8) /* PIO0_3 */ +#define CMP0_OUT_PIO0_4 IOPCTL_MUX(4, 7) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define FC0_RTS_SCL_SSEL1_PIO0_4 IOPCTL_MUX(4, 1) /* PIO0_4 */ +#define FC1_SSEL3_PIO0_4 IOPCTL_MUX(4, 5) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOPCTL_MUX(4, 8) /* PIO0_4 */ +#define ADC0_CH0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define FC0_SSEL2_PIO0_5 IOPCTL_MUX(5, 1) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_OUT0_PIO0_5 IOPCTL_MUX(5, 3) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOPCTL_MUX(5, 8) /* PIO0_5 */ +#define ADC0_CH8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER0_MATCH0_PIO0_6 IOPCTL_MUX(6, 4) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define FC0_SSEL3_PIO0_6 IOPCTL_MUX(6, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_OUT1_PIO0_6 IOPCTL_MUX(6, 3) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOPCTL_MUX(6, 8) /* PIO0_6 */ +#define CTIMER1_MATCH0_PIO0_7 IOPCTL_MUX(7, 4) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOPCTL_MUX(7, 1) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_7 IOPCTL_MUX(7, 5) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SCT0_IN0_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN1_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN2_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN3_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN4_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN5_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN6_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_OUT4_PIO0_7 IOPCTL_MUX(7, 3) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOPCTL_MUX(7, 8) /* PIO0_7 */ +#define CTIMER1_MATCH1_PIO0_8 IOPCTL_MUX(8, 4) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_8 IOPCTL_MUX(8, 1) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define I2S_BRIDGE_WS_OUT_PIO0_8 IOPCTL_MUX(8, 5) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define SCT0_IN0_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN1_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN2_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN3_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN4_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN5_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN6_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_OUT5_PIO0_8 IOPCTL_MUX(8, 3) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOPCTL_MUX(8, 8) /* PIO0_8 */ +#define CTIMER1_MATCH2_PIO0_9 IOPCTL_MUX(9, 4) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_9 IOPCTL_MUX(9, 1) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_9 IOPCTL_MUX(9, 5) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define SCT0_IN0_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN1_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN2_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN3_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN4_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN5_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN6_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_OUT6_PIO0_9 IOPCTL_MUX(9, 3) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOPCTL_MUX(9, 8) /* PIO0_9 */ +#define CTIMER1_MATCH3_PIO0_10 IOPCTL_MUX(10, 4) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define FC0_SSEL2_PIO0_10 IOPCTL_MUX(10, 5) /* PIO0_10 */ +#define FC1_CTS_SDA_SSEL0_PIO0_10 IOPCTL_MUX(10, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define SCT0_IN0_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN1_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN2_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN3_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN4_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN5_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN6_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_OUT7_PIO0_10 IOPCTL_MUX(10, 3) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOPCTL_MUX(10, 8) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define FC0_SSEL3_PIO0_11 IOPCTL_MUX(11, 5) /* PIO0_11 */ +#define FC1_RTS_SCL_SSEL1_PIO0_11 IOPCTL_MUX(11, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define SCT0_IN0_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN1_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN2_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN3_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN4_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN5_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN6_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_OUT8_PIO0_11 IOPCTL_MUX(11, 3) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOPCTL_MUX(11, 8) /* PIO0_11 */ +#define ADC0_CH1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define FC1_SSEL2_PIO0_12 IOPCTL_MUX(12, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_OUT2_PIO0_12 IOPCTL_MUX(12, 3) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOPCTL_MUX(12, 8) /* PIO0_12 */ +#define ADC0_CH9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define CTIMER0_MATCH1_PIO0_13 IOPCTL_MUX(13, 4) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define FC1_SSEL3_PIO0_13 IOPCTL_MUX(13, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_OUT3_PIO0_13 IOPCTL_MUX(13, 3) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOPCTL_MUX(13, 8) /* PIO0_13 */ +#define CTIMER2_MATCH0_PIO0_14 IOPCTL_MUX(14, 4) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define FC2_SCK_PIO0_14 IOPCTL_MUX(14, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define I2S_BRIDGE_CLK_IN_PIO0_14 IOPCTL_MUX(14, 5) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_OUT0_PIO0_14 IOPCTL_MUX(14, 3) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOPCTL_MUX(14, 8) /* PIO0_14 */ +#define CTIMER2_MATCH1_PIO0_15 IOPCTL_MUX(15, 4) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_15 IOPCTL_MUX(15, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define I2S_BRIDGE_WS_IN_PIO0_15 IOPCTL_MUX(15, 5) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define SCT0_IN0_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN1_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN2_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN3_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN4_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN5_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN6_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_OUT1_PIO0_15 IOPCTL_MUX(15, 3) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOPCTL_MUX(15, 8) /* PIO0_15 */ +#define CTIMER2_MATCH2_PIO0_16 IOPCTL_MUX(16, 4) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_16 IOPCTL_MUX(16, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define I2S_BRIDGE_DATA_IN_PIO0_16 IOPCTL_MUX(16, 5) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define SCT0_IN0_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN1_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN2_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN3_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN4_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN5_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN6_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_OUT2_PIO0_16 IOPCTL_MUX(16, 3) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOPCTL_MUX(16, 8) /* PIO0_16 */ +#define ADC0_CH2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define FC2_SSEL2_PIO0_19 IOPCTL_MUX(19, 1) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define SCT0_IN0_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN1_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN2_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN3_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN4_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN5_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN6_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_OUT4_PIO0_19 IOPCTL_MUX(19, 3) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOPCTL_MUX(19, 8) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 5) /* PIO0_19 */ +#define ADC0_CH10_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_MATCH2_PIO0_20 IOPCTL_MUX(20, 4) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG30_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG31_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG32_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG0_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG1_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG20_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG21_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG22_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG23_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG24_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG25_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG26_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG27_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG28_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG29_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG2_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG30_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG31_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG32_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG3_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG4_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG5_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG6_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG7_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG8_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG9_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define FC2_SSEL3_PIO0_20 IOPCTL_MUX(20, 1) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_OUT5_PIO0_20 IOPCTL_MUX(20, 3) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOPCTL_MUX(20, 8) /* PIO0_20 */ +#define CTIMER3_MATCH0_PIO0_21 IOPCTL_MUX(21, 4) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define FC3_SCK_PIO0_21 IOPCTL_MUX(21, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOPCTL_MUX(21, 8) /* PIO0_21 */ +#define TRACECLK_PIO0_21 IOPCTL_MUX(21, 6) /* PIO0_21 */ +#define CTIMER3_MATCH1_PIO0_22 IOPCTL_MUX(22, 4) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_22 IOPCTL_MUX(22, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOPCTL_MUX(22, 8) /* PIO0_22 */ +#define SWD_TRACEDATA0_PIO0_22 IOPCTL_MUX(22, 6) /* PIO0_22 */ +#define CTIMER3_MATCH2_PIO0_23 IOPCTL_MUX(23, 4) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_23 IOPCTL_MUX(23, 1) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOPCTL_MUX(23, 8) /* PIO0_23 */ +#define SWD_TRACEDATA1_PIO0_23 IOPCTL_MUX(23, 6) /* PIO0_23 */ +#define CLKOUT_PIO0_24 IOPCTL_MUX(24, 7) /* PIO0_24 */ +#define CTIMER3_MATCH3_PIO0_24 IOPCTL_MUX(24, 4) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define FC2_SSEL2_PIO0_24 IOPCTL_MUX(24, 5) /* PIO0_24 */ +#define FC3_CTS_SDA_SSEL0_PIO0_24 IOPCTL_MUX(24, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOPCTL_MUX(24, 8) /* PIO0_24 */ +#define SWD_TRACEDATA2_PIO0_24 IOPCTL_MUX(24, 6) /* PIO0_24 */ +#define CLKIN_PIO0_25 IOPCTL_MUX(25, 7) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define FC2_SSEL3_PIO0_25 IOPCTL_MUX(25, 5) /* PIO0_25 */ +#define FC3_RTS_SCL_SSEL1_PIO0_25 IOPCTL_MUX(25, 1) /* PIO0_25 */ +#define FREQME_IN0_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define FREQME_IN1_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOPCTL_MUX(25, 8) /* PIO0_25 */ +#define SWD_TRACEDATA3_PIO0_25 IOPCTL_MUX(25, 6) /* PIO0_25 */ +#define ADC0_CH3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG30_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG31_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG32_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG0_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG1_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG20_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG21_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG22_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG23_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG24_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG25_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG26_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG27_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG28_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG29_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG2_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG30_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG31_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG32_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG4_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG5_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG6_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG7_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG8_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG9_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define FC3_SSEL2_PIO0_26 IOPCTL_MUX(26, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define SCT0_IN0_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN1_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN2_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN3_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN4_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN5_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN6_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_OUT6_PIO0_26 IOPCTL_MUX(26, 3) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOPCTL_MUX(26, 8) /* PIO0_26 */ +#define ADC0_CH11_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define CTIMER0_MATCH3_PIO0_27 IOPCTL_MUX(27, 4) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG30_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG31_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG32_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG0_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG1_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG20_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG21_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG22_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG23_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG24_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG25_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG26_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG27_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG28_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG29_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG2_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG30_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG31_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG32_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG3_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG4_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG5_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG6_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG7_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG8_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG9_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define FC3_SSEL3_PIO0_27 IOPCTL_MUX(27, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define SCT0_IN0_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN1_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN2_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN3_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN4_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN5_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN6_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_OUT7_PIO0_27 IOPCTL_MUX(27, 3) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOPCTL_MUX(27, 8) /* PIO0_27 */ +#define CTIMER4_MATCH1_PIO0_29 IOPCTL_MUX(29, 4) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_29 IOPCTL_MUX(29, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define I2S_BRIDGE_WS_OUT_PIO0_29 IOPCTL_MUX(29, 5) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOPCTL_MUX(29, 8) /* PIO0_29 */ +#define CTIMER4_MATCH2_PIO0_30 IOPCTL_MUX(30, 4) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_30 IOPCTL_MUX(30, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_30 IOPCTL_MUX(30, 5) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOPCTL_MUX(30, 8) /* PIO0_30 */ +#define CMP_IN3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define CTIMER1_MATCH1_PIO1_2 IOPCTL_MUX(34, 4) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG30_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG31_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG32_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG0_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG1_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG20_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG21_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG22_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG23_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG24_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG25_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG26_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG27_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG28_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG29_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG2_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG30_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG31_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG32_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG4_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG5_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG6_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG7_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG8_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG9_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define FC4_SSEL3_PIO1_2 IOPCTL_MUX(34, 1) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_OUT9_PIO1_2 IOPCTL_MUX(34, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define FC5_SCK_PIO1_3 IOPCTL_MUX(35, 1) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define FC5_TXD_SCL_MISO_WS_PIO1_4 IOPCTL_MUX(36, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO1_5 IOPCTL_MUX(37, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define ADC0_CH4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define CTIMER0_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER0_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER0_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER0_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_MATCH2_PIO1_8 IOPCTL_MUX(40, 4) /* PIO1_8 */ +#define CTIMER2_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER2_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER2_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER2_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG30_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG31_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG32_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG0_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG1_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG20_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG21_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG22_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG23_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG24_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG25_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG26_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG27_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG28_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG29_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG2_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG30_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG31_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG32_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG3_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG5_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG6_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG7_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG8_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG9_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define FC5_SSEL2_PIO1_8 IOPCTL_MUX(40, 1) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define SCT0_IN0_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN1_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN2_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN3_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN4_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN5_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN6_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define CTIMER1_MATCH3_PIO1_9 IOPCTL_MUX(41, 4) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG30_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG31_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG32_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG20_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG21_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG22_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG23_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG24_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG25_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG26_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG27_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG28_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG29_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG30_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG31_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG32_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG8_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG9_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define FC5_SSEL3_PIO1_9 IOPCTL_MUX(41, 1) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define SCT0_IN0_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN1_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN2_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN3_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN4_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN5_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN6_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define UTICK0_CAPTURE1_PIO1_9 IOPCTL_MUX(41, 3) /* PIO1_9 */ +#define CLKOUT_PIO1_10 IOPCTL_MUX(42, 7) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG30_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG31_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG32_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG20_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG21_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG22_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG23_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG24_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG25_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG26_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG27_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG28_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG29_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG30_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG31_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG32_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG8_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG9_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define FREQME_IN0_PIO1_10 IOPCTL_MUX(42, 3) /* PIO1_10 */ +#define FREQME_IN1_PIO1_10 IOPCTL_MUX(42, 3) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define MCLK_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define SCT0_IN0_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN1_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN2_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN3_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN4_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN5_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN6_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define CTIMER2_MATCH0_PIO1_11 IOPCTL_MUX(43, 4) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define FLEXSPI0B_DATA0_PIO1_11 IOPCTL_MUX(43, 6) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define HS_SPI_SCK_PIO1_11 IOPCTL_MUX(43, 1) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define CTIMER2_MATCH1_PIO1_12 IOPCTL_MUX(44, 4) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define FLEXSPI0B_DATA1_PIO1_12 IOPCTL_MUX(44, 6) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define HS_SPI_MISO_PIO1_12 IOPCTL_MUX(44, 1) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define CTIMER2_MATCH2_PIO1_13 IOPCTL_MUX(45, 4) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define FLEXSPI0B_DATA2_PIO1_13 IOPCTL_MUX(45, 6) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define HS_SPI_MOSI_PIO1_13 IOPCTL_MUX(45, 1) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define CTIMER2_MATCH3_PIO1_14 IOPCTL_MUX(46, 4) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define FLEXSPI0B_DATA3_PIO1_14 IOPCTL_MUX(46, 6) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define HS_SPI_SSEL0_PIO1_14 IOPCTL_MUX(46, 1) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define CTIMER3_MATCH0_PIO1_15 IOPCTL_MUX(47, 4) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define HS_SPI_SSEL1_PIO1_15 IOPCTL_MUX(47, 1) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define CTIMER3_MATCH1_PIO1_16 IOPCTL_MUX(48, 4) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG30_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG31_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG32_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG0_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG1_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG20_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG21_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG22_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG23_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG24_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG25_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG26_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG27_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG28_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG29_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG2_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG30_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG31_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG32_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG3_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG4_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG5_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG6_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG7_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG8_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG9_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define HS_SPI_SSEL2_PIO1_16 IOPCTL_MUX(48, 1) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define SCT0_OUT8_PIO1_16 IOPCTL_MUX(48, 2) /* PIO1_16 */ +#define CTIMER3_MATCH2_PIO1_17 IOPCTL_MUX(49, 4) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG30_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG31_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG32_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG0_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG1_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG20_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG21_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG22_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG23_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG24_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG25_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG26_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG27_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG28_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG29_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG2_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG30_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG31_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG32_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG3_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG4_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG5_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG6_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG7_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG8_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG9_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define HS_SPI_SSEL3_PIO1_17 IOPCTL_MUX(49, 1) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define SCT0_OUT9_PIO1_17 IOPCTL_MUX(49, 2) /* PIO1_17 */ +#define CTIMER3_MATCH3_PIO1_18 IOPCTL_MUX(50, 4) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define FLEXSPI0A_SCLK_PIO1_18 IOPCTL_MUX(50, 1) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define SCT0_IN0_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN1_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN2_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN3_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN4_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN5_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN6_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define CTIMER4_MATCH0_PIO1_19 IOPCTL_MUX(51, 4) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define FLEXSPI0A_SS0_N_PIO1_19 IOPCTL_MUX(51, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define SCT0_OUT0_PIO1_19 IOPCTL_MUX(51, 2) /* PIO1_19 */ +#define CTIMER4_MATCH1_PIO1_20 IOPCTL_MUX(52, 4) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define FLEXSPI0A_DATA0_PIO1_20 IOPCTL_MUX(52, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define SCT0_IN0_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN1_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN2_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN3_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN4_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN5_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN6_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define CTIMER4_MATCH2_PIO1_21 IOPCTL_MUX(53, 4) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define FLEXSPI0A_DATA1_PIO1_21 IOPCTL_MUX(53, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define SCT0_OUT1_PIO1_21 IOPCTL_MUX(53, 2) /* PIO1_21 */ +#define CTIMER4_MATCH3_PIO1_22 IOPCTL_MUX(54, 4) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define FLEXSPI0A_DATA2_PIO1_22 IOPCTL_MUX(54, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define CTIMER0_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define FLEXSPI0A_DATA3_PIO1_23 IOPCTL_MUX(55, 1) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define SCT0_OUT2_PIO1_23 IOPCTL_MUX(55, 2) /* PIO1_23 */ +#define CMP_IN1_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define CTIMER0_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define SCT0_OUT8_PIO2_14 IOPCTL_MUX(78, 2) /* PIO2_14 */ +#define CLKIN_PIO2_15 IOPCTL_MUX(79, 7) /* PIO2_15 */ +#define CMP_IN4_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define SCT0_OUT9_PIO2_15 IOPCTL_MUX(79, 2) /* PIO2_15 */ +#define DMIC0_CLK0_1_PIO2_16 IOPCTL_MUX(80, 1) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOPCTL_MUX(80, 0) /* PIO2_16 */ +#define DMIC0_CLK2_3_PIO2_17 IOPCTL_MUX(81, 1) /* PIO2_17 */ +#define FLEXSPI0B_DATA4_PIO2_17 IOPCTL_MUX(81, 6) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOPCTL_MUX(81, 0) /* PIO2_17 */ +#define DMIC0_CLK4_5_PIO2_18 IOPCTL_MUX(82, 1) /* PIO2_18 */ +#define FLEXSPI0B_DATA5_PIO2_18 IOPCTL_MUX(82, 6) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOPCTL_MUX(82, 0) /* PIO2_18 */ +#define DMIC0_CLK6_7_PIO2_19 IOPCTL_MUX(83, 1) /* PIO2_19 */ +#define FLEXSPI0B_SS0_N_PIO2_19 IOPCTL_MUX(83, 6) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOPCTL_MUX(83, 0) /* PIO2_19 */ +#define DMIC0_DATA0_1_PIO2_20 IOPCTL_MUX(84, 1) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOPCTL_MUX(84, 0) /* PIO2_20 */ +#define CTIMER0_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER0_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER0_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER0_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define DMIC0_DATA2_3_PIO2_21 IOPCTL_MUX(85, 1) /* PIO2_21 */ +#define FLEXSPI0B_SS1_N_PIO2_21 IOPCTL_MUX(85, 6) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOPCTL_MUX(85, 0) /* PIO2_21 */ +#define GPIO_PIO225_PIO2_25 IOPCTL_MUX(89, 0) /* PIO2_25 */ +#define SWCLK_PIO2_25 IOPCTL_MUX(89, 1) /* PIO2_25 */ +#define GPIO_PIO226_PIO2_26 IOPCTL_MUX(90, 0) /* PIO2_26 */ +#define SWDIO_PIO2_26 IOPCTL_MUX(90, 1) /* PIO2_26 */ +#define GPIO_PIO227_PIO2_27 IOPCTL_MUX(91, 0) /* PIO2_27 */ +#define USB1_OVERCURRENTN_PIO2_27 IOPCTL_MUX(91, 1) /* PIO2_27 */ +#define GPIO_PIO228_PIO2_28 IOPCTL_MUX(92, 0) /* PIO2_28 */ +#define USB1_PORTPWRN_PIO2_28 IOPCTL_MUX(92, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOPCTL_MUX(93, 5) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOPCTL_MUX(93, 0) /* PIO2_29 */ +#define I3C0_SCL_PIO2_29 IOPCTL_MUX(93, 1) /* PIO2_29 */ +#define SCT0_OUT0_PIO2_29 IOPCTL_MUX(93, 2) /* PIO2_29 */ +#define CLKIN_PIO2_30 IOPCTL_MUX(94, 5) /* PIO2_30 */ +#define CMP0_OUT_PIO2_30 IOPCTL_MUX(94, 7) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOPCTL_MUX(94, 0) /* PIO2_30 */ +#define I3C0_SDA_PIO2_30 IOPCTL_MUX(94, 1) /* PIO2_30 */ +#define SCT0_OUT3_PIO2_30 IOPCTL_MUX(94, 2) /* PIO2_30 */ +#define CMP_IN2_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define CTIMER0_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define GPIO_PIO231_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define I3C0_PUR_PIO2_31 IOPCTL_MUX(95, 1) /* PIO2_31 */ +#define SCT0_OUT7_PIO2_31 IOPCTL_MUX(95, 2) /* PIO2_31 */ +#define SWO_PIO2_31 IOPCTL_MUX(95, 5) /* PIO2_31 */ +#define UTICK0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 3) /* PIO2_31 */ +#define FC6_TXD_SCL_MISO_WS_PIO3_26 IOPCTL_MUX(122, 1) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOPCTL_MUX(122, 0) /* PIO3_26 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO3_27 IOPCTL_MUX(123, 1) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOPCTL_MUX(123, 0) /* PIO3_27 */ + +#endif diff --git a/dts/nxp/nxp_imx/rt/MIMXRT633SFFOB-pinctrl.h b/dts/nxp/nxp_imx/rt/MIMXRT633SFFOB-pinctrl.h new file mode 100644 index 000000000..acf938c3e --- /dev/null +++ b/dts/nxp/nxp_imx/rt/MIMXRT633SFFOB-pinctrl.h @@ -0,0 +1,5979 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from MIMXRT633SFFOB/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MIMXRT633SFFOB_ +#define _ZEPHYR_DTS_BINDING_MIMXRT633SFFOB_ + +#define IOPCTL_MUX(offset, mux) \ + ((((offset) & 0xFFF) << 20) | \ + (((mux) & 0xF) << 0)) + +#define CTIMER0_MATCH0_PIO0_0 IOPCTL_MUX(0, 4) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define FC0_SCK_PIO0_0 IOPCTL_MUX(0, 1) /* PIO0_0 */ +#define GPIO_INT_BMAT_PIO0_0 IOPCTL_MUX(0, 6) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define I2S_BRIDGE_CLK_IN_PIO0_0 IOPCTL_MUX(0, 5) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOPCTL_MUX(0, 8) /* PIO0_0 */ +#define PMIC_I2C_SCL IOPCTL_MUX(256, 0) /* PIO0_0 */ +#define PMIC_I2C_SDA IOPCTL_MUX(257, 0) /* PIO0_0 */ +#define CTIMER0_MATCH1_PIO0_1 IOPCTL_MUX(1, 4) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_1 IOPCTL_MUX(1, 1) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define I2S_BRIDGE_WS_IN_PIO0_1 IOPCTL_MUX(1, 5) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOPCTL_MUX(1, 8) /* PIO0_1 */ +#define CTIMER0_MATCH2_PIO0_2 IOPCTL_MUX(2, 4) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_2 IOPCTL_MUX(2, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define I2S_BRIDGE_DATA_IN_PIO0_2 IOPCTL_MUX(2, 5) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOPCTL_MUX(2, 8) /* PIO0_2 */ +#define CTIMER0_MATCH3_PIO0_3 IOPCTL_MUX(3, 4) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define FC0_CTS_SDA_SSEL0_PIO0_3 IOPCTL_MUX(3, 1) /* PIO0_3 */ +#define FC1_SSEL2_PIO0_3 IOPCTL_MUX(3, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOPCTL_MUX(3, 8) /* PIO0_3 */ +#define CMP0_OUT_PIO0_4 IOPCTL_MUX(4, 7) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define FC0_RTS_SCL_SSEL1_PIO0_4 IOPCTL_MUX(4, 1) /* PIO0_4 */ +#define FC1_SSEL3_PIO0_4 IOPCTL_MUX(4, 5) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOPCTL_MUX(4, 8) /* PIO0_4 */ +#define ADC0_CH0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define FC0_SSEL2_PIO0_5 IOPCTL_MUX(5, 1) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_OUT0_PIO0_5 IOPCTL_MUX(5, 3) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOPCTL_MUX(5, 8) /* PIO0_5 */ +#define ADC0_CH8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER0_MATCH0_PIO0_6 IOPCTL_MUX(6, 4) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define FC0_SSEL3_PIO0_6 IOPCTL_MUX(6, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_OUT1_PIO0_6 IOPCTL_MUX(6, 3) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOPCTL_MUX(6, 8) /* PIO0_6 */ +#define CTIMER1_MATCH0_PIO0_7 IOPCTL_MUX(7, 4) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOPCTL_MUX(7, 1) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_7 IOPCTL_MUX(7, 5) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SCT0_IN0_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN1_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN2_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN3_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN4_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN5_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN6_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_OUT4_PIO0_7 IOPCTL_MUX(7, 3) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOPCTL_MUX(7, 8) /* PIO0_7 */ +#define CTIMER1_MATCH1_PIO0_8 IOPCTL_MUX(8, 4) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_8 IOPCTL_MUX(8, 1) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define I2S_BRIDGE_WS_OUT_PIO0_8 IOPCTL_MUX(8, 5) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define SCT0_IN0_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN1_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN2_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN3_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN4_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN5_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN6_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_OUT5_PIO0_8 IOPCTL_MUX(8, 3) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOPCTL_MUX(8, 8) /* PIO0_8 */ +#define CTIMER1_MATCH2_PIO0_9 IOPCTL_MUX(9, 4) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_9 IOPCTL_MUX(9, 1) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_9 IOPCTL_MUX(9, 5) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define SCT0_IN0_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN1_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN2_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN3_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN4_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN5_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN6_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_OUT6_PIO0_9 IOPCTL_MUX(9, 3) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOPCTL_MUX(9, 8) /* PIO0_9 */ +#define CTIMER1_MATCH3_PIO0_10 IOPCTL_MUX(10, 4) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define FC0_SSEL2_PIO0_10 IOPCTL_MUX(10, 5) /* PIO0_10 */ +#define FC1_CTS_SDA_SSEL0_PIO0_10 IOPCTL_MUX(10, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define SCT0_IN0_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN1_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN2_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN3_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN4_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN5_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN6_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_OUT7_PIO0_10 IOPCTL_MUX(10, 3) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOPCTL_MUX(10, 8) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define FC0_SSEL3_PIO0_11 IOPCTL_MUX(11, 5) /* PIO0_11 */ +#define FC1_RTS_SCL_SSEL1_PIO0_11 IOPCTL_MUX(11, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define SCT0_IN0_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN1_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN2_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN3_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN4_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN5_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN6_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_OUT8_PIO0_11 IOPCTL_MUX(11, 3) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOPCTL_MUX(11, 8) /* PIO0_11 */ +#define ADC0_CH1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define FC1_SSEL2_PIO0_12 IOPCTL_MUX(12, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_OUT2_PIO0_12 IOPCTL_MUX(12, 3) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOPCTL_MUX(12, 8) /* PIO0_12 */ +#define ADC0_CH9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define CTIMER0_MATCH1_PIO0_13 IOPCTL_MUX(13, 4) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define FC1_SSEL3_PIO0_13 IOPCTL_MUX(13, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_OUT3_PIO0_13 IOPCTL_MUX(13, 3) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOPCTL_MUX(13, 8) /* PIO0_13 */ +#define CTIMER2_MATCH0_PIO0_14 IOPCTL_MUX(14, 4) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define FC2_SCK_PIO0_14 IOPCTL_MUX(14, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define I2S_BRIDGE_CLK_IN_PIO0_14 IOPCTL_MUX(14, 5) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_OUT0_PIO0_14 IOPCTL_MUX(14, 3) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOPCTL_MUX(14, 8) /* PIO0_14 */ +#define CTIMER2_MATCH1_PIO0_15 IOPCTL_MUX(15, 4) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_15 IOPCTL_MUX(15, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define I2S_BRIDGE_WS_IN_PIO0_15 IOPCTL_MUX(15, 5) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define SCT0_IN0_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN1_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN2_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN3_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN4_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN5_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN6_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_OUT1_PIO0_15 IOPCTL_MUX(15, 3) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOPCTL_MUX(15, 8) /* PIO0_15 */ +#define CTIMER2_MATCH2_PIO0_16 IOPCTL_MUX(16, 4) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_16 IOPCTL_MUX(16, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define I2S_BRIDGE_DATA_IN_PIO0_16 IOPCTL_MUX(16, 5) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define SCT0_IN0_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN1_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN2_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN3_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN4_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN5_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN6_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_OUT2_PIO0_16 IOPCTL_MUX(16, 3) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOPCTL_MUX(16, 8) /* PIO0_16 */ +#define CTIMER2_MATCH3_PIO0_17 IOPCTL_MUX(17, 4) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define FC2_CTS_SDA_SSEL0_PIO0_17 IOPCTL_MUX(17, 1) /* PIO0_17 */ +#define FC5_SSEL2_PIO0_17 IOPCTL_MUX(17, 5) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_OUT3_PIO0_17 IOPCTL_MUX(17, 3) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOPCTL_MUX(17, 8) /* PIO0_17 */ +#define CTIMER0_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define FC2_RTS_SCL_SSEL1_PIO0_18 IOPCTL_MUX(18, 1) /* PIO0_18 */ +#define FC5_SSEL3_PIO0_18 IOPCTL_MUX(18, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define SCT0_IN0_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN1_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN2_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN3_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN4_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN5_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN6_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_OUT6_PIO0_18 IOPCTL_MUX(18, 3) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOPCTL_MUX(18, 8) /* PIO0_18 */ +#define ADC0_CH2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define FC2_SSEL2_PIO0_19 IOPCTL_MUX(19, 1) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define SCT0_IN0_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN1_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN2_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN3_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN4_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN5_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN6_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_OUT4_PIO0_19 IOPCTL_MUX(19, 3) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOPCTL_MUX(19, 8) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 5) /* PIO0_19 */ +#define ADC0_CH10_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_MATCH2_PIO0_20 IOPCTL_MUX(20, 4) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG30_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG31_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG32_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG0_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG1_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG20_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG21_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG22_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG23_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG24_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG25_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG26_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG27_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG28_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG29_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG2_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG30_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG31_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG32_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG3_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG4_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG5_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG6_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG7_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG8_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG9_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define FC2_SSEL3_PIO0_20 IOPCTL_MUX(20, 1) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_OUT5_PIO0_20 IOPCTL_MUX(20, 3) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOPCTL_MUX(20, 8) /* PIO0_20 */ +#define CTIMER3_MATCH0_PIO0_21 IOPCTL_MUX(21, 4) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define FC3_SCK_PIO0_21 IOPCTL_MUX(21, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOPCTL_MUX(21, 8) /* PIO0_21 */ +#define TRACECLK_PIO0_21 IOPCTL_MUX(21, 6) /* PIO0_21 */ +#define CTIMER3_MATCH1_PIO0_22 IOPCTL_MUX(22, 4) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_22 IOPCTL_MUX(22, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOPCTL_MUX(22, 8) /* PIO0_22 */ +#define SWD_TRACEDATA0_PIO0_22 IOPCTL_MUX(22, 6) /* PIO0_22 */ +#define CTIMER3_MATCH2_PIO0_23 IOPCTL_MUX(23, 4) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_23 IOPCTL_MUX(23, 1) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOPCTL_MUX(23, 8) /* PIO0_23 */ +#define SWD_TRACEDATA1_PIO0_23 IOPCTL_MUX(23, 6) /* PIO0_23 */ +#define CLKOUT_PIO0_24 IOPCTL_MUX(24, 7) /* PIO0_24 */ +#define CTIMER3_MATCH3_PIO0_24 IOPCTL_MUX(24, 4) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define FC2_SSEL2_PIO0_24 IOPCTL_MUX(24, 5) /* PIO0_24 */ +#define FC3_CTS_SDA_SSEL0_PIO0_24 IOPCTL_MUX(24, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOPCTL_MUX(24, 8) /* PIO0_24 */ +#define SWD_TRACEDATA2_PIO0_24 IOPCTL_MUX(24, 6) /* PIO0_24 */ +#define CLKIN_PIO0_25 IOPCTL_MUX(25, 7) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define FC2_SSEL3_PIO0_25 IOPCTL_MUX(25, 5) /* PIO0_25 */ +#define FC3_RTS_SCL_SSEL1_PIO0_25 IOPCTL_MUX(25, 1) /* PIO0_25 */ +#define FREQME_IN0_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define FREQME_IN1_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOPCTL_MUX(25, 8) /* PIO0_25 */ +#define SWD_TRACEDATA3_PIO0_25 IOPCTL_MUX(25, 6) /* PIO0_25 */ +#define ADC0_CH3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG30_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG31_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG32_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG0_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG1_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG20_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG21_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG22_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG23_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG24_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG25_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG26_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG27_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG28_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG29_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG2_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG30_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG31_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG32_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG4_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG5_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG6_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG7_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG8_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG9_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define FC3_SSEL2_PIO0_26 IOPCTL_MUX(26, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define SCT0_IN0_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN1_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN2_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN3_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN4_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN5_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN6_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_OUT6_PIO0_26 IOPCTL_MUX(26, 3) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOPCTL_MUX(26, 8) /* PIO0_26 */ +#define ADC0_CH11_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define CTIMER0_MATCH3_PIO0_27 IOPCTL_MUX(27, 4) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG30_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG31_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG32_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG0_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG1_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG20_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG21_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG22_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG23_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG24_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG25_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG26_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG27_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG28_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG29_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG2_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG30_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG31_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG32_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG3_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG4_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG5_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG6_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG7_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG8_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG9_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define FC3_SSEL3_PIO0_27 IOPCTL_MUX(27, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define SCT0_IN0_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN1_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN2_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN3_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN4_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN5_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN6_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_OUT7_PIO0_27 IOPCTL_MUX(27, 3) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOPCTL_MUX(27, 8) /* PIO0_27 */ +#define CTIMER4_MATCH0_PIO0_28 IOPCTL_MUX(28, 4) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define FC4_SCK_PIO0_28 IOPCTL_MUX(28, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_28 IOPCTL_MUX(28, 5) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOPCTL_MUX(28, 8) /* PIO0_28 */ +#define CTIMER4_MATCH1_PIO0_29 IOPCTL_MUX(29, 4) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_29 IOPCTL_MUX(29, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define I2S_BRIDGE_WS_OUT_PIO0_29 IOPCTL_MUX(29, 5) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOPCTL_MUX(29, 8) /* PIO0_29 */ +#define CTIMER4_MATCH2_PIO0_30 IOPCTL_MUX(30, 4) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_30 IOPCTL_MUX(30, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_30 IOPCTL_MUX(30, 5) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOPCTL_MUX(30, 8) /* PIO0_30 */ +#define CTIMER4_MATCH3_PIO0_31 IOPCTL_MUX(31, 4) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define FC3_SSEL2_PIO0_31 IOPCTL_MUX(31, 5) /* PIO0_31 */ +#define FC4_CTS_SDA_SSEL0_PIO0_31 IOPCTL_MUX(31, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define SCT0_IN0_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN1_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN2_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN3_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN4_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN5_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN6_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_OUT6_PIO0_31 IOPCTL_MUX(31, 3) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOPCTL_MUX(31, 8) /* PIO0_31 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define FC3_SSEL3_PIO1_0 IOPCTL_MUX(32, 5) /* PIO1_0 */ +#define FC4_RTS_SCL_SSEL1_PIO1_0 IOPCTL_MUX(32, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_OUT7_PIO1_0 IOPCTL_MUX(32, 3) /* PIO1_0 */ +#define CTIMER1_MATCH0_PIO1_1 IOPCTL_MUX(33, 4) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG30_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG31_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG32_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG0_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG1_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG20_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG21_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG22_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG23_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG24_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG25_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG26_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG27_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG28_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG29_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG2_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG30_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG31_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG32_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG3_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG4_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG5_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG6_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG7_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG8_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG9_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define FC4_SSEL2_PIO1_1 IOPCTL_MUX(33, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_OUT8_PIO1_1 IOPCTL_MUX(33, 3) /* PIO1_1 */ +#define CMP_IN3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define CTIMER1_MATCH1_PIO1_2 IOPCTL_MUX(34, 4) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG30_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG31_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG32_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG0_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG1_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG20_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG21_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG22_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG23_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG24_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG25_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG26_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG27_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG28_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG29_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG2_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG30_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG31_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG32_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG4_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG5_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG6_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG7_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG8_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG9_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define FC4_SSEL3_PIO1_2 IOPCTL_MUX(34, 1) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_OUT9_PIO1_2 IOPCTL_MUX(34, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define FC5_SCK_PIO1_3 IOPCTL_MUX(35, 1) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define FC5_TXD_SCL_MISO_WS_PIO1_4 IOPCTL_MUX(36, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO1_5 IOPCTL_MUX(37, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define FC4_SSEL2_PIO1_6 IOPCTL_MUX(38, 5) /* PIO1_6 */ +#define FC5_CTS_SDA_SSEL0_PIO1_6 IOPCTL_MUX(38, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_OUT4_PIO1_6 IOPCTL_MUX(38, 3) /* PIO1_6 */ +#define CTIMER0_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define FC4_SSEL3_PIO1_7 IOPCTL_MUX(39, 5) /* PIO1_7 */ +#define FC5_RTS_SCL_SSEL1_PIO1_7 IOPCTL_MUX(39, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_OUT5_PIO1_7 IOPCTL_MUX(39, 3) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define CTIMER0_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER0_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER0_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER0_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_MATCH2_PIO1_8 IOPCTL_MUX(40, 4) /* PIO1_8 */ +#define CTIMER2_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER2_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER2_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER2_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG30_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG31_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG32_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG0_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG1_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG20_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG21_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG22_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG23_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG24_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG25_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG26_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG27_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG28_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG29_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG2_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG30_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG31_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG32_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG3_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG5_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG6_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG7_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG8_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG9_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define FC5_SSEL2_PIO1_8 IOPCTL_MUX(40, 1) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define SCT0_IN0_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN1_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN2_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN3_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN4_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN5_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN6_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define CTIMER1_MATCH3_PIO1_9 IOPCTL_MUX(41, 4) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG30_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG31_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG32_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG20_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG21_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG22_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG23_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG24_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG25_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG26_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG27_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG28_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG29_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG30_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG31_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG32_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG8_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG9_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define FC5_SSEL3_PIO1_9 IOPCTL_MUX(41, 1) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define SCT0_IN0_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN1_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN2_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN3_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN4_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN5_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN6_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define UTICK0_CAPTURE1_PIO1_9 IOPCTL_MUX(41, 3) /* PIO1_9 */ +#define CLKOUT_PIO1_10 IOPCTL_MUX(42, 7) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG30_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG31_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG32_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG20_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG21_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG22_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG23_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG24_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG25_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG26_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG27_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG28_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG29_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG30_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG31_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG32_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG8_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG9_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define FREQME_IN0_PIO1_10 IOPCTL_MUX(42, 3) /* PIO1_10 */ +#define FREQME_IN1_PIO1_10 IOPCTL_MUX(42, 3) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define MCLK_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define SCT0_IN0_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN1_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN2_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN3_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN4_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN5_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN6_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define CTIMER2_MATCH0_PIO1_11 IOPCTL_MUX(43, 4) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define FLEXSPI0B_DATA0_PIO1_11 IOPCTL_MUX(43, 6) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define HS_SPI_SCK_PIO1_11 IOPCTL_MUX(43, 1) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define CTIMER2_MATCH1_PIO1_12 IOPCTL_MUX(44, 4) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define FLEXSPI0B_DATA1_PIO1_12 IOPCTL_MUX(44, 6) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define HS_SPI_MISO_PIO1_12 IOPCTL_MUX(44, 1) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define CTIMER2_MATCH2_PIO1_13 IOPCTL_MUX(45, 4) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define FLEXSPI0B_DATA2_PIO1_13 IOPCTL_MUX(45, 6) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define HS_SPI_MOSI_PIO1_13 IOPCTL_MUX(45, 1) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define CTIMER2_MATCH3_PIO1_14 IOPCTL_MUX(46, 4) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define FLEXSPI0B_DATA3_PIO1_14 IOPCTL_MUX(46, 6) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define HS_SPI_SSEL0_PIO1_14 IOPCTL_MUX(46, 1) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define CTIMER3_MATCH0_PIO1_15 IOPCTL_MUX(47, 4) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define HS_SPI_SSEL1_PIO1_15 IOPCTL_MUX(47, 1) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define CTIMER3_MATCH1_PIO1_16 IOPCTL_MUX(48, 4) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG30_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG31_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG32_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG0_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG1_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG20_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG21_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG22_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG23_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG24_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG25_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG26_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG27_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG28_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG29_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG2_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG30_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG31_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG32_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG3_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG4_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG5_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG6_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG7_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG8_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG9_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define HS_SPI_SSEL2_PIO1_16 IOPCTL_MUX(48, 1) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define SCT0_OUT8_PIO1_16 IOPCTL_MUX(48, 2) /* PIO1_16 */ +#define CTIMER3_MATCH2_PIO1_17 IOPCTL_MUX(49, 4) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG30_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG31_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG32_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG0_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG1_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG20_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG21_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG22_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG23_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG24_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG25_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG26_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG27_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG28_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG29_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG2_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG30_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG31_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG32_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG3_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG4_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG5_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG6_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG7_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG8_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG9_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define HS_SPI_SSEL3_PIO1_17 IOPCTL_MUX(49, 1) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define SCT0_OUT9_PIO1_17 IOPCTL_MUX(49, 2) /* PIO1_17 */ +#define CTIMER3_MATCH3_PIO1_18 IOPCTL_MUX(50, 4) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define FLEXSPI0A_SCLK_PIO1_18 IOPCTL_MUX(50, 1) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define SCT0_IN0_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN1_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN2_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN3_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN4_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN5_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN6_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define CTIMER4_MATCH0_PIO1_19 IOPCTL_MUX(51, 4) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define FLEXSPI0A_SS0_N_PIO1_19 IOPCTL_MUX(51, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define SCT0_OUT0_PIO1_19 IOPCTL_MUX(51, 2) /* PIO1_19 */ +#define CTIMER4_MATCH1_PIO1_20 IOPCTL_MUX(52, 4) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define FLEXSPI0A_DATA0_PIO1_20 IOPCTL_MUX(52, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define SCT0_IN0_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN1_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN2_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN3_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN4_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN5_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN6_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define CTIMER4_MATCH2_PIO1_21 IOPCTL_MUX(53, 4) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define FLEXSPI0A_DATA1_PIO1_21 IOPCTL_MUX(53, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define SCT0_OUT1_PIO1_21 IOPCTL_MUX(53, 2) /* PIO1_21 */ +#define CTIMER4_MATCH3_PIO1_22 IOPCTL_MUX(54, 4) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define FLEXSPI0A_DATA2_PIO1_22 IOPCTL_MUX(54, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define CTIMER0_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define FLEXSPI0A_DATA3_PIO1_23 IOPCTL_MUX(55, 1) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define SCT0_OUT2_PIO1_23 IOPCTL_MUX(55, 2) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG30_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG31_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG32_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG20_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG21_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG22_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG23_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG24_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG25_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG26_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG27_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG28_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG29_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG30_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG31_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG32_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG8_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG9_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define FLEXSPI0A_DATA4_PIO1_24 IOPCTL_MUX(56, 1) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define SCT0_IN0_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN1_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN2_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN3_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN4_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN5_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN6_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG30_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG31_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG32_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG20_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG21_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG22_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG23_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG24_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG25_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG26_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG27_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG28_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG29_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG30_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG31_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG32_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG8_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG9_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define FLEXSPI0A_DATA5_PIO1_25 IOPCTL_MUX(57, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define SCT0_OUT3_PIO1_25 IOPCTL_MUX(57, 2) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG30_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG31_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG32_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG20_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG21_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG22_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG23_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG24_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG25_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG26_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG27_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG28_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG29_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG30_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG31_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG32_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG8_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG9_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define FLEXSPI0A_DATA6_PIO1_26 IOPCTL_MUX(58, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define SCT0_IN0_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN1_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN2_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN3_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN4_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN5_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN6_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG30_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG31_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG32_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG20_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG21_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG22_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG23_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG24_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG25_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG26_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG27_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG28_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG29_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG30_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG31_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG32_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG8_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG9_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define FLEXSPI0A_DATA7_PIO1_27 IOPCTL_MUX(59, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define SCT0_OUT4_PIO1_27 IOPCTL_MUX(59, 2) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define FLEXSPI0A_DQS_PIO1_28 IOPCTL_MUX(60, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define SCT0_IN0_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN1_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN2_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN3_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN4_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN5_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN6_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define CTIMER0_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG30_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG31_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG32_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG20_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG21_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG22_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG23_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG24_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG25_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG26_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG27_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG28_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG29_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG30_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG31_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG32_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG8_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG9_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define FLEXSPI0A_SS1_N_PIO1_29 IOPCTL_MUX(61, 1) /* PIO1_29 */ +#define FLEXSPI0B_SCLK_PIO1_29 IOPCTL_MUX(61, 5) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define SCT0_OUT5_PIO1_29 IOPCTL_MUX(61, 2) /* PIO1_29 */ +#define UTICK0_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 3) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG30_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG31_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG32_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG20_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG21_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG22_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG23_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG24_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG25_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG26_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG27_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG28_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG29_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG30_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG31_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG32_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG8_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG9_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SD0_CLK_PIO1_30 IOPCTL_MUX(62, 1) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG30_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG31_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG32_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG20_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG21_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG22_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG23_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG24_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG25_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG26_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG27_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG28_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG29_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG30_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG31_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG32_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG8_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG9_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define SCT0_IN0_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN1_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN2_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN3_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN4_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN5_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN6_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SD0_CMD_PIO1_31 IOPCTL_MUX(63, 1) /* PIO1_31 */ +#define GPIO_PIO20_PIO2_0 IOPCTL_MUX(64, 0) /* PIO2_0 */ +#define SCT0_IN0_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN1_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN2_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN3_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN4_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN5_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN6_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define USDHC0_USDHC_DATA0_PIO2_0 IOPCTL_MUX(64, 1) /* PIO2_0 */ +#define GPIO_PIO21_PIO2_1 IOPCTL_MUX(65, 0) /* PIO2_1 */ +#define SCT0_IN0_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN1_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN2_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN3_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN4_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN5_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN6_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define USDHC0_USDHC_DATA1_PIO2_1 IOPCTL_MUX(65, 1) /* PIO2_1 */ +#define GPIO_PIO22_PIO2_2 IOPCTL_MUX(66, 0) /* PIO2_2 */ +#define SCT0_OUT0_PIO2_2 IOPCTL_MUX(66, 2) /* PIO2_2 */ +#define USDHC0_USDHC_DATA2_PIO2_2 IOPCTL_MUX(66, 1) /* PIO2_2 */ +#define GPIO_PIO23_PIO2_3 IOPCTL_MUX(67, 0) /* PIO2_3 */ +#define SCT0_OUT1_PIO2_3 IOPCTL_MUX(67, 2) /* PIO2_3 */ +#define USDHC0_USDHC_DATA3_PIO2_3 IOPCTL_MUX(67, 1) /* PIO2_3 */ +#define GPIO_PIO24_PIO2_4 IOPCTL_MUX(68, 0) /* PIO2_4 */ +#define SCT0_OUT2_PIO2_4 IOPCTL_MUX(68, 2) /* PIO2_4 */ +#define SD0_DS_PIO2_4 IOPCTL_MUX(68, 5) /* PIO2_4 */ +#define SD0_WR_PRT_PIO2_4 IOPCTL_MUX(68, 1) /* PIO2_4 */ +#define GPIO_PIO25_PIO2_5 IOPCTL_MUX(69, 0) /* PIO2_5 */ +#define SCT0_OUT3_PIO2_5 IOPCTL_MUX(69, 2) /* PIO2_5 */ +#define USDHC0_USDHC_DATA4_PIO2_5 IOPCTL_MUX(69, 1) /* PIO2_5 */ +#define CTIMER1_MATCH0_PIO2_6 IOPCTL_MUX(70, 4) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOPCTL_MUX(70, 0) /* PIO2_6 */ +#define SCT0_IN0_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN1_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN2_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN3_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN4_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN5_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN6_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define USDHC0_USDHC_DATA5_PIO2_6 IOPCTL_MUX(70, 1) /* PIO2_6 */ +#define CTIMER1_MATCH1_PIO2_7 IOPCTL_MUX(71, 4) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOPCTL_MUX(71, 0) /* PIO2_7 */ +#define SCT0_IN0_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN1_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN2_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN3_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN4_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN5_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN6_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define USDHC0_USDHC_DATA6_PIO2_7 IOPCTL_MUX(71, 1) /* PIO2_7 */ +#define CTIMER1_MATCH2_PIO2_8 IOPCTL_MUX(72, 4) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOPCTL_MUX(72, 0) /* PIO2_8 */ +#define SCT0_OUT4_PIO2_8 IOPCTL_MUX(72, 2) /* PIO2_8 */ +#define USDHC0_USDHC_DATA7_PIO2_8 IOPCTL_MUX(72, 1) /* PIO2_8 */ +#define CTIMER1_MATCH3_PIO2_9 IOPCTL_MUX(73, 4) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOPCTL_MUX(73, 0) /* PIO2_9 */ +#define SCT0_OUT5_PIO2_9 IOPCTL_MUX(73, 2) /* PIO2_9 */ +#define SD0_CARD_DET_N_PIO2_9 IOPCTL_MUX(73, 1) /* PIO2_9 */ +#define CTIMER2_MATCH0_PIO2_10 IOPCTL_MUX(74, 4) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOPCTL_MUX(74, 0) /* PIO2_10 */ +#define SCT0_IN0_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN1_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN2_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN3_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN4_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN5_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN6_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SD0_RESET_N_PIO2_10 IOPCTL_MUX(74, 1) /* PIO2_10 */ +#define CTIMER2_MATCH1_PIO2_11 IOPCTL_MUX(75, 4) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOPCTL_MUX(75, 0) /* PIO2_11 */ +#define SCT0_IN0_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN1_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN2_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN3_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN4_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN5_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN6_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SD0_VOLT_PIO2_11 IOPCTL_MUX(75, 1) /* PIO2_11 */ +#define CTIMER2_MATCH2_PIO2_12 IOPCTL_MUX(76, 4) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOPCTL_MUX(76, 0) /* PIO2_12 */ +#define SCT0_OUT6_PIO2_12 IOPCTL_MUX(76, 2) /* PIO2_12 */ +#define CMP0_OUT_PIO2_13 IOPCTL_MUX(77, 7) /* PIO2_13 */ +#define CTIMER2_MATCH3_PIO2_13 IOPCTL_MUX(77, 4) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOPCTL_MUX(77, 0) /* PIO2_13 */ +#define SCT0_OUT7_PIO2_13 IOPCTL_MUX(77, 2) /* PIO2_13 */ +#define CMP_IN1_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define CTIMER0_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define SCT0_OUT8_PIO2_14 IOPCTL_MUX(78, 2) /* PIO2_14 */ +#define CLKIN_PIO2_15 IOPCTL_MUX(79, 7) /* PIO2_15 */ +#define CMP_IN4_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define SCT0_OUT9_PIO2_15 IOPCTL_MUX(79, 2) /* PIO2_15 */ +#define DMIC0_CLK0_1_PIO2_16 IOPCTL_MUX(80, 1) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOPCTL_MUX(80, 0) /* PIO2_16 */ +#define DMIC0_CLK2_3_PIO2_17 IOPCTL_MUX(81, 1) /* PIO2_17 */ +#define FLEXSPI0B_DATA4_PIO2_17 IOPCTL_MUX(81, 6) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOPCTL_MUX(81, 0) /* PIO2_17 */ +#define DMIC0_CLK4_5_PIO2_18 IOPCTL_MUX(82, 1) /* PIO2_18 */ +#define FLEXSPI0B_DATA5_PIO2_18 IOPCTL_MUX(82, 6) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOPCTL_MUX(82, 0) /* PIO2_18 */ +#define DMIC0_CLK6_7_PIO2_19 IOPCTL_MUX(83, 1) /* PIO2_19 */ +#define FLEXSPI0B_SS0_N_PIO2_19 IOPCTL_MUX(83, 6) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOPCTL_MUX(83, 0) /* PIO2_19 */ +#define DMIC0_DATA0_1_PIO2_20 IOPCTL_MUX(84, 1) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOPCTL_MUX(84, 0) /* PIO2_20 */ +#define CTIMER0_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER0_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER0_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER0_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define DMIC0_DATA2_3_PIO2_21 IOPCTL_MUX(85, 1) /* PIO2_21 */ +#define FLEXSPI0B_SS1_N_PIO2_21 IOPCTL_MUX(85, 6) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOPCTL_MUX(85, 0) /* PIO2_21 */ +#define DMIC0_DATA4_5_PIO2_22 IOPCTL_MUX(86, 1) /* PIO2_22 */ +#define FLEXSPI0B_DATA6_PIO2_22 IOPCTL_MUX(86, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOPCTL_MUX(86, 0) /* PIO2_22 */ +#define DMIC0_DATA6_7_PIO2_23 IOPCTL_MUX(87, 1) /* PIO2_23 */ +#define FLEXSPI0B_DATA7_PIO2_23 IOPCTL_MUX(87, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOPCTL_MUX(87, 0) /* PIO2_23 */ +#define GPIO_INT_BMAT_PIO2_24 IOPCTL_MUX(88, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOPCTL_MUX(88, 0) /* PIO2_24 */ +#define SWO_PIO2_24 IOPCTL_MUX(88, 1) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOPCTL_MUX(89, 0) /* PIO2_25 */ +#define SWCLK_PIO2_25 IOPCTL_MUX(89, 1) /* PIO2_25 */ +#define GPIO_PIO226_PIO2_26 IOPCTL_MUX(90, 0) /* PIO2_26 */ +#define SWDIO_PIO2_26 IOPCTL_MUX(90, 1) /* PIO2_26 */ +#define GPIO_PIO227_PIO2_27 IOPCTL_MUX(91, 0) /* PIO2_27 */ +#define USB1_OVERCURRENTN_PIO2_27 IOPCTL_MUX(91, 1) /* PIO2_27 */ +#define GPIO_PIO228_PIO2_28 IOPCTL_MUX(92, 0) /* PIO2_28 */ +#define USB1_PORTPWRN_PIO2_28 IOPCTL_MUX(92, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOPCTL_MUX(93, 5) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOPCTL_MUX(93, 0) /* PIO2_29 */ +#define I3C0_SCL_PIO2_29 IOPCTL_MUX(93, 1) /* PIO2_29 */ +#define SCT0_OUT0_PIO2_29 IOPCTL_MUX(93, 2) /* PIO2_29 */ +#define CLKIN_PIO2_30 IOPCTL_MUX(94, 5) /* PIO2_30 */ +#define CMP0_OUT_PIO2_30 IOPCTL_MUX(94, 7) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOPCTL_MUX(94, 0) /* PIO2_30 */ +#define I3C0_SDA_PIO2_30 IOPCTL_MUX(94, 1) /* PIO2_30 */ +#define SCT0_OUT3_PIO2_30 IOPCTL_MUX(94, 2) /* PIO2_30 */ +#define CMP_IN2_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define CTIMER0_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define GPIO_PIO231_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define I3C0_PUR_PIO2_31 IOPCTL_MUX(95, 1) /* PIO2_31 */ +#define SCT0_OUT7_PIO2_31 IOPCTL_MUX(95, 2) /* PIO2_31 */ +#define SWO_PIO2_31 IOPCTL_MUX(95, 5) /* PIO2_31 */ +#define UTICK0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 3) /* PIO2_31 */ +#define DMIC0_CLK0_1_PIO3_0 IOPCTL_MUX(96, 1) /* PIO3_0 */ +#define FC0_SCK_PIO3_0 IOPCTL_MUX(96, 5) /* PIO3_0 */ +#define GPIO_PIO30_PIO3_0 IOPCTL_MUX(96, 0) /* PIO3_0 */ +#define DMIC0_CLK2_3_PIO3_1 IOPCTL_MUX(97, 1) /* PIO3_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO3_1 IOPCTL_MUX(97, 5) /* PIO3_1 */ +#define GPIO_PIO31_PIO3_1 IOPCTL_MUX(97, 0) /* PIO3_1 */ +#define DMIC0_CLK4_5_PIO3_2 IOPCTL_MUX(98, 1) /* PIO3_2 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO3_2 IOPCTL_MUX(98, 5) /* PIO3_2 */ +#define GPIO_PIO32_PIO3_2 IOPCTL_MUX(98, 0) /* PIO3_2 */ +#define CMP0_OUT_PIO3_3 IOPCTL_MUX(99, 7) /* PIO3_3 */ +#define DMIC0_CLK6_7_PIO3_3 IOPCTL_MUX(99, 1) /* PIO3_3 */ +#define FC0_CTS_SDA_SSEL0_PIO3_3 IOPCTL_MUX(99, 5) /* PIO3_3 */ +#define GPIO_PIO33_PIO3_3 IOPCTL_MUX(99, 0) /* PIO3_3 */ +#define DMIC0_DATA0_1_PIO3_4 IOPCTL_MUX(100, 1) /* PIO3_4 */ +#define FC0_RTS_SCL_SSEL1_PIO3_4 IOPCTL_MUX(100, 5) /* PIO3_4 */ +#define GPIO_PIO34_PIO3_4 IOPCTL_MUX(100, 0) /* PIO3_4 */ +#define DMIC0_DATA2_3_PIO3_5 IOPCTL_MUX(101, 1) /* PIO3_5 */ +#define FC0_SSEL2_PIO3_5 IOPCTL_MUX(101, 5) /* PIO3_5 */ +#define GPIO_PIO35_PIO3_5 IOPCTL_MUX(101, 0) /* PIO3_5 */ +#define DMIC0_DATA4_5_PIO3_6 IOPCTL_MUX(102, 1) /* PIO3_6 */ +#define FC0_SSEL3_PIO3_6 IOPCTL_MUX(102, 5) /* PIO3_6 */ +#define GPIO_PIO36_PIO3_6 IOPCTL_MUX(102, 0) /* PIO3_6 */ +#define DMIC0_DATA6_7_PIO3_7 IOPCTL_MUX(103, 1) /* PIO3_7 */ +#define GPIO_PIO37_PIO3_7 IOPCTL_MUX(103, 0) /* PIO3_7 */ +#define CTIMER0_MATCH0_PIO3_8 IOPCTL_MUX(104, 4) /* PIO3_8 */ +#define GPIO_PIO38_PIO3_8 IOPCTL_MUX(104, 0) /* PIO3_8 */ +#define SD1_CLK_PIO3_8 IOPCTL_MUX(104, 1) /* PIO3_8 */ +#define CTIMER0_MATCH1_PIO3_9 IOPCTL_MUX(105, 4) /* PIO3_9 */ +#define GPIO_PIO39_PIO3_9 IOPCTL_MUX(105, 0) /* PIO3_9 */ +#define SD1_CMD_PIO3_9 IOPCTL_MUX(105, 1) /* PIO3_9 */ +#define CTIMER0_MATCH2_PIO3_10 IOPCTL_MUX(106, 4) /* PIO3_10 */ +#define GPIO_PIO310_PIO3_10 IOPCTL_MUX(106, 0) /* PIO3_10 */ +#define USDHC1_USDHC_DATA0_PIO3_10 IOPCTL_MUX(106, 1) /* PIO3_10 */ +#define CTIMER0_MATCH3_PIO3_11 IOPCTL_MUX(107, 4) /* PIO3_11 */ +#define GPIO_PIO311_PIO3_11 IOPCTL_MUX(107, 0) /* PIO3_11 */ +#define USDHC1_USDHC_DATA1_PIO3_11 IOPCTL_MUX(107, 1) /* PIO3_11 */ +#define CTIMER0_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER0_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER0_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER0_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER1_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER2_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER3_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE0_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE1_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE2_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define CTIMER4_CAPTURE3_PIO3_12 IOPCTL_MUX(108, 4) /* PIO3_12 */ +#define GPIO_PIO312_PIO3_12 IOPCTL_MUX(108, 0) /* PIO3_12 */ +#define USDHC1_USDHC_DATA2_PIO3_12 IOPCTL_MUX(108, 1) /* PIO3_12 */ +#define CTIMER0_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER0_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER0_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER0_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER1_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER2_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER3_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE0_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE1_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE2_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define CTIMER4_CAPTURE3_PIO3_13 IOPCTL_MUX(109, 4) /* PIO3_13 */ +#define GPIO_PIO313_PIO3_13 IOPCTL_MUX(109, 0) /* PIO3_13 */ +#define USDHC1_USDHC_DATA3_PIO3_13 IOPCTL_MUX(109, 1) /* PIO3_13 */ +#define CTIMER3_MATCH0_PIO3_14 IOPCTL_MUX(110, 4) /* PIO3_14 */ +#define GPIO_PIO314_PIO3_14 IOPCTL_MUX(110, 0) /* PIO3_14 */ +#define SD1_WR_PRT_PIO3_14 IOPCTL_MUX(110, 1) /* PIO3_14 */ +#define CTIMER3_MATCH1_PIO3_15 IOPCTL_MUX(111, 4) /* PIO3_15 */ +#define FC5_SCK_PIO3_15 IOPCTL_MUX(111, 5) /* PIO3_15 */ +#define GPIO_PIO315_PIO3_15 IOPCTL_MUX(111, 0) /* PIO3_15 */ +#define USDHC1_USDHC_DATA4_PIO3_15 IOPCTL_MUX(111, 1) /* PIO3_15 */ +#define CTIMER3_MATCH2_PIO3_16 IOPCTL_MUX(112, 4) /* PIO3_16 */ +#define FC5_TXD_SCL_MISO_WS_PIO3_16 IOPCTL_MUX(112, 5) /* PIO3_16 */ +#define GPIO_PIO316_PIO3_16 IOPCTL_MUX(112, 0) /* PIO3_16 */ +#define USDHC1_USDHC_DATA5_PIO3_16 IOPCTL_MUX(112, 1) /* PIO3_16 */ +#define CTIMER3_MATCH3_PIO3_17 IOPCTL_MUX(113, 4) /* PIO3_17 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO3_17 IOPCTL_MUX(113, 5) /* PIO3_17 */ +#define GPIO_PIO317_PIO3_17 IOPCTL_MUX(113, 0) /* PIO3_17 */ +#define USDHC1_USDHC_DATA6_PIO3_17 IOPCTL_MUX(113, 1) /* PIO3_17 */ +#define CTIMER4_MATCH0_PIO3_18 IOPCTL_MUX(114, 4) /* PIO3_18 */ +#define FC5_CTS_SDA_SSEL0_PIO3_18 IOPCTL_MUX(114, 5) /* PIO3_18 */ +#define GPIO_PIO318_PIO3_18 IOPCTL_MUX(114, 0) /* PIO3_18 */ +#define USDHC1_USDHC_DATA7_PIO3_18 IOPCTL_MUX(114, 1) /* PIO3_18 */ +#define CTIMER4_MATCH1_PIO3_19 IOPCTL_MUX(115, 4) /* PIO3_19 */ +#define GPIO_PIO319_PIO3_19 IOPCTL_MUX(115, 0) /* PIO3_19 */ +#define MCLK_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN0_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN1_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN2_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN3_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN4_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN5_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SCT0_IN6_PIO3_19 IOPCTL_MUX(115, 5) /* PIO3_19 */ +#define SD1_CARD_DET_N_PIO3_19 IOPCTL_MUX(115, 1) /* PIO3_19 */ +#define CTIMER4_MATCH2_PIO3_20 IOPCTL_MUX(116, 4) /* PIO3_20 */ +#define GPIO_PIO320_PIO3_20 IOPCTL_MUX(116, 0) /* PIO3_20 */ +#define SD1_RESET_N_PIO3_20 IOPCTL_MUX(116, 1) /* PIO3_20 */ +#define CTIMER4_MATCH3_PIO3_21 IOPCTL_MUX(117, 4) /* PIO3_21 */ +#define GPIO_INT_BMAT_PIO3_21 IOPCTL_MUX(117, 6) /* PIO3_21 */ +#define GPIO_PIO321_PIO3_21 IOPCTL_MUX(117, 0) /* PIO3_21 */ +#define SD1_VOLT_PIO3_21 IOPCTL_MUX(117, 1) /* PIO3_21 */ +#define FC5_RTS_SCL_SSEL1_PIO3_22 IOPCTL_MUX(118, 5) /* PIO3_22 */ +#define GPIO_PIO322_PIO3_22 IOPCTL_MUX(118, 0) /* PIO3_22 */ +#define ADC0_CH5_PIO3_23 IOPCTL_MUX(119, 0) /* PIO3_23 */ +#define FC5_SSEL2_PIO3_23 IOPCTL_MUX(119, 5) /* PIO3_23 */ +#define GPIO_PIO323_PIO3_23 IOPCTL_MUX(119, 0) /* PIO3_23 */ +#define ADC0_CH13_PIO3_24 IOPCTL_MUX(120, 0) /* PIO3_24 */ +#define FC5_SSEL3_PIO3_24 IOPCTL_MUX(120, 5) /* PIO3_24 */ +#define GPIO_PIO324_PIO3_24 IOPCTL_MUX(120, 0) /* PIO3_24 */ +#define FC6_SCK_PIO3_25 IOPCTL_MUX(121, 1) /* PIO3_25 */ +#define GPIO_PIO325_PIO3_25 IOPCTL_MUX(121, 0) /* PIO3_25 */ +#define FC6_TXD_SCL_MISO_WS_PIO3_26 IOPCTL_MUX(122, 1) /* PIO3_26 */ +#define GPIO_PIO326_PIO3_26 IOPCTL_MUX(122, 0) /* PIO3_26 */ +#define FC6_RXD_SDA_MOSI_DATA_PIO3_27 IOPCTL_MUX(123, 1) /* PIO3_27 */ +#define GPIO_PIO327_PIO3_27 IOPCTL_MUX(123, 0) /* PIO3_27 */ +#define FC6_CTS_SDA_SSEL0_PIO3_28 IOPCTL_MUX(124, 1) /* PIO3_28 */ +#define GPIO_PIO328_PIO3_28 IOPCTL_MUX(124, 0) /* PIO3_28 */ +#define FC6_RTS_SCL_SSEL1_PIO3_29 IOPCTL_MUX(125, 1) /* PIO3_29 */ +#define GPIO_PIO329_PIO3_29 IOPCTL_MUX(125, 0) /* PIO3_29 */ +#define FC6_SSEL2_PIO3_30 IOPCTL_MUX(126, 1) /* PIO3_30 */ +#define GPIO_PIO330_PIO3_30 IOPCTL_MUX(126, 0) /* PIO3_30 */ +#define FC6_SSEL3_PIO3_31 IOPCTL_MUX(127, 1) /* PIO3_31 */ +#define GPIO_PIO331_PIO3_31 IOPCTL_MUX(127, 0) /* PIO3_31 */ +#define CLKOUT_PIO4_0 IOPCTL_MUX(128, 7) /* PIO4_0 */ +#define FC7_SCK_PIO4_0 IOPCTL_MUX(128, 1) /* PIO4_0 */ +#define FREQME_IN0_PIO4_0 IOPCTL_MUX(128, 4) /* PIO4_0 */ +#define FREQME_IN1_PIO4_0 IOPCTL_MUX(128, 4) /* PIO4_0 */ +#define GPIO_PIO40_PIO4_0 IOPCTL_MUX(128, 0) /* PIO4_0 */ +#define CLKIN_PIO4_1 IOPCTL_MUX(129, 7) /* PIO4_1 */ +#define FC7_TXD_SCL_MISO_WS_PIO4_1 IOPCTL_MUX(129, 1) /* PIO4_1 */ +#define GPIO_PIO41_PIO4_1 IOPCTL_MUX(129, 0) /* PIO4_1 */ +#define FC7_RXD_SDA_MOSI_DATA_PIO4_2 IOPCTL_MUX(130, 1) /* PIO4_2 */ +#define GPIO_PIO42_PIO4_2 IOPCTL_MUX(130, 0) /* PIO4_2 */ +#define FC7_CTS_SDA_SSEL0_PIO4_3 IOPCTL_MUX(131, 1) /* PIO4_3 */ +#define GPIO_PIO43_PIO4_3 IOPCTL_MUX(131, 0) /* PIO4_3 */ +#define FC7_RTS_SCL_SSEL1_PIO4_4 IOPCTL_MUX(132, 1) /* PIO4_4 */ +#define GPIO_PIO44_PIO4_4 IOPCTL_MUX(132, 0) /* PIO4_4 */ +#define FC7_SSEL2_PIO4_5 IOPCTL_MUX(133, 1) /* PIO4_5 */ +#define GPIO_PIO45_PIO4_5 IOPCTL_MUX(133, 0) /* PIO4_5 */ +#define FC7_SSEL3_PIO4_6 IOPCTL_MUX(134, 1) /* PIO4_6 */ +#define GPIO_PIO46_PIO4_6 IOPCTL_MUX(134, 0) /* PIO4_6 */ +#define GPIO_PIO47_PIO4_7 IOPCTL_MUX(135, 0) /* PIO4_7 */ +#define MCLK_PIO4_7 IOPCTL_MUX(135, 1) /* PIO4_7 */ +#define SCT0_IN0_PIO4_7 IOPCTL_MUX(135, 1) /* PIO4_7 */ +#define SCT0_IN1_PIO4_7 IOPCTL_MUX(135, 1) /* PIO4_7 */ +#define SCT0_IN2_PIO4_7 IOPCTL_MUX(135, 1) /* PIO4_7 */ +#define SCT0_IN3_PIO4_7 IOPCTL_MUX(135, 1) /* PIO4_7 */ +#define SCT0_IN4_PIO4_7 IOPCTL_MUX(135, 1) /* PIO4_7 */ +#define SCT0_IN5_PIO4_7 IOPCTL_MUX(135, 1) /* PIO4_7 */ +#define SCT0_IN6_PIO4_7 IOPCTL_MUX(135, 1) /* PIO4_7 */ +#define CMP0_OUT_PIO4_8 IOPCTL_MUX(136, 7) /* PIO4_8 */ +#define FC2_CTS_SDA_SSEL0_PIO4_8 IOPCTL_MUX(136, 5) /* PIO4_8 */ +#define GPIO_PIO48_PIO4_8 IOPCTL_MUX(136, 0) /* PIO4_8 */ +#define GPIO_INT_BMAT_PIO4_9 IOPCTL_MUX(137, 6) /* PIO4_9 */ +#define GPIO_PIO49_PIO4_9 IOPCTL_MUX(137, 0) /* PIO4_9 */ +#define FC2_SCK_PIO7_24 IOPCTL_MUX(248, 5) /* PIO7_24 */ +#define GPIO_PIO724_PIO7_24 IOPCTL_MUX(248, 0) /* PIO7_24 */ +#define FC1_SCK_PIO7_25 IOPCTL_MUX(249, 1) /* PIO7_25 */ +#define GPIO_PIO725_PIO7_25 IOPCTL_MUX(249, 0) /* PIO7_25 */ +#define FC1_TXD_SCL_MISO_WS_PIO7_26 IOPCTL_MUX(250, 1) /* PIO7_26 */ +#define GPIO_PIO726_PIO7_26 IOPCTL_MUX(250, 0) /* PIO7_26 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO7_27 IOPCTL_MUX(251, 1) /* PIO7_27 */ +#define GPIO_PIO727_PIO7_27 IOPCTL_MUX(251, 0) /* PIO7_27 */ +#define FC1_CTS_SDA_SSEL0_PIO7_28 IOPCTL_MUX(252, 1) /* PIO7_28 */ +#define GPIO_PIO728_PIO7_28 IOPCTL_MUX(252, 0) /* PIO7_28 */ +#define FC1_RTS_SCL_SSEL1_PIO7_29 IOPCTL_MUX(253, 1) /* PIO7_29 */ +#define GPIO_PIO729_PIO7_29 IOPCTL_MUX(253, 0) /* PIO7_29 */ +#define FC1_SSEL2_PIO7_30 IOPCTL_MUX(254, 1) /* PIO7_30 */ +#define FC2_TXD_SCL_MISO_WS_PIO7_30 IOPCTL_MUX(254, 5) /* PIO7_30 */ +#define GPIO_PIO730_PIO7_30 IOPCTL_MUX(254, 0) /* PIO7_30 */ +#define FC1_SSEL3_PIO7_31 IOPCTL_MUX(255, 1) /* PIO7_31 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO7_31 IOPCTL_MUX(255, 5) /* PIO7_31 */ +#define GPIO_PIO731_PIO7_31 IOPCTL_MUX(255, 0) /* PIO7_31 */ + +#endif diff --git a/dts/nxp/nxp_imx/rt/MIMXRT633SFVKB-pinctrl.h b/dts/nxp/nxp_imx/rt/MIMXRT633SFVKB-pinctrl.h new file mode 100644 index 000000000..32d9fa49d --- /dev/null +++ b/dts/nxp/nxp_imx/rt/MIMXRT633SFVKB-pinctrl.h @@ -0,0 +1,5790 @@ +/* + * NOTE: File generated by gen_soc_headers.py + * from MIMXRT633SFVKB/signal_configuration.xml + * + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DTS_BINDING_MIMXRT633SFVKB_ +#define _ZEPHYR_DTS_BINDING_MIMXRT633SFVKB_ + +#define IOPCTL_MUX(offset, mux) \ + ((((offset) & 0xFFF) << 20) | \ + (((mux) & 0xF) << 0)) + +#define CTIMER0_MATCH0_PIO0_0 IOPCTL_MUX(0, 4) /* PIO0_0 */ +#define DMA0_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA0_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG10_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG11_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG12_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG13_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG14_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG15_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG16_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG17_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG18_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG19_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG20_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG21_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG22_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG23_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG24_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG25_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG26_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG27_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG28_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG29_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG30_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG31_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG32_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG8_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define DMA1_TRIG9_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define FC0_SCK_PIO0_0 IOPCTL_MUX(0, 1) /* PIO0_0 */ +#define GPIO_INT_BMAT_PIO0_0 IOPCTL_MUX(0, 6) /* PIO0_0 */ +#define GPIO_PIO00_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define I2S_BRIDGE_CLK_IN_PIO0_0 IOPCTL_MUX(0, 5) /* PIO0_0 */ +#define PINT_PINT0_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT1_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT2_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT3_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT4_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT5_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT6_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define PINT_PINT7_PIO0_0 IOPCTL_MUX(0, 0) /* PIO0_0 */ +#define SECGPIO_SECPIO00_PIO0_0 IOPCTL_MUX(0, 8) /* PIO0_0 */ +#define PMIC_I2C_SCL IOPCTL_MUX(256, 0) /* PIO0_0 */ +#define PMIC_I2C_SDA IOPCTL_MUX(257, 0) /* PIO0_0 */ +#define CTIMER0_MATCH1_PIO0_1 IOPCTL_MUX(1, 4) /* PIO0_1 */ +#define DMA0_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA0_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG10_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG11_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG12_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG13_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG14_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG15_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG16_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG17_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG18_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG19_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG20_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG21_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG22_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG23_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG24_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG25_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG26_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG27_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG28_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG29_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG30_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG31_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG32_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG8_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define DMA1_TRIG9_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define FC0_TXD_SCL_MISO_WS_PIO0_1 IOPCTL_MUX(1, 1) /* PIO0_1 */ +#define GPIO_PIO01_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define I2S_BRIDGE_WS_IN_PIO0_1 IOPCTL_MUX(1, 5) /* PIO0_1 */ +#define PINT_PINT0_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT1_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT2_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT3_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT4_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT5_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT6_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define PINT_PINT7_PIO0_1 IOPCTL_MUX(1, 0) /* PIO0_1 */ +#define SECGPIO_SECPIO01_PIO0_1 IOPCTL_MUX(1, 8) /* PIO0_1 */ +#define CTIMER0_MATCH2_PIO0_2 IOPCTL_MUX(2, 4) /* PIO0_2 */ +#define DMA0_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA0_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG10_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG11_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG12_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG13_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG14_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG15_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG16_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG17_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG18_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG19_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG20_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG21_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG22_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG23_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG24_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG25_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG26_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG27_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG28_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG29_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG30_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG31_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG32_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG8_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define DMA1_TRIG9_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define FC0_RXD_SDA_MOSI_DATA_PIO0_2 IOPCTL_MUX(2, 1) /* PIO0_2 */ +#define GPIO_PIO02_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define I2S_BRIDGE_DATA_IN_PIO0_2 IOPCTL_MUX(2, 5) /* PIO0_2 */ +#define PINT_PINT0_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT1_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT2_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT3_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT4_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT5_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT6_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define PINT_PINT7_PIO0_2 IOPCTL_MUX(2, 0) /* PIO0_2 */ +#define SECGPIO_SECPIO02_PIO0_2 IOPCTL_MUX(2, 8) /* PIO0_2 */ +#define CTIMER0_MATCH3_PIO0_3 IOPCTL_MUX(3, 4) /* PIO0_3 */ +#define DMA0_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA0_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG10_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG11_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG12_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG13_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG14_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG15_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG16_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG17_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG18_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG19_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG20_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG21_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG22_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG23_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG24_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG25_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG26_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG27_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG28_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG29_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG30_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG31_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG32_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG8_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define DMA1_TRIG9_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define FC0_CTS_SDA_SSEL0_PIO0_3 IOPCTL_MUX(3, 1) /* PIO0_3 */ +#define FC1_SSEL2_PIO0_3 IOPCTL_MUX(3, 5) /* PIO0_3 */ +#define GPIO_PIO03_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT0_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT1_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT2_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT3_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT4_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT5_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT6_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define PINT_PINT7_PIO0_3 IOPCTL_MUX(3, 0) /* PIO0_3 */ +#define SECGPIO_SECPIO03_PIO0_3 IOPCTL_MUX(3, 8) /* PIO0_3 */ +#define CMP0_OUT_PIO0_4 IOPCTL_MUX(4, 7) /* PIO0_4 */ +#define CTIMER0_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER0_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER1_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER2_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER3_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE0_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE1_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE2_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define CTIMER4_CAPTURE3_PIO0_4 IOPCTL_MUX(4, 4) /* PIO0_4 */ +#define DMA0_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA0_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG10_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG11_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG12_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG13_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG14_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG15_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG16_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG17_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG18_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG19_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG20_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG21_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG22_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG23_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG24_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG25_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG26_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG27_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG28_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG29_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG30_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG31_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG32_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG8_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define DMA1_TRIG9_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define FC0_RTS_SCL_SSEL1_PIO0_4 IOPCTL_MUX(4, 1) /* PIO0_4 */ +#define FC1_SSEL3_PIO0_4 IOPCTL_MUX(4, 5) /* PIO0_4 */ +#define GPIO_PIO04_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT0_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT1_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT2_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT3_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT4_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT5_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT6_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define PINT_PINT7_PIO0_4 IOPCTL_MUX(4, 0) /* PIO0_4 */ +#define SECGPIO_SECPIO04_PIO0_4 IOPCTL_MUX(4, 8) /* PIO0_4 */ +#define ADC0_CH0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define CTIMER0_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER0_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER1_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER2_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER3_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE0_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE1_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE2_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define CTIMER4_CAPTURE3_PIO0_5 IOPCTL_MUX(5, 4) /* PIO0_5 */ +#define DMA0_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA0_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG10_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG11_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG12_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG13_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG14_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG15_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG16_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG17_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG18_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG19_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG20_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG21_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG22_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG23_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG24_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG25_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG26_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG27_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG28_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG29_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG30_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG31_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG32_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG8_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define DMA1_TRIG9_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define FC0_SSEL2_PIO0_5 IOPCTL_MUX(5, 1) /* PIO0_5 */ +#define GPIO_PIO05_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT0_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT1_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT2_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT3_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT4_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT5_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define PINT_PINT7_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ +#define SCT0_IN0_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN1_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN2_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN3_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN4_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN5_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_IN6_PIO0_5 IOPCTL_MUX(5, 2) /* PIO0_5 */ +#define SCT0_OUT0_PIO0_5 IOPCTL_MUX(5, 3) /* PIO0_5 */ +#define SECGPIO_SECPIO05_PIO0_5 IOPCTL_MUX(5, 8) /* PIO0_5 */ +#define ADC0_CH8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define CTIMER0_MATCH0_PIO0_6 IOPCTL_MUX(6, 4) /* PIO0_6 */ +#define DMA0_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA0_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG10_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG11_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG12_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG13_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG14_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG15_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG16_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG17_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG18_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG19_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG20_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG21_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG22_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG23_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG24_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG25_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG26_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG27_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG28_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG29_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG30_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG31_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG32_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG8_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define DMA1_TRIG9_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define FC0_SSEL3_PIO0_6 IOPCTL_MUX(6, 1) /* PIO0_6 */ +#define GPIO_PIO06_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT0_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT1_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT2_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT3_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT4_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT5_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT6_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define PINT_PINT7_PIO0_6 IOPCTL_MUX(6, 0) /* PIO0_6 */ +#define SCT0_IN0_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN1_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN2_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN3_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN4_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN5_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_IN6_PIO0_6 IOPCTL_MUX(6, 2) /* PIO0_6 */ +#define SCT0_OUT1_PIO0_6 IOPCTL_MUX(6, 3) /* PIO0_6 */ +#define SECGPIO_SECPIO06_PIO0_6 IOPCTL_MUX(6, 8) /* PIO0_6 */ +#define CTIMER1_MATCH0_PIO0_7 IOPCTL_MUX(7, 4) /* PIO0_7 */ +#define DMA0_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA0_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG10_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG11_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG12_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG13_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG14_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG15_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG16_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG17_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG18_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG19_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG20_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG21_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG22_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG23_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG24_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG25_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG26_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG27_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG28_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG29_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG30_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG31_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG32_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG8_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define DMA1_TRIG9_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define FC1_SCK_PIO0_7 IOPCTL_MUX(7, 1) /* PIO0_7 */ +#define GPIO_PIO07_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_7 IOPCTL_MUX(7, 5) /* PIO0_7 */ +#define PINT_PINT0_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT1_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT2_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT3_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT4_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT5_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT6_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define PINT_PINT7_PIO0_7 IOPCTL_MUX(7, 0) /* PIO0_7 */ +#define SCT0_IN0_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN1_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN2_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN3_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN4_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN5_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_IN6_PIO0_7 IOPCTL_MUX(7, 2) /* PIO0_7 */ +#define SCT0_OUT4_PIO0_7 IOPCTL_MUX(7, 3) /* PIO0_7 */ +#define SECGPIO_SECPIO07_PIO0_7 IOPCTL_MUX(7, 8) /* PIO0_7 */ +#define CTIMER1_MATCH1_PIO0_8 IOPCTL_MUX(8, 4) /* PIO0_8 */ +#define DMA0_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA0_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG10_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG11_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG12_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG13_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG14_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG15_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG16_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG17_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG18_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG19_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG20_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG21_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG22_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG23_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG24_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG25_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG26_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG27_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG28_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG29_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG30_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG31_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG32_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG8_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define DMA1_TRIG9_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define FC1_TXD_SCL_MISO_WS_PIO0_8 IOPCTL_MUX(8, 1) /* PIO0_8 */ +#define GPIO_PIO08_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define I2S_BRIDGE_WS_OUT_PIO0_8 IOPCTL_MUX(8, 5) /* PIO0_8 */ +#define PINT_PINT0_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT1_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT2_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT3_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT4_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT5_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT6_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define PINT_PINT7_PIO0_8 IOPCTL_MUX(8, 0) /* PIO0_8 */ +#define SCT0_IN0_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN1_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN2_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN3_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN4_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN5_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_IN6_PIO0_8 IOPCTL_MUX(8, 2) /* PIO0_8 */ +#define SCT0_OUT5_PIO0_8 IOPCTL_MUX(8, 3) /* PIO0_8 */ +#define SECGPIO_SECPIO08_PIO0_8 IOPCTL_MUX(8, 8) /* PIO0_8 */ +#define CTIMER1_MATCH2_PIO0_9 IOPCTL_MUX(9, 4) /* PIO0_9 */ +#define DMA0_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA0_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG10_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG11_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG12_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG13_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG14_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG15_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG16_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG17_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG18_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG19_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG20_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG21_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG22_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG23_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG24_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG25_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG26_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG27_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG28_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG29_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG30_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG31_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG32_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG8_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define DMA1_TRIG9_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define FC1_RXD_SDA_MOSI_DATA_PIO0_9 IOPCTL_MUX(9, 1) /* PIO0_9 */ +#define GPIO_PIO09_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_9 IOPCTL_MUX(9, 5) /* PIO0_9 */ +#define PINT_PINT0_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT1_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT2_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT3_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT4_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT5_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT6_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define PINT_PINT7_PIO0_9 IOPCTL_MUX(9, 0) /* PIO0_9 */ +#define SCT0_IN0_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN1_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN2_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN3_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN4_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN5_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_IN6_PIO0_9 IOPCTL_MUX(9, 2) /* PIO0_9 */ +#define SCT0_OUT6_PIO0_9 IOPCTL_MUX(9, 3) /* PIO0_9 */ +#define SECGPIO_SECPIO09_PIO0_9 IOPCTL_MUX(9, 8) /* PIO0_9 */ +#define CTIMER1_MATCH3_PIO0_10 IOPCTL_MUX(10, 4) /* PIO0_10 */ +#define DMA0_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA0_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG10_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG11_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG12_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG13_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG14_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG15_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG16_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG17_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG18_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG19_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG20_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG21_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG22_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG23_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG24_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG25_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG26_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG27_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG28_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG29_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG30_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG31_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG32_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG8_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define DMA1_TRIG9_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define FC0_SSEL2_PIO0_10 IOPCTL_MUX(10, 5) /* PIO0_10 */ +#define FC1_CTS_SDA_SSEL0_PIO0_10 IOPCTL_MUX(10, 1) /* PIO0_10 */ +#define GPIO_PIO010_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT0_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT1_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT2_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT3_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT4_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT5_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT6_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define PINT_PINT7_PIO0_10 IOPCTL_MUX(10, 0) /* PIO0_10 */ +#define SCT0_IN0_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN1_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN2_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN3_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN4_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN5_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_IN6_PIO0_10 IOPCTL_MUX(10, 2) /* PIO0_10 */ +#define SCT0_OUT7_PIO0_10 IOPCTL_MUX(10, 3) /* PIO0_10 */ +#define SECGPIO_SECPIO010_PIO0_10 IOPCTL_MUX(10, 8) /* PIO0_10 */ +#define CTIMER0_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER0_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER1_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER2_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER3_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE0_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE1_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE2_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define CTIMER4_CAPTURE3_PIO0_11 IOPCTL_MUX(11, 4) /* PIO0_11 */ +#define DMA0_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA0_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG10_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG11_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG12_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG13_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG14_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG15_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG16_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG17_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG18_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG19_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG20_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG21_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG22_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG23_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG24_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG25_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG26_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG27_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG28_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG29_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG30_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG31_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG32_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG8_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define DMA1_TRIG9_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define FC0_SSEL3_PIO0_11 IOPCTL_MUX(11, 5) /* PIO0_11 */ +#define FC1_RTS_SCL_SSEL1_PIO0_11 IOPCTL_MUX(11, 1) /* PIO0_11 */ +#define GPIO_PIO011_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT0_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT1_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT2_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT3_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT4_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT5_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT6_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define PINT_PINT7_PIO0_11 IOPCTL_MUX(11, 0) /* PIO0_11 */ +#define SCT0_IN0_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN1_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN2_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN3_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN4_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN5_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_IN6_PIO0_11 IOPCTL_MUX(11, 2) /* PIO0_11 */ +#define SCT0_OUT8_PIO0_11 IOPCTL_MUX(11, 3) /* PIO0_11 */ +#define SECGPIO_SECPIO011_PIO0_11 IOPCTL_MUX(11, 8) /* PIO0_11 */ +#define ADC0_CH1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define CTIMER0_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER0_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER1_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER2_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER3_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE0_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE1_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE2_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define CTIMER4_CAPTURE3_PIO0_12 IOPCTL_MUX(12, 4) /* PIO0_12 */ +#define DMA0_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA0_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG10_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG11_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG12_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG13_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG14_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG15_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG16_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG17_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG18_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG19_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG20_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG21_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG22_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG23_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG24_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG25_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG26_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG27_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG28_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG29_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG30_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG31_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG32_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG8_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define DMA1_TRIG9_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define FC1_SSEL2_PIO0_12 IOPCTL_MUX(12, 1) /* PIO0_12 */ +#define GPIO_PIO012_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT0_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT1_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT2_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT3_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT4_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT5_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT6_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define PINT_PINT7_PIO0_12 IOPCTL_MUX(12, 0) /* PIO0_12 */ +#define SCT0_IN0_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN1_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN2_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN3_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN4_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN5_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_IN6_PIO0_12 IOPCTL_MUX(12, 2) /* PIO0_12 */ +#define SCT0_OUT2_PIO0_12 IOPCTL_MUX(12, 3) /* PIO0_12 */ +#define SECGPIO_SECPIO012_PIO0_12 IOPCTL_MUX(12, 8) /* PIO0_12 */ +#define ADC0_CH9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define CTIMER0_MATCH1_PIO0_13 IOPCTL_MUX(13, 4) /* PIO0_13 */ +#define DMA0_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA0_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG10_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG11_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG12_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG13_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG14_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG15_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG16_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG17_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG18_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG19_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG20_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG21_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG22_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG23_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG24_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG25_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG26_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG27_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG28_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG29_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG30_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG31_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG32_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG8_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define DMA1_TRIG9_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define FC1_SSEL3_PIO0_13 IOPCTL_MUX(13, 1) /* PIO0_13 */ +#define GPIO_PIO013_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT0_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT1_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT2_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT3_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT4_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT5_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT6_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define PINT_PINT7_PIO0_13 IOPCTL_MUX(13, 0) /* PIO0_13 */ +#define SCT0_IN0_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN1_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN2_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN3_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN4_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN5_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_IN6_PIO0_13 IOPCTL_MUX(13, 2) /* PIO0_13 */ +#define SCT0_OUT3_PIO0_13 IOPCTL_MUX(13, 3) /* PIO0_13 */ +#define SECGPIO_SECPIO013_PIO0_13 IOPCTL_MUX(13, 8) /* PIO0_13 */ +#define CTIMER2_MATCH0_PIO0_14 IOPCTL_MUX(14, 4) /* PIO0_14 */ +#define DMA0_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA0_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG10_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG11_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG12_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG13_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG14_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG15_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG16_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG17_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG18_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG19_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG20_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG21_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG22_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG23_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG24_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG25_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG26_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG27_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG28_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG29_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG30_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG31_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG32_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG8_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define DMA1_TRIG9_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define FC2_SCK_PIO0_14 IOPCTL_MUX(14, 1) /* PIO0_14 */ +#define GPIO_PIO014_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define I2S_BRIDGE_CLK_IN_PIO0_14 IOPCTL_MUX(14, 5) /* PIO0_14 */ +#define PINT_PINT0_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT1_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT2_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT3_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT4_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT5_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT6_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define PINT_PINT7_PIO0_14 IOPCTL_MUX(14, 0) /* PIO0_14 */ +#define SCT0_IN0_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN1_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN2_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN3_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN4_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN5_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_IN6_PIO0_14 IOPCTL_MUX(14, 2) /* PIO0_14 */ +#define SCT0_OUT0_PIO0_14 IOPCTL_MUX(14, 3) /* PIO0_14 */ +#define SECGPIO_SECPIO014_PIO0_14 IOPCTL_MUX(14, 8) /* PIO0_14 */ +#define CTIMER2_MATCH1_PIO0_15 IOPCTL_MUX(15, 4) /* PIO0_15 */ +#define DMA0_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA0_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG10_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG11_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG12_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG13_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG14_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG15_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG16_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG17_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG18_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG19_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG20_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG21_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG22_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG23_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG24_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG25_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG26_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG27_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG28_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG29_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG30_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG31_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG32_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG8_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define DMA1_TRIG9_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define FC2_TXD_SCL_MISO_WS_PIO0_15 IOPCTL_MUX(15, 1) /* PIO0_15 */ +#define GPIO_PIO015_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define I2S_BRIDGE_WS_IN_PIO0_15 IOPCTL_MUX(15, 5) /* PIO0_15 */ +#define PINT_PINT0_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT1_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT2_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT3_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT4_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT5_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT6_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define PINT_PINT7_PIO0_15 IOPCTL_MUX(15, 0) /* PIO0_15 */ +#define SCT0_IN0_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN1_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN2_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN3_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN4_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN5_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_IN6_PIO0_15 IOPCTL_MUX(15, 2) /* PIO0_15 */ +#define SCT0_OUT1_PIO0_15 IOPCTL_MUX(15, 3) /* PIO0_15 */ +#define SECGPIO_SECPIO015_PIO0_15 IOPCTL_MUX(15, 8) /* PIO0_15 */ +#define CTIMER2_MATCH2_PIO0_16 IOPCTL_MUX(16, 4) /* PIO0_16 */ +#define DMA0_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA0_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG10_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG11_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG12_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG13_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG14_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG15_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG16_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG17_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG18_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG19_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG20_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG21_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG22_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG23_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG24_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG25_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG26_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG27_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG28_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG29_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG30_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG31_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG32_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG8_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define DMA1_TRIG9_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define FC2_RXD_SDA_MOSI_DATA_PIO0_16 IOPCTL_MUX(16, 1) /* PIO0_16 */ +#define GPIO_PIO016_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define I2S_BRIDGE_DATA_IN_PIO0_16 IOPCTL_MUX(16, 5) /* PIO0_16 */ +#define PINT_PINT0_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT1_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT2_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT3_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT4_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT5_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT6_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define PINT_PINT7_PIO0_16 IOPCTL_MUX(16, 0) /* PIO0_16 */ +#define SCT0_IN0_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN1_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN2_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN3_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN4_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN5_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_IN6_PIO0_16 IOPCTL_MUX(16, 2) /* PIO0_16 */ +#define SCT0_OUT2_PIO0_16 IOPCTL_MUX(16, 3) /* PIO0_16 */ +#define SECGPIO_SECPIO016_PIO0_16 IOPCTL_MUX(16, 8) /* PIO0_16 */ +#define CTIMER2_MATCH3_PIO0_17 IOPCTL_MUX(17, 4) /* PIO0_17 */ +#define DMA0_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA0_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG10_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG11_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG12_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG13_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG14_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG15_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG16_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG17_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG18_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG19_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG20_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG21_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG22_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG23_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG24_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG25_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG26_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG27_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG28_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG29_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG30_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG31_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG32_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG8_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define DMA1_TRIG9_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define FC2_CTS_SDA_SSEL0_PIO0_17 IOPCTL_MUX(17, 1) /* PIO0_17 */ +#define FC5_SSEL2_PIO0_17 IOPCTL_MUX(17, 5) /* PIO0_17 */ +#define GPIO_PIO017_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT0_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT1_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT2_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT3_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT4_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT5_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT6_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define PINT_PINT7_PIO0_17 IOPCTL_MUX(17, 0) /* PIO0_17 */ +#define SCT0_IN0_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN1_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN2_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN3_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN4_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN5_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_IN6_PIO0_17 IOPCTL_MUX(17, 2) /* PIO0_17 */ +#define SCT0_OUT3_PIO0_17 IOPCTL_MUX(17, 3) /* PIO0_17 */ +#define SECGPIO_SECPIO017_PIO0_17 IOPCTL_MUX(17, 8) /* PIO0_17 */ +#define CTIMER0_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER0_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER1_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER2_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER3_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE0_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE1_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE2_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define CTIMER4_CAPTURE3_PIO0_18 IOPCTL_MUX(18, 4) /* PIO0_18 */ +#define DMA0_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA0_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG10_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG11_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG12_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG13_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG14_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG15_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG16_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG17_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG18_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG19_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG20_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG21_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG22_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG23_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG24_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG25_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG26_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG27_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG28_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG29_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG30_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG31_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG32_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG8_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define DMA1_TRIG9_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define FC2_RTS_SCL_SSEL1_PIO0_18 IOPCTL_MUX(18, 1) /* PIO0_18 */ +#define FC5_SSEL3_PIO0_18 IOPCTL_MUX(18, 5) /* PIO0_18 */ +#define GPIO_PIO018_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT0_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT1_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT2_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT3_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT4_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT5_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT6_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define PINT_PINT7_PIO0_18 IOPCTL_MUX(18, 0) /* PIO0_18 */ +#define SCT0_IN0_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN1_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN2_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN3_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN4_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN5_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_IN6_PIO0_18 IOPCTL_MUX(18, 2) /* PIO0_18 */ +#define SCT0_OUT6_PIO0_18 IOPCTL_MUX(18, 3) /* PIO0_18 */ +#define SECGPIO_SECPIO018_PIO0_18 IOPCTL_MUX(18, 8) /* PIO0_18 */ +#define ADC0_CH2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define CTIMER0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER0_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER1_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER2_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER3_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE1_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE2_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define CTIMER4_CAPTURE3_PIO0_19 IOPCTL_MUX(19, 4) /* PIO0_19 */ +#define DMA0_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA0_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG10_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG11_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG12_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG13_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG14_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG15_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG16_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG17_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG18_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG19_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG20_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG21_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG22_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG23_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG24_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG25_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG26_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG27_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG28_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG29_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG30_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG31_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG32_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG8_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define DMA1_TRIG9_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define FC2_SSEL2_PIO0_19 IOPCTL_MUX(19, 1) /* PIO0_19 */ +#define GPIO_PIO019_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT0_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT1_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT2_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT3_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT4_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT5_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT6_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define PINT_PINT7_PIO0_19 IOPCTL_MUX(19, 0) /* PIO0_19 */ +#define SCT0_IN0_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN1_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN2_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN3_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN4_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN5_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_IN6_PIO0_19 IOPCTL_MUX(19, 2) /* PIO0_19 */ +#define SCT0_OUT4_PIO0_19 IOPCTL_MUX(19, 3) /* PIO0_19 */ +#define SECGPIO_SECPIO019_PIO0_19 IOPCTL_MUX(19, 8) /* PIO0_19 */ +#define UTICK0_CAPTURE0_PIO0_19 IOPCTL_MUX(19, 5) /* PIO0_19 */ +#define ADC0_CH10_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define CTIMER0_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER0_MATCH2_PIO0_20 IOPCTL_MUX(20, 4) /* PIO0_20 */ +#define CTIMER1_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER1_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER1_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER1_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER2_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER3_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE0_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE1_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE2_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define CTIMER4_CAPTURE3_PIO0_20 IOPCTL_MUX(20, 5) /* PIO0_20 */ +#define DMA0_TRIG0_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG10_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG11_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG12_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG13_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG14_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG15_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG16_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG17_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG18_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG19_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG1_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG20_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG21_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG22_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG23_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG24_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG25_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG26_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG27_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG28_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG29_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG2_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG30_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG31_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG32_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG3_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG4_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG5_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG6_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG7_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG8_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA0_TRIG9_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG0_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG10_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG11_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG12_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG13_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG14_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG15_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG16_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG17_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG18_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG19_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG1_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG20_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG21_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG22_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG23_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG24_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG25_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG26_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG27_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG28_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG29_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG2_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG30_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG31_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG32_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG3_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG4_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG5_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG6_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG7_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG8_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define DMA1_TRIG9_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define FC2_SSEL3_PIO0_20 IOPCTL_MUX(20, 1) /* PIO0_20 */ +#define GPIO_PIO020_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT0_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT1_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT2_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT3_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT4_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT5_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT6_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define PINT_PINT7_PIO0_20 IOPCTL_MUX(20, 0) /* PIO0_20 */ +#define SCT0_IN0_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN1_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN2_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN3_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN4_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN5_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_IN6_PIO0_20 IOPCTL_MUX(20, 2) /* PIO0_20 */ +#define SCT0_OUT5_PIO0_20 IOPCTL_MUX(20, 3) /* PIO0_20 */ +#define SECGPIO_SECPIO020_PIO0_20 IOPCTL_MUX(20, 8) /* PIO0_20 */ +#define CTIMER3_MATCH0_PIO0_21 IOPCTL_MUX(21, 4) /* PIO0_21 */ +#define DMA0_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA0_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG10_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG11_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG12_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG13_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG14_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG15_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG16_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG17_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG18_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG19_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG20_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG21_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG22_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG23_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG24_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG25_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG26_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG27_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG28_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG29_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG30_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG31_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG32_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG8_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define DMA1_TRIG9_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define FC3_SCK_PIO0_21 IOPCTL_MUX(21, 1) /* PIO0_21 */ +#define GPIO_PIO021_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT0_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT1_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT2_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT3_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT4_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT5_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT6_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define PINT_PINT7_PIO0_21 IOPCTL_MUX(21, 0) /* PIO0_21 */ +#define SECGPIO_SECPIO021_PIO0_21 IOPCTL_MUX(21, 8) /* PIO0_21 */ +#define TRACECLK_PIO0_21 IOPCTL_MUX(21, 6) /* PIO0_21 */ +#define CTIMER3_MATCH1_PIO0_22 IOPCTL_MUX(22, 4) /* PIO0_22 */ +#define DMA0_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA0_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG10_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG11_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG12_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG13_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG14_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG15_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG16_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG17_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG18_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG19_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG20_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG21_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG22_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG23_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG24_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG25_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG26_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG27_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG28_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG29_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG30_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG31_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG32_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG8_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define DMA1_TRIG9_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define FC3_TXD_SCL_MISO_WS_PIO0_22 IOPCTL_MUX(22, 1) /* PIO0_22 */ +#define GPIO_PIO022_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT0_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT1_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT2_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT3_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT4_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT5_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT6_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define PINT_PINT7_PIO0_22 IOPCTL_MUX(22, 0) /* PIO0_22 */ +#define SECGPIO_SECPIO022_PIO0_22 IOPCTL_MUX(22, 8) /* PIO0_22 */ +#define SWD_TRACEDATA0_PIO0_22 IOPCTL_MUX(22, 6) /* PIO0_22 */ +#define CTIMER3_MATCH2_PIO0_23 IOPCTL_MUX(23, 4) /* PIO0_23 */ +#define DMA0_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA0_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG10_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG11_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG12_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG13_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG14_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG15_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG16_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG17_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG18_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG19_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG20_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG21_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG22_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG23_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG24_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG25_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG26_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG27_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG28_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG29_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG30_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG31_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG32_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG8_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define DMA1_TRIG9_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define FC3_RXD_SDA_MOSI_DATA_PIO0_23 IOPCTL_MUX(23, 1) /* PIO0_23 */ +#define GPIO_PIO023_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT0_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT1_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT2_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT3_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT4_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT5_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT6_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define PINT_PINT7_PIO0_23 IOPCTL_MUX(23, 0) /* PIO0_23 */ +#define SECGPIO_SECPIO023_PIO0_23 IOPCTL_MUX(23, 8) /* PIO0_23 */ +#define SWD_TRACEDATA1_PIO0_23 IOPCTL_MUX(23, 6) /* PIO0_23 */ +#define CLKOUT_PIO0_24 IOPCTL_MUX(24, 7) /* PIO0_24 */ +#define CTIMER3_MATCH3_PIO0_24 IOPCTL_MUX(24, 4) /* PIO0_24 */ +#define DMA0_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA0_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG10_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG11_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG12_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG13_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG14_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG15_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG16_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG17_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG18_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG19_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG20_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG21_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG22_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG23_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG24_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG25_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG26_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG27_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG28_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG29_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG30_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG31_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG32_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG8_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define DMA1_TRIG9_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define FC2_SSEL2_PIO0_24 IOPCTL_MUX(24, 5) /* PIO0_24 */ +#define FC3_CTS_SDA_SSEL0_PIO0_24 IOPCTL_MUX(24, 1) /* PIO0_24 */ +#define GPIO_PIO024_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT0_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT1_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT2_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT3_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT4_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT5_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT6_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define PINT_PINT7_PIO0_24 IOPCTL_MUX(24, 0) /* PIO0_24 */ +#define SECGPIO_SECPIO024_PIO0_24 IOPCTL_MUX(24, 8) /* PIO0_24 */ +#define SWD_TRACEDATA2_PIO0_24 IOPCTL_MUX(24, 6) /* PIO0_24 */ +#define CLKIN_PIO0_25 IOPCTL_MUX(25, 7) /* PIO0_25 */ +#define CTIMER0_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER0_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER1_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER2_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER3_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE0_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE1_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE2_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define CTIMER4_CAPTURE3_PIO0_25 IOPCTL_MUX(25, 4) /* PIO0_25 */ +#define DMA0_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA0_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG10_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG11_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG12_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG13_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG14_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG15_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG16_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG17_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG18_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG19_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG20_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG21_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG22_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG23_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG24_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG25_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG26_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG27_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG28_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG29_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG30_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG31_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG32_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG8_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define DMA1_TRIG9_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define FC2_SSEL3_PIO0_25 IOPCTL_MUX(25, 5) /* PIO0_25 */ +#define FC3_RTS_SCL_SSEL1_PIO0_25 IOPCTL_MUX(25, 1) /* PIO0_25 */ +#define FREQME_IN0_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define FREQME_IN1_PIO0_25 IOPCTL_MUX(25, 3) /* PIO0_25 */ +#define GPIO_PIO025_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT0_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT1_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT2_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT3_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT4_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT5_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT6_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define PINT_PINT7_PIO0_25 IOPCTL_MUX(25, 0) /* PIO0_25 */ +#define SECGPIO_SECPIO025_PIO0_25 IOPCTL_MUX(25, 8) /* PIO0_25 */ +#define SWD_TRACEDATA3_PIO0_25 IOPCTL_MUX(25, 6) /* PIO0_25 */ +#define ADC0_CH3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define CTIMER0_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER0_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER0_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER0_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER1_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER2_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER3_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE0_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE1_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE2_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define CTIMER4_CAPTURE3_PIO0_26 IOPCTL_MUX(26, 4) /* PIO0_26 */ +#define DMA0_TRIG0_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG10_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG11_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG12_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG13_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG14_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG15_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG16_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG17_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG18_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG19_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG1_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG20_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG21_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG22_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG23_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG24_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG25_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG26_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG27_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG28_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG29_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG2_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG30_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG31_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG32_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG4_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG5_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG6_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG7_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG8_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA0_TRIG9_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG0_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG10_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG11_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG12_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG13_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG14_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG15_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG16_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG17_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG18_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG19_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG1_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG20_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG21_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG22_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG23_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG24_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG25_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG26_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG27_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG28_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG29_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG2_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG30_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG31_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG32_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG4_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG5_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG6_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG7_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG8_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define DMA1_TRIG9_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define FC3_SSEL2_PIO0_26 IOPCTL_MUX(26, 1) /* PIO0_26 */ +#define GPIO_PIO026_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT0_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT1_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT2_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT3_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT4_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT5_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT6_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define PINT_PINT7_PIO0_26 IOPCTL_MUX(26, 0) /* PIO0_26 */ +#define SCT0_IN0_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN1_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN2_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN3_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN4_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN5_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_IN6_PIO0_26 IOPCTL_MUX(26, 2) /* PIO0_26 */ +#define SCT0_OUT6_PIO0_26 IOPCTL_MUX(26, 3) /* PIO0_26 */ +#define SECGPIO_SECPIO026_PIO0_26 IOPCTL_MUX(26, 8) /* PIO0_26 */ +#define ADC0_CH11_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define CTIMER0_MATCH3_PIO0_27 IOPCTL_MUX(27, 4) /* PIO0_27 */ +#define DMA0_TRIG0_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG10_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG11_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG12_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG13_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG14_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG15_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG16_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG17_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG18_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG19_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG1_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG20_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG21_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG22_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG23_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG24_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG25_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG26_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG27_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG28_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG29_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG2_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG30_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG31_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG32_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG3_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG4_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG5_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG6_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG7_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG8_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA0_TRIG9_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG0_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG10_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG11_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG12_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG13_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG14_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG15_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG16_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG17_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG18_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG19_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG1_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG20_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG21_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG22_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG23_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG24_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG25_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG26_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG27_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG28_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG29_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG2_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG30_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG31_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG32_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG3_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG4_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG5_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG6_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG7_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG8_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define DMA1_TRIG9_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define FC3_SSEL3_PIO0_27 IOPCTL_MUX(27, 1) /* PIO0_27 */ +#define GPIO_PIO027_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT0_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT1_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT2_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT3_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT4_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT5_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT6_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define PINT_PINT7_PIO0_27 IOPCTL_MUX(27, 0) /* PIO0_27 */ +#define SCT0_IN0_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN1_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN2_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN3_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN4_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN5_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_IN6_PIO0_27 IOPCTL_MUX(27, 2) /* PIO0_27 */ +#define SCT0_OUT7_PIO0_27 IOPCTL_MUX(27, 3) /* PIO0_27 */ +#define SECGPIO_SECPIO027_PIO0_27 IOPCTL_MUX(27, 8) /* PIO0_27 */ +#define CTIMER4_MATCH0_PIO0_28 IOPCTL_MUX(28, 4) /* PIO0_28 */ +#define DMA0_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA0_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG10_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG11_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG12_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG13_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG14_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG15_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG16_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG17_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG18_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG19_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG20_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG21_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG22_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG23_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG24_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG25_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG26_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG27_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG28_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG29_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG30_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG31_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG32_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG8_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define DMA1_TRIG9_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define FC4_SCK_PIO0_28 IOPCTL_MUX(28, 1) /* PIO0_28 */ +#define GPIO_PIO028_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define I2S_BRIDGE_CLK_OUT_PIO0_28 IOPCTL_MUX(28, 5) /* PIO0_28 */ +#define PINT_PINT0_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT1_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT2_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT3_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT4_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT5_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT6_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define PINT_PINT7_PIO0_28 IOPCTL_MUX(28, 0) /* PIO0_28 */ +#define SECGPIO_SECPIO028_PIO0_28 IOPCTL_MUX(28, 8) /* PIO0_28 */ +#define CTIMER4_MATCH1_PIO0_29 IOPCTL_MUX(29, 4) /* PIO0_29 */ +#define DMA0_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA0_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG10_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG11_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG12_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG13_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG14_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG15_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG16_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG17_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG18_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG19_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG20_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG21_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG22_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG23_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG24_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG25_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG26_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG27_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG28_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG29_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG30_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG31_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG32_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG8_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define DMA1_TRIG9_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define FC4_TXD_SCL_MISO_WS_PIO0_29 IOPCTL_MUX(29, 1) /* PIO0_29 */ +#define GPIO_PIO029_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define I2S_BRIDGE_WS_OUT_PIO0_29 IOPCTL_MUX(29, 5) /* PIO0_29 */ +#define PINT_PINT0_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT1_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT2_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT3_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT4_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT5_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT6_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define PINT_PINT7_PIO0_29 IOPCTL_MUX(29, 0) /* PIO0_29 */ +#define SECGPIO_SECPIO029_PIO0_29 IOPCTL_MUX(29, 8) /* PIO0_29 */ +#define CTIMER4_MATCH2_PIO0_30 IOPCTL_MUX(30, 4) /* PIO0_30 */ +#define DMA0_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA0_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG10_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG11_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG12_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG13_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG14_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG15_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG16_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG17_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG18_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG19_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG20_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG21_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG22_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG23_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG24_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG25_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG26_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG27_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG28_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG29_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG30_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG31_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG32_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG8_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define DMA1_TRIG9_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define FC4_RXD_SDA_MOSI_DATA_PIO0_30 IOPCTL_MUX(30, 1) /* PIO0_30 */ +#define GPIO_PIO030_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define I2S_BRIDGE_DATA_OUT_PIO0_30 IOPCTL_MUX(30, 5) /* PIO0_30 */ +#define PINT_PINT0_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT1_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT2_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT3_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT4_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT5_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT6_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define PINT_PINT7_PIO0_30 IOPCTL_MUX(30, 0) /* PIO0_30 */ +#define SECGPIO_SECPIO030_PIO0_30 IOPCTL_MUX(30, 8) /* PIO0_30 */ +#define CTIMER4_MATCH3_PIO0_31 IOPCTL_MUX(31, 4) /* PIO0_31 */ +#define DMA0_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA0_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG10_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG11_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG12_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG13_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG14_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG15_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG16_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG17_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG18_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG19_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG20_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG21_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG22_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG23_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG24_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG25_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG26_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG27_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG28_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG29_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG30_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG31_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG32_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG8_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define DMA1_TRIG9_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define FC3_SSEL2_PIO0_31 IOPCTL_MUX(31, 5) /* PIO0_31 */ +#define FC4_CTS_SDA_SSEL0_PIO0_31 IOPCTL_MUX(31, 1) /* PIO0_31 */ +#define GPIO_PIO031_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT0_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT1_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT2_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT3_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT4_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT5_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT6_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define PINT_PINT7_PIO0_31 IOPCTL_MUX(31, 0) /* PIO0_31 */ +#define SCT0_IN0_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN1_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN2_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN3_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN4_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN5_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_IN6_PIO0_31 IOPCTL_MUX(31, 2) /* PIO0_31 */ +#define SCT0_OUT6_PIO0_31 IOPCTL_MUX(31, 3) /* PIO0_31 */ +#define SECGPIO_SECPIO031_PIO0_31 IOPCTL_MUX(31, 8) /* PIO0_31 */ +#define CTIMER0_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER0_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER1_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER2_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER3_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE0_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE1_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE2_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define CTIMER4_CAPTURE3_PIO1_0 IOPCTL_MUX(32, 4) /* PIO1_0 */ +#define DMA0_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA0_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG11_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG12_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG13_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG14_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG15_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG16_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG17_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG18_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG19_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG20_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG21_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG22_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG23_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG24_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG25_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG26_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG27_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG28_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG29_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG30_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG31_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG32_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG8_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define DMA1_TRIG9_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define FC3_SSEL3_PIO1_0 IOPCTL_MUX(32, 5) /* PIO1_0 */ +#define FC4_RTS_SCL_SSEL1_PIO1_0 IOPCTL_MUX(32, 1) /* PIO1_0 */ +#define GPIO_PIO10_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT0_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT1_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT2_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT3_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT4_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT5_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT6_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define PINT_PINT7_PIO1_0 IOPCTL_MUX(32, 0) /* PIO1_0 */ +#define SCT0_IN0_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN1_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN2_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN3_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN4_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN5_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_IN6_PIO1_0 IOPCTL_MUX(32, 2) /* PIO1_0 */ +#define SCT0_OUT7_PIO1_0 IOPCTL_MUX(32, 3) /* PIO1_0 */ +#define CTIMER1_MATCH0_PIO1_1 IOPCTL_MUX(33, 4) /* PIO1_1 */ +#define DMA0_TRIG0_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG10_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG11_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG12_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG13_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG14_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG15_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG16_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG17_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG18_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG19_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG1_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG20_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG21_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG22_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG23_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG24_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG25_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG26_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG27_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG28_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG29_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG2_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG30_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG31_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG32_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG3_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG4_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG5_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG6_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG7_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG8_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA0_TRIG9_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG0_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG10_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG11_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG12_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG13_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG14_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG15_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG16_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG17_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG18_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG19_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG1_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG20_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG21_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG22_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG23_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG24_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG25_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG26_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG27_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG28_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG29_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG2_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG30_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG31_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG32_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG3_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG4_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG5_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG6_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG7_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG8_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define DMA1_TRIG9_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define FC4_SSEL2_PIO1_1 IOPCTL_MUX(33, 1) /* PIO1_1 */ +#define GPIO_PIO11_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT0_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT1_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT2_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT3_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT4_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT5_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT6_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define PINT_PINT7_PIO1_1 IOPCTL_MUX(33, 0) /* PIO1_1 */ +#define SCT0_IN0_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN1_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN2_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN3_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN4_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN5_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_IN6_PIO1_1 IOPCTL_MUX(33, 2) /* PIO1_1 */ +#define SCT0_OUT8_PIO1_1 IOPCTL_MUX(33, 3) /* PIO1_1 */ +#define CMP_IN3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define CTIMER1_MATCH1_PIO1_2 IOPCTL_MUX(34, 4) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG10_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG11_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG12_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG13_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG14_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG15_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG16_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG17_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG18_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG19_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG1_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG20_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG21_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG22_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG23_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG24_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG25_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG26_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG27_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG28_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG29_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG2_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG30_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG31_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG32_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG4_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG5_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG6_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG7_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG8_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA0_TRIG9_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG0_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG10_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG11_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG12_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG13_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG14_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG15_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG16_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG17_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG18_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG19_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG1_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG20_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG21_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG22_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG23_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG24_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG25_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG26_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG27_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG28_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG29_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG2_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG30_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG31_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG32_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG4_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG5_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG6_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG7_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG8_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define DMA1_TRIG9_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define FC4_SSEL3_PIO1_2 IOPCTL_MUX(34, 1) /* PIO1_2 */ +#define GPIO_PIO12_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT0_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT1_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT2_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT3_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT4_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT5_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT6_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define PINT_PINT7_PIO1_2 IOPCTL_MUX(34, 0) /* PIO1_2 */ +#define SCT0_IN0_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN1_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN2_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN3_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN4_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN5_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_IN6_PIO1_2 IOPCTL_MUX(34, 2) /* PIO1_2 */ +#define SCT0_OUT9_PIO1_2 IOPCTL_MUX(34, 3) /* PIO1_2 */ +#define DMA0_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG10_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG11_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG12_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG14_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG15_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG16_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG17_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG18_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG19_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG20_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG21_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG22_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG23_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG24_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG25_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG26_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG27_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG28_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG29_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG30_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG31_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG32_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG8_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA1_TRIG9_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define FC5_SCK_PIO1_3 IOPCTL_MUX(35, 1) /* PIO1_3 */ +#define GPIO_PIO13_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT0_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT1_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT2_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT3_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT4_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT5_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT6_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define PINT_PINT7_PIO1_3 IOPCTL_MUX(35, 0) /* PIO1_3 */ +#define DMA0_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG10_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG11_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG12_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG13_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG15_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG16_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG17_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG18_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG19_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG20_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG21_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG22_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG23_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG24_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG25_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG26_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG27_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG28_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG29_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG30_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG31_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG32_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG8_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA1_TRIG9_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define FC5_TXD_SCL_MISO_WS_PIO1_4 IOPCTL_MUX(36, 1) /* PIO1_4 */ +#define GPIO_PIO14_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT0_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT1_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT2_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT3_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT4_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT5_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT6_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define PINT_PINT7_PIO1_4 IOPCTL_MUX(36, 0) /* PIO1_4 */ +#define DMA0_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG10_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG11_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG12_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG13_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG14_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG16_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG17_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG18_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG19_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG20_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG21_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG22_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG23_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG24_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG25_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG26_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG27_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG28_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG29_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG30_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG31_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG32_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG8_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA1_TRIG9_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define FC5_RXD_SDA_MOSI_DATA_PIO1_5 IOPCTL_MUX(37, 1) /* PIO1_5 */ +#define GPIO_PIO15_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT0_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT1_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT2_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT3_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT4_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT5_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT6_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define PINT_PINT7_PIO1_5 IOPCTL_MUX(37, 0) /* PIO1_5 */ +#define DMA0_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA0_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG10_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG11_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG12_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG13_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG14_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG15_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG17_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG18_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG19_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG20_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG21_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG22_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG23_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG24_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG25_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG26_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG27_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG28_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG29_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG30_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG31_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG32_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG8_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define DMA1_TRIG9_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define FC4_SSEL2_PIO1_6 IOPCTL_MUX(38, 5) /* PIO1_6 */ +#define FC5_CTS_SDA_SSEL0_PIO1_6 IOPCTL_MUX(38, 1) /* PIO1_6 */ +#define GPIO_PIO16_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT0_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT1_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT2_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT3_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT4_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT5_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT6_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define PINT_PINT7_PIO1_6 IOPCTL_MUX(38, 0) /* PIO1_6 */ +#define SCT0_IN0_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN1_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN2_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN3_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN4_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN5_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_IN6_PIO1_6 IOPCTL_MUX(38, 2) /* PIO1_6 */ +#define SCT0_OUT4_PIO1_6 IOPCTL_MUX(38, 3) /* PIO1_6 */ +#define CTIMER0_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER0_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER1_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER2_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER3_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE0_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE1_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE2_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define CTIMER4_CAPTURE3_PIO1_7 IOPCTL_MUX(39, 4) /* PIO1_7 */ +#define DMA0_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA0_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG10_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG11_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG12_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG13_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG14_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG15_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG16_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG18_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG19_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG20_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG21_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG22_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG23_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG24_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG25_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG26_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG27_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG28_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG29_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG30_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG31_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG32_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG8_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define DMA1_TRIG9_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define FC4_SSEL3_PIO1_7 IOPCTL_MUX(39, 5) /* PIO1_7 */ +#define FC5_RTS_SCL_SSEL1_PIO1_7 IOPCTL_MUX(39, 1) /* PIO1_7 */ +#define GPIO_PIO17_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT0_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT1_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT2_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT3_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT4_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT5_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT6_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define PINT_PINT7_PIO1_7 IOPCTL_MUX(39, 0) /* PIO1_7 */ +#define SCT0_IN0_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN1_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN2_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN3_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN4_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN5_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_IN6_PIO1_7 IOPCTL_MUX(39, 2) /* PIO1_7 */ +#define SCT0_OUT5_PIO1_7 IOPCTL_MUX(39, 3) /* PIO1_7 */ +#define ADC0_CH4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define CTIMER0_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER0_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER0_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER0_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER1_MATCH2_PIO1_8 IOPCTL_MUX(40, 4) /* PIO1_8 */ +#define CTIMER2_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER2_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER2_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER2_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER3_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE0_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE1_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE2_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define CTIMER4_CAPTURE3_PIO1_8 IOPCTL_MUX(40, 3) /* PIO1_8 */ +#define DMA0_TRIG0_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG10_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG11_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG12_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG13_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG14_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG15_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG16_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG17_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG18_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG19_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG1_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG20_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG21_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG22_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG23_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG24_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG25_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG26_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG27_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG28_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG29_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG2_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG30_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG31_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG32_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG3_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG5_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG6_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG7_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG8_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA0_TRIG9_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG0_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG10_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG11_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG12_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG13_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG14_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG15_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG16_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG17_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG18_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG19_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG1_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG20_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG21_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG22_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG23_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG24_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG25_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG26_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG27_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG28_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG29_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG2_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG30_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG31_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG32_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG3_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG5_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG6_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG7_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG8_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define DMA1_TRIG9_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define FC5_SSEL2_PIO1_8 IOPCTL_MUX(40, 1) /* PIO1_8 */ +#define GPIO_PIO18_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT0_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT1_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT2_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT3_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT4_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT5_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT6_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define PINT_PINT7_PIO1_8 IOPCTL_MUX(40, 0) /* PIO1_8 */ +#define SCT0_IN0_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN1_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN2_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN3_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN4_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN5_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define SCT0_IN6_PIO1_8 IOPCTL_MUX(40, 2) /* PIO1_8 */ +#define ADC0_CH12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define CTIMER1_MATCH3_PIO1_9 IOPCTL_MUX(41, 4) /* PIO1_9 */ +#define DMA0_TRIG0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG10_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG11_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG13_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG14_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG15_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG16_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG17_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG18_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG20_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG21_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG22_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG23_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG24_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG25_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG26_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG27_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG28_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG29_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG30_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG31_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG32_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG8_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA0_TRIG9_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG10_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG11_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG12_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG13_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG14_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG15_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG16_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG17_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG18_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG20_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG21_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG22_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG23_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG24_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG25_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG26_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG27_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG28_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG29_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG30_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG31_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG32_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG8_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define DMA1_TRIG9_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define FC5_SSEL3_PIO1_9 IOPCTL_MUX(41, 1) /* PIO1_9 */ +#define GPIO_PIO19_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT0_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT1_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT2_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT3_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT4_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT5_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT6_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define PINT_PINT7_PIO1_9 IOPCTL_MUX(41, 0) /* PIO1_9 */ +#define SCT0_IN0_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN1_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN2_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN3_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN4_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN5_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define SCT0_IN6_PIO1_9 IOPCTL_MUX(41, 2) /* PIO1_9 */ +#define UTICK0_CAPTURE1_PIO1_9 IOPCTL_MUX(41, 3) /* PIO1_9 */ +#define CLKOUT_PIO1_10 IOPCTL_MUX(42, 7) /* PIO1_10 */ +#define CTIMER0_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER0_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER1_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER2_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER3_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE0_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE1_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE2_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define CTIMER4_CAPTURE3_PIO1_10 IOPCTL_MUX(42, 4) /* PIO1_10 */ +#define DMA0_TRIG0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG10_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG11_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG12_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG13_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG14_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG15_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG16_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG17_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG18_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG19_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG20_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG21_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG22_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG23_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG24_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG25_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG26_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG27_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG28_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG29_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG30_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG31_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG32_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG8_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA0_TRIG9_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG10_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG11_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG12_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG13_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG14_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG15_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG16_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG17_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG18_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG19_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG20_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG21_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG22_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG23_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG24_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG25_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG26_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG27_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG28_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG29_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG30_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG31_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG32_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG8_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define DMA1_TRIG9_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define FREQME_IN0_PIO1_10 IOPCTL_MUX(42, 3) /* PIO1_10 */ +#define FREQME_IN1_PIO1_10 IOPCTL_MUX(42, 3) /* PIO1_10 */ +#define GPIO_PIO110_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define MCLK_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define PINT_PINT0_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT1_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT2_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT3_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT4_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT5_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT6_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define PINT_PINT7_PIO1_10 IOPCTL_MUX(42, 0) /* PIO1_10 */ +#define SCT0_IN0_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN1_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN2_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN3_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN4_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN5_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define SCT0_IN6_PIO1_10 IOPCTL_MUX(42, 1) /* PIO1_10 */ +#define CTIMER2_MATCH0_PIO1_11 IOPCTL_MUX(43, 4) /* PIO1_11 */ +#define DMA0_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA0_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG10_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG11_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG12_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG13_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG14_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG15_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG16_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG17_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG18_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG19_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG20_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG21_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG22_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG23_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG24_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG25_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG26_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG27_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG28_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG29_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG30_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG31_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG32_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG8_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define DMA1_TRIG9_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define FLEXSPI0B_DATA0_PIO1_11 IOPCTL_MUX(43, 6) /* PIO1_11 */ +#define GPIO_PIO111_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define HS_SPI_SCK_PIO1_11 IOPCTL_MUX(43, 1) /* PIO1_11 */ +#define PINT_PINT0_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT1_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT2_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT3_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT4_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT5_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT6_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define PINT_PINT7_PIO1_11 IOPCTL_MUX(43, 0) /* PIO1_11 */ +#define CTIMER2_MATCH1_PIO1_12 IOPCTL_MUX(44, 4) /* PIO1_12 */ +#define DMA0_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA0_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG10_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG11_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG12_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG13_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG14_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG15_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG16_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG17_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG18_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG19_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG20_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG21_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG22_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG23_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG24_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG25_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG26_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG27_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG28_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG29_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG30_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG31_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG32_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG8_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define DMA1_TRIG9_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define FLEXSPI0B_DATA1_PIO1_12 IOPCTL_MUX(44, 6) /* PIO1_12 */ +#define GPIO_PIO112_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define HS_SPI_MISO_PIO1_12 IOPCTL_MUX(44, 1) /* PIO1_12 */ +#define PINT_PINT0_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT1_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT2_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT3_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT4_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT5_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT6_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define PINT_PINT7_PIO1_12 IOPCTL_MUX(44, 0) /* PIO1_12 */ +#define CTIMER2_MATCH2_PIO1_13 IOPCTL_MUX(45, 4) /* PIO1_13 */ +#define DMA0_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA0_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG10_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG11_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG12_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG13_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG14_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG15_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG16_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG17_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG18_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG19_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG20_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG21_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG22_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG23_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG24_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG25_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG26_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG27_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG28_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG29_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG30_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG31_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG32_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG8_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define DMA1_TRIG9_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define FLEXSPI0B_DATA2_PIO1_13 IOPCTL_MUX(45, 6) /* PIO1_13 */ +#define GPIO_PIO113_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define HS_SPI_MOSI_PIO1_13 IOPCTL_MUX(45, 1) /* PIO1_13 */ +#define PINT_PINT0_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT1_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT2_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT3_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT4_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT5_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT6_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define PINT_PINT7_PIO1_13 IOPCTL_MUX(45, 0) /* PIO1_13 */ +#define CTIMER2_MATCH3_PIO1_14 IOPCTL_MUX(46, 4) /* PIO1_14 */ +#define DMA0_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA0_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG10_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG11_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG12_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG13_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG14_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG15_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG16_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG17_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG18_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG19_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG20_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG21_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG22_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG23_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG24_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG25_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG26_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG27_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG28_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG29_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG30_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG31_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG32_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG8_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define DMA1_TRIG9_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define FLEXSPI0B_DATA3_PIO1_14 IOPCTL_MUX(46, 6) /* PIO1_14 */ +#define GPIO_PIO114_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define HS_SPI_SSEL0_PIO1_14 IOPCTL_MUX(46, 1) /* PIO1_14 */ +#define PINT_PINT0_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT1_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT2_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT3_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT4_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT5_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT6_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define PINT_PINT7_PIO1_14 IOPCTL_MUX(46, 0) /* PIO1_14 */ +#define CTIMER3_MATCH0_PIO1_15 IOPCTL_MUX(47, 4) /* PIO1_15 */ +#define DMA0_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA0_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG10_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG11_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG12_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG13_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG14_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG15_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG16_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG17_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG18_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG19_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG20_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG21_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG22_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG23_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG24_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG25_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG26_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG27_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG28_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG29_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG30_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG31_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG32_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG8_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define DMA1_TRIG9_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define GPIO_PIO115_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define HS_SPI_SSEL1_PIO1_15 IOPCTL_MUX(47, 1) /* PIO1_15 */ +#define PINT_PINT0_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT1_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT2_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT3_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT4_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT5_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT6_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define PINT_PINT7_PIO1_15 IOPCTL_MUX(47, 0) /* PIO1_15 */ +#define CTIMER3_MATCH1_PIO1_16 IOPCTL_MUX(48, 4) /* PIO1_16 */ +#define DMA0_TRIG0_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG10_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG11_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG12_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG13_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG14_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG15_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG16_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG17_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG18_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG19_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG1_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG20_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG21_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG22_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG23_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG24_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG25_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG26_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG27_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG28_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG29_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG2_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG30_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG31_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG32_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG3_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG4_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG5_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG6_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG7_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG8_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA0_TRIG9_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG0_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG10_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG11_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG12_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG13_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG14_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG15_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG16_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG17_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG18_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG19_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG1_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG20_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG21_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG22_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG23_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG24_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG25_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG26_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG27_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG28_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG29_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG2_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG30_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG31_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG32_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG3_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG4_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG5_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG6_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG7_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG8_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define DMA1_TRIG9_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define GPIO_PIO116_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define HS_SPI_SSEL2_PIO1_16 IOPCTL_MUX(48, 1) /* PIO1_16 */ +#define PINT_PINT0_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT1_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT2_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT3_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT4_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT5_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT6_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define PINT_PINT7_PIO1_16 IOPCTL_MUX(48, 0) /* PIO1_16 */ +#define SCT0_OUT8_PIO1_16 IOPCTL_MUX(48, 2) /* PIO1_16 */ +#define CTIMER3_MATCH2_PIO1_17 IOPCTL_MUX(49, 4) /* PIO1_17 */ +#define DMA0_TRIG0_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG10_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG11_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG12_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG13_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG14_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG15_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG16_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG17_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG18_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG19_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG1_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG20_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG21_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG22_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG23_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG24_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG25_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG26_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG27_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG28_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG29_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG2_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG30_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG31_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG32_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG3_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG4_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG5_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG6_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG7_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG8_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA0_TRIG9_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG0_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG10_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG11_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG12_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG13_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG14_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG15_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG16_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG17_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG18_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG19_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG1_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG20_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG21_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG22_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG23_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG24_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG25_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG26_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG27_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG28_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG29_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG2_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG30_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG31_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG32_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG3_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG4_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG5_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG6_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG7_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG8_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define DMA1_TRIG9_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define GPIO_PIO117_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define HS_SPI_SSEL3_PIO1_17 IOPCTL_MUX(49, 1) /* PIO1_17 */ +#define PINT_PINT0_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT1_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT2_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT3_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT4_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT5_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT6_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define PINT_PINT7_PIO1_17 IOPCTL_MUX(49, 0) /* PIO1_17 */ +#define SCT0_OUT9_PIO1_17 IOPCTL_MUX(49, 2) /* PIO1_17 */ +#define CTIMER3_MATCH3_PIO1_18 IOPCTL_MUX(50, 4) /* PIO1_18 */ +#define DMA0_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA0_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG10_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG11_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG12_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG13_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG14_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG15_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG16_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG17_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG18_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG19_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG20_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG21_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG22_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG23_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG24_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG25_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG26_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG27_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG28_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG29_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG30_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG31_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG32_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG8_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define DMA1_TRIG9_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define FLEXSPI0A_SCLK_PIO1_18 IOPCTL_MUX(50, 1) /* PIO1_18 */ +#define GPIO_PIO118_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT0_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT1_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT2_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT3_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT4_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT5_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT6_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define PINT_PINT7_PIO1_18 IOPCTL_MUX(50, 0) /* PIO1_18 */ +#define SCT0_IN0_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN1_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN2_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN3_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN4_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN5_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define SCT0_IN6_PIO1_18 IOPCTL_MUX(50, 2) /* PIO1_18 */ +#define CTIMER4_MATCH0_PIO1_19 IOPCTL_MUX(51, 4) /* PIO1_19 */ +#define DMA0_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA0_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG10_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG11_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG12_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG13_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG14_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG15_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG16_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG17_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG18_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG19_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG20_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG21_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG22_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG23_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG24_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG25_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG26_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG27_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG28_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG29_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG30_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG31_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG32_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG8_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define DMA1_TRIG9_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define FLEXSPI0A_SS0_N_PIO1_19 IOPCTL_MUX(51, 1) /* PIO1_19 */ +#define GPIO_PIO119_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT0_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT1_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT2_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT3_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT4_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT5_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT6_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define PINT_PINT7_PIO1_19 IOPCTL_MUX(51, 0) /* PIO1_19 */ +#define SCT0_OUT0_PIO1_19 IOPCTL_MUX(51, 2) /* PIO1_19 */ +#define CTIMER4_MATCH1_PIO1_20 IOPCTL_MUX(52, 4) /* PIO1_20 */ +#define DMA0_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA0_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG10_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG11_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG12_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG13_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG14_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG15_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG16_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG17_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG18_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG19_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG20_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG21_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG22_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG23_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG24_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG25_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG26_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG27_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG28_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG29_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG30_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG31_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG32_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG8_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define DMA1_TRIG9_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define FLEXSPI0A_DATA0_PIO1_20 IOPCTL_MUX(52, 1) /* PIO1_20 */ +#define GPIO_PIO120_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT0_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT1_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT2_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT3_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT4_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT5_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT6_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define PINT_PINT7_PIO1_20 IOPCTL_MUX(52, 0) /* PIO1_20 */ +#define SCT0_IN0_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN1_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN2_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN3_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN4_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN5_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define SCT0_IN6_PIO1_20 IOPCTL_MUX(52, 2) /* PIO1_20 */ +#define CTIMER4_MATCH2_PIO1_21 IOPCTL_MUX(53, 4) /* PIO1_21 */ +#define DMA0_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA0_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG10_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG11_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG12_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG13_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG14_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG15_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG16_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG17_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG18_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG19_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG20_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG21_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG22_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG23_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG24_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG25_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG26_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG27_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG28_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG29_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG30_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG31_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG32_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG8_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define DMA1_TRIG9_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define FLEXSPI0A_DATA1_PIO1_21 IOPCTL_MUX(53, 1) /* PIO1_21 */ +#define GPIO_PIO121_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT0_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT1_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT2_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT3_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT4_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT5_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT6_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define PINT_PINT7_PIO1_21 IOPCTL_MUX(53, 0) /* PIO1_21 */ +#define SCT0_OUT1_PIO1_21 IOPCTL_MUX(53, 2) /* PIO1_21 */ +#define CTIMER4_MATCH3_PIO1_22 IOPCTL_MUX(54, 4) /* PIO1_22 */ +#define DMA0_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA0_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG10_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG11_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG12_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG13_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG14_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG15_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG16_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG17_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG18_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG19_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG20_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG21_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG22_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG23_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG24_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG25_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG26_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG27_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG28_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG29_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG30_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG31_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG32_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG8_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define DMA1_TRIG9_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define FLEXSPI0A_DATA2_PIO1_22 IOPCTL_MUX(54, 1) /* PIO1_22 */ +#define GPIO_PIO122_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT0_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT1_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT2_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT3_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT4_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT5_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT6_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define PINT_PINT7_PIO1_22 IOPCTL_MUX(54, 0) /* PIO1_22 */ +#define SCT0_IN0_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN1_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN2_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN3_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN4_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN5_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define SCT0_IN6_PIO1_22 IOPCTL_MUX(54, 2) /* PIO1_22 */ +#define CTIMER0_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER0_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER1_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER2_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER3_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE0_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE1_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE2_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define CTIMER4_CAPTURE3_PIO1_23 IOPCTL_MUX(55, 4) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA0_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG10_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG11_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG12_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG13_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG14_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG15_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG16_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG17_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG18_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG19_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG20_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG21_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG22_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG23_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG24_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG25_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG26_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG27_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG28_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG29_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG30_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG31_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG32_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG8_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define DMA1_TRIG9_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define FLEXSPI0A_DATA3_PIO1_23 IOPCTL_MUX(55, 1) /* PIO1_23 */ +#define GPIO_PIO123_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT0_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT1_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT2_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT3_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT4_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT5_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT6_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define PINT_PINT7_PIO1_23 IOPCTL_MUX(55, 0) /* PIO1_23 */ +#define SCT0_OUT2_PIO1_23 IOPCTL_MUX(55, 2) /* PIO1_23 */ +#define DMA0_TRIG0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG10_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG11_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG12_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG13_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG14_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG15_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG16_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG17_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG18_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG19_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG20_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG21_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG22_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG23_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG24_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG25_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG26_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG27_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG28_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG29_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG30_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG31_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG32_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG8_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA0_TRIG9_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG10_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG11_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG12_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG13_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG14_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG15_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG16_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG17_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG18_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG19_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG20_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG21_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG22_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG23_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG24_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG25_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG26_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG27_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG28_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG29_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG30_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG31_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG32_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG8_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define DMA1_TRIG9_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define FLEXSPI0A_DATA4_PIO1_24 IOPCTL_MUX(56, 1) /* PIO1_24 */ +#define GPIO_PIO124_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT0_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT1_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT2_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT3_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT4_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT5_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT6_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define PINT_PINT7_PIO1_24 IOPCTL_MUX(56, 0) /* PIO1_24 */ +#define SCT0_IN0_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN1_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN2_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN3_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN4_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN5_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define SCT0_IN6_PIO1_24 IOPCTL_MUX(56, 2) /* PIO1_24 */ +#define DMA0_TRIG0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG10_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG11_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG12_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG13_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG14_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG15_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG16_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG17_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG18_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG19_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG20_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG21_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG22_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG23_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG24_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG25_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG26_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG27_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG28_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG29_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG30_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG31_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG32_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG8_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA0_TRIG9_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG10_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG11_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG12_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG13_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG14_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG15_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG16_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG17_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG18_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG19_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG20_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG21_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG22_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG23_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG24_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG25_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG26_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG27_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG28_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG29_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG30_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG31_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG32_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG8_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define DMA1_TRIG9_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define FLEXSPI0A_DATA5_PIO1_25 IOPCTL_MUX(57, 1) /* PIO1_25 */ +#define GPIO_PIO125_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT0_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT1_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT2_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT3_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT4_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT5_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT6_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define PINT_PINT7_PIO1_25 IOPCTL_MUX(57, 0) /* PIO1_25 */ +#define SCT0_OUT3_PIO1_25 IOPCTL_MUX(57, 2) /* PIO1_25 */ +#define DMA0_TRIG0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG10_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG11_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG12_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG13_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG14_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG15_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG16_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG17_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG18_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG19_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG20_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG21_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG22_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG23_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG24_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG25_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG26_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG27_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG28_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG29_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG30_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG31_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG32_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG8_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA0_TRIG9_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG10_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG11_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG12_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG13_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG14_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG15_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG16_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG17_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG18_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG19_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG20_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG21_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG22_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG23_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG24_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG25_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG26_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG27_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG28_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG29_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG30_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG31_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG32_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG8_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define DMA1_TRIG9_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define FLEXSPI0A_DATA6_PIO1_26 IOPCTL_MUX(58, 1) /* PIO1_26 */ +#define GPIO_PIO126_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT0_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT1_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT2_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT3_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT4_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT5_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT6_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define PINT_PINT7_PIO1_26 IOPCTL_MUX(58, 0) /* PIO1_26 */ +#define SCT0_IN0_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN1_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN2_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN3_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN4_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN5_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define SCT0_IN6_PIO1_26 IOPCTL_MUX(58, 2) /* PIO1_26 */ +#define DMA0_TRIG0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG10_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG11_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG12_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG13_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG14_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG15_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG16_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG17_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG18_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG19_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG20_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG21_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG22_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG23_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG24_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG25_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG26_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG27_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG28_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG29_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG30_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG31_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG32_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG8_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA0_TRIG9_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG10_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG11_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG12_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG13_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG14_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG15_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG16_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG17_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG18_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG19_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG20_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG21_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG22_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG23_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG24_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG25_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG26_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG27_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG28_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG29_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG30_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG31_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG32_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG8_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define DMA1_TRIG9_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define FLEXSPI0A_DATA7_PIO1_27 IOPCTL_MUX(59, 1) /* PIO1_27 */ +#define GPIO_PIO127_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT0_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT1_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT2_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT3_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT4_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT5_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT6_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define PINT_PINT7_PIO1_27 IOPCTL_MUX(59, 0) /* PIO1_27 */ +#define SCT0_OUT4_PIO1_27 IOPCTL_MUX(59, 2) /* PIO1_27 */ +#define DMA0_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA0_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG10_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG11_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG12_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG13_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG14_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG15_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG16_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG17_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG18_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG19_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG20_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG21_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG22_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG23_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG24_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG25_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG26_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG27_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG28_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG29_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG30_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG31_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG32_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG8_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define DMA1_TRIG9_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define FLEXSPI0A_DQS_PIO1_28 IOPCTL_MUX(60, 1) /* PIO1_28 */ +#define GPIO_PIO128_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT0_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT1_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT2_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT3_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT4_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT5_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT6_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define PINT_PINT7_PIO1_28 IOPCTL_MUX(60, 0) /* PIO1_28 */ +#define SCT0_IN0_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN1_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN2_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN3_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN4_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN5_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define SCT0_IN6_PIO1_28 IOPCTL_MUX(60, 2) /* PIO1_28 */ +#define CTIMER0_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER0_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER1_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER2_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER3_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE0_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE1_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define CTIMER4_CAPTURE3_PIO1_29 IOPCTL_MUX(61, 4) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG10_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG11_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG12_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG13_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG14_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG15_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG16_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG17_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG18_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG19_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG20_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG21_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG22_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG23_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG24_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG25_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG26_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG27_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG28_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG29_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG30_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG31_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG32_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG8_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA0_TRIG9_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG10_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG11_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG12_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG13_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG14_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG15_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG16_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG17_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG18_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG19_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG20_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG21_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG22_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG23_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG24_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG25_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG26_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG27_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG28_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG29_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG30_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG31_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG32_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG8_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define DMA1_TRIG9_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define FLEXSPI0A_SS1_N_PIO1_29 IOPCTL_MUX(61, 1) /* PIO1_29 */ +#define FLEXSPI0B_SCLK_PIO1_29 IOPCTL_MUX(61, 5) /* PIO1_29 */ +#define GPIO_PIO129_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT0_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT1_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT2_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT3_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT4_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT5_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT6_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define PINT_PINT7_PIO1_29 IOPCTL_MUX(61, 0) /* PIO1_29 */ +#define SCT0_OUT5_PIO1_29 IOPCTL_MUX(61, 2) /* PIO1_29 */ +#define UTICK0_CAPTURE2_PIO1_29 IOPCTL_MUX(61, 3) /* PIO1_29 */ +#define DMA0_TRIG0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG10_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG11_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG12_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG13_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG14_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG15_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG16_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG17_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG18_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG19_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG20_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG21_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG22_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG23_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG24_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG25_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG26_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG27_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG28_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG29_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG30_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG31_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG32_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG8_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA0_TRIG9_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG10_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG11_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG12_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG13_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG14_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG15_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG16_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG17_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG18_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG19_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG20_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG21_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG22_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG23_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG24_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG25_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG26_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG27_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG28_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG29_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG30_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG31_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG32_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG8_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define DMA1_TRIG9_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define GPIO_PIO130_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT0_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT1_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT2_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT3_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT4_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT5_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT6_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define PINT_PINT7_PIO1_30 IOPCTL_MUX(62, 0) /* PIO1_30 */ +#define SCT0_IN0_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN1_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN2_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN3_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN4_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN5_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SCT0_IN6_PIO1_30 IOPCTL_MUX(62, 2) /* PIO1_30 */ +#define SD0_CLK_PIO1_30 IOPCTL_MUX(62, 1) /* PIO1_30 */ +#define DMA0_TRIG0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG10_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG11_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG12_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG13_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG14_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG15_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG16_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG17_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG18_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG19_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG20_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG21_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG22_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG23_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG24_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG25_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG26_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG27_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG28_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG29_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG30_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG31_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG32_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG8_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA0_TRIG9_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG10_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG11_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG12_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG13_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG14_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG15_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG16_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG17_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG18_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG19_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG20_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG21_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG22_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG23_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG24_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG25_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG26_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG27_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG28_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG29_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG30_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG31_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG32_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG8_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define DMA1_TRIG9_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define GPIO_PIO131_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT0_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT1_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT2_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT3_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT4_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT5_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT6_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define PINT_PINT7_PIO1_31 IOPCTL_MUX(63, 0) /* PIO1_31 */ +#define SCT0_IN0_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN1_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN2_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN3_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN4_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN5_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SCT0_IN6_PIO1_31 IOPCTL_MUX(63, 2) /* PIO1_31 */ +#define SD0_CMD_PIO1_31 IOPCTL_MUX(63, 1) /* PIO1_31 */ +#define GPIO_PIO20_PIO2_0 IOPCTL_MUX(64, 0) /* PIO2_0 */ +#define SCT0_IN0_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN1_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN2_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN3_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN4_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN5_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define SCT0_IN6_PIO2_0 IOPCTL_MUX(64, 2) /* PIO2_0 */ +#define USDHC0_USDHC_DATA0_PIO2_0 IOPCTL_MUX(64, 1) /* PIO2_0 */ +#define GPIO_PIO21_PIO2_1 IOPCTL_MUX(65, 0) /* PIO2_1 */ +#define SCT0_IN0_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN1_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN2_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN3_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN4_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN5_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define SCT0_IN6_PIO2_1 IOPCTL_MUX(65, 2) /* PIO2_1 */ +#define USDHC0_USDHC_DATA1_PIO2_1 IOPCTL_MUX(65, 1) /* PIO2_1 */ +#define GPIO_PIO22_PIO2_2 IOPCTL_MUX(66, 0) /* PIO2_2 */ +#define SCT0_OUT0_PIO2_2 IOPCTL_MUX(66, 2) /* PIO2_2 */ +#define USDHC0_USDHC_DATA2_PIO2_2 IOPCTL_MUX(66, 1) /* PIO2_2 */ +#define GPIO_PIO23_PIO2_3 IOPCTL_MUX(67, 0) /* PIO2_3 */ +#define SCT0_OUT1_PIO2_3 IOPCTL_MUX(67, 2) /* PIO2_3 */ +#define USDHC0_USDHC_DATA3_PIO2_3 IOPCTL_MUX(67, 1) /* PIO2_3 */ +#define GPIO_PIO24_PIO2_4 IOPCTL_MUX(68, 0) /* PIO2_4 */ +#define SCT0_OUT2_PIO2_4 IOPCTL_MUX(68, 2) /* PIO2_4 */ +#define SD0_DS_PIO2_4 IOPCTL_MUX(68, 5) /* PIO2_4 */ +#define SD0_WR_PRT_PIO2_4 IOPCTL_MUX(68, 1) /* PIO2_4 */ +#define GPIO_PIO25_PIO2_5 IOPCTL_MUX(69, 0) /* PIO2_5 */ +#define SCT0_OUT3_PIO2_5 IOPCTL_MUX(69, 2) /* PIO2_5 */ +#define USDHC0_USDHC_DATA4_PIO2_5 IOPCTL_MUX(69, 1) /* PIO2_5 */ +#define CTIMER1_MATCH0_PIO2_6 IOPCTL_MUX(70, 4) /* PIO2_6 */ +#define GPIO_PIO26_PIO2_6 IOPCTL_MUX(70, 0) /* PIO2_6 */ +#define SCT0_IN0_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN1_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN2_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN3_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN4_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN5_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define SCT0_IN6_PIO2_6 IOPCTL_MUX(70, 2) /* PIO2_6 */ +#define USDHC0_USDHC_DATA5_PIO2_6 IOPCTL_MUX(70, 1) /* PIO2_6 */ +#define CTIMER1_MATCH1_PIO2_7 IOPCTL_MUX(71, 4) /* PIO2_7 */ +#define GPIO_PIO27_PIO2_7 IOPCTL_MUX(71, 0) /* PIO2_7 */ +#define SCT0_IN0_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN1_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN2_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN3_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN4_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN5_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define SCT0_IN6_PIO2_7 IOPCTL_MUX(71, 2) /* PIO2_7 */ +#define USDHC0_USDHC_DATA6_PIO2_7 IOPCTL_MUX(71, 1) /* PIO2_7 */ +#define CTIMER1_MATCH2_PIO2_8 IOPCTL_MUX(72, 4) /* PIO2_8 */ +#define GPIO_PIO28_PIO2_8 IOPCTL_MUX(72, 0) /* PIO2_8 */ +#define SCT0_OUT4_PIO2_8 IOPCTL_MUX(72, 2) /* PIO2_8 */ +#define USDHC0_USDHC_DATA7_PIO2_8 IOPCTL_MUX(72, 1) /* PIO2_8 */ +#define CTIMER1_MATCH3_PIO2_9 IOPCTL_MUX(73, 4) /* PIO2_9 */ +#define GPIO_PIO29_PIO2_9 IOPCTL_MUX(73, 0) /* PIO2_9 */ +#define SCT0_OUT5_PIO2_9 IOPCTL_MUX(73, 2) /* PIO2_9 */ +#define SD0_CARD_DET_N_PIO2_9 IOPCTL_MUX(73, 1) /* PIO2_9 */ +#define CTIMER2_MATCH0_PIO2_10 IOPCTL_MUX(74, 4) /* PIO2_10 */ +#define GPIO_PIO210_PIO2_10 IOPCTL_MUX(74, 0) /* PIO2_10 */ +#define SCT0_IN0_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN1_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN2_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN3_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN4_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN5_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SCT0_IN6_PIO2_10 IOPCTL_MUX(74, 2) /* PIO2_10 */ +#define SD0_RESET_N_PIO2_10 IOPCTL_MUX(74, 1) /* PIO2_10 */ +#define CTIMER2_MATCH1_PIO2_11 IOPCTL_MUX(75, 4) /* PIO2_11 */ +#define GPIO_PIO211_PIO2_11 IOPCTL_MUX(75, 0) /* PIO2_11 */ +#define SCT0_IN0_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN1_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN2_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN3_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN4_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN5_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SCT0_IN6_PIO2_11 IOPCTL_MUX(75, 2) /* PIO2_11 */ +#define SD0_VOLT_PIO2_11 IOPCTL_MUX(75, 1) /* PIO2_11 */ +#define CTIMER2_MATCH2_PIO2_12 IOPCTL_MUX(76, 4) /* PIO2_12 */ +#define GPIO_PIO212_PIO2_12 IOPCTL_MUX(76, 0) /* PIO2_12 */ +#define SCT0_OUT6_PIO2_12 IOPCTL_MUX(76, 2) /* PIO2_12 */ +#define CMP0_OUT_PIO2_13 IOPCTL_MUX(77, 7) /* PIO2_13 */ +#define CTIMER2_MATCH3_PIO2_13 IOPCTL_MUX(77, 4) /* PIO2_13 */ +#define GPIO_PIO213_PIO2_13 IOPCTL_MUX(77, 0) /* PIO2_13 */ +#define SCT0_OUT7_PIO2_13 IOPCTL_MUX(77, 2) /* PIO2_13 */ +#define CMP_IN1_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define CTIMER0_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER0_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER1_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER2_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER3_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE0_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE1_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE2_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define CTIMER4_CAPTURE3_PIO2_14 IOPCTL_MUX(78, 4) /* PIO2_14 */ +#define GPIO_PIO214_PIO2_14 IOPCTL_MUX(78, 0) /* PIO2_14 */ +#define SCT0_OUT8_PIO2_14 IOPCTL_MUX(78, 2) /* PIO2_14 */ +#define CLKIN_PIO2_15 IOPCTL_MUX(79, 7) /* PIO2_15 */ +#define CMP_IN4_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define GPIO_PIO215_PIO2_15 IOPCTL_MUX(79, 0) /* PIO2_15 */ +#define SCT0_OUT9_PIO2_15 IOPCTL_MUX(79, 2) /* PIO2_15 */ +#define DMIC0_CLK0_1_PIO2_16 IOPCTL_MUX(80, 1) /* PIO2_16 */ +#define GPIO_PIO216_PIO2_16 IOPCTL_MUX(80, 0) /* PIO2_16 */ +#define DMIC0_CLK2_3_PIO2_17 IOPCTL_MUX(81, 1) /* PIO2_17 */ +#define FLEXSPI0B_DATA4_PIO2_17 IOPCTL_MUX(81, 6) /* PIO2_17 */ +#define GPIO_PIO217_PIO2_17 IOPCTL_MUX(81, 0) /* PIO2_17 */ +#define DMIC0_CLK4_5_PIO2_18 IOPCTL_MUX(82, 1) /* PIO2_18 */ +#define FLEXSPI0B_DATA5_PIO2_18 IOPCTL_MUX(82, 6) /* PIO2_18 */ +#define GPIO_PIO218_PIO2_18 IOPCTL_MUX(82, 0) /* PIO2_18 */ +#define DMIC0_CLK6_7_PIO2_19 IOPCTL_MUX(83, 1) /* PIO2_19 */ +#define FLEXSPI0B_SS0_N_PIO2_19 IOPCTL_MUX(83, 6) /* PIO2_19 */ +#define GPIO_PIO219_PIO2_19 IOPCTL_MUX(83, 0) /* PIO2_19 */ +#define DMIC0_DATA0_1_PIO2_20 IOPCTL_MUX(84, 1) /* PIO2_20 */ +#define GPIO_PIO220_PIO2_20 IOPCTL_MUX(84, 0) /* PIO2_20 */ +#define CTIMER0_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER0_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER0_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER0_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER1_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER2_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER3_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE0_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE1_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE2_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define CTIMER4_CAPTURE3_PIO2_21 IOPCTL_MUX(85, 4) /* PIO2_21 */ +#define DMIC0_DATA2_3_PIO2_21 IOPCTL_MUX(85, 1) /* PIO2_21 */ +#define FLEXSPI0B_SS1_N_PIO2_21 IOPCTL_MUX(85, 6) /* PIO2_21 */ +#define GPIO_PIO221_PIO2_21 IOPCTL_MUX(85, 0) /* PIO2_21 */ +#define DMIC0_DATA4_5_PIO2_22 IOPCTL_MUX(86, 1) /* PIO2_22 */ +#define FLEXSPI0B_DATA6_PIO2_22 IOPCTL_MUX(86, 6) /* PIO2_22 */ +#define GPIO_PIO222_PIO2_22 IOPCTL_MUX(86, 0) /* PIO2_22 */ +#define DMIC0_DATA6_7_PIO2_23 IOPCTL_MUX(87, 1) /* PIO2_23 */ +#define FLEXSPI0B_DATA7_PIO2_23 IOPCTL_MUX(87, 6) /* PIO2_23 */ +#define GPIO_PIO223_PIO2_23 IOPCTL_MUX(87, 0) /* PIO2_23 */ +#define GPIO_INT_BMAT_PIO2_24 IOPCTL_MUX(88, 6) /* PIO2_24 */ +#define GPIO_PIO224_PIO2_24 IOPCTL_MUX(88, 0) /* PIO2_24 */ +#define SWO_PIO2_24 IOPCTL_MUX(88, 1) /* PIO2_24 */ +#define GPIO_PIO225_PIO2_25 IOPCTL_MUX(89, 0) /* PIO2_25 */ +#define SWCLK_PIO2_25 IOPCTL_MUX(89, 1) /* PIO2_25 */ +#define GPIO_PIO226_PIO2_26 IOPCTL_MUX(90, 0) /* PIO2_26 */ +#define SWDIO_PIO2_26 IOPCTL_MUX(90, 1) /* PIO2_26 */ +#define GPIO_PIO227_PIO2_27 IOPCTL_MUX(91, 0) /* PIO2_27 */ +#define USB1_OVERCURRENTN_PIO2_27 IOPCTL_MUX(91, 1) /* PIO2_27 */ +#define GPIO_PIO228_PIO2_28 IOPCTL_MUX(92, 0) /* PIO2_28 */ +#define USB1_PORTPWRN_PIO2_28 IOPCTL_MUX(92, 1) /* PIO2_28 */ +#define CLKOUT_PIO2_29 IOPCTL_MUX(93, 5) /* PIO2_29 */ +#define GPIO_PIO229_PIO2_29 IOPCTL_MUX(93, 0) /* PIO2_29 */ +#define I3C0_SCL_PIO2_29 IOPCTL_MUX(93, 1) /* PIO2_29 */ +#define SCT0_OUT0_PIO2_29 IOPCTL_MUX(93, 2) /* PIO2_29 */ +#define CLKIN_PIO2_30 IOPCTL_MUX(94, 5) /* PIO2_30 */ +#define CMP0_OUT_PIO2_30 IOPCTL_MUX(94, 7) /* PIO2_30 */ +#define GPIO_PIO230_PIO2_30 IOPCTL_MUX(94, 0) /* PIO2_30 */ +#define I3C0_SDA_PIO2_30 IOPCTL_MUX(94, 1) /* PIO2_30 */ +#define SCT0_OUT3_PIO2_30 IOPCTL_MUX(94, 2) /* PIO2_30 */ +#define CMP_IN2_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define CTIMER0_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER1_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER2_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER3_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE0_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE1_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE2_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define CTIMER4_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 4) /* PIO2_31 */ +#define GPIO_PIO231_PIO2_31 IOPCTL_MUX(95, 0) /* PIO2_31 */ +#define I3C0_PUR_PIO2_31 IOPCTL_MUX(95, 1) /* PIO2_31 */ +#define SCT0_OUT7_PIO2_31 IOPCTL_MUX(95, 2) /* PIO2_31 */ +#define SWO_PIO2_31 IOPCTL_MUX(95, 5) /* PIO2_31 */ +#define UTICK0_CAPTURE3_PIO2_31 IOPCTL_MUX(95, 3) /* PIO2_31 */ + +#endif diff --git a/dts/nxp/nxp_imx/rt/mimxrt1015caf4b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1015caf4b-pinctrl.dtsi new file mode 100644 index 000000000..50b0a7f76 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1015caf4b-pinctrl.dtsi @@ -0,0 +1,860 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1015CAF4B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpt1_compare1: IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 { + pinmux = <0x401f80bc 7 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_jtag_tms: IOMUXC_GPIO_AD_B0_00_JTAG_TMS { + pinmux = <0x401f80bc 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpt1_capture2: IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 { + pinmux = <0x401f80c0 7 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_jtag_tck: IOMUXC_GPIO_AD_B0_01_JTAG_TCK { + pinmux = <0x401f80c0 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpt1_capture1: IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 { + pinmux = <0x401f80c4 7 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_jtag_mod: IOMUXC_GPIO_AD_B0_02_JTAG_MOD { + pinmux = <0x401f80c4 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY { + pinmux = <0x401f80c8 7 0x401f8300 2 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_jtag_tdi: IOMUXC_GPIO_AD_B0_03_JTAG_TDI { + pinmux = <0x401f80c8 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_sai1_mclk: IOMUXC_GPIO_AD_B0_03_SAI1_MCLK { + pinmux = <0x401f80c8 3 0x401f8430 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 6 0x401f848c 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_wdog1_b: IOMUXC_GPIO_AD_B0_03_WDOG1_B { + pinmux = <0x401f80c8 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_ewm_out_b: IOMUXC_GPIO_AD_B0_04_EWM_OUT_B { + pinmux = <0x401f80cc 7 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_jtag_tdo: IOMUXC_GPIO_AD_B0_04_JTAG_TDO { + pinmux = <0x401f80cc 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR { + pinmux = <0x401f80cc 6 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_arm_nmi: IOMUXC_GPIO_AD_B0_05_ARM_NMI { + pinmux = <0x401f80d0 7 0x401f840c 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_jtag_trstb: IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB { + pinmux = <0x401f80d0 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usb_otg1_id: IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID { + pinmux = <0x401f80d0 6 0x401f82fc 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpuart1_tx: IOMUXC_GPIO_AD_B0_06_LPUART1_TX { + pinmux = <0x401f80d4 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_mqs_right: IOMUXC_GPIO_AD_B0_06_MQS_RIGHT { + pinmux = <0x401f80d4 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_pit_trigger0: IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER0 { + pinmux = <0x401f80d4 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_ref_32k_out: IOMUXC_GPIO_AD_B0_06_REF_32K_OUT { + pinmux = <0x401f80d4 6 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_lpuart1_rx: IOMUXC_GPIO_AD_B0_07_LPUART1_RX { + pinmux = <0x401f80d8 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_mqs_left: IOMUXC_GPIO_AD_B0_07_MQS_LEFT { + pinmux = <0x401f80d8 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_pit_trigger1: IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER1 { + pinmux = <0x401f80d8 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_ref_24m_out: IOMUXC_GPIO_AD_B0_07_REF_24M_OUT { + pinmux = <0x401f80d8 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_arm_cm7_txev: IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV { + pinmux = <0x401f80dc 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_kpp_col0: IOMUXC_GPIO_AD_B0_08_KPP_COL0 { + pinmux = <0x401f80dc 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B { + pinmux = <0x401f80dc 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_arm_cm7_rxev: IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV { + pinmux = <0x401f80e0 6 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_kpp_row0: IOMUXC_GPIO_AD_B0_09_KPP_ROW0 { + pinmux = <0x401f80e0 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B { + pinmux = <0x401f80e0 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_clk: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_CLK { + pinmux = <0x401f80e4 6 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_kpp_col1: IOMUXC_GPIO_AD_B0_10_KPP_COL1 { + pinmux = <0x401f80e4 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpspi1_sck: IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK { + pinmux = <0x401f80e4 1 0x401f83a0 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_arm_trace_swo: IOMUXC_GPIO_AD_B0_11_ARM_TRACE_SWO { + pinmux = <0x401f80e8 6 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_kpp_row1: IOMUXC_GPIO_AD_B0_11_KPP_ROW1 { + pinmux = <0x401f80e8 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpspi1_pcs0: IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 { + pinmux = <0x401f80e8 1 0x401f839c 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in0: IOMUXC_GPIO_AD_B0_12_ADC1_IN0 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_trace0: IOMUXC_GPIO_AD_B0_12_ARM_TRACE0 { + pinmux = <0x401f80ec 6 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_kpp_col2: IOMUXC_GPIO_AD_B0_12_KPP_COL2 { + pinmux = <0x401f80ec 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpspi1_sdo: IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO { + pinmux = <0x401f80ec 1 0x401f83a8 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart3_cts_b: IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B { + pinmux = <0x401f80ec 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_snvs_vio_5_ctl: IOMUXC_GPIO_AD_B0_12_SNVS_VIO_5_CTL { + pinmux = <0x401f80ec 7 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_arm_trace1: IOMUXC_GPIO_AD_B0_13_ARM_TRACE1 { + pinmux = <0x401f80f0 6 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_kpp_row2: IOMUXC_GPIO_AD_B0_13_KPP_ROW2 { + pinmux = <0x401f80f0 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpspi1_sdi: IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI { + pinmux = <0x401f80f0 1 0x401f83a4 1 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart3_rts_b: IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B { + pinmux = <0x401f80f0 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_snvs_vio_5_b: IOMUXC_GPIO_AD_B0_13_SNVS_VIO_5_B { + pinmux = <0x401f80f0 7 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in1: IOMUXC_GPIO_AD_B0_14_ADC1_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_arm_trace2: IOMUXC_GPIO_AD_B0_14_ARM_TRACE2 { + pinmux = <0x401f80f4 6 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_kpp_col3: IOMUXC_GPIO_AD_B0_14_KPP_COL3 { + pinmux = <0x401f80f4 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart3_tx: IOMUXC_GPIO_AD_B0_14_LPUART3_TX { + pinmux = <0x401f80f4 2 0x401f83dc 1 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_wdog1_any: IOMUXC_GPIO_AD_B0_14_WDOG1_ANY { + pinmux = <0x401f80f4 7 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in2: IOMUXC_GPIO_AD_B0_15_ADC1_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_arm_trace3: IOMUXC_GPIO_AD_B0_15_ARM_TRACE3 { + pinmux = <0x401f80f8 6 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_kpp_row3: IOMUXC_GPIO_AD_B0_15_KPP_ROW3 { + pinmux = <0x401f80f8 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart3_rx: IOMUXC_GPIO_AD_B0_15_LPUART3_RX { + pinmux = <0x401f80f8 2 0x401f83d8 1 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in10: IOMUXC_GPIO_AD_B1_10_ADC1_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio1_flexio05: IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8124 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexpwm1_pwma2: IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA2 { + pinmux = <0x401f8124 1 0x401f8330 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpt2_capture1: IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 { + pinmux = <0x401f8124 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart4_tx: IOMUXC_GPIO_AD_B1_10_LPUART4_TX { + pinmux = <0x401f8124 2 0x401f83e8 1 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR { + pinmux = <0x401f8124 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in11: IOMUXC_GPIO_AD_B1_11_ADC1_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio1_flexio04: IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8128 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexpwm1_pwmb2: IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB2 { + pinmux = <0x401f8128 1 0x401f8340 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpt2_compare1: IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 { + pinmux = <0x401f8128 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart4_rx: IOMUXC_GPIO_AD_B1_11_LPUART4_RX { + pinmux = <0x401f8128 2 0x401f83e4 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usb_otg1_id: IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID { + pinmux = <0x401f8128 0 0x401f82fc 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc1_in12: IOMUXC_GPIO_AD_B1_12_ADC1_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio1_flexio03: IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 { + pinmux = <0x401f812c 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexpwm1_pwma3: IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f812c 6 0x401f8334 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usb_otg1_oc: IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC { + pinmux = <0x401f812c 0 0x401f848c 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc1_in13: IOMUXC_GPIO_AD_B1_13_ADC1_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio1_flexio02: IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 { + pinmux = <0x401f8130 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8130 6 0x401f8344 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpi2c1_hreq: IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ { + pinmux = <0x401f8130 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc1_in14: IOMUXC_GPIO_AD_B1_14_ADC1_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio1_flexio01: IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8134 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpi2c1_scl: IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL { + pinmux = <0x401f8134 0 0x401f837c 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc1_in15: IOMUXC_GPIO_AD_B1_15_ADC1_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio1_flexio00: IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8138 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpi2c1_sda: IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA { + pinmux = <0x401f8138 0 0x401f8380 1 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio16: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 { + pinmux = <0x401f8024 4 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio2_io04: IOMUXC_GPIO_EMC_04_GPIO2_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_bclk: IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK { + pinmux = <0x401f8024 3 0x401f8464 1 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_spdif_out: IOMUXC_GPIO_EMC_04_SPDIF_OUT { + pinmux = <0x401f8024 2 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio17: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 { + pinmux = <0x401f8028 4 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio2_io05: IOMUXC_GPIO_EMC_05_GPIO2_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 3 0x401f8468 1 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_spdif_in: IOMUXC_GPIO_EMC_05_SPDIF_IN { + pinmux = <0x401f8028 2 0x401f8488 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio18: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 { + pinmux = <0x401f802c 4 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio2_io06: IOMUXC_GPIO_EMC_06_GPIO2_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_lpuart3_tx: IOMUXC_GPIO_EMC_06_LPUART3_TX { + pinmux = <0x401f802c 2 0x401f83dc 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_data: IOMUXC_GPIO_EMC_06_SAI2_TX_DATA { + pinmux = <0x401f802c 3 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio19: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 { + pinmux = <0x401f8030 4 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio2_io07: IOMUXC_GPIO_EMC_07_GPIO2_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_lpuart3_rx: IOMUXC_GPIO_EMC_07_LPUART3_RX { + pinmux = <0x401f8030 2 0x401f83d8 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_rx_sync: IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC { + pinmux = <0x401f8030 3 0x401f8460 1 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio20: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 { + pinmux = <0x401f8034 4 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio2_io08: IOMUXC_GPIO_EMC_08_GPIO2_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 3 0x401f845c 1 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio21: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 { + pinmux = <0x401f8038 4 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio2_io09: IOMUXC_GPIO_EMC_09_GPIO2_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_bclk: IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK { + pinmux = <0x401f8038 3 0x401f8458 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_in09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_IN09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio2_io16: IOMUXC_GPIO_EMC_16_GPIO2_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_mqs_right: IOMUXC_GPIO_EMC_16_MQS_RIGHT { + pinmux = <0x401f8054 2 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_sai2_mclk: IOMUXC_GPIO_EMC_16_SAI2_MCLK { + pinmux = <0x401f8054 3 0x401f8454 1 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_src_boot_mode0: IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE0 { + pinmux = <0x401f8054 6 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio2_io17: IOMUXC_GPIO_EMC_17_GPIO2_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_mqs_left: IOMUXC_GPIO_EMC_17_MQS_LEFT { + pinmux = <0x401f8058 2 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_sai3_mclk: IOMUXC_GPIO_EMC_17_SAI3_MCLK { + pinmux = <0x401f8058 3 0x401f846c 1 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_src_boot_mode1: IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE1 { + pinmux = <0x401f8058 6 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexio1_flexio22: IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 { + pinmux = <0x401f805c 4 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio2_io18: IOMUXC_GPIO_EMC_18_GPIO2_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpi2c2_sda: IOMUXC_GPIO_EMC_18_LPI2C2_SDA { + pinmux = <0x401f805c 2 0x401f8388 1 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_sai1_rx_sync: IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC { + pinmux = <0x401f805c 3 0x401f8448 2 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_src_bt_cfg0: IOMUXC_GPIO_EMC_18_SRC_BT_CFG0 { + pinmux = <0x401f805c 6 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_IN16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexio1_flexio23: IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 { + pinmux = <0x401f8060 4 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio2_io19: IOMUXC_GPIO_EMC_19_GPIO2_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpi2c2_scl: IOMUXC_GPIO_EMC_19_LPI2C2_SCL { + pinmux = <0x401f8060 2 0x401f8384 1 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_sai1_rx_bclk: IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK { + pinmux = <0x401f8060 3 0x401f8434 2 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_src_bt_cfg1: IOMUXC_GPIO_EMC_19_SRC_BT_CFG1 { + pinmux = <0x401f8060 6 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_in17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_IN17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexio1_flexio24: IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 { + pinmux = <0x401f8064 4 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm1_pwma3: IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA3 { + pinmux = <0x401f8064 1 0x401f8334 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio2_io20: IOMUXC_GPIO_EMC_20_GPIO2_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart2_cts_b: IOMUXC_GPIO_EMC_20_LPUART2_CTS_B { + pinmux = <0x401f8064 2 0x401f83cc 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_sai1_mclk: IOMUXC_GPIO_EMC_20_SAI1_MCLK { + pinmux = <0x401f8064 3 0x401f8430 3 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_src_bt_cfg2: IOMUXC_GPIO_EMC_20_SRC_BT_CFG2 { + pinmux = <0x401f8064 6 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexio1_flexio25: IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 { + pinmux = <0x401f8068 4 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB3 { + pinmux = <0x401f8068 1 0x401f8344 1 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio2_io21: IOMUXC_GPIO_EMC_21_GPIO2_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpuart2_rts_b: IOMUXC_GPIO_EMC_21_LPUART2_RTS_B { + pinmux = <0x401f8068 2 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_sai1_rx_data0: IOMUXC_GPIO_EMC_21_SAI1_RX_DATA0 { + pinmux = <0x401f8068 3 0x401f8438 2 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_src_bt_cfg3: IOMUXC_GPIO_EMC_21_SRC_BT_CFG3 { + pinmux = <0x401f8068 6 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexio1_flexio26: IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 { + pinmux = <0x401f806c 4 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm1_pwma2: IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA2 { + pinmux = <0x401f806c 1 0x401f8330 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio2_io22: IOMUXC_GPIO_EMC_22_GPIO2_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpuart2_tx: IOMUXC_GPIO_EMC_22_LPUART2_TX { + pinmux = <0x401f806c 2 0x401f83d4 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_sai1_tx_data3: IOMUXC_GPIO_EMC_22_SAI1_TX_DATA3 { + pinmux = <0x401f806c 3 0x401f843c 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_src_bt_cfg4: IOMUXC_GPIO_EMC_22_SRC_BT_CFG4 { + pinmux = <0x401f806c 6 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexio1_flexio27: IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 { + pinmux = <0x401f8070 4 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB2 { + pinmux = <0x401f8070 1 0x401f8340 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio2_io23: IOMUXC_GPIO_EMC_23_GPIO2_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart2_rx: IOMUXC_GPIO_EMC_23_LPUART2_RX { + pinmux = <0x401f8070 2 0x401f83d0 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_sai1_tx_data2: IOMUXC_GPIO_EMC_23_SAI1_TX_DATA2 { + pinmux = <0x401f8070 3 0x401f8440 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_src_bt_cfg5: IOMUXC_GPIO_EMC_23_SRC_BT_CFG5 { + pinmux = <0x401f8070 6 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexio1_flexio28: IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 { + pinmux = <0x401f8074 4 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwma1: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA1 { + pinmux = <0x401f8074 1 0x401f832c 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio2_io24: IOMUXC_GPIO_EMC_24_GPIO2_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_sai1_tx_data1: IOMUXC_GPIO_EMC_24_SAI1_TX_DATA1 { + pinmux = <0x401f8074 3 0x401f8444 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_src_bt_cfg6: IOMUXC_GPIO_EMC_24_SRC_BT_CFG6 { + pinmux = <0x401f8074 6 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexio1_flexio29: IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 { + pinmux = <0x401f8078 4 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB1 { + pinmux = <0x401f8078 1 0x401f833c 1 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio2_io25: IOMUXC_GPIO_EMC_25_GPIO2_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_sai1_tx_data0: IOMUXC_GPIO_EMC_25_SAI1_TX_DATA0 { + pinmux = <0x401f8078 3 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_src_bt_cfg7: IOMUXC_GPIO_EMC_25_SRC_BT_CFG7 { + pinmux = <0x401f8078 6 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio30: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 { + pinmux = <0x401f807c 4 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwma0: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA0 { + pinmux = <0x401f807c 1 0x401f8328 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio2_io26: IOMUXC_GPIO_EMC_26_GPIO2_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_sai1_tx_bclk: IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK { + pinmux = <0x401f807c 3 0x401f844c 2 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_src_bt_cfg8: IOMUXC_GPIO_EMC_26_SRC_BT_CFG8 { + pinmux = <0x401f807c 6 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio31: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 { + pinmux = <0x401f8080 4 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB0 { + pinmux = <0x401f8080 1 0x401f8338 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio2_io27: IOMUXC_GPIO_EMC_27_GPIO2_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_sai1_tx_sync: IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC { + pinmux = <0x401f8080 3 0x401f8450 2 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_src_bt_cfg9: IOMUXC_GPIO_EMC_27_SRC_BT_CFG9 { + pinmux = <0x401f8080 6 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io00: IOMUXC_GPIO_EMC_32_GPIO3_IO00 { + pinmux = <0x401f8094 5 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart4_tx: IOMUXC_GPIO_EMC_32_LPUART4_TX { + pinmux = <0x401f8094 2 0x401f83e8 2 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_qtimer1_timer0: IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 { + pinmux = <0x401f8094 1 0x401f8410 1 0x401f8208>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ref_24m_out: IOMUXC_GPIO_EMC_32_REF_24M_OUT { + pinmux = <0x401f8094 7 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_sai3_tx_data: IOMUXC_GPIO_EMC_32_SAI3_TX_DATA { + pinmux = <0x401f8094 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io01: IOMUXC_GPIO_EMC_33_GPIO3_IO01 { + pinmux = <0x401f8098 5 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpuart4_rx: IOMUXC_GPIO_EMC_33_LPUART4_RX { + pinmux = <0x401f8098 2 0x401f83e4 2 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_qtimer1_timer1: IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 { + pinmux = <0x401f8098 1 0x401f8414 1 0x401f820c>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_tx_bclk: IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK { + pinmux = <0x401f8098 3 0x401f847c 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io02: IOMUXC_GPIO_EMC_34_GPIO3_IO02 { + pinmux = <0x401f809c 5 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_qtimer1_timer2: IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 { + pinmux = <0x401f809c 1 0x401f8418 1 0x401f8210>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_tx_sync: IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC { + pinmux = <0x401f809c 3 0x401f8480 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io03: IOMUXC_GPIO_EMC_35_GPIO3_IO03 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_qtimer1_timer3: IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 { + pinmux = <0x401f80a0 1 0x401f841c 1 0x401f8214>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f8158 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io20: IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 { + pinmux = <0x401f8158 5 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B { + pinmux = <0x401f815c 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK { + pinmux = <0x401f815c 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io21: IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 { + pinmux = <0x401f815c 5 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_clko1: IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 { + pinmux = <0x401f8160 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data0: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA0 { + pinmux = <0x401f8160 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io22: IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 { + pinmux = <0x401f8160 5 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_clko2: IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 { + pinmux = <0x401f8164 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data2: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA2 { + pinmux = <0x401f8164 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io23: IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 { + pinmux = <0x401f8164 5 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_wait: IOMUXC_GPIO_SD_B1_04_CCM_WAIT { + pinmux = <0x401f8168 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ewm_out_b: IOMUXC_GPIO_SD_B1_04_EWM_OUT_B { + pinmux = <0x401f8168 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_data1: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA1 { + pinmux = <0x401f8168 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io24: IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 { + pinmux = <0x401f8168 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY { + pinmux = <0x401f816c 6 0x401f8300 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f816c 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f816c 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io25: IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 { + pinmux = <0x401f816c 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_mclk: IOMUXC_GPIO_SD_B1_05_SAI3_MCLK { + pinmux = <0x401f816c 3 0x401f846c 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_ccm_stop: IOMUXC_GPIO_SD_B1_06_CCM_STOP { + pinmux = <0x401f8170 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_data3: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA3 { + pinmux = <0x401f8170 1 0x401f8374 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io26: IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 { + pinmux = <0x401f8170 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f8170 4 0x401f83ac 2 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK { + pinmux = <0x401f8170 3 0x401f847c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f8174 1 0x401f8378 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io27: IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 { + pinmux = <0x401f8174 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f8174 4 0x401f83b0 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai3_tx_sync: IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC { + pinmux = <0x401f8174 3 0x401f8480 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f8178 1 0x401f8368 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io28: IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 { + pinmux = <0x401f8178 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f8178 4 0x401f83b8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai3_tx_data: IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA { + pinmux = <0x401f8178 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_ccm_ref_en_b: IOMUXC_GPIO_SD_B1_09_CCM_REF_EN_B { + pinmux = <0x401f817c 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data2: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA2 { + pinmux = <0x401f817c 1 0x401f8370 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io29: IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 { + pinmux = <0x401f817c 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f817c 4 0x401f83b4 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK { + pinmux = <0x401f817c 3 0x401f8470 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data1: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA1 { + pinmux = <0x401f8180 1 0x401f836c 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io30: IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 { + pinmux = <0x401f8180 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f8180 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_sai3_rx_sync: IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC { + pinmux = <0x401f8180 3 0x401f8478 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B { + pinmux = <0x401f8184 1 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io31: IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 { + pinmux = <0x401f8184 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8184 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_sai3_rx_data: IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA { + pinmux = <0x401f8184 3 0x401f8474 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1015daf5b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1015daf5b-pinctrl.dtsi new file mode 100644 index 000000000..110f37b7d --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1015daf5b-pinctrl.dtsi @@ -0,0 +1,860 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1015DAF5B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpt1_compare1: IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 { + pinmux = <0x401f80bc 7 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_jtag_tms: IOMUXC_GPIO_AD_B0_00_JTAG_TMS { + pinmux = <0x401f80bc 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpt1_capture2: IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 { + pinmux = <0x401f80c0 7 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_jtag_tck: IOMUXC_GPIO_AD_B0_01_JTAG_TCK { + pinmux = <0x401f80c0 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpt1_capture1: IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 { + pinmux = <0x401f80c4 7 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_jtag_mod: IOMUXC_GPIO_AD_B0_02_JTAG_MOD { + pinmux = <0x401f80c4 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY { + pinmux = <0x401f80c8 7 0x401f8300 2 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_jtag_tdi: IOMUXC_GPIO_AD_B0_03_JTAG_TDI { + pinmux = <0x401f80c8 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_sai1_mclk: IOMUXC_GPIO_AD_B0_03_SAI1_MCLK { + pinmux = <0x401f80c8 3 0x401f8430 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 6 0x401f848c 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_wdog1_b: IOMUXC_GPIO_AD_B0_03_WDOG1_B { + pinmux = <0x401f80c8 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_ewm_out_b: IOMUXC_GPIO_AD_B0_04_EWM_OUT_B { + pinmux = <0x401f80cc 7 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_jtag_tdo: IOMUXC_GPIO_AD_B0_04_JTAG_TDO { + pinmux = <0x401f80cc 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR { + pinmux = <0x401f80cc 6 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_arm_nmi: IOMUXC_GPIO_AD_B0_05_ARM_NMI { + pinmux = <0x401f80d0 7 0x401f840c 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_jtag_trstb: IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB { + pinmux = <0x401f80d0 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usb_otg1_id: IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID { + pinmux = <0x401f80d0 6 0x401f82fc 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpuart1_tx: IOMUXC_GPIO_AD_B0_06_LPUART1_TX { + pinmux = <0x401f80d4 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_mqs_right: IOMUXC_GPIO_AD_B0_06_MQS_RIGHT { + pinmux = <0x401f80d4 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_pit_trigger0: IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER0 { + pinmux = <0x401f80d4 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_ref_32k_out: IOMUXC_GPIO_AD_B0_06_REF_32K_OUT { + pinmux = <0x401f80d4 6 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_lpuart1_rx: IOMUXC_GPIO_AD_B0_07_LPUART1_RX { + pinmux = <0x401f80d8 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_mqs_left: IOMUXC_GPIO_AD_B0_07_MQS_LEFT { + pinmux = <0x401f80d8 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_pit_trigger1: IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER1 { + pinmux = <0x401f80d8 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_ref_24m_out: IOMUXC_GPIO_AD_B0_07_REF_24M_OUT { + pinmux = <0x401f80d8 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_arm_cm7_txev: IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV { + pinmux = <0x401f80dc 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_kpp_col0: IOMUXC_GPIO_AD_B0_08_KPP_COL0 { + pinmux = <0x401f80dc 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B { + pinmux = <0x401f80dc 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_arm_cm7_rxev: IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV { + pinmux = <0x401f80e0 6 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_kpp_row0: IOMUXC_GPIO_AD_B0_09_KPP_ROW0 { + pinmux = <0x401f80e0 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B { + pinmux = <0x401f80e0 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_clk: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_CLK { + pinmux = <0x401f80e4 6 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_kpp_col1: IOMUXC_GPIO_AD_B0_10_KPP_COL1 { + pinmux = <0x401f80e4 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpspi1_sck: IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK { + pinmux = <0x401f80e4 1 0x401f83a0 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_arm_trace_swo: IOMUXC_GPIO_AD_B0_11_ARM_TRACE_SWO { + pinmux = <0x401f80e8 6 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_kpp_row1: IOMUXC_GPIO_AD_B0_11_KPP_ROW1 { + pinmux = <0x401f80e8 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpspi1_pcs0: IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 { + pinmux = <0x401f80e8 1 0x401f839c 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in0: IOMUXC_GPIO_AD_B0_12_ADC1_IN0 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_trace0: IOMUXC_GPIO_AD_B0_12_ARM_TRACE0 { + pinmux = <0x401f80ec 6 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_kpp_col2: IOMUXC_GPIO_AD_B0_12_KPP_COL2 { + pinmux = <0x401f80ec 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpspi1_sdo: IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO { + pinmux = <0x401f80ec 1 0x401f83a8 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart3_cts_b: IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B { + pinmux = <0x401f80ec 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_snvs_vio_5_ctl: IOMUXC_GPIO_AD_B0_12_SNVS_VIO_5_CTL { + pinmux = <0x401f80ec 7 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_arm_trace1: IOMUXC_GPIO_AD_B0_13_ARM_TRACE1 { + pinmux = <0x401f80f0 6 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_kpp_row2: IOMUXC_GPIO_AD_B0_13_KPP_ROW2 { + pinmux = <0x401f80f0 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpspi1_sdi: IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI { + pinmux = <0x401f80f0 1 0x401f83a4 1 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart3_rts_b: IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B { + pinmux = <0x401f80f0 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_snvs_vio_5_b: IOMUXC_GPIO_AD_B0_13_SNVS_VIO_5_B { + pinmux = <0x401f80f0 7 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in1: IOMUXC_GPIO_AD_B0_14_ADC1_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_arm_trace2: IOMUXC_GPIO_AD_B0_14_ARM_TRACE2 { + pinmux = <0x401f80f4 6 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_kpp_col3: IOMUXC_GPIO_AD_B0_14_KPP_COL3 { + pinmux = <0x401f80f4 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart3_tx: IOMUXC_GPIO_AD_B0_14_LPUART3_TX { + pinmux = <0x401f80f4 2 0x401f83dc 1 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_wdog1_any: IOMUXC_GPIO_AD_B0_14_WDOG1_ANY { + pinmux = <0x401f80f4 7 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in2: IOMUXC_GPIO_AD_B0_15_ADC1_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_arm_trace3: IOMUXC_GPIO_AD_B0_15_ARM_TRACE3 { + pinmux = <0x401f80f8 6 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_kpp_row3: IOMUXC_GPIO_AD_B0_15_KPP_ROW3 { + pinmux = <0x401f80f8 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart3_rx: IOMUXC_GPIO_AD_B0_15_LPUART3_RX { + pinmux = <0x401f80f8 2 0x401f83d8 1 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in10: IOMUXC_GPIO_AD_B1_10_ADC1_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio1_flexio05: IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8124 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexpwm1_pwma2: IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA2 { + pinmux = <0x401f8124 1 0x401f8330 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpt2_capture1: IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 { + pinmux = <0x401f8124 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart4_tx: IOMUXC_GPIO_AD_B1_10_LPUART4_TX { + pinmux = <0x401f8124 2 0x401f83e8 1 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR { + pinmux = <0x401f8124 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in11: IOMUXC_GPIO_AD_B1_11_ADC1_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio1_flexio04: IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8128 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexpwm1_pwmb2: IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB2 { + pinmux = <0x401f8128 1 0x401f8340 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpt2_compare1: IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 { + pinmux = <0x401f8128 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart4_rx: IOMUXC_GPIO_AD_B1_11_LPUART4_RX { + pinmux = <0x401f8128 2 0x401f83e4 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usb_otg1_id: IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID { + pinmux = <0x401f8128 0 0x401f82fc 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc1_in12: IOMUXC_GPIO_AD_B1_12_ADC1_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio1_flexio03: IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 { + pinmux = <0x401f812c 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexpwm1_pwma3: IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f812c 6 0x401f8334 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usb_otg1_oc: IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC { + pinmux = <0x401f812c 0 0x401f848c 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc1_in13: IOMUXC_GPIO_AD_B1_13_ADC1_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio1_flexio02: IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 { + pinmux = <0x401f8130 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8130 6 0x401f8344 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpi2c1_hreq: IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ { + pinmux = <0x401f8130 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc1_in14: IOMUXC_GPIO_AD_B1_14_ADC1_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio1_flexio01: IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8134 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpi2c1_scl: IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL { + pinmux = <0x401f8134 0 0x401f837c 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc1_in15: IOMUXC_GPIO_AD_B1_15_ADC1_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio1_flexio00: IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8138 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpi2c1_sda: IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA { + pinmux = <0x401f8138 0 0x401f8380 1 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio16: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 { + pinmux = <0x401f8024 4 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio2_io04: IOMUXC_GPIO_EMC_04_GPIO2_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_bclk: IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK { + pinmux = <0x401f8024 3 0x401f8464 1 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_spdif_out: IOMUXC_GPIO_EMC_04_SPDIF_OUT { + pinmux = <0x401f8024 2 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio17: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 { + pinmux = <0x401f8028 4 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio2_io05: IOMUXC_GPIO_EMC_05_GPIO2_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 3 0x401f8468 1 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_spdif_in: IOMUXC_GPIO_EMC_05_SPDIF_IN { + pinmux = <0x401f8028 2 0x401f8488 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio18: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 { + pinmux = <0x401f802c 4 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio2_io06: IOMUXC_GPIO_EMC_06_GPIO2_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_lpuart3_tx: IOMUXC_GPIO_EMC_06_LPUART3_TX { + pinmux = <0x401f802c 2 0x401f83dc 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_data: IOMUXC_GPIO_EMC_06_SAI2_TX_DATA { + pinmux = <0x401f802c 3 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio19: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 { + pinmux = <0x401f8030 4 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio2_io07: IOMUXC_GPIO_EMC_07_GPIO2_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_lpuart3_rx: IOMUXC_GPIO_EMC_07_LPUART3_RX { + pinmux = <0x401f8030 2 0x401f83d8 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_rx_sync: IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC { + pinmux = <0x401f8030 3 0x401f8460 1 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio20: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 { + pinmux = <0x401f8034 4 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio2_io08: IOMUXC_GPIO_EMC_08_GPIO2_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 3 0x401f845c 1 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio21: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 { + pinmux = <0x401f8038 4 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio2_io09: IOMUXC_GPIO_EMC_09_GPIO2_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_bclk: IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK { + pinmux = <0x401f8038 3 0x401f8458 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_in09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_IN09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio2_io16: IOMUXC_GPIO_EMC_16_GPIO2_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_mqs_right: IOMUXC_GPIO_EMC_16_MQS_RIGHT { + pinmux = <0x401f8054 2 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_sai2_mclk: IOMUXC_GPIO_EMC_16_SAI2_MCLK { + pinmux = <0x401f8054 3 0x401f8454 1 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_src_boot_mode0: IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE0 { + pinmux = <0x401f8054 6 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio2_io17: IOMUXC_GPIO_EMC_17_GPIO2_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_mqs_left: IOMUXC_GPIO_EMC_17_MQS_LEFT { + pinmux = <0x401f8058 2 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_sai3_mclk: IOMUXC_GPIO_EMC_17_SAI3_MCLK { + pinmux = <0x401f8058 3 0x401f846c 1 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_src_boot_mode1: IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE1 { + pinmux = <0x401f8058 6 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexio1_flexio22: IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 { + pinmux = <0x401f805c 4 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio2_io18: IOMUXC_GPIO_EMC_18_GPIO2_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpi2c2_sda: IOMUXC_GPIO_EMC_18_LPI2C2_SDA { + pinmux = <0x401f805c 2 0x401f8388 1 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_sai1_rx_sync: IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC { + pinmux = <0x401f805c 3 0x401f8448 2 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_src_bt_cfg0: IOMUXC_GPIO_EMC_18_SRC_BT_CFG0 { + pinmux = <0x401f805c 6 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_IN16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexio1_flexio23: IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 { + pinmux = <0x401f8060 4 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio2_io19: IOMUXC_GPIO_EMC_19_GPIO2_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpi2c2_scl: IOMUXC_GPIO_EMC_19_LPI2C2_SCL { + pinmux = <0x401f8060 2 0x401f8384 1 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_sai1_rx_bclk: IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK { + pinmux = <0x401f8060 3 0x401f8434 2 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_src_bt_cfg1: IOMUXC_GPIO_EMC_19_SRC_BT_CFG1 { + pinmux = <0x401f8060 6 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_in17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_IN17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexio1_flexio24: IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 { + pinmux = <0x401f8064 4 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm1_pwma3: IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA3 { + pinmux = <0x401f8064 1 0x401f8334 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio2_io20: IOMUXC_GPIO_EMC_20_GPIO2_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart2_cts_b: IOMUXC_GPIO_EMC_20_LPUART2_CTS_B { + pinmux = <0x401f8064 2 0x401f83cc 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_sai1_mclk: IOMUXC_GPIO_EMC_20_SAI1_MCLK { + pinmux = <0x401f8064 3 0x401f8430 3 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_src_bt_cfg2: IOMUXC_GPIO_EMC_20_SRC_BT_CFG2 { + pinmux = <0x401f8064 6 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexio1_flexio25: IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 { + pinmux = <0x401f8068 4 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB3 { + pinmux = <0x401f8068 1 0x401f8344 1 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio2_io21: IOMUXC_GPIO_EMC_21_GPIO2_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpuart2_rts_b: IOMUXC_GPIO_EMC_21_LPUART2_RTS_B { + pinmux = <0x401f8068 2 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_sai1_rx_data0: IOMUXC_GPIO_EMC_21_SAI1_RX_DATA0 { + pinmux = <0x401f8068 3 0x401f8438 2 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_src_bt_cfg3: IOMUXC_GPIO_EMC_21_SRC_BT_CFG3 { + pinmux = <0x401f8068 6 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexio1_flexio26: IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 { + pinmux = <0x401f806c 4 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm1_pwma2: IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA2 { + pinmux = <0x401f806c 1 0x401f8330 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio2_io22: IOMUXC_GPIO_EMC_22_GPIO2_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpuart2_tx: IOMUXC_GPIO_EMC_22_LPUART2_TX { + pinmux = <0x401f806c 2 0x401f83d4 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_sai1_tx_data3: IOMUXC_GPIO_EMC_22_SAI1_TX_DATA3 { + pinmux = <0x401f806c 3 0x401f843c 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_src_bt_cfg4: IOMUXC_GPIO_EMC_22_SRC_BT_CFG4 { + pinmux = <0x401f806c 6 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexio1_flexio27: IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 { + pinmux = <0x401f8070 4 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB2 { + pinmux = <0x401f8070 1 0x401f8340 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio2_io23: IOMUXC_GPIO_EMC_23_GPIO2_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart2_rx: IOMUXC_GPIO_EMC_23_LPUART2_RX { + pinmux = <0x401f8070 2 0x401f83d0 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_sai1_tx_data2: IOMUXC_GPIO_EMC_23_SAI1_TX_DATA2 { + pinmux = <0x401f8070 3 0x401f8440 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_src_bt_cfg5: IOMUXC_GPIO_EMC_23_SRC_BT_CFG5 { + pinmux = <0x401f8070 6 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexio1_flexio28: IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 { + pinmux = <0x401f8074 4 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwma1: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA1 { + pinmux = <0x401f8074 1 0x401f832c 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio2_io24: IOMUXC_GPIO_EMC_24_GPIO2_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_sai1_tx_data1: IOMUXC_GPIO_EMC_24_SAI1_TX_DATA1 { + pinmux = <0x401f8074 3 0x401f8444 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_src_bt_cfg6: IOMUXC_GPIO_EMC_24_SRC_BT_CFG6 { + pinmux = <0x401f8074 6 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexio1_flexio29: IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 { + pinmux = <0x401f8078 4 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB1 { + pinmux = <0x401f8078 1 0x401f833c 1 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio2_io25: IOMUXC_GPIO_EMC_25_GPIO2_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_sai1_tx_data0: IOMUXC_GPIO_EMC_25_SAI1_TX_DATA0 { + pinmux = <0x401f8078 3 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_src_bt_cfg7: IOMUXC_GPIO_EMC_25_SRC_BT_CFG7 { + pinmux = <0x401f8078 6 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio30: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 { + pinmux = <0x401f807c 4 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwma0: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA0 { + pinmux = <0x401f807c 1 0x401f8328 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio2_io26: IOMUXC_GPIO_EMC_26_GPIO2_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_sai1_tx_bclk: IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK { + pinmux = <0x401f807c 3 0x401f844c 2 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_src_bt_cfg8: IOMUXC_GPIO_EMC_26_SRC_BT_CFG8 { + pinmux = <0x401f807c 6 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio31: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 { + pinmux = <0x401f8080 4 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB0 { + pinmux = <0x401f8080 1 0x401f8338 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio2_io27: IOMUXC_GPIO_EMC_27_GPIO2_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_sai1_tx_sync: IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC { + pinmux = <0x401f8080 3 0x401f8450 2 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_src_bt_cfg9: IOMUXC_GPIO_EMC_27_SRC_BT_CFG9 { + pinmux = <0x401f8080 6 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io00: IOMUXC_GPIO_EMC_32_GPIO3_IO00 { + pinmux = <0x401f8094 5 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart4_tx: IOMUXC_GPIO_EMC_32_LPUART4_TX { + pinmux = <0x401f8094 2 0x401f83e8 2 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_qtimer1_timer0: IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 { + pinmux = <0x401f8094 1 0x401f8410 1 0x401f8208>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ref_24m_out: IOMUXC_GPIO_EMC_32_REF_24M_OUT { + pinmux = <0x401f8094 7 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_sai3_tx_data: IOMUXC_GPIO_EMC_32_SAI3_TX_DATA { + pinmux = <0x401f8094 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io01: IOMUXC_GPIO_EMC_33_GPIO3_IO01 { + pinmux = <0x401f8098 5 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpuart4_rx: IOMUXC_GPIO_EMC_33_LPUART4_RX { + pinmux = <0x401f8098 2 0x401f83e4 2 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_qtimer1_timer1: IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 { + pinmux = <0x401f8098 1 0x401f8414 1 0x401f820c>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_tx_bclk: IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK { + pinmux = <0x401f8098 3 0x401f847c 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io02: IOMUXC_GPIO_EMC_34_GPIO3_IO02 { + pinmux = <0x401f809c 5 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_qtimer1_timer2: IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 { + pinmux = <0x401f809c 1 0x401f8418 1 0x401f8210>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_tx_sync: IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC { + pinmux = <0x401f809c 3 0x401f8480 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io03: IOMUXC_GPIO_EMC_35_GPIO3_IO03 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_qtimer1_timer3: IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 { + pinmux = <0x401f80a0 1 0x401f841c 1 0x401f8214>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f8158 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io20: IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 { + pinmux = <0x401f8158 5 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B { + pinmux = <0x401f815c 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK { + pinmux = <0x401f815c 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io21: IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 { + pinmux = <0x401f815c 5 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_clko1: IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 { + pinmux = <0x401f8160 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data0: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA0 { + pinmux = <0x401f8160 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io22: IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 { + pinmux = <0x401f8160 5 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_clko2: IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 { + pinmux = <0x401f8164 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data2: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA2 { + pinmux = <0x401f8164 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io23: IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 { + pinmux = <0x401f8164 5 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_wait: IOMUXC_GPIO_SD_B1_04_CCM_WAIT { + pinmux = <0x401f8168 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ewm_out_b: IOMUXC_GPIO_SD_B1_04_EWM_OUT_B { + pinmux = <0x401f8168 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_data1: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA1 { + pinmux = <0x401f8168 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io24: IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 { + pinmux = <0x401f8168 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY { + pinmux = <0x401f816c 6 0x401f8300 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f816c 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f816c 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io25: IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 { + pinmux = <0x401f816c 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_mclk: IOMUXC_GPIO_SD_B1_05_SAI3_MCLK { + pinmux = <0x401f816c 3 0x401f846c 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_ccm_stop: IOMUXC_GPIO_SD_B1_06_CCM_STOP { + pinmux = <0x401f8170 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_data3: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA3 { + pinmux = <0x401f8170 1 0x401f8374 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io26: IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 { + pinmux = <0x401f8170 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f8170 4 0x401f83ac 2 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK { + pinmux = <0x401f8170 3 0x401f847c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f8174 1 0x401f8378 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io27: IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 { + pinmux = <0x401f8174 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f8174 4 0x401f83b0 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai3_tx_sync: IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC { + pinmux = <0x401f8174 3 0x401f8480 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f8178 1 0x401f8368 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io28: IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 { + pinmux = <0x401f8178 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f8178 4 0x401f83b8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai3_tx_data: IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA { + pinmux = <0x401f8178 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_ccm_ref_en_b: IOMUXC_GPIO_SD_B1_09_CCM_REF_EN_B { + pinmux = <0x401f817c 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data2: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA2 { + pinmux = <0x401f817c 1 0x401f8370 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io29: IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 { + pinmux = <0x401f817c 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f817c 4 0x401f83b4 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK { + pinmux = <0x401f817c 3 0x401f8470 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data1: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA1 { + pinmux = <0x401f8180 1 0x401f836c 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io30: IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 { + pinmux = <0x401f8180 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f8180 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_sai3_rx_sync: IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC { + pinmux = <0x401f8180 3 0x401f8478 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B { + pinmux = <0x401f8184 1 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io31: IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 { + pinmux = <0x401f8184 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8184 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_sai3_rx_data: IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA { + pinmux = <0x401f8184 3 0x401f8474 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1021caf4b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1021caf4b-pinctrl.dtsi new file mode 100644 index 000000000..6d94345be --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1021caf4b-pinctrl.dtsi @@ -0,0 +1,1284 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1021CAF4B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpt1_compare1: IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 { + pinmux = <0x401f80bc 7 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_jtag_tms: IOMUXC_GPIO_AD_B0_00_JTAG_TMS { + pinmux = <0x401f80bc 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpt1_capture2: IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 { + pinmux = <0x401f80c0 7 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_jtag_tck: IOMUXC_GPIO_AD_B0_01_JTAG_TCK { + pinmux = <0x401f80c0 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpt1_capture1: IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 { + pinmux = <0x401f80c4 7 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_jtag_mod: IOMUXC_GPIO_AD_B0_02_JTAG_MOD { + pinmux = <0x401f80c4 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY { + pinmux = <0x401f80c8 7 0x401f8300 2 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_jtag_tdi: IOMUXC_GPIO_AD_B0_03_JTAG_TDI { + pinmux = <0x401f80c8 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_sai1_mclk: IOMUXC_GPIO_AD_B0_03_SAI1_MCLK { + pinmux = <0x401f80c8 3 0x401f8430 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 6 0x401f848c 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc1_wp: IOMUXC_GPIO_AD_B0_03_USDHC1_WP { + pinmux = <0x401f80c8 4 0x401f8494 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B { + pinmux = <0x401f80c8 1 0x401f8498 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_wdog1_b: IOMUXC_GPIO_AD_B0_03_WDOG1_B { + pinmux = <0x401f80c8 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_mdio: IOMUXC_GPIO_AD_B0_04_ENET_MDIO { + pinmux = <0x401f80cc 4 0x401f8308 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_ewm_out_b: IOMUXC_GPIO_AD_B0_04_EWM_OUT_B { + pinmux = <0x401f80cc 7 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_flexcan1_tx: IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX { + pinmux = <0x401f80cc 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_jtag_tdo: IOMUXC_GPIO_AD_B0_04_JTAG_TDO { + pinmux = <0x401f80cc 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_qtimer2_timer0: IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 { + pinmux = <0x401f80cc 3 0x401f8420 1 0x401f8240>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR { + pinmux = <0x401f80cc 6 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usdhc1_wp: IOMUXC_GPIO_AD_B0_04_USDHC1_WP { + pinmux = <0x401f80cc 2 0x401f8494 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_arm_nmi: IOMUXC_GPIO_AD_B0_05_ARM_NMI { + pinmux = <0x401f80d0 7 0x401f840c 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_mdc: IOMUXC_GPIO_AD_B0_05_ENET_MDC { + pinmux = <0x401f80d0 4 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_flexcan1_rx: IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX { + pinmux = <0x401f80d0 1 0x401f8320 2 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_jtag_trstb: IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB { + pinmux = <0x401f80d0 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_qtimer2_timer1: IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 { + pinmux = <0x401f80d0 3 0x401f8424 1 0x401f8244>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usb_otg1_id: IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID { + pinmux = <0x401f80d0 6 0x401f82fc 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usdhc1_cd_b: IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B { + pinmux = <0x401f80d0 2 0x401f8490 1 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA3 { + pinmux = <0x401f80d4 4 0x401f8354 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpuart1_tx: IOMUXC_GPIO_AD_B0_06_LPUART1_TX { + pinmux = <0x401f80d4 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_mqs_right: IOMUXC_GPIO_AD_B0_06_MQS_RIGHT { + pinmux = <0x401f80d4 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_pit_trigger0: IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER0 { + pinmux = <0x401f80d4 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_qtimer2_timer2: IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 { + pinmux = <0x401f80d4 3 0x401f8428 1 0x401f8248>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_ref_32k_out: IOMUXC_GPIO_AD_B0_06_REF_32K_OUT { + pinmux = <0x401f80d4 6 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_flexpwm2_pwmb3: IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB3 { + pinmux = <0x401f80d8 4 0x401f8364 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_lpuart1_rx: IOMUXC_GPIO_AD_B0_07_LPUART1_RX { + pinmux = <0x401f80d8 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_mqs_left: IOMUXC_GPIO_AD_B0_07_MQS_LEFT { + pinmux = <0x401f80d8 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_pit_trigger1: IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER1 { + pinmux = <0x401f80d8 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_qtimer2_timer3: IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 { + pinmux = <0x401f80d8 3 0x401f842c 1 0x401f824c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_ref_24m_out: IOMUXC_GPIO_AD_B0_07_REF_24M_OUT { + pinmux = <0x401f80d8 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_acmp1_in4: IOMUXC_GPIO_AD_B0_08_ACMP1_IN4 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_arm_cm7_txev: IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV { + pinmux = <0x401f80dc 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_ref_clk: IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK { + pinmux = <0x401f80dc 4 0x401f8304 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_tx_clk: IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK { + pinmux = <0x401f80dc 0 0x401f831c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_kpp_col0: IOMUXC_GPIO_AD_B0_08_KPP_COL0 { + pinmux = <0x401f80dc 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpi2c3_scl: IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL { + pinmux = <0x401f80dc 1 0x401f838c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B { + pinmux = <0x401f80dc 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_acmp2_in4: IOMUXC_GPIO_AD_B0_09_ACMP2_IN4 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_arm_cm7_rxev: IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV { + pinmux = <0x401f80e0 6 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data1: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA1 { + pinmux = <0x401f80e0 0 0x401f8310 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_kpp_row0: IOMUXC_GPIO_AD_B0_09_KPP_ROW0 { + pinmux = <0x401f80e0 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpi2c3_sda: IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA { + pinmux = <0x401f80e0 1 0x401f8390 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B { + pinmux = <0x401f80e0 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_acmp3_in4: IOMUXC_GPIO_AD_B0_10_ACMP3_IN4 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_clk: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_CLK { + pinmux = <0x401f80e4 6 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_rx_data0: IOMUXC_GPIO_AD_B0_10_ENET_RX_DATA0 { + pinmux = <0x401f80e4 0 0x401f830c 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f80e4 4 0x401f8350 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_kpp_col1: IOMUXC_GPIO_AD_B0_10_KPP_COL1 { + pinmux = <0x401f80e4 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpspi1_sck: IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK { + pinmux = <0x401f80e4 1 0x401f83a0 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpuart5_tx: IOMUXC_GPIO_AD_B0_10_LPUART5_TX { + pinmux = <0x401f80e4 2 0x401f83f0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_acmp4_in4: IOMUXC_GPIO_AD_B0_11_ACMP4_IN4 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_arm_trace_swo: IOMUXC_GPIO_AD_B0_11_ARM_TRACE_SWO { + pinmux = <0x401f80e8 6 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_rx_en: IOMUXC_GPIO_AD_B0_11_ENET_RX_EN { + pinmux = <0x401f80e8 0 0x401f8314 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f80e8 4 0x401f8360 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_kpp_row1: IOMUXC_GPIO_AD_B0_11_KPP_ROW1 { + pinmux = <0x401f80e8 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpspi1_pcs0: IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 { + pinmux = <0x401f80e8 1 0x401f839c 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpuart5_rx: IOMUXC_GPIO_AD_B0_11_LPUART5_RX { + pinmux = <0x401f80e8 2 0x401f83ec 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in0: IOMUXC_GPIO_AD_B0_12_ADC1_IN0 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_trace0: IOMUXC_GPIO_AD_B0_12_ARM_TRACE0 { + pinmux = <0x401f80ec 6 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_rx_er: IOMUXC_GPIO_AD_B0_12_ENET_RX_ER { + pinmux = <0x401f80ec 0 0x401f8318 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm2_pwma1: IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA1 { + pinmux = <0x401f80ec 4 0x401f834c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_kpp_col2: IOMUXC_GPIO_AD_B0_12_KPP_COL2 { + pinmux = <0x401f80ec 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpspi1_sdo: IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO { + pinmux = <0x401f80ec 1 0x401f83a8 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart3_cts_b: IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B { + pinmux = <0x401f80ec 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_snvs_vio_5_ctl: IOMUXC_GPIO_AD_B0_12_SNVS_VIO_5_CTL { + pinmux = <0x401f80ec 7 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc2_in0: IOMUXC_GPIO_AD_B0_13_ADC2_IN0 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_tx_en: IOMUXC_GPIO_AD_B0_13_ENET_TX_EN { + pinmux = <0x401f80f0 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm2_pwmb1: IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB1 { + pinmux = <0x401f80f0 4 0x401f835c 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_kpp_row2: IOMUXC_GPIO_AD_B0_13_KPP_ROW2 { + pinmux = <0x401f80f0 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpspi1_sdi: IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI { + pinmux = <0x401f80f0 1 0x401f83a4 1 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart3_rts_b: IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B { + pinmux = <0x401f80f0 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_snvs_vio_5_b: IOMUXC_GPIO_AD_B0_13_SNVS_VIO_5_B { + pinmux = <0x401f80f0 7 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp1_in0: IOMUXC_GPIO_AD_B0_14_ACMP1_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in0: IOMUXC_GPIO_AD_B0_14_ACMP2_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp3_in0: IOMUXC_GPIO_AD_B0_14_ACMP3_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp4_in0: IOMUXC_GPIO_AD_B0_14_ACMP4_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in1: IOMUXC_GPIO_AD_B0_14_ADC1_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc2_in1: IOMUXC_GPIO_AD_B0_14_ADC2_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_tx_data0: IOMUXC_GPIO_AD_B0_14_ENET_TX_DATA0 { + pinmux = <0x401f80f4 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexpwm2_pwma0: IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA0 { + pinmux = <0x401f80f4 4 0x401f8348 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_kpp_col3: IOMUXC_GPIO_AD_B0_14_KPP_COL3 { + pinmux = <0x401f80f4 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart3_tx: IOMUXC_GPIO_AD_B0_14_LPUART3_TX { + pinmux = <0x401f80f4 2 0x401f83dc 1 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_wdog1_any: IOMUXC_GPIO_AD_B0_14_WDOG1_ANY { + pinmux = <0x401f80f4 7 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp1_in1: IOMUXC_GPIO_AD_B0_15_ACMP1_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp2_in1: IOMUXC_GPIO_AD_B0_15_ACMP2_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in1: IOMUXC_GPIO_AD_B0_15_ACMP3_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp4_in1: IOMUXC_GPIO_AD_B0_15_ACMP4_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in2: IOMUXC_GPIO_AD_B0_15_ADC1_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc2_in2: IOMUXC_GPIO_AD_B0_15_ADC2_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_tx_data1: IOMUXC_GPIO_AD_B0_15_ENET_TX_DATA1 { + pinmux = <0x401f80f8 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 1 0x401f8324 2 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexpwm2_pwmb0: IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB0 { + pinmux = <0x401f80f8 4 0x401f8358 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_kpp_row3: IOMUXC_GPIO_AD_B0_15_KPP_ROW3 { + pinmux = <0x401f80f8 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart3_rx: IOMUXC_GPIO_AD_B0_15_LPUART3_RX { + pinmux = <0x401f80f8 2 0x401f83d8 1 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_acmp3_in5: IOMUXC_GPIO_AD_B1_10_ACMP3_IN5 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in10: IOMUXC_GPIO_AD_B1_10_ADC1_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc2_in10: IOMUXC_GPIO_AD_B1_10_ADC2_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio1_flexio05: IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8124 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexpwm1_pwma2: IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA2 { + pinmux = <0x401f8124 1 0x401f8330 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpt2_capture1: IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 { + pinmux = <0x401f8124 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart4_tx: IOMUXC_GPIO_AD_B1_10_LPUART4_TX { + pinmux = <0x401f8124 2 0x401f83e8 1 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR { + pinmux = <0x401f8124 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B { + pinmux = <0x401f8124 3 0x401f8490 2 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_acmp4_in5: IOMUXC_GPIO_AD_B1_11_ACMP4_IN5 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in11: IOMUXC_GPIO_AD_B1_11_ADC1_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc2_in11: IOMUXC_GPIO_AD_B1_11_ADC2_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio1_flexio04: IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8128 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexpwm1_pwmb2: IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB2 { + pinmux = <0x401f8128 1 0x401f8340 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpt2_compare1: IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 { + pinmux = <0x401f8128 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart4_rx: IOMUXC_GPIO_AD_B1_11_LPUART4_RX { + pinmux = <0x401f8128 2 0x401f83e4 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usb_otg1_id: IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID { + pinmux = <0x401f8128 0 0x401f82fc 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usdhc1_wp: IOMUXC_GPIO_AD_B1_11_USDHC1_WP { + pinmux = <0x401f8128 3 0x401f8494 3 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_in6: IOMUXC_GPIO_AD_B1_12_ACMP1_IN6 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_out: IOMUXC_GPIO_AD_B1_12_ACMP1_OUT { + pinmux = <0x401f812c 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc1_in12: IOMUXC_GPIO_AD_B1_12_ADC1_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc2_in12: IOMUXC_GPIO_AD_B1_12_ADC2_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio1_flexio03: IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 { + pinmux = <0x401f812c 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexpwm1_pwma3: IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f812c 6 0x401f8334 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_lpspi3_sck: IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK { + pinmux = <0x401f812c 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usb_otg1_oc: IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC { + pinmux = <0x401f812c 0 0x401f848c 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B { + pinmux = <0x401f812c 3 0x401f8498 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_in6: IOMUXC_GPIO_AD_B1_13_ACMP2_IN6 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_out: IOMUXC_GPIO_AD_B1_13_ACMP2_OUT { + pinmux = <0x401f8130 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc1_in13: IOMUXC_GPIO_AD_B1_13_ADC1_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc2_in13: IOMUXC_GPIO_AD_B1_13_ADC2_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio1_flexio02: IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 { + pinmux = <0x401f8130 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8130 6 0x401f8344 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpi2c1_hreq: IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ { + pinmux = <0x401f8130 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpspi3_pcs0: IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 { + pinmux = <0x401f8130 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_usdhc2_wp: IOMUXC_GPIO_AD_B1_13_USDHC2_WP { + pinmux = <0x401f8130 3 0x401f849c 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_in6: IOMUXC_GPIO_AD_B1_14_ACMP3_IN6 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_out: IOMUXC_GPIO_AD_B1_14_ACMP3_OUT { + pinmux = <0x401f8134 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc1_in14: IOMUXC_GPIO_AD_B1_14_ADC1_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc2_in14: IOMUXC_GPIO_AD_B1_14_ADC2_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f8134 3 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio1_flexio01: IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8134 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpi2c1_scl: IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL { + pinmux = <0x401f8134 0 0x401f837c 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpspi3_sdo: IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO { + pinmux = <0x401f8134 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_in6: IOMUXC_GPIO_AD_B1_15_ACMP4_IN6 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_out: IOMUXC_GPIO_AD_B1_15_ACMP4_OUT { + pinmux = <0x401f8138 1 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc1_in15: IOMUXC_GPIO_AD_B1_15_ADC1_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc2_in15: IOMUXC_GPIO_AD_B1_15_ADC2_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f8138 3 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio1_flexio00: IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8138 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpi2c1_sda: IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA { + pinmux = <0x401f8138 0 0x401f8380 1 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpspi3_sdi: IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI { + pinmux = <0x401f8138 2 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio16: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 { + pinmux = <0x401f8024 4 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio2_io04: IOMUXC_GPIO_EMC_04_GPIO2_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_bclk: IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK { + pinmux = <0x401f8024 3 0x401f8464 1 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_spdif_out: IOMUXC_GPIO_EMC_04_SPDIF_OUT { + pinmux = <0x401f8024 2 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio17: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 { + pinmux = <0x401f8028 4 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio2_io05: IOMUXC_GPIO_EMC_05_GPIO2_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 3 0x401f8468 1 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_spdif_in: IOMUXC_GPIO_EMC_05_SPDIF_IN { + pinmux = <0x401f8028 2 0x401f8488 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio18: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 { + pinmux = <0x401f802c 4 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio2_io06: IOMUXC_GPIO_EMC_06_GPIO2_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_lpuart3_tx: IOMUXC_GPIO_EMC_06_LPUART3_TX { + pinmux = <0x401f802c 2 0x401f83dc 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_data: IOMUXC_GPIO_EMC_06_SAI2_TX_DATA { + pinmux = <0x401f802c 3 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio19: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 { + pinmux = <0x401f8030 4 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio2_io07: IOMUXC_GPIO_EMC_07_GPIO2_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_lpuart3_rx: IOMUXC_GPIO_EMC_07_LPUART3_RX { + pinmux = <0x401f8030 2 0x401f83d8 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_rx_sync: IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC { + pinmux = <0x401f8030 3 0x401f8460 1 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexcan2_tx: IOMUXC_GPIO_EMC_08_FLEXCAN2_TX { + pinmux = <0x401f8034 2 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio20: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 { + pinmux = <0x401f8034 4 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio2_io08: IOMUXC_GPIO_EMC_08_GPIO2_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 3 0x401f845c 1 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_rx: IOMUXC_GPIO_EMC_09_FLEXCAN2_RX { + pinmux = <0x401f8038 2 0x401f8324 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio21: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 { + pinmux = <0x401f8038 4 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio2_io09: IOMUXC_GPIO_EMC_09_GPIO2_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_bclk: IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK { + pinmux = <0x401f8038 3 0x401f8458 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_we: IOMUXC_GPIO_EMC_09_SEMC_WE { + pinmux = <0x401f8038 0 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_in09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_IN09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio2_io16: IOMUXC_GPIO_EMC_16_GPIO2_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_mqs_right: IOMUXC_GPIO_EMC_16_MQS_RIGHT { + pinmux = <0x401f8054 2 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_sai2_mclk: IOMUXC_GPIO_EMC_16_SAI2_MCLK { + pinmux = <0x401f8054 3 0x401f8454 1 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr00: IOMUXC_GPIO_EMC_16_SEMC_ADDR00 { + pinmux = <0x401f8054 0 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_src_boot_mode0: IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE0 { + pinmux = <0x401f8054 6 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio2_io17: IOMUXC_GPIO_EMC_17_GPIO2_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_mqs_left: IOMUXC_GPIO_EMC_17_MQS_LEFT { + pinmux = <0x401f8058 2 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_sai3_mclk: IOMUXC_GPIO_EMC_17_SAI3_MCLK { + pinmux = <0x401f8058 3 0x401f846c 1 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr01: IOMUXC_GPIO_EMC_17_SEMC_ADDR01 { + pinmux = <0x401f8058 0 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_src_boot_mode1: IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE1 { + pinmux = <0x401f8058 6 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexio1_flexio22: IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 { + pinmux = <0x401f805c 4 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio2_io18: IOMUXC_GPIO_EMC_18_GPIO2_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpi2c2_sda: IOMUXC_GPIO_EMC_18_LPI2C2_SDA { + pinmux = <0x401f805c 2 0x401f8388 1 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_sai1_rx_sync: IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC { + pinmux = <0x401f805c 3 0x401f8448 2 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr02: IOMUXC_GPIO_EMC_18_SEMC_ADDR02 { + pinmux = <0x401f805c 0 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_src_bt_cfg0: IOMUXC_GPIO_EMC_18_SRC_BT_CFG0 { + pinmux = <0x401f805c 6 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_IN16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexio1_flexio23: IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 { + pinmux = <0x401f8060 4 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio2_io19: IOMUXC_GPIO_EMC_19_GPIO2_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpi2c2_scl: IOMUXC_GPIO_EMC_19_LPI2C2_SCL { + pinmux = <0x401f8060 2 0x401f8384 1 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_sai1_rx_bclk: IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK { + pinmux = <0x401f8060 3 0x401f8434 2 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr03: IOMUXC_GPIO_EMC_19_SEMC_ADDR03 { + pinmux = <0x401f8060 0 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_src_bt_cfg1: IOMUXC_GPIO_EMC_19_SRC_BT_CFG1 { + pinmux = <0x401f8060 6 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_in17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_IN17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexio1_flexio24: IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 { + pinmux = <0x401f8064 4 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm1_pwma3: IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA3 { + pinmux = <0x401f8064 1 0x401f8334 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio2_io20: IOMUXC_GPIO_EMC_20_GPIO2_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart2_cts_b: IOMUXC_GPIO_EMC_20_LPUART2_CTS_B { + pinmux = <0x401f8064 2 0x401f83cc 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_sai1_mclk: IOMUXC_GPIO_EMC_20_SAI1_MCLK { + pinmux = <0x401f8064 3 0x401f8430 3 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr04: IOMUXC_GPIO_EMC_20_SEMC_ADDR04 { + pinmux = <0x401f8064 0 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_src_bt_cfg2: IOMUXC_GPIO_EMC_20_SRC_BT_CFG2 { + pinmux = <0x401f8064 6 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexio1_flexio25: IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 { + pinmux = <0x401f8068 4 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB3 { + pinmux = <0x401f8068 1 0x401f8344 1 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio2_io21: IOMUXC_GPIO_EMC_21_GPIO2_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpuart2_rts_b: IOMUXC_GPIO_EMC_21_LPUART2_RTS_B { + pinmux = <0x401f8068 2 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_sai1_rx_data0: IOMUXC_GPIO_EMC_21_SAI1_RX_DATA0 { + pinmux = <0x401f8068 3 0x401f8438 2 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_addr05: IOMUXC_GPIO_EMC_21_SEMC_ADDR05 { + pinmux = <0x401f8068 0 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_src_bt_cfg3: IOMUXC_GPIO_EMC_21_SRC_BT_CFG3 { + pinmux = <0x401f8068 6 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexio1_flexio26: IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 { + pinmux = <0x401f806c 4 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm1_pwma2: IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA2 { + pinmux = <0x401f806c 1 0x401f8330 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio2_io22: IOMUXC_GPIO_EMC_22_GPIO2_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpuart2_tx: IOMUXC_GPIO_EMC_22_LPUART2_TX { + pinmux = <0x401f806c 2 0x401f83d4 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_sai1_tx_data3: IOMUXC_GPIO_EMC_22_SAI1_TX_DATA3 { + pinmux = <0x401f806c 3 0x401f843c 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_addr06: IOMUXC_GPIO_EMC_22_SEMC_ADDR06 { + pinmux = <0x401f806c 0 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_src_bt_cfg4: IOMUXC_GPIO_EMC_22_SRC_BT_CFG4 { + pinmux = <0x401f806c 6 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexio1_flexio27: IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 { + pinmux = <0x401f8070 4 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB2 { + pinmux = <0x401f8070 1 0x401f8340 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio2_io23: IOMUXC_GPIO_EMC_23_GPIO2_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart2_rx: IOMUXC_GPIO_EMC_23_LPUART2_RX { + pinmux = <0x401f8070 2 0x401f83d0 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_sai1_tx_data2: IOMUXC_GPIO_EMC_23_SAI1_TX_DATA2 { + pinmux = <0x401f8070 3 0x401f8440 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr07: IOMUXC_GPIO_EMC_23_SEMC_ADDR07 { + pinmux = <0x401f8070 0 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_src_bt_cfg5: IOMUXC_GPIO_EMC_23_SRC_BT_CFG5 { + pinmux = <0x401f8070 6 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexio1_flexio28: IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 { + pinmux = <0x401f8074 4 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwma1: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA1 { + pinmux = <0x401f8074 1 0x401f832c 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio2_io24: IOMUXC_GPIO_EMC_24_GPIO2_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart8_cts_b: IOMUXC_GPIO_EMC_24_LPUART8_CTS_B { + pinmux = <0x401f8074 2 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_sai1_tx_data1: IOMUXC_GPIO_EMC_24_SAI1_TX_DATA1 { + pinmux = <0x401f8074 3 0x401f8444 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_addr08: IOMUXC_GPIO_EMC_24_SEMC_ADDR08 { + pinmux = <0x401f8074 0 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_src_bt_cfg6: IOMUXC_GPIO_EMC_24_SRC_BT_CFG6 { + pinmux = <0x401f8074 6 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexio1_flexio29: IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 { + pinmux = <0x401f8078 4 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB1 { + pinmux = <0x401f8078 1 0x401f833c 1 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio2_io25: IOMUXC_GPIO_EMC_25_GPIO2_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart8_rts_b: IOMUXC_GPIO_EMC_25_LPUART8_RTS_B { + pinmux = <0x401f8078 2 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_sai1_tx_data0: IOMUXC_GPIO_EMC_25_SAI1_TX_DATA0 { + pinmux = <0x401f8078 3 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_addr09: IOMUXC_GPIO_EMC_25_SEMC_ADDR09 { + pinmux = <0x401f8078 0 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_src_bt_cfg7: IOMUXC_GPIO_EMC_25_SRC_BT_CFG7 { + pinmux = <0x401f8078 6 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio30: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 { + pinmux = <0x401f807c 4 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwma0: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA0 { + pinmux = <0x401f807c 1 0x401f8328 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio2_io26: IOMUXC_GPIO_EMC_26_GPIO2_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart8_tx: IOMUXC_GPIO_EMC_26_LPUART8_TX { + pinmux = <0x401f807c 2 0x401f8408 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_sai1_tx_bclk: IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK { + pinmux = <0x401f807c 3 0x401f844c 2 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_addr11: IOMUXC_GPIO_EMC_26_SEMC_ADDR11 { + pinmux = <0x401f807c 0 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_src_bt_cfg8: IOMUXC_GPIO_EMC_26_SRC_BT_CFG8 { + pinmux = <0x401f807c 6 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio31: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 { + pinmux = <0x401f8080 4 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB0 { + pinmux = <0x401f8080 1 0x401f8338 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio2_io27: IOMUXC_GPIO_EMC_27_GPIO2_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart8_rx: IOMUXC_GPIO_EMC_27_LPUART8_RX { + pinmux = <0x401f8080 2 0x401f8404 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_sai1_tx_sync: IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC { + pinmux = <0x401f8080 3 0x401f8450 2 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_addr12: IOMUXC_GPIO_EMC_27_SEMC_ADDR12 { + pinmux = <0x401f8080 0 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_src_bt_cfg9: IOMUXC_GPIO_EMC_27_SRC_BT_CFG9 { + pinmux = <0x401f8080 6 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io00: IOMUXC_GPIO_EMC_32_GPIO3_IO00 { + pinmux = <0x401f8094 5 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpspi4_sck: IOMUXC_GPIO_EMC_32_LPSPI4_SCK { + pinmux = <0x401f8094 4 0x401f83c0 1 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart4_tx: IOMUXC_GPIO_EMC_32_LPUART4_TX { + pinmux = <0x401f8094 2 0x401f83e8 2 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_qtimer1_timer0: IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 { + pinmux = <0x401f8094 1 0x401f8410 1 0x401f8208>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ref_24m_out: IOMUXC_GPIO_EMC_32_REF_24M_OUT { + pinmux = <0x401f8094 7 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_sai3_tx_data: IOMUXC_GPIO_EMC_32_SAI3_TX_DATA { + pinmux = <0x401f8094 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data08: IOMUXC_GPIO_EMC_32_SEMC_DATA08 { + pinmux = <0x401f8094 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io01: IOMUXC_GPIO_EMC_33_GPIO3_IO01 { + pinmux = <0x401f8098 5 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpspi4_pcs0: IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 { + pinmux = <0x401f8098 4 0x401f83bc 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpuart4_rx: IOMUXC_GPIO_EMC_33_LPUART4_RX { + pinmux = <0x401f8098 2 0x401f83e4 2 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_qtimer1_timer1: IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 { + pinmux = <0x401f8098 1 0x401f8414 1 0x401f820c>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_tx_bclk: IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK { + pinmux = <0x401f8098 3 0x401f847c 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data09: IOMUXC_GPIO_EMC_33_SEMC_DATA09 { + pinmux = <0x401f8098 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_enet_crs: IOMUXC_GPIO_EMC_34_ENET_CRS { + pinmux = <0x401f809c 6 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io02: IOMUXC_GPIO_EMC_34_GPIO3_IO02 { + pinmux = <0x401f809c 5 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpspi4_sdo: IOMUXC_GPIO_EMC_34_LPSPI4_SDO { + pinmux = <0x401f809c 4 0x401f83c8 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpuart7_tx: IOMUXC_GPIO_EMC_34_LPUART7_TX { + pinmux = <0x401f809c 2 0x401f8400 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_qtimer1_timer2: IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 { + pinmux = <0x401f809c 1 0x401f8418 1 0x401f8210>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_tx_sync: IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC { + pinmux = <0x401f809c 3 0x401f8480 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data10: IOMUXC_GPIO_EMC_34_SEMC_DATA10 { + pinmux = <0x401f809c 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_enet_col: IOMUXC_GPIO_EMC_35_ENET_COL { + pinmux = <0x401f80a0 6 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io03: IOMUXC_GPIO_EMC_35_GPIO3_IO03 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpspi4_sdi: IOMUXC_GPIO_EMC_35_LPSPI4_SDI { + pinmux = <0x401f80a0 4 0x401f83c4 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpuart7_rx: IOMUXC_GPIO_EMC_35_LPUART7_RX { + pinmux = <0x401f80a0 2 0x401f83fc 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_qtimer1_timer3: IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 { + pinmux = <0x401f80a0 1 0x401f841c 1 0x401f8214>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data11: IOMUXC_GPIO_EMC_35_SEMC_DATA11 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc2_wp: IOMUXC_GPIO_EMC_35_USDHC2_WP { + pinmux = <0x401f80a0 3 0x401f849c 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexcan1_tx: IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX { + pinmux = <0x401f8158 4 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f8158 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io20: IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 { + pinmux = <0x401f8158 5 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart6_tx: IOMUXC_GPIO_SD_B1_00_LPUART6_TX { + pinmux = <0x401f8158 2 0x401f83f8 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data2: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 { + pinmux = <0x401f8158 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexcan1_rx: IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX { + pinmux = <0x401f815c 4 0x401f8320 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B { + pinmux = <0x401f815c 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK { + pinmux = <0x401f815c 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io21: IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 { + pinmux = <0x401f815c 5 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart6_rx: IOMUXC_GPIO_SD_B1_01_LPUART6_RX { + pinmux = <0x401f815c 2 0x401f83f4 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data3: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 { + pinmux = <0x401f815c 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_clko1: IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 { + pinmux = <0x401f8160 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_enet_1588_event1_out: IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT { + pinmux = <0x401f8160 4 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data0: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA0 { + pinmux = <0x401f8160 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io22: IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 { + pinmux = <0x401f8160 5 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpi2c4_scl: IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL { + pinmux = <0x401f8160 3 0x401f8394 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpuart8_tx: IOMUXC_GPIO_SD_B1_02_LPUART8_TX { + pinmux = <0x401f8160 2 0x401f8408 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_cmd: IOMUXC_GPIO_SD_B1_02_USDHC2_CMD { + pinmux = <0x401f8160 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_clko2: IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 { + pinmux = <0x401f8164 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_enet_1588_event1_in: IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN { + pinmux = <0x401f8164 4 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data2: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA2 { + pinmux = <0x401f8164 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io23: IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 { + pinmux = <0x401f8164 5 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpi2c4_sda: IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA { + pinmux = <0x401f8164 3 0x401f8398 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpuart8_rx: IOMUXC_GPIO_SD_B1_03_LPUART8_RX { + pinmux = <0x401f8164 2 0x401f8404 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_clk: IOMUXC_GPIO_SD_B1_03_USDHC2_CLK { + pinmux = <0x401f8164 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_wait: IOMUXC_GPIO_SD_B1_04_CCM_WAIT { + pinmux = <0x401f8168 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_ref_clk: IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK { + pinmux = <0x401f8168 3 0x401f8304 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_tx_clk: IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK { + pinmux = <0x401f8168 2 0x401f831c 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ewm_out_b: IOMUXC_GPIO_SD_B1_04_EWM_OUT_B { + pinmux = <0x401f8168 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_data1: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA1 { + pinmux = <0x401f8168 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io24: IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 { + pinmux = <0x401f8168 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_data0: IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f8168 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY { + pinmux = <0x401f816c 6 0x401f8300 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_enet_rx_data1: IOMUXC_GPIO_SD_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f816c 2 0x401f8310 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f816c 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f816c 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io25: IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 { + pinmux = <0x401f816c 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_mclk: IOMUXC_GPIO_SD_B1_05_SAI3_MCLK { + pinmux = <0x401f816c 3 0x401f846c 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_data1: IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f816c 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_ccm_stop: IOMUXC_GPIO_SD_B1_06_CCM_STOP { + pinmux = <0x401f8170 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_enet_rx_data0: IOMUXC_GPIO_SD_B1_06_ENET_RX_DATA0 { + pinmux = <0x401f8170 2 0x401f830c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_data3: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA3 { + pinmux = <0x401f8170 1 0x401f8374 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io26: IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 { + pinmux = <0x401f8170 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f8170 4 0x401f83ac 2 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK { + pinmux = <0x401f8170 3 0x401f847c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_cd_b: IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B { + pinmux = <0x401f8170 0 0x401f8498 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_enet_rx_en: IOMUXC_GPIO_SD_B1_07_ENET_RX_EN { + pinmux = <0x401f8174 2 0x401f8314 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f8174 1 0x401f8378 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io27: IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 { + pinmux = <0x401f8174 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f8174 4 0x401f83b0 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai3_tx_sync: IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC { + pinmux = <0x401f8174 3 0x401f8480 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B { + pinmux = <0x401f8174 0 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_enet_rx_er: IOMUXC_GPIO_SD_B1_08_ENET_RX_ER { + pinmux = <0x401f8178 2 0x401f8318 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f8178 1 0x401f8368 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io28: IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 { + pinmux = <0x401f8178 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f8178 4 0x401f83b8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai3_tx_data: IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA { + pinmux = <0x401f8178 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f8178 0 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_enet_tx_en: IOMUXC_GPIO_SD_B1_09_ENET_TX_EN { + pinmux = <0x401f817c 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data2: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA2 { + pinmux = <0x401f817c 1 0x401f8370 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io29: IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 { + pinmux = <0x401f817c 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f817c 4 0x401f83b4 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK { + pinmux = <0x401f817c 3 0x401f8470 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f817c 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_enet_tx_data0: IOMUXC_GPIO_SD_B1_10_ENET_TX_DATA0 { + pinmux = <0x401f8180 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data1: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA1 { + pinmux = <0x401f8180 1 0x401f836c 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io30: IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 { + pinmux = <0x401f8180 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f8180 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_sai3_rx_sync: IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC { + pinmux = <0x401f8180 3 0x401f8478 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f8180 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_enet_tx_data1: IOMUXC_GPIO_SD_B1_11_ENET_TX_DATA1 { + pinmux = <0x401f8184 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B { + pinmux = <0x401f8184 1 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io31: IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 { + pinmux = <0x401f8184 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8184 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_sai3_rx_data: IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA { + pinmux = <0x401f8184 3 0x401f8474 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8184 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1021cag4b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1021cag4b-pinctrl.dtsi new file mode 100644 index 000000000..b9bdca6cc --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1021cag4b-pinctrl.dtsi @@ -0,0 +1,2311 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1021CAG4B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpt1_compare1: IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 { + pinmux = <0x401f80bc 7 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_jtag_tms: IOMUXC_GPIO_AD_B0_00_JTAG_TMS { + pinmux = <0x401f80bc 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpt1_capture2: IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 { + pinmux = <0x401f80c0 7 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_jtag_tck: IOMUXC_GPIO_AD_B0_01_JTAG_TCK { + pinmux = <0x401f80c0 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpt1_capture1: IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 { + pinmux = <0x401f80c4 7 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_jtag_mod: IOMUXC_GPIO_AD_B0_02_JTAG_MOD { + pinmux = <0x401f80c4 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY { + pinmux = <0x401f80c8 7 0x401f8300 2 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_jtag_tdi: IOMUXC_GPIO_AD_B0_03_JTAG_TDI { + pinmux = <0x401f80c8 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_sai1_mclk: IOMUXC_GPIO_AD_B0_03_SAI1_MCLK { + pinmux = <0x401f80c8 3 0x401f8430 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 6 0x401f848c 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc1_wp: IOMUXC_GPIO_AD_B0_03_USDHC1_WP { + pinmux = <0x401f80c8 4 0x401f8494 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B { + pinmux = <0x401f80c8 1 0x401f8498 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_wdog1_b: IOMUXC_GPIO_AD_B0_03_WDOG1_B { + pinmux = <0x401f80c8 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_mdio: IOMUXC_GPIO_AD_B0_04_ENET_MDIO { + pinmux = <0x401f80cc 4 0x401f8308 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_ewm_out_b: IOMUXC_GPIO_AD_B0_04_EWM_OUT_B { + pinmux = <0x401f80cc 7 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_flexcan1_tx: IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX { + pinmux = <0x401f80cc 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_jtag_tdo: IOMUXC_GPIO_AD_B0_04_JTAG_TDO { + pinmux = <0x401f80cc 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_qtimer2_timer0: IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 { + pinmux = <0x401f80cc 3 0x401f8420 1 0x401f8240>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR { + pinmux = <0x401f80cc 6 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usdhc1_wp: IOMUXC_GPIO_AD_B0_04_USDHC1_WP { + pinmux = <0x401f80cc 2 0x401f8494 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_arm_nmi: IOMUXC_GPIO_AD_B0_05_ARM_NMI { + pinmux = <0x401f80d0 7 0x401f840c 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_mdc: IOMUXC_GPIO_AD_B0_05_ENET_MDC { + pinmux = <0x401f80d0 4 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_flexcan1_rx: IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX { + pinmux = <0x401f80d0 1 0x401f8320 2 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_jtag_trstb: IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB { + pinmux = <0x401f80d0 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_qtimer2_timer1: IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 { + pinmux = <0x401f80d0 3 0x401f8424 1 0x401f8244>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usb_otg1_id: IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID { + pinmux = <0x401f80d0 6 0x401f82fc 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usdhc1_cd_b: IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B { + pinmux = <0x401f80d0 2 0x401f8490 1 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA3 { + pinmux = <0x401f80d4 4 0x401f8354 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpuart1_tx: IOMUXC_GPIO_AD_B0_06_LPUART1_TX { + pinmux = <0x401f80d4 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_mqs_right: IOMUXC_GPIO_AD_B0_06_MQS_RIGHT { + pinmux = <0x401f80d4 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_pit_trigger0: IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER0 { + pinmux = <0x401f80d4 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_qtimer2_timer2: IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 { + pinmux = <0x401f80d4 3 0x401f8428 1 0x401f8248>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_ref_32k_out: IOMUXC_GPIO_AD_B0_06_REF_32K_OUT { + pinmux = <0x401f80d4 6 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_flexpwm2_pwmb3: IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB3 { + pinmux = <0x401f80d8 4 0x401f8364 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_lpuart1_rx: IOMUXC_GPIO_AD_B0_07_LPUART1_RX { + pinmux = <0x401f80d8 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_mqs_left: IOMUXC_GPIO_AD_B0_07_MQS_LEFT { + pinmux = <0x401f80d8 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_pit_trigger1: IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER1 { + pinmux = <0x401f80d8 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_qtimer2_timer3: IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 { + pinmux = <0x401f80d8 3 0x401f842c 1 0x401f824c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_ref_24m_out: IOMUXC_GPIO_AD_B0_07_REF_24M_OUT { + pinmux = <0x401f80d8 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_acmp1_in4: IOMUXC_GPIO_AD_B0_08_ACMP1_IN4 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_arm_cm7_txev: IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV { + pinmux = <0x401f80dc 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_ref_clk: IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK { + pinmux = <0x401f80dc 4 0x401f8304 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_tx_clk: IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK { + pinmux = <0x401f80dc 0 0x401f831c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_kpp_col0: IOMUXC_GPIO_AD_B0_08_KPP_COL0 { + pinmux = <0x401f80dc 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpi2c3_scl: IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL { + pinmux = <0x401f80dc 1 0x401f838c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B { + pinmux = <0x401f80dc 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_acmp2_in4: IOMUXC_GPIO_AD_B0_09_ACMP2_IN4 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_arm_cm7_rxev: IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV { + pinmux = <0x401f80e0 6 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data1: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA1 { + pinmux = <0x401f80e0 0 0x401f8310 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_kpp_row0: IOMUXC_GPIO_AD_B0_09_KPP_ROW0 { + pinmux = <0x401f80e0 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpi2c3_sda: IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA { + pinmux = <0x401f80e0 1 0x401f8390 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B { + pinmux = <0x401f80e0 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_acmp3_in4: IOMUXC_GPIO_AD_B0_10_ACMP3_IN4 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_clk: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_CLK { + pinmux = <0x401f80e4 6 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_rx_data0: IOMUXC_GPIO_AD_B0_10_ENET_RX_DATA0 { + pinmux = <0x401f80e4 0 0x401f830c 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f80e4 4 0x401f8350 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_kpp_col1: IOMUXC_GPIO_AD_B0_10_KPP_COL1 { + pinmux = <0x401f80e4 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpspi1_sck: IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK { + pinmux = <0x401f80e4 1 0x401f83a0 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpuart5_tx: IOMUXC_GPIO_AD_B0_10_LPUART5_TX { + pinmux = <0x401f80e4 2 0x401f83f0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_acmp4_in4: IOMUXC_GPIO_AD_B0_11_ACMP4_IN4 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_arm_trace_swo: IOMUXC_GPIO_AD_B0_11_ARM_TRACE_SWO { + pinmux = <0x401f80e8 6 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_rx_en: IOMUXC_GPIO_AD_B0_11_ENET_RX_EN { + pinmux = <0x401f80e8 0 0x401f8314 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f80e8 4 0x401f8360 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_kpp_row1: IOMUXC_GPIO_AD_B0_11_KPP_ROW1 { + pinmux = <0x401f80e8 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpspi1_pcs0: IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 { + pinmux = <0x401f80e8 1 0x401f839c 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpuart5_rx: IOMUXC_GPIO_AD_B0_11_LPUART5_RX { + pinmux = <0x401f80e8 2 0x401f83ec 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in0: IOMUXC_GPIO_AD_B0_12_ADC1_IN0 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_trace0: IOMUXC_GPIO_AD_B0_12_ARM_TRACE0 { + pinmux = <0x401f80ec 6 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_rx_er: IOMUXC_GPIO_AD_B0_12_ENET_RX_ER { + pinmux = <0x401f80ec 0 0x401f8318 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm2_pwma1: IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA1 { + pinmux = <0x401f80ec 4 0x401f834c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_kpp_col2: IOMUXC_GPIO_AD_B0_12_KPP_COL2 { + pinmux = <0x401f80ec 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpspi1_sdo: IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO { + pinmux = <0x401f80ec 1 0x401f83a8 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart3_cts_b: IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B { + pinmux = <0x401f80ec 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_snvs_vio_5_ctl: IOMUXC_GPIO_AD_B0_12_SNVS_VIO_5_CTL { + pinmux = <0x401f80ec 7 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc2_in0: IOMUXC_GPIO_AD_B0_13_ADC2_IN0 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_tx_en: IOMUXC_GPIO_AD_B0_13_ENET_TX_EN { + pinmux = <0x401f80f0 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm2_pwmb1: IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB1 { + pinmux = <0x401f80f0 4 0x401f835c 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_kpp_row2: IOMUXC_GPIO_AD_B0_13_KPP_ROW2 { + pinmux = <0x401f80f0 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpspi1_sdi: IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI { + pinmux = <0x401f80f0 1 0x401f83a4 1 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart3_rts_b: IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B { + pinmux = <0x401f80f0 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_snvs_vio_5_b: IOMUXC_GPIO_AD_B0_13_SNVS_VIO_5_B { + pinmux = <0x401f80f0 7 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp1_in0: IOMUXC_GPIO_AD_B0_14_ACMP1_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in0: IOMUXC_GPIO_AD_B0_14_ACMP2_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp3_in0: IOMUXC_GPIO_AD_B0_14_ACMP3_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp4_in0: IOMUXC_GPIO_AD_B0_14_ACMP4_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in1: IOMUXC_GPIO_AD_B0_14_ADC1_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc2_in1: IOMUXC_GPIO_AD_B0_14_ADC2_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_tx_data0: IOMUXC_GPIO_AD_B0_14_ENET_TX_DATA0 { + pinmux = <0x401f80f4 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexpwm2_pwma0: IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA0 { + pinmux = <0x401f80f4 4 0x401f8348 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_kpp_col3: IOMUXC_GPIO_AD_B0_14_KPP_COL3 { + pinmux = <0x401f80f4 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart3_tx: IOMUXC_GPIO_AD_B0_14_LPUART3_TX { + pinmux = <0x401f80f4 2 0x401f83dc 1 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_wdog1_any: IOMUXC_GPIO_AD_B0_14_WDOG1_ANY { + pinmux = <0x401f80f4 7 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp1_in1: IOMUXC_GPIO_AD_B0_15_ACMP1_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp2_in1: IOMUXC_GPIO_AD_B0_15_ACMP2_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in1: IOMUXC_GPIO_AD_B0_15_ACMP3_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp4_in1: IOMUXC_GPIO_AD_B0_15_ACMP4_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in2: IOMUXC_GPIO_AD_B0_15_ADC1_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc2_in2: IOMUXC_GPIO_AD_B0_15_ADC2_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_tx_data1: IOMUXC_GPIO_AD_B0_15_ENET_TX_DATA1 { + pinmux = <0x401f80f8 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 1 0x401f8324 2 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexpwm2_pwmb0: IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB0 { + pinmux = <0x401f80f8 4 0x401f8358 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_kpp_row3: IOMUXC_GPIO_AD_B0_15_KPP_ROW3 { + pinmux = <0x401f80f8 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart3_rx: IOMUXC_GPIO_AD_B0_15_LPUART3_RX { + pinmux = <0x401f80f8 2 0x401f83d8 1 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp1_in2: IOMUXC_GPIO_AD_B1_00_ACMP1_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_00_ENET_1588_EVENT2_OUT { + pinmux = <0x401f80fc 6 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexcan2_tx: IOMUXC_GPIO_AD_B1_00_FLEXCAN2_TX { + pinmux = <0x401f80fc 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio1_flexio15: IOMUXC_GPIO_AD_B1_00_FLEXIO1_FLEXIO15 { + pinmux = <0x401f80fc 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexspi_a_data3: IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA3 { + pinmux = <0x401f80fc 1 0x401f8374 1 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_kpp_col4: IOMUXC_GPIO_AD_B1_00_KPP_COL4 { + pinmux = <0x401f80fc 7 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_sai1_mclk: IOMUXC_GPIO_AD_B1_00_SAI1_MCLK { + pinmux = <0x401f80fc 3 0x401f8430 2 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_semc_rdy: IOMUXC_GPIO_AD_B1_00_SEMC_RDY { + pinmux = <0x401f80fc 0 0x401f8484 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in2: IOMUXC_GPIO_AD_B1_01_ACMP2_IN2 { + pinmux = <0x401f8100 5 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in3: IOMUXC_GPIO_AD_B1_01_ADC1_IN3 { + pinmux = <0x401f8100 5 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_01_ENET_1588_EVENT2_IN { + pinmux = <0x401f8100 6 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexcan2_rx: IOMUXC_GPIO_AD_B1_01_FLEXCAN2_RX { + pinmux = <0x401f8100 2 0x401f8324 3 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio1_flexio14: IOMUXC_GPIO_AD_B1_01_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8100 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexspi_a_sclk: IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK { + pinmux = <0x401f8100 1 0x401f8378 1 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_kpp_row4: IOMUXC_GPIO_AD_B1_01_KPP_ROW4 { + pinmux = <0x401f8100 7 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_sai1_tx_bclk: IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK { + pinmux = <0x401f8100 3 0x401f844c 1 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_semc_csx0: IOMUXC_GPIO_AD_B1_01_SEMC_CSX0 { + pinmux = <0x401f8100 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp3_in2: IOMUXC_GPIO_AD_B1_02_ACMP3_IN2 { + pinmux = <0x401f8104 5 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in3: IOMUXC_GPIO_AD_B1_02_ADC2_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event3_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT3_OUT { + pinmux = <0x401f8104 6 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio1_flexio13: IOMUXC_GPIO_AD_B1_02_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8104 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexspi_a_data0: IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA0 { + pinmux = <0x401f8104 1 0x401f8368 1 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_kpp_col5: IOMUXC_GPIO_AD_B1_02_KPP_COL5 { + pinmux = <0x401f8104 7 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpspi4_sck: IOMUXC_GPIO_AD_B1_02_LPSPI4_SCK { + pinmux = <0x401f8104 2 0x401f83c0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_sai1_tx_sync: IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC { + pinmux = <0x401f8104 3 0x401f8450 1 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_semc_csx1: IOMUXC_GPIO_AD_B1_02_SEMC_CSX1 { + pinmux = <0x401f8104 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp4_in2: IOMUXC_GPIO_AD_B1_03_ACMP4_IN2 { + pinmux = <0x401f8108 5 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in4: IOMUXC_GPIO_AD_B1_03_ADC1_IN4 { + pinmux = <0x401f8108 5 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event3_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT3_IN { + pinmux = <0x401f8108 6 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio1_flexio12: IOMUXC_GPIO_AD_B1_03_FLEXIO1_FLEXIO12 { + pinmux = <0x401f8108 4 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexspi_a_data2: IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA2 { + pinmux = <0x401f8108 1 0x401f8370 1 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_kpp_row5: IOMUXC_GPIO_AD_B1_03_KPP_ROW5 { + pinmux = <0x401f8108 7 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpspi4_pcs0: IOMUXC_GPIO_AD_B1_03_LPSPI4_PCS0 { + pinmux = <0x401f8108 2 0x401f83bc 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_sai1_tx_data0: IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA0 { + pinmux = <0x401f8108 3 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_semc_csx2: IOMUXC_GPIO_AD_B1_03_SEMC_CSX2 { + pinmux = <0x401f8108 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp1_in3: IOMUXC_GPIO_AD_B1_04_ACMP1_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in4: IOMUXC_GPIO_AD_B1_04_ADC2_IN4 { + pinmux = <0x401f810c 5 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio1_flexio11: IOMUXC_GPIO_AD_B1_04_FLEXIO1_FLEXIO11 { + pinmux = <0x401f810c 4 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_a_data1: IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA1 { + pinmux = <0x401f810c 1 0x401f836c 1 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_kpp_col6: IOMUXC_GPIO_AD_B1_04_KPP_COL6 { + pinmux = <0x401f810c 7 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpspi1_pcs1: IOMUXC_GPIO_AD_B1_04_LPSPI1_PCS1 { + pinmux = <0x401f810c 6 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpspi4_sdo: IOMUXC_GPIO_AD_B1_04_LPSPI4_SDO { + pinmux = <0x401f810c 2 0x401f83c8 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_sai1_rx_sync: IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f810c 3 0x401f8448 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_semc_csx3: IOMUXC_GPIO_AD_B1_04_SEMC_CSX3 { + pinmux = <0x401f810c 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp2_in3: IOMUXC_GPIO_AD_B1_05_ACMP2_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in5: IOMUXC_GPIO_AD_B1_05_ADC1_IN5 { + pinmux = <0x401f8110 5 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in5: IOMUXC_GPIO_AD_B1_05_ADC2_IN5 { + pinmux = <0x401f8110 5 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio1_flexio10: IOMUXC_GPIO_AD_B1_05_FLEXIO1_FLEXIO10 { + pinmux = <0x401f8110 4 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_a_ss0_b: IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B { + pinmux = <0x401f8110 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_kpp_row6: IOMUXC_GPIO_AD_B1_05_KPP_ROW6 { + pinmux = <0x401f8110 7 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpspi1_pcs2: IOMUXC_GPIO_AD_B1_05_LPSPI1_PCS2 { + pinmux = <0x401f8110 6 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpspi4_sdi: IOMUXC_GPIO_AD_B1_05_LPSPI4_SDI { + pinmux = <0x401f8110 2 0x401f83c4 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_sai1_rx_data0: IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA0 { + pinmux = <0x401f8110 3 0x401f8438 1 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc1_wp: IOMUXC_GPIO_AD_B1_05_USDHC1_WP { + pinmux = <0x401f8110 0 0x401f8494 2 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in3: IOMUXC_GPIO_AD_B1_06_ACMP3_IN3 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in6: IOMUXC_GPIO_AD_B1_06_ADC1_IN6 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in6: IOMUXC_GPIO_AD_B1_06_ADC2_IN6 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio1_flexio09: IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8114 4 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexpwm1_pwma0: IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA0 { + pinmux = <0x401f8114 1 0x401f8328 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_kpp_col7: IOMUXC_GPIO_AD_B1_06_KPP_COL7 { + pinmux = <0x401f8114 7 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpspi1_pcs3: IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3 { + pinmux = <0x401f8114 6 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B { + pinmux = <0x401f8114 2 0x401f83cc 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_sai1_rx_bclk: IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK { + pinmux = <0x401f8114 3 0x401f8434 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc1_reset_b: IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B { + pinmux = <0x401f8114 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp4_in3: IOMUXC_GPIO_AD_B1_07_ACMP4_IN3 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in7: IOMUXC_GPIO_AD_B1_07_ADC1_IN7 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in7: IOMUXC_GPIO_AD_B1_07_ADC2_IN7 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio1_flexio08: IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8118 4 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexpwm1_pwmb0: IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB0 { + pinmux = <0x401f8118 1 0x401f8338 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_kpp_row7: IOMUXC_GPIO_AD_B1_07_KPP_ROW7 { + pinmux = <0x401f8118 7 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpspi3_pcs3: IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3 { + pinmux = <0x401f8118 6 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B { + pinmux = <0x401f8118 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_sai1_tx_data1: IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA1 { + pinmux = <0x401f8118 3 0x401f8444 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc1_vselect: IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT { + pinmux = <0x401f8118 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_acmp1_in5: IOMUXC_GPIO_AD_B1_08_ACMP1_IN5 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc1_in8: IOMUXC_GPIO_AD_B1_08_ADC1_IN8 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc2_in8: IOMUXC_GPIO_AD_B1_08_ADC2_IN8 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexio1_flexio07: IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07 { + pinmux = <0x401f811c 4 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexpwm1_pwma1: IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA1 { + pinmux = <0x401f811c 1 0x401f832c 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio1_io24: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpi2c2_scl: IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL { + pinmux = <0x401f811c 0 0x401f8384 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpspi3_pcs2: IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2 { + pinmux = <0x401f811c 6 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpuart2_tx: IOMUXC_GPIO_AD_B1_08_LPUART2_TX { + pinmux = <0x401f811c 2 0x401f83d4 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_sai1_tx_data2: IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA2 { + pinmux = <0x401f811c 3 0x401f8440 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_xbar1_xbar_in12: IOMUXC_GPIO_AD_B1_08_XBAR1_XBAR_IN12 { + pinmux = <0x401f811c 7 0x401f84b4 1 0x401f8290>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_xbar1_xbar_inout12: IOMUXC_GPIO_AD_B1_08_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f811c 7 0x401f84b4 1 0x401f8290>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_acmp2_in5: IOMUXC_GPIO_AD_B1_09_ACMP2_IN5 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc1_in9: IOMUXC_GPIO_AD_B1_09_ADC1_IN9 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc2_in9: IOMUXC_GPIO_AD_B1_09_ADC2_IN9 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexio1_flexio06: IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO06 { + pinmux = <0x401f8120 4 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexpwm1_pwmb1: IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB1 { + pinmux = <0x401f8120 1 0x401f833c 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio1_io25: IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpi2c2_sda: IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA { + pinmux = <0x401f8120 0 0x401f8388 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpspi3_pcs1: IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 { + pinmux = <0x401f8120 6 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpuart2_rx: IOMUXC_GPIO_AD_B1_09_LPUART2_RX { + pinmux = <0x401f8120 2 0x401f83d0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_sai1_tx_data3: IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA3 { + pinmux = <0x401f8120 3 0x401f843c 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_xbar1_xbar_in13: IOMUXC_GPIO_AD_B1_09_XBAR1_XBAR_IN13 { + pinmux = <0x401f8120 7 0x401f84b8 1 0x401f8294>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_xbar1_xbar_inout13: IOMUXC_GPIO_AD_B1_09_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8120 7 0x401f84b8 1 0x401f8294>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_acmp3_in5: IOMUXC_GPIO_AD_B1_10_ACMP3_IN5 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in10: IOMUXC_GPIO_AD_B1_10_ADC1_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc2_in10: IOMUXC_GPIO_AD_B1_10_ADC2_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio1_flexio05: IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8124 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexpwm1_pwma2: IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA2 { + pinmux = <0x401f8124 1 0x401f8330 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpt2_capture1: IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 { + pinmux = <0x401f8124 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart4_tx: IOMUXC_GPIO_AD_B1_10_LPUART4_TX { + pinmux = <0x401f8124 2 0x401f83e8 1 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR { + pinmux = <0x401f8124 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B { + pinmux = <0x401f8124 3 0x401f8490 2 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_acmp4_in5: IOMUXC_GPIO_AD_B1_11_ACMP4_IN5 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in11: IOMUXC_GPIO_AD_B1_11_ADC1_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc2_in11: IOMUXC_GPIO_AD_B1_11_ADC2_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio1_flexio04: IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8128 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexpwm1_pwmb2: IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB2 { + pinmux = <0x401f8128 1 0x401f8340 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpt2_compare1: IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 { + pinmux = <0x401f8128 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart4_rx: IOMUXC_GPIO_AD_B1_11_LPUART4_RX { + pinmux = <0x401f8128 2 0x401f83e4 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usb_otg1_id: IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID { + pinmux = <0x401f8128 0 0x401f82fc 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usdhc1_wp: IOMUXC_GPIO_AD_B1_11_USDHC1_WP { + pinmux = <0x401f8128 3 0x401f8494 3 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_in6: IOMUXC_GPIO_AD_B1_12_ACMP1_IN6 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_out: IOMUXC_GPIO_AD_B1_12_ACMP1_OUT { + pinmux = <0x401f812c 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc1_in12: IOMUXC_GPIO_AD_B1_12_ADC1_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc2_in12: IOMUXC_GPIO_AD_B1_12_ADC2_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio1_flexio03: IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 { + pinmux = <0x401f812c 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexpwm1_pwma3: IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f812c 6 0x401f8334 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_lpspi3_sck: IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK { + pinmux = <0x401f812c 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usb_otg1_oc: IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC { + pinmux = <0x401f812c 0 0x401f848c 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B { + pinmux = <0x401f812c 3 0x401f8498 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_in6: IOMUXC_GPIO_AD_B1_13_ACMP2_IN6 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_out: IOMUXC_GPIO_AD_B1_13_ACMP2_OUT { + pinmux = <0x401f8130 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc1_in13: IOMUXC_GPIO_AD_B1_13_ADC1_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc2_in13: IOMUXC_GPIO_AD_B1_13_ADC2_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio1_flexio02: IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 { + pinmux = <0x401f8130 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8130 6 0x401f8344 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpi2c1_hreq: IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ { + pinmux = <0x401f8130 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpspi3_pcs0: IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 { + pinmux = <0x401f8130 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_usdhc2_wp: IOMUXC_GPIO_AD_B1_13_USDHC2_WP { + pinmux = <0x401f8130 3 0x401f849c 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_in6: IOMUXC_GPIO_AD_B1_14_ACMP3_IN6 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_out: IOMUXC_GPIO_AD_B1_14_ACMP3_OUT { + pinmux = <0x401f8134 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc1_in14: IOMUXC_GPIO_AD_B1_14_ADC1_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc2_in14: IOMUXC_GPIO_AD_B1_14_ADC2_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f8134 3 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio1_flexio01: IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8134 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpi2c1_scl: IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL { + pinmux = <0x401f8134 0 0x401f837c 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpspi3_sdo: IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO { + pinmux = <0x401f8134 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_in6: IOMUXC_GPIO_AD_B1_15_ACMP4_IN6 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_out: IOMUXC_GPIO_AD_B1_15_ACMP4_OUT { + pinmux = <0x401f8138 1 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc1_in15: IOMUXC_GPIO_AD_B1_15_ADC1_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc2_in15: IOMUXC_GPIO_AD_B1_15_ADC2_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f8138 3 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio1_flexio00: IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8138 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpi2c1_sda: IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA { + pinmux = <0x401f8138 0 0x401f8380 1 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpspi3_sdi: IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI { + pinmux = <0x401f8138 2 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexcan1_tx: IOMUXC_GPIO_EMC_00_FLEXCAN1_TX { + pinmux = <0x401f8014 6 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio2_io00: IOMUXC_GPIO_EMC_00_GPIO2_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 4 0x401f83b0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpuart4_cts_b: IOMUXC_GPIO_EMC_00_LPUART4_CTS_B { + pinmux = <0x401f8014 2 0x401f83e0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_pit_trigger2: IOMUXC_GPIO_EMC_00_PIT_TRIGGER2 { + pinmux = <0x401f8014 7 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_qtimer2_timer0: IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0 { + pinmux = <0x401f8014 1 0x401f8420 0 0x401f8188>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_spdif_sr_clk: IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK { + pinmux = <0x401f8014 3 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexcan1_rx: IOMUXC_GPIO_EMC_01_FLEXCAN1_RX { + pinmux = <0x401f8018 6 0x401f8320 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio2_io01: IOMUXC_GPIO_EMC_01_GPIO2_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 4 0x401f83ac 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpuart4_rts_b: IOMUXC_GPIO_EMC_01_LPUART4_RTS_B { + pinmux = <0x401f8018 2 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_pit_trigger3: IOMUXC_GPIO_EMC_01_PIT_TRIGGER3 { + pinmux = <0x401f8018 7 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_qtimer2_timer1: IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1 { + pinmux = <0x401f8018 1 0x401f8424 0 0x401f818c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_spdif_out: IOMUXC_GPIO_EMC_01_SPDIF_OUT { + pinmux = <0x401f8018 3 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio2_io02: IOMUXC_GPIO_EMC_02_GPIO2_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpi2c1_scl: IOMUXC_GPIO_EMC_02_LPI2C1_SCL { + pinmux = <0x401f801c 6 0x401f837c 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 4 0x401f83b8 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpuart4_tx: IOMUXC_GPIO_EMC_02_LPUART4_TX { + pinmux = <0x401f801c 2 0x401f83e8 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_qtimer2_timer2: IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2 { + pinmux = <0x401f801c 1 0x401f8428 0 0x401f8190>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_spdif_lock: IOMUXC_GPIO_EMC_02_SPDIF_LOCK { + pinmux = <0x401f801c 3 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio2_io03: IOMUXC_GPIO_EMC_03_GPIO2_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpi2c1_sda: IOMUXC_GPIO_EMC_03_LPI2C1_SDA { + pinmux = <0x401f8020 6 0x401f8380 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 4 0x401f83b4 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpuart4_rx: IOMUXC_GPIO_EMC_03_LPUART4_RX { + pinmux = <0x401f8020 2 0x401f83e4 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_qtimer2_timer3: IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3 { + pinmux = <0x401f8020 1 0x401f842c 0 0x401f8194>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_spdif_ext_clk: IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK { + pinmux = <0x401f8020 3 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio16: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 { + pinmux = <0x401f8024 4 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio2_io04: IOMUXC_GPIO_EMC_04_GPIO2_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_bclk: IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK { + pinmux = <0x401f8024 3 0x401f8464 1 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_spdif_out: IOMUXC_GPIO_EMC_04_SPDIF_OUT { + pinmux = <0x401f8024 2 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio17: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 { + pinmux = <0x401f8028 4 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio2_io05: IOMUXC_GPIO_EMC_05_GPIO2_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 3 0x401f8468 1 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_spdif_in: IOMUXC_GPIO_EMC_05_SPDIF_IN { + pinmux = <0x401f8028 2 0x401f8488 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio18: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 { + pinmux = <0x401f802c 4 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio2_io06: IOMUXC_GPIO_EMC_06_GPIO2_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_lpuart3_tx: IOMUXC_GPIO_EMC_06_LPUART3_TX { + pinmux = <0x401f802c 2 0x401f83dc 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_data: IOMUXC_GPIO_EMC_06_SAI2_TX_DATA { + pinmux = <0x401f802c 3 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio19: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 { + pinmux = <0x401f8030 4 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio2_io07: IOMUXC_GPIO_EMC_07_GPIO2_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_lpuart3_rx: IOMUXC_GPIO_EMC_07_LPUART3_RX { + pinmux = <0x401f8030 2 0x401f83d8 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_rx_sync: IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC { + pinmux = <0x401f8030 3 0x401f8460 1 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexcan2_tx: IOMUXC_GPIO_EMC_08_FLEXCAN2_TX { + pinmux = <0x401f8034 2 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio20: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 { + pinmux = <0x401f8034 4 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio2_io08: IOMUXC_GPIO_EMC_08_GPIO2_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 3 0x401f845c 1 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_rx: IOMUXC_GPIO_EMC_09_FLEXCAN2_RX { + pinmux = <0x401f8038 2 0x401f8324 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio21: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 { + pinmux = <0x401f8038 4 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio2_io09: IOMUXC_GPIO_EMC_09_GPIO2_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_bclk: IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK { + pinmux = <0x401f8038 3 0x401f8458 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_we: IOMUXC_GPIO_EMC_09_SEMC_WE { + pinmux = <0x401f8038 0 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_in09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_IN09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwmx0: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX0 { + pinmux = <0x401f803c 6 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio2_io10: IOMUXC_GPIO_EMC_10_GPIO2_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_lpi2c4_sda: IOMUXC_GPIO_EMC_10_LPI2C4_SDA { + pinmux = <0x401f803c 2 0x401f8398 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_lpspi2_sck: IOMUXC_GPIO_EMC_10_LPSPI2_SCK { + pinmux = <0x401f803c 4 0x401f83b0 1 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai1_tx_sync: IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC { + pinmux = <0x401f803c 3 0x401f8450 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_cas: IOMUXC_GPIO_EMC_10_SEMC_CAS { + pinmux = <0x401f803c 0 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_xbar1_xbar_in10: IOMUXC_GPIO_EMC_10_XBAR1_XBAR_IN10 { + pinmux = <0x401f803c 1 0x401f84b0 0 0x401f81b0>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_10_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f803c 1 0x401f84b0 0 0x401f81b0>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmx1: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX1 { + pinmux = <0x401f8040 6 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio2_io11: IOMUXC_GPIO_EMC_11_GPIO2_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_scl: IOMUXC_GPIO_EMC_11_LPI2C4_SCL { + pinmux = <0x401f8040 2 0x401f8394 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpspi2_pcs0: IOMUXC_GPIO_EMC_11_LPSPI2_PCS0 { + pinmux = <0x401f8040 4 0x401f83ac 1 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_sai1_tx_bclk: IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK { + pinmux = <0x401f8040 3 0x401f844c 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_ras: IOMUXC_GPIO_EMC_11_SEMC_RAS { + pinmux = <0x401f8040 0 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_xbar1_xbar_in11: IOMUXC_GPIO_EMC_11_XBAR1_XBAR_IN11 { + pinmux = <0x401f8040 1 0x0 0 0x401f81b4>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_11_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8040 1 0x0 0 0x401f81b4>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm2_pwmx2: IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX2 { + pinmux = <0x401f8044 6 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio2_io12: IOMUXC_GPIO_EMC_12_GPIO2_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpspi2_sdo: IOMUXC_GPIO_EMC_12_LPSPI2_SDO { + pinmux = <0x401f8044 4 0x401f83b8 1 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpuart6_tx: IOMUXC_GPIO_EMC_12_LPUART6_TX { + pinmux = <0x401f8044 2 0x401f83f8 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_sai1_tx_data0: IOMUXC_GPIO_EMC_12_SAI1_TX_DATA0 { + pinmux = <0x401f8044 3 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_cs0: IOMUXC_GPIO_EMC_12_SEMC_CS0 { + pinmux = <0x401f8044 0 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in12: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN12 { + pinmux = <0x401f8044 1 0x401f84b4 0 0x401f81b8>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8044 1 0x401f84b4 0 0x401f81b8>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_ccm_pmic_rdy: IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY { + pinmux = <0x401f8048 7 0x401f8300 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm2_pwmx3: IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX3 { + pinmux = <0x401f8048 6 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio2_io13: IOMUXC_GPIO_EMC_13_GPIO2_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpspi2_sdi: IOMUXC_GPIO_EMC_13_LPSPI2_SDI { + pinmux = <0x401f8048 4 0x401f83b4 1 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart6_rx: IOMUXC_GPIO_EMC_13_LPUART6_RX { + pinmux = <0x401f8048 2 0x401f83f4 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_sai1_rx_data0: IOMUXC_GPIO_EMC_13_SAI1_RX_DATA0 { + pinmux = <0x401f8048 3 0x401f8438 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_ba0: IOMUXC_GPIO_EMC_13_SEMC_BA0 { + pinmux = <0x401f8048 0 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in13: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN13 { + pinmux = <0x401f8048 1 0x401f84b8 0 0x401f81bc>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8048 1 0x401f84b8 0 0x401f81bc>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_flexcan1_tx: IOMUXC_GPIO_EMC_14_FLEXCAN1_TX { + pinmux = <0x401f804c 6 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio2_io14: IOMUXC_GPIO_EMC_14_GPIO2_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart6_cts_b: IOMUXC_GPIO_EMC_14_LPUART6_CTS_B { + pinmux = <0x401f804c 2 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_sai1_rx_bclk: IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK { + pinmux = <0x401f804c 3 0x401f8434 1 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_ba1: IOMUXC_GPIO_EMC_14_SEMC_BA1 { + pinmux = <0x401f804c 0 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in14: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN14 { + pinmux = <0x401f804c 1 0x401f84a0 1 0x401f81c0>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f804c 1 0x401f84a0 1 0x401f81c0>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_flexcan1_rx: IOMUXC_GPIO_EMC_15_FLEXCAN1_RX { + pinmux = <0x401f8050 6 0x401f8320 3 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio2_io15: IOMUXC_GPIO_EMC_15_GPIO2_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart6_rts_b: IOMUXC_GPIO_EMC_15_LPUART6_RTS_B { + pinmux = <0x401f8050 2 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_sai1_rx_sync: IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC { + pinmux = <0x401f8050 3 0x401f8448 1 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr10: IOMUXC_GPIO_EMC_15_SEMC_ADDR10 { + pinmux = <0x401f8050 0 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_wdog1_b: IOMUXC_GPIO_EMC_15_WDOG1_B { + pinmux = <0x401f8050 4 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in15: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN15 { + pinmux = <0x401f8050 1 0x401f84a4 1 0x401f81c4>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8050 1 0x401f84a4 1 0x401f81c4>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio2_io16: IOMUXC_GPIO_EMC_16_GPIO2_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_mqs_right: IOMUXC_GPIO_EMC_16_MQS_RIGHT { + pinmux = <0x401f8054 2 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_sai2_mclk: IOMUXC_GPIO_EMC_16_SAI2_MCLK { + pinmux = <0x401f8054 3 0x401f8454 1 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr00: IOMUXC_GPIO_EMC_16_SEMC_ADDR00 { + pinmux = <0x401f8054 0 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_src_boot_mode0: IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE0 { + pinmux = <0x401f8054 6 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio2_io17: IOMUXC_GPIO_EMC_17_GPIO2_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_mqs_left: IOMUXC_GPIO_EMC_17_MQS_LEFT { + pinmux = <0x401f8058 2 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_sai3_mclk: IOMUXC_GPIO_EMC_17_SAI3_MCLK { + pinmux = <0x401f8058 3 0x401f846c 1 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr01: IOMUXC_GPIO_EMC_17_SEMC_ADDR01 { + pinmux = <0x401f8058 0 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_src_boot_mode1: IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE1 { + pinmux = <0x401f8058 6 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexio1_flexio22: IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 { + pinmux = <0x401f805c 4 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio2_io18: IOMUXC_GPIO_EMC_18_GPIO2_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpi2c2_sda: IOMUXC_GPIO_EMC_18_LPI2C2_SDA { + pinmux = <0x401f805c 2 0x401f8388 1 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_sai1_rx_sync: IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC { + pinmux = <0x401f805c 3 0x401f8448 2 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr02: IOMUXC_GPIO_EMC_18_SEMC_ADDR02 { + pinmux = <0x401f805c 0 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_src_bt_cfg0: IOMUXC_GPIO_EMC_18_SRC_BT_CFG0 { + pinmux = <0x401f805c 6 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_IN16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexio1_flexio23: IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 { + pinmux = <0x401f8060 4 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio2_io19: IOMUXC_GPIO_EMC_19_GPIO2_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpi2c2_scl: IOMUXC_GPIO_EMC_19_LPI2C2_SCL { + pinmux = <0x401f8060 2 0x401f8384 1 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_sai1_rx_bclk: IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK { + pinmux = <0x401f8060 3 0x401f8434 2 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr03: IOMUXC_GPIO_EMC_19_SEMC_ADDR03 { + pinmux = <0x401f8060 0 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_src_bt_cfg1: IOMUXC_GPIO_EMC_19_SRC_BT_CFG1 { + pinmux = <0x401f8060 6 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_in17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_IN17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexio1_flexio24: IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 { + pinmux = <0x401f8064 4 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm1_pwma3: IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA3 { + pinmux = <0x401f8064 1 0x401f8334 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio2_io20: IOMUXC_GPIO_EMC_20_GPIO2_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart2_cts_b: IOMUXC_GPIO_EMC_20_LPUART2_CTS_B { + pinmux = <0x401f8064 2 0x401f83cc 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_sai1_mclk: IOMUXC_GPIO_EMC_20_SAI1_MCLK { + pinmux = <0x401f8064 3 0x401f8430 3 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr04: IOMUXC_GPIO_EMC_20_SEMC_ADDR04 { + pinmux = <0x401f8064 0 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_src_bt_cfg2: IOMUXC_GPIO_EMC_20_SRC_BT_CFG2 { + pinmux = <0x401f8064 6 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexio1_flexio25: IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 { + pinmux = <0x401f8068 4 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB3 { + pinmux = <0x401f8068 1 0x401f8344 1 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio2_io21: IOMUXC_GPIO_EMC_21_GPIO2_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpuart2_rts_b: IOMUXC_GPIO_EMC_21_LPUART2_RTS_B { + pinmux = <0x401f8068 2 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_sai1_rx_data0: IOMUXC_GPIO_EMC_21_SAI1_RX_DATA0 { + pinmux = <0x401f8068 3 0x401f8438 2 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_addr05: IOMUXC_GPIO_EMC_21_SEMC_ADDR05 { + pinmux = <0x401f8068 0 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_src_bt_cfg3: IOMUXC_GPIO_EMC_21_SRC_BT_CFG3 { + pinmux = <0x401f8068 6 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexio1_flexio26: IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 { + pinmux = <0x401f806c 4 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm1_pwma2: IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA2 { + pinmux = <0x401f806c 1 0x401f8330 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio2_io22: IOMUXC_GPIO_EMC_22_GPIO2_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpuart2_tx: IOMUXC_GPIO_EMC_22_LPUART2_TX { + pinmux = <0x401f806c 2 0x401f83d4 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_sai1_tx_data3: IOMUXC_GPIO_EMC_22_SAI1_TX_DATA3 { + pinmux = <0x401f806c 3 0x401f843c 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_addr06: IOMUXC_GPIO_EMC_22_SEMC_ADDR06 { + pinmux = <0x401f806c 0 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_src_bt_cfg4: IOMUXC_GPIO_EMC_22_SRC_BT_CFG4 { + pinmux = <0x401f806c 6 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexio1_flexio27: IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 { + pinmux = <0x401f8070 4 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB2 { + pinmux = <0x401f8070 1 0x401f8340 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio2_io23: IOMUXC_GPIO_EMC_23_GPIO2_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart2_rx: IOMUXC_GPIO_EMC_23_LPUART2_RX { + pinmux = <0x401f8070 2 0x401f83d0 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_sai1_tx_data2: IOMUXC_GPIO_EMC_23_SAI1_TX_DATA2 { + pinmux = <0x401f8070 3 0x401f8440 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr07: IOMUXC_GPIO_EMC_23_SEMC_ADDR07 { + pinmux = <0x401f8070 0 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_src_bt_cfg5: IOMUXC_GPIO_EMC_23_SRC_BT_CFG5 { + pinmux = <0x401f8070 6 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexio1_flexio28: IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 { + pinmux = <0x401f8074 4 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwma1: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA1 { + pinmux = <0x401f8074 1 0x401f832c 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio2_io24: IOMUXC_GPIO_EMC_24_GPIO2_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart8_cts_b: IOMUXC_GPIO_EMC_24_LPUART8_CTS_B { + pinmux = <0x401f8074 2 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_sai1_tx_data1: IOMUXC_GPIO_EMC_24_SAI1_TX_DATA1 { + pinmux = <0x401f8074 3 0x401f8444 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_addr08: IOMUXC_GPIO_EMC_24_SEMC_ADDR08 { + pinmux = <0x401f8074 0 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_src_bt_cfg6: IOMUXC_GPIO_EMC_24_SRC_BT_CFG6 { + pinmux = <0x401f8074 6 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexio1_flexio29: IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 { + pinmux = <0x401f8078 4 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB1 { + pinmux = <0x401f8078 1 0x401f833c 1 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio2_io25: IOMUXC_GPIO_EMC_25_GPIO2_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart8_rts_b: IOMUXC_GPIO_EMC_25_LPUART8_RTS_B { + pinmux = <0x401f8078 2 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_sai1_tx_data0: IOMUXC_GPIO_EMC_25_SAI1_TX_DATA0 { + pinmux = <0x401f8078 3 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_addr09: IOMUXC_GPIO_EMC_25_SEMC_ADDR09 { + pinmux = <0x401f8078 0 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_src_bt_cfg7: IOMUXC_GPIO_EMC_25_SRC_BT_CFG7 { + pinmux = <0x401f8078 6 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio30: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 { + pinmux = <0x401f807c 4 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwma0: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA0 { + pinmux = <0x401f807c 1 0x401f8328 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio2_io26: IOMUXC_GPIO_EMC_26_GPIO2_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart8_tx: IOMUXC_GPIO_EMC_26_LPUART8_TX { + pinmux = <0x401f807c 2 0x401f8408 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_sai1_tx_bclk: IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK { + pinmux = <0x401f807c 3 0x401f844c 2 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_addr11: IOMUXC_GPIO_EMC_26_SEMC_ADDR11 { + pinmux = <0x401f807c 0 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_src_bt_cfg8: IOMUXC_GPIO_EMC_26_SRC_BT_CFG8 { + pinmux = <0x401f807c 6 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio31: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 { + pinmux = <0x401f8080 4 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB0 { + pinmux = <0x401f8080 1 0x401f8338 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio2_io27: IOMUXC_GPIO_EMC_27_GPIO2_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart8_rx: IOMUXC_GPIO_EMC_27_LPUART8_RX { + pinmux = <0x401f8080 2 0x401f8404 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_sai1_tx_sync: IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC { + pinmux = <0x401f8080 3 0x401f8450 2 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_addr12: IOMUXC_GPIO_EMC_27_SEMC_ADDR12 { + pinmux = <0x401f8080 0 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_src_bt_cfg9: IOMUXC_GPIO_EMC_27_SRC_BT_CFG9 { + pinmux = <0x401f8080 6 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_ewm_out_b: IOMUXC_GPIO_EMC_28_EWM_OUT_B { + pinmux = <0x401f8084 4 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmx0: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX0 { + pinmux = <0x401f8084 7 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm2_pwma3: IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA3 { + pinmux = <0x401f8084 1 0x401f8354 1 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio2_io28: IOMUXC_GPIO_EMC_28_GPIO2_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpt2_capture2: IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2 { + pinmux = <0x401f8084 6 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_sai3_mclk: IOMUXC_GPIO_EMC_28_SAI3_MCLK { + pinmux = <0x401f8084 3 0x401f846c 2 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_dqs: IOMUXC_GPIO_EMC_28_SEMC_DQS { + pinmux = <0x401f8084 0 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_xbar1_xbar_in18: IOMUXC_GPIO_EMC_28_XBAR1_XBAR_IN18 { + pinmux = <0x401f8084 2 0x401f84bc 0 0x401f81f8>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_28_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f8084 2 0x401f84bc 0 0x401f81f8>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm1_pwmx1: IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX1 { + pinmux = <0x401f8088 7 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB3 { + pinmux = <0x401f8088 1 0x401f8364 1 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio2_io29: IOMUXC_GPIO_EMC_29_GPIO2_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpt2_compare2: IOMUXC_GPIO_EMC_29_GPT2_COMPARE2 { + pinmux = <0x401f8088 6 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_sai3_rx_bclk: IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK { + pinmux = <0x401f8088 3 0x401f8470 1 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cke: IOMUXC_GPIO_EMC_29_SEMC_CKE { + pinmux = <0x401f8088 0 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_wdog2_rst_b_deb: IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB { + pinmux = <0x401f8088 4 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_xbar1_xbar_in19: IOMUXC_GPIO_EMC_29_XBAR1_XBAR_IN19 { + pinmux = <0x401f8088 2 0x401f84c0 0 0x401f81fc>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_29_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f8088 2 0x401f84c0 0 0x401f81fc>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm1_pwmx2: IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX2 { + pinmux = <0x401f808c 7 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm2_pwma2: IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA2 { + pinmux = <0x401f808c 1 0x401f8350 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio2_io30: IOMUXC_GPIO_EMC_30_GPIO2_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpt2_compare3: IOMUXC_GPIO_EMC_30_GPT2_COMPARE3 { + pinmux = <0x401f808c 6 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart4_cts_b: IOMUXC_GPIO_EMC_30_LPUART4_CTS_B { + pinmux = <0x401f808c 2 0x401f83e0 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_sai3_rx_sync: IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC { + pinmux = <0x401f808c 3 0x401f8478 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_clk: IOMUXC_GPIO_EMC_30_SEMC_CLK { + pinmux = <0x401f808c 0 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_wdog1_rst_b_deb: IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB { + pinmux = <0x401f808c 4 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm1_pwmx3: IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX3 { + pinmux = <0x401f8090 7 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB2 { + pinmux = <0x401f8090 1 0x401f8360 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio2_io31: IOMUXC_GPIO_EMC_31_GPIO2_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpt2_clk: IOMUXC_GPIO_EMC_31_GPT2_CLK { + pinmux = <0x401f8090 6 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart4_rts_b: IOMUXC_GPIO_EMC_31_LPUART4_RTS_B { + pinmux = <0x401f8090 2 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_sai3_rx_data: IOMUXC_GPIO_EMC_31_SAI3_RX_DATA { + pinmux = <0x401f8090 3 0x401f8474 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_dm1: IOMUXC_GPIO_EMC_31_SEMC_DM1 { + pinmux = <0x401f8090 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_wdog2_b: IOMUXC_GPIO_EMC_31_WDOG2_B { + pinmux = <0x401f8090 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io00: IOMUXC_GPIO_EMC_32_GPIO3_IO00 { + pinmux = <0x401f8094 5 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpspi4_sck: IOMUXC_GPIO_EMC_32_LPSPI4_SCK { + pinmux = <0x401f8094 4 0x401f83c0 1 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart4_tx: IOMUXC_GPIO_EMC_32_LPUART4_TX { + pinmux = <0x401f8094 2 0x401f83e8 2 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_qtimer1_timer0: IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 { + pinmux = <0x401f8094 1 0x401f8410 1 0x401f8208>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ref_24m_out: IOMUXC_GPIO_EMC_32_REF_24M_OUT { + pinmux = <0x401f8094 7 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_sai3_tx_data: IOMUXC_GPIO_EMC_32_SAI3_TX_DATA { + pinmux = <0x401f8094 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data08: IOMUXC_GPIO_EMC_32_SEMC_DATA08 { + pinmux = <0x401f8094 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io01: IOMUXC_GPIO_EMC_33_GPIO3_IO01 { + pinmux = <0x401f8098 5 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpspi4_pcs0: IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 { + pinmux = <0x401f8098 4 0x401f83bc 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpuart4_rx: IOMUXC_GPIO_EMC_33_LPUART4_RX { + pinmux = <0x401f8098 2 0x401f83e4 2 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_qtimer1_timer1: IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 { + pinmux = <0x401f8098 1 0x401f8414 1 0x401f820c>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_tx_bclk: IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK { + pinmux = <0x401f8098 3 0x401f847c 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data09: IOMUXC_GPIO_EMC_33_SEMC_DATA09 { + pinmux = <0x401f8098 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_enet_crs: IOMUXC_GPIO_EMC_34_ENET_CRS { + pinmux = <0x401f809c 6 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io02: IOMUXC_GPIO_EMC_34_GPIO3_IO02 { + pinmux = <0x401f809c 5 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpspi4_sdo: IOMUXC_GPIO_EMC_34_LPSPI4_SDO { + pinmux = <0x401f809c 4 0x401f83c8 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpuart7_tx: IOMUXC_GPIO_EMC_34_LPUART7_TX { + pinmux = <0x401f809c 2 0x401f8400 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_qtimer1_timer2: IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 { + pinmux = <0x401f809c 1 0x401f8418 1 0x401f8210>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_tx_sync: IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC { + pinmux = <0x401f809c 3 0x401f8480 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data10: IOMUXC_GPIO_EMC_34_SEMC_DATA10 { + pinmux = <0x401f809c 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_enet_col: IOMUXC_GPIO_EMC_35_ENET_COL { + pinmux = <0x401f80a0 6 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io03: IOMUXC_GPIO_EMC_35_GPIO3_IO03 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpspi4_sdi: IOMUXC_GPIO_EMC_35_LPSPI4_SDI { + pinmux = <0x401f80a0 4 0x401f83c4 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpuart7_rx: IOMUXC_GPIO_EMC_35_LPUART7_RX { + pinmux = <0x401f80a0 2 0x401f83fc 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_qtimer1_timer3: IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 { + pinmux = <0x401f80a0 1 0x401f841c 1 0x401f8214>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data11: IOMUXC_GPIO_EMC_35_SEMC_DATA11 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc2_wp: IOMUXC_GPIO_EMC_35_USDHC2_WP { + pinmux = <0x401f80a0 3 0x401f849c 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_ccm_pmic_rdy: IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY { + pinmux = <0x401f80a4 3 0x401f8300 3 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_enet_rx_clk: IOMUXC_GPIO_EMC_36_ENET_RX_CLK { + pinmux = <0x401f80a4 6 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexpwm2_pwma1: IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA1 { + pinmux = <0x401f80a4 1 0x401f834c 1 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io04: IOMUXC_GPIO_EMC_36_GPIO3_IO04 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_lpspi4_pcs1: IOMUXC_GPIO_EMC_36_LPSPI4_PCS1 { + pinmux = <0x401f80a4 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_lpuart5_cts_b: IOMUXC_GPIO_EMC_36_LPUART5_CTS_B { + pinmux = <0x401f80a4 2 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data12: IOMUXC_GPIO_EMC_36_SEMC_DATA12 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 7 0x401f8494 4 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_enet_rx_data3: IOMUXC_GPIO_EMC_37_ENET_RX_DATA3 { + pinmux = <0x401f80a8 6 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB1 { + pinmux = <0x401f80a8 1 0x401f835c 1 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io05: IOMUXC_GPIO_EMC_37_GPIO3_IO05 { + pinmux = <0x401f80a8 5 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_lpspi4_pcs2: IOMUXC_GPIO_EMC_37_LPSPI4_PCS2 { + pinmux = <0x401f80a8 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_lpuart5_rts_b: IOMUXC_GPIO_EMC_37_LPUART5_RTS_B { + pinmux = <0x401f80a8 2 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_mqs_right: IOMUXC_GPIO_EMC_37_MQS_RIGHT { + pinmux = <0x401f80a8 3 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data13: IOMUXC_GPIO_EMC_37_SEMC_DATA13 { + pinmux = <0x401f80a8 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc1_vselect: IOMUXC_GPIO_EMC_37_USDHC1_VSELECT { + pinmux = <0x401f80a8 7 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_enet_rx_data2: IOMUXC_GPIO_EMC_38_ENET_RX_DATA2 { + pinmux = <0x401f80ac 6 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm2_pwma0: IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA0 { + pinmux = <0x401f80ac 1 0x401f8348 1 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io06: IOMUXC_GPIO_EMC_38_GPIO3_IO06 { + pinmux = <0x401f80ac 5 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpspi4_pcs3: IOMUXC_GPIO_EMC_38_LPSPI4_PCS3 { + pinmux = <0x401f80ac 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart5_tx: IOMUXC_GPIO_EMC_38_LPUART5_TX { + pinmux = <0x401f80ac 2 0x401f83f0 1 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_mqs_left: IOMUXC_GPIO_EMC_38_MQS_LEFT { + pinmux = <0x401f80ac 3 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_data14: IOMUXC_GPIO_EMC_38_SEMC_DATA14 { + pinmux = <0x401f80ac 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc1_cd_b: IOMUXC_GPIO_EMC_38_USDHC1_CD_B { + pinmux = <0x401f80ac 7 0x401f8490 3 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_enet_tx_er: IOMUXC_GPIO_EMC_39_ENET_TX_ER { + pinmux = <0x401f80b0 6 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB0 { + pinmux = <0x401f80b0 1 0x401f8358 1 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io07: IOMUXC_GPIO_EMC_39_GPIO3_IO07 { + pinmux = <0x401f80b0 5 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpt1_clk: IOMUXC_GPIO_EMC_39_GPT1_CLK { + pinmux = <0x401f80b0 7 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart5_rx: IOMUXC_GPIO_EMC_39_LPUART5_RX { + pinmux = <0x401f80b0 2 0x401f83ec 1 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_data15: IOMUXC_GPIO_EMC_39_SEMC_DATA15 { + pinmux = <0x401f80b0 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usb_otg1_oc: IOMUXC_GPIO_EMC_39_USB_OTG1_OC { + pinmux = <0x401f80b0 3 0x401f848c 2 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdio: IOMUXC_GPIO_EMC_40_ENET_MDIO { + pinmux = <0x401f80b4 4 0x401f8308 2 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_tx_data3: IOMUXC_GPIO_EMC_40_ENET_TX_DATA3 { + pinmux = <0x401f80b4 6 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io08: IOMUXC_GPIO_EMC_40_GPIO3_IO08 { + pinmux = <0x401f80b4 5 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt1_compare3: IOMUXC_GPIO_EMC_40_GPT1_COMPARE3 { + pinmux = <0x401f80b4 7 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_csx0: IOMUXC_GPIO_EMC_40_SEMC_CSX0 { + pinmux = <0x401f80b4 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_spdif_out: IOMUXC_GPIO_EMC_40_SPDIF_OUT { + pinmux = <0x401f80b4 2 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usb_otg1_id: IOMUXC_GPIO_EMC_40_USB_OTG1_ID { + pinmux = <0x401f80b4 3 0x401f82fc 2 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_xbar1_xbar_in18: IOMUXC_GPIO_EMC_40_XBAR1_XBAR_IN18 { + pinmux = <0x401f80b4 1 0x401f84bc 1 0x401f8228>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_40_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80b4 1 0x401f84bc 1 0x401f8228>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdc: IOMUXC_GPIO_EMC_41_ENET_MDC { + pinmux = <0x401f80b8 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_tx_data2: IOMUXC_GPIO_EMC_41_ENET_TX_DATA2 { + pinmux = <0x401f80b8 6 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io09: IOMUXC_GPIO_EMC_41_GPIO3_IO09 { + pinmux = <0x401f80b8 5 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt1_compare2: IOMUXC_GPIO_EMC_41_GPT1_COMPARE2 { + pinmux = <0x401f80b8 7 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_rdy: IOMUXC_GPIO_EMC_41_SEMC_RDY { + pinmux = <0x401f80b8 0 0x401f8484 1 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_spdif_in: IOMUXC_GPIO_EMC_41_SPDIF_IN { + pinmux = <0x401f80b8 2 0x401f8488 1 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usb_otg1_pwr: IOMUXC_GPIO_EMC_41_USB_OTG1_PWR { + pinmux = <0x401f80b8 3 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_xbar1_xbar_in19: IOMUXC_GPIO_EMC_41_XBAR1_XBAR_IN19 { + pinmux = <0x401f80b8 1 0x401f84c0 1 0x401f822c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_41_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80b8 1 0x401f84c0 1 0x401f822c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f813c 6 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io13: IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 { + pinmux = <0x401f813c 5 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f813c 4 0x401f838c 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_qtimer1_timer0: IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x401f8410 0 0x401f82b0>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_sai1_mclk: IOMUXC_GPIO_SD_B0_00_SAI1_MCLK { + pinmux = <0x401f813c 2 0x401f8430 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_sai2_mclk: IOMUXC_GPIO_SD_B0_00_SAI2_MCLK { + pinmux = <0x401f813c 3 0x401f8454 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_data2: IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 { + pinmux = <0x401f813c 0 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in14: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f813c 7 0x401f84a0 0 0x401f82b0>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout14: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f813c 7 0x401f84a0 0 0x401f82b0>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f8140 6 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io14: IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 { + pinmux = <0x401f8140 5 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f8140 4 0x401f8390 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_qtimer1_timer1: IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x401f8414 0 0x401f82b4>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_ref_24m_out: IOMUXC_GPIO_SD_B0_01_REF_24M_OUT { + pinmux = <0x401f8140 2 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_sai2_rx_sync: IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC { + pinmux = <0x401f8140 3 0x401f8460 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_data3: IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 { + pinmux = <0x401f8140 0 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in15: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8140 7 0x401f84a4 0 0x401f82b4>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout15: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8140 7 0x401f84a4 0 0x401f82b4>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_enet_mdio: IOMUXC_GPIO_SD_B0_02_ENET_MDIO { + pinmux = <0x401f8144 6 0x401f8308 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io15: IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 { + pinmux = <0x401f8144 5 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sck: IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK { + pinmux = <0x401f8144 4 0x401f83a0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart7_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B { + pinmux = <0x401f8144 2 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_qtimer1_timer2: IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x401f8418 0 0x401f82b8>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_sai2_rx_bclk: IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK { + pinmux = <0x401f8144 3 0x401f8458 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_cmd: IOMUXC_GPIO_SD_B0_02_USDHC1_CMD { + pinmux = <0x401f8144 0 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in16: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8144 7 0x401f84a8 0 0x401f82b8>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout16: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8144 7 0x401f84a8 0 0x401f82b8>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_enet_mdc: IOMUXC_GPIO_SD_B0_03_ENET_MDC { + pinmux = <0x401f8148 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io16: IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 { + pinmux = <0x401f8148 5 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0 { + pinmux = <0x401f8148 4 0x401f839c 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart7_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B { + pinmux = <0x401f8148 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_qtimer1_timer3: IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3 { + pinmux = <0x401f8148 1 0x401f841c 0 0x401f82bc>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_sai2_rx_data: IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA { + pinmux = <0x401f8148 3 0x401f845c 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_clk: IOMUXC_GPIO_SD_B0_03_USDHC1_CLK { + pinmux = <0x401f8148 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexcan2_tx: IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX { + pinmux = <0x401f814c 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f814c 6 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io17: IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 { + pinmux = <0x401f814c 5 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpspi1_sdo: IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO { + pinmux = <0x401f814c 4 0x401f83a8 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart7_tx: IOMUXC_GPIO_SD_B0_04_LPUART7_TX { + pinmux = <0x401f814c 2 0x401f8400 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_sai2_tx_data: IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA { + pinmux = <0x401f814c 3 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data0: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 { + pinmux = <0x401f814c 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexcan2_rx: IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX { + pinmux = <0x401f8150 1 0x401f8324 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f8150 6 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io18: IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 { + pinmux = <0x401f8150 5 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpspi1_sdi: IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI { + pinmux = <0x401f8150 4 0x401f83a4 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart7_rx: IOMUXC_GPIO_SD_B0_05_LPUART7_RX { + pinmux = <0x401f8150 2 0x401f83fc 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_sai2_tx_bclk: IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f8150 3 0x401f8464 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data1: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 { + pinmux = <0x401f8150 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_gpio3_io19: IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 { + pinmux = <0x401f8154 5 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_ref_32k_out: IOMUXC_GPIO_SD_B0_06_REF_32K_OUT { + pinmux = <0x401f8154 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_sai2_tx_sync: IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC { + pinmux = <0x401f8154 3 0x401f8468 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_usdhc1_cd_b: IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B { + pinmux = <0x401f8154 0 0x401f8490 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_usdhc1_reset_b: IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B { + pinmux = <0x401f8154 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_wdog1_b: IOMUXC_GPIO_SD_B0_06_WDOG1_B { + pinmux = <0x401f8154 4 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_xbar1_xbar_in17: IOMUXC_GPIO_SD_B0_06_XBAR1_XBAR_IN17 { + pinmux = <0x401f8154 6 0x401f84ac 0 0x401f82c8>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_xbar1_xbar_inout17: IOMUXC_GPIO_SD_B0_06_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8154 6 0x401f84ac 0 0x401f82c8>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexcan1_tx: IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX { + pinmux = <0x401f8158 4 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f8158 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io20: IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 { + pinmux = <0x401f8158 5 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart6_tx: IOMUXC_GPIO_SD_B1_00_LPUART6_TX { + pinmux = <0x401f8158 2 0x401f83f8 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data2: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 { + pinmux = <0x401f8158 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexcan1_rx: IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX { + pinmux = <0x401f815c 4 0x401f8320 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B { + pinmux = <0x401f815c 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK { + pinmux = <0x401f815c 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io21: IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 { + pinmux = <0x401f815c 5 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart6_rx: IOMUXC_GPIO_SD_B1_01_LPUART6_RX { + pinmux = <0x401f815c 2 0x401f83f4 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data3: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 { + pinmux = <0x401f815c 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_clko1: IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 { + pinmux = <0x401f8160 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_enet_1588_event1_out: IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT { + pinmux = <0x401f8160 4 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data0: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA0 { + pinmux = <0x401f8160 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io22: IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 { + pinmux = <0x401f8160 5 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpi2c4_scl: IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL { + pinmux = <0x401f8160 3 0x401f8394 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpuart8_tx: IOMUXC_GPIO_SD_B1_02_LPUART8_TX { + pinmux = <0x401f8160 2 0x401f8408 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_cmd: IOMUXC_GPIO_SD_B1_02_USDHC2_CMD { + pinmux = <0x401f8160 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_clko2: IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 { + pinmux = <0x401f8164 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_enet_1588_event1_in: IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN { + pinmux = <0x401f8164 4 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data2: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA2 { + pinmux = <0x401f8164 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io23: IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 { + pinmux = <0x401f8164 5 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpi2c4_sda: IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA { + pinmux = <0x401f8164 3 0x401f8398 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpuart8_rx: IOMUXC_GPIO_SD_B1_03_LPUART8_RX { + pinmux = <0x401f8164 2 0x401f8404 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_clk: IOMUXC_GPIO_SD_B1_03_USDHC2_CLK { + pinmux = <0x401f8164 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_wait: IOMUXC_GPIO_SD_B1_04_CCM_WAIT { + pinmux = <0x401f8168 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_ref_clk: IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK { + pinmux = <0x401f8168 3 0x401f8304 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_tx_clk: IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK { + pinmux = <0x401f8168 2 0x401f831c 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ewm_out_b: IOMUXC_GPIO_SD_B1_04_EWM_OUT_B { + pinmux = <0x401f8168 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_data1: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA1 { + pinmux = <0x401f8168 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io24: IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 { + pinmux = <0x401f8168 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_data0: IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f8168 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY { + pinmux = <0x401f816c 6 0x401f8300 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_enet_rx_data1: IOMUXC_GPIO_SD_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f816c 2 0x401f8310 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f816c 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f816c 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io25: IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 { + pinmux = <0x401f816c 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_mclk: IOMUXC_GPIO_SD_B1_05_SAI3_MCLK { + pinmux = <0x401f816c 3 0x401f846c 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_data1: IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f816c 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_ccm_stop: IOMUXC_GPIO_SD_B1_06_CCM_STOP { + pinmux = <0x401f8170 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_enet_rx_data0: IOMUXC_GPIO_SD_B1_06_ENET_RX_DATA0 { + pinmux = <0x401f8170 2 0x401f830c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_data3: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA3 { + pinmux = <0x401f8170 1 0x401f8374 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io26: IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 { + pinmux = <0x401f8170 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f8170 4 0x401f83ac 2 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK { + pinmux = <0x401f8170 3 0x401f847c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_cd_b: IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B { + pinmux = <0x401f8170 0 0x401f8498 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_enet_rx_en: IOMUXC_GPIO_SD_B1_07_ENET_RX_EN { + pinmux = <0x401f8174 2 0x401f8314 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f8174 1 0x401f8378 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io27: IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 { + pinmux = <0x401f8174 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f8174 4 0x401f83b0 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai3_tx_sync: IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC { + pinmux = <0x401f8174 3 0x401f8480 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B { + pinmux = <0x401f8174 0 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_enet_rx_er: IOMUXC_GPIO_SD_B1_08_ENET_RX_ER { + pinmux = <0x401f8178 2 0x401f8318 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f8178 1 0x401f8368 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io28: IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 { + pinmux = <0x401f8178 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f8178 4 0x401f83b8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai3_tx_data: IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA { + pinmux = <0x401f8178 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f8178 0 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_enet_tx_en: IOMUXC_GPIO_SD_B1_09_ENET_TX_EN { + pinmux = <0x401f817c 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data2: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA2 { + pinmux = <0x401f817c 1 0x401f8370 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io29: IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 { + pinmux = <0x401f817c 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f817c 4 0x401f83b4 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK { + pinmux = <0x401f817c 3 0x401f8470 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f817c 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_enet_tx_data0: IOMUXC_GPIO_SD_B1_10_ENET_TX_DATA0 { + pinmux = <0x401f8180 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data1: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA1 { + pinmux = <0x401f8180 1 0x401f836c 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io30: IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 { + pinmux = <0x401f8180 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f8180 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_sai3_rx_sync: IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC { + pinmux = <0x401f8180 3 0x401f8478 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f8180 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_enet_tx_data1: IOMUXC_GPIO_SD_B1_11_ENET_TX_DATA1 { + pinmux = <0x401f8184 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B { + pinmux = <0x401f8184 1 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io31: IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 { + pinmux = <0x401f8184 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8184 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_sai3_rx_data: IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA { + pinmux = <0x401f8184 3 0x401f8474 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8184 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_ccm_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ { + pinmux = <0x400a8008 0 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_gpio5_io02: IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 { + pinmux = <0x400a8008 5 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x401f840c 1 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1021daf5b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1021daf5b-pinctrl.dtsi new file mode 100644 index 000000000..9ca622b7e --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1021daf5b-pinctrl.dtsi @@ -0,0 +1,1284 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1021DAF5B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpt1_compare1: IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 { + pinmux = <0x401f80bc 7 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_jtag_tms: IOMUXC_GPIO_AD_B0_00_JTAG_TMS { + pinmux = <0x401f80bc 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpt1_capture2: IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 { + pinmux = <0x401f80c0 7 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_jtag_tck: IOMUXC_GPIO_AD_B0_01_JTAG_TCK { + pinmux = <0x401f80c0 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpt1_capture1: IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 { + pinmux = <0x401f80c4 7 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_jtag_mod: IOMUXC_GPIO_AD_B0_02_JTAG_MOD { + pinmux = <0x401f80c4 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY { + pinmux = <0x401f80c8 7 0x401f8300 2 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_jtag_tdi: IOMUXC_GPIO_AD_B0_03_JTAG_TDI { + pinmux = <0x401f80c8 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_sai1_mclk: IOMUXC_GPIO_AD_B0_03_SAI1_MCLK { + pinmux = <0x401f80c8 3 0x401f8430 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 6 0x401f848c 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc1_wp: IOMUXC_GPIO_AD_B0_03_USDHC1_WP { + pinmux = <0x401f80c8 4 0x401f8494 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B { + pinmux = <0x401f80c8 1 0x401f8498 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_wdog1_b: IOMUXC_GPIO_AD_B0_03_WDOG1_B { + pinmux = <0x401f80c8 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_mdio: IOMUXC_GPIO_AD_B0_04_ENET_MDIO { + pinmux = <0x401f80cc 4 0x401f8308 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_ewm_out_b: IOMUXC_GPIO_AD_B0_04_EWM_OUT_B { + pinmux = <0x401f80cc 7 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_flexcan1_tx: IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX { + pinmux = <0x401f80cc 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_jtag_tdo: IOMUXC_GPIO_AD_B0_04_JTAG_TDO { + pinmux = <0x401f80cc 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_qtimer2_timer0: IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 { + pinmux = <0x401f80cc 3 0x401f8420 1 0x401f8240>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR { + pinmux = <0x401f80cc 6 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usdhc1_wp: IOMUXC_GPIO_AD_B0_04_USDHC1_WP { + pinmux = <0x401f80cc 2 0x401f8494 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_arm_nmi: IOMUXC_GPIO_AD_B0_05_ARM_NMI { + pinmux = <0x401f80d0 7 0x401f840c 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_mdc: IOMUXC_GPIO_AD_B0_05_ENET_MDC { + pinmux = <0x401f80d0 4 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_flexcan1_rx: IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX { + pinmux = <0x401f80d0 1 0x401f8320 2 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_jtag_trstb: IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB { + pinmux = <0x401f80d0 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_qtimer2_timer1: IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 { + pinmux = <0x401f80d0 3 0x401f8424 1 0x401f8244>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usb_otg1_id: IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID { + pinmux = <0x401f80d0 6 0x401f82fc 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usdhc1_cd_b: IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B { + pinmux = <0x401f80d0 2 0x401f8490 1 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA3 { + pinmux = <0x401f80d4 4 0x401f8354 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpuart1_tx: IOMUXC_GPIO_AD_B0_06_LPUART1_TX { + pinmux = <0x401f80d4 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_mqs_right: IOMUXC_GPIO_AD_B0_06_MQS_RIGHT { + pinmux = <0x401f80d4 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_pit_trigger0: IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER0 { + pinmux = <0x401f80d4 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_qtimer2_timer2: IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 { + pinmux = <0x401f80d4 3 0x401f8428 1 0x401f8248>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_ref_32k_out: IOMUXC_GPIO_AD_B0_06_REF_32K_OUT { + pinmux = <0x401f80d4 6 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_flexpwm2_pwmb3: IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB3 { + pinmux = <0x401f80d8 4 0x401f8364 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_lpuart1_rx: IOMUXC_GPIO_AD_B0_07_LPUART1_RX { + pinmux = <0x401f80d8 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_mqs_left: IOMUXC_GPIO_AD_B0_07_MQS_LEFT { + pinmux = <0x401f80d8 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_pit_trigger1: IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER1 { + pinmux = <0x401f80d8 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_qtimer2_timer3: IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 { + pinmux = <0x401f80d8 3 0x401f842c 1 0x401f824c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_ref_24m_out: IOMUXC_GPIO_AD_B0_07_REF_24M_OUT { + pinmux = <0x401f80d8 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_acmp1_in4: IOMUXC_GPIO_AD_B0_08_ACMP1_IN4 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_arm_cm7_txev: IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV { + pinmux = <0x401f80dc 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_ref_clk: IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK { + pinmux = <0x401f80dc 4 0x401f8304 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_tx_clk: IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK { + pinmux = <0x401f80dc 0 0x401f831c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_kpp_col0: IOMUXC_GPIO_AD_B0_08_KPP_COL0 { + pinmux = <0x401f80dc 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpi2c3_scl: IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL { + pinmux = <0x401f80dc 1 0x401f838c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B { + pinmux = <0x401f80dc 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_acmp2_in4: IOMUXC_GPIO_AD_B0_09_ACMP2_IN4 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_arm_cm7_rxev: IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV { + pinmux = <0x401f80e0 6 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data1: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA1 { + pinmux = <0x401f80e0 0 0x401f8310 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_kpp_row0: IOMUXC_GPIO_AD_B0_09_KPP_ROW0 { + pinmux = <0x401f80e0 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpi2c3_sda: IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA { + pinmux = <0x401f80e0 1 0x401f8390 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B { + pinmux = <0x401f80e0 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_acmp3_in4: IOMUXC_GPIO_AD_B0_10_ACMP3_IN4 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_clk: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_CLK { + pinmux = <0x401f80e4 6 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_rx_data0: IOMUXC_GPIO_AD_B0_10_ENET_RX_DATA0 { + pinmux = <0x401f80e4 0 0x401f830c 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f80e4 4 0x401f8350 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_kpp_col1: IOMUXC_GPIO_AD_B0_10_KPP_COL1 { + pinmux = <0x401f80e4 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpspi1_sck: IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK { + pinmux = <0x401f80e4 1 0x401f83a0 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpuart5_tx: IOMUXC_GPIO_AD_B0_10_LPUART5_TX { + pinmux = <0x401f80e4 2 0x401f83f0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_acmp4_in4: IOMUXC_GPIO_AD_B0_11_ACMP4_IN4 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_arm_trace_swo: IOMUXC_GPIO_AD_B0_11_ARM_TRACE_SWO { + pinmux = <0x401f80e8 6 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_rx_en: IOMUXC_GPIO_AD_B0_11_ENET_RX_EN { + pinmux = <0x401f80e8 0 0x401f8314 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f80e8 4 0x401f8360 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_kpp_row1: IOMUXC_GPIO_AD_B0_11_KPP_ROW1 { + pinmux = <0x401f80e8 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpspi1_pcs0: IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 { + pinmux = <0x401f80e8 1 0x401f839c 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpuart5_rx: IOMUXC_GPIO_AD_B0_11_LPUART5_RX { + pinmux = <0x401f80e8 2 0x401f83ec 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in0: IOMUXC_GPIO_AD_B0_12_ADC1_IN0 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_trace0: IOMUXC_GPIO_AD_B0_12_ARM_TRACE0 { + pinmux = <0x401f80ec 6 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_rx_er: IOMUXC_GPIO_AD_B0_12_ENET_RX_ER { + pinmux = <0x401f80ec 0 0x401f8318 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm2_pwma1: IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA1 { + pinmux = <0x401f80ec 4 0x401f834c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_kpp_col2: IOMUXC_GPIO_AD_B0_12_KPP_COL2 { + pinmux = <0x401f80ec 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpspi1_sdo: IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO { + pinmux = <0x401f80ec 1 0x401f83a8 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart3_cts_b: IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B { + pinmux = <0x401f80ec 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_snvs_vio_5_ctl: IOMUXC_GPIO_AD_B0_12_SNVS_VIO_5_CTL { + pinmux = <0x401f80ec 7 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc2_in0: IOMUXC_GPIO_AD_B0_13_ADC2_IN0 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_tx_en: IOMUXC_GPIO_AD_B0_13_ENET_TX_EN { + pinmux = <0x401f80f0 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm2_pwmb1: IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB1 { + pinmux = <0x401f80f0 4 0x401f835c 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_kpp_row2: IOMUXC_GPIO_AD_B0_13_KPP_ROW2 { + pinmux = <0x401f80f0 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpspi1_sdi: IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI { + pinmux = <0x401f80f0 1 0x401f83a4 1 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart3_rts_b: IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B { + pinmux = <0x401f80f0 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_snvs_vio_5_b: IOMUXC_GPIO_AD_B0_13_SNVS_VIO_5_B { + pinmux = <0x401f80f0 7 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp1_in0: IOMUXC_GPIO_AD_B0_14_ACMP1_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in0: IOMUXC_GPIO_AD_B0_14_ACMP2_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp3_in0: IOMUXC_GPIO_AD_B0_14_ACMP3_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp4_in0: IOMUXC_GPIO_AD_B0_14_ACMP4_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in1: IOMUXC_GPIO_AD_B0_14_ADC1_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc2_in1: IOMUXC_GPIO_AD_B0_14_ADC2_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_tx_data0: IOMUXC_GPIO_AD_B0_14_ENET_TX_DATA0 { + pinmux = <0x401f80f4 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexpwm2_pwma0: IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA0 { + pinmux = <0x401f80f4 4 0x401f8348 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_kpp_col3: IOMUXC_GPIO_AD_B0_14_KPP_COL3 { + pinmux = <0x401f80f4 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart3_tx: IOMUXC_GPIO_AD_B0_14_LPUART3_TX { + pinmux = <0x401f80f4 2 0x401f83dc 1 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_wdog1_any: IOMUXC_GPIO_AD_B0_14_WDOG1_ANY { + pinmux = <0x401f80f4 7 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp1_in1: IOMUXC_GPIO_AD_B0_15_ACMP1_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp2_in1: IOMUXC_GPIO_AD_B0_15_ACMP2_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in1: IOMUXC_GPIO_AD_B0_15_ACMP3_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp4_in1: IOMUXC_GPIO_AD_B0_15_ACMP4_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in2: IOMUXC_GPIO_AD_B0_15_ADC1_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc2_in2: IOMUXC_GPIO_AD_B0_15_ADC2_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_tx_data1: IOMUXC_GPIO_AD_B0_15_ENET_TX_DATA1 { + pinmux = <0x401f80f8 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 1 0x401f8324 2 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexpwm2_pwmb0: IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB0 { + pinmux = <0x401f80f8 4 0x401f8358 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_kpp_row3: IOMUXC_GPIO_AD_B0_15_KPP_ROW3 { + pinmux = <0x401f80f8 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart3_rx: IOMUXC_GPIO_AD_B0_15_LPUART3_RX { + pinmux = <0x401f80f8 2 0x401f83d8 1 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_acmp3_in5: IOMUXC_GPIO_AD_B1_10_ACMP3_IN5 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in10: IOMUXC_GPIO_AD_B1_10_ADC1_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc2_in10: IOMUXC_GPIO_AD_B1_10_ADC2_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio1_flexio05: IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8124 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexpwm1_pwma2: IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA2 { + pinmux = <0x401f8124 1 0x401f8330 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpt2_capture1: IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 { + pinmux = <0x401f8124 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart4_tx: IOMUXC_GPIO_AD_B1_10_LPUART4_TX { + pinmux = <0x401f8124 2 0x401f83e8 1 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR { + pinmux = <0x401f8124 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B { + pinmux = <0x401f8124 3 0x401f8490 2 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_acmp4_in5: IOMUXC_GPIO_AD_B1_11_ACMP4_IN5 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in11: IOMUXC_GPIO_AD_B1_11_ADC1_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc2_in11: IOMUXC_GPIO_AD_B1_11_ADC2_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio1_flexio04: IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8128 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexpwm1_pwmb2: IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB2 { + pinmux = <0x401f8128 1 0x401f8340 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpt2_compare1: IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 { + pinmux = <0x401f8128 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart4_rx: IOMUXC_GPIO_AD_B1_11_LPUART4_RX { + pinmux = <0x401f8128 2 0x401f83e4 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usb_otg1_id: IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID { + pinmux = <0x401f8128 0 0x401f82fc 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usdhc1_wp: IOMUXC_GPIO_AD_B1_11_USDHC1_WP { + pinmux = <0x401f8128 3 0x401f8494 3 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_in6: IOMUXC_GPIO_AD_B1_12_ACMP1_IN6 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_out: IOMUXC_GPIO_AD_B1_12_ACMP1_OUT { + pinmux = <0x401f812c 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc1_in12: IOMUXC_GPIO_AD_B1_12_ADC1_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc2_in12: IOMUXC_GPIO_AD_B1_12_ADC2_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio1_flexio03: IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 { + pinmux = <0x401f812c 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexpwm1_pwma3: IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f812c 6 0x401f8334 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_lpspi3_sck: IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK { + pinmux = <0x401f812c 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usb_otg1_oc: IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC { + pinmux = <0x401f812c 0 0x401f848c 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B { + pinmux = <0x401f812c 3 0x401f8498 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_in6: IOMUXC_GPIO_AD_B1_13_ACMP2_IN6 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_out: IOMUXC_GPIO_AD_B1_13_ACMP2_OUT { + pinmux = <0x401f8130 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc1_in13: IOMUXC_GPIO_AD_B1_13_ADC1_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc2_in13: IOMUXC_GPIO_AD_B1_13_ADC2_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio1_flexio02: IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 { + pinmux = <0x401f8130 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8130 6 0x401f8344 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpi2c1_hreq: IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ { + pinmux = <0x401f8130 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpspi3_pcs0: IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 { + pinmux = <0x401f8130 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_usdhc2_wp: IOMUXC_GPIO_AD_B1_13_USDHC2_WP { + pinmux = <0x401f8130 3 0x401f849c 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_in6: IOMUXC_GPIO_AD_B1_14_ACMP3_IN6 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_out: IOMUXC_GPIO_AD_B1_14_ACMP3_OUT { + pinmux = <0x401f8134 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc1_in14: IOMUXC_GPIO_AD_B1_14_ADC1_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc2_in14: IOMUXC_GPIO_AD_B1_14_ADC2_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f8134 3 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio1_flexio01: IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8134 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpi2c1_scl: IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL { + pinmux = <0x401f8134 0 0x401f837c 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpspi3_sdo: IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO { + pinmux = <0x401f8134 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_in6: IOMUXC_GPIO_AD_B1_15_ACMP4_IN6 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_out: IOMUXC_GPIO_AD_B1_15_ACMP4_OUT { + pinmux = <0x401f8138 1 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc1_in15: IOMUXC_GPIO_AD_B1_15_ADC1_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc2_in15: IOMUXC_GPIO_AD_B1_15_ADC2_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f8138 3 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio1_flexio00: IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8138 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpi2c1_sda: IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA { + pinmux = <0x401f8138 0 0x401f8380 1 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpspi3_sdi: IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI { + pinmux = <0x401f8138 2 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio16: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 { + pinmux = <0x401f8024 4 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio2_io04: IOMUXC_GPIO_EMC_04_GPIO2_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_bclk: IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK { + pinmux = <0x401f8024 3 0x401f8464 1 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_spdif_out: IOMUXC_GPIO_EMC_04_SPDIF_OUT { + pinmux = <0x401f8024 2 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio17: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 { + pinmux = <0x401f8028 4 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio2_io05: IOMUXC_GPIO_EMC_05_GPIO2_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 3 0x401f8468 1 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_spdif_in: IOMUXC_GPIO_EMC_05_SPDIF_IN { + pinmux = <0x401f8028 2 0x401f8488 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio18: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 { + pinmux = <0x401f802c 4 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio2_io06: IOMUXC_GPIO_EMC_06_GPIO2_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_lpuart3_tx: IOMUXC_GPIO_EMC_06_LPUART3_TX { + pinmux = <0x401f802c 2 0x401f83dc 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_data: IOMUXC_GPIO_EMC_06_SAI2_TX_DATA { + pinmux = <0x401f802c 3 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio19: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 { + pinmux = <0x401f8030 4 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio2_io07: IOMUXC_GPIO_EMC_07_GPIO2_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_lpuart3_rx: IOMUXC_GPIO_EMC_07_LPUART3_RX { + pinmux = <0x401f8030 2 0x401f83d8 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_rx_sync: IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC { + pinmux = <0x401f8030 3 0x401f8460 1 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexcan2_tx: IOMUXC_GPIO_EMC_08_FLEXCAN2_TX { + pinmux = <0x401f8034 2 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio20: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 { + pinmux = <0x401f8034 4 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio2_io08: IOMUXC_GPIO_EMC_08_GPIO2_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 3 0x401f845c 1 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_rx: IOMUXC_GPIO_EMC_09_FLEXCAN2_RX { + pinmux = <0x401f8038 2 0x401f8324 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio21: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 { + pinmux = <0x401f8038 4 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio2_io09: IOMUXC_GPIO_EMC_09_GPIO2_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_bclk: IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK { + pinmux = <0x401f8038 3 0x401f8458 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_we: IOMUXC_GPIO_EMC_09_SEMC_WE { + pinmux = <0x401f8038 0 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_in09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_IN09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio2_io16: IOMUXC_GPIO_EMC_16_GPIO2_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_mqs_right: IOMUXC_GPIO_EMC_16_MQS_RIGHT { + pinmux = <0x401f8054 2 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_sai2_mclk: IOMUXC_GPIO_EMC_16_SAI2_MCLK { + pinmux = <0x401f8054 3 0x401f8454 1 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr00: IOMUXC_GPIO_EMC_16_SEMC_ADDR00 { + pinmux = <0x401f8054 0 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_src_boot_mode0: IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE0 { + pinmux = <0x401f8054 6 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio2_io17: IOMUXC_GPIO_EMC_17_GPIO2_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_mqs_left: IOMUXC_GPIO_EMC_17_MQS_LEFT { + pinmux = <0x401f8058 2 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_sai3_mclk: IOMUXC_GPIO_EMC_17_SAI3_MCLK { + pinmux = <0x401f8058 3 0x401f846c 1 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr01: IOMUXC_GPIO_EMC_17_SEMC_ADDR01 { + pinmux = <0x401f8058 0 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_src_boot_mode1: IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE1 { + pinmux = <0x401f8058 6 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexio1_flexio22: IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 { + pinmux = <0x401f805c 4 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio2_io18: IOMUXC_GPIO_EMC_18_GPIO2_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpi2c2_sda: IOMUXC_GPIO_EMC_18_LPI2C2_SDA { + pinmux = <0x401f805c 2 0x401f8388 1 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_sai1_rx_sync: IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC { + pinmux = <0x401f805c 3 0x401f8448 2 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr02: IOMUXC_GPIO_EMC_18_SEMC_ADDR02 { + pinmux = <0x401f805c 0 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_src_bt_cfg0: IOMUXC_GPIO_EMC_18_SRC_BT_CFG0 { + pinmux = <0x401f805c 6 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_IN16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexio1_flexio23: IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 { + pinmux = <0x401f8060 4 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio2_io19: IOMUXC_GPIO_EMC_19_GPIO2_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpi2c2_scl: IOMUXC_GPIO_EMC_19_LPI2C2_SCL { + pinmux = <0x401f8060 2 0x401f8384 1 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_sai1_rx_bclk: IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK { + pinmux = <0x401f8060 3 0x401f8434 2 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr03: IOMUXC_GPIO_EMC_19_SEMC_ADDR03 { + pinmux = <0x401f8060 0 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_src_bt_cfg1: IOMUXC_GPIO_EMC_19_SRC_BT_CFG1 { + pinmux = <0x401f8060 6 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_in17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_IN17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexio1_flexio24: IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 { + pinmux = <0x401f8064 4 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm1_pwma3: IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA3 { + pinmux = <0x401f8064 1 0x401f8334 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio2_io20: IOMUXC_GPIO_EMC_20_GPIO2_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart2_cts_b: IOMUXC_GPIO_EMC_20_LPUART2_CTS_B { + pinmux = <0x401f8064 2 0x401f83cc 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_sai1_mclk: IOMUXC_GPIO_EMC_20_SAI1_MCLK { + pinmux = <0x401f8064 3 0x401f8430 3 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr04: IOMUXC_GPIO_EMC_20_SEMC_ADDR04 { + pinmux = <0x401f8064 0 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_src_bt_cfg2: IOMUXC_GPIO_EMC_20_SRC_BT_CFG2 { + pinmux = <0x401f8064 6 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexio1_flexio25: IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 { + pinmux = <0x401f8068 4 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB3 { + pinmux = <0x401f8068 1 0x401f8344 1 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio2_io21: IOMUXC_GPIO_EMC_21_GPIO2_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpuart2_rts_b: IOMUXC_GPIO_EMC_21_LPUART2_RTS_B { + pinmux = <0x401f8068 2 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_sai1_rx_data0: IOMUXC_GPIO_EMC_21_SAI1_RX_DATA0 { + pinmux = <0x401f8068 3 0x401f8438 2 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_addr05: IOMUXC_GPIO_EMC_21_SEMC_ADDR05 { + pinmux = <0x401f8068 0 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_src_bt_cfg3: IOMUXC_GPIO_EMC_21_SRC_BT_CFG3 { + pinmux = <0x401f8068 6 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexio1_flexio26: IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 { + pinmux = <0x401f806c 4 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm1_pwma2: IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA2 { + pinmux = <0x401f806c 1 0x401f8330 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio2_io22: IOMUXC_GPIO_EMC_22_GPIO2_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpuart2_tx: IOMUXC_GPIO_EMC_22_LPUART2_TX { + pinmux = <0x401f806c 2 0x401f83d4 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_sai1_tx_data3: IOMUXC_GPIO_EMC_22_SAI1_TX_DATA3 { + pinmux = <0x401f806c 3 0x401f843c 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_addr06: IOMUXC_GPIO_EMC_22_SEMC_ADDR06 { + pinmux = <0x401f806c 0 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_src_bt_cfg4: IOMUXC_GPIO_EMC_22_SRC_BT_CFG4 { + pinmux = <0x401f806c 6 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexio1_flexio27: IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 { + pinmux = <0x401f8070 4 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB2 { + pinmux = <0x401f8070 1 0x401f8340 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio2_io23: IOMUXC_GPIO_EMC_23_GPIO2_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart2_rx: IOMUXC_GPIO_EMC_23_LPUART2_RX { + pinmux = <0x401f8070 2 0x401f83d0 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_sai1_tx_data2: IOMUXC_GPIO_EMC_23_SAI1_TX_DATA2 { + pinmux = <0x401f8070 3 0x401f8440 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr07: IOMUXC_GPIO_EMC_23_SEMC_ADDR07 { + pinmux = <0x401f8070 0 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_src_bt_cfg5: IOMUXC_GPIO_EMC_23_SRC_BT_CFG5 { + pinmux = <0x401f8070 6 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexio1_flexio28: IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 { + pinmux = <0x401f8074 4 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwma1: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA1 { + pinmux = <0x401f8074 1 0x401f832c 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio2_io24: IOMUXC_GPIO_EMC_24_GPIO2_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart8_cts_b: IOMUXC_GPIO_EMC_24_LPUART8_CTS_B { + pinmux = <0x401f8074 2 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_sai1_tx_data1: IOMUXC_GPIO_EMC_24_SAI1_TX_DATA1 { + pinmux = <0x401f8074 3 0x401f8444 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_addr08: IOMUXC_GPIO_EMC_24_SEMC_ADDR08 { + pinmux = <0x401f8074 0 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_src_bt_cfg6: IOMUXC_GPIO_EMC_24_SRC_BT_CFG6 { + pinmux = <0x401f8074 6 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexio1_flexio29: IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 { + pinmux = <0x401f8078 4 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB1 { + pinmux = <0x401f8078 1 0x401f833c 1 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio2_io25: IOMUXC_GPIO_EMC_25_GPIO2_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart8_rts_b: IOMUXC_GPIO_EMC_25_LPUART8_RTS_B { + pinmux = <0x401f8078 2 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_sai1_tx_data0: IOMUXC_GPIO_EMC_25_SAI1_TX_DATA0 { + pinmux = <0x401f8078 3 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_addr09: IOMUXC_GPIO_EMC_25_SEMC_ADDR09 { + pinmux = <0x401f8078 0 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_src_bt_cfg7: IOMUXC_GPIO_EMC_25_SRC_BT_CFG7 { + pinmux = <0x401f8078 6 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio30: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 { + pinmux = <0x401f807c 4 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwma0: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA0 { + pinmux = <0x401f807c 1 0x401f8328 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio2_io26: IOMUXC_GPIO_EMC_26_GPIO2_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart8_tx: IOMUXC_GPIO_EMC_26_LPUART8_TX { + pinmux = <0x401f807c 2 0x401f8408 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_sai1_tx_bclk: IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK { + pinmux = <0x401f807c 3 0x401f844c 2 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_addr11: IOMUXC_GPIO_EMC_26_SEMC_ADDR11 { + pinmux = <0x401f807c 0 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_src_bt_cfg8: IOMUXC_GPIO_EMC_26_SRC_BT_CFG8 { + pinmux = <0x401f807c 6 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio31: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 { + pinmux = <0x401f8080 4 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB0 { + pinmux = <0x401f8080 1 0x401f8338 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio2_io27: IOMUXC_GPIO_EMC_27_GPIO2_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart8_rx: IOMUXC_GPIO_EMC_27_LPUART8_RX { + pinmux = <0x401f8080 2 0x401f8404 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_sai1_tx_sync: IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC { + pinmux = <0x401f8080 3 0x401f8450 2 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_addr12: IOMUXC_GPIO_EMC_27_SEMC_ADDR12 { + pinmux = <0x401f8080 0 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_src_bt_cfg9: IOMUXC_GPIO_EMC_27_SRC_BT_CFG9 { + pinmux = <0x401f8080 6 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io00: IOMUXC_GPIO_EMC_32_GPIO3_IO00 { + pinmux = <0x401f8094 5 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpspi4_sck: IOMUXC_GPIO_EMC_32_LPSPI4_SCK { + pinmux = <0x401f8094 4 0x401f83c0 1 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart4_tx: IOMUXC_GPIO_EMC_32_LPUART4_TX { + pinmux = <0x401f8094 2 0x401f83e8 2 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_qtimer1_timer0: IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 { + pinmux = <0x401f8094 1 0x401f8410 1 0x401f8208>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ref_24m_out: IOMUXC_GPIO_EMC_32_REF_24M_OUT { + pinmux = <0x401f8094 7 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_sai3_tx_data: IOMUXC_GPIO_EMC_32_SAI3_TX_DATA { + pinmux = <0x401f8094 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data08: IOMUXC_GPIO_EMC_32_SEMC_DATA08 { + pinmux = <0x401f8094 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io01: IOMUXC_GPIO_EMC_33_GPIO3_IO01 { + pinmux = <0x401f8098 5 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpspi4_pcs0: IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 { + pinmux = <0x401f8098 4 0x401f83bc 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpuart4_rx: IOMUXC_GPIO_EMC_33_LPUART4_RX { + pinmux = <0x401f8098 2 0x401f83e4 2 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_qtimer1_timer1: IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 { + pinmux = <0x401f8098 1 0x401f8414 1 0x401f820c>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_tx_bclk: IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK { + pinmux = <0x401f8098 3 0x401f847c 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data09: IOMUXC_GPIO_EMC_33_SEMC_DATA09 { + pinmux = <0x401f8098 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_enet_crs: IOMUXC_GPIO_EMC_34_ENET_CRS { + pinmux = <0x401f809c 6 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io02: IOMUXC_GPIO_EMC_34_GPIO3_IO02 { + pinmux = <0x401f809c 5 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpspi4_sdo: IOMUXC_GPIO_EMC_34_LPSPI4_SDO { + pinmux = <0x401f809c 4 0x401f83c8 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpuart7_tx: IOMUXC_GPIO_EMC_34_LPUART7_TX { + pinmux = <0x401f809c 2 0x401f8400 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_qtimer1_timer2: IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 { + pinmux = <0x401f809c 1 0x401f8418 1 0x401f8210>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_tx_sync: IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC { + pinmux = <0x401f809c 3 0x401f8480 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data10: IOMUXC_GPIO_EMC_34_SEMC_DATA10 { + pinmux = <0x401f809c 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_enet_col: IOMUXC_GPIO_EMC_35_ENET_COL { + pinmux = <0x401f80a0 6 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io03: IOMUXC_GPIO_EMC_35_GPIO3_IO03 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpspi4_sdi: IOMUXC_GPIO_EMC_35_LPSPI4_SDI { + pinmux = <0x401f80a0 4 0x401f83c4 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpuart7_rx: IOMUXC_GPIO_EMC_35_LPUART7_RX { + pinmux = <0x401f80a0 2 0x401f83fc 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_qtimer1_timer3: IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 { + pinmux = <0x401f80a0 1 0x401f841c 1 0x401f8214>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data11: IOMUXC_GPIO_EMC_35_SEMC_DATA11 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc2_wp: IOMUXC_GPIO_EMC_35_USDHC2_WP { + pinmux = <0x401f80a0 3 0x401f849c 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexcan1_tx: IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX { + pinmux = <0x401f8158 4 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f8158 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io20: IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 { + pinmux = <0x401f8158 5 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart6_tx: IOMUXC_GPIO_SD_B1_00_LPUART6_TX { + pinmux = <0x401f8158 2 0x401f83f8 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data2: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 { + pinmux = <0x401f8158 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexcan1_rx: IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX { + pinmux = <0x401f815c 4 0x401f8320 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B { + pinmux = <0x401f815c 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK { + pinmux = <0x401f815c 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io21: IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 { + pinmux = <0x401f815c 5 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart6_rx: IOMUXC_GPIO_SD_B1_01_LPUART6_RX { + pinmux = <0x401f815c 2 0x401f83f4 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data3: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 { + pinmux = <0x401f815c 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_clko1: IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 { + pinmux = <0x401f8160 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_enet_1588_event1_out: IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT { + pinmux = <0x401f8160 4 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data0: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA0 { + pinmux = <0x401f8160 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io22: IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 { + pinmux = <0x401f8160 5 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpi2c4_scl: IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL { + pinmux = <0x401f8160 3 0x401f8394 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpuart8_tx: IOMUXC_GPIO_SD_B1_02_LPUART8_TX { + pinmux = <0x401f8160 2 0x401f8408 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_cmd: IOMUXC_GPIO_SD_B1_02_USDHC2_CMD { + pinmux = <0x401f8160 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_clko2: IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 { + pinmux = <0x401f8164 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_enet_1588_event1_in: IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN { + pinmux = <0x401f8164 4 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data2: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA2 { + pinmux = <0x401f8164 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io23: IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 { + pinmux = <0x401f8164 5 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpi2c4_sda: IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA { + pinmux = <0x401f8164 3 0x401f8398 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpuart8_rx: IOMUXC_GPIO_SD_B1_03_LPUART8_RX { + pinmux = <0x401f8164 2 0x401f8404 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_clk: IOMUXC_GPIO_SD_B1_03_USDHC2_CLK { + pinmux = <0x401f8164 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_wait: IOMUXC_GPIO_SD_B1_04_CCM_WAIT { + pinmux = <0x401f8168 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_ref_clk: IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK { + pinmux = <0x401f8168 3 0x401f8304 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_tx_clk: IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK { + pinmux = <0x401f8168 2 0x401f831c 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ewm_out_b: IOMUXC_GPIO_SD_B1_04_EWM_OUT_B { + pinmux = <0x401f8168 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_data1: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA1 { + pinmux = <0x401f8168 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io24: IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 { + pinmux = <0x401f8168 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_data0: IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f8168 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY { + pinmux = <0x401f816c 6 0x401f8300 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_enet_rx_data1: IOMUXC_GPIO_SD_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f816c 2 0x401f8310 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f816c 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f816c 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io25: IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 { + pinmux = <0x401f816c 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_mclk: IOMUXC_GPIO_SD_B1_05_SAI3_MCLK { + pinmux = <0x401f816c 3 0x401f846c 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_data1: IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f816c 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_ccm_stop: IOMUXC_GPIO_SD_B1_06_CCM_STOP { + pinmux = <0x401f8170 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_enet_rx_data0: IOMUXC_GPIO_SD_B1_06_ENET_RX_DATA0 { + pinmux = <0x401f8170 2 0x401f830c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_data3: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA3 { + pinmux = <0x401f8170 1 0x401f8374 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io26: IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 { + pinmux = <0x401f8170 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f8170 4 0x401f83ac 2 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK { + pinmux = <0x401f8170 3 0x401f847c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_cd_b: IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B { + pinmux = <0x401f8170 0 0x401f8498 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_enet_rx_en: IOMUXC_GPIO_SD_B1_07_ENET_RX_EN { + pinmux = <0x401f8174 2 0x401f8314 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f8174 1 0x401f8378 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io27: IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 { + pinmux = <0x401f8174 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f8174 4 0x401f83b0 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai3_tx_sync: IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC { + pinmux = <0x401f8174 3 0x401f8480 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B { + pinmux = <0x401f8174 0 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_enet_rx_er: IOMUXC_GPIO_SD_B1_08_ENET_RX_ER { + pinmux = <0x401f8178 2 0x401f8318 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f8178 1 0x401f8368 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io28: IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 { + pinmux = <0x401f8178 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f8178 4 0x401f83b8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai3_tx_data: IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA { + pinmux = <0x401f8178 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f8178 0 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_enet_tx_en: IOMUXC_GPIO_SD_B1_09_ENET_TX_EN { + pinmux = <0x401f817c 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data2: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA2 { + pinmux = <0x401f817c 1 0x401f8370 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io29: IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 { + pinmux = <0x401f817c 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f817c 4 0x401f83b4 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK { + pinmux = <0x401f817c 3 0x401f8470 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f817c 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_enet_tx_data0: IOMUXC_GPIO_SD_B1_10_ENET_TX_DATA0 { + pinmux = <0x401f8180 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data1: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA1 { + pinmux = <0x401f8180 1 0x401f836c 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io30: IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 { + pinmux = <0x401f8180 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f8180 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_sai3_rx_sync: IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC { + pinmux = <0x401f8180 3 0x401f8478 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f8180 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_enet_tx_data1: IOMUXC_GPIO_SD_B1_11_ENET_TX_DATA1 { + pinmux = <0x401f8184 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B { + pinmux = <0x401f8184 1 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io31: IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 { + pinmux = <0x401f8184 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8184 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_sai3_rx_data: IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA { + pinmux = <0x401f8184 3 0x401f8474 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8184 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1021dag5b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1021dag5b-pinctrl.dtsi new file mode 100644 index 000000000..64ac76787 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1021dag5b-pinctrl.dtsi @@ -0,0 +1,2311 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1021DAG5B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpt1_compare1: IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 { + pinmux = <0x401f80bc 7 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_jtag_tms: IOMUXC_GPIO_AD_B0_00_JTAG_TMS { + pinmux = <0x401f80bc 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpt1_capture2: IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 { + pinmux = <0x401f80c0 7 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_jtag_tck: IOMUXC_GPIO_AD_B0_01_JTAG_TCK { + pinmux = <0x401f80c0 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpt1_capture1: IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 { + pinmux = <0x401f80c4 7 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_jtag_mod: IOMUXC_GPIO_AD_B0_02_JTAG_MOD { + pinmux = <0x401f80c4 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY { + pinmux = <0x401f80c8 7 0x401f8300 2 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_jtag_tdi: IOMUXC_GPIO_AD_B0_03_JTAG_TDI { + pinmux = <0x401f80c8 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_sai1_mclk: IOMUXC_GPIO_AD_B0_03_SAI1_MCLK { + pinmux = <0x401f80c8 3 0x401f8430 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 6 0x401f848c 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc1_wp: IOMUXC_GPIO_AD_B0_03_USDHC1_WP { + pinmux = <0x401f80c8 4 0x401f8494 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B { + pinmux = <0x401f80c8 1 0x401f8498 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_wdog1_b: IOMUXC_GPIO_AD_B0_03_WDOG1_B { + pinmux = <0x401f80c8 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_mdio: IOMUXC_GPIO_AD_B0_04_ENET_MDIO { + pinmux = <0x401f80cc 4 0x401f8308 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_ewm_out_b: IOMUXC_GPIO_AD_B0_04_EWM_OUT_B { + pinmux = <0x401f80cc 7 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_flexcan1_tx: IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX { + pinmux = <0x401f80cc 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_jtag_tdo: IOMUXC_GPIO_AD_B0_04_JTAG_TDO { + pinmux = <0x401f80cc 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_qtimer2_timer0: IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 { + pinmux = <0x401f80cc 3 0x401f8420 1 0x401f8240>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR { + pinmux = <0x401f80cc 6 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usdhc1_wp: IOMUXC_GPIO_AD_B0_04_USDHC1_WP { + pinmux = <0x401f80cc 2 0x401f8494 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_arm_nmi: IOMUXC_GPIO_AD_B0_05_ARM_NMI { + pinmux = <0x401f80d0 7 0x401f840c 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_mdc: IOMUXC_GPIO_AD_B0_05_ENET_MDC { + pinmux = <0x401f80d0 4 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_flexcan1_rx: IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX { + pinmux = <0x401f80d0 1 0x401f8320 2 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_jtag_trstb: IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB { + pinmux = <0x401f80d0 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_qtimer2_timer1: IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 { + pinmux = <0x401f80d0 3 0x401f8424 1 0x401f8244>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usb_otg1_id: IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID { + pinmux = <0x401f80d0 6 0x401f82fc 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usdhc1_cd_b: IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B { + pinmux = <0x401f80d0 2 0x401f8490 1 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA3 { + pinmux = <0x401f80d4 4 0x401f8354 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpuart1_tx: IOMUXC_GPIO_AD_B0_06_LPUART1_TX { + pinmux = <0x401f80d4 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_mqs_right: IOMUXC_GPIO_AD_B0_06_MQS_RIGHT { + pinmux = <0x401f80d4 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_pit_trigger0: IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER0 { + pinmux = <0x401f80d4 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_qtimer2_timer2: IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 { + pinmux = <0x401f80d4 3 0x401f8428 1 0x401f8248>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_ref_32k_out: IOMUXC_GPIO_AD_B0_06_REF_32K_OUT { + pinmux = <0x401f80d4 6 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_flexpwm2_pwmb3: IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB3 { + pinmux = <0x401f80d8 4 0x401f8364 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_lpuart1_rx: IOMUXC_GPIO_AD_B0_07_LPUART1_RX { + pinmux = <0x401f80d8 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_mqs_left: IOMUXC_GPIO_AD_B0_07_MQS_LEFT { + pinmux = <0x401f80d8 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_pit_trigger1: IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER1 { + pinmux = <0x401f80d8 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_qtimer2_timer3: IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 { + pinmux = <0x401f80d8 3 0x401f842c 1 0x401f824c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_ref_24m_out: IOMUXC_GPIO_AD_B0_07_REF_24M_OUT { + pinmux = <0x401f80d8 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_acmp1_in4: IOMUXC_GPIO_AD_B0_08_ACMP1_IN4 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_arm_cm7_txev: IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV { + pinmux = <0x401f80dc 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_ref_clk: IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK { + pinmux = <0x401f80dc 4 0x401f8304 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_tx_clk: IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK { + pinmux = <0x401f80dc 0 0x401f831c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_kpp_col0: IOMUXC_GPIO_AD_B0_08_KPP_COL0 { + pinmux = <0x401f80dc 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpi2c3_scl: IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL { + pinmux = <0x401f80dc 1 0x401f838c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B { + pinmux = <0x401f80dc 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_acmp2_in4: IOMUXC_GPIO_AD_B0_09_ACMP2_IN4 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_arm_cm7_rxev: IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV { + pinmux = <0x401f80e0 6 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data1: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA1 { + pinmux = <0x401f80e0 0 0x401f8310 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_kpp_row0: IOMUXC_GPIO_AD_B0_09_KPP_ROW0 { + pinmux = <0x401f80e0 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpi2c3_sda: IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA { + pinmux = <0x401f80e0 1 0x401f8390 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B { + pinmux = <0x401f80e0 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_acmp3_in4: IOMUXC_GPIO_AD_B0_10_ACMP3_IN4 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_clk: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_CLK { + pinmux = <0x401f80e4 6 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_rx_data0: IOMUXC_GPIO_AD_B0_10_ENET_RX_DATA0 { + pinmux = <0x401f80e4 0 0x401f830c 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f80e4 4 0x401f8350 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_kpp_col1: IOMUXC_GPIO_AD_B0_10_KPP_COL1 { + pinmux = <0x401f80e4 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpspi1_sck: IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK { + pinmux = <0x401f80e4 1 0x401f83a0 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpuart5_tx: IOMUXC_GPIO_AD_B0_10_LPUART5_TX { + pinmux = <0x401f80e4 2 0x401f83f0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_acmp4_in4: IOMUXC_GPIO_AD_B0_11_ACMP4_IN4 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_arm_trace_swo: IOMUXC_GPIO_AD_B0_11_ARM_TRACE_SWO { + pinmux = <0x401f80e8 6 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_rx_en: IOMUXC_GPIO_AD_B0_11_ENET_RX_EN { + pinmux = <0x401f80e8 0 0x401f8314 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f80e8 4 0x401f8360 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_kpp_row1: IOMUXC_GPIO_AD_B0_11_KPP_ROW1 { + pinmux = <0x401f80e8 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpspi1_pcs0: IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 { + pinmux = <0x401f80e8 1 0x401f839c 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpuart5_rx: IOMUXC_GPIO_AD_B0_11_LPUART5_RX { + pinmux = <0x401f80e8 2 0x401f83ec 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in0: IOMUXC_GPIO_AD_B0_12_ADC1_IN0 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_trace0: IOMUXC_GPIO_AD_B0_12_ARM_TRACE0 { + pinmux = <0x401f80ec 6 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_rx_er: IOMUXC_GPIO_AD_B0_12_ENET_RX_ER { + pinmux = <0x401f80ec 0 0x401f8318 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm2_pwma1: IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA1 { + pinmux = <0x401f80ec 4 0x401f834c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_kpp_col2: IOMUXC_GPIO_AD_B0_12_KPP_COL2 { + pinmux = <0x401f80ec 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpspi1_sdo: IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO { + pinmux = <0x401f80ec 1 0x401f83a8 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart3_cts_b: IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B { + pinmux = <0x401f80ec 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_snvs_vio_5_ctl: IOMUXC_GPIO_AD_B0_12_SNVS_VIO_5_CTL { + pinmux = <0x401f80ec 7 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc2_in0: IOMUXC_GPIO_AD_B0_13_ADC2_IN0 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_tx_en: IOMUXC_GPIO_AD_B0_13_ENET_TX_EN { + pinmux = <0x401f80f0 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm2_pwmb1: IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB1 { + pinmux = <0x401f80f0 4 0x401f835c 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_kpp_row2: IOMUXC_GPIO_AD_B0_13_KPP_ROW2 { + pinmux = <0x401f80f0 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpspi1_sdi: IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI { + pinmux = <0x401f80f0 1 0x401f83a4 1 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart3_rts_b: IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B { + pinmux = <0x401f80f0 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_snvs_vio_5_b: IOMUXC_GPIO_AD_B0_13_SNVS_VIO_5_B { + pinmux = <0x401f80f0 7 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp1_in0: IOMUXC_GPIO_AD_B0_14_ACMP1_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in0: IOMUXC_GPIO_AD_B0_14_ACMP2_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp3_in0: IOMUXC_GPIO_AD_B0_14_ACMP3_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp4_in0: IOMUXC_GPIO_AD_B0_14_ACMP4_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in1: IOMUXC_GPIO_AD_B0_14_ADC1_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc2_in1: IOMUXC_GPIO_AD_B0_14_ADC2_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_tx_data0: IOMUXC_GPIO_AD_B0_14_ENET_TX_DATA0 { + pinmux = <0x401f80f4 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexpwm2_pwma0: IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA0 { + pinmux = <0x401f80f4 4 0x401f8348 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_kpp_col3: IOMUXC_GPIO_AD_B0_14_KPP_COL3 { + pinmux = <0x401f80f4 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart3_tx: IOMUXC_GPIO_AD_B0_14_LPUART3_TX { + pinmux = <0x401f80f4 2 0x401f83dc 1 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_wdog1_any: IOMUXC_GPIO_AD_B0_14_WDOG1_ANY { + pinmux = <0x401f80f4 7 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp1_in1: IOMUXC_GPIO_AD_B0_15_ACMP1_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp2_in1: IOMUXC_GPIO_AD_B0_15_ACMP2_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in1: IOMUXC_GPIO_AD_B0_15_ACMP3_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp4_in1: IOMUXC_GPIO_AD_B0_15_ACMP4_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in2: IOMUXC_GPIO_AD_B0_15_ADC1_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc2_in2: IOMUXC_GPIO_AD_B0_15_ADC2_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_tx_data1: IOMUXC_GPIO_AD_B0_15_ENET_TX_DATA1 { + pinmux = <0x401f80f8 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 1 0x401f8324 2 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexpwm2_pwmb0: IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB0 { + pinmux = <0x401f80f8 4 0x401f8358 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_kpp_row3: IOMUXC_GPIO_AD_B0_15_KPP_ROW3 { + pinmux = <0x401f80f8 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart3_rx: IOMUXC_GPIO_AD_B0_15_LPUART3_RX { + pinmux = <0x401f80f8 2 0x401f83d8 1 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp1_in2: IOMUXC_GPIO_AD_B1_00_ACMP1_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_00_ENET_1588_EVENT2_OUT { + pinmux = <0x401f80fc 6 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexcan2_tx: IOMUXC_GPIO_AD_B1_00_FLEXCAN2_TX { + pinmux = <0x401f80fc 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio1_flexio15: IOMUXC_GPIO_AD_B1_00_FLEXIO1_FLEXIO15 { + pinmux = <0x401f80fc 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexspi_a_data3: IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA3 { + pinmux = <0x401f80fc 1 0x401f8374 1 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_kpp_col4: IOMUXC_GPIO_AD_B1_00_KPP_COL4 { + pinmux = <0x401f80fc 7 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_sai1_mclk: IOMUXC_GPIO_AD_B1_00_SAI1_MCLK { + pinmux = <0x401f80fc 3 0x401f8430 2 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_semc_rdy: IOMUXC_GPIO_AD_B1_00_SEMC_RDY { + pinmux = <0x401f80fc 0 0x401f8484 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in2: IOMUXC_GPIO_AD_B1_01_ACMP2_IN2 { + pinmux = <0x401f8100 5 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in3: IOMUXC_GPIO_AD_B1_01_ADC1_IN3 { + pinmux = <0x401f8100 5 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_01_ENET_1588_EVENT2_IN { + pinmux = <0x401f8100 6 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexcan2_rx: IOMUXC_GPIO_AD_B1_01_FLEXCAN2_RX { + pinmux = <0x401f8100 2 0x401f8324 3 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio1_flexio14: IOMUXC_GPIO_AD_B1_01_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8100 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexspi_a_sclk: IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK { + pinmux = <0x401f8100 1 0x401f8378 1 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_kpp_row4: IOMUXC_GPIO_AD_B1_01_KPP_ROW4 { + pinmux = <0x401f8100 7 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_sai1_tx_bclk: IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK { + pinmux = <0x401f8100 3 0x401f844c 1 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_semc_csx0: IOMUXC_GPIO_AD_B1_01_SEMC_CSX0 { + pinmux = <0x401f8100 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp3_in2: IOMUXC_GPIO_AD_B1_02_ACMP3_IN2 { + pinmux = <0x401f8104 5 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in3: IOMUXC_GPIO_AD_B1_02_ADC2_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event3_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT3_OUT { + pinmux = <0x401f8104 6 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio1_flexio13: IOMUXC_GPIO_AD_B1_02_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8104 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexspi_a_data0: IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA0 { + pinmux = <0x401f8104 1 0x401f8368 1 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_kpp_col5: IOMUXC_GPIO_AD_B1_02_KPP_COL5 { + pinmux = <0x401f8104 7 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpspi4_sck: IOMUXC_GPIO_AD_B1_02_LPSPI4_SCK { + pinmux = <0x401f8104 2 0x401f83c0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_sai1_tx_sync: IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC { + pinmux = <0x401f8104 3 0x401f8450 1 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_semc_csx1: IOMUXC_GPIO_AD_B1_02_SEMC_CSX1 { + pinmux = <0x401f8104 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp4_in2: IOMUXC_GPIO_AD_B1_03_ACMP4_IN2 { + pinmux = <0x401f8108 5 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in4: IOMUXC_GPIO_AD_B1_03_ADC1_IN4 { + pinmux = <0x401f8108 5 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event3_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT3_IN { + pinmux = <0x401f8108 6 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio1_flexio12: IOMUXC_GPIO_AD_B1_03_FLEXIO1_FLEXIO12 { + pinmux = <0x401f8108 4 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexspi_a_data2: IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA2 { + pinmux = <0x401f8108 1 0x401f8370 1 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_kpp_row5: IOMUXC_GPIO_AD_B1_03_KPP_ROW5 { + pinmux = <0x401f8108 7 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpspi4_pcs0: IOMUXC_GPIO_AD_B1_03_LPSPI4_PCS0 { + pinmux = <0x401f8108 2 0x401f83bc 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_sai1_tx_data0: IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA0 { + pinmux = <0x401f8108 3 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_semc_csx2: IOMUXC_GPIO_AD_B1_03_SEMC_CSX2 { + pinmux = <0x401f8108 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp1_in3: IOMUXC_GPIO_AD_B1_04_ACMP1_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in4: IOMUXC_GPIO_AD_B1_04_ADC2_IN4 { + pinmux = <0x401f810c 5 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio1_flexio11: IOMUXC_GPIO_AD_B1_04_FLEXIO1_FLEXIO11 { + pinmux = <0x401f810c 4 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_a_data1: IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA1 { + pinmux = <0x401f810c 1 0x401f836c 1 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_kpp_col6: IOMUXC_GPIO_AD_B1_04_KPP_COL6 { + pinmux = <0x401f810c 7 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpspi1_pcs1: IOMUXC_GPIO_AD_B1_04_LPSPI1_PCS1 { + pinmux = <0x401f810c 6 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpspi4_sdo: IOMUXC_GPIO_AD_B1_04_LPSPI4_SDO { + pinmux = <0x401f810c 2 0x401f83c8 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_sai1_rx_sync: IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f810c 3 0x401f8448 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_semc_csx3: IOMUXC_GPIO_AD_B1_04_SEMC_CSX3 { + pinmux = <0x401f810c 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp2_in3: IOMUXC_GPIO_AD_B1_05_ACMP2_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in5: IOMUXC_GPIO_AD_B1_05_ADC1_IN5 { + pinmux = <0x401f8110 5 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in5: IOMUXC_GPIO_AD_B1_05_ADC2_IN5 { + pinmux = <0x401f8110 5 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio1_flexio10: IOMUXC_GPIO_AD_B1_05_FLEXIO1_FLEXIO10 { + pinmux = <0x401f8110 4 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_a_ss0_b: IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B { + pinmux = <0x401f8110 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_kpp_row6: IOMUXC_GPIO_AD_B1_05_KPP_ROW6 { + pinmux = <0x401f8110 7 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpspi1_pcs2: IOMUXC_GPIO_AD_B1_05_LPSPI1_PCS2 { + pinmux = <0x401f8110 6 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpspi4_sdi: IOMUXC_GPIO_AD_B1_05_LPSPI4_SDI { + pinmux = <0x401f8110 2 0x401f83c4 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_sai1_rx_data0: IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA0 { + pinmux = <0x401f8110 3 0x401f8438 1 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc1_wp: IOMUXC_GPIO_AD_B1_05_USDHC1_WP { + pinmux = <0x401f8110 0 0x401f8494 2 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in3: IOMUXC_GPIO_AD_B1_06_ACMP3_IN3 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in6: IOMUXC_GPIO_AD_B1_06_ADC1_IN6 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in6: IOMUXC_GPIO_AD_B1_06_ADC2_IN6 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio1_flexio09: IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8114 4 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexpwm1_pwma0: IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA0 { + pinmux = <0x401f8114 1 0x401f8328 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_kpp_col7: IOMUXC_GPIO_AD_B1_06_KPP_COL7 { + pinmux = <0x401f8114 7 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpspi1_pcs3: IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3 { + pinmux = <0x401f8114 6 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B { + pinmux = <0x401f8114 2 0x401f83cc 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_sai1_rx_bclk: IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK { + pinmux = <0x401f8114 3 0x401f8434 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc1_reset_b: IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B { + pinmux = <0x401f8114 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp4_in3: IOMUXC_GPIO_AD_B1_07_ACMP4_IN3 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in7: IOMUXC_GPIO_AD_B1_07_ADC1_IN7 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in7: IOMUXC_GPIO_AD_B1_07_ADC2_IN7 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio1_flexio08: IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8118 4 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexpwm1_pwmb0: IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB0 { + pinmux = <0x401f8118 1 0x401f8338 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_kpp_row7: IOMUXC_GPIO_AD_B1_07_KPP_ROW7 { + pinmux = <0x401f8118 7 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpspi3_pcs3: IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3 { + pinmux = <0x401f8118 6 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B { + pinmux = <0x401f8118 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_sai1_tx_data1: IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA1 { + pinmux = <0x401f8118 3 0x401f8444 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc1_vselect: IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT { + pinmux = <0x401f8118 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_acmp1_in5: IOMUXC_GPIO_AD_B1_08_ACMP1_IN5 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc1_in8: IOMUXC_GPIO_AD_B1_08_ADC1_IN8 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc2_in8: IOMUXC_GPIO_AD_B1_08_ADC2_IN8 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexio1_flexio07: IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07 { + pinmux = <0x401f811c 4 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexpwm1_pwma1: IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA1 { + pinmux = <0x401f811c 1 0x401f832c 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio1_io24: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpi2c2_scl: IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL { + pinmux = <0x401f811c 0 0x401f8384 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpspi3_pcs2: IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2 { + pinmux = <0x401f811c 6 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpuart2_tx: IOMUXC_GPIO_AD_B1_08_LPUART2_TX { + pinmux = <0x401f811c 2 0x401f83d4 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_sai1_tx_data2: IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA2 { + pinmux = <0x401f811c 3 0x401f8440 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_xbar1_xbar_in12: IOMUXC_GPIO_AD_B1_08_XBAR1_XBAR_IN12 { + pinmux = <0x401f811c 7 0x401f84b4 1 0x401f8290>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_xbar1_xbar_inout12: IOMUXC_GPIO_AD_B1_08_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f811c 7 0x401f84b4 1 0x401f8290>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_acmp2_in5: IOMUXC_GPIO_AD_B1_09_ACMP2_IN5 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc1_in9: IOMUXC_GPIO_AD_B1_09_ADC1_IN9 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc2_in9: IOMUXC_GPIO_AD_B1_09_ADC2_IN9 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexio1_flexio06: IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO06 { + pinmux = <0x401f8120 4 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexpwm1_pwmb1: IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB1 { + pinmux = <0x401f8120 1 0x401f833c 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio1_io25: IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpi2c2_sda: IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA { + pinmux = <0x401f8120 0 0x401f8388 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpspi3_pcs1: IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 { + pinmux = <0x401f8120 6 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpuart2_rx: IOMUXC_GPIO_AD_B1_09_LPUART2_RX { + pinmux = <0x401f8120 2 0x401f83d0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_sai1_tx_data3: IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA3 { + pinmux = <0x401f8120 3 0x401f843c 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_xbar1_xbar_in13: IOMUXC_GPIO_AD_B1_09_XBAR1_XBAR_IN13 { + pinmux = <0x401f8120 7 0x401f84b8 1 0x401f8294>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_xbar1_xbar_inout13: IOMUXC_GPIO_AD_B1_09_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8120 7 0x401f84b8 1 0x401f8294>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_acmp3_in5: IOMUXC_GPIO_AD_B1_10_ACMP3_IN5 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in10: IOMUXC_GPIO_AD_B1_10_ADC1_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc2_in10: IOMUXC_GPIO_AD_B1_10_ADC2_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio1_flexio05: IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8124 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexpwm1_pwma2: IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA2 { + pinmux = <0x401f8124 1 0x401f8330 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpt2_capture1: IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 { + pinmux = <0x401f8124 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart4_tx: IOMUXC_GPIO_AD_B1_10_LPUART4_TX { + pinmux = <0x401f8124 2 0x401f83e8 1 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR { + pinmux = <0x401f8124 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B { + pinmux = <0x401f8124 3 0x401f8490 2 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_acmp4_in5: IOMUXC_GPIO_AD_B1_11_ACMP4_IN5 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in11: IOMUXC_GPIO_AD_B1_11_ADC1_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc2_in11: IOMUXC_GPIO_AD_B1_11_ADC2_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio1_flexio04: IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8128 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexpwm1_pwmb2: IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB2 { + pinmux = <0x401f8128 1 0x401f8340 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpt2_compare1: IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 { + pinmux = <0x401f8128 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart4_rx: IOMUXC_GPIO_AD_B1_11_LPUART4_RX { + pinmux = <0x401f8128 2 0x401f83e4 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usb_otg1_id: IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID { + pinmux = <0x401f8128 0 0x401f82fc 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usdhc1_wp: IOMUXC_GPIO_AD_B1_11_USDHC1_WP { + pinmux = <0x401f8128 3 0x401f8494 3 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_in6: IOMUXC_GPIO_AD_B1_12_ACMP1_IN6 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_out: IOMUXC_GPIO_AD_B1_12_ACMP1_OUT { + pinmux = <0x401f812c 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc1_in12: IOMUXC_GPIO_AD_B1_12_ADC1_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc2_in12: IOMUXC_GPIO_AD_B1_12_ADC2_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio1_flexio03: IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 { + pinmux = <0x401f812c 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexpwm1_pwma3: IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f812c 6 0x401f8334 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_lpspi3_sck: IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK { + pinmux = <0x401f812c 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usb_otg1_oc: IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC { + pinmux = <0x401f812c 0 0x401f848c 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B { + pinmux = <0x401f812c 3 0x401f8498 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_in6: IOMUXC_GPIO_AD_B1_13_ACMP2_IN6 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_out: IOMUXC_GPIO_AD_B1_13_ACMP2_OUT { + pinmux = <0x401f8130 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc1_in13: IOMUXC_GPIO_AD_B1_13_ADC1_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc2_in13: IOMUXC_GPIO_AD_B1_13_ADC2_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio1_flexio02: IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 { + pinmux = <0x401f8130 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8130 6 0x401f8344 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpi2c1_hreq: IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ { + pinmux = <0x401f8130 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpspi3_pcs0: IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 { + pinmux = <0x401f8130 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_usdhc2_wp: IOMUXC_GPIO_AD_B1_13_USDHC2_WP { + pinmux = <0x401f8130 3 0x401f849c 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_in6: IOMUXC_GPIO_AD_B1_14_ACMP3_IN6 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_out: IOMUXC_GPIO_AD_B1_14_ACMP3_OUT { + pinmux = <0x401f8134 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc1_in14: IOMUXC_GPIO_AD_B1_14_ADC1_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc2_in14: IOMUXC_GPIO_AD_B1_14_ADC2_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f8134 3 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio1_flexio01: IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8134 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpi2c1_scl: IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL { + pinmux = <0x401f8134 0 0x401f837c 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpspi3_sdo: IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO { + pinmux = <0x401f8134 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_in6: IOMUXC_GPIO_AD_B1_15_ACMP4_IN6 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_out: IOMUXC_GPIO_AD_B1_15_ACMP4_OUT { + pinmux = <0x401f8138 1 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc1_in15: IOMUXC_GPIO_AD_B1_15_ADC1_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc2_in15: IOMUXC_GPIO_AD_B1_15_ADC2_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f8138 3 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio1_flexio00: IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8138 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpi2c1_sda: IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA { + pinmux = <0x401f8138 0 0x401f8380 1 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpspi3_sdi: IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI { + pinmux = <0x401f8138 2 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexcan1_tx: IOMUXC_GPIO_EMC_00_FLEXCAN1_TX { + pinmux = <0x401f8014 6 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio2_io00: IOMUXC_GPIO_EMC_00_GPIO2_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 4 0x401f83b0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpuart4_cts_b: IOMUXC_GPIO_EMC_00_LPUART4_CTS_B { + pinmux = <0x401f8014 2 0x401f83e0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_pit_trigger2: IOMUXC_GPIO_EMC_00_PIT_TRIGGER2 { + pinmux = <0x401f8014 7 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_qtimer2_timer0: IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0 { + pinmux = <0x401f8014 1 0x401f8420 0 0x401f8188>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_spdif_sr_clk: IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK { + pinmux = <0x401f8014 3 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexcan1_rx: IOMUXC_GPIO_EMC_01_FLEXCAN1_RX { + pinmux = <0x401f8018 6 0x401f8320 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio2_io01: IOMUXC_GPIO_EMC_01_GPIO2_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 4 0x401f83ac 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpuart4_rts_b: IOMUXC_GPIO_EMC_01_LPUART4_RTS_B { + pinmux = <0x401f8018 2 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_pit_trigger3: IOMUXC_GPIO_EMC_01_PIT_TRIGGER3 { + pinmux = <0x401f8018 7 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_qtimer2_timer1: IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1 { + pinmux = <0x401f8018 1 0x401f8424 0 0x401f818c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_spdif_out: IOMUXC_GPIO_EMC_01_SPDIF_OUT { + pinmux = <0x401f8018 3 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio2_io02: IOMUXC_GPIO_EMC_02_GPIO2_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpi2c1_scl: IOMUXC_GPIO_EMC_02_LPI2C1_SCL { + pinmux = <0x401f801c 6 0x401f837c 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 4 0x401f83b8 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpuart4_tx: IOMUXC_GPIO_EMC_02_LPUART4_TX { + pinmux = <0x401f801c 2 0x401f83e8 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_qtimer2_timer2: IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2 { + pinmux = <0x401f801c 1 0x401f8428 0 0x401f8190>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_spdif_lock: IOMUXC_GPIO_EMC_02_SPDIF_LOCK { + pinmux = <0x401f801c 3 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio2_io03: IOMUXC_GPIO_EMC_03_GPIO2_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpi2c1_sda: IOMUXC_GPIO_EMC_03_LPI2C1_SDA { + pinmux = <0x401f8020 6 0x401f8380 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 4 0x401f83b4 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpuart4_rx: IOMUXC_GPIO_EMC_03_LPUART4_RX { + pinmux = <0x401f8020 2 0x401f83e4 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_qtimer2_timer3: IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3 { + pinmux = <0x401f8020 1 0x401f842c 0 0x401f8194>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_spdif_ext_clk: IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK { + pinmux = <0x401f8020 3 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio16: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 { + pinmux = <0x401f8024 4 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio2_io04: IOMUXC_GPIO_EMC_04_GPIO2_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_bclk: IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK { + pinmux = <0x401f8024 3 0x401f8464 1 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_spdif_out: IOMUXC_GPIO_EMC_04_SPDIF_OUT { + pinmux = <0x401f8024 2 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio17: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 { + pinmux = <0x401f8028 4 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio2_io05: IOMUXC_GPIO_EMC_05_GPIO2_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 3 0x401f8468 1 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_spdif_in: IOMUXC_GPIO_EMC_05_SPDIF_IN { + pinmux = <0x401f8028 2 0x401f8488 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio18: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 { + pinmux = <0x401f802c 4 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio2_io06: IOMUXC_GPIO_EMC_06_GPIO2_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_lpuart3_tx: IOMUXC_GPIO_EMC_06_LPUART3_TX { + pinmux = <0x401f802c 2 0x401f83dc 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_data: IOMUXC_GPIO_EMC_06_SAI2_TX_DATA { + pinmux = <0x401f802c 3 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio19: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 { + pinmux = <0x401f8030 4 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio2_io07: IOMUXC_GPIO_EMC_07_GPIO2_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_lpuart3_rx: IOMUXC_GPIO_EMC_07_LPUART3_RX { + pinmux = <0x401f8030 2 0x401f83d8 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_rx_sync: IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC { + pinmux = <0x401f8030 3 0x401f8460 1 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexcan2_tx: IOMUXC_GPIO_EMC_08_FLEXCAN2_TX { + pinmux = <0x401f8034 2 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio20: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 { + pinmux = <0x401f8034 4 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio2_io08: IOMUXC_GPIO_EMC_08_GPIO2_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 3 0x401f845c 1 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_rx: IOMUXC_GPIO_EMC_09_FLEXCAN2_RX { + pinmux = <0x401f8038 2 0x401f8324 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio21: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 { + pinmux = <0x401f8038 4 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio2_io09: IOMUXC_GPIO_EMC_09_GPIO2_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_bclk: IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK { + pinmux = <0x401f8038 3 0x401f8458 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_we: IOMUXC_GPIO_EMC_09_SEMC_WE { + pinmux = <0x401f8038 0 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_in09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_IN09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwmx0: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX0 { + pinmux = <0x401f803c 6 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio2_io10: IOMUXC_GPIO_EMC_10_GPIO2_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_lpi2c4_sda: IOMUXC_GPIO_EMC_10_LPI2C4_SDA { + pinmux = <0x401f803c 2 0x401f8398 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_lpspi2_sck: IOMUXC_GPIO_EMC_10_LPSPI2_SCK { + pinmux = <0x401f803c 4 0x401f83b0 1 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai1_tx_sync: IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC { + pinmux = <0x401f803c 3 0x401f8450 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_cas: IOMUXC_GPIO_EMC_10_SEMC_CAS { + pinmux = <0x401f803c 0 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_xbar1_xbar_in10: IOMUXC_GPIO_EMC_10_XBAR1_XBAR_IN10 { + pinmux = <0x401f803c 1 0x401f84b0 0 0x401f81b0>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_10_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f803c 1 0x401f84b0 0 0x401f81b0>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmx1: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX1 { + pinmux = <0x401f8040 6 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio2_io11: IOMUXC_GPIO_EMC_11_GPIO2_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_scl: IOMUXC_GPIO_EMC_11_LPI2C4_SCL { + pinmux = <0x401f8040 2 0x401f8394 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpspi2_pcs0: IOMUXC_GPIO_EMC_11_LPSPI2_PCS0 { + pinmux = <0x401f8040 4 0x401f83ac 1 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_sai1_tx_bclk: IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK { + pinmux = <0x401f8040 3 0x401f844c 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_ras: IOMUXC_GPIO_EMC_11_SEMC_RAS { + pinmux = <0x401f8040 0 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_xbar1_xbar_in11: IOMUXC_GPIO_EMC_11_XBAR1_XBAR_IN11 { + pinmux = <0x401f8040 1 0x0 0 0x401f81b4>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_11_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8040 1 0x0 0 0x401f81b4>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm2_pwmx2: IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX2 { + pinmux = <0x401f8044 6 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio2_io12: IOMUXC_GPIO_EMC_12_GPIO2_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpspi2_sdo: IOMUXC_GPIO_EMC_12_LPSPI2_SDO { + pinmux = <0x401f8044 4 0x401f83b8 1 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpuart6_tx: IOMUXC_GPIO_EMC_12_LPUART6_TX { + pinmux = <0x401f8044 2 0x401f83f8 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_sai1_tx_data0: IOMUXC_GPIO_EMC_12_SAI1_TX_DATA0 { + pinmux = <0x401f8044 3 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_cs0: IOMUXC_GPIO_EMC_12_SEMC_CS0 { + pinmux = <0x401f8044 0 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in12: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN12 { + pinmux = <0x401f8044 1 0x401f84b4 0 0x401f81b8>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8044 1 0x401f84b4 0 0x401f81b8>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_ccm_pmic_rdy: IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY { + pinmux = <0x401f8048 7 0x401f8300 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm2_pwmx3: IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX3 { + pinmux = <0x401f8048 6 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio2_io13: IOMUXC_GPIO_EMC_13_GPIO2_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpspi2_sdi: IOMUXC_GPIO_EMC_13_LPSPI2_SDI { + pinmux = <0x401f8048 4 0x401f83b4 1 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart6_rx: IOMUXC_GPIO_EMC_13_LPUART6_RX { + pinmux = <0x401f8048 2 0x401f83f4 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_sai1_rx_data0: IOMUXC_GPIO_EMC_13_SAI1_RX_DATA0 { + pinmux = <0x401f8048 3 0x401f8438 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_ba0: IOMUXC_GPIO_EMC_13_SEMC_BA0 { + pinmux = <0x401f8048 0 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in13: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN13 { + pinmux = <0x401f8048 1 0x401f84b8 0 0x401f81bc>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8048 1 0x401f84b8 0 0x401f81bc>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_flexcan1_tx: IOMUXC_GPIO_EMC_14_FLEXCAN1_TX { + pinmux = <0x401f804c 6 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio2_io14: IOMUXC_GPIO_EMC_14_GPIO2_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart6_cts_b: IOMUXC_GPIO_EMC_14_LPUART6_CTS_B { + pinmux = <0x401f804c 2 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_sai1_rx_bclk: IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK { + pinmux = <0x401f804c 3 0x401f8434 1 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_ba1: IOMUXC_GPIO_EMC_14_SEMC_BA1 { + pinmux = <0x401f804c 0 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in14: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN14 { + pinmux = <0x401f804c 1 0x401f84a0 1 0x401f81c0>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f804c 1 0x401f84a0 1 0x401f81c0>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_flexcan1_rx: IOMUXC_GPIO_EMC_15_FLEXCAN1_RX { + pinmux = <0x401f8050 6 0x401f8320 3 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio2_io15: IOMUXC_GPIO_EMC_15_GPIO2_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart6_rts_b: IOMUXC_GPIO_EMC_15_LPUART6_RTS_B { + pinmux = <0x401f8050 2 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_sai1_rx_sync: IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC { + pinmux = <0x401f8050 3 0x401f8448 1 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr10: IOMUXC_GPIO_EMC_15_SEMC_ADDR10 { + pinmux = <0x401f8050 0 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_wdog1_b: IOMUXC_GPIO_EMC_15_WDOG1_B { + pinmux = <0x401f8050 4 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in15: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN15 { + pinmux = <0x401f8050 1 0x401f84a4 1 0x401f81c4>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8050 1 0x401f84a4 1 0x401f81c4>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio2_io16: IOMUXC_GPIO_EMC_16_GPIO2_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_mqs_right: IOMUXC_GPIO_EMC_16_MQS_RIGHT { + pinmux = <0x401f8054 2 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_sai2_mclk: IOMUXC_GPIO_EMC_16_SAI2_MCLK { + pinmux = <0x401f8054 3 0x401f8454 1 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr00: IOMUXC_GPIO_EMC_16_SEMC_ADDR00 { + pinmux = <0x401f8054 0 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_src_boot_mode0: IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE0 { + pinmux = <0x401f8054 6 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio2_io17: IOMUXC_GPIO_EMC_17_GPIO2_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_mqs_left: IOMUXC_GPIO_EMC_17_MQS_LEFT { + pinmux = <0x401f8058 2 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_sai3_mclk: IOMUXC_GPIO_EMC_17_SAI3_MCLK { + pinmux = <0x401f8058 3 0x401f846c 1 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr01: IOMUXC_GPIO_EMC_17_SEMC_ADDR01 { + pinmux = <0x401f8058 0 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_src_boot_mode1: IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE1 { + pinmux = <0x401f8058 6 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexio1_flexio22: IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 { + pinmux = <0x401f805c 4 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio2_io18: IOMUXC_GPIO_EMC_18_GPIO2_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpi2c2_sda: IOMUXC_GPIO_EMC_18_LPI2C2_SDA { + pinmux = <0x401f805c 2 0x401f8388 1 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_sai1_rx_sync: IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC { + pinmux = <0x401f805c 3 0x401f8448 2 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr02: IOMUXC_GPIO_EMC_18_SEMC_ADDR02 { + pinmux = <0x401f805c 0 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_src_bt_cfg0: IOMUXC_GPIO_EMC_18_SRC_BT_CFG0 { + pinmux = <0x401f805c 6 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_IN16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexio1_flexio23: IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 { + pinmux = <0x401f8060 4 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio2_io19: IOMUXC_GPIO_EMC_19_GPIO2_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpi2c2_scl: IOMUXC_GPIO_EMC_19_LPI2C2_SCL { + pinmux = <0x401f8060 2 0x401f8384 1 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_sai1_rx_bclk: IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK { + pinmux = <0x401f8060 3 0x401f8434 2 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr03: IOMUXC_GPIO_EMC_19_SEMC_ADDR03 { + pinmux = <0x401f8060 0 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_src_bt_cfg1: IOMUXC_GPIO_EMC_19_SRC_BT_CFG1 { + pinmux = <0x401f8060 6 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_in17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_IN17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexio1_flexio24: IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 { + pinmux = <0x401f8064 4 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm1_pwma3: IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA3 { + pinmux = <0x401f8064 1 0x401f8334 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio2_io20: IOMUXC_GPIO_EMC_20_GPIO2_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart2_cts_b: IOMUXC_GPIO_EMC_20_LPUART2_CTS_B { + pinmux = <0x401f8064 2 0x401f83cc 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_sai1_mclk: IOMUXC_GPIO_EMC_20_SAI1_MCLK { + pinmux = <0x401f8064 3 0x401f8430 3 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr04: IOMUXC_GPIO_EMC_20_SEMC_ADDR04 { + pinmux = <0x401f8064 0 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_src_bt_cfg2: IOMUXC_GPIO_EMC_20_SRC_BT_CFG2 { + pinmux = <0x401f8064 6 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexio1_flexio25: IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 { + pinmux = <0x401f8068 4 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB3 { + pinmux = <0x401f8068 1 0x401f8344 1 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio2_io21: IOMUXC_GPIO_EMC_21_GPIO2_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpuart2_rts_b: IOMUXC_GPIO_EMC_21_LPUART2_RTS_B { + pinmux = <0x401f8068 2 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_sai1_rx_data0: IOMUXC_GPIO_EMC_21_SAI1_RX_DATA0 { + pinmux = <0x401f8068 3 0x401f8438 2 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_addr05: IOMUXC_GPIO_EMC_21_SEMC_ADDR05 { + pinmux = <0x401f8068 0 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_src_bt_cfg3: IOMUXC_GPIO_EMC_21_SRC_BT_CFG3 { + pinmux = <0x401f8068 6 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexio1_flexio26: IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 { + pinmux = <0x401f806c 4 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm1_pwma2: IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA2 { + pinmux = <0x401f806c 1 0x401f8330 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio2_io22: IOMUXC_GPIO_EMC_22_GPIO2_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpuart2_tx: IOMUXC_GPIO_EMC_22_LPUART2_TX { + pinmux = <0x401f806c 2 0x401f83d4 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_sai1_tx_data3: IOMUXC_GPIO_EMC_22_SAI1_TX_DATA3 { + pinmux = <0x401f806c 3 0x401f843c 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_addr06: IOMUXC_GPIO_EMC_22_SEMC_ADDR06 { + pinmux = <0x401f806c 0 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_src_bt_cfg4: IOMUXC_GPIO_EMC_22_SRC_BT_CFG4 { + pinmux = <0x401f806c 6 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexio1_flexio27: IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 { + pinmux = <0x401f8070 4 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB2 { + pinmux = <0x401f8070 1 0x401f8340 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio2_io23: IOMUXC_GPIO_EMC_23_GPIO2_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart2_rx: IOMUXC_GPIO_EMC_23_LPUART2_RX { + pinmux = <0x401f8070 2 0x401f83d0 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_sai1_tx_data2: IOMUXC_GPIO_EMC_23_SAI1_TX_DATA2 { + pinmux = <0x401f8070 3 0x401f8440 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr07: IOMUXC_GPIO_EMC_23_SEMC_ADDR07 { + pinmux = <0x401f8070 0 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_src_bt_cfg5: IOMUXC_GPIO_EMC_23_SRC_BT_CFG5 { + pinmux = <0x401f8070 6 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexio1_flexio28: IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 { + pinmux = <0x401f8074 4 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwma1: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA1 { + pinmux = <0x401f8074 1 0x401f832c 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio2_io24: IOMUXC_GPIO_EMC_24_GPIO2_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart8_cts_b: IOMUXC_GPIO_EMC_24_LPUART8_CTS_B { + pinmux = <0x401f8074 2 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_sai1_tx_data1: IOMUXC_GPIO_EMC_24_SAI1_TX_DATA1 { + pinmux = <0x401f8074 3 0x401f8444 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_addr08: IOMUXC_GPIO_EMC_24_SEMC_ADDR08 { + pinmux = <0x401f8074 0 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_src_bt_cfg6: IOMUXC_GPIO_EMC_24_SRC_BT_CFG6 { + pinmux = <0x401f8074 6 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexio1_flexio29: IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 { + pinmux = <0x401f8078 4 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB1 { + pinmux = <0x401f8078 1 0x401f833c 1 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio2_io25: IOMUXC_GPIO_EMC_25_GPIO2_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart8_rts_b: IOMUXC_GPIO_EMC_25_LPUART8_RTS_B { + pinmux = <0x401f8078 2 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_sai1_tx_data0: IOMUXC_GPIO_EMC_25_SAI1_TX_DATA0 { + pinmux = <0x401f8078 3 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_addr09: IOMUXC_GPIO_EMC_25_SEMC_ADDR09 { + pinmux = <0x401f8078 0 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_src_bt_cfg7: IOMUXC_GPIO_EMC_25_SRC_BT_CFG7 { + pinmux = <0x401f8078 6 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio30: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 { + pinmux = <0x401f807c 4 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwma0: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA0 { + pinmux = <0x401f807c 1 0x401f8328 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio2_io26: IOMUXC_GPIO_EMC_26_GPIO2_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart8_tx: IOMUXC_GPIO_EMC_26_LPUART8_TX { + pinmux = <0x401f807c 2 0x401f8408 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_sai1_tx_bclk: IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK { + pinmux = <0x401f807c 3 0x401f844c 2 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_addr11: IOMUXC_GPIO_EMC_26_SEMC_ADDR11 { + pinmux = <0x401f807c 0 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_src_bt_cfg8: IOMUXC_GPIO_EMC_26_SRC_BT_CFG8 { + pinmux = <0x401f807c 6 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio31: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 { + pinmux = <0x401f8080 4 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB0 { + pinmux = <0x401f8080 1 0x401f8338 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio2_io27: IOMUXC_GPIO_EMC_27_GPIO2_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart8_rx: IOMUXC_GPIO_EMC_27_LPUART8_RX { + pinmux = <0x401f8080 2 0x401f8404 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_sai1_tx_sync: IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC { + pinmux = <0x401f8080 3 0x401f8450 2 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_addr12: IOMUXC_GPIO_EMC_27_SEMC_ADDR12 { + pinmux = <0x401f8080 0 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_src_bt_cfg9: IOMUXC_GPIO_EMC_27_SRC_BT_CFG9 { + pinmux = <0x401f8080 6 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_ewm_out_b: IOMUXC_GPIO_EMC_28_EWM_OUT_B { + pinmux = <0x401f8084 4 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmx0: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX0 { + pinmux = <0x401f8084 7 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm2_pwma3: IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA3 { + pinmux = <0x401f8084 1 0x401f8354 1 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio2_io28: IOMUXC_GPIO_EMC_28_GPIO2_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpt2_capture2: IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2 { + pinmux = <0x401f8084 6 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_sai3_mclk: IOMUXC_GPIO_EMC_28_SAI3_MCLK { + pinmux = <0x401f8084 3 0x401f846c 2 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_dqs: IOMUXC_GPIO_EMC_28_SEMC_DQS { + pinmux = <0x401f8084 0 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_xbar1_xbar_in18: IOMUXC_GPIO_EMC_28_XBAR1_XBAR_IN18 { + pinmux = <0x401f8084 2 0x401f84bc 0 0x401f81f8>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_28_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f8084 2 0x401f84bc 0 0x401f81f8>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm1_pwmx1: IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX1 { + pinmux = <0x401f8088 7 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB3 { + pinmux = <0x401f8088 1 0x401f8364 1 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio2_io29: IOMUXC_GPIO_EMC_29_GPIO2_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpt2_compare2: IOMUXC_GPIO_EMC_29_GPT2_COMPARE2 { + pinmux = <0x401f8088 6 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_sai3_rx_bclk: IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK { + pinmux = <0x401f8088 3 0x401f8470 1 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cke: IOMUXC_GPIO_EMC_29_SEMC_CKE { + pinmux = <0x401f8088 0 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_wdog2_rst_b_deb: IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB { + pinmux = <0x401f8088 4 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_xbar1_xbar_in19: IOMUXC_GPIO_EMC_29_XBAR1_XBAR_IN19 { + pinmux = <0x401f8088 2 0x401f84c0 0 0x401f81fc>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_29_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f8088 2 0x401f84c0 0 0x401f81fc>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm1_pwmx2: IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX2 { + pinmux = <0x401f808c 7 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm2_pwma2: IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA2 { + pinmux = <0x401f808c 1 0x401f8350 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio2_io30: IOMUXC_GPIO_EMC_30_GPIO2_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpt2_compare3: IOMUXC_GPIO_EMC_30_GPT2_COMPARE3 { + pinmux = <0x401f808c 6 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart4_cts_b: IOMUXC_GPIO_EMC_30_LPUART4_CTS_B { + pinmux = <0x401f808c 2 0x401f83e0 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_sai3_rx_sync: IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC { + pinmux = <0x401f808c 3 0x401f8478 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_clk: IOMUXC_GPIO_EMC_30_SEMC_CLK { + pinmux = <0x401f808c 0 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_wdog1_rst_b_deb: IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB { + pinmux = <0x401f808c 4 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm1_pwmx3: IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX3 { + pinmux = <0x401f8090 7 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB2 { + pinmux = <0x401f8090 1 0x401f8360 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio2_io31: IOMUXC_GPIO_EMC_31_GPIO2_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpt2_clk: IOMUXC_GPIO_EMC_31_GPT2_CLK { + pinmux = <0x401f8090 6 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart4_rts_b: IOMUXC_GPIO_EMC_31_LPUART4_RTS_B { + pinmux = <0x401f8090 2 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_sai3_rx_data: IOMUXC_GPIO_EMC_31_SAI3_RX_DATA { + pinmux = <0x401f8090 3 0x401f8474 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_dm1: IOMUXC_GPIO_EMC_31_SEMC_DM1 { + pinmux = <0x401f8090 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_wdog2_b: IOMUXC_GPIO_EMC_31_WDOG2_B { + pinmux = <0x401f8090 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io00: IOMUXC_GPIO_EMC_32_GPIO3_IO00 { + pinmux = <0x401f8094 5 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpspi4_sck: IOMUXC_GPIO_EMC_32_LPSPI4_SCK { + pinmux = <0x401f8094 4 0x401f83c0 1 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart4_tx: IOMUXC_GPIO_EMC_32_LPUART4_TX { + pinmux = <0x401f8094 2 0x401f83e8 2 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_qtimer1_timer0: IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 { + pinmux = <0x401f8094 1 0x401f8410 1 0x401f8208>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ref_24m_out: IOMUXC_GPIO_EMC_32_REF_24M_OUT { + pinmux = <0x401f8094 7 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_sai3_tx_data: IOMUXC_GPIO_EMC_32_SAI3_TX_DATA { + pinmux = <0x401f8094 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data08: IOMUXC_GPIO_EMC_32_SEMC_DATA08 { + pinmux = <0x401f8094 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io01: IOMUXC_GPIO_EMC_33_GPIO3_IO01 { + pinmux = <0x401f8098 5 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpspi4_pcs0: IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 { + pinmux = <0x401f8098 4 0x401f83bc 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpuart4_rx: IOMUXC_GPIO_EMC_33_LPUART4_RX { + pinmux = <0x401f8098 2 0x401f83e4 2 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_qtimer1_timer1: IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 { + pinmux = <0x401f8098 1 0x401f8414 1 0x401f820c>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_tx_bclk: IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK { + pinmux = <0x401f8098 3 0x401f847c 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data09: IOMUXC_GPIO_EMC_33_SEMC_DATA09 { + pinmux = <0x401f8098 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_enet_crs: IOMUXC_GPIO_EMC_34_ENET_CRS { + pinmux = <0x401f809c 6 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io02: IOMUXC_GPIO_EMC_34_GPIO3_IO02 { + pinmux = <0x401f809c 5 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpspi4_sdo: IOMUXC_GPIO_EMC_34_LPSPI4_SDO { + pinmux = <0x401f809c 4 0x401f83c8 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpuart7_tx: IOMUXC_GPIO_EMC_34_LPUART7_TX { + pinmux = <0x401f809c 2 0x401f8400 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_qtimer1_timer2: IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 { + pinmux = <0x401f809c 1 0x401f8418 1 0x401f8210>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_tx_sync: IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC { + pinmux = <0x401f809c 3 0x401f8480 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data10: IOMUXC_GPIO_EMC_34_SEMC_DATA10 { + pinmux = <0x401f809c 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_enet_col: IOMUXC_GPIO_EMC_35_ENET_COL { + pinmux = <0x401f80a0 6 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io03: IOMUXC_GPIO_EMC_35_GPIO3_IO03 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpspi4_sdi: IOMUXC_GPIO_EMC_35_LPSPI4_SDI { + pinmux = <0x401f80a0 4 0x401f83c4 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpuart7_rx: IOMUXC_GPIO_EMC_35_LPUART7_RX { + pinmux = <0x401f80a0 2 0x401f83fc 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_qtimer1_timer3: IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 { + pinmux = <0x401f80a0 1 0x401f841c 1 0x401f8214>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data11: IOMUXC_GPIO_EMC_35_SEMC_DATA11 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc2_wp: IOMUXC_GPIO_EMC_35_USDHC2_WP { + pinmux = <0x401f80a0 3 0x401f849c 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_ccm_pmic_rdy: IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY { + pinmux = <0x401f80a4 3 0x401f8300 3 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_enet_rx_clk: IOMUXC_GPIO_EMC_36_ENET_RX_CLK { + pinmux = <0x401f80a4 6 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexpwm2_pwma1: IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA1 { + pinmux = <0x401f80a4 1 0x401f834c 1 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io04: IOMUXC_GPIO_EMC_36_GPIO3_IO04 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_lpspi4_pcs1: IOMUXC_GPIO_EMC_36_LPSPI4_PCS1 { + pinmux = <0x401f80a4 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_lpuart5_cts_b: IOMUXC_GPIO_EMC_36_LPUART5_CTS_B { + pinmux = <0x401f80a4 2 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data12: IOMUXC_GPIO_EMC_36_SEMC_DATA12 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 7 0x401f8494 4 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_enet_rx_data3: IOMUXC_GPIO_EMC_37_ENET_RX_DATA3 { + pinmux = <0x401f80a8 6 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB1 { + pinmux = <0x401f80a8 1 0x401f835c 1 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io05: IOMUXC_GPIO_EMC_37_GPIO3_IO05 { + pinmux = <0x401f80a8 5 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_lpspi4_pcs2: IOMUXC_GPIO_EMC_37_LPSPI4_PCS2 { + pinmux = <0x401f80a8 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_lpuart5_rts_b: IOMUXC_GPIO_EMC_37_LPUART5_RTS_B { + pinmux = <0x401f80a8 2 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_mqs_right: IOMUXC_GPIO_EMC_37_MQS_RIGHT { + pinmux = <0x401f80a8 3 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data13: IOMUXC_GPIO_EMC_37_SEMC_DATA13 { + pinmux = <0x401f80a8 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc1_vselect: IOMUXC_GPIO_EMC_37_USDHC1_VSELECT { + pinmux = <0x401f80a8 7 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_enet_rx_data2: IOMUXC_GPIO_EMC_38_ENET_RX_DATA2 { + pinmux = <0x401f80ac 6 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm2_pwma0: IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA0 { + pinmux = <0x401f80ac 1 0x401f8348 1 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io06: IOMUXC_GPIO_EMC_38_GPIO3_IO06 { + pinmux = <0x401f80ac 5 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpspi4_pcs3: IOMUXC_GPIO_EMC_38_LPSPI4_PCS3 { + pinmux = <0x401f80ac 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart5_tx: IOMUXC_GPIO_EMC_38_LPUART5_TX { + pinmux = <0x401f80ac 2 0x401f83f0 1 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_mqs_left: IOMUXC_GPIO_EMC_38_MQS_LEFT { + pinmux = <0x401f80ac 3 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_data14: IOMUXC_GPIO_EMC_38_SEMC_DATA14 { + pinmux = <0x401f80ac 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc1_cd_b: IOMUXC_GPIO_EMC_38_USDHC1_CD_B { + pinmux = <0x401f80ac 7 0x401f8490 3 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_enet_tx_er: IOMUXC_GPIO_EMC_39_ENET_TX_ER { + pinmux = <0x401f80b0 6 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB0 { + pinmux = <0x401f80b0 1 0x401f8358 1 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io07: IOMUXC_GPIO_EMC_39_GPIO3_IO07 { + pinmux = <0x401f80b0 5 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpt1_clk: IOMUXC_GPIO_EMC_39_GPT1_CLK { + pinmux = <0x401f80b0 7 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart5_rx: IOMUXC_GPIO_EMC_39_LPUART5_RX { + pinmux = <0x401f80b0 2 0x401f83ec 1 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_data15: IOMUXC_GPIO_EMC_39_SEMC_DATA15 { + pinmux = <0x401f80b0 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usb_otg1_oc: IOMUXC_GPIO_EMC_39_USB_OTG1_OC { + pinmux = <0x401f80b0 3 0x401f848c 2 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdio: IOMUXC_GPIO_EMC_40_ENET_MDIO { + pinmux = <0x401f80b4 4 0x401f8308 2 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_tx_data3: IOMUXC_GPIO_EMC_40_ENET_TX_DATA3 { + pinmux = <0x401f80b4 6 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io08: IOMUXC_GPIO_EMC_40_GPIO3_IO08 { + pinmux = <0x401f80b4 5 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt1_compare3: IOMUXC_GPIO_EMC_40_GPT1_COMPARE3 { + pinmux = <0x401f80b4 7 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_csx0: IOMUXC_GPIO_EMC_40_SEMC_CSX0 { + pinmux = <0x401f80b4 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_spdif_out: IOMUXC_GPIO_EMC_40_SPDIF_OUT { + pinmux = <0x401f80b4 2 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usb_otg1_id: IOMUXC_GPIO_EMC_40_USB_OTG1_ID { + pinmux = <0x401f80b4 3 0x401f82fc 2 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_xbar1_xbar_in18: IOMUXC_GPIO_EMC_40_XBAR1_XBAR_IN18 { + pinmux = <0x401f80b4 1 0x401f84bc 1 0x401f8228>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_40_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80b4 1 0x401f84bc 1 0x401f8228>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdc: IOMUXC_GPIO_EMC_41_ENET_MDC { + pinmux = <0x401f80b8 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_tx_data2: IOMUXC_GPIO_EMC_41_ENET_TX_DATA2 { + pinmux = <0x401f80b8 6 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io09: IOMUXC_GPIO_EMC_41_GPIO3_IO09 { + pinmux = <0x401f80b8 5 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt1_compare2: IOMUXC_GPIO_EMC_41_GPT1_COMPARE2 { + pinmux = <0x401f80b8 7 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_rdy: IOMUXC_GPIO_EMC_41_SEMC_RDY { + pinmux = <0x401f80b8 0 0x401f8484 1 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_spdif_in: IOMUXC_GPIO_EMC_41_SPDIF_IN { + pinmux = <0x401f80b8 2 0x401f8488 1 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usb_otg1_pwr: IOMUXC_GPIO_EMC_41_USB_OTG1_PWR { + pinmux = <0x401f80b8 3 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_xbar1_xbar_in19: IOMUXC_GPIO_EMC_41_XBAR1_XBAR_IN19 { + pinmux = <0x401f80b8 1 0x401f84c0 1 0x401f822c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_41_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80b8 1 0x401f84c0 1 0x401f822c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f813c 6 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io13: IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 { + pinmux = <0x401f813c 5 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f813c 4 0x401f838c 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_qtimer1_timer0: IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x401f8410 0 0x401f82b0>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_sai1_mclk: IOMUXC_GPIO_SD_B0_00_SAI1_MCLK { + pinmux = <0x401f813c 2 0x401f8430 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_sai2_mclk: IOMUXC_GPIO_SD_B0_00_SAI2_MCLK { + pinmux = <0x401f813c 3 0x401f8454 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_data2: IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 { + pinmux = <0x401f813c 0 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in14: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f813c 7 0x401f84a0 0 0x401f82b0>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout14: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f813c 7 0x401f84a0 0 0x401f82b0>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f8140 6 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io14: IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 { + pinmux = <0x401f8140 5 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f8140 4 0x401f8390 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_qtimer1_timer1: IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x401f8414 0 0x401f82b4>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_ref_24m_out: IOMUXC_GPIO_SD_B0_01_REF_24M_OUT { + pinmux = <0x401f8140 2 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_sai2_rx_sync: IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC { + pinmux = <0x401f8140 3 0x401f8460 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_data3: IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 { + pinmux = <0x401f8140 0 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in15: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8140 7 0x401f84a4 0 0x401f82b4>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout15: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8140 7 0x401f84a4 0 0x401f82b4>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_enet_mdio: IOMUXC_GPIO_SD_B0_02_ENET_MDIO { + pinmux = <0x401f8144 6 0x401f8308 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io15: IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 { + pinmux = <0x401f8144 5 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sck: IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK { + pinmux = <0x401f8144 4 0x401f83a0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart7_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B { + pinmux = <0x401f8144 2 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_qtimer1_timer2: IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x401f8418 0 0x401f82b8>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_sai2_rx_bclk: IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK { + pinmux = <0x401f8144 3 0x401f8458 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_cmd: IOMUXC_GPIO_SD_B0_02_USDHC1_CMD { + pinmux = <0x401f8144 0 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in16: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8144 7 0x401f84a8 0 0x401f82b8>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout16: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8144 7 0x401f84a8 0 0x401f82b8>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_enet_mdc: IOMUXC_GPIO_SD_B0_03_ENET_MDC { + pinmux = <0x401f8148 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io16: IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 { + pinmux = <0x401f8148 5 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0 { + pinmux = <0x401f8148 4 0x401f839c 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart7_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B { + pinmux = <0x401f8148 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_qtimer1_timer3: IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3 { + pinmux = <0x401f8148 1 0x401f841c 0 0x401f82bc>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_sai2_rx_data: IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA { + pinmux = <0x401f8148 3 0x401f845c 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_clk: IOMUXC_GPIO_SD_B0_03_USDHC1_CLK { + pinmux = <0x401f8148 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexcan2_tx: IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX { + pinmux = <0x401f814c 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f814c 6 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io17: IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 { + pinmux = <0x401f814c 5 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpspi1_sdo: IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO { + pinmux = <0x401f814c 4 0x401f83a8 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart7_tx: IOMUXC_GPIO_SD_B0_04_LPUART7_TX { + pinmux = <0x401f814c 2 0x401f8400 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_sai2_tx_data: IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA { + pinmux = <0x401f814c 3 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data0: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 { + pinmux = <0x401f814c 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexcan2_rx: IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX { + pinmux = <0x401f8150 1 0x401f8324 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f8150 6 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io18: IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 { + pinmux = <0x401f8150 5 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpspi1_sdi: IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI { + pinmux = <0x401f8150 4 0x401f83a4 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart7_rx: IOMUXC_GPIO_SD_B0_05_LPUART7_RX { + pinmux = <0x401f8150 2 0x401f83fc 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_sai2_tx_bclk: IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f8150 3 0x401f8464 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data1: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 { + pinmux = <0x401f8150 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_gpio3_io19: IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 { + pinmux = <0x401f8154 5 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_ref_32k_out: IOMUXC_GPIO_SD_B0_06_REF_32K_OUT { + pinmux = <0x401f8154 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_sai2_tx_sync: IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC { + pinmux = <0x401f8154 3 0x401f8468 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_usdhc1_cd_b: IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B { + pinmux = <0x401f8154 0 0x401f8490 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_usdhc1_reset_b: IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B { + pinmux = <0x401f8154 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_wdog1_b: IOMUXC_GPIO_SD_B0_06_WDOG1_B { + pinmux = <0x401f8154 4 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_xbar1_xbar_in17: IOMUXC_GPIO_SD_B0_06_XBAR1_XBAR_IN17 { + pinmux = <0x401f8154 6 0x401f84ac 0 0x401f82c8>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_xbar1_xbar_inout17: IOMUXC_GPIO_SD_B0_06_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8154 6 0x401f84ac 0 0x401f82c8>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexcan1_tx: IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX { + pinmux = <0x401f8158 4 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f8158 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io20: IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 { + pinmux = <0x401f8158 5 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart6_tx: IOMUXC_GPIO_SD_B1_00_LPUART6_TX { + pinmux = <0x401f8158 2 0x401f83f8 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data2: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 { + pinmux = <0x401f8158 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexcan1_rx: IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX { + pinmux = <0x401f815c 4 0x401f8320 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B { + pinmux = <0x401f815c 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK { + pinmux = <0x401f815c 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io21: IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 { + pinmux = <0x401f815c 5 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart6_rx: IOMUXC_GPIO_SD_B1_01_LPUART6_RX { + pinmux = <0x401f815c 2 0x401f83f4 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data3: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 { + pinmux = <0x401f815c 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_clko1: IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 { + pinmux = <0x401f8160 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_enet_1588_event1_out: IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT { + pinmux = <0x401f8160 4 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data0: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA0 { + pinmux = <0x401f8160 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io22: IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 { + pinmux = <0x401f8160 5 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpi2c4_scl: IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL { + pinmux = <0x401f8160 3 0x401f8394 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpuart8_tx: IOMUXC_GPIO_SD_B1_02_LPUART8_TX { + pinmux = <0x401f8160 2 0x401f8408 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_cmd: IOMUXC_GPIO_SD_B1_02_USDHC2_CMD { + pinmux = <0x401f8160 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_clko2: IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 { + pinmux = <0x401f8164 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_enet_1588_event1_in: IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN { + pinmux = <0x401f8164 4 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data2: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA2 { + pinmux = <0x401f8164 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io23: IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 { + pinmux = <0x401f8164 5 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpi2c4_sda: IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA { + pinmux = <0x401f8164 3 0x401f8398 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpuart8_rx: IOMUXC_GPIO_SD_B1_03_LPUART8_RX { + pinmux = <0x401f8164 2 0x401f8404 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_clk: IOMUXC_GPIO_SD_B1_03_USDHC2_CLK { + pinmux = <0x401f8164 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_wait: IOMUXC_GPIO_SD_B1_04_CCM_WAIT { + pinmux = <0x401f8168 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_ref_clk: IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK { + pinmux = <0x401f8168 3 0x401f8304 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_tx_clk: IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK { + pinmux = <0x401f8168 2 0x401f831c 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ewm_out_b: IOMUXC_GPIO_SD_B1_04_EWM_OUT_B { + pinmux = <0x401f8168 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_data1: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA1 { + pinmux = <0x401f8168 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io24: IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 { + pinmux = <0x401f8168 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_data0: IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f8168 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY { + pinmux = <0x401f816c 6 0x401f8300 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_enet_rx_data1: IOMUXC_GPIO_SD_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f816c 2 0x401f8310 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f816c 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f816c 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io25: IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 { + pinmux = <0x401f816c 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_mclk: IOMUXC_GPIO_SD_B1_05_SAI3_MCLK { + pinmux = <0x401f816c 3 0x401f846c 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_data1: IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f816c 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_ccm_stop: IOMUXC_GPIO_SD_B1_06_CCM_STOP { + pinmux = <0x401f8170 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_enet_rx_data0: IOMUXC_GPIO_SD_B1_06_ENET_RX_DATA0 { + pinmux = <0x401f8170 2 0x401f830c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_data3: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA3 { + pinmux = <0x401f8170 1 0x401f8374 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io26: IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 { + pinmux = <0x401f8170 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f8170 4 0x401f83ac 2 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK { + pinmux = <0x401f8170 3 0x401f847c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_cd_b: IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B { + pinmux = <0x401f8170 0 0x401f8498 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_enet_rx_en: IOMUXC_GPIO_SD_B1_07_ENET_RX_EN { + pinmux = <0x401f8174 2 0x401f8314 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f8174 1 0x401f8378 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io27: IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 { + pinmux = <0x401f8174 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f8174 4 0x401f83b0 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai3_tx_sync: IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC { + pinmux = <0x401f8174 3 0x401f8480 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B { + pinmux = <0x401f8174 0 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_enet_rx_er: IOMUXC_GPIO_SD_B1_08_ENET_RX_ER { + pinmux = <0x401f8178 2 0x401f8318 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f8178 1 0x401f8368 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io28: IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 { + pinmux = <0x401f8178 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f8178 4 0x401f83b8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai3_tx_data: IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA { + pinmux = <0x401f8178 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f8178 0 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_enet_tx_en: IOMUXC_GPIO_SD_B1_09_ENET_TX_EN { + pinmux = <0x401f817c 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data2: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA2 { + pinmux = <0x401f817c 1 0x401f8370 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io29: IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 { + pinmux = <0x401f817c 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f817c 4 0x401f83b4 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK { + pinmux = <0x401f817c 3 0x401f8470 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f817c 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_enet_tx_data0: IOMUXC_GPIO_SD_B1_10_ENET_TX_DATA0 { + pinmux = <0x401f8180 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data1: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA1 { + pinmux = <0x401f8180 1 0x401f836c 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io30: IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 { + pinmux = <0x401f8180 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f8180 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_sai3_rx_sync: IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC { + pinmux = <0x401f8180 3 0x401f8478 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f8180 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_enet_tx_data1: IOMUXC_GPIO_SD_B1_11_ENET_TX_DATA1 { + pinmux = <0x401f8184 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B { + pinmux = <0x401f8184 1 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io31: IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 { + pinmux = <0x401f8184 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8184 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_sai3_rx_data: IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA { + pinmux = <0x401f8184 3 0x401f8474 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8184 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_ccm_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ { + pinmux = <0x400a8008 0 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_gpio5_io02: IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 { + pinmux = <0x400a8008 5 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x401f840c 1 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1024cag4b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1024cag4b-pinctrl.dtsi new file mode 100644 index 000000000..48d9a7698 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1024cag4b-pinctrl.dtsi @@ -0,0 +1,2131 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1024CAG4B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpt1_compare1: IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 { + pinmux = <0x401f80bc 7 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_jtag_tms: IOMUXC_GPIO_AD_B0_00_JTAG_TMS { + pinmux = <0x401f80bc 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpt1_capture2: IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 { + pinmux = <0x401f80c0 7 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_jtag_tck: IOMUXC_GPIO_AD_B0_01_JTAG_TCK { + pinmux = <0x401f80c0 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpt1_capture1: IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 { + pinmux = <0x401f80c4 7 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_jtag_mod: IOMUXC_GPIO_AD_B0_02_JTAG_MOD { + pinmux = <0x401f80c4 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY { + pinmux = <0x401f80c8 7 0x401f8300 2 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_jtag_tdi: IOMUXC_GPIO_AD_B0_03_JTAG_TDI { + pinmux = <0x401f80c8 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_sai1_mclk: IOMUXC_GPIO_AD_B0_03_SAI1_MCLK { + pinmux = <0x401f80c8 3 0x401f8430 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 6 0x401f848c 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc1_wp: IOMUXC_GPIO_AD_B0_03_USDHC1_WP { + pinmux = <0x401f80c8 4 0x401f8494 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B { + pinmux = <0x401f80c8 1 0x401f8498 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_wdog1_b: IOMUXC_GPIO_AD_B0_03_WDOG1_B { + pinmux = <0x401f80c8 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_mdio: IOMUXC_GPIO_AD_B0_04_ENET_MDIO { + pinmux = <0x401f80cc 4 0x401f8308 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_ewm_out_b: IOMUXC_GPIO_AD_B0_04_EWM_OUT_B { + pinmux = <0x401f80cc 7 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_flexcan1_tx: IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX { + pinmux = <0x401f80cc 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_jtag_tdo: IOMUXC_GPIO_AD_B0_04_JTAG_TDO { + pinmux = <0x401f80cc 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_qtimer2_timer0: IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 { + pinmux = <0x401f80cc 3 0x401f8420 1 0x401f8240>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR { + pinmux = <0x401f80cc 6 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usdhc1_wp: IOMUXC_GPIO_AD_B0_04_USDHC1_WP { + pinmux = <0x401f80cc 2 0x401f8494 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_arm_nmi: IOMUXC_GPIO_AD_B0_05_ARM_NMI { + pinmux = <0x401f80d0 7 0x401f840c 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_mdc: IOMUXC_GPIO_AD_B0_05_ENET_MDC { + pinmux = <0x401f80d0 4 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_flexcan1_rx: IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX { + pinmux = <0x401f80d0 1 0x401f8320 2 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_jtag_trstb: IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB { + pinmux = <0x401f80d0 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_qtimer2_timer1: IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 { + pinmux = <0x401f80d0 3 0x401f8424 1 0x401f8244>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usb_otg1_id: IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID { + pinmux = <0x401f80d0 6 0x401f82fc 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usdhc1_cd_b: IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B { + pinmux = <0x401f80d0 2 0x401f8490 1 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA3 { + pinmux = <0x401f80d4 4 0x401f8354 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpuart1_tx: IOMUXC_GPIO_AD_B0_06_LPUART1_TX { + pinmux = <0x401f80d4 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_mqs_right: IOMUXC_GPIO_AD_B0_06_MQS_RIGHT { + pinmux = <0x401f80d4 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_pit_trigger0: IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER0 { + pinmux = <0x401f80d4 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_qtimer2_timer2: IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 { + pinmux = <0x401f80d4 3 0x401f8428 1 0x401f8248>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_ref_32k_out: IOMUXC_GPIO_AD_B0_06_REF_32K_OUT { + pinmux = <0x401f80d4 6 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_flexpwm2_pwmb3: IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB3 { + pinmux = <0x401f80d8 4 0x401f8364 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_lpuart1_rx: IOMUXC_GPIO_AD_B0_07_LPUART1_RX { + pinmux = <0x401f80d8 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_mqs_left: IOMUXC_GPIO_AD_B0_07_MQS_LEFT { + pinmux = <0x401f80d8 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_pit_trigger1: IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER1 { + pinmux = <0x401f80d8 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_qtimer2_timer3: IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 { + pinmux = <0x401f80d8 3 0x401f842c 1 0x401f824c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_ref_24m_out: IOMUXC_GPIO_AD_B0_07_REF_24M_OUT { + pinmux = <0x401f80d8 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_acmp1_in4: IOMUXC_GPIO_AD_B0_08_ACMP1_IN4 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_arm_cm7_txev: IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV { + pinmux = <0x401f80dc 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_ref_clk: IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK { + pinmux = <0x401f80dc 4 0x401f8304 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_tx_clk: IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK { + pinmux = <0x401f80dc 0 0x401f831c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_kpp_col0: IOMUXC_GPIO_AD_B0_08_KPP_COL0 { + pinmux = <0x401f80dc 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpi2c3_scl: IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL { + pinmux = <0x401f80dc 1 0x401f838c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B { + pinmux = <0x401f80dc 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_acmp2_in4: IOMUXC_GPIO_AD_B0_09_ACMP2_IN4 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_arm_cm7_rxev: IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV { + pinmux = <0x401f80e0 6 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data1: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA1 { + pinmux = <0x401f80e0 0 0x401f8310 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_kpp_row0: IOMUXC_GPIO_AD_B0_09_KPP_ROW0 { + pinmux = <0x401f80e0 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpi2c3_sda: IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA { + pinmux = <0x401f80e0 1 0x401f8390 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B { + pinmux = <0x401f80e0 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_acmp3_in4: IOMUXC_GPIO_AD_B0_10_ACMP3_IN4 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_clk: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_CLK { + pinmux = <0x401f80e4 6 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_rx_data0: IOMUXC_GPIO_AD_B0_10_ENET_RX_DATA0 { + pinmux = <0x401f80e4 0 0x401f830c 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f80e4 4 0x401f8350 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_kpp_col1: IOMUXC_GPIO_AD_B0_10_KPP_COL1 { + pinmux = <0x401f80e4 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpspi1_sck: IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK { + pinmux = <0x401f80e4 1 0x401f83a0 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpuart5_tx: IOMUXC_GPIO_AD_B0_10_LPUART5_TX { + pinmux = <0x401f80e4 2 0x401f83f0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_acmp4_in4: IOMUXC_GPIO_AD_B0_11_ACMP4_IN4 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_arm_trace_swo: IOMUXC_GPIO_AD_B0_11_ARM_TRACE_SWO { + pinmux = <0x401f80e8 6 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_rx_en: IOMUXC_GPIO_AD_B0_11_ENET_RX_EN { + pinmux = <0x401f80e8 0 0x401f8314 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f80e8 4 0x401f8360 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_kpp_row1: IOMUXC_GPIO_AD_B0_11_KPP_ROW1 { + pinmux = <0x401f80e8 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpspi1_pcs0: IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 { + pinmux = <0x401f80e8 1 0x401f839c 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpuart5_rx: IOMUXC_GPIO_AD_B0_11_LPUART5_RX { + pinmux = <0x401f80e8 2 0x401f83ec 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in0: IOMUXC_GPIO_AD_B0_12_ADC1_IN0 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_trace0: IOMUXC_GPIO_AD_B0_12_ARM_TRACE0 { + pinmux = <0x401f80ec 6 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_rx_er: IOMUXC_GPIO_AD_B0_12_ENET_RX_ER { + pinmux = <0x401f80ec 0 0x401f8318 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm2_pwma1: IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA1 { + pinmux = <0x401f80ec 4 0x401f834c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_kpp_col2: IOMUXC_GPIO_AD_B0_12_KPP_COL2 { + pinmux = <0x401f80ec 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpspi1_sdo: IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO { + pinmux = <0x401f80ec 1 0x401f83a8 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart3_cts_b: IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B { + pinmux = <0x401f80ec 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_snvs_vio_5_ctl: IOMUXC_GPIO_AD_B0_12_SNVS_VIO_5_CTL { + pinmux = <0x401f80ec 7 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc2_in0: IOMUXC_GPIO_AD_B0_13_ADC2_IN0 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_tx_en: IOMUXC_GPIO_AD_B0_13_ENET_TX_EN { + pinmux = <0x401f80f0 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm2_pwmb1: IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB1 { + pinmux = <0x401f80f0 4 0x401f835c 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_kpp_row2: IOMUXC_GPIO_AD_B0_13_KPP_ROW2 { + pinmux = <0x401f80f0 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpspi1_sdi: IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI { + pinmux = <0x401f80f0 1 0x401f83a4 1 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart3_rts_b: IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B { + pinmux = <0x401f80f0 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_snvs_vio_5_b: IOMUXC_GPIO_AD_B0_13_SNVS_VIO_5_B { + pinmux = <0x401f80f0 7 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp1_in0: IOMUXC_GPIO_AD_B0_14_ACMP1_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in0: IOMUXC_GPIO_AD_B0_14_ACMP2_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp3_in0: IOMUXC_GPIO_AD_B0_14_ACMP3_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp4_in0: IOMUXC_GPIO_AD_B0_14_ACMP4_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in1: IOMUXC_GPIO_AD_B0_14_ADC1_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc2_in1: IOMUXC_GPIO_AD_B0_14_ADC2_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_tx_data0: IOMUXC_GPIO_AD_B0_14_ENET_TX_DATA0 { + pinmux = <0x401f80f4 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexpwm2_pwma0: IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA0 { + pinmux = <0x401f80f4 4 0x401f8348 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_kpp_col3: IOMUXC_GPIO_AD_B0_14_KPP_COL3 { + pinmux = <0x401f80f4 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart3_tx: IOMUXC_GPIO_AD_B0_14_LPUART3_TX { + pinmux = <0x401f80f4 2 0x401f83dc 1 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_wdog1_any: IOMUXC_GPIO_AD_B0_14_WDOG1_ANY { + pinmux = <0x401f80f4 7 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp1_in1: IOMUXC_GPIO_AD_B0_15_ACMP1_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp2_in1: IOMUXC_GPIO_AD_B0_15_ACMP2_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in1: IOMUXC_GPIO_AD_B0_15_ACMP3_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp4_in1: IOMUXC_GPIO_AD_B0_15_ACMP4_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in2: IOMUXC_GPIO_AD_B0_15_ADC1_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc2_in2: IOMUXC_GPIO_AD_B0_15_ADC2_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_tx_data1: IOMUXC_GPIO_AD_B0_15_ENET_TX_DATA1 { + pinmux = <0x401f80f8 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 1 0x401f8324 2 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexpwm2_pwmb0: IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB0 { + pinmux = <0x401f80f8 4 0x401f8358 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_kpp_row3: IOMUXC_GPIO_AD_B0_15_KPP_ROW3 { + pinmux = <0x401f80f8 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart3_rx: IOMUXC_GPIO_AD_B0_15_LPUART3_RX { + pinmux = <0x401f80f8 2 0x401f83d8 1 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in3: IOMUXC_GPIO_AD_B1_06_ACMP3_IN3 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in6: IOMUXC_GPIO_AD_B1_06_ADC1_IN6 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in6: IOMUXC_GPIO_AD_B1_06_ADC2_IN6 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio1_flexio09: IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8114 4 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexpwm1_pwma0: IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA0 { + pinmux = <0x401f8114 1 0x401f8328 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_kpp_col7: IOMUXC_GPIO_AD_B1_06_KPP_COL7 { + pinmux = <0x401f8114 7 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpspi1_pcs3: IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3 { + pinmux = <0x401f8114 6 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B { + pinmux = <0x401f8114 2 0x401f83cc 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_sai1_rx_bclk: IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK { + pinmux = <0x401f8114 3 0x401f8434 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc1_reset_b: IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B { + pinmux = <0x401f8114 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp4_in3: IOMUXC_GPIO_AD_B1_07_ACMP4_IN3 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in7: IOMUXC_GPIO_AD_B1_07_ADC1_IN7 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in7: IOMUXC_GPIO_AD_B1_07_ADC2_IN7 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio1_flexio08: IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8118 4 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexpwm1_pwmb0: IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB0 { + pinmux = <0x401f8118 1 0x401f8338 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_kpp_row7: IOMUXC_GPIO_AD_B1_07_KPP_ROW7 { + pinmux = <0x401f8118 7 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpspi3_pcs3: IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3 { + pinmux = <0x401f8118 6 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B { + pinmux = <0x401f8118 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_sai1_tx_data1: IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA1 { + pinmux = <0x401f8118 3 0x401f8444 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc1_vselect: IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT { + pinmux = <0x401f8118 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_acmp1_in5: IOMUXC_GPIO_AD_B1_08_ACMP1_IN5 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc1_in8: IOMUXC_GPIO_AD_B1_08_ADC1_IN8 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc2_in8: IOMUXC_GPIO_AD_B1_08_ADC2_IN8 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexio1_flexio07: IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07 { + pinmux = <0x401f811c 4 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexpwm1_pwma1: IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA1 { + pinmux = <0x401f811c 1 0x401f832c 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio1_io24: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpi2c2_scl: IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL { + pinmux = <0x401f811c 0 0x401f8384 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpspi3_pcs2: IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2 { + pinmux = <0x401f811c 6 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpuart2_tx: IOMUXC_GPIO_AD_B1_08_LPUART2_TX { + pinmux = <0x401f811c 2 0x401f83d4 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_sai1_tx_data2: IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA2 { + pinmux = <0x401f811c 3 0x401f8440 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_xbar1_xbar_in12: IOMUXC_GPIO_AD_B1_08_XBAR1_XBAR_IN12 { + pinmux = <0x401f811c 7 0x401f84b4 1 0x401f8290>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_xbar1_xbar_inout12: IOMUXC_GPIO_AD_B1_08_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f811c 7 0x401f84b4 1 0x401f8290>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_acmp2_in5: IOMUXC_GPIO_AD_B1_09_ACMP2_IN5 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc1_in9: IOMUXC_GPIO_AD_B1_09_ADC1_IN9 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc2_in9: IOMUXC_GPIO_AD_B1_09_ADC2_IN9 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexio1_flexio06: IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO06 { + pinmux = <0x401f8120 4 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexpwm1_pwmb1: IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB1 { + pinmux = <0x401f8120 1 0x401f833c 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio1_io25: IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpi2c2_sda: IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA { + pinmux = <0x401f8120 0 0x401f8388 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpspi3_pcs1: IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 { + pinmux = <0x401f8120 6 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpuart2_rx: IOMUXC_GPIO_AD_B1_09_LPUART2_RX { + pinmux = <0x401f8120 2 0x401f83d0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_sai1_tx_data3: IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA3 { + pinmux = <0x401f8120 3 0x401f843c 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_xbar1_xbar_in13: IOMUXC_GPIO_AD_B1_09_XBAR1_XBAR_IN13 { + pinmux = <0x401f8120 7 0x401f84b8 1 0x401f8294>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_xbar1_xbar_inout13: IOMUXC_GPIO_AD_B1_09_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8120 7 0x401f84b8 1 0x401f8294>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_acmp3_in5: IOMUXC_GPIO_AD_B1_10_ACMP3_IN5 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in10: IOMUXC_GPIO_AD_B1_10_ADC1_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc2_in10: IOMUXC_GPIO_AD_B1_10_ADC2_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio1_flexio05: IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8124 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexpwm1_pwma2: IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA2 { + pinmux = <0x401f8124 1 0x401f8330 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpt2_capture1: IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 { + pinmux = <0x401f8124 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart4_tx: IOMUXC_GPIO_AD_B1_10_LPUART4_TX { + pinmux = <0x401f8124 2 0x401f83e8 1 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR { + pinmux = <0x401f8124 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B { + pinmux = <0x401f8124 3 0x401f8490 2 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_acmp4_in5: IOMUXC_GPIO_AD_B1_11_ACMP4_IN5 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in11: IOMUXC_GPIO_AD_B1_11_ADC1_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc2_in11: IOMUXC_GPIO_AD_B1_11_ADC2_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio1_flexio04: IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8128 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexpwm1_pwmb2: IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB2 { + pinmux = <0x401f8128 1 0x401f8340 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpt2_compare1: IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 { + pinmux = <0x401f8128 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart4_rx: IOMUXC_GPIO_AD_B1_11_LPUART4_RX { + pinmux = <0x401f8128 2 0x401f83e4 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usb_otg1_id: IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID { + pinmux = <0x401f8128 0 0x401f82fc 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usdhc1_wp: IOMUXC_GPIO_AD_B1_11_USDHC1_WP { + pinmux = <0x401f8128 3 0x401f8494 3 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_in6: IOMUXC_GPIO_AD_B1_12_ACMP1_IN6 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_out: IOMUXC_GPIO_AD_B1_12_ACMP1_OUT { + pinmux = <0x401f812c 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc1_in12: IOMUXC_GPIO_AD_B1_12_ADC1_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc2_in12: IOMUXC_GPIO_AD_B1_12_ADC2_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio1_flexio03: IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 { + pinmux = <0x401f812c 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexpwm1_pwma3: IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f812c 6 0x401f8334 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_lpspi3_sck: IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK { + pinmux = <0x401f812c 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usb_otg1_oc: IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC { + pinmux = <0x401f812c 0 0x401f848c 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B { + pinmux = <0x401f812c 3 0x401f8498 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_in6: IOMUXC_GPIO_AD_B1_13_ACMP2_IN6 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_out: IOMUXC_GPIO_AD_B1_13_ACMP2_OUT { + pinmux = <0x401f8130 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc1_in13: IOMUXC_GPIO_AD_B1_13_ADC1_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc2_in13: IOMUXC_GPIO_AD_B1_13_ADC2_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio1_flexio02: IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 { + pinmux = <0x401f8130 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8130 6 0x401f8344 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpi2c1_hreq: IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ { + pinmux = <0x401f8130 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpspi3_pcs0: IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 { + pinmux = <0x401f8130 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_usdhc2_wp: IOMUXC_GPIO_AD_B1_13_USDHC2_WP { + pinmux = <0x401f8130 3 0x401f849c 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_in6: IOMUXC_GPIO_AD_B1_14_ACMP3_IN6 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_out: IOMUXC_GPIO_AD_B1_14_ACMP3_OUT { + pinmux = <0x401f8134 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc1_in14: IOMUXC_GPIO_AD_B1_14_ADC1_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc2_in14: IOMUXC_GPIO_AD_B1_14_ADC2_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f8134 3 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio1_flexio01: IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8134 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpi2c1_scl: IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL { + pinmux = <0x401f8134 0 0x401f837c 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpspi3_sdo: IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO { + pinmux = <0x401f8134 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_in6: IOMUXC_GPIO_AD_B1_15_ACMP4_IN6 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_out: IOMUXC_GPIO_AD_B1_15_ACMP4_OUT { + pinmux = <0x401f8138 1 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc1_in15: IOMUXC_GPIO_AD_B1_15_ADC1_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc2_in15: IOMUXC_GPIO_AD_B1_15_ADC2_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f8138 3 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio1_flexio00: IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8138 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpi2c1_sda: IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA { + pinmux = <0x401f8138 0 0x401f8380 1 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpspi3_sdi: IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI { + pinmux = <0x401f8138 2 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexcan1_tx: IOMUXC_GPIO_EMC_00_FLEXCAN1_TX { + pinmux = <0x401f8014 6 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio2_io00: IOMUXC_GPIO_EMC_00_GPIO2_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 4 0x401f83b0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpuart4_cts_b: IOMUXC_GPIO_EMC_00_LPUART4_CTS_B { + pinmux = <0x401f8014 2 0x401f83e0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_pit_trigger2: IOMUXC_GPIO_EMC_00_PIT_TRIGGER2 { + pinmux = <0x401f8014 7 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_qtimer2_timer0: IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0 { + pinmux = <0x401f8014 1 0x401f8420 0 0x401f8188>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_spdif_sr_clk: IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK { + pinmux = <0x401f8014 3 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexcan1_rx: IOMUXC_GPIO_EMC_01_FLEXCAN1_RX { + pinmux = <0x401f8018 6 0x401f8320 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio2_io01: IOMUXC_GPIO_EMC_01_GPIO2_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 4 0x401f83ac 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpuart4_rts_b: IOMUXC_GPIO_EMC_01_LPUART4_RTS_B { + pinmux = <0x401f8018 2 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_pit_trigger3: IOMUXC_GPIO_EMC_01_PIT_TRIGGER3 { + pinmux = <0x401f8018 7 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_qtimer2_timer1: IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1 { + pinmux = <0x401f8018 1 0x401f8424 0 0x401f818c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_spdif_out: IOMUXC_GPIO_EMC_01_SPDIF_OUT { + pinmux = <0x401f8018 3 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio2_io02: IOMUXC_GPIO_EMC_02_GPIO2_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpi2c1_scl: IOMUXC_GPIO_EMC_02_LPI2C1_SCL { + pinmux = <0x401f801c 6 0x401f837c 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 4 0x401f83b8 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpuart4_tx: IOMUXC_GPIO_EMC_02_LPUART4_TX { + pinmux = <0x401f801c 2 0x401f83e8 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_qtimer2_timer2: IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2 { + pinmux = <0x401f801c 1 0x401f8428 0 0x401f8190>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_spdif_lock: IOMUXC_GPIO_EMC_02_SPDIF_LOCK { + pinmux = <0x401f801c 3 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio2_io03: IOMUXC_GPIO_EMC_03_GPIO2_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpi2c1_sda: IOMUXC_GPIO_EMC_03_LPI2C1_SDA { + pinmux = <0x401f8020 6 0x401f8380 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 4 0x401f83b4 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpuart4_rx: IOMUXC_GPIO_EMC_03_LPUART4_RX { + pinmux = <0x401f8020 2 0x401f83e4 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_qtimer2_timer3: IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3 { + pinmux = <0x401f8020 1 0x401f842c 0 0x401f8194>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_spdif_ext_clk: IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK { + pinmux = <0x401f8020 3 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio16: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 { + pinmux = <0x401f8024 4 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio2_io04: IOMUXC_GPIO_EMC_04_GPIO2_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_bclk: IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK { + pinmux = <0x401f8024 3 0x401f8464 1 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_spdif_out: IOMUXC_GPIO_EMC_04_SPDIF_OUT { + pinmux = <0x401f8024 2 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio17: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 { + pinmux = <0x401f8028 4 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio2_io05: IOMUXC_GPIO_EMC_05_GPIO2_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 3 0x401f8468 1 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_spdif_in: IOMUXC_GPIO_EMC_05_SPDIF_IN { + pinmux = <0x401f8028 2 0x401f8488 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio18: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 { + pinmux = <0x401f802c 4 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio2_io06: IOMUXC_GPIO_EMC_06_GPIO2_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_lpuart3_tx: IOMUXC_GPIO_EMC_06_LPUART3_TX { + pinmux = <0x401f802c 2 0x401f83dc 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_data: IOMUXC_GPIO_EMC_06_SAI2_TX_DATA { + pinmux = <0x401f802c 3 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio19: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 { + pinmux = <0x401f8030 4 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio2_io07: IOMUXC_GPIO_EMC_07_GPIO2_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_lpuart3_rx: IOMUXC_GPIO_EMC_07_LPUART3_RX { + pinmux = <0x401f8030 2 0x401f83d8 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_rx_sync: IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC { + pinmux = <0x401f8030 3 0x401f8460 1 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexcan2_tx: IOMUXC_GPIO_EMC_08_FLEXCAN2_TX { + pinmux = <0x401f8034 2 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio20: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 { + pinmux = <0x401f8034 4 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio2_io08: IOMUXC_GPIO_EMC_08_GPIO2_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 3 0x401f845c 1 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_rx: IOMUXC_GPIO_EMC_09_FLEXCAN2_RX { + pinmux = <0x401f8038 2 0x401f8324 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio21: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 { + pinmux = <0x401f8038 4 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio2_io09: IOMUXC_GPIO_EMC_09_GPIO2_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_bclk: IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK { + pinmux = <0x401f8038 3 0x401f8458 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_we: IOMUXC_GPIO_EMC_09_SEMC_WE { + pinmux = <0x401f8038 0 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_in09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_IN09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwmx0: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX0 { + pinmux = <0x401f803c 6 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio2_io10: IOMUXC_GPIO_EMC_10_GPIO2_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_lpi2c4_sda: IOMUXC_GPIO_EMC_10_LPI2C4_SDA { + pinmux = <0x401f803c 2 0x401f8398 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_lpspi2_sck: IOMUXC_GPIO_EMC_10_LPSPI2_SCK { + pinmux = <0x401f803c 4 0x401f83b0 1 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai1_tx_sync: IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC { + pinmux = <0x401f803c 3 0x401f8450 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_cas: IOMUXC_GPIO_EMC_10_SEMC_CAS { + pinmux = <0x401f803c 0 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_xbar1_xbar_in10: IOMUXC_GPIO_EMC_10_XBAR1_XBAR_IN10 { + pinmux = <0x401f803c 1 0x401f84b0 0 0x401f81b0>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_10_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f803c 1 0x401f84b0 0 0x401f81b0>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmx1: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX1 { + pinmux = <0x401f8040 6 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio2_io11: IOMUXC_GPIO_EMC_11_GPIO2_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_scl: IOMUXC_GPIO_EMC_11_LPI2C4_SCL { + pinmux = <0x401f8040 2 0x401f8394 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpspi2_pcs0: IOMUXC_GPIO_EMC_11_LPSPI2_PCS0 { + pinmux = <0x401f8040 4 0x401f83ac 1 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_sai1_tx_bclk: IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK { + pinmux = <0x401f8040 3 0x401f844c 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_ras: IOMUXC_GPIO_EMC_11_SEMC_RAS { + pinmux = <0x401f8040 0 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_xbar1_xbar_in11: IOMUXC_GPIO_EMC_11_XBAR1_XBAR_IN11 { + pinmux = <0x401f8040 1 0x0 0 0x401f81b4>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_11_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8040 1 0x0 0 0x401f81b4>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm2_pwmx2: IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX2 { + pinmux = <0x401f8044 6 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio2_io12: IOMUXC_GPIO_EMC_12_GPIO2_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpspi2_sdo: IOMUXC_GPIO_EMC_12_LPSPI2_SDO { + pinmux = <0x401f8044 4 0x401f83b8 1 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpuart6_tx: IOMUXC_GPIO_EMC_12_LPUART6_TX { + pinmux = <0x401f8044 2 0x401f83f8 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_sai1_tx_data0: IOMUXC_GPIO_EMC_12_SAI1_TX_DATA0 { + pinmux = <0x401f8044 3 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_cs0: IOMUXC_GPIO_EMC_12_SEMC_CS0 { + pinmux = <0x401f8044 0 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in12: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN12 { + pinmux = <0x401f8044 1 0x401f84b4 0 0x401f81b8>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8044 1 0x401f84b4 0 0x401f81b8>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_ccm_pmic_rdy: IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY { + pinmux = <0x401f8048 7 0x401f8300 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm2_pwmx3: IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX3 { + pinmux = <0x401f8048 6 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio2_io13: IOMUXC_GPIO_EMC_13_GPIO2_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpspi2_sdi: IOMUXC_GPIO_EMC_13_LPSPI2_SDI { + pinmux = <0x401f8048 4 0x401f83b4 1 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart6_rx: IOMUXC_GPIO_EMC_13_LPUART6_RX { + pinmux = <0x401f8048 2 0x401f83f4 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_sai1_rx_data0: IOMUXC_GPIO_EMC_13_SAI1_RX_DATA0 { + pinmux = <0x401f8048 3 0x401f8438 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_ba0: IOMUXC_GPIO_EMC_13_SEMC_BA0 { + pinmux = <0x401f8048 0 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in13: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN13 { + pinmux = <0x401f8048 1 0x401f84b8 0 0x401f81bc>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8048 1 0x401f84b8 0 0x401f81bc>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_flexcan1_tx: IOMUXC_GPIO_EMC_14_FLEXCAN1_TX { + pinmux = <0x401f804c 6 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio2_io14: IOMUXC_GPIO_EMC_14_GPIO2_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart6_cts_b: IOMUXC_GPIO_EMC_14_LPUART6_CTS_B { + pinmux = <0x401f804c 2 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_sai1_rx_bclk: IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK { + pinmux = <0x401f804c 3 0x401f8434 1 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_ba1: IOMUXC_GPIO_EMC_14_SEMC_BA1 { + pinmux = <0x401f804c 0 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in14: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN14 { + pinmux = <0x401f804c 1 0x401f84a0 1 0x401f81c0>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f804c 1 0x401f84a0 1 0x401f81c0>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_flexcan1_rx: IOMUXC_GPIO_EMC_15_FLEXCAN1_RX { + pinmux = <0x401f8050 6 0x401f8320 3 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio2_io15: IOMUXC_GPIO_EMC_15_GPIO2_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart6_rts_b: IOMUXC_GPIO_EMC_15_LPUART6_RTS_B { + pinmux = <0x401f8050 2 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_sai1_rx_sync: IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC { + pinmux = <0x401f8050 3 0x401f8448 1 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr10: IOMUXC_GPIO_EMC_15_SEMC_ADDR10 { + pinmux = <0x401f8050 0 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_wdog1_b: IOMUXC_GPIO_EMC_15_WDOG1_B { + pinmux = <0x401f8050 4 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in15: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN15 { + pinmux = <0x401f8050 1 0x401f84a4 1 0x401f81c4>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8050 1 0x401f84a4 1 0x401f81c4>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio2_io16: IOMUXC_GPIO_EMC_16_GPIO2_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_mqs_right: IOMUXC_GPIO_EMC_16_MQS_RIGHT { + pinmux = <0x401f8054 2 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_sai2_mclk: IOMUXC_GPIO_EMC_16_SAI2_MCLK { + pinmux = <0x401f8054 3 0x401f8454 1 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr00: IOMUXC_GPIO_EMC_16_SEMC_ADDR00 { + pinmux = <0x401f8054 0 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_src_boot_mode0: IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE0 { + pinmux = <0x401f8054 6 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio2_io17: IOMUXC_GPIO_EMC_17_GPIO2_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_mqs_left: IOMUXC_GPIO_EMC_17_MQS_LEFT { + pinmux = <0x401f8058 2 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_sai3_mclk: IOMUXC_GPIO_EMC_17_SAI3_MCLK { + pinmux = <0x401f8058 3 0x401f846c 1 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr01: IOMUXC_GPIO_EMC_17_SEMC_ADDR01 { + pinmux = <0x401f8058 0 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_src_boot_mode1: IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE1 { + pinmux = <0x401f8058 6 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexio1_flexio22: IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 { + pinmux = <0x401f805c 4 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio2_io18: IOMUXC_GPIO_EMC_18_GPIO2_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpi2c2_sda: IOMUXC_GPIO_EMC_18_LPI2C2_SDA { + pinmux = <0x401f805c 2 0x401f8388 1 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_sai1_rx_sync: IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC { + pinmux = <0x401f805c 3 0x401f8448 2 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr02: IOMUXC_GPIO_EMC_18_SEMC_ADDR02 { + pinmux = <0x401f805c 0 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_src_bt_cfg0: IOMUXC_GPIO_EMC_18_SRC_BT_CFG0 { + pinmux = <0x401f805c 6 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_IN16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexio1_flexio23: IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 { + pinmux = <0x401f8060 4 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio2_io19: IOMUXC_GPIO_EMC_19_GPIO2_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpi2c2_scl: IOMUXC_GPIO_EMC_19_LPI2C2_SCL { + pinmux = <0x401f8060 2 0x401f8384 1 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_sai1_rx_bclk: IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK { + pinmux = <0x401f8060 3 0x401f8434 2 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr03: IOMUXC_GPIO_EMC_19_SEMC_ADDR03 { + pinmux = <0x401f8060 0 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_src_bt_cfg1: IOMUXC_GPIO_EMC_19_SRC_BT_CFG1 { + pinmux = <0x401f8060 6 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_in17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_IN17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexio1_flexio24: IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 { + pinmux = <0x401f8064 4 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm1_pwma3: IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA3 { + pinmux = <0x401f8064 1 0x401f8334 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio2_io20: IOMUXC_GPIO_EMC_20_GPIO2_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart2_cts_b: IOMUXC_GPIO_EMC_20_LPUART2_CTS_B { + pinmux = <0x401f8064 2 0x401f83cc 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_sai1_mclk: IOMUXC_GPIO_EMC_20_SAI1_MCLK { + pinmux = <0x401f8064 3 0x401f8430 3 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr04: IOMUXC_GPIO_EMC_20_SEMC_ADDR04 { + pinmux = <0x401f8064 0 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_src_bt_cfg2: IOMUXC_GPIO_EMC_20_SRC_BT_CFG2 { + pinmux = <0x401f8064 6 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexio1_flexio25: IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 { + pinmux = <0x401f8068 4 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB3 { + pinmux = <0x401f8068 1 0x401f8344 1 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio2_io21: IOMUXC_GPIO_EMC_21_GPIO2_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpuart2_rts_b: IOMUXC_GPIO_EMC_21_LPUART2_RTS_B { + pinmux = <0x401f8068 2 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_sai1_rx_data0: IOMUXC_GPIO_EMC_21_SAI1_RX_DATA0 { + pinmux = <0x401f8068 3 0x401f8438 2 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_addr05: IOMUXC_GPIO_EMC_21_SEMC_ADDR05 { + pinmux = <0x401f8068 0 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_src_bt_cfg3: IOMUXC_GPIO_EMC_21_SRC_BT_CFG3 { + pinmux = <0x401f8068 6 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexio1_flexio26: IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 { + pinmux = <0x401f806c 4 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm1_pwma2: IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA2 { + pinmux = <0x401f806c 1 0x401f8330 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio2_io22: IOMUXC_GPIO_EMC_22_GPIO2_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpuart2_tx: IOMUXC_GPIO_EMC_22_LPUART2_TX { + pinmux = <0x401f806c 2 0x401f83d4 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_sai1_tx_data3: IOMUXC_GPIO_EMC_22_SAI1_TX_DATA3 { + pinmux = <0x401f806c 3 0x401f843c 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_addr06: IOMUXC_GPIO_EMC_22_SEMC_ADDR06 { + pinmux = <0x401f806c 0 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_src_bt_cfg4: IOMUXC_GPIO_EMC_22_SRC_BT_CFG4 { + pinmux = <0x401f806c 6 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexio1_flexio27: IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 { + pinmux = <0x401f8070 4 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB2 { + pinmux = <0x401f8070 1 0x401f8340 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio2_io23: IOMUXC_GPIO_EMC_23_GPIO2_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart2_rx: IOMUXC_GPIO_EMC_23_LPUART2_RX { + pinmux = <0x401f8070 2 0x401f83d0 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_sai1_tx_data2: IOMUXC_GPIO_EMC_23_SAI1_TX_DATA2 { + pinmux = <0x401f8070 3 0x401f8440 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr07: IOMUXC_GPIO_EMC_23_SEMC_ADDR07 { + pinmux = <0x401f8070 0 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_src_bt_cfg5: IOMUXC_GPIO_EMC_23_SRC_BT_CFG5 { + pinmux = <0x401f8070 6 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexio1_flexio28: IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 { + pinmux = <0x401f8074 4 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwma1: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA1 { + pinmux = <0x401f8074 1 0x401f832c 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio2_io24: IOMUXC_GPIO_EMC_24_GPIO2_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart8_cts_b: IOMUXC_GPIO_EMC_24_LPUART8_CTS_B { + pinmux = <0x401f8074 2 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_sai1_tx_data1: IOMUXC_GPIO_EMC_24_SAI1_TX_DATA1 { + pinmux = <0x401f8074 3 0x401f8444 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_addr08: IOMUXC_GPIO_EMC_24_SEMC_ADDR08 { + pinmux = <0x401f8074 0 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_src_bt_cfg6: IOMUXC_GPIO_EMC_24_SRC_BT_CFG6 { + pinmux = <0x401f8074 6 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexio1_flexio29: IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 { + pinmux = <0x401f8078 4 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB1 { + pinmux = <0x401f8078 1 0x401f833c 1 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio2_io25: IOMUXC_GPIO_EMC_25_GPIO2_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart8_rts_b: IOMUXC_GPIO_EMC_25_LPUART8_RTS_B { + pinmux = <0x401f8078 2 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_sai1_tx_data0: IOMUXC_GPIO_EMC_25_SAI1_TX_DATA0 { + pinmux = <0x401f8078 3 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_addr09: IOMUXC_GPIO_EMC_25_SEMC_ADDR09 { + pinmux = <0x401f8078 0 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_src_bt_cfg7: IOMUXC_GPIO_EMC_25_SRC_BT_CFG7 { + pinmux = <0x401f8078 6 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio30: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 { + pinmux = <0x401f807c 4 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwma0: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA0 { + pinmux = <0x401f807c 1 0x401f8328 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio2_io26: IOMUXC_GPIO_EMC_26_GPIO2_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart8_tx: IOMUXC_GPIO_EMC_26_LPUART8_TX { + pinmux = <0x401f807c 2 0x401f8408 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_sai1_tx_bclk: IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK { + pinmux = <0x401f807c 3 0x401f844c 2 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_addr11: IOMUXC_GPIO_EMC_26_SEMC_ADDR11 { + pinmux = <0x401f807c 0 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_src_bt_cfg8: IOMUXC_GPIO_EMC_26_SRC_BT_CFG8 { + pinmux = <0x401f807c 6 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio31: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 { + pinmux = <0x401f8080 4 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB0 { + pinmux = <0x401f8080 1 0x401f8338 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio2_io27: IOMUXC_GPIO_EMC_27_GPIO2_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart8_rx: IOMUXC_GPIO_EMC_27_LPUART8_RX { + pinmux = <0x401f8080 2 0x401f8404 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_sai1_tx_sync: IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC { + pinmux = <0x401f8080 3 0x401f8450 2 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_addr12: IOMUXC_GPIO_EMC_27_SEMC_ADDR12 { + pinmux = <0x401f8080 0 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_src_bt_cfg9: IOMUXC_GPIO_EMC_27_SRC_BT_CFG9 { + pinmux = <0x401f8080 6 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_ewm_out_b: IOMUXC_GPIO_EMC_28_EWM_OUT_B { + pinmux = <0x401f8084 4 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmx0: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX0 { + pinmux = <0x401f8084 7 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm2_pwma3: IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA3 { + pinmux = <0x401f8084 1 0x401f8354 1 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio2_io28: IOMUXC_GPIO_EMC_28_GPIO2_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpt2_capture2: IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2 { + pinmux = <0x401f8084 6 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_sai3_mclk: IOMUXC_GPIO_EMC_28_SAI3_MCLK { + pinmux = <0x401f8084 3 0x401f846c 2 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_dqs: IOMUXC_GPIO_EMC_28_SEMC_DQS { + pinmux = <0x401f8084 0 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_xbar1_xbar_in18: IOMUXC_GPIO_EMC_28_XBAR1_XBAR_IN18 { + pinmux = <0x401f8084 2 0x401f84bc 0 0x401f81f8>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_28_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f8084 2 0x401f84bc 0 0x401f81f8>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm1_pwmx1: IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX1 { + pinmux = <0x401f8088 7 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB3 { + pinmux = <0x401f8088 1 0x401f8364 1 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio2_io29: IOMUXC_GPIO_EMC_29_GPIO2_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpt2_compare2: IOMUXC_GPIO_EMC_29_GPT2_COMPARE2 { + pinmux = <0x401f8088 6 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_sai3_rx_bclk: IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK { + pinmux = <0x401f8088 3 0x401f8470 1 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cke: IOMUXC_GPIO_EMC_29_SEMC_CKE { + pinmux = <0x401f8088 0 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_wdog2_rst_b_deb: IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB { + pinmux = <0x401f8088 4 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_xbar1_xbar_in19: IOMUXC_GPIO_EMC_29_XBAR1_XBAR_IN19 { + pinmux = <0x401f8088 2 0x401f84c0 0 0x401f81fc>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_29_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f8088 2 0x401f84c0 0 0x401f81fc>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm1_pwmx2: IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX2 { + pinmux = <0x401f808c 7 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm2_pwma2: IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA2 { + pinmux = <0x401f808c 1 0x401f8350 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio2_io30: IOMUXC_GPIO_EMC_30_GPIO2_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpt2_compare3: IOMUXC_GPIO_EMC_30_GPT2_COMPARE3 { + pinmux = <0x401f808c 6 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart4_cts_b: IOMUXC_GPIO_EMC_30_LPUART4_CTS_B { + pinmux = <0x401f808c 2 0x401f83e0 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_sai3_rx_sync: IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC { + pinmux = <0x401f808c 3 0x401f8478 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_clk: IOMUXC_GPIO_EMC_30_SEMC_CLK { + pinmux = <0x401f808c 0 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_wdog1_rst_b_deb: IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB { + pinmux = <0x401f808c 4 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm1_pwmx3: IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX3 { + pinmux = <0x401f8090 7 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB2 { + pinmux = <0x401f8090 1 0x401f8360 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio2_io31: IOMUXC_GPIO_EMC_31_GPIO2_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpt2_clk: IOMUXC_GPIO_EMC_31_GPT2_CLK { + pinmux = <0x401f8090 6 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart4_rts_b: IOMUXC_GPIO_EMC_31_LPUART4_RTS_B { + pinmux = <0x401f8090 2 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_sai3_rx_data: IOMUXC_GPIO_EMC_31_SAI3_RX_DATA { + pinmux = <0x401f8090 3 0x401f8474 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_dm1: IOMUXC_GPIO_EMC_31_SEMC_DM1 { + pinmux = <0x401f8090 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_wdog2_b: IOMUXC_GPIO_EMC_31_WDOG2_B { + pinmux = <0x401f8090 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io00: IOMUXC_GPIO_EMC_32_GPIO3_IO00 { + pinmux = <0x401f8094 5 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpspi4_sck: IOMUXC_GPIO_EMC_32_LPSPI4_SCK { + pinmux = <0x401f8094 4 0x401f83c0 1 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart4_tx: IOMUXC_GPIO_EMC_32_LPUART4_TX { + pinmux = <0x401f8094 2 0x401f83e8 2 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_qtimer1_timer0: IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 { + pinmux = <0x401f8094 1 0x401f8410 1 0x401f8208>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ref_24m_out: IOMUXC_GPIO_EMC_32_REF_24M_OUT { + pinmux = <0x401f8094 7 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_sai3_tx_data: IOMUXC_GPIO_EMC_32_SAI3_TX_DATA { + pinmux = <0x401f8094 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data08: IOMUXC_GPIO_EMC_32_SEMC_DATA08 { + pinmux = <0x401f8094 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io01: IOMUXC_GPIO_EMC_33_GPIO3_IO01 { + pinmux = <0x401f8098 5 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpspi4_pcs0: IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 { + pinmux = <0x401f8098 4 0x401f83bc 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpuart4_rx: IOMUXC_GPIO_EMC_33_LPUART4_RX { + pinmux = <0x401f8098 2 0x401f83e4 2 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_qtimer1_timer1: IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 { + pinmux = <0x401f8098 1 0x401f8414 1 0x401f820c>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_tx_bclk: IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK { + pinmux = <0x401f8098 3 0x401f847c 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data09: IOMUXC_GPIO_EMC_33_SEMC_DATA09 { + pinmux = <0x401f8098 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_enet_crs: IOMUXC_GPIO_EMC_34_ENET_CRS { + pinmux = <0x401f809c 6 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io02: IOMUXC_GPIO_EMC_34_GPIO3_IO02 { + pinmux = <0x401f809c 5 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpspi4_sdo: IOMUXC_GPIO_EMC_34_LPSPI4_SDO { + pinmux = <0x401f809c 4 0x401f83c8 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpuart7_tx: IOMUXC_GPIO_EMC_34_LPUART7_TX { + pinmux = <0x401f809c 2 0x401f8400 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_qtimer1_timer2: IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 { + pinmux = <0x401f809c 1 0x401f8418 1 0x401f8210>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_tx_sync: IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC { + pinmux = <0x401f809c 3 0x401f8480 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data10: IOMUXC_GPIO_EMC_34_SEMC_DATA10 { + pinmux = <0x401f809c 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_enet_col: IOMUXC_GPIO_EMC_35_ENET_COL { + pinmux = <0x401f80a0 6 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io03: IOMUXC_GPIO_EMC_35_GPIO3_IO03 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpspi4_sdi: IOMUXC_GPIO_EMC_35_LPSPI4_SDI { + pinmux = <0x401f80a0 4 0x401f83c4 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpuart7_rx: IOMUXC_GPIO_EMC_35_LPUART7_RX { + pinmux = <0x401f80a0 2 0x401f83fc 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_qtimer1_timer3: IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 { + pinmux = <0x401f80a0 1 0x401f841c 1 0x401f8214>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data11: IOMUXC_GPIO_EMC_35_SEMC_DATA11 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc2_wp: IOMUXC_GPIO_EMC_35_USDHC2_WP { + pinmux = <0x401f80a0 3 0x401f849c 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_ccm_pmic_rdy: IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY { + pinmux = <0x401f80a4 3 0x401f8300 3 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_enet_rx_clk: IOMUXC_GPIO_EMC_36_ENET_RX_CLK { + pinmux = <0x401f80a4 6 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexpwm2_pwma1: IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA1 { + pinmux = <0x401f80a4 1 0x401f834c 1 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io04: IOMUXC_GPIO_EMC_36_GPIO3_IO04 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_lpspi4_pcs1: IOMUXC_GPIO_EMC_36_LPSPI4_PCS1 { + pinmux = <0x401f80a4 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_lpuart5_cts_b: IOMUXC_GPIO_EMC_36_LPUART5_CTS_B { + pinmux = <0x401f80a4 2 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data12: IOMUXC_GPIO_EMC_36_SEMC_DATA12 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 7 0x401f8494 4 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_enet_rx_data3: IOMUXC_GPIO_EMC_37_ENET_RX_DATA3 { + pinmux = <0x401f80a8 6 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB1 { + pinmux = <0x401f80a8 1 0x401f835c 1 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io05: IOMUXC_GPIO_EMC_37_GPIO3_IO05 { + pinmux = <0x401f80a8 5 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_lpspi4_pcs2: IOMUXC_GPIO_EMC_37_LPSPI4_PCS2 { + pinmux = <0x401f80a8 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_lpuart5_rts_b: IOMUXC_GPIO_EMC_37_LPUART5_RTS_B { + pinmux = <0x401f80a8 2 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_mqs_right: IOMUXC_GPIO_EMC_37_MQS_RIGHT { + pinmux = <0x401f80a8 3 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data13: IOMUXC_GPIO_EMC_37_SEMC_DATA13 { + pinmux = <0x401f80a8 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc1_vselect: IOMUXC_GPIO_EMC_37_USDHC1_VSELECT { + pinmux = <0x401f80a8 7 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_enet_rx_data2: IOMUXC_GPIO_EMC_38_ENET_RX_DATA2 { + pinmux = <0x401f80ac 6 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm2_pwma0: IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA0 { + pinmux = <0x401f80ac 1 0x401f8348 1 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io06: IOMUXC_GPIO_EMC_38_GPIO3_IO06 { + pinmux = <0x401f80ac 5 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpspi4_pcs3: IOMUXC_GPIO_EMC_38_LPSPI4_PCS3 { + pinmux = <0x401f80ac 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart5_tx: IOMUXC_GPIO_EMC_38_LPUART5_TX { + pinmux = <0x401f80ac 2 0x401f83f0 1 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_mqs_left: IOMUXC_GPIO_EMC_38_MQS_LEFT { + pinmux = <0x401f80ac 3 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_data14: IOMUXC_GPIO_EMC_38_SEMC_DATA14 { + pinmux = <0x401f80ac 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc1_cd_b: IOMUXC_GPIO_EMC_38_USDHC1_CD_B { + pinmux = <0x401f80ac 7 0x401f8490 3 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_enet_tx_er: IOMUXC_GPIO_EMC_39_ENET_TX_ER { + pinmux = <0x401f80b0 6 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB0 { + pinmux = <0x401f80b0 1 0x401f8358 1 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io07: IOMUXC_GPIO_EMC_39_GPIO3_IO07 { + pinmux = <0x401f80b0 5 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpt1_clk: IOMUXC_GPIO_EMC_39_GPT1_CLK { + pinmux = <0x401f80b0 7 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart5_rx: IOMUXC_GPIO_EMC_39_LPUART5_RX { + pinmux = <0x401f80b0 2 0x401f83ec 1 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_data15: IOMUXC_GPIO_EMC_39_SEMC_DATA15 { + pinmux = <0x401f80b0 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usb_otg1_oc: IOMUXC_GPIO_EMC_39_USB_OTG1_OC { + pinmux = <0x401f80b0 3 0x401f848c 2 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdio: IOMUXC_GPIO_EMC_40_ENET_MDIO { + pinmux = <0x401f80b4 4 0x401f8308 2 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_tx_data3: IOMUXC_GPIO_EMC_40_ENET_TX_DATA3 { + pinmux = <0x401f80b4 6 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io08: IOMUXC_GPIO_EMC_40_GPIO3_IO08 { + pinmux = <0x401f80b4 5 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt1_compare3: IOMUXC_GPIO_EMC_40_GPT1_COMPARE3 { + pinmux = <0x401f80b4 7 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_csx0: IOMUXC_GPIO_EMC_40_SEMC_CSX0 { + pinmux = <0x401f80b4 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_spdif_out: IOMUXC_GPIO_EMC_40_SPDIF_OUT { + pinmux = <0x401f80b4 2 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usb_otg1_id: IOMUXC_GPIO_EMC_40_USB_OTG1_ID { + pinmux = <0x401f80b4 3 0x401f82fc 2 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_xbar1_xbar_in18: IOMUXC_GPIO_EMC_40_XBAR1_XBAR_IN18 { + pinmux = <0x401f80b4 1 0x401f84bc 1 0x401f8228>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_40_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80b4 1 0x401f84bc 1 0x401f8228>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdc: IOMUXC_GPIO_EMC_41_ENET_MDC { + pinmux = <0x401f80b8 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_tx_data2: IOMUXC_GPIO_EMC_41_ENET_TX_DATA2 { + pinmux = <0x401f80b8 6 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io09: IOMUXC_GPIO_EMC_41_GPIO3_IO09 { + pinmux = <0x401f80b8 5 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt1_compare2: IOMUXC_GPIO_EMC_41_GPT1_COMPARE2 { + pinmux = <0x401f80b8 7 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_rdy: IOMUXC_GPIO_EMC_41_SEMC_RDY { + pinmux = <0x401f80b8 0 0x401f8484 1 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_spdif_in: IOMUXC_GPIO_EMC_41_SPDIF_IN { + pinmux = <0x401f80b8 2 0x401f8488 1 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usb_otg1_pwr: IOMUXC_GPIO_EMC_41_USB_OTG1_PWR { + pinmux = <0x401f80b8 3 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_xbar1_xbar_in19: IOMUXC_GPIO_EMC_41_XBAR1_XBAR_IN19 { + pinmux = <0x401f80b8 1 0x401f84c0 1 0x401f822c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_41_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80b8 1 0x401f84c0 1 0x401f822c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f813c 6 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io13: IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 { + pinmux = <0x401f813c 5 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f813c 4 0x401f838c 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_qtimer1_timer0: IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x401f8410 0 0x401f82b0>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_sai1_mclk: IOMUXC_GPIO_SD_B0_00_SAI1_MCLK { + pinmux = <0x401f813c 2 0x401f8430 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_sai2_mclk: IOMUXC_GPIO_SD_B0_00_SAI2_MCLK { + pinmux = <0x401f813c 3 0x401f8454 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_data2: IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 { + pinmux = <0x401f813c 0 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in14: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f813c 7 0x401f84a0 0 0x401f82b0>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout14: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f813c 7 0x401f84a0 0 0x401f82b0>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f8140 6 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io14: IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 { + pinmux = <0x401f8140 5 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f8140 4 0x401f8390 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_qtimer1_timer1: IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x401f8414 0 0x401f82b4>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_ref_24m_out: IOMUXC_GPIO_SD_B0_01_REF_24M_OUT { + pinmux = <0x401f8140 2 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_sai2_rx_sync: IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC { + pinmux = <0x401f8140 3 0x401f8460 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_data3: IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 { + pinmux = <0x401f8140 0 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in15: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8140 7 0x401f84a4 0 0x401f82b4>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout15: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8140 7 0x401f84a4 0 0x401f82b4>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_enet_mdio: IOMUXC_GPIO_SD_B0_02_ENET_MDIO { + pinmux = <0x401f8144 6 0x401f8308 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io15: IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 { + pinmux = <0x401f8144 5 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sck: IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK { + pinmux = <0x401f8144 4 0x401f83a0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart7_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B { + pinmux = <0x401f8144 2 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_qtimer1_timer2: IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x401f8418 0 0x401f82b8>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_sai2_rx_bclk: IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK { + pinmux = <0x401f8144 3 0x401f8458 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_cmd: IOMUXC_GPIO_SD_B0_02_USDHC1_CMD { + pinmux = <0x401f8144 0 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in16: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8144 7 0x401f84a8 0 0x401f82b8>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout16: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8144 7 0x401f84a8 0 0x401f82b8>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_enet_mdc: IOMUXC_GPIO_SD_B0_03_ENET_MDC { + pinmux = <0x401f8148 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io16: IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 { + pinmux = <0x401f8148 5 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0 { + pinmux = <0x401f8148 4 0x401f839c 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart7_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B { + pinmux = <0x401f8148 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_qtimer1_timer3: IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3 { + pinmux = <0x401f8148 1 0x401f841c 0 0x401f82bc>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_sai2_rx_data: IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA { + pinmux = <0x401f8148 3 0x401f845c 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_clk: IOMUXC_GPIO_SD_B0_03_USDHC1_CLK { + pinmux = <0x401f8148 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexcan2_tx: IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX { + pinmux = <0x401f814c 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f814c 6 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io17: IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 { + pinmux = <0x401f814c 5 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpspi1_sdo: IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO { + pinmux = <0x401f814c 4 0x401f83a8 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart7_tx: IOMUXC_GPIO_SD_B0_04_LPUART7_TX { + pinmux = <0x401f814c 2 0x401f8400 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_sai2_tx_data: IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA { + pinmux = <0x401f814c 3 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data0: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 { + pinmux = <0x401f814c 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexcan2_rx: IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX { + pinmux = <0x401f8150 1 0x401f8324 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f8150 6 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io18: IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 { + pinmux = <0x401f8150 5 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpspi1_sdi: IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI { + pinmux = <0x401f8150 4 0x401f83a4 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart7_rx: IOMUXC_GPIO_SD_B0_05_LPUART7_RX { + pinmux = <0x401f8150 2 0x401f83fc 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_sai2_tx_bclk: IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f8150 3 0x401f8464 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data1: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 { + pinmux = <0x401f8150 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_gpio3_io19: IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 { + pinmux = <0x401f8154 5 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_ref_32k_out: IOMUXC_GPIO_SD_B0_06_REF_32K_OUT { + pinmux = <0x401f8154 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_sai2_tx_sync: IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC { + pinmux = <0x401f8154 3 0x401f8468 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_usdhc1_cd_b: IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B { + pinmux = <0x401f8154 0 0x401f8490 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_usdhc1_reset_b: IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B { + pinmux = <0x401f8154 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_wdog1_b: IOMUXC_GPIO_SD_B0_06_WDOG1_B { + pinmux = <0x401f8154 4 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_xbar1_xbar_in17: IOMUXC_GPIO_SD_B0_06_XBAR1_XBAR_IN17 { + pinmux = <0x401f8154 6 0x401f84ac 0 0x401f82c8>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_xbar1_xbar_inout17: IOMUXC_GPIO_SD_B0_06_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8154 6 0x401f84ac 0 0x401f82c8>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexcan1_tx: IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX { + pinmux = <0x401f8158 4 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f8158 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io20: IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 { + pinmux = <0x401f8158 5 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart6_tx: IOMUXC_GPIO_SD_B1_00_LPUART6_TX { + pinmux = <0x401f8158 2 0x401f83f8 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data2: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 { + pinmux = <0x401f8158 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexcan1_rx: IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX { + pinmux = <0x401f815c 4 0x401f8320 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B { + pinmux = <0x401f815c 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK { + pinmux = <0x401f815c 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io21: IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 { + pinmux = <0x401f815c 5 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart6_rx: IOMUXC_GPIO_SD_B1_01_LPUART6_RX { + pinmux = <0x401f815c 2 0x401f83f4 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data3: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 { + pinmux = <0x401f815c 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_clko1: IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 { + pinmux = <0x401f8160 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_enet_1588_event1_out: IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT { + pinmux = <0x401f8160 4 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data0: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA0 { + pinmux = <0x401f8160 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io22: IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 { + pinmux = <0x401f8160 5 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpi2c4_scl: IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL { + pinmux = <0x401f8160 3 0x401f8394 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpuart8_tx: IOMUXC_GPIO_SD_B1_02_LPUART8_TX { + pinmux = <0x401f8160 2 0x401f8408 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_cmd: IOMUXC_GPIO_SD_B1_02_USDHC2_CMD { + pinmux = <0x401f8160 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_clko2: IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 { + pinmux = <0x401f8164 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_enet_1588_event1_in: IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN { + pinmux = <0x401f8164 4 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data2: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA2 { + pinmux = <0x401f8164 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io23: IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 { + pinmux = <0x401f8164 5 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpi2c4_sda: IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA { + pinmux = <0x401f8164 3 0x401f8398 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpuart8_rx: IOMUXC_GPIO_SD_B1_03_LPUART8_RX { + pinmux = <0x401f8164 2 0x401f8404 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_clk: IOMUXC_GPIO_SD_B1_03_USDHC2_CLK { + pinmux = <0x401f8164 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_wait: IOMUXC_GPIO_SD_B1_04_CCM_WAIT { + pinmux = <0x401f8168 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_ref_clk: IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK { + pinmux = <0x401f8168 3 0x401f8304 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_tx_clk: IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK { + pinmux = <0x401f8168 2 0x401f831c 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ewm_out_b: IOMUXC_GPIO_SD_B1_04_EWM_OUT_B { + pinmux = <0x401f8168 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_data1: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA1 { + pinmux = <0x401f8168 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io24: IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 { + pinmux = <0x401f8168 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_data0: IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f8168 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY { + pinmux = <0x401f816c 6 0x401f8300 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_enet_rx_data1: IOMUXC_GPIO_SD_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f816c 2 0x401f8310 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f816c 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f816c 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io25: IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 { + pinmux = <0x401f816c 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_mclk: IOMUXC_GPIO_SD_B1_05_SAI3_MCLK { + pinmux = <0x401f816c 3 0x401f846c 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_data1: IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f816c 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_ccm_stop: IOMUXC_GPIO_SD_B1_06_CCM_STOP { + pinmux = <0x401f8170 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_enet_rx_data0: IOMUXC_GPIO_SD_B1_06_ENET_RX_DATA0 { + pinmux = <0x401f8170 2 0x401f830c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_data3: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA3 { + pinmux = <0x401f8170 1 0x401f8374 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io26: IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 { + pinmux = <0x401f8170 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f8170 4 0x401f83ac 2 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK { + pinmux = <0x401f8170 3 0x401f847c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_cd_b: IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B { + pinmux = <0x401f8170 0 0x401f8498 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_enet_rx_en: IOMUXC_GPIO_SD_B1_07_ENET_RX_EN { + pinmux = <0x401f8174 2 0x401f8314 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f8174 1 0x401f8378 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io27: IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 { + pinmux = <0x401f8174 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f8174 4 0x401f83b0 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai3_tx_sync: IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC { + pinmux = <0x401f8174 3 0x401f8480 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B { + pinmux = <0x401f8174 0 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_enet_rx_er: IOMUXC_GPIO_SD_B1_08_ENET_RX_ER { + pinmux = <0x401f8178 2 0x401f8318 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f8178 1 0x401f8368 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io28: IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 { + pinmux = <0x401f8178 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f8178 4 0x401f83b8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai3_tx_data: IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA { + pinmux = <0x401f8178 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f8178 0 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_enet_tx_en: IOMUXC_GPIO_SD_B1_09_ENET_TX_EN { + pinmux = <0x401f817c 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data2: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA2 { + pinmux = <0x401f817c 1 0x401f8370 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io29: IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 { + pinmux = <0x401f817c 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f817c 4 0x401f83b4 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK { + pinmux = <0x401f817c 3 0x401f8470 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f817c 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_enet_tx_data0: IOMUXC_GPIO_SD_B1_10_ENET_TX_DATA0 { + pinmux = <0x401f8180 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data1: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA1 { + pinmux = <0x401f8180 1 0x401f836c 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io30: IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 { + pinmux = <0x401f8180 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f8180 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_sai3_rx_sync: IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC { + pinmux = <0x401f8180 3 0x401f8478 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f8180 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_enet_tx_data1: IOMUXC_GPIO_SD_B1_11_ENET_TX_DATA1 { + pinmux = <0x401f8184 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B { + pinmux = <0x401f8184 1 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io31: IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 { + pinmux = <0x401f8184 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8184 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_sai3_rx_data: IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA { + pinmux = <0x401f8184 3 0x401f8474 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8184 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_ccm_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ { + pinmux = <0x400a8008 0 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_gpio5_io02: IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 { + pinmux = <0x400a8008 5 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x401f840c 1 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1024dag5b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1024dag5b-pinctrl.dtsi new file mode 100644 index 000000000..58c34a853 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1024dag5b-pinctrl.dtsi @@ -0,0 +1,2131 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1024DAG5B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpt1_compare1: IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 { + pinmux = <0x401f80bc 7 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_jtag_tms: IOMUXC_GPIO_AD_B0_00_JTAG_TMS { + pinmux = <0x401f80bc 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpt1_capture2: IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 { + pinmux = <0x401f80c0 7 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_jtag_tck: IOMUXC_GPIO_AD_B0_01_JTAG_TCK { + pinmux = <0x401f80c0 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpt1_capture1: IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 { + pinmux = <0x401f80c4 7 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_jtag_mod: IOMUXC_GPIO_AD_B0_02_JTAG_MOD { + pinmux = <0x401f80c4 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY { + pinmux = <0x401f80c8 7 0x401f8300 2 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_jtag_tdi: IOMUXC_GPIO_AD_B0_03_JTAG_TDI { + pinmux = <0x401f80c8 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_sai1_mclk: IOMUXC_GPIO_AD_B0_03_SAI1_MCLK { + pinmux = <0x401f80c8 3 0x401f8430 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 6 0x401f848c 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc1_wp: IOMUXC_GPIO_AD_B0_03_USDHC1_WP { + pinmux = <0x401f80c8 4 0x401f8494 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B { + pinmux = <0x401f80c8 1 0x401f8498 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_wdog1_b: IOMUXC_GPIO_AD_B0_03_WDOG1_B { + pinmux = <0x401f80c8 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_mdio: IOMUXC_GPIO_AD_B0_04_ENET_MDIO { + pinmux = <0x401f80cc 4 0x401f8308 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_ewm_out_b: IOMUXC_GPIO_AD_B0_04_EWM_OUT_B { + pinmux = <0x401f80cc 7 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_flexcan1_tx: IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX { + pinmux = <0x401f80cc 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_jtag_tdo: IOMUXC_GPIO_AD_B0_04_JTAG_TDO { + pinmux = <0x401f80cc 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_qtimer2_timer0: IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 { + pinmux = <0x401f80cc 3 0x401f8420 1 0x401f8240>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR { + pinmux = <0x401f80cc 6 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_usdhc1_wp: IOMUXC_GPIO_AD_B0_04_USDHC1_WP { + pinmux = <0x401f80cc 2 0x401f8494 1 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_arm_nmi: IOMUXC_GPIO_AD_B0_05_ARM_NMI { + pinmux = <0x401f80d0 7 0x401f840c 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_mdc: IOMUXC_GPIO_AD_B0_05_ENET_MDC { + pinmux = <0x401f80d0 4 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_flexcan1_rx: IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX { + pinmux = <0x401f80d0 1 0x401f8320 2 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_jtag_trstb: IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB { + pinmux = <0x401f80d0 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_qtimer2_timer1: IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 { + pinmux = <0x401f80d0 3 0x401f8424 1 0x401f8244>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usb_otg1_id: IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID { + pinmux = <0x401f80d0 6 0x401f82fc 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_usdhc1_cd_b: IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B { + pinmux = <0x401f80d0 2 0x401f8490 1 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA3 { + pinmux = <0x401f80d4 4 0x401f8354 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpuart1_tx: IOMUXC_GPIO_AD_B0_06_LPUART1_TX { + pinmux = <0x401f80d4 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_mqs_right: IOMUXC_GPIO_AD_B0_06_MQS_RIGHT { + pinmux = <0x401f80d4 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_pit_trigger0: IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER0 { + pinmux = <0x401f80d4 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_qtimer2_timer2: IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 { + pinmux = <0x401f80d4 3 0x401f8428 1 0x401f8248>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_ref_32k_out: IOMUXC_GPIO_AD_B0_06_REF_32K_OUT { + pinmux = <0x401f80d4 6 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_flexpwm2_pwmb3: IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB3 { + pinmux = <0x401f80d8 4 0x401f8364 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_lpuart1_rx: IOMUXC_GPIO_AD_B0_07_LPUART1_RX { + pinmux = <0x401f80d8 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_mqs_left: IOMUXC_GPIO_AD_B0_07_MQS_LEFT { + pinmux = <0x401f80d8 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_pit_trigger1: IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER1 { + pinmux = <0x401f80d8 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_qtimer2_timer3: IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 { + pinmux = <0x401f80d8 3 0x401f842c 1 0x401f824c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_ref_24m_out: IOMUXC_GPIO_AD_B0_07_REF_24M_OUT { + pinmux = <0x401f80d8 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_acmp1_in4: IOMUXC_GPIO_AD_B0_08_ACMP1_IN4 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_arm_cm7_txev: IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV { + pinmux = <0x401f80dc 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_ref_clk: IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK { + pinmux = <0x401f80dc 4 0x401f8304 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_tx_clk: IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK { + pinmux = <0x401f80dc 0 0x401f831c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_kpp_col0: IOMUXC_GPIO_AD_B0_08_KPP_COL0 { + pinmux = <0x401f80dc 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpi2c3_scl: IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL { + pinmux = <0x401f80dc 1 0x401f838c 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B { + pinmux = <0x401f80dc 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_acmp2_in4: IOMUXC_GPIO_AD_B0_09_ACMP2_IN4 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_arm_cm7_rxev: IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV { + pinmux = <0x401f80e0 6 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data1: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA1 { + pinmux = <0x401f80e0 0 0x401f8310 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_kpp_row0: IOMUXC_GPIO_AD_B0_09_KPP_ROW0 { + pinmux = <0x401f80e0 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpi2c3_sda: IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA { + pinmux = <0x401f80e0 1 0x401f8390 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B { + pinmux = <0x401f80e0 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_acmp3_in4: IOMUXC_GPIO_AD_B0_10_ACMP3_IN4 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_clk: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_CLK { + pinmux = <0x401f80e4 6 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_rx_data0: IOMUXC_GPIO_AD_B0_10_ENET_RX_DATA0 { + pinmux = <0x401f80e4 0 0x401f830c 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f80e4 4 0x401f8350 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_kpp_col1: IOMUXC_GPIO_AD_B0_10_KPP_COL1 { + pinmux = <0x401f80e4 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpspi1_sck: IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK { + pinmux = <0x401f80e4 1 0x401f83a0 1 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_lpuart5_tx: IOMUXC_GPIO_AD_B0_10_LPUART5_TX { + pinmux = <0x401f80e4 2 0x401f83f0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_acmp4_in4: IOMUXC_GPIO_AD_B0_11_ACMP4_IN4 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_arm_trace_swo: IOMUXC_GPIO_AD_B0_11_ARM_TRACE_SWO { + pinmux = <0x401f80e8 6 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_rx_en: IOMUXC_GPIO_AD_B0_11_ENET_RX_EN { + pinmux = <0x401f80e8 0 0x401f8314 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f80e8 4 0x401f8360 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_kpp_row1: IOMUXC_GPIO_AD_B0_11_KPP_ROW1 { + pinmux = <0x401f80e8 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpspi1_pcs0: IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 { + pinmux = <0x401f80e8 1 0x401f839c 1 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_lpuart5_rx: IOMUXC_GPIO_AD_B0_11_LPUART5_RX { + pinmux = <0x401f80e8 2 0x401f83ec 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in0: IOMUXC_GPIO_AD_B0_12_ADC1_IN0 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_trace0: IOMUXC_GPIO_AD_B0_12_ARM_TRACE0 { + pinmux = <0x401f80ec 6 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_rx_er: IOMUXC_GPIO_AD_B0_12_ENET_RX_ER { + pinmux = <0x401f80ec 0 0x401f8318 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm2_pwma1: IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA1 { + pinmux = <0x401f80ec 4 0x401f834c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_kpp_col2: IOMUXC_GPIO_AD_B0_12_KPP_COL2 { + pinmux = <0x401f80ec 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpspi1_sdo: IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO { + pinmux = <0x401f80ec 1 0x401f83a8 1 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart3_cts_b: IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B { + pinmux = <0x401f80ec 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_snvs_vio_5_ctl: IOMUXC_GPIO_AD_B0_12_SNVS_VIO_5_CTL { + pinmux = <0x401f80ec 7 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc2_in0: IOMUXC_GPIO_AD_B0_13_ADC2_IN0 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_tx_en: IOMUXC_GPIO_AD_B0_13_ENET_TX_EN { + pinmux = <0x401f80f0 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm2_pwmb1: IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB1 { + pinmux = <0x401f80f0 4 0x401f835c 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_kpp_row2: IOMUXC_GPIO_AD_B0_13_KPP_ROW2 { + pinmux = <0x401f80f0 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpspi1_sdi: IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI { + pinmux = <0x401f80f0 1 0x401f83a4 1 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart3_rts_b: IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B { + pinmux = <0x401f80f0 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_snvs_vio_5_b: IOMUXC_GPIO_AD_B0_13_SNVS_VIO_5_B { + pinmux = <0x401f80f0 7 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp1_in0: IOMUXC_GPIO_AD_B0_14_ACMP1_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in0: IOMUXC_GPIO_AD_B0_14_ACMP2_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp3_in0: IOMUXC_GPIO_AD_B0_14_ACMP3_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp4_in0: IOMUXC_GPIO_AD_B0_14_ACMP4_IN0 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in1: IOMUXC_GPIO_AD_B0_14_ADC1_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc2_in1: IOMUXC_GPIO_AD_B0_14_ADC2_IN1 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_tx_data0: IOMUXC_GPIO_AD_B0_14_ENET_TX_DATA0 { + pinmux = <0x401f80f4 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexpwm2_pwma0: IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA0 { + pinmux = <0x401f80f4 4 0x401f8348 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_kpp_col3: IOMUXC_GPIO_AD_B0_14_KPP_COL3 { + pinmux = <0x401f80f4 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart3_tx: IOMUXC_GPIO_AD_B0_14_LPUART3_TX { + pinmux = <0x401f80f4 2 0x401f83dc 1 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_wdog1_any: IOMUXC_GPIO_AD_B0_14_WDOG1_ANY { + pinmux = <0x401f80f4 7 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp1_in1: IOMUXC_GPIO_AD_B0_15_ACMP1_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp2_in1: IOMUXC_GPIO_AD_B0_15_ACMP2_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in1: IOMUXC_GPIO_AD_B0_15_ACMP3_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp4_in1: IOMUXC_GPIO_AD_B0_15_ACMP4_IN1 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in2: IOMUXC_GPIO_AD_B0_15_ADC1_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc2_in2: IOMUXC_GPIO_AD_B0_15_ADC2_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_tx_data1: IOMUXC_GPIO_AD_B0_15_ENET_TX_DATA1 { + pinmux = <0x401f80f8 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 1 0x401f8324 2 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexpwm2_pwmb0: IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB0 { + pinmux = <0x401f80f8 4 0x401f8358 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_kpp_row3: IOMUXC_GPIO_AD_B0_15_KPP_ROW3 { + pinmux = <0x401f80f8 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart3_rx: IOMUXC_GPIO_AD_B0_15_LPUART3_RX { + pinmux = <0x401f80f8 2 0x401f83d8 1 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in3: IOMUXC_GPIO_AD_B1_06_ACMP3_IN3 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in6: IOMUXC_GPIO_AD_B1_06_ADC1_IN6 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in6: IOMUXC_GPIO_AD_B1_06_ADC2_IN6 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio1_flexio09: IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8114 4 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexpwm1_pwma0: IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA0 { + pinmux = <0x401f8114 1 0x401f8328 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_kpp_col7: IOMUXC_GPIO_AD_B1_06_KPP_COL7 { + pinmux = <0x401f8114 7 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpspi1_pcs3: IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3 { + pinmux = <0x401f8114 6 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B { + pinmux = <0x401f8114 2 0x401f83cc 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_sai1_rx_bclk: IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK { + pinmux = <0x401f8114 3 0x401f8434 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc1_reset_b: IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B { + pinmux = <0x401f8114 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp4_in3: IOMUXC_GPIO_AD_B1_07_ACMP4_IN3 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in7: IOMUXC_GPIO_AD_B1_07_ADC1_IN7 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in7: IOMUXC_GPIO_AD_B1_07_ADC2_IN7 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio1_flexio08: IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8118 4 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexpwm1_pwmb0: IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB0 { + pinmux = <0x401f8118 1 0x401f8338 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_kpp_row7: IOMUXC_GPIO_AD_B1_07_KPP_ROW7 { + pinmux = <0x401f8118 7 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpspi3_pcs3: IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3 { + pinmux = <0x401f8118 6 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B { + pinmux = <0x401f8118 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_sai1_tx_data1: IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA1 { + pinmux = <0x401f8118 3 0x401f8444 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc1_vselect: IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT { + pinmux = <0x401f8118 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_acmp1_in5: IOMUXC_GPIO_AD_B1_08_ACMP1_IN5 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc1_in8: IOMUXC_GPIO_AD_B1_08_ADC1_IN8 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc2_in8: IOMUXC_GPIO_AD_B1_08_ADC2_IN8 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexio1_flexio07: IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07 { + pinmux = <0x401f811c 4 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexpwm1_pwma1: IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA1 { + pinmux = <0x401f811c 1 0x401f832c 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio1_io24: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpi2c2_scl: IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL { + pinmux = <0x401f811c 0 0x401f8384 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpspi3_pcs2: IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2 { + pinmux = <0x401f811c 6 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_lpuart2_tx: IOMUXC_GPIO_AD_B1_08_LPUART2_TX { + pinmux = <0x401f811c 2 0x401f83d4 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_sai1_tx_data2: IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA2 { + pinmux = <0x401f811c 3 0x401f8440 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_xbar1_xbar_in12: IOMUXC_GPIO_AD_B1_08_XBAR1_XBAR_IN12 { + pinmux = <0x401f811c 7 0x401f84b4 1 0x401f8290>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_xbar1_xbar_inout12: IOMUXC_GPIO_AD_B1_08_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f811c 7 0x401f84b4 1 0x401f8290>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_acmp2_in5: IOMUXC_GPIO_AD_B1_09_ACMP2_IN5 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc1_in9: IOMUXC_GPIO_AD_B1_09_ADC1_IN9 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc2_in9: IOMUXC_GPIO_AD_B1_09_ADC2_IN9 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexio1_flexio06: IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO06 { + pinmux = <0x401f8120 4 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexpwm1_pwmb1: IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB1 { + pinmux = <0x401f8120 1 0x401f833c 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio1_io25: IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpi2c2_sda: IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA { + pinmux = <0x401f8120 0 0x401f8388 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpspi3_pcs1: IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 { + pinmux = <0x401f8120 6 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_lpuart2_rx: IOMUXC_GPIO_AD_B1_09_LPUART2_RX { + pinmux = <0x401f8120 2 0x401f83d0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_sai1_tx_data3: IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA3 { + pinmux = <0x401f8120 3 0x401f843c 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_xbar1_xbar_in13: IOMUXC_GPIO_AD_B1_09_XBAR1_XBAR_IN13 { + pinmux = <0x401f8120 7 0x401f84b8 1 0x401f8294>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_xbar1_xbar_inout13: IOMUXC_GPIO_AD_B1_09_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8120 7 0x401f84b8 1 0x401f8294>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_acmp3_in5: IOMUXC_GPIO_AD_B1_10_ACMP3_IN5 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in10: IOMUXC_GPIO_AD_B1_10_ADC1_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc2_in10: IOMUXC_GPIO_AD_B1_10_ADC2_IN10 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio1_flexio05: IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8124 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexpwm1_pwma2: IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA2 { + pinmux = <0x401f8124 1 0x401f8330 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpt2_capture1: IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 { + pinmux = <0x401f8124 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart4_tx: IOMUXC_GPIO_AD_B1_10_LPUART4_TX { + pinmux = <0x401f8124 2 0x401f83e8 1 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR { + pinmux = <0x401f8124 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B { + pinmux = <0x401f8124 3 0x401f8490 2 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_acmp4_in5: IOMUXC_GPIO_AD_B1_11_ACMP4_IN5 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in11: IOMUXC_GPIO_AD_B1_11_ADC1_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc2_in11: IOMUXC_GPIO_AD_B1_11_ADC2_IN11 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio1_flexio04: IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8128 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexpwm1_pwmb2: IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB2 { + pinmux = <0x401f8128 1 0x401f8340 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpt2_compare1: IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 { + pinmux = <0x401f8128 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart4_rx: IOMUXC_GPIO_AD_B1_11_LPUART4_RX { + pinmux = <0x401f8128 2 0x401f83e4 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usb_otg1_id: IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID { + pinmux = <0x401f8128 0 0x401f82fc 1 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usdhc1_wp: IOMUXC_GPIO_AD_B1_11_USDHC1_WP { + pinmux = <0x401f8128 3 0x401f8494 3 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_in6: IOMUXC_GPIO_AD_B1_12_ACMP1_IN6 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_out: IOMUXC_GPIO_AD_B1_12_ACMP1_OUT { + pinmux = <0x401f812c 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc1_in12: IOMUXC_GPIO_AD_B1_12_ADC1_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc2_in12: IOMUXC_GPIO_AD_B1_12_ADC2_IN12 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio1_flexio03: IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 { + pinmux = <0x401f812c 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexpwm1_pwma3: IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f812c 6 0x401f8334 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_lpspi3_sck: IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK { + pinmux = <0x401f812c 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usb_otg1_oc: IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC { + pinmux = <0x401f812c 0 0x401f848c 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B { + pinmux = <0x401f812c 3 0x401f8498 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_in6: IOMUXC_GPIO_AD_B1_13_ACMP2_IN6 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_out: IOMUXC_GPIO_AD_B1_13_ACMP2_OUT { + pinmux = <0x401f8130 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc1_in13: IOMUXC_GPIO_AD_B1_13_ADC1_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc2_in13: IOMUXC_GPIO_AD_B1_13_ADC2_IN13 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio1_flexio02: IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 { + pinmux = <0x401f8130 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8130 6 0x401f8344 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpi2c1_hreq: IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ { + pinmux = <0x401f8130 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpspi3_pcs0: IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 { + pinmux = <0x401f8130 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_usdhc2_wp: IOMUXC_GPIO_AD_B1_13_USDHC2_WP { + pinmux = <0x401f8130 3 0x401f849c 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_in6: IOMUXC_GPIO_AD_B1_14_ACMP3_IN6 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_out: IOMUXC_GPIO_AD_B1_14_ACMP3_OUT { + pinmux = <0x401f8134 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc1_in14: IOMUXC_GPIO_AD_B1_14_ADC1_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc2_in14: IOMUXC_GPIO_AD_B1_14_ADC2_IN14 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f8134 3 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio1_flexio01: IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8134 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpi2c1_scl: IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL { + pinmux = <0x401f8134 0 0x401f837c 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpspi3_sdo: IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO { + pinmux = <0x401f8134 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_in6: IOMUXC_GPIO_AD_B1_15_ACMP4_IN6 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_out: IOMUXC_GPIO_AD_B1_15_ACMP4_OUT { + pinmux = <0x401f8138 1 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc1_in15: IOMUXC_GPIO_AD_B1_15_ADC1_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc2_in15: IOMUXC_GPIO_AD_B1_15_ADC2_IN15 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f8138 3 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio1_flexio00: IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8138 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpi2c1_sda: IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA { + pinmux = <0x401f8138 0 0x401f8380 1 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpspi3_sdi: IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI { + pinmux = <0x401f8138 2 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexcan1_tx: IOMUXC_GPIO_EMC_00_FLEXCAN1_TX { + pinmux = <0x401f8014 6 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio2_io00: IOMUXC_GPIO_EMC_00_GPIO2_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 4 0x401f83b0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpuart4_cts_b: IOMUXC_GPIO_EMC_00_LPUART4_CTS_B { + pinmux = <0x401f8014 2 0x401f83e0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_pit_trigger2: IOMUXC_GPIO_EMC_00_PIT_TRIGGER2 { + pinmux = <0x401f8014 7 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_qtimer2_timer0: IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0 { + pinmux = <0x401f8014 1 0x401f8420 0 0x401f8188>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_spdif_sr_clk: IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK { + pinmux = <0x401f8014 3 0x0 0 0x401f8188>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexcan1_rx: IOMUXC_GPIO_EMC_01_FLEXCAN1_RX { + pinmux = <0x401f8018 6 0x401f8320 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio2_io01: IOMUXC_GPIO_EMC_01_GPIO2_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 4 0x401f83ac 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpuart4_rts_b: IOMUXC_GPIO_EMC_01_LPUART4_RTS_B { + pinmux = <0x401f8018 2 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_pit_trigger3: IOMUXC_GPIO_EMC_01_PIT_TRIGGER3 { + pinmux = <0x401f8018 7 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_qtimer2_timer1: IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1 { + pinmux = <0x401f8018 1 0x401f8424 0 0x401f818c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_spdif_out: IOMUXC_GPIO_EMC_01_SPDIF_OUT { + pinmux = <0x401f8018 3 0x0 0 0x401f818c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio2_io02: IOMUXC_GPIO_EMC_02_GPIO2_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpi2c1_scl: IOMUXC_GPIO_EMC_02_LPI2C1_SCL { + pinmux = <0x401f801c 6 0x401f837c 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 4 0x401f83b8 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpuart4_tx: IOMUXC_GPIO_EMC_02_LPUART4_TX { + pinmux = <0x401f801c 2 0x401f83e8 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_qtimer2_timer2: IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2 { + pinmux = <0x401f801c 1 0x401f8428 0 0x401f8190>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_spdif_lock: IOMUXC_GPIO_EMC_02_SPDIF_LOCK { + pinmux = <0x401f801c 3 0x0 0 0x401f8190>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio2_io03: IOMUXC_GPIO_EMC_03_GPIO2_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpi2c1_sda: IOMUXC_GPIO_EMC_03_LPI2C1_SDA { + pinmux = <0x401f8020 6 0x401f8380 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 4 0x401f83b4 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpuart4_rx: IOMUXC_GPIO_EMC_03_LPUART4_RX { + pinmux = <0x401f8020 2 0x401f83e4 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_qtimer2_timer3: IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3 { + pinmux = <0x401f8020 1 0x401f842c 0 0x401f8194>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_spdif_ext_clk: IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK { + pinmux = <0x401f8020 3 0x0 0 0x401f8194>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio16: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 { + pinmux = <0x401f8024 4 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio2_io04: IOMUXC_GPIO_EMC_04_GPIO2_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_bclk: IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK { + pinmux = <0x401f8024 3 0x401f8464 1 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_spdif_out: IOMUXC_GPIO_EMC_04_SPDIF_OUT { + pinmux = <0x401f8024 2 0x0 0 0x401f8198>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f8024 1 0x0 0 0x401f8198>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio17: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 { + pinmux = <0x401f8028 4 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio2_io05: IOMUXC_GPIO_EMC_05_GPIO2_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 3 0x401f8468 1 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_spdif_in: IOMUXC_GPIO_EMC_05_SPDIF_IN { + pinmux = <0x401f8028 2 0x401f8488 0 0x401f819c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8028 1 0x0 0 0x401f819c>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio18: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 { + pinmux = <0x401f802c 4 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio2_io06: IOMUXC_GPIO_EMC_06_GPIO2_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_lpuart3_tx: IOMUXC_GPIO_EMC_06_LPUART3_TX { + pinmux = <0x401f802c 2 0x401f83dc 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_data: IOMUXC_GPIO_EMC_06_SAI2_TX_DATA { + pinmux = <0x401f802c 3 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f81a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f802c 1 0x0 0 0x401f81a0>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio19: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 { + pinmux = <0x401f8030 4 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio2_io07: IOMUXC_GPIO_EMC_07_GPIO2_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_lpuart3_rx: IOMUXC_GPIO_EMC_07_LPUART3_RX { + pinmux = <0x401f8030 2 0x401f83d8 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_rx_sync: IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC { + pinmux = <0x401f8030 3 0x401f8460 1 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f81a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8030 1 0x0 0 0x401f81a4>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexcan2_tx: IOMUXC_GPIO_EMC_08_FLEXCAN2_TX { + pinmux = <0x401f8034 2 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio20: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 { + pinmux = <0x401f8034 4 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio2_io08: IOMUXC_GPIO_EMC_08_GPIO2_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 3 0x401f845c 1 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f81a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f8034 1 0x0 0 0x401f81a8>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_rx: IOMUXC_GPIO_EMC_09_FLEXCAN2_RX { + pinmux = <0x401f8038 2 0x401f8324 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio21: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 { + pinmux = <0x401f8038 4 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio2_io09: IOMUXC_GPIO_EMC_09_GPIO2_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_bclk: IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK { + pinmux = <0x401f8038 3 0x401f8458 1 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_we: IOMUXC_GPIO_EMC_09_SEMC_WE { + pinmux = <0x401f8038 0 0x0 0 0x401f81ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_in09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_IN09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_09_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8038 1 0x0 0 0x401f81ac>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwmx0: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX0 { + pinmux = <0x401f803c 6 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio2_io10: IOMUXC_GPIO_EMC_10_GPIO2_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_lpi2c4_sda: IOMUXC_GPIO_EMC_10_LPI2C4_SDA { + pinmux = <0x401f803c 2 0x401f8398 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_lpspi2_sck: IOMUXC_GPIO_EMC_10_LPSPI2_SCK { + pinmux = <0x401f803c 4 0x401f83b0 1 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai1_tx_sync: IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC { + pinmux = <0x401f803c 3 0x401f8450 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_cas: IOMUXC_GPIO_EMC_10_SEMC_CAS { + pinmux = <0x401f803c 0 0x0 0 0x401f81b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_xbar1_xbar_in10: IOMUXC_GPIO_EMC_10_XBAR1_XBAR_IN10 { + pinmux = <0x401f803c 1 0x401f84b0 0 0x401f81b0>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_10_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f803c 1 0x401f84b0 0 0x401f81b0>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmx1: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX1 { + pinmux = <0x401f8040 6 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio2_io11: IOMUXC_GPIO_EMC_11_GPIO2_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_scl: IOMUXC_GPIO_EMC_11_LPI2C4_SCL { + pinmux = <0x401f8040 2 0x401f8394 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpspi2_pcs0: IOMUXC_GPIO_EMC_11_LPSPI2_PCS0 { + pinmux = <0x401f8040 4 0x401f83ac 1 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_sai1_tx_bclk: IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK { + pinmux = <0x401f8040 3 0x401f844c 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_ras: IOMUXC_GPIO_EMC_11_SEMC_RAS { + pinmux = <0x401f8040 0 0x0 0 0x401f81b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_xbar1_xbar_in11: IOMUXC_GPIO_EMC_11_XBAR1_XBAR_IN11 { + pinmux = <0x401f8040 1 0x0 0 0x401f81b4>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_11_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8040 1 0x0 0 0x401f81b4>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm2_pwmx2: IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX2 { + pinmux = <0x401f8044 6 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio2_io12: IOMUXC_GPIO_EMC_12_GPIO2_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpspi2_sdo: IOMUXC_GPIO_EMC_12_LPSPI2_SDO { + pinmux = <0x401f8044 4 0x401f83b8 1 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpuart6_tx: IOMUXC_GPIO_EMC_12_LPUART6_TX { + pinmux = <0x401f8044 2 0x401f83f8 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_sai1_tx_data0: IOMUXC_GPIO_EMC_12_SAI1_TX_DATA0 { + pinmux = <0x401f8044 3 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_cs0: IOMUXC_GPIO_EMC_12_SEMC_CS0 { + pinmux = <0x401f8044 0 0x0 0 0x401f81b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in12: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN12 { + pinmux = <0x401f8044 1 0x401f84b4 0 0x401f81b8>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8044 1 0x401f84b4 0 0x401f81b8>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_ccm_pmic_rdy: IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY { + pinmux = <0x401f8048 7 0x401f8300 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm2_pwmx3: IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX3 { + pinmux = <0x401f8048 6 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio2_io13: IOMUXC_GPIO_EMC_13_GPIO2_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpspi2_sdi: IOMUXC_GPIO_EMC_13_LPSPI2_SDI { + pinmux = <0x401f8048 4 0x401f83b4 1 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart6_rx: IOMUXC_GPIO_EMC_13_LPUART6_RX { + pinmux = <0x401f8048 2 0x401f83f4 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_sai1_rx_data0: IOMUXC_GPIO_EMC_13_SAI1_RX_DATA0 { + pinmux = <0x401f8048 3 0x401f8438 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_ba0: IOMUXC_GPIO_EMC_13_SEMC_BA0 { + pinmux = <0x401f8048 0 0x0 0 0x401f81bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in13: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN13 { + pinmux = <0x401f8048 1 0x401f84b8 0 0x401f81bc>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8048 1 0x401f84b8 0 0x401f81bc>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_flexcan1_tx: IOMUXC_GPIO_EMC_14_FLEXCAN1_TX { + pinmux = <0x401f804c 6 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio2_io14: IOMUXC_GPIO_EMC_14_GPIO2_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart6_cts_b: IOMUXC_GPIO_EMC_14_LPUART6_CTS_B { + pinmux = <0x401f804c 2 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_sai1_rx_bclk: IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK { + pinmux = <0x401f804c 3 0x401f8434 1 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_ba1: IOMUXC_GPIO_EMC_14_SEMC_BA1 { + pinmux = <0x401f804c 0 0x0 0 0x401f81c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in14: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN14 { + pinmux = <0x401f804c 1 0x401f84a0 1 0x401f81c0>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f804c 1 0x401f84a0 1 0x401f81c0>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_flexcan1_rx: IOMUXC_GPIO_EMC_15_FLEXCAN1_RX { + pinmux = <0x401f8050 6 0x401f8320 3 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio2_io15: IOMUXC_GPIO_EMC_15_GPIO2_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart6_rts_b: IOMUXC_GPIO_EMC_15_LPUART6_RTS_B { + pinmux = <0x401f8050 2 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_sai1_rx_sync: IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC { + pinmux = <0x401f8050 3 0x401f8448 1 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr10: IOMUXC_GPIO_EMC_15_SEMC_ADDR10 { + pinmux = <0x401f8050 0 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_wdog1_b: IOMUXC_GPIO_EMC_15_WDOG1_B { + pinmux = <0x401f8050 4 0x0 0 0x401f81c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in15: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN15 { + pinmux = <0x401f8050 1 0x401f84a4 1 0x401f81c4>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8050 1 0x401f84a4 1 0x401f81c4>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio2_io16: IOMUXC_GPIO_EMC_16_GPIO2_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_mqs_right: IOMUXC_GPIO_EMC_16_MQS_RIGHT { + pinmux = <0x401f8054 2 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_sai2_mclk: IOMUXC_GPIO_EMC_16_SAI2_MCLK { + pinmux = <0x401f8054 3 0x401f8454 1 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr00: IOMUXC_GPIO_EMC_16_SEMC_ADDR00 { + pinmux = <0x401f8054 0 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_src_boot_mode0: IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE0 { + pinmux = <0x401f8054 6 0x0 0 0x401f81c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio2_io17: IOMUXC_GPIO_EMC_17_GPIO2_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_mqs_left: IOMUXC_GPIO_EMC_17_MQS_LEFT { + pinmux = <0x401f8058 2 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_sai3_mclk: IOMUXC_GPIO_EMC_17_SAI3_MCLK { + pinmux = <0x401f8058 3 0x401f846c 1 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr01: IOMUXC_GPIO_EMC_17_SEMC_ADDR01 { + pinmux = <0x401f8058 0 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_src_boot_mode1: IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE1 { + pinmux = <0x401f8058 6 0x0 0 0x401f81cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexio1_flexio22: IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 { + pinmux = <0x401f805c 4 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio2_io18: IOMUXC_GPIO_EMC_18_GPIO2_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpi2c2_sda: IOMUXC_GPIO_EMC_18_LPI2C2_SDA { + pinmux = <0x401f805c 2 0x401f8388 1 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_sai1_rx_sync: IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC { + pinmux = <0x401f805c 3 0x401f8448 2 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr02: IOMUXC_GPIO_EMC_18_SEMC_ADDR02 { + pinmux = <0x401f805c 0 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_src_bt_cfg0: IOMUXC_GPIO_EMC_18_SRC_BT_CFG0 { + pinmux = <0x401f805c 6 0x0 0 0x401f81d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_IN16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f805c 1 0x401f84a8 1 0x401f81d0>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexio1_flexio23: IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 { + pinmux = <0x401f8060 4 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio2_io19: IOMUXC_GPIO_EMC_19_GPIO2_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpi2c2_scl: IOMUXC_GPIO_EMC_19_LPI2C2_SCL { + pinmux = <0x401f8060 2 0x401f8384 1 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_sai1_rx_bclk: IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK { + pinmux = <0x401f8060 3 0x401f8434 2 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr03: IOMUXC_GPIO_EMC_19_SEMC_ADDR03 { + pinmux = <0x401f8060 0 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_src_bt_cfg1: IOMUXC_GPIO_EMC_19_SRC_BT_CFG1 { + pinmux = <0x401f8060 6 0x0 0 0x401f81d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_in17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_IN17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_19_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8060 1 0x401f84ac 1 0x401f81d4>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexio1_flexio24: IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 { + pinmux = <0x401f8064 4 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm1_pwma3: IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA3 { + pinmux = <0x401f8064 1 0x401f8334 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio2_io20: IOMUXC_GPIO_EMC_20_GPIO2_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart2_cts_b: IOMUXC_GPIO_EMC_20_LPUART2_CTS_B { + pinmux = <0x401f8064 2 0x401f83cc 1 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_sai1_mclk: IOMUXC_GPIO_EMC_20_SAI1_MCLK { + pinmux = <0x401f8064 3 0x401f8430 3 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr04: IOMUXC_GPIO_EMC_20_SEMC_ADDR04 { + pinmux = <0x401f8064 0 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_src_bt_cfg2: IOMUXC_GPIO_EMC_20_SRC_BT_CFG2 { + pinmux = <0x401f8064 6 0x0 0 0x401f81d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexio1_flexio25: IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 { + pinmux = <0x401f8068 4 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB3 { + pinmux = <0x401f8068 1 0x401f8344 1 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio2_io21: IOMUXC_GPIO_EMC_21_GPIO2_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpuart2_rts_b: IOMUXC_GPIO_EMC_21_LPUART2_RTS_B { + pinmux = <0x401f8068 2 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_sai1_rx_data0: IOMUXC_GPIO_EMC_21_SAI1_RX_DATA0 { + pinmux = <0x401f8068 3 0x401f8438 2 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_addr05: IOMUXC_GPIO_EMC_21_SEMC_ADDR05 { + pinmux = <0x401f8068 0 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_src_bt_cfg3: IOMUXC_GPIO_EMC_21_SRC_BT_CFG3 { + pinmux = <0x401f8068 6 0x0 0 0x401f81dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexio1_flexio26: IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 { + pinmux = <0x401f806c 4 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm1_pwma2: IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA2 { + pinmux = <0x401f806c 1 0x401f8330 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio2_io22: IOMUXC_GPIO_EMC_22_GPIO2_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpuart2_tx: IOMUXC_GPIO_EMC_22_LPUART2_TX { + pinmux = <0x401f806c 2 0x401f83d4 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_sai1_tx_data3: IOMUXC_GPIO_EMC_22_SAI1_TX_DATA3 { + pinmux = <0x401f806c 3 0x401f843c 1 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_addr06: IOMUXC_GPIO_EMC_22_SEMC_ADDR06 { + pinmux = <0x401f806c 0 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_src_bt_cfg4: IOMUXC_GPIO_EMC_22_SRC_BT_CFG4 { + pinmux = <0x401f806c 6 0x0 0 0x401f81e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexio1_flexio27: IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 { + pinmux = <0x401f8070 4 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB2 { + pinmux = <0x401f8070 1 0x401f8340 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio2_io23: IOMUXC_GPIO_EMC_23_GPIO2_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart2_rx: IOMUXC_GPIO_EMC_23_LPUART2_RX { + pinmux = <0x401f8070 2 0x401f83d0 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_sai1_tx_data2: IOMUXC_GPIO_EMC_23_SAI1_TX_DATA2 { + pinmux = <0x401f8070 3 0x401f8440 1 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr07: IOMUXC_GPIO_EMC_23_SEMC_ADDR07 { + pinmux = <0x401f8070 0 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_src_bt_cfg5: IOMUXC_GPIO_EMC_23_SRC_BT_CFG5 { + pinmux = <0x401f8070 6 0x0 0 0x401f81e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexio1_flexio28: IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 { + pinmux = <0x401f8074 4 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwma1: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA1 { + pinmux = <0x401f8074 1 0x401f832c 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio2_io24: IOMUXC_GPIO_EMC_24_GPIO2_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart8_cts_b: IOMUXC_GPIO_EMC_24_LPUART8_CTS_B { + pinmux = <0x401f8074 2 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_sai1_tx_data1: IOMUXC_GPIO_EMC_24_SAI1_TX_DATA1 { + pinmux = <0x401f8074 3 0x401f8444 1 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_addr08: IOMUXC_GPIO_EMC_24_SEMC_ADDR08 { + pinmux = <0x401f8074 0 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_src_bt_cfg6: IOMUXC_GPIO_EMC_24_SRC_BT_CFG6 { + pinmux = <0x401f8074 6 0x0 0 0x401f81e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexio1_flexio29: IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 { + pinmux = <0x401f8078 4 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB1 { + pinmux = <0x401f8078 1 0x401f833c 1 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio2_io25: IOMUXC_GPIO_EMC_25_GPIO2_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart8_rts_b: IOMUXC_GPIO_EMC_25_LPUART8_RTS_B { + pinmux = <0x401f8078 2 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_sai1_tx_data0: IOMUXC_GPIO_EMC_25_SAI1_TX_DATA0 { + pinmux = <0x401f8078 3 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_addr09: IOMUXC_GPIO_EMC_25_SEMC_ADDR09 { + pinmux = <0x401f8078 0 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_src_bt_cfg7: IOMUXC_GPIO_EMC_25_SRC_BT_CFG7 { + pinmux = <0x401f8078 6 0x0 0 0x401f81ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio30: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 { + pinmux = <0x401f807c 4 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwma0: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA0 { + pinmux = <0x401f807c 1 0x401f8328 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio2_io26: IOMUXC_GPIO_EMC_26_GPIO2_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart8_tx: IOMUXC_GPIO_EMC_26_LPUART8_TX { + pinmux = <0x401f807c 2 0x401f8408 1 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_sai1_tx_bclk: IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK { + pinmux = <0x401f807c 3 0x401f844c 2 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_addr11: IOMUXC_GPIO_EMC_26_SEMC_ADDR11 { + pinmux = <0x401f807c 0 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_src_bt_cfg8: IOMUXC_GPIO_EMC_26_SRC_BT_CFG8 { + pinmux = <0x401f807c 6 0x0 0 0x401f81f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio31: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 { + pinmux = <0x401f8080 4 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB0 { + pinmux = <0x401f8080 1 0x401f8338 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio2_io27: IOMUXC_GPIO_EMC_27_GPIO2_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart8_rx: IOMUXC_GPIO_EMC_27_LPUART8_RX { + pinmux = <0x401f8080 2 0x401f8404 1 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_sai1_tx_sync: IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC { + pinmux = <0x401f8080 3 0x401f8450 2 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_addr12: IOMUXC_GPIO_EMC_27_SEMC_ADDR12 { + pinmux = <0x401f8080 0 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_src_bt_cfg9: IOMUXC_GPIO_EMC_27_SRC_BT_CFG9 { + pinmux = <0x401f8080 6 0x0 0 0x401f81f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_ewm_out_b: IOMUXC_GPIO_EMC_28_EWM_OUT_B { + pinmux = <0x401f8084 4 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmx0: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX0 { + pinmux = <0x401f8084 7 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm2_pwma3: IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA3 { + pinmux = <0x401f8084 1 0x401f8354 1 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio2_io28: IOMUXC_GPIO_EMC_28_GPIO2_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpt2_capture2: IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2 { + pinmux = <0x401f8084 6 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_sai3_mclk: IOMUXC_GPIO_EMC_28_SAI3_MCLK { + pinmux = <0x401f8084 3 0x401f846c 2 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_dqs: IOMUXC_GPIO_EMC_28_SEMC_DQS { + pinmux = <0x401f8084 0 0x0 0 0x401f81f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_xbar1_xbar_in18: IOMUXC_GPIO_EMC_28_XBAR1_XBAR_IN18 { + pinmux = <0x401f8084 2 0x401f84bc 0 0x401f81f8>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_28_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f8084 2 0x401f84bc 0 0x401f81f8>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm1_pwmx1: IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX1 { + pinmux = <0x401f8088 7 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB3 { + pinmux = <0x401f8088 1 0x401f8364 1 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio2_io29: IOMUXC_GPIO_EMC_29_GPIO2_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpt2_compare2: IOMUXC_GPIO_EMC_29_GPT2_COMPARE2 { + pinmux = <0x401f8088 6 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_sai3_rx_bclk: IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK { + pinmux = <0x401f8088 3 0x401f8470 1 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cke: IOMUXC_GPIO_EMC_29_SEMC_CKE { + pinmux = <0x401f8088 0 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_wdog2_rst_b_deb: IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB { + pinmux = <0x401f8088 4 0x0 0 0x401f81fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_xbar1_xbar_in19: IOMUXC_GPIO_EMC_29_XBAR1_XBAR_IN19 { + pinmux = <0x401f8088 2 0x401f84c0 0 0x401f81fc>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_29_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f8088 2 0x401f84c0 0 0x401f81fc>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm1_pwmx2: IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX2 { + pinmux = <0x401f808c 7 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm2_pwma2: IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA2 { + pinmux = <0x401f808c 1 0x401f8350 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio2_io30: IOMUXC_GPIO_EMC_30_GPIO2_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpt2_compare3: IOMUXC_GPIO_EMC_30_GPT2_COMPARE3 { + pinmux = <0x401f808c 6 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart4_cts_b: IOMUXC_GPIO_EMC_30_LPUART4_CTS_B { + pinmux = <0x401f808c 2 0x401f83e0 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_sai3_rx_sync: IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC { + pinmux = <0x401f808c 3 0x401f8478 1 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_clk: IOMUXC_GPIO_EMC_30_SEMC_CLK { + pinmux = <0x401f808c 0 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_wdog1_rst_b_deb: IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB { + pinmux = <0x401f808c 4 0x0 0 0x401f8200>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm1_pwmx3: IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX3 { + pinmux = <0x401f8090 7 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB2 { + pinmux = <0x401f8090 1 0x401f8360 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio2_io31: IOMUXC_GPIO_EMC_31_GPIO2_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpt2_clk: IOMUXC_GPIO_EMC_31_GPT2_CLK { + pinmux = <0x401f8090 6 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart4_rts_b: IOMUXC_GPIO_EMC_31_LPUART4_RTS_B { + pinmux = <0x401f8090 2 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_sai3_rx_data: IOMUXC_GPIO_EMC_31_SAI3_RX_DATA { + pinmux = <0x401f8090 3 0x401f8474 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_dm1: IOMUXC_GPIO_EMC_31_SEMC_DM1 { + pinmux = <0x401f8090 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_wdog2_b: IOMUXC_GPIO_EMC_31_WDOG2_B { + pinmux = <0x401f8090 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io00: IOMUXC_GPIO_EMC_32_GPIO3_IO00 { + pinmux = <0x401f8094 5 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpspi4_sck: IOMUXC_GPIO_EMC_32_LPSPI4_SCK { + pinmux = <0x401f8094 4 0x401f83c0 1 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart4_tx: IOMUXC_GPIO_EMC_32_LPUART4_TX { + pinmux = <0x401f8094 2 0x401f83e8 2 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_qtimer1_timer0: IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 { + pinmux = <0x401f8094 1 0x401f8410 1 0x401f8208>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ref_24m_out: IOMUXC_GPIO_EMC_32_REF_24M_OUT { + pinmux = <0x401f8094 7 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_sai3_tx_data: IOMUXC_GPIO_EMC_32_SAI3_TX_DATA { + pinmux = <0x401f8094 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data08: IOMUXC_GPIO_EMC_32_SEMC_DATA08 { + pinmux = <0x401f8094 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io01: IOMUXC_GPIO_EMC_33_GPIO3_IO01 { + pinmux = <0x401f8098 5 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpspi4_pcs0: IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 { + pinmux = <0x401f8098 4 0x401f83bc 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_lpuart4_rx: IOMUXC_GPIO_EMC_33_LPUART4_RX { + pinmux = <0x401f8098 2 0x401f83e4 2 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_qtimer1_timer1: IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 { + pinmux = <0x401f8098 1 0x401f8414 1 0x401f820c>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_tx_bclk: IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK { + pinmux = <0x401f8098 3 0x401f847c 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data09: IOMUXC_GPIO_EMC_33_SEMC_DATA09 { + pinmux = <0x401f8098 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_enet_crs: IOMUXC_GPIO_EMC_34_ENET_CRS { + pinmux = <0x401f809c 6 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io02: IOMUXC_GPIO_EMC_34_GPIO3_IO02 { + pinmux = <0x401f809c 5 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpspi4_sdo: IOMUXC_GPIO_EMC_34_LPSPI4_SDO { + pinmux = <0x401f809c 4 0x401f83c8 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_lpuart7_tx: IOMUXC_GPIO_EMC_34_LPUART7_TX { + pinmux = <0x401f809c 2 0x401f8400 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_qtimer1_timer2: IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 { + pinmux = <0x401f809c 1 0x401f8418 1 0x401f8210>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_tx_sync: IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC { + pinmux = <0x401f809c 3 0x401f8480 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data10: IOMUXC_GPIO_EMC_34_SEMC_DATA10 { + pinmux = <0x401f809c 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_enet_col: IOMUXC_GPIO_EMC_35_ENET_COL { + pinmux = <0x401f80a0 6 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io03: IOMUXC_GPIO_EMC_35_GPIO3_IO03 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpspi4_sdi: IOMUXC_GPIO_EMC_35_LPSPI4_SDI { + pinmux = <0x401f80a0 4 0x401f83c4 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_lpuart7_rx: IOMUXC_GPIO_EMC_35_LPUART7_RX { + pinmux = <0x401f80a0 2 0x401f83fc 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_qtimer1_timer3: IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 { + pinmux = <0x401f80a0 1 0x401f841c 1 0x401f8214>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data11: IOMUXC_GPIO_EMC_35_SEMC_DATA11 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc2_wp: IOMUXC_GPIO_EMC_35_USDHC2_WP { + pinmux = <0x401f80a0 3 0x401f849c 1 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_ccm_pmic_rdy: IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY { + pinmux = <0x401f80a4 3 0x401f8300 3 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_enet_rx_clk: IOMUXC_GPIO_EMC_36_ENET_RX_CLK { + pinmux = <0x401f80a4 6 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexpwm2_pwma1: IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA1 { + pinmux = <0x401f80a4 1 0x401f834c 1 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io04: IOMUXC_GPIO_EMC_36_GPIO3_IO04 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_lpspi4_pcs1: IOMUXC_GPIO_EMC_36_LPSPI4_PCS1 { + pinmux = <0x401f80a4 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_lpuart5_cts_b: IOMUXC_GPIO_EMC_36_LPUART5_CTS_B { + pinmux = <0x401f80a4 2 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data12: IOMUXC_GPIO_EMC_36_SEMC_DATA12 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 7 0x401f8494 4 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_enet_rx_data3: IOMUXC_GPIO_EMC_37_ENET_RX_DATA3 { + pinmux = <0x401f80a8 6 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB1 { + pinmux = <0x401f80a8 1 0x401f835c 1 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io05: IOMUXC_GPIO_EMC_37_GPIO3_IO05 { + pinmux = <0x401f80a8 5 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_lpspi4_pcs2: IOMUXC_GPIO_EMC_37_LPSPI4_PCS2 { + pinmux = <0x401f80a8 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_lpuart5_rts_b: IOMUXC_GPIO_EMC_37_LPUART5_RTS_B { + pinmux = <0x401f80a8 2 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_mqs_right: IOMUXC_GPIO_EMC_37_MQS_RIGHT { + pinmux = <0x401f80a8 3 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data13: IOMUXC_GPIO_EMC_37_SEMC_DATA13 { + pinmux = <0x401f80a8 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc1_vselect: IOMUXC_GPIO_EMC_37_USDHC1_VSELECT { + pinmux = <0x401f80a8 7 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_enet_rx_data2: IOMUXC_GPIO_EMC_38_ENET_RX_DATA2 { + pinmux = <0x401f80ac 6 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm2_pwma0: IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA0 { + pinmux = <0x401f80ac 1 0x401f8348 1 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io06: IOMUXC_GPIO_EMC_38_GPIO3_IO06 { + pinmux = <0x401f80ac 5 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpspi4_pcs3: IOMUXC_GPIO_EMC_38_LPSPI4_PCS3 { + pinmux = <0x401f80ac 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart5_tx: IOMUXC_GPIO_EMC_38_LPUART5_TX { + pinmux = <0x401f80ac 2 0x401f83f0 1 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_mqs_left: IOMUXC_GPIO_EMC_38_MQS_LEFT { + pinmux = <0x401f80ac 3 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_data14: IOMUXC_GPIO_EMC_38_SEMC_DATA14 { + pinmux = <0x401f80ac 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc1_cd_b: IOMUXC_GPIO_EMC_38_USDHC1_CD_B { + pinmux = <0x401f80ac 7 0x401f8490 3 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_enet_tx_er: IOMUXC_GPIO_EMC_39_ENET_TX_ER { + pinmux = <0x401f80b0 6 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB0 { + pinmux = <0x401f80b0 1 0x401f8358 1 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io07: IOMUXC_GPIO_EMC_39_GPIO3_IO07 { + pinmux = <0x401f80b0 5 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpt1_clk: IOMUXC_GPIO_EMC_39_GPT1_CLK { + pinmux = <0x401f80b0 7 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart5_rx: IOMUXC_GPIO_EMC_39_LPUART5_RX { + pinmux = <0x401f80b0 2 0x401f83ec 1 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_data15: IOMUXC_GPIO_EMC_39_SEMC_DATA15 { + pinmux = <0x401f80b0 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usb_otg1_oc: IOMUXC_GPIO_EMC_39_USB_OTG1_OC { + pinmux = <0x401f80b0 3 0x401f848c 2 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdio: IOMUXC_GPIO_EMC_40_ENET_MDIO { + pinmux = <0x401f80b4 4 0x401f8308 2 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_tx_data3: IOMUXC_GPIO_EMC_40_ENET_TX_DATA3 { + pinmux = <0x401f80b4 6 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io08: IOMUXC_GPIO_EMC_40_GPIO3_IO08 { + pinmux = <0x401f80b4 5 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt1_compare3: IOMUXC_GPIO_EMC_40_GPT1_COMPARE3 { + pinmux = <0x401f80b4 7 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_csx0: IOMUXC_GPIO_EMC_40_SEMC_CSX0 { + pinmux = <0x401f80b4 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_spdif_out: IOMUXC_GPIO_EMC_40_SPDIF_OUT { + pinmux = <0x401f80b4 2 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usb_otg1_id: IOMUXC_GPIO_EMC_40_USB_OTG1_ID { + pinmux = <0x401f80b4 3 0x401f82fc 2 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_xbar1_xbar_in18: IOMUXC_GPIO_EMC_40_XBAR1_XBAR_IN18 { + pinmux = <0x401f80b4 1 0x401f84bc 1 0x401f8228>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_40_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80b4 1 0x401f84bc 1 0x401f8228>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdc: IOMUXC_GPIO_EMC_41_ENET_MDC { + pinmux = <0x401f80b8 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_tx_data2: IOMUXC_GPIO_EMC_41_ENET_TX_DATA2 { + pinmux = <0x401f80b8 6 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io09: IOMUXC_GPIO_EMC_41_GPIO3_IO09 { + pinmux = <0x401f80b8 5 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt1_compare2: IOMUXC_GPIO_EMC_41_GPT1_COMPARE2 { + pinmux = <0x401f80b8 7 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_rdy: IOMUXC_GPIO_EMC_41_SEMC_RDY { + pinmux = <0x401f80b8 0 0x401f8484 1 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_spdif_in: IOMUXC_GPIO_EMC_41_SPDIF_IN { + pinmux = <0x401f80b8 2 0x401f8488 1 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usb_otg1_pwr: IOMUXC_GPIO_EMC_41_USB_OTG1_PWR { + pinmux = <0x401f80b8 3 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_xbar1_xbar_in19: IOMUXC_GPIO_EMC_41_XBAR1_XBAR_IN19 { + pinmux = <0x401f80b8 1 0x401f84c0 1 0x401f822c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_41_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80b8 1 0x401f84c0 1 0x401f822c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f813c 6 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io13: IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 { + pinmux = <0x401f813c 5 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f813c 4 0x401f838c 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_qtimer1_timer0: IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x401f8410 0 0x401f82b0>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_sai1_mclk: IOMUXC_GPIO_SD_B0_00_SAI1_MCLK { + pinmux = <0x401f813c 2 0x401f8430 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_sai2_mclk: IOMUXC_GPIO_SD_B0_00_SAI2_MCLK { + pinmux = <0x401f813c 3 0x401f8454 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_data2: IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 { + pinmux = <0x401f813c 0 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in14: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f813c 7 0x401f84a0 0 0x401f82b0>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout14: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f813c 7 0x401f84a0 0 0x401f82b0>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f8140 6 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io14: IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 { + pinmux = <0x401f8140 5 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f8140 4 0x401f8390 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_qtimer1_timer1: IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x401f8414 0 0x401f82b4>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_ref_24m_out: IOMUXC_GPIO_SD_B0_01_REF_24M_OUT { + pinmux = <0x401f8140 2 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_sai2_rx_sync: IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC { + pinmux = <0x401f8140 3 0x401f8460 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_data3: IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 { + pinmux = <0x401f8140 0 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in15: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8140 7 0x401f84a4 0 0x401f82b4>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout15: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8140 7 0x401f84a4 0 0x401f82b4>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_enet_mdio: IOMUXC_GPIO_SD_B0_02_ENET_MDIO { + pinmux = <0x401f8144 6 0x401f8308 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io15: IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 { + pinmux = <0x401f8144 5 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sck: IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK { + pinmux = <0x401f8144 4 0x401f83a0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart7_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B { + pinmux = <0x401f8144 2 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_qtimer1_timer2: IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x401f8418 0 0x401f82b8>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_sai2_rx_bclk: IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK { + pinmux = <0x401f8144 3 0x401f8458 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_cmd: IOMUXC_GPIO_SD_B0_02_USDHC1_CMD { + pinmux = <0x401f8144 0 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in16: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8144 7 0x401f84a8 0 0x401f82b8>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout16: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8144 7 0x401f84a8 0 0x401f82b8>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_enet_mdc: IOMUXC_GPIO_SD_B0_03_ENET_MDC { + pinmux = <0x401f8148 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io16: IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 { + pinmux = <0x401f8148 5 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0 { + pinmux = <0x401f8148 4 0x401f839c 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart7_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B { + pinmux = <0x401f8148 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_qtimer1_timer3: IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3 { + pinmux = <0x401f8148 1 0x401f841c 0 0x401f82bc>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_sai2_rx_data: IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA { + pinmux = <0x401f8148 3 0x401f845c 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_clk: IOMUXC_GPIO_SD_B0_03_USDHC1_CLK { + pinmux = <0x401f8148 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexcan2_tx: IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX { + pinmux = <0x401f814c 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f814c 6 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io17: IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 { + pinmux = <0x401f814c 5 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpspi1_sdo: IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO { + pinmux = <0x401f814c 4 0x401f83a8 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart7_tx: IOMUXC_GPIO_SD_B0_04_LPUART7_TX { + pinmux = <0x401f814c 2 0x401f8400 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_sai2_tx_data: IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA { + pinmux = <0x401f814c 3 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data0: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 { + pinmux = <0x401f814c 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexcan2_rx: IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX { + pinmux = <0x401f8150 1 0x401f8324 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f8150 6 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io18: IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 { + pinmux = <0x401f8150 5 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpspi1_sdi: IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI { + pinmux = <0x401f8150 4 0x401f83a4 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart7_rx: IOMUXC_GPIO_SD_B0_05_LPUART7_RX { + pinmux = <0x401f8150 2 0x401f83fc 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_sai2_tx_bclk: IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f8150 3 0x401f8464 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data1: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 { + pinmux = <0x401f8150 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_gpio3_io19: IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 { + pinmux = <0x401f8154 5 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_ref_32k_out: IOMUXC_GPIO_SD_B0_06_REF_32K_OUT { + pinmux = <0x401f8154 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_sai2_tx_sync: IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC { + pinmux = <0x401f8154 3 0x401f8468 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_usdhc1_cd_b: IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B { + pinmux = <0x401f8154 0 0x401f8490 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_usdhc1_reset_b: IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B { + pinmux = <0x401f8154 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_wdog1_b: IOMUXC_GPIO_SD_B0_06_WDOG1_B { + pinmux = <0x401f8154 4 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_xbar1_xbar_in17: IOMUXC_GPIO_SD_B0_06_XBAR1_XBAR_IN17 { + pinmux = <0x401f8154 6 0x401f84ac 0 0x401f82c8>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_06_xbar1_xbar_inout17: IOMUXC_GPIO_SD_B0_06_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8154 6 0x401f84ac 0 0x401f82c8>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexcan1_tx: IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX { + pinmux = <0x401f8158 4 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f8158 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io20: IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 { + pinmux = <0x401f8158 5 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart6_tx: IOMUXC_GPIO_SD_B1_00_LPUART6_TX { + pinmux = <0x401f8158 2 0x401f83f8 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data2: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 { + pinmux = <0x401f8158 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout10: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f8158 3 0x401f84b0 1 0x401f82cc>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexcan1_rx: IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX { + pinmux = <0x401f815c 4 0x401f8320 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B { + pinmux = <0x401f815c 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK { + pinmux = <0x401f815c 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io21: IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 { + pinmux = <0x401f815c 5 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart6_rx: IOMUXC_GPIO_SD_B1_01_LPUART6_RX { + pinmux = <0x401f815c 2 0x401f83f4 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data3: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 { + pinmux = <0x401f815c 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_clko1: IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 { + pinmux = <0x401f8160 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_enet_1588_event1_out: IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT { + pinmux = <0x401f8160 4 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data0: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA0 { + pinmux = <0x401f8160 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io22: IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 { + pinmux = <0x401f8160 5 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpi2c4_scl: IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL { + pinmux = <0x401f8160 3 0x401f8394 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_lpuart8_tx: IOMUXC_GPIO_SD_B1_02_LPUART8_TX { + pinmux = <0x401f8160 2 0x401f8408 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_cmd: IOMUXC_GPIO_SD_B1_02_USDHC2_CMD { + pinmux = <0x401f8160 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_clko2: IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 { + pinmux = <0x401f8164 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_enet_1588_event1_in: IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN { + pinmux = <0x401f8164 4 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data2: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA2 { + pinmux = <0x401f8164 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io23: IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 { + pinmux = <0x401f8164 5 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpi2c4_sda: IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA { + pinmux = <0x401f8164 3 0x401f8398 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_lpuart8_rx: IOMUXC_GPIO_SD_B1_03_LPUART8_RX { + pinmux = <0x401f8164 2 0x401f8404 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_clk: IOMUXC_GPIO_SD_B1_03_USDHC2_CLK { + pinmux = <0x401f8164 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_wait: IOMUXC_GPIO_SD_B1_04_CCM_WAIT { + pinmux = <0x401f8168 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_ref_clk: IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK { + pinmux = <0x401f8168 3 0x401f8304 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_enet_tx_clk: IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK { + pinmux = <0x401f8168 2 0x401f831c 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ewm_out_b: IOMUXC_GPIO_SD_B1_04_EWM_OUT_B { + pinmux = <0x401f8168 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_data1: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA1 { + pinmux = <0x401f8168 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io24: IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 { + pinmux = <0x401f8168 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_data0: IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f8168 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY { + pinmux = <0x401f816c 6 0x401f8300 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_enet_rx_data1: IOMUXC_GPIO_SD_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f816c 2 0x401f8310 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f816c 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f816c 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io25: IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 { + pinmux = <0x401f816c 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_mclk: IOMUXC_GPIO_SD_B1_05_SAI3_MCLK { + pinmux = <0x401f816c 3 0x401f846c 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_data1: IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f816c 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_ccm_stop: IOMUXC_GPIO_SD_B1_06_CCM_STOP { + pinmux = <0x401f8170 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_enet_rx_data0: IOMUXC_GPIO_SD_B1_06_ENET_RX_DATA0 { + pinmux = <0x401f8170 2 0x401f830c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_data3: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA3 { + pinmux = <0x401f8170 1 0x401f8374 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io26: IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 { + pinmux = <0x401f8170 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f8170 4 0x401f83ac 2 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK { + pinmux = <0x401f8170 3 0x401f847c 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_cd_b: IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B { + pinmux = <0x401f8170 0 0x401f8498 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_enet_rx_en: IOMUXC_GPIO_SD_B1_07_ENET_RX_EN { + pinmux = <0x401f8174 2 0x401f8314 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f8174 1 0x401f8378 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io27: IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 { + pinmux = <0x401f8174 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f8174 4 0x401f83b0 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai3_tx_sync: IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC { + pinmux = <0x401f8174 3 0x401f8480 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B { + pinmux = <0x401f8174 0 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_enet_rx_er: IOMUXC_GPIO_SD_B1_08_ENET_RX_ER { + pinmux = <0x401f8178 2 0x401f8318 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f8178 1 0x401f8368 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io28: IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 { + pinmux = <0x401f8178 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f8178 4 0x401f83b8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai3_tx_data: IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA { + pinmux = <0x401f8178 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f8178 0 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_enet_tx_en: IOMUXC_GPIO_SD_B1_09_ENET_TX_EN { + pinmux = <0x401f817c 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data2: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA2 { + pinmux = <0x401f817c 1 0x401f8370 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io29: IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 { + pinmux = <0x401f817c 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f817c 4 0x401f83b4 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK { + pinmux = <0x401f817c 3 0x401f8470 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f817c 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_enet_tx_data0: IOMUXC_GPIO_SD_B1_10_ENET_TX_DATA0 { + pinmux = <0x401f8180 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data1: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA1 { + pinmux = <0x401f8180 1 0x401f836c 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io30: IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 { + pinmux = <0x401f8180 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f8180 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_sai3_rx_sync: IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC { + pinmux = <0x401f8180 3 0x401f8478 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f8180 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_enet_tx_data1: IOMUXC_GPIO_SD_B1_11_ENET_TX_DATA1 { + pinmux = <0x401f8184 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B { + pinmux = <0x401f8184 1 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io31: IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 { + pinmux = <0x401f8184 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8184 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_sai3_rx_data: IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA { + pinmux = <0x401f8184 3 0x401f8474 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8184 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_ccm_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ { + pinmux = <0x400a8008 0 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_gpio5_io02: IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 { + pinmux = <0x400a8008 5 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x401f840c 1 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1041dfp6b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1041dfp6b-pinctrl.dtsi new file mode 100644 index 000000000..95acd9b85 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1041dfp6b-pinctrl.dtsi @@ -0,0 +1,3116 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1041DFP6B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_tx_data3: IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA3 { + pinmux = <0x401f80cc 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio6_io04: IOMUXC_GPIO_AD_B0_04_GPIO6_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_mqs_right: IOMUXC_GPIO_AD_B0_04_MQS_RIGHT { + pinmux = <0x401f80cc 1 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_pit_trigger0: IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER0 { + pinmux = <0x401f80cc 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_sai2_tx_sync: IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC { + pinmux = <0x401f80cc 3 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_src_boot_mode0: IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE0 { + pinmux = <0x401f80cc 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_tx_data2: IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA2 { + pinmux = <0x401f80d0 2 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio6_io05: IOMUXC_GPIO_AD_B0_05_GPIO6_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_mqs_left: IOMUXC_GPIO_AD_B0_05_MQS_LEFT { + pinmux = <0x401f80d0 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_sai2_tx_bclk: IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f80d0 3 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_src_boot_mode1: IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE1 { + pinmux = <0x401f80d0 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_IN17 { + pinmux = <0x401f80d0 6 0x0 0 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80d0 6 0x0 0 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_enet_rx_clk: IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK { + pinmux = <0x401f80d4 2 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio6_io06: IOMUXC_GPIO_AD_B0_06_GPIO6_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpt2_compare1: IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 { + pinmux = <0x401f80d4 1 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_jtag_tms: IOMUXC_GPIO_AD_B0_06_JTAG_TMS { + pinmux = <0x401f80d4 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_sai2_rx_bclk: IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK { + pinmux = <0x401f80d4 3 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_in18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_IN18 { + pinmux = <0x401f80d4 6 0x0 0 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_inout18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80d4 6 0x0 0 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_1588_event3_out: IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT { + pinmux = <0x401f80d8 7 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_tx_er: IOMUXC_GPIO_AD_B0_07_ENET_TX_ER { + pinmux = <0x401f80d8 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio6_io07: IOMUXC_GPIO_AD_B0_07_GPIO6_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpt2_compare2: IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 { + pinmux = <0x401f80d8 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_jtag_tck: IOMUXC_GPIO_AD_B0_07_JTAG_TCK { + pinmux = <0x401f80d8 0 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_sai2_rx_sync: IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC { + pinmux = <0x401f80d8 3 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_in19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_IN19 { + pinmux = <0x401f80d8 6 0x0 0 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_inout19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80d8 6 0x0 0 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_1588_event3_in: IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN { + pinmux = <0x401f80dc 7 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_rx_data3: IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA3 { + pinmux = <0x401f80dc 2 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio6_io08: IOMUXC_GPIO_AD_B0_08_GPIO6_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpt2_compare3: IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 { + pinmux = <0x401f80dc 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_jtag_mod: IOMUXC_GPIO_AD_B0_08_JTAG_MOD { + pinmux = <0x401f80dc 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_sai2_rx_data: IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA { + pinmux = <0x401f80dc 3 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_xbar1_xbar_in20: IOMUXC_GPIO_AD_B0_08_XBAR1_XBAR_IN20 { + pinmux = <0x401f80dc 6 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data2: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA2 { + pinmux = <0x401f80e0 2 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA3 { + pinmux = <0x401f80e0 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio6_io09: IOMUXC_GPIO_AD_B0_09_GPIO6_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpt2_clk: IOMUXC_GPIO_AD_B0_09_GPT2_CLK { + pinmux = <0x401f80e0 7 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_jtag_tdi: IOMUXC_GPIO_AD_B0_09_JTAG_TDI { + pinmux = <0x401f80e0 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_sai2_tx_data: IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA { + pinmux = <0x401f80e0 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_semc_dqs4: IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 { + pinmux = <0x401f80e0 9 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_xbar1_xbar_in21: IOMUXC_GPIO_AD_B0_09_XBAR1_XBAR_IN21 { + pinmux = <0x401f80e0 6 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_swo: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO { + pinmux = <0x401f80e4 9 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80e4 7 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_crs: IOMUXC_GPIO_AD_B0_10_ENET_CRS { + pinmux = <0x401f80e4 2 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexcan3_tx: IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX { + pinmux = <0x401f80e4 8 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm1_pwma3: IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA3 { + pinmux = <0x401f80e4 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio6_io10: IOMUXC_GPIO_AD_B0_10_GPIO6_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_jtag_tdo: IOMUXC_GPIO_AD_B0_10_JTAG_TDO { + pinmux = <0x401f80e4 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_sai2_mclk: IOMUXC_GPIO_AD_B0_10_SAI2_MCLK { + pinmux = <0x401f80e4 3 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_xbar1_xbar_in22: IOMUXC_GPIO_AD_B0_10_XBAR1_XBAR_IN22 { + pinmux = <0x401f80e4 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN { + pinmux = <0x401f80e8 7 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_col: IOMUXC_GPIO_AD_B0_11_ENET_COL { + pinmux = <0x401f80e8 2 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexcan3_rx: IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX { + pinmux = <0x401f80e8 8 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB3 { + pinmux = <0x401f80e8 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio6_io11: IOMUXC_GPIO_AD_B0_11_GPIO6_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_jtag_trstb: IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB { + pinmux = <0x401f80e8 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_semc_clk6: IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 { + pinmux = <0x401f80e8 9 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_wdog1_b: IOMUXC_GPIO_AD_B0_11_WDOG1_B { + pinmux = <0x401f80e8 3 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_xbar1_xbar_in23: IOMUXC_GPIO_AD_B0_11_XBAR1_XBAR_IN23 { + pinmux = <0x401f80e8 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in1: IOMUXC_GPIO_AD_B0_12_ADC1_IN1 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_nmi: IOMUXC_GPIO_AD_B0_12_ARM_NMI { + pinmux = <0x401f80ec 7 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_12_CCM_PMIC_RDY { + pinmux = <0x401f80ec 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_1588_event1_out: IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT { + pinmux = <0x401f80ec 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm1_pwmx2: IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX2 { + pinmux = <0x401f80ec 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio6_io12: IOMUXC_GPIO_AD_B0_12_GPIO6_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpi2c4_scl: IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL { + pinmux = <0x401f80ec 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart1_tx: IOMUXC_GPIO_AD_B0_12_LPUART1_TX { + pinmux = <0x401f80ec 2 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_wdog2_b: IOMUXC_GPIO_AD_B0_12_WDOG2_B { + pinmux = <0x401f80ec 3 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_acmp1_in2: IOMUXC_GPIO_AD_B0_13_ACMP1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc1_in2: IOMUXC_GPIO_AD_B0_13_ADC1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_1588_event1_in: IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN { + pinmux = <0x401f80f0 6 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ewm_out_b: IOMUXC_GPIO_AD_B0_13_EWM_OUT_B { + pinmux = <0x401f80f0 3 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm1_pwmx3: IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX3 { + pinmux = <0x401f80f0 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio6_io13: IOMUXC_GPIO_AD_B0_13_GPIO6_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpt1_clk: IOMUXC_GPIO_AD_B0_13_GPT1_CLK { + pinmux = <0x401f80f0 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpi2c4_sda: IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA { + pinmux = <0x401f80f0 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart1_rx: IOMUXC_GPIO_AD_B0_13_LPUART1_RX { + pinmux = <0x401f80f0 2 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ref_24m_out: IOMUXC_GPIO_AD_B0_13_REF_24M_OUT { + pinmux = <0x401f80f0 7 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in2: IOMUXC_GPIO_AD_B0_14_ACMP2_IN2 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in3: IOMUXC_GPIO_AD_B0_14_ADC1_IN3 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80f4 3 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan3_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX { + pinmux = <0x401f80f4 8 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio6_io14: IOMUXC_GPIO_AD_B0_14_GPIO6_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B { + pinmux = <0x401f80f4 2 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_xbar1_xbar_in24: IOMUXC_GPIO_AD_B0_14_XBAR1_XBAR_IN24 { + pinmux = <0x401f80f4 1 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in2: IOMUXC_GPIO_AD_B0_15_ACMP3_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in4: IOMUXC_GPIO_AD_B0_15_ADC1_IN4 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f80f8 3 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 6 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan3_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX { + pinmux = <0x401f80f8 8 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio6_io15: IOMUXC_GPIO_AD_B0_15_GPIO6_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B { + pinmux = <0x401f80f8 2 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb: IOMUXC_GPIO_AD_B0_15_WDOG1_RST_B_DEB { + pinmux = <0x401f80f8 7 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_xbar1_xbar_in25: IOMUXC_GPIO_AD_B0_15_XBAR1_XBAR_IN25 { + pinmux = <0x401f80f8 1 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp4_in2: IOMUXC_GPIO_AD_B1_00_ACMP4_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc1_in5: IOMUXC_GPIO_AD_B1_00_ADC1_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc2_in5: IOMUXC_GPIO_AD_B1_00_ADC2_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio3_flexio00: IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 { + pinmux = <0x401f80fc 9 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio6_io16: IOMUXC_GPIO_AD_B1_00_GPIO6_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpi2c1_scl: IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL { + pinmux = <0x401f80fc 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B { + pinmux = <0x401f80fc 2 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_qtimer3_timer0: IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 { + pinmux = <0x401f80fc 1 0x0 0 0x401f82ec>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usdhc1_wp: IOMUXC_GPIO_AD_B1_00_USDHC1_WP { + pinmux = <0x401f80fc 6 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_wdog1_b: IOMUXC_GPIO_AD_B1_00_WDOG1_B { + pinmux = <0x401f80fc 4 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp1_in0: IOMUXC_GPIO_AD_B1_01_ACMP1_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in0: IOMUXC_GPIO_AD_B1_01_ACMP2_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp3_in0: IOMUXC_GPIO_AD_B1_01_ACMP3_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp4_in0: IOMUXC_GPIO_AD_B1_01_ACMP4_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in6: IOMUXC_GPIO_AD_B1_01_ADC1_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc2_in6: IOMUXC_GPIO_AD_B1_01_ADC2_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_01_CCM_PMIC_RDY { + pinmux = <0x401f8100 4 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio3_flexio01: IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 { + pinmux = <0x401f8100 9 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio6_io17: IOMUXC_GPIO_AD_B1_01_GPIO6_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpi2c1_sda: IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA { + pinmux = <0x401f8100 3 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B { + pinmux = <0x401f8100 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_qtimer3_timer1: IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 { + pinmux = <0x401f8100 1 0x0 0 0x401f82f0>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR { + pinmux = <0x401f8100 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usdhc1_vselect: IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT { + pinmux = <0x401f8100 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp1_in3: IOMUXC_GPIO_AD_B1_02_ACMP1_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc1_in7: IOMUXC_GPIO_AD_B1_02_ADC1_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in7: IOMUXC_GPIO_AD_B1_02_ADC2_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT { + pinmux = <0x401f8104 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio3_flexio02: IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 { + pinmux = <0x401f8104 9 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio6_io18: IOMUXC_GPIO_AD_B1_02_GPIO6_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpt2_clk: IOMUXC_GPIO_AD_B1_02_GPT2_CLK { + pinmux = <0x401f8104 8 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpuart2_tx: IOMUXC_GPIO_AD_B1_02_LPUART2_TX { + pinmux = <0x401f8104 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_qtimer3_timer2: IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 { + pinmux = <0x401f8104 1 0x0 0 0x401f82f4>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_spdif_out: IOMUXC_GPIO_AD_B1_02_SPDIF_OUT { + pinmux = <0x401f8104 3 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usb_otg1_id: IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID { + pinmux = <0x401f8104 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B { + pinmux = <0x401f8104 6 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp2_in3: IOMUXC_GPIO_AD_B1_03_ACMP2_IN3 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in8: IOMUXC_GPIO_AD_B1_03_ADC1_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc2_in8: IOMUXC_GPIO_AD_B1_03_ADC2_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN { + pinmux = <0x401f8108 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio3_flexio03: IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 { + pinmux = <0x401f8108 9 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio6_io19: IOMUXC_GPIO_AD_B1_03_GPIO6_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpt2_capture1: IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 { + pinmux = <0x401f8108 8 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpuart2_rx: IOMUXC_GPIO_AD_B1_03_LPUART2_RX { + pinmux = <0x401f8108 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_qtimer3_timer3: IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 { + pinmux = <0x401f8108 1 0x0 0 0x401f82f8>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_spdif_in: IOMUXC_GPIO_AD_B1_03_SPDIF_IN { + pinmux = <0x401f8108 3 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usb_otg1_oc: IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC { + pinmux = <0x401f8108 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B { + pinmux = <0x401f8108 6 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp3_in3: IOMUXC_GPIO_AD_B1_04_ACMP3_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc1_in9: IOMUXC_GPIO_AD_B1_04_ADC1_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in9: IOMUXC_GPIO_AD_B1_04_ADC2_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_enet_mdc: IOMUXC_GPIO_AD_B1_04_ENET_MDC { + pinmux = <0x401f810c 1 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio3_flexio04: IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 { + pinmux = <0x401f810c 9 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_b_data3: IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 { + pinmux = <0x401f810c 0 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio6_io20: IOMUXC_GPIO_AD_B1_04_GPIO6_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpt2_capture2: IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 { + pinmux = <0x401f810c 8 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpuart3_cts_b: IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B { + pinmux = <0x401f810c 2 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_spdif_sr_clk: IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK { + pinmux = <0x401f810c 3 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_usdhc2_data0: IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f810c 6 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp4_in3: IOMUXC_GPIO_AD_B1_05_ACMP4_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in10: IOMUXC_GPIO_AD_B1_05_ADC1_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in10: IOMUXC_GPIO_AD_B1_05_ADC2_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_enet_mdio: IOMUXC_GPIO_AD_B1_05_ENET_MDIO { + pinmux = <0x401f8110 1 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio3_flexio05: IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 { + pinmux = <0x401f8110 9 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_b_data2: IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 { + pinmux = <0x401f8110 0 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio6_io21: IOMUXC_GPIO_AD_B1_05_GPIO6_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpt2_compare1: IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 { + pinmux = <0x401f8110 8 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpuart3_rts_b: IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B { + pinmux = <0x401f8110 2 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_spdif_out: IOMUXC_GPIO_AD_B1_05_SPDIF_OUT { + pinmux = <0x401f8110 3 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc2_data1: IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f8110 6 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp1_in1: IOMUXC_GPIO_AD_B1_06_ACMP1_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp2_in1: IOMUXC_GPIO_AD_B1_06_ACMP2_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in1: IOMUXC_GPIO_AD_B1_06_ACMP3_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp4_in1: IOMUXC_GPIO_AD_B1_06_ACMP4_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in11: IOMUXC_GPIO_AD_B1_06_ADC1_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in11: IOMUXC_GPIO_AD_B1_06_ADC2_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio3_flexio06: IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 { + pinmux = <0x401f8114 9 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexspi_b_data1: IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 { + pinmux = <0x401f8114 0 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio6_io22: IOMUXC_GPIO_AD_B1_06_GPIO6_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpt2_compare2: IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 { + pinmux = <0x401f8114 8 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpi2c3_sda: IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA { + pinmux = <0x401f8114 1 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart3_tx: IOMUXC_GPIO_AD_B1_06_LPUART3_TX { + pinmux = <0x401f8114 2 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_spdif_lock: IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK { + pinmux = <0x401f8114 3 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc2_data2: IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 { + pinmux = <0x401f8114 6 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp1_in5: IOMUXC_GPIO_AD_B1_07_ACMP1_IN5 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in12: IOMUXC_GPIO_AD_B1_07_ADC1_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in12: IOMUXC_GPIO_AD_B1_07_ADC2_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio3_flexio07: IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 { + pinmux = <0x401f8118 9 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexspi_b_data0: IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 { + pinmux = <0x401f8118 0 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio6_io23: IOMUXC_GPIO_AD_B1_07_GPIO6_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpt2_compare3: IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 { + pinmux = <0x401f8118 8 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpi2c3_scl: IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL { + pinmux = <0x401f8118 1 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart3_rx: IOMUXC_GPIO_AD_B1_07_LPUART3_RX { + pinmux = <0x401f8118 2 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_spdif_ext_clk: IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK { + pinmux = <0x401f8118 3 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc2_data3: IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 { + pinmux = <0x401f8118 6 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_flexio2_flexio00: IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 { + pinmux = <0x401f813c 4 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio2_io00: IOMUXC_GPIO_B0_00_GPIO2_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio7_io00: IOMUXC_GPIO_B0_00_GPIO7_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lpspi3_pcs0: IOMUXC_GPIO_B0_00_LPSPI3_PCS0 { + pinmux = <0x401f813c 3 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_mqs_right: IOMUXC_GPIO_B0_00_MQS_RIGHT { + pinmux = <0x401f813c 2 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_qtimer1_timer0: IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x0 0 0x401f832c>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_semc_csx1: IOMUXC_GPIO_B0_00_SEMC_CSX1 { + pinmux = <0x401f813c 6 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_flexio2_flexio01: IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 { + pinmux = <0x401f8140 4 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio2_io01: IOMUXC_GPIO_B0_01_GPIO2_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio7_io01: IOMUXC_GPIO_B0_01_GPIO7_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lpspi3_sdi: IOMUXC_GPIO_B0_01_LPSPI3_SDI { + pinmux = <0x401f8140 3 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_mqs_left: IOMUXC_GPIO_B0_01_MQS_LEFT { + pinmux = <0x401f8140 2 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_qtimer1_timer1: IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x0 0 0x401f8330>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_semc_csx2: IOMUXC_GPIO_B0_01_SEMC_CSX2 { + pinmux = <0x401f8140 6 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexcan1_tx: IOMUXC_GPIO_B0_02_FLEXCAN1_TX { + pinmux = <0x401f8144 2 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexio2_flexio02: IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 { + pinmux = <0x401f8144 4 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio2_io02: IOMUXC_GPIO_B0_02_GPIO2_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio7_io02: IOMUXC_GPIO_B0_02_GPIO7_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lpspi3_sdo: IOMUXC_GPIO_B0_02_LPSPI3_SDO { + pinmux = <0x401f8144 3 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_qtimer1_timer2: IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x0 0 0x401f8334>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_semc_csx3: IOMUXC_GPIO_B0_02_SEMC_CSX3 { + pinmux = <0x401f8144 6 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexcan1_rx: IOMUXC_GPIO_B0_03_FLEXCAN1_RX { + pinmux = <0x401f8148 2 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexio2_flexio03: IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 { + pinmux = <0x401f8148 4 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio2_io03: IOMUXC_GPIO_B0_03_GPIO2_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio7_io03: IOMUXC_GPIO_B0_03_GPIO7_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lpspi3_sck: IOMUXC_GPIO_B0_03_LPSPI3_SCK { + pinmux = <0x401f8148 3 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_qtimer2_timer0: IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 { + pinmux = <0x401f8148 1 0x0 0 0x401f8338>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_wdog2_rst_b_deb: IOMUXC_GPIO_B0_03_WDOG2_RST_B_DEB { + pinmux = <0x401f8148 6 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_arm_trace0: IOMUXC_GPIO_B0_04_ARM_TRACE0 { + pinmux = <0x401f814c 3 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_flexio2_flexio04: IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 { + pinmux = <0x401f814c 4 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio2_io04: IOMUXC_GPIO_B0_04_GPIO2_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio7_io04: IOMUXC_GPIO_B0_04_GPIO7_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lpi2c2_scl: IOMUXC_GPIO_B0_04_LPI2C2_SCL { + pinmux = <0x401f814c 2 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_qtimer2_timer1: IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 { + pinmux = <0x401f814c 1 0x0 0 0x401f833c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_src_bt_cfg0: IOMUXC_GPIO_B0_04_SRC_BT_CFG0 { + pinmux = <0x401f814c 6 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_arm_trace1: IOMUXC_GPIO_B0_05_ARM_TRACE1 { + pinmux = <0x401f8150 3 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_flexio2_flexio05: IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 { + pinmux = <0x401f8150 4 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio2_io05: IOMUXC_GPIO_B0_05_GPIO2_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio7_io05: IOMUXC_GPIO_B0_05_GPIO7_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lpi2c2_sda: IOMUXC_GPIO_B0_05_LPI2C2_SDA { + pinmux = <0x401f8150 2 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_qtimer2_timer2: IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 { + pinmux = <0x401f8150 1 0x0 0 0x401f8340>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_src_bt_cfg1: IOMUXC_GPIO_B0_05_SRC_BT_CFG1 { + pinmux = <0x401f8150 6 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_arm_trace2: IOMUXC_GPIO_B0_06_ARM_TRACE2 { + pinmux = <0x401f8154 3 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexio2_flexio06: IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 { + pinmux = <0x401f8154 4 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexpwm2_pwma0: IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f8154 2 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio2_io06: IOMUXC_GPIO_B0_06_GPIO2_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio7_io06: IOMUXC_GPIO_B0_06_GPIO7_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_qtimer3_timer0: IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 { + pinmux = <0x401f8154 1 0x0 0 0x401f8344>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_src_bt_cfg2: IOMUXC_GPIO_B0_06_SRC_BT_CFG2 { + pinmux = <0x401f8154 6 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_arm_trace3: IOMUXC_GPIO_B0_07_ARM_TRACE3 { + pinmux = <0x401f8158 3 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexio2_flexio07: IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 { + pinmux = <0x401f8158 4 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexpwm2_pwmb0: IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8158 2 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio2_io07: IOMUXC_GPIO_B0_07_GPIO2_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio7_io07: IOMUXC_GPIO_B0_07_GPIO7_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_qtimer3_timer1: IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 { + pinmux = <0x401f8158 1 0x0 0 0x401f8348>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_src_bt_cfg3: IOMUXC_GPIO_B0_07_SRC_BT_CFG3 { + pinmux = <0x401f8158 6 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexio2_flexio08: IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 { + pinmux = <0x401f815c 4 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexpwm2_pwma1: IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f815c 2 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio2_io08: IOMUXC_GPIO_B0_08_GPIO2_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio7_io08: IOMUXC_GPIO_B0_08_GPIO7_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lpuart3_tx: IOMUXC_GPIO_B0_08_LPUART3_TX { + pinmux = <0x401f815c 3 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_qtimer3_timer2: IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 { + pinmux = <0x401f815c 1 0x0 0 0x401f834c>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_src_bt_cfg4: IOMUXC_GPIO_B0_08_SRC_BT_CFG4 { + pinmux = <0x401f815c 6 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexio2_flexio09: IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 { + pinmux = <0x401f8160 4 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexpwm2_pwmb1: IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8160 2 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio2_io09: IOMUXC_GPIO_B0_09_GPIO2_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio7_io09: IOMUXC_GPIO_B0_09_GPIO7_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lpuart3_rx: IOMUXC_GPIO_B0_09_LPUART3_RX { + pinmux = <0x401f8160 3 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_qtimer4_timer0: IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 { + pinmux = <0x401f8160 1 0x0 0 0x401f8350>; + gpr = <0x400ac018 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_src_bt_cfg5: IOMUXC_GPIO_B0_09_SRC_BT_CFG5 { + pinmux = <0x401f8160 6 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexio2_flexio10: IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 { + pinmux = <0x401f8164 4 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f8164 2 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio2_io10: IOMUXC_GPIO_B0_10_GPIO2_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio7_io10: IOMUXC_GPIO_B0_10_GPIO7_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_qtimer4_timer1: IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 { + pinmux = <0x401f8164 1 0x0 0 0x401f8354>; + gpr = <0x400ac018 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_sai1_tx_data3: IOMUXC_GPIO_B0_10_SAI1_TX_DATA3 { + pinmux = <0x401f8164 3 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_src_bt_cfg6: IOMUXC_GPIO_B0_10_SRC_BT_CFG6 { + pinmux = <0x401f8164 6 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexio2_flexio11: IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 { + pinmux = <0x401f8168 4 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8168 2 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio2_io11: IOMUXC_GPIO_B0_11_GPIO2_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio7_io11: IOMUXC_GPIO_B0_11_GPIO7_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_qtimer4_timer2: IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 { + pinmux = <0x401f8168 1 0x0 0 0x401f8358>; + gpr = <0x400ac018 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_sai1_tx_data2: IOMUXC_GPIO_B0_11_SAI1_TX_DATA2 { + pinmux = <0x401f8168 3 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_src_bt_cfg7: IOMUXC_GPIO_B0_11_SRC_BT_CFG7 { + pinmux = <0x401f8168 6 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_arm_trace_clk: IOMUXC_GPIO_B0_12_ARM_TRACE_CLK { + pinmux = <0x401f816c 2 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_flexio2_flexio12: IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 { + pinmux = <0x401f816c 4 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio2_io12: IOMUXC_GPIO_B0_12_GPIO2_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio7_io12: IOMUXC_GPIO_B0_12_GPIO7_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_sai1_tx_data1: IOMUXC_GPIO_B0_12_SAI1_TX_DATA1 { + pinmux = <0x401f816c 3 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_src_bt_cfg8: IOMUXC_GPIO_B0_12_SRC_BT_CFG8 { + pinmux = <0x401f816c 6 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_in10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_IN10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_inout10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_arm_trace_swo: IOMUXC_GPIO_B0_13_ARM_TRACE_SWO { + pinmux = <0x401f8170 2 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_flexio2_flexio13: IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 { + pinmux = <0x401f8170 4 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio2_io13: IOMUXC_GPIO_B0_13_GPIO2_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio7_io13: IOMUXC_GPIO_B0_13_GPIO7_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_sai1_mclk: IOMUXC_GPIO_B0_13_SAI1_MCLK { + pinmux = <0x401f8170 3 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_src_bt_cfg9: IOMUXC_GPIO_B0_13_SRC_BT_CFG9 { + pinmux = <0x401f8170 6 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_in11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_IN11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_inout11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_flexio2_flexio14: IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 { + pinmux = <0x401f8174 4 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio2_io14: IOMUXC_GPIO_B0_14_GPIO2_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio7_io14: IOMUXC_GPIO_B0_14_GPIO7_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_sai1_rx_sync: IOMUXC_GPIO_B0_14_SAI1_RX_SYNC { + pinmux = <0x401f8174 3 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_src_bt_cfg10: IOMUXC_GPIO_B0_14_SRC_BT_CFG10 { + pinmux = <0x401f8174 6 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_in12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_IN12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_inout12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_flexio2_flexio15: IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 { + pinmux = <0x401f8178 4 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio2_io15: IOMUXC_GPIO_B0_15_GPIO2_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio7_io15: IOMUXC_GPIO_B0_15_GPIO7_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_sai1_rx_bclk: IOMUXC_GPIO_B0_15_SAI1_RX_BCLK { + pinmux = <0x401f8178 3 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_src_bt_cfg11: IOMUXC_GPIO_B0_15_SRC_BT_CFG11 { + pinmux = <0x401f8178 6 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_in13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_IN13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_inout13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio2_flexio16: IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 { + pinmux = <0x401f817c 4 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio3_flexio16: IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 { + pinmux = <0x401f817c 9 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f817c 6 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio2_io16: IOMUXC_GPIO_B1_00_GPIO2_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio7_io16: IOMUXC_GPIO_B1_00_GPIO7_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lpuart4_tx: IOMUXC_GPIO_B1_00_LPUART4_TX { + pinmux = <0x401f817c 2 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_sai1_rx_data0: IOMUXC_GPIO_B1_00_SAI1_RX_DATA0 { + pinmux = <0x401f817c 3 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_in14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f817c 1 0x0 0 0x401f836c>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_inout14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f817c 1 0x0 0 0x401f836c>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio2_flexio17: IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 { + pinmux = <0x401f8180 4 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio3_flexio17: IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 { + pinmux = <0x401f8180 9 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f8180 6 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio2_io17: IOMUXC_GPIO_B1_01_GPIO2_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio7_io17: IOMUXC_GPIO_B1_01_GPIO7_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lpuart4_rx: IOMUXC_GPIO_B1_01_LPUART4_RX { + pinmux = <0x401f8180 2 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_sai1_tx_data0: IOMUXC_GPIO_B1_01_SAI1_TX_DATA0 { + pinmux = <0x401f8180 3 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_in15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8180 1 0x0 0 0x401f8370>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_inout15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8180 1 0x0 0 0x401f8370>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio2_flexio18: IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 { + pinmux = <0x401f8184 4 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio3_flexio18: IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 { + pinmux = <0x401f8184 9 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f8184 6 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio2_io18: IOMUXC_GPIO_B1_02_GPIO2_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio7_io18: IOMUXC_GPIO_B1_02_GPIO7_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lpspi3_pcs2: IOMUXC_GPIO_B1_02_LPSPI3_PCS2 { + pinmux = <0x401f8184 2 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_sai1_tx_bclk: IOMUXC_GPIO_B1_02_SAI1_TX_BCLK { + pinmux = <0x401f8184 3 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_in16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8184 1 0x0 0 0x401f8374>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_inout16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8184 1 0x0 0 0x401f8374>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio2_flexio19: IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 { + pinmux = <0x401f8188 4 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio3_flexio19: IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 { + pinmux = <0x401f8188 9 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f8188 6 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio2_io19: IOMUXC_GPIO_B1_03_GPIO2_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio7_io19: IOMUXC_GPIO_B1_03_GPIO7_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lpspi3_pcs1: IOMUXC_GPIO_B1_03_LPSPI3_PCS1 { + pinmux = <0x401f8188 2 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_sai1_tx_sync: IOMUXC_GPIO_B1_03_SAI1_TX_SYNC { + pinmux = <0x401f8188 3 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_in17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f8188 1 0x0 0 0x401f8378>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_inout17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8188 1 0x0 0 0x401f8378>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_enet_rx_data0: IOMUXC_GPIO_B1_04_ENET_RX_DATA0 { + pinmux = <0x401f818c 3 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio2_flexio20: IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 { + pinmux = <0x401f818c 4 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio3_flexio20: IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 { + pinmux = <0x401f818c 9 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio2_io20: IOMUXC_GPIO_B1_04_GPIO2_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio7_io20: IOMUXC_GPIO_B1_04_GPIO7_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpt1_clk: IOMUXC_GPIO_B1_04_GPT1_CLK { + pinmux = <0x401f818c 8 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lpspi3_pcs0: IOMUXC_GPIO_B1_04_LPSPI3_PCS0 { + pinmux = <0x401f818c 1 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_enet_rx_data1: IOMUXC_GPIO_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f8190 3 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio2_flexio21: IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 { + pinmux = <0x401f8190 4 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio3_flexio21: IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 { + pinmux = <0x401f8190 9 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio2_io21: IOMUXC_GPIO_B1_05_GPIO2_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio7_io21: IOMUXC_GPIO_B1_05_GPIO7_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpt1_capture1: IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 { + pinmux = <0x401f8190 8 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lpspi3_sdi: IOMUXC_GPIO_B1_05_LPSPI3_SDI { + pinmux = <0x401f8190 1 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_enet_rx_en: IOMUXC_GPIO_B1_06_ENET_RX_EN { + pinmux = <0x401f8194 3 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio2_flexio22: IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 { + pinmux = <0x401f8194 4 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio3_flexio22: IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 { + pinmux = <0x401f8194 9 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio2_io22: IOMUXC_GPIO_B1_06_GPIO2_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio7_io22: IOMUXC_GPIO_B1_06_GPIO7_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpt1_capture2: IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 { + pinmux = <0x401f8194 8 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lpspi3_sdo: IOMUXC_GPIO_B1_06_LPSPI3_SDO { + pinmux = <0x401f8194 1 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_enet_tx_data0: IOMUXC_GPIO_B1_07_ENET_TX_DATA0 { + pinmux = <0x401f8198 3 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio2_flexio23: IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 { + pinmux = <0x401f8198 4 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio3_flexio23: IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 { + pinmux = <0x401f8198 9 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio2_io23: IOMUXC_GPIO_B1_07_GPIO2_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio7_io23: IOMUXC_GPIO_B1_07_GPIO7_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpt1_compare1: IOMUXC_GPIO_B1_07_GPT1_COMPARE1 { + pinmux = <0x401f8198 8 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lpspi3_sck: IOMUXC_GPIO_B1_07_LPSPI3_SCK { + pinmux = <0x401f8198 1 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_enet_tx_data1: IOMUXC_GPIO_B1_08_ENET_TX_DATA1 { + pinmux = <0x401f819c 3 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexcan2_tx: IOMUXC_GPIO_B1_08_FLEXCAN2_TX { + pinmux = <0x401f819c 6 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio2_flexio24: IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 { + pinmux = <0x401f819c 4 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio3_flexio24: IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 { + pinmux = <0x401f819c 9 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio2_io24: IOMUXC_GPIO_B1_08_GPIO2_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio7_io24: IOMUXC_GPIO_B1_08_GPIO7_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpt1_compare2: IOMUXC_GPIO_B1_08_GPT1_COMPARE2 { + pinmux = <0x401f819c 8 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_qtimer1_timer3: IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 { + pinmux = <0x401f819c 1 0x0 0 0x401f838c>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_enet_tx_en: IOMUXC_GPIO_B1_09_ENET_TX_EN { + pinmux = <0x401f81a0 3 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexcan2_rx: IOMUXC_GPIO_B1_09_FLEXCAN2_RX { + pinmux = <0x401f81a0 6 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio2_flexio25: IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 { + pinmux = <0x401f81a0 4 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio3_flexio25: IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 { + pinmux = <0x401f81a0 9 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio2_io25: IOMUXC_GPIO_B1_09_GPIO2_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio7_io25: IOMUXC_GPIO_B1_09_GPIO7_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpt1_compare3: IOMUXC_GPIO_B1_09_GPT1_COMPARE3 { + pinmux = <0x401f81a0 8 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_qtimer2_timer3: IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 { + pinmux = <0x401f81a0 1 0x0 0 0x401f8390>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_ref_clk: IOMUXC_GPIO_B1_10_ENET_REF_CLK { + pinmux = <0x401f81a4 6 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_tx_clk: IOMUXC_GPIO_B1_10_ENET_TX_CLK { + pinmux = <0x401f81a4 3 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio2_flexio26: IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 { + pinmux = <0x401f81a4 4 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio3_flexio26: IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 { + pinmux = <0x401f81a4 9 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio2_io26: IOMUXC_GPIO_B1_10_GPIO2_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio7_io26: IOMUXC_GPIO_B1_10_GPIO7_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_qtimer3_timer3: IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 { + pinmux = <0x401f81a4 1 0x0 0 0x401f8394>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_enet_rx_er: IOMUXC_GPIO_B1_11_ENET_RX_ER { + pinmux = <0x401f81a8 3 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio2_flexio27: IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 { + pinmux = <0x401f81a8 4 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio3_flexio27: IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 { + pinmux = <0x401f81a8 9 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio2_io27: IOMUXC_GPIO_B1_11_GPIO2_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio7_io27: IOMUXC_GPIO_B1_11_GPIO7_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lpspi3_pcs3: IOMUXC_GPIO_B1_11_LPSPI3_PCS3 { + pinmux = <0x401f81a8 6 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_qtimer4_timer3: IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 { + pinmux = <0x401f81a8 1 0x0 0 0x401f8398>; + gpr = <0x400ac018 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_enet_1588_event0_in: IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN { + pinmux = <0x401f81ac 3 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio2_flexio28: IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 { + pinmux = <0x401f81ac 4 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio3_flexio28: IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 { + pinmux = <0x401f81ac 9 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio2_io28: IOMUXC_GPIO_B1_12_GPIO2_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio7_io28: IOMUXC_GPIO_B1_12_GPIO7_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_lpuart5_tx: IOMUXC_GPIO_B1_12_LPUART5_TX { + pinmux = <0x401f81ac 1 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_usdhc1_cd_b: IOMUXC_GPIO_B1_12_USDHC1_CD_B { + pinmux = <0x401f81ac 6 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_enet_1588_event0_out: IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT { + pinmux = <0x401f81b0 3 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio2_flexio29: IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 { + pinmux = <0x401f81b0 4 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio3_flexio29: IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 { + pinmux = <0x401f81b0 9 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio2_io29: IOMUXC_GPIO_B1_13_GPIO2_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio7_io29: IOMUXC_GPIO_B1_13_GPIO7_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_lpuart5_rx: IOMUXC_GPIO_B1_13_LPUART5_RX { + pinmux = <0x401f81b0 1 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_semc_dqs4: IOMUXC_GPIO_B1_13_SEMC_DQS4 { + pinmux = <0x401f81b0 8 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_usdhc1_wp: IOMUXC_GPIO_B1_13_USDHC1_WP { + pinmux = <0x401f81b0 6 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_wdog1_b: IOMUXC_GPIO_B1_13_WDOG1_B { + pinmux = <0x401f81b0 0 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet_mdc: IOMUXC_GPIO_B1_14_ENET_MDC { + pinmux = <0x401f81b4 0 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio2_flexio30: IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 { + pinmux = <0x401f81b4 4 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio3_flexio30: IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 { + pinmux = <0x401f81b4 9 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexpwm4_pwma2: IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA2 { + pinmux = <0x401f81b4 1 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio2_io30: IOMUXC_GPIO_B1_14_GPIO2_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio7_io30: IOMUXC_GPIO_B1_14_GPIO7_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_usdhc1_vselect: IOMUXC_GPIO_B1_14_USDHC1_VSELECT { + pinmux = <0x401f81b4 6 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_xbar1_xbar_in02: IOMUXC_GPIO_B1_14_XBAR1_XBAR_IN02 { + pinmux = <0x401f81b4 3 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet_mdio: IOMUXC_GPIO_B1_15_ENET_MDIO { + pinmux = <0x401f81b8 0 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio2_flexio31: IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 { + pinmux = <0x401f81b8 4 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio3_flexio31: IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 { + pinmux = <0x401f81b8 9 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexpwm4_pwma3: IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA3 { + pinmux = <0x401f81b8 1 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio2_io31: IOMUXC_GPIO_B1_15_GPIO2_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio7_io31: IOMUXC_GPIO_B1_15_GPIO7_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_usdhc1_reset_b: IOMUXC_GPIO_B1_15_USDHC1_RESET_B { + pinmux = <0x401f81b8 6 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_xbar1_xbar_in03: IOMUXC_GPIO_B1_15_XBAR1_XBAR_IN03 { + pinmux = <0x401f81b8 3 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexio1_flexio00: IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8014 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexpwm4_pwma0: IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA0 { + pinmux = <0x401f8014 1 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio4_io00: IOMUXC_GPIO_EMC_00_GPIO4_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio9_io00: IOMUXC_GPIO_EMC_00_GPIO9_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 2 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_xbar1_xbar_in02: IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 { + pinmux = <0x401f8014 3 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexio1_flexio01: IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8018 4 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexpwm4_pwmb0: IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB0 { + pinmux = <0x401f8018 1 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio4_io01: IOMUXC_GPIO_EMC_01_GPIO4_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio9_io01: IOMUXC_GPIO_EMC_01_GPIO9_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 2 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_xbar1_xbar_in03: IOMUXC_GPIO_EMC_01_XBAR1_XBAR_IN03 { + pinmux = <0x401f8018 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexio1_flexio02: IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 { + pinmux = <0x401f801c 4 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexpwm4_pwma1: IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA1 { + pinmux = <0x401f801c 1 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio4_io02: IOMUXC_GPIO_EMC_02_GPIO4_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio9_io02: IOMUXC_GPIO_EMC_02_GPIO9_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 2 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_in04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_IN04 { + pinmux = <0x401f801c 3 0x0 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f801c 3 0x0 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexio1_flexio03: IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 { + pinmux = <0x401f8020 4 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexpwm4_pwmb1: IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB1 { + pinmux = <0x401f8020 1 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio4_io03: IOMUXC_GPIO_EMC_03_GPIO4_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio9_io03: IOMUXC_GPIO_EMC_03_GPIO9_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 2 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_in05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_IN05 { + pinmux = <0x401f8020 3 0x0 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8020 3 0x0 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio04: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8024 4 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexpwm4_pwma2: IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA2 { + pinmux = <0x401f8024 1 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio4_io04: IOMUXC_GPIO_EMC_04_GPIO4_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio9_io04: IOMUXC_GPIO_EMC_04_GPIO9_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_data: IOMUXC_GPIO_EMC_04_SAI2_TX_DATA { + pinmux = <0x401f8024 2 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN06 { + pinmux = <0x401f8024 3 0x0 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f8024 3 0x0 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio05: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8028 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexpwm4_pwmb2: IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB2 { + pinmux = <0x401f8028 1 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio4_io05: IOMUXC_GPIO_EMC_05_GPIO4_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio9_io05: IOMUXC_GPIO_EMC_05_GPIO9_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 2 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN07 { + pinmux = <0x401f8028 3 0x0 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8028 3 0x0 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio06: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 { + pinmux = <0x401f802c 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexpwm2_pwma0: IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f802c 1 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio4_io06: IOMUXC_GPIO_EMC_06_GPIO4_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio9_io06: IOMUXC_GPIO_EMC_06_GPIO9_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_bclk: IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK { + pinmux = <0x401f802c 2 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN08 { + pinmux = <0x401f802c 3 0x0 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f802c 3 0x0 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio07: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 { + pinmux = <0x401f8030 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8030 1 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio4_io07: IOMUXC_GPIO_EMC_07_GPIO4_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio9_io07: IOMUXC_GPIO_EMC_07_GPIO9_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_mclk: IOMUXC_GPIO_EMC_07_SAI2_MCLK { + pinmux = <0x401f8030 2 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN09 { + pinmux = <0x401f8030 3 0x0 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8030 3 0x0 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio08: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8034 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexpwm2_pwma1: IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f8034 1 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio4_io08: IOMUXC_GPIO_EMC_08_GPIO4_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio9_io08: IOMUXC_GPIO_EMC_08_GPIO9_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 2 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN17 { + pinmux = <0x401f8034 3 0x0 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8034 3 0x0 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_tx: IOMUXC_GPIO_EMC_09_FLEXCAN2_TX { + pinmux = <0x401f8038 3 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio09: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8038 4 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8038 1 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexspi2_b_ss1_b: IOMUXC_GPIO_EMC_09_FLEXSPI2_B_SS1_B { + pinmux = <0x401f8038 8 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio4_io09: IOMUXC_GPIO_EMC_09_GPIO4_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio9_io09: IOMUXC_GPIO_EMC_09_GPIO9_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_sync: IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC { + pinmux = <0x401f8038 2 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_addr00: IOMUXC_GPIO_EMC_09_SEMC_ADDR00 { + pinmux = <0x401f8038 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexcan2_rx: IOMUXC_GPIO_EMC_10_FLEXCAN2_RX { + pinmux = <0x401f803c 3 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexio1_flexio10: IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 { + pinmux = <0x401f803c 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwma2: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f803c 1 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_10_FLEXSPI2_B_SS0_B { + pinmux = <0x401f803c 8 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio4_io10: IOMUXC_GPIO_EMC_10_GPIO4_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio9_io10: IOMUXC_GPIO_EMC_10_GPIO9_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai2_rx_bclk: IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK { + pinmux = <0x401f803c 2 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_addr01: IOMUXC_GPIO_EMC_10_SEMC_ADDR01 { + pinmux = <0x401f803c 0 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexio1_flexio11: IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 { + pinmux = <0x401f8040 4 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8040 1 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexspi2_b_dqs: IOMUXC_GPIO_EMC_11_FLEXSPI2_B_DQS { + pinmux = <0x401f8040 8 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio4_io11: IOMUXC_GPIO_EMC_11_GPIO4_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio9_io11: IOMUXC_GPIO_EMC_11_GPIO9_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_sda: IOMUXC_GPIO_EMC_11_LPI2C4_SDA { + pinmux = <0x401f8040 2 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_addr02: IOMUXC_GPIO_EMC_11_SEMC_ADDR02 { + pinmux = <0x401f8040 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_usdhc2_reset_b: IOMUXC_GPIO_EMC_11_USDHC2_RESET_B { + pinmux = <0x401f8040 3 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm1_pwma3: IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f8044 4 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexspi2_b_sclk: IOMUXC_GPIO_EMC_12_FLEXSPI2_B_SCLK { + pinmux = <0x401f8044 8 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio4_io12: IOMUXC_GPIO_EMC_12_GPIO4_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio9_io12: IOMUXC_GPIO_EMC_12_GPIO9_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpi2c4_scl: IOMUXC_GPIO_EMC_12_LPI2C4_SCL { + pinmux = <0x401f8044 2 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_addr03: IOMUXC_GPIO_EMC_12_SEMC_ADDR03 { + pinmux = <0x401f8044 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_usdhc1_wp: IOMUXC_GPIO_EMC_12_USDHC1_WP { + pinmux = <0x401f8044 3 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in24: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN24 { + pinmux = <0x401f8044 1 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8048 4 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexspi2_b_data0: IOMUXC_GPIO_EMC_13_FLEXSPI2_B_DATA0 { + pinmux = <0x401f8048 8 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio4_io13: IOMUXC_GPIO_EMC_13_GPIO4_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio9_io13: IOMUXC_GPIO_EMC_13_GPIO9_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart3_tx: IOMUXC_GPIO_EMC_13_LPUART3_TX { + pinmux = <0x401f8048 2 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_mqs_right: IOMUXC_GPIO_EMC_13_MQS_RIGHT { + pinmux = <0x401f8048 3 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_addr04: IOMUXC_GPIO_EMC_13_SEMC_ADDR04 { + pinmux = <0x401f8048 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in25: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN25 { + pinmux = <0x401f8048 1 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_flexspi2_b_data1: IOMUXC_GPIO_EMC_14_FLEXSPI2_B_DATA1 { + pinmux = <0x401f804c 8 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio4_io14: IOMUXC_GPIO_EMC_14_GPIO4_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio9_io14: IOMUXC_GPIO_EMC_14_GPIO9_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart3_rx: IOMUXC_GPIO_EMC_14_LPUART3_RX { + pinmux = <0x401f804c 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_mqs_left: IOMUXC_GPIO_EMC_14_MQS_LEFT { + pinmux = <0x401f804c 3 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_addr05: IOMUXC_GPIO_EMC_14_SEMC_ADDR05 { + pinmux = <0x401f804c 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN19 { + pinmux = <0x401f804c 1 0x0 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f804c 1 0x0 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_flexspi2_b_data2: IOMUXC_GPIO_EMC_15_FLEXSPI2_B_DATA2 { + pinmux = <0x401f8050 8 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio4_io15: IOMUXC_GPIO_EMC_15_GPIO4_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio9_io15: IOMUXC_GPIO_EMC_15_GPIO9_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart3_cts_b: IOMUXC_GPIO_EMC_15_LPUART3_CTS_B { + pinmux = <0x401f8050 2 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_qtimer3_timer0: IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 { + pinmux = <0x401f8050 4 0x0 0 0x401f8240>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr06: IOMUXC_GPIO_EMC_15_SEMC_ADDR06 { + pinmux = <0x401f8050 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_spdif_out: IOMUXC_GPIO_EMC_15_SPDIF_OUT { + pinmux = <0x401f8050 3 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in20: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN20 { + pinmux = <0x401f8050 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_flexspi2_b_data3: IOMUXC_GPIO_EMC_16_FLEXSPI2_B_DATA3 { + pinmux = <0x401f8054 8 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio4_io16: IOMUXC_GPIO_EMC_16_GPIO4_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio9_io16: IOMUXC_GPIO_EMC_16_GPIO9_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_lpuart3_rts_b: IOMUXC_GPIO_EMC_16_LPUART3_RTS_B { + pinmux = <0x401f8054 2 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_qtimer3_timer1: IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 { + pinmux = <0x401f8054 4 0x0 0 0x401f8244>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr07: IOMUXC_GPIO_EMC_16_SEMC_ADDR07 { + pinmux = <0x401f8054 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_spdif_in: IOMUXC_GPIO_EMC_16_SPDIF_IN { + pinmux = <0x401f8054 3 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_xbar1_xbar_in21: IOMUXC_GPIO_EMC_16_XBAR1_XBAR_IN21 { + pinmux = <0x401f8054 1 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexcan1_tx: IOMUXC_GPIO_EMC_17_FLEXCAN1_TX { + pinmux = <0x401f8058 3 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexpwm4_pwma3: IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA3 { + pinmux = <0x401f8058 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio4_io17: IOMUXC_GPIO_EMC_17_GPIO4_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio9_io17: IOMUXC_GPIO_EMC_17_GPIO9_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_lpuart4_cts_b: IOMUXC_GPIO_EMC_17_LPUART4_CTS_B { + pinmux = <0x401f8058 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_qtimer3_timer2: IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 { + pinmux = <0x401f8058 4 0x0 0 0x401f8248>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr08: IOMUXC_GPIO_EMC_17_SEMC_ADDR08 { + pinmux = <0x401f8058 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexcan1_rx: IOMUXC_GPIO_EMC_18_FLEXCAN1_RX { + pinmux = <0x401f805c 3 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexpwm4_pwmb3: IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB3 { + pinmux = <0x401f805c 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio4_io18: IOMUXC_GPIO_EMC_18_GPIO4_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio9_io18: IOMUXC_GPIO_EMC_18_GPIO9_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpuart4_rts_b: IOMUXC_GPIO_EMC_18_LPUART4_RTS_B { + pinmux = <0x401f805c 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_qtimer3_timer3: IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 { + pinmux = <0x401f805c 4 0x0 0 0x401f824c>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr09: IOMUXC_GPIO_EMC_18_SEMC_ADDR09 { + pinmux = <0x401f805c 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_snvs_vio_5_ctl: IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL { + pinmux = <0x401f805c 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_enet_rx_data1: IOMUXC_GPIO_EMC_19_ENET_RX_DATA1 { + pinmux = <0x401f8060 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexpwm2_pwma3: IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA3 { + pinmux = <0x401f8060 1 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio4_io19: IOMUXC_GPIO_EMC_19_GPIO4_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio9_io19: IOMUXC_GPIO_EMC_19_GPIO9_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpuart4_tx: IOMUXC_GPIO_EMC_19_LPUART4_TX { + pinmux = <0x401f8060 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_qtimer2_timer0: IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 { + pinmux = <0x401f8060 4 0x0 0 0x401f8250>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr11: IOMUXC_GPIO_EMC_19_SEMC_ADDR11 { + pinmux = <0x401f8060 0 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_snvs_vio_5_b: IOMUXC_GPIO_EMC_19_SNVS_VIO_5_B { + pinmux = <0x401f8060 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_enet_rx_data0: IOMUXC_GPIO_EMC_20_ENET_RX_DATA0 { + pinmux = <0x401f8064 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB3 { + pinmux = <0x401f8064 1 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio4_io20: IOMUXC_GPIO_EMC_20_GPIO4_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio9_io20: IOMUXC_GPIO_EMC_20_GPIO9_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart4_rx: IOMUXC_GPIO_EMC_20_LPUART4_RX { + pinmux = <0x401f8064 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_qtimer2_timer1: IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 { + pinmux = <0x401f8064 4 0x0 0 0x401f8254>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr12: IOMUXC_GPIO_EMC_20_SEMC_ADDR12 { + pinmux = <0x401f8064 0 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_enet_tx_data1: IOMUXC_GPIO_EMC_21_ENET_TX_DATA1 { + pinmux = <0x401f8068 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm3_pwma3: IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA3 { + pinmux = <0x401f8068 1 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio4_io21: IOMUXC_GPIO_EMC_21_GPIO4_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio9_io21: IOMUXC_GPIO_EMC_21_GPIO9_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpi2c3_sda: IOMUXC_GPIO_EMC_21_LPI2C3_SDA { + pinmux = <0x401f8068 2 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_qtimer2_timer2: IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 { + pinmux = <0x401f8068 4 0x0 0 0x401f8258>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_ba0: IOMUXC_GPIO_EMC_21_SEMC_BA0 { + pinmux = <0x401f8068 0 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_enet_tx_data0: IOMUXC_GPIO_EMC_22_ENET_TX_DATA0 { + pinmux = <0x401f806c 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm3_pwmb3: IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB3 { + pinmux = <0x401f806c 1 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexspi2_a_ss1_b: IOMUXC_GPIO_EMC_22_FLEXSPI2_A_SS1_B { + pinmux = <0x401f806c 8 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio4_io22: IOMUXC_GPIO_EMC_22_GPIO4_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio9_io22: IOMUXC_GPIO_EMC_22_GPIO9_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpi2c3_scl: IOMUXC_GPIO_EMC_22_LPI2C3_SCL { + pinmux = <0x401f806c 2 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_qtimer2_timer3: IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 { + pinmux = <0x401f806c 4 0x0 0 0x401f825c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_ba1: IOMUXC_GPIO_EMC_22_SEMC_BA1 { + pinmux = <0x401f806c 0 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_enet_rx_en: IOMUXC_GPIO_EMC_23_ENET_RX_EN { + pinmux = <0x401f8070 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwma0: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA0 { + pinmux = <0x401f8070 1 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexspi2_a_dqs: IOMUXC_GPIO_EMC_23_FLEXSPI2_A_DQS { + pinmux = <0x401f8070 8 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio4_io23: IOMUXC_GPIO_EMC_23_GPIO4_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio9_io23: IOMUXC_GPIO_EMC_23_GPIO9_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpt1_capture2: IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 { + pinmux = <0x401f8070 4 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart5_tx: IOMUXC_GPIO_EMC_23_LPUART5_TX { + pinmux = <0x401f8070 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr10: IOMUXC_GPIO_EMC_23_SEMC_ADDR10 { + pinmux = <0x401f8070 0 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_enet_tx_en: IOMUXC_GPIO_EMC_24_ENET_TX_EN { + pinmux = <0x401f8074 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB0 { + pinmux = <0x401f8074 1 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_24_FLEXSPI2_A_SS0_B { + pinmux = <0x401f8074 8 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio4_io24: IOMUXC_GPIO_EMC_24_GPIO4_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio9_io24: IOMUXC_GPIO_EMC_24_GPIO9_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpt1_capture1: IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 { + pinmux = <0x401f8074 4 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart5_rx: IOMUXC_GPIO_EMC_24_LPUART5_RX { + pinmux = <0x401f8074 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_cas: IOMUXC_GPIO_EMC_24_SEMC_CAS { + pinmux = <0x401f8074 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_ref_clk: IOMUXC_GPIO_EMC_25_ENET_REF_CLK { + pinmux = <0x401f8078 4 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_tx_clk: IOMUXC_GPIO_EMC_25_ENET_TX_CLK { + pinmux = <0x401f8078 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwma1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA1 { + pinmux = <0x401f8078 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexspi2_a_sclk: IOMUXC_GPIO_EMC_25_FLEXSPI2_A_SCLK { + pinmux = <0x401f8078 8 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio4_io25: IOMUXC_GPIO_EMC_25_GPIO4_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio9_io25: IOMUXC_GPIO_EMC_25_GPIO9_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart6_tx: IOMUXC_GPIO_EMC_25_LPUART6_TX { + pinmux = <0x401f8078 2 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_ras: IOMUXC_GPIO_EMC_25_SEMC_RAS { + pinmux = <0x401f8078 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_enet_rx_er: IOMUXC_GPIO_EMC_26_ENET_RX_ER { + pinmux = <0x401f807c 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio12: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 { + pinmux = <0x401f807c 4 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB1 { + pinmux = <0x401f807c 1 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexspi2_a_data0: IOMUXC_GPIO_EMC_26_FLEXSPI2_A_DATA0 { + pinmux = <0x401f807c 8 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio4_io26: IOMUXC_GPIO_EMC_26_GPIO4_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio9_io26: IOMUXC_GPIO_EMC_26_GPIO9_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart6_rx: IOMUXC_GPIO_EMC_26_LPUART6_RX { + pinmux = <0x401f807c 2 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_clk: IOMUXC_GPIO_EMC_26_SEMC_CLK { + pinmux = <0x401f807c 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio13: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8080 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwma2: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA2 { + pinmux = <0x401f8080 1 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexspi2_a_data1: IOMUXC_GPIO_EMC_27_FLEXSPI2_A_DATA1 { + pinmux = <0x401f8080 8 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio4_io27: IOMUXC_GPIO_EMC_27_GPIO4_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio9_io27: IOMUXC_GPIO_EMC_27_GPIO9_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpspi1_sck: IOMUXC_GPIO_EMC_27_LPSPI1_SCK { + pinmux = <0x401f8080 3 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart5_rts_b: IOMUXC_GPIO_EMC_27_LPUART5_RTS_B { + pinmux = <0x401f8080 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_cke: IOMUXC_GPIO_EMC_27_SEMC_CKE { + pinmux = <0x401f8080 0 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexio1_flexio14: IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8084 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB2 { + pinmux = <0x401f8084 1 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexspi2_a_data2: IOMUXC_GPIO_EMC_28_FLEXSPI2_A_DATA2 { + pinmux = <0x401f8084 8 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio4_io28: IOMUXC_GPIO_EMC_28_GPIO4_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio9_io28: IOMUXC_GPIO_EMC_28_GPIO9_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpspi1_sdo: IOMUXC_GPIO_EMC_28_LPSPI1_SDO { + pinmux = <0x401f8084 3 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpuart5_cts_b: IOMUXC_GPIO_EMC_28_LPUART5_CTS_B { + pinmux = <0x401f8084 2 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_we: IOMUXC_GPIO_EMC_28_SEMC_WE { + pinmux = <0x401f8084 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexio1_flexio15: IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 { + pinmux = <0x401f8088 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm3_pwma0: IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA0 { + pinmux = <0x401f8088 1 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexspi2_a_data3: IOMUXC_GPIO_EMC_29_FLEXSPI2_A_DATA3 { + pinmux = <0x401f8088 8 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio4_io29: IOMUXC_GPIO_EMC_29_GPIO4_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio9_io29: IOMUXC_GPIO_EMC_29_GPIO9_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpspi1_sdi: IOMUXC_GPIO_EMC_29_LPSPI1_SDI { + pinmux = <0x401f8088 3 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpuart6_rts_b: IOMUXC_GPIO_EMC_29_LPUART6_RTS_B { + pinmux = <0x401f8088 2 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cs0: IOMUXC_GPIO_EMC_29_SEMC_CS0 { + pinmux = <0x401f8088 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm3_pwmb0: IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB0 { + pinmux = <0x401f808c 1 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio4_io30: IOMUXC_GPIO_EMC_30_GPIO4_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio9_io30: IOMUXC_GPIO_EMC_30_GPIO9_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpspi1_pcs0: IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 { + pinmux = <0x401f808c 3 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart6_cts_b: IOMUXC_GPIO_EMC_30_LPUART6_CTS_B { + pinmux = <0x401f808c 2 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_data08: IOMUXC_GPIO_EMC_30_SEMC_DATA08 { + pinmux = <0x401f808c 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm3_pwma1: IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA1 { + pinmux = <0x401f8090 1 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio4_io31: IOMUXC_GPIO_EMC_31_GPIO4_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio9_io31: IOMUXC_GPIO_EMC_31_GPIO9_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpspi1_pcs1: IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 { + pinmux = <0x401f8090 3 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart7_tx: IOMUXC_GPIO_EMC_31_LPUART7_TX { + pinmux = <0x401f8090 2 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_data09: IOMUXC_GPIO_EMC_31_SEMC_DATA09 { + pinmux = <0x401f8090 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ccm_pmic_rdy: IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY { + pinmux = <0x401f8094 3 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_flexpwm3_pwmb1: IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB1 { + pinmux = <0x401f8094 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io18: IOMUXC_GPIO_EMC_32_GPIO3_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio8_io18: IOMUXC_GPIO_EMC_32_GPIO8_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart7_rx: IOMUXC_GPIO_EMC_32_LPUART7_RX { + pinmux = <0x401f8094 2 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data10: IOMUXC_GPIO_EMC_32_SEMC_DATA10 { + pinmux = <0x401f8094 0 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_flexpwm3_pwma2: IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA2 { + pinmux = <0x401f8098 1 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io19: IOMUXC_GPIO_EMC_33_GPIO3_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio8_io19: IOMUXC_GPIO_EMC_33_GPIO8_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_rx_data: IOMUXC_GPIO_EMC_33_SAI3_RX_DATA { + pinmux = <0x401f8098 3 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data11: IOMUXC_GPIO_EMC_33_SEMC_DATA11 { + pinmux = <0x401f8098 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_usdhc1_reset_b: IOMUXC_GPIO_EMC_33_USDHC1_RESET_B { + pinmux = <0x401f8098 2 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_flexpwm3_pwmb2: IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB2 { + pinmux = <0x401f809c 1 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io20: IOMUXC_GPIO_EMC_34_GPIO3_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio8_io20: IOMUXC_GPIO_EMC_34_GPIO8_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_rx_sync: IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC { + pinmux = <0x401f809c 3 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data12: IOMUXC_GPIO_EMC_34_SEMC_DATA12 { + pinmux = <0x401f809c 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_usdhc1_vselect: IOMUXC_GPIO_EMC_34_USDHC1_VSELECT { + pinmux = <0x401f809c 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io21: IOMUXC_GPIO_EMC_35_GPIO3_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio8_io21: IOMUXC_GPIO_EMC_35_GPIO8_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpt1_compare1: IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 { + pinmux = <0x401f80a0 2 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_sai3_rx_bclk: IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK { + pinmux = <0x401f80a0 3 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data13: IOMUXC_GPIO_EMC_35_SEMC_DATA13 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc1_cd_b: IOMUXC_GPIO_EMC_35_USDHC1_CD_B { + pinmux = <0x401f80a0 6 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_in18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_IN18 { + pinmux = <0x401f80a0 1 0x0 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80a0 1 0x0 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexcan3_tx: IOMUXC_GPIO_EMC_36_FLEXCAN3_TX { + pinmux = <0x401f80a4 9 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io22: IOMUXC_GPIO_EMC_36_GPIO3_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio8_io22: IOMUXC_GPIO_EMC_36_GPIO8_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpt1_compare2: IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 { + pinmux = <0x401f80a4 2 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_sai3_tx_data: IOMUXC_GPIO_EMC_36_SAI3_TX_DATA { + pinmux = <0x401f80a4 3 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data14: IOMUXC_GPIO_EMC_36_SEMC_DATA14 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 6 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_xbar1_xbar_in22: IOMUXC_GPIO_EMC_36_XBAR1_XBAR_IN22 { + pinmux = <0x401f80a4 1 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexcan3_rx: IOMUXC_GPIO_EMC_37_FLEXCAN3_RX { + pinmux = <0x401f80a8 9 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io23: IOMUXC_GPIO_EMC_37_GPIO3_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio8_io23: IOMUXC_GPIO_EMC_37_GPIO8_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpt1_compare3: IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 { + pinmux = <0x401f80a8 2 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_sai3_mclk: IOMUXC_GPIO_EMC_37_SAI3_MCLK { + pinmux = <0x401f80a8 3 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data15: IOMUXC_GPIO_EMC_37_SEMC_DATA15 { + pinmux = <0x401f80a8 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc2_wp: IOMUXC_GPIO_EMC_37_USDHC2_WP { + pinmux = <0x401f80a8 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_xbar1_xbar_in23: IOMUXC_GPIO_EMC_37_XBAR1_XBAR_IN23 { + pinmux = <0x401f80a8 1 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm1_pwma3: IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA3 { + pinmux = <0x401f80ac 1 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io24: IOMUXC_GPIO_EMC_38_GPIO3_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio8_io24: IOMUXC_GPIO_EMC_38_GPIO8_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart8_tx: IOMUXC_GPIO_EMC_38_LPUART8_TX { + pinmux = <0x401f80ac 2 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_sai3_tx_bclk: IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK { + pinmux = <0x401f80ac 3 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_dm1: IOMUXC_GPIO_EMC_38_SEMC_DM1 { + pinmux = <0x401f80ac 0 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc2_vselect: IOMUXC_GPIO_EMC_38_USDHC2_VSELECT { + pinmux = <0x401f80ac 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB3 { + pinmux = <0x401f80b0 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io25: IOMUXC_GPIO_EMC_39_GPIO3_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio8_io25: IOMUXC_GPIO_EMC_39_GPIO8_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart8_rx: IOMUXC_GPIO_EMC_39_LPUART8_RX { + pinmux = <0x401f80b0 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_sai3_tx_sync: IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC { + pinmux = <0x401f80b0 3 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs: IOMUXC_GPIO_EMC_39_SEMC_DQS { + pinmux = <0x401f80b0 0 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs4: IOMUXC_GPIO_EMC_39_SEMC_DQS4 { + pinmux = <0x401f80b0 9 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usdhc2_cd_b: IOMUXC_GPIO_EMC_39_USDHC2_CD_B { + pinmux = <0x401f80b0 6 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdc: IOMUXC_GPIO_EMC_40_ENET_MDC { + pinmux = <0x401f80b4 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io26: IOMUXC_GPIO_EMC_40_GPIO3_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio8_io26: IOMUXC_GPIO_EMC_40_GPIO8_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt2_capture2: IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 { + pinmux = <0x401f80b4 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_lpspi1_pcs2: IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 { + pinmux = <0x401f80b4 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_clk5: IOMUXC_GPIO_EMC_40_SEMC_CLK5 { + pinmux = <0x401f80b4 9 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_rdy: IOMUXC_GPIO_EMC_40_SEMC_RDY { + pinmux = <0x401f80b4 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usdhc2_reset_b: IOMUXC_GPIO_EMC_40_USDHC2_RESET_B { + pinmux = <0x401f80b4 6 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdio: IOMUXC_GPIO_EMC_41_ENET_MDIO { + pinmux = <0x401f80b8 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io27: IOMUXC_GPIO_EMC_41_GPIO3_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio8_io27: IOMUXC_GPIO_EMC_41_GPIO8_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt2_capture1: IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 { + pinmux = <0x401f80b8 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_lpspi1_pcs3: IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 { + pinmux = <0x401f80b8 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_csx0: IOMUXC_GPIO_EMC_41_SEMC_CSX0 { + pinmux = <0x401f80b8 0 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usdhc1_vselect: IOMUXC_GPIO_EMC_41_USDHC1_VSELECT { + pinmux = <0x401f80b8 6 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexpwm1_pwma0: IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA0 { + pinmux = <0x401f81bc 1 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f81bc 6 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io12: IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio8_io12: IOMUXC_GPIO_SD_B0_00_GPIO8_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f81bc 2 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpspi1_sck: IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK { + pinmux = <0x401f81bc 4 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_semc_dqs4: IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 { + pinmux = <0x401f81bc 9 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_cmd: IOMUXC_GPIO_SD_B0_00_USDHC1_CMD { + pinmux = <0x401f81bc 0 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN04 { + pinmux = <0x401f81bc 3 0x0 0 0x401f83ac>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f81bc 3 0x0 0 0x401f83ac>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexpwm1_pwmb0: IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB0 { + pinmux = <0x401f81c0 1 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f81c0 6 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io13: IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio8_io13: IOMUXC_GPIO_SD_B0_01_GPIO8_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f81c0 2 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 { + pinmux = <0x401f81c0 4 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_clk: IOMUXC_GPIO_SD_B0_01_USDHC1_CLK { + pinmux = <0x401f81c0 0 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN05 { + pinmux = <0x401f81c0 3 0x0 0 0x401f83b0>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f81c0 3 0x0 0 0x401f83b0>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_flexpwm1_pwma1: IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA1 { + pinmux = <0x401f81c4 1 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io14: IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio8_io14: IOMUXC_GPIO_SD_B0_02_GPIO8_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sdo: IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO { + pinmux = <0x401f81c4 4 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart8_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B { + pinmux = <0x401f81c4 2 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_semc_clk5: IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 { + pinmux = <0x401f81c4 9 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_data0: IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 { + pinmux = <0x401f81c4 0 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN06 { + pinmux = <0x401f81c4 3 0x0 0 0x401f83b4>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f81c4 3 0x0 0 0x401f83b4>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_flexpwm1_pwmb1: IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB1 { + pinmux = <0x401f81c8 1 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io15: IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio8_io15: IOMUXC_GPIO_SD_B0_03_GPIO8_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_sdi: IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI { + pinmux = <0x401f81c8 4 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart8_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B { + pinmux = <0x401f81c8 2 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_semc_clk6: IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 { + pinmux = <0x401f81c8 9 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_data1: IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 { + pinmux = <0x401f81c8 0 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_in07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_IN07 { + pinmux = <0x401f81c8 3 0x0 0 0x401f83b8>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_inout07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f81c8 3 0x0 0 0x401f83b8>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_ccm_clko1: IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 { + pinmux = <0x401f81cc 6 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexpwm1_pwma2: IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA2 { + pinmux = <0x401f81cc 1 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f81cc 4 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io16: IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio8_io16: IOMUXC_GPIO_SD_B0_04_GPIO8_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart8_tx: IOMUXC_GPIO_SD_B0_04_LPUART8_TX { + pinmux = <0x401f81cc 2 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data2: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 { + pinmux = <0x401f81cc 0 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_in08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_IN08 { + pinmux = <0x401f81cc 3 0x0 0 0x401f83bc>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_inout08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f81cc 3 0x0 0 0x401f83bc>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_ccm_clko2: IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 { + pinmux = <0x401f81d0 6 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexpwm1_pwmb2: IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB2 { + pinmux = <0x401f81d0 1 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f81d0 4 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io17: IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio8_io17: IOMUXC_GPIO_SD_B0_05_GPIO8_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart8_rx: IOMUXC_GPIO_SD_B0_05_LPUART8_RX { + pinmux = <0x401f81d0 2 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data3: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 { + pinmux = <0x401f81d0 0 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_in09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_IN09 { + pinmux = <0x401f81d0 3 0x0 0 0x401f83c0>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_inout09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f81d0 3 0x0 0 0x401f83c0>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f81d4 2 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f81d4 1 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io00: IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio8_io00: IOMUXC_GPIO_SD_B1_00_GPIO8_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart4_tx: IOMUXC_GPIO_SD_B1_00_LPUART4_TX { + pinmux = <0x401f81d4 4 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai1_tx_data3: IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA3 { + pinmux = <0x401f81d4 3 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai3_rx_data: IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA { + pinmux = <0x401f81d4 8 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data3: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 { + pinmux = <0x401f81d4 0 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f81d8 2 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_data2: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 { + pinmux = <0x401f81d8 1 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io01: IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio8_io01: IOMUXC_GPIO_SD_B1_01_GPIO8_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart4_rx: IOMUXC_GPIO_SD_B1_01_LPUART4_RX { + pinmux = <0x401f81d8 4 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai1_tx_data2: IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA2 { + pinmux = <0x401f81d8 3 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai3_tx_data: IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA { + pinmux = <0x401f81d8 8 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data2: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 { + pinmux = <0x401f81d8 0 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_wait: IOMUXC_GPIO_SD_B1_02_CCM_WAIT { + pinmux = <0x401f81dc 6 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexcan1_tx: IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX { + pinmux = <0x401f81dc 4 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f81dc 2 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data1: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 { + pinmux = <0x401f81dc 1 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io02: IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio8_io02: IOMUXC_GPIO_SD_B1_02_GPIO8_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai1_tx_data1: IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA1 { + pinmux = <0x401f81dc 3 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai3_tx_sync: IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC { + pinmux = <0x401f81dc 8 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_data1: IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 { + pinmux = <0x401f81dc 0 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_03_CCM_PMIC_RDY { + pinmux = <0x401f81e0 6 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexcan1_rx: IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX { + pinmux = <0x401f81e0 4 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f81e0 2 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data0: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 { + pinmux = <0x401f81e0 1 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io03: IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio8_io03: IOMUXC_GPIO_SD_B1_03_GPIO8_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai1_mclk: IOMUXC_GPIO_SD_B1_03_SAI1_MCLK { + pinmux = <0x401f81e0 3 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK { + pinmux = <0x401f81e0 8 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_data0: IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 { + pinmux = <0x401f81e0 0 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_stop: IOMUXC_GPIO_SD_B1_04_CCM_STOP { + pinmux = <0x401f81e4 6 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI_A_SS1_B { + pinmux = <0x401f81e4 4 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK { + pinmux = <0x401f81e4 1 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io04: IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio8_io04: IOMUXC_GPIO_SD_B1_04_GPIO8_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_lpi2c1_scl: IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL { + pinmux = <0x401f81e4 2 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai1_rx_sync: IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f81e4 3 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai3_mclk: IOMUXC_GPIO_SD_B1_04_SAI3_MCLK { + pinmux = <0x401f81e4 8 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_clk: IOMUXC_GPIO_SD_B1_04_USDHC2_CLK { + pinmux = <0x401f81e4 0 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f81e8 1 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f81e8 4 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io05: IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio8_io05: IOMUXC_GPIO_SD_B1_05_GPIO8_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_lpi2c1_sda: IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA { + pinmux = <0x401f81e8 2 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai1_rx_bclk: IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK { + pinmux = <0x401f81e8 3 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_rx_sync: IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC { + pinmux = <0x401f81e8 8 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_cmd: IOMUXC_GPIO_SD_B1_05_USDHC2_CMD { + pinmux = <0x401f81e8 0 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B { + pinmux = <0x401f81ec 1 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io06: IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio8_io06: IOMUXC_GPIO_SD_B1_06_GPIO8_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f81ec 4 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpuart7_cts_b: IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B { + pinmux = <0x401f81ec 2 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai1_rx_data0: IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA0 { + pinmux = <0x401f81ec 3 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK { + pinmux = <0x401f81ec 8 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B { + pinmux = <0x401f81ec 0 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f81f0 1 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io07: IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio8_io07: IOMUXC_GPIO_SD_B1_07_GPIO8_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f81f0 4 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpuart7_rts_b: IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B { + pinmux = <0x401f81f0 2 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai1_tx_data0: IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA0 { + pinmux = <0x401f81f0 3 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_semc_csx1: IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 { + pinmux = <0x401f81f0 0 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f81f4 1 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io08: IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio8_io08: IOMUXC_GPIO_SD_B1_08_GPIO8_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f81f4 4 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpuart7_tx: IOMUXC_GPIO_SD_B1_08_LPUART7_TX { + pinmux = <0x401f81f4 2 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai1_tx_bclk: IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK { + pinmux = <0x401f81f4 3 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_semc_csx2: IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 { + pinmux = <0x401f81f4 6 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f81f4 0 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data1: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 { + pinmux = <0x401f81f8 1 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io09: IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio8_io09: IOMUXC_GPIO_SD_B1_09_GPIO8_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f81f8 4 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpuart7_rx: IOMUXC_GPIO_SD_B1_09_LPUART7_RX { + pinmux = <0x401f81f8 2 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai1_tx_sync: IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC { + pinmux = <0x401f81f8 3 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f81f8 0 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data2: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 { + pinmux = <0x401f81fc 1 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io10: IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio8_io10: IOMUXC_GPIO_SD_B1_10_GPIO8_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpi2c2_sda: IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA { + pinmux = <0x401f81fc 3 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f81fc 4 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpuart2_rx: IOMUXC_GPIO_SD_B1_10_LPUART2_RX { + pinmux = <0x401f81fc 2 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f81fc 0 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_data3: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 { + pinmux = <0x401f8200 1 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io11: IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio8_io11: IOMUXC_GPIO_SD_B1_11_GPIO8_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpi2c2_scl: IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL { + pinmux = <0x401f8200 3 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8200 4 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpuart2_tx: IOMUXC_GPIO_SD_B1_11_LPUART2_TX { + pinmux = <0x401f8200 2 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8200 0 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x0 0 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1041djm6b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1041djm6b-pinctrl.dtsi new file mode 100644 index 000000000..cbe558202 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1041djm6b-pinctrl.dtsi @@ -0,0 +1,3116 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1041DJM6B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_tx_data3: IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA3 { + pinmux = <0x401f80cc 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio6_io04: IOMUXC_GPIO_AD_B0_04_GPIO6_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_mqs_right: IOMUXC_GPIO_AD_B0_04_MQS_RIGHT { + pinmux = <0x401f80cc 1 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_pit_trigger0: IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER0 { + pinmux = <0x401f80cc 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_sai2_tx_sync: IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC { + pinmux = <0x401f80cc 3 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_src_boot_mode0: IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE0 { + pinmux = <0x401f80cc 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_tx_data2: IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA2 { + pinmux = <0x401f80d0 2 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio6_io05: IOMUXC_GPIO_AD_B0_05_GPIO6_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_mqs_left: IOMUXC_GPIO_AD_B0_05_MQS_LEFT { + pinmux = <0x401f80d0 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_sai2_tx_bclk: IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f80d0 3 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_src_boot_mode1: IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE1 { + pinmux = <0x401f80d0 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_IN17 { + pinmux = <0x401f80d0 6 0x0 0 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80d0 6 0x0 0 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_enet_rx_clk: IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK { + pinmux = <0x401f80d4 2 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio6_io06: IOMUXC_GPIO_AD_B0_06_GPIO6_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpt2_compare1: IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 { + pinmux = <0x401f80d4 1 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_jtag_tms: IOMUXC_GPIO_AD_B0_06_JTAG_TMS { + pinmux = <0x401f80d4 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_sai2_rx_bclk: IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK { + pinmux = <0x401f80d4 3 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_in18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_IN18 { + pinmux = <0x401f80d4 6 0x0 0 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_inout18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80d4 6 0x0 0 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_1588_event3_out: IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT { + pinmux = <0x401f80d8 7 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_tx_er: IOMUXC_GPIO_AD_B0_07_ENET_TX_ER { + pinmux = <0x401f80d8 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio6_io07: IOMUXC_GPIO_AD_B0_07_GPIO6_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpt2_compare2: IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 { + pinmux = <0x401f80d8 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_jtag_tck: IOMUXC_GPIO_AD_B0_07_JTAG_TCK { + pinmux = <0x401f80d8 0 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_sai2_rx_sync: IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC { + pinmux = <0x401f80d8 3 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_in19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_IN19 { + pinmux = <0x401f80d8 6 0x0 0 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_inout19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80d8 6 0x0 0 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_1588_event3_in: IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN { + pinmux = <0x401f80dc 7 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_rx_data3: IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA3 { + pinmux = <0x401f80dc 2 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio6_io08: IOMUXC_GPIO_AD_B0_08_GPIO6_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpt2_compare3: IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 { + pinmux = <0x401f80dc 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_jtag_mod: IOMUXC_GPIO_AD_B0_08_JTAG_MOD { + pinmux = <0x401f80dc 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_sai2_rx_data: IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA { + pinmux = <0x401f80dc 3 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_xbar1_xbar_in20: IOMUXC_GPIO_AD_B0_08_XBAR1_XBAR_IN20 { + pinmux = <0x401f80dc 6 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data2: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA2 { + pinmux = <0x401f80e0 2 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA3 { + pinmux = <0x401f80e0 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio6_io09: IOMUXC_GPIO_AD_B0_09_GPIO6_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpt2_clk: IOMUXC_GPIO_AD_B0_09_GPT2_CLK { + pinmux = <0x401f80e0 7 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_jtag_tdi: IOMUXC_GPIO_AD_B0_09_JTAG_TDI { + pinmux = <0x401f80e0 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_sai2_tx_data: IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA { + pinmux = <0x401f80e0 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_semc_dqs4: IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 { + pinmux = <0x401f80e0 9 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_xbar1_xbar_in21: IOMUXC_GPIO_AD_B0_09_XBAR1_XBAR_IN21 { + pinmux = <0x401f80e0 6 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_swo: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO { + pinmux = <0x401f80e4 9 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80e4 7 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_crs: IOMUXC_GPIO_AD_B0_10_ENET_CRS { + pinmux = <0x401f80e4 2 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexcan3_tx: IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX { + pinmux = <0x401f80e4 8 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm1_pwma3: IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA3 { + pinmux = <0x401f80e4 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio6_io10: IOMUXC_GPIO_AD_B0_10_GPIO6_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_jtag_tdo: IOMUXC_GPIO_AD_B0_10_JTAG_TDO { + pinmux = <0x401f80e4 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_sai2_mclk: IOMUXC_GPIO_AD_B0_10_SAI2_MCLK { + pinmux = <0x401f80e4 3 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_xbar1_xbar_in22: IOMUXC_GPIO_AD_B0_10_XBAR1_XBAR_IN22 { + pinmux = <0x401f80e4 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN { + pinmux = <0x401f80e8 7 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_col: IOMUXC_GPIO_AD_B0_11_ENET_COL { + pinmux = <0x401f80e8 2 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexcan3_rx: IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX { + pinmux = <0x401f80e8 8 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB3 { + pinmux = <0x401f80e8 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio6_io11: IOMUXC_GPIO_AD_B0_11_GPIO6_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_jtag_trstb: IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB { + pinmux = <0x401f80e8 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_semc_clk6: IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 { + pinmux = <0x401f80e8 9 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_wdog1_b: IOMUXC_GPIO_AD_B0_11_WDOG1_B { + pinmux = <0x401f80e8 3 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_xbar1_xbar_in23: IOMUXC_GPIO_AD_B0_11_XBAR1_XBAR_IN23 { + pinmux = <0x401f80e8 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in1: IOMUXC_GPIO_AD_B0_12_ADC1_IN1 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_nmi: IOMUXC_GPIO_AD_B0_12_ARM_NMI { + pinmux = <0x401f80ec 7 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_12_CCM_PMIC_RDY { + pinmux = <0x401f80ec 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_1588_event1_out: IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT { + pinmux = <0x401f80ec 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm1_pwmx2: IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX2 { + pinmux = <0x401f80ec 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio6_io12: IOMUXC_GPIO_AD_B0_12_GPIO6_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpi2c4_scl: IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL { + pinmux = <0x401f80ec 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart1_tx: IOMUXC_GPIO_AD_B0_12_LPUART1_TX { + pinmux = <0x401f80ec 2 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_wdog2_b: IOMUXC_GPIO_AD_B0_12_WDOG2_B { + pinmux = <0x401f80ec 3 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_acmp1_in2: IOMUXC_GPIO_AD_B0_13_ACMP1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc1_in2: IOMUXC_GPIO_AD_B0_13_ADC1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_1588_event1_in: IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN { + pinmux = <0x401f80f0 6 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ewm_out_b: IOMUXC_GPIO_AD_B0_13_EWM_OUT_B { + pinmux = <0x401f80f0 3 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm1_pwmx3: IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX3 { + pinmux = <0x401f80f0 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio6_io13: IOMUXC_GPIO_AD_B0_13_GPIO6_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpt1_clk: IOMUXC_GPIO_AD_B0_13_GPT1_CLK { + pinmux = <0x401f80f0 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpi2c4_sda: IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA { + pinmux = <0x401f80f0 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart1_rx: IOMUXC_GPIO_AD_B0_13_LPUART1_RX { + pinmux = <0x401f80f0 2 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ref_24m_out: IOMUXC_GPIO_AD_B0_13_REF_24M_OUT { + pinmux = <0x401f80f0 7 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in2: IOMUXC_GPIO_AD_B0_14_ACMP2_IN2 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in3: IOMUXC_GPIO_AD_B0_14_ADC1_IN3 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80f4 3 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan3_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX { + pinmux = <0x401f80f4 8 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio6_io14: IOMUXC_GPIO_AD_B0_14_GPIO6_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B { + pinmux = <0x401f80f4 2 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_xbar1_xbar_in24: IOMUXC_GPIO_AD_B0_14_XBAR1_XBAR_IN24 { + pinmux = <0x401f80f4 1 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in2: IOMUXC_GPIO_AD_B0_15_ACMP3_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in4: IOMUXC_GPIO_AD_B0_15_ADC1_IN4 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f80f8 3 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 6 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan3_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX { + pinmux = <0x401f80f8 8 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio6_io15: IOMUXC_GPIO_AD_B0_15_GPIO6_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B { + pinmux = <0x401f80f8 2 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb: IOMUXC_GPIO_AD_B0_15_WDOG1_RST_B_DEB { + pinmux = <0x401f80f8 7 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_xbar1_xbar_in25: IOMUXC_GPIO_AD_B0_15_XBAR1_XBAR_IN25 { + pinmux = <0x401f80f8 1 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp4_in2: IOMUXC_GPIO_AD_B1_00_ACMP4_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc1_in5: IOMUXC_GPIO_AD_B1_00_ADC1_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc2_in5: IOMUXC_GPIO_AD_B1_00_ADC2_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio3_flexio00: IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 { + pinmux = <0x401f80fc 9 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio6_io16: IOMUXC_GPIO_AD_B1_00_GPIO6_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpi2c1_scl: IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL { + pinmux = <0x401f80fc 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B { + pinmux = <0x401f80fc 2 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_qtimer3_timer0: IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 { + pinmux = <0x401f80fc 1 0x0 0 0x401f82ec>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usdhc1_wp: IOMUXC_GPIO_AD_B1_00_USDHC1_WP { + pinmux = <0x401f80fc 6 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_wdog1_b: IOMUXC_GPIO_AD_B1_00_WDOG1_B { + pinmux = <0x401f80fc 4 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp1_in0: IOMUXC_GPIO_AD_B1_01_ACMP1_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in0: IOMUXC_GPIO_AD_B1_01_ACMP2_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp3_in0: IOMUXC_GPIO_AD_B1_01_ACMP3_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp4_in0: IOMUXC_GPIO_AD_B1_01_ACMP4_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in6: IOMUXC_GPIO_AD_B1_01_ADC1_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc2_in6: IOMUXC_GPIO_AD_B1_01_ADC2_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_01_CCM_PMIC_RDY { + pinmux = <0x401f8100 4 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio3_flexio01: IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 { + pinmux = <0x401f8100 9 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio6_io17: IOMUXC_GPIO_AD_B1_01_GPIO6_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpi2c1_sda: IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA { + pinmux = <0x401f8100 3 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B { + pinmux = <0x401f8100 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_qtimer3_timer1: IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 { + pinmux = <0x401f8100 1 0x0 0 0x401f82f0>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR { + pinmux = <0x401f8100 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usdhc1_vselect: IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT { + pinmux = <0x401f8100 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp1_in3: IOMUXC_GPIO_AD_B1_02_ACMP1_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc1_in7: IOMUXC_GPIO_AD_B1_02_ADC1_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in7: IOMUXC_GPIO_AD_B1_02_ADC2_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT { + pinmux = <0x401f8104 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio3_flexio02: IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 { + pinmux = <0x401f8104 9 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio6_io18: IOMUXC_GPIO_AD_B1_02_GPIO6_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpt2_clk: IOMUXC_GPIO_AD_B1_02_GPT2_CLK { + pinmux = <0x401f8104 8 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpuart2_tx: IOMUXC_GPIO_AD_B1_02_LPUART2_TX { + pinmux = <0x401f8104 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_qtimer3_timer2: IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 { + pinmux = <0x401f8104 1 0x0 0 0x401f82f4>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_spdif_out: IOMUXC_GPIO_AD_B1_02_SPDIF_OUT { + pinmux = <0x401f8104 3 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usb_otg1_id: IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID { + pinmux = <0x401f8104 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B { + pinmux = <0x401f8104 6 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp2_in3: IOMUXC_GPIO_AD_B1_03_ACMP2_IN3 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in8: IOMUXC_GPIO_AD_B1_03_ADC1_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc2_in8: IOMUXC_GPIO_AD_B1_03_ADC2_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN { + pinmux = <0x401f8108 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio3_flexio03: IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 { + pinmux = <0x401f8108 9 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio6_io19: IOMUXC_GPIO_AD_B1_03_GPIO6_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpt2_capture1: IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 { + pinmux = <0x401f8108 8 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpuart2_rx: IOMUXC_GPIO_AD_B1_03_LPUART2_RX { + pinmux = <0x401f8108 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_qtimer3_timer3: IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 { + pinmux = <0x401f8108 1 0x0 0 0x401f82f8>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_spdif_in: IOMUXC_GPIO_AD_B1_03_SPDIF_IN { + pinmux = <0x401f8108 3 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usb_otg1_oc: IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC { + pinmux = <0x401f8108 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B { + pinmux = <0x401f8108 6 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp3_in3: IOMUXC_GPIO_AD_B1_04_ACMP3_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc1_in9: IOMUXC_GPIO_AD_B1_04_ADC1_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in9: IOMUXC_GPIO_AD_B1_04_ADC2_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_enet_mdc: IOMUXC_GPIO_AD_B1_04_ENET_MDC { + pinmux = <0x401f810c 1 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio3_flexio04: IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 { + pinmux = <0x401f810c 9 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_b_data3: IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 { + pinmux = <0x401f810c 0 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio6_io20: IOMUXC_GPIO_AD_B1_04_GPIO6_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpt2_capture2: IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 { + pinmux = <0x401f810c 8 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpuart3_cts_b: IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B { + pinmux = <0x401f810c 2 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_spdif_sr_clk: IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK { + pinmux = <0x401f810c 3 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_usdhc2_data0: IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f810c 6 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp4_in3: IOMUXC_GPIO_AD_B1_05_ACMP4_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in10: IOMUXC_GPIO_AD_B1_05_ADC1_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in10: IOMUXC_GPIO_AD_B1_05_ADC2_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_enet_mdio: IOMUXC_GPIO_AD_B1_05_ENET_MDIO { + pinmux = <0x401f8110 1 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio3_flexio05: IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 { + pinmux = <0x401f8110 9 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_b_data2: IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 { + pinmux = <0x401f8110 0 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio6_io21: IOMUXC_GPIO_AD_B1_05_GPIO6_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpt2_compare1: IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 { + pinmux = <0x401f8110 8 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpuart3_rts_b: IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B { + pinmux = <0x401f8110 2 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_spdif_out: IOMUXC_GPIO_AD_B1_05_SPDIF_OUT { + pinmux = <0x401f8110 3 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc2_data1: IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f8110 6 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp1_in1: IOMUXC_GPIO_AD_B1_06_ACMP1_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp2_in1: IOMUXC_GPIO_AD_B1_06_ACMP2_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in1: IOMUXC_GPIO_AD_B1_06_ACMP3_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp4_in1: IOMUXC_GPIO_AD_B1_06_ACMP4_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in11: IOMUXC_GPIO_AD_B1_06_ADC1_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in11: IOMUXC_GPIO_AD_B1_06_ADC2_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio3_flexio06: IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 { + pinmux = <0x401f8114 9 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexspi_b_data1: IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 { + pinmux = <0x401f8114 0 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio6_io22: IOMUXC_GPIO_AD_B1_06_GPIO6_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpt2_compare2: IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 { + pinmux = <0x401f8114 8 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpi2c3_sda: IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA { + pinmux = <0x401f8114 1 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart3_tx: IOMUXC_GPIO_AD_B1_06_LPUART3_TX { + pinmux = <0x401f8114 2 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_spdif_lock: IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK { + pinmux = <0x401f8114 3 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc2_data2: IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 { + pinmux = <0x401f8114 6 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp1_in5: IOMUXC_GPIO_AD_B1_07_ACMP1_IN5 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in12: IOMUXC_GPIO_AD_B1_07_ADC1_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in12: IOMUXC_GPIO_AD_B1_07_ADC2_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio3_flexio07: IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 { + pinmux = <0x401f8118 9 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexspi_b_data0: IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 { + pinmux = <0x401f8118 0 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio6_io23: IOMUXC_GPIO_AD_B1_07_GPIO6_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpt2_compare3: IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 { + pinmux = <0x401f8118 8 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpi2c3_scl: IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL { + pinmux = <0x401f8118 1 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart3_rx: IOMUXC_GPIO_AD_B1_07_LPUART3_RX { + pinmux = <0x401f8118 2 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_spdif_ext_clk: IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK { + pinmux = <0x401f8118 3 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc2_data3: IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 { + pinmux = <0x401f8118 6 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_flexio2_flexio00: IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 { + pinmux = <0x401f813c 4 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio2_io00: IOMUXC_GPIO_B0_00_GPIO2_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio7_io00: IOMUXC_GPIO_B0_00_GPIO7_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lpspi3_pcs0: IOMUXC_GPIO_B0_00_LPSPI3_PCS0 { + pinmux = <0x401f813c 3 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_mqs_right: IOMUXC_GPIO_B0_00_MQS_RIGHT { + pinmux = <0x401f813c 2 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_qtimer1_timer0: IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x0 0 0x401f832c>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_semc_csx1: IOMUXC_GPIO_B0_00_SEMC_CSX1 { + pinmux = <0x401f813c 6 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_flexio2_flexio01: IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 { + pinmux = <0x401f8140 4 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio2_io01: IOMUXC_GPIO_B0_01_GPIO2_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio7_io01: IOMUXC_GPIO_B0_01_GPIO7_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lpspi3_sdi: IOMUXC_GPIO_B0_01_LPSPI3_SDI { + pinmux = <0x401f8140 3 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_mqs_left: IOMUXC_GPIO_B0_01_MQS_LEFT { + pinmux = <0x401f8140 2 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_qtimer1_timer1: IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x0 0 0x401f8330>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_semc_csx2: IOMUXC_GPIO_B0_01_SEMC_CSX2 { + pinmux = <0x401f8140 6 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexcan1_tx: IOMUXC_GPIO_B0_02_FLEXCAN1_TX { + pinmux = <0x401f8144 2 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexio2_flexio02: IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 { + pinmux = <0x401f8144 4 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio2_io02: IOMUXC_GPIO_B0_02_GPIO2_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio7_io02: IOMUXC_GPIO_B0_02_GPIO7_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lpspi3_sdo: IOMUXC_GPIO_B0_02_LPSPI3_SDO { + pinmux = <0x401f8144 3 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_qtimer1_timer2: IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x0 0 0x401f8334>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_semc_csx3: IOMUXC_GPIO_B0_02_SEMC_CSX3 { + pinmux = <0x401f8144 6 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexcan1_rx: IOMUXC_GPIO_B0_03_FLEXCAN1_RX { + pinmux = <0x401f8148 2 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexio2_flexio03: IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 { + pinmux = <0x401f8148 4 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio2_io03: IOMUXC_GPIO_B0_03_GPIO2_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio7_io03: IOMUXC_GPIO_B0_03_GPIO7_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lpspi3_sck: IOMUXC_GPIO_B0_03_LPSPI3_SCK { + pinmux = <0x401f8148 3 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_qtimer2_timer0: IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 { + pinmux = <0x401f8148 1 0x0 0 0x401f8338>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_wdog2_rst_b_deb: IOMUXC_GPIO_B0_03_WDOG2_RST_B_DEB { + pinmux = <0x401f8148 6 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_arm_trace0: IOMUXC_GPIO_B0_04_ARM_TRACE0 { + pinmux = <0x401f814c 3 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_flexio2_flexio04: IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 { + pinmux = <0x401f814c 4 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio2_io04: IOMUXC_GPIO_B0_04_GPIO2_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio7_io04: IOMUXC_GPIO_B0_04_GPIO7_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lpi2c2_scl: IOMUXC_GPIO_B0_04_LPI2C2_SCL { + pinmux = <0x401f814c 2 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_qtimer2_timer1: IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 { + pinmux = <0x401f814c 1 0x0 0 0x401f833c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_src_bt_cfg0: IOMUXC_GPIO_B0_04_SRC_BT_CFG0 { + pinmux = <0x401f814c 6 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_arm_trace1: IOMUXC_GPIO_B0_05_ARM_TRACE1 { + pinmux = <0x401f8150 3 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_flexio2_flexio05: IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 { + pinmux = <0x401f8150 4 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio2_io05: IOMUXC_GPIO_B0_05_GPIO2_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio7_io05: IOMUXC_GPIO_B0_05_GPIO7_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lpi2c2_sda: IOMUXC_GPIO_B0_05_LPI2C2_SDA { + pinmux = <0x401f8150 2 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_qtimer2_timer2: IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 { + pinmux = <0x401f8150 1 0x0 0 0x401f8340>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_src_bt_cfg1: IOMUXC_GPIO_B0_05_SRC_BT_CFG1 { + pinmux = <0x401f8150 6 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_arm_trace2: IOMUXC_GPIO_B0_06_ARM_TRACE2 { + pinmux = <0x401f8154 3 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexio2_flexio06: IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 { + pinmux = <0x401f8154 4 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexpwm2_pwma0: IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f8154 2 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio2_io06: IOMUXC_GPIO_B0_06_GPIO2_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio7_io06: IOMUXC_GPIO_B0_06_GPIO7_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_qtimer3_timer0: IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 { + pinmux = <0x401f8154 1 0x0 0 0x401f8344>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_src_bt_cfg2: IOMUXC_GPIO_B0_06_SRC_BT_CFG2 { + pinmux = <0x401f8154 6 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_arm_trace3: IOMUXC_GPIO_B0_07_ARM_TRACE3 { + pinmux = <0x401f8158 3 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexio2_flexio07: IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 { + pinmux = <0x401f8158 4 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexpwm2_pwmb0: IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8158 2 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio2_io07: IOMUXC_GPIO_B0_07_GPIO2_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio7_io07: IOMUXC_GPIO_B0_07_GPIO7_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_qtimer3_timer1: IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 { + pinmux = <0x401f8158 1 0x0 0 0x401f8348>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_src_bt_cfg3: IOMUXC_GPIO_B0_07_SRC_BT_CFG3 { + pinmux = <0x401f8158 6 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexio2_flexio08: IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 { + pinmux = <0x401f815c 4 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexpwm2_pwma1: IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f815c 2 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio2_io08: IOMUXC_GPIO_B0_08_GPIO2_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio7_io08: IOMUXC_GPIO_B0_08_GPIO7_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lpuart3_tx: IOMUXC_GPIO_B0_08_LPUART3_TX { + pinmux = <0x401f815c 3 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_qtimer3_timer2: IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 { + pinmux = <0x401f815c 1 0x0 0 0x401f834c>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_src_bt_cfg4: IOMUXC_GPIO_B0_08_SRC_BT_CFG4 { + pinmux = <0x401f815c 6 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexio2_flexio09: IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 { + pinmux = <0x401f8160 4 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexpwm2_pwmb1: IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8160 2 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio2_io09: IOMUXC_GPIO_B0_09_GPIO2_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio7_io09: IOMUXC_GPIO_B0_09_GPIO7_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lpuart3_rx: IOMUXC_GPIO_B0_09_LPUART3_RX { + pinmux = <0x401f8160 3 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_qtimer4_timer0: IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 { + pinmux = <0x401f8160 1 0x0 0 0x401f8350>; + gpr = <0x400ac018 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_src_bt_cfg5: IOMUXC_GPIO_B0_09_SRC_BT_CFG5 { + pinmux = <0x401f8160 6 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexio2_flexio10: IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 { + pinmux = <0x401f8164 4 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f8164 2 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio2_io10: IOMUXC_GPIO_B0_10_GPIO2_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio7_io10: IOMUXC_GPIO_B0_10_GPIO7_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_qtimer4_timer1: IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 { + pinmux = <0x401f8164 1 0x0 0 0x401f8354>; + gpr = <0x400ac018 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_sai1_tx_data3: IOMUXC_GPIO_B0_10_SAI1_TX_DATA3 { + pinmux = <0x401f8164 3 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_src_bt_cfg6: IOMUXC_GPIO_B0_10_SRC_BT_CFG6 { + pinmux = <0x401f8164 6 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexio2_flexio11: IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 { + pinmux = <0x401f8168 4 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8168 2 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio2_io11: IOMUXC_GPIO_B0_11_GPIO2_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio7_io11: IOMUXC_GPIO_B0_11_GPIO7_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_qtimer4_timer2: IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 { + pinmux = <0x401f8168 1 0x0 0 0x401f8358>; + gpr = <0x400ac018 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_sai1_tx_data2: IOMUXC_GPIO_B0_11_SAI1_TX_DATA2 { + pinmux = <0x401f8168 3 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_src_bt_cfg7: IOMUXC_GPIO_B0_11_SRC_BT_CFG7 { + pinmux = <0x401f8168 6 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_arm_trace_clk: IOMUXC_GPIO_B0_12_ARM_TRACE_CLK { + pinmux = <0x401f816c 2 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_flexio2_flexio12: IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 { + pinmux = <0x401f816c 4 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio2_io12: IOMUXC_GPIO_B0_12_GPIO2_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio7_io12: IOMUXC_GPIO_B0_12_GPIO7_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_sai1_tx_data1: IOMUXC_GPIO_B0_12_SAI1_TX_DATA1 { + pinmux = <0x401f816c 3 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_src_bt_cfg8: IOMUXC_GPIO_B0_12_SRC_BT_CFG8 { + pinmux = <0x401f816c 6 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_in10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_IN10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_inout10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_arm_trace_swo: IOMUXC_GPIO_B0_13_ARM_TRACE_SWO { + pinmux = <0x401f8170 2 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_flexio2_flexio13: IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 { + pinmux = <0x401f8170 4 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio2_io13: IOMUXC_GPIO_B0_13_GPIO2_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio7_io13: IOMUXC_GPIO_B0_13_GPIO7_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_sai1_mclk: IOMUXC_GPIO_B0_13_SAI1_MCLK { + pinmux = <0x401f8170 3 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_src_bt_cfg9: IOMUXC_GPIO_B0_13_SRC_BT_CFG9 { + pinmux = <0x401f8170 6 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_in11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_IN11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_inout11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_flexio2_flexio14: IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 { + pinmux = <0x401f8174 4 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio2_io14: IOMUXC_GPIO_B0_14_GPIO2_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio7_io14: IOMUXC_GPIO_B0_14_GPIO7_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_sai1_rx_sync: IOMUXC_GPIO_B0_14_SAI1_RX_SYNC { + pinmux = <0x401f8174 3 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_src_bt_cfg10: IOMUXC_GPIO_B0_14_SRC_BT_CFG10 { + pinmux = <0x401f8174 6 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_in12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_IN12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_inout12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_flexio2_flexio15: IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 { + pinmux = <0x401f8178 4 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio2_io15: IOMUXC_GPIO_B0_15_GPIO2_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio7_io15: IOMUXC_GPIO_B0_15_GPIO7_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_sai1_rx_bclk: IOMUXC_GPIO_B0_15_SAI1_RX_BCLK { + pinmux = <0x401f8178 3 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_src_bt_cfg11: IOMUXC_GPIO_B0_15_SRC_BT_CFG11 { + pinmux = <0x401f8178 6 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_in13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_IN13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_inout13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio2_flexio16: IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 { + pinmux = <0x401f817c 4 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio3_flexio16: IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 { + pinmux = <0x401f817c 9 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f817c 6 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio2_io16: IOMUXC_GPIO_B1_00_GPIO2_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio7_io16: IOMUXC_GPIO_B1_00_GPIO7_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lpuart4_tx: IOMUXC_GPIO_B1_00_LPUART4_TX { + pinmux = <0x401f817c 2 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_sai1_rx_data0: IOMUXC_GPIO_B1_00_SAI1_RX_DATA0 { + pinmux = <0x401f817c 3 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_in14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f817c 1 0x0 0 0x401f836c>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_inout14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f817c 1 0x0 0 0x401f836c>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio2_flexio17: IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 { + pinmux = <0x401f8180 4 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio3_flexio17: IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 { + pinmux = <0x401f8180 9 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f8180 6 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio2_io17: IOMUXC_GPIO_B1_01_GPIO2_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio7_io17: IOMUXC_GPIO_B1_01_GPIO7_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lpuart4_rx: IOMUXC_GPIO_B1_01_LPUART4_RX { + pinmux = <0x401f8180 2 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_sai1_tx_data0: IOMUXC_GPIO_B1_01_SAI1_TX_DATA0 { + pinmux = <0x401f8180 3 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_in15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8180 1 0x0 0 0x401f8370>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_inout15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8180 1 0x0 0 0x401f8370>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio2_flexio18: IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 { + pinmux = <0x401f8184 4 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio3_flexio18: IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 { + pinmux = <0x401f8184 9 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f8184 6 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio2_io18: IOMUXC_GPIO_B1_02_GPIO2_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio7_io18: IOMUXC_GPIO_B1_02_GPIO7_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lpspi3_pcs2: IOMUXC_GPIO_B1_02_LPSPI3_PCS2 { + pinmux = <0x401f8184 2 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_sai1_tx_bclk: IOMUXC_GPIO_B1_02_SAI1_TX_BCLK { + pinmux = <0x401f8184 3 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_in16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8184 1 0x0 0 0x401f8374>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_inout16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8184 1 0x0 0 0x401f8374>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio2_flexio19: IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 { + pinmux = <0x401f8188 4 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio3_flexio19: IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 { + pinmux = <0x401f8188 9 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f8188 6 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio2_io19: IOMUXC_GPIO_B1_03_GPIO2_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio7_io19: IOMUXC_GPIO_B1_03_GPIO7_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lpspi3_pcs1: IOMUXC_GPIO_B1_03_LPSPI3_PCS1 { + pinmux = <0x401f8188 2 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_sai1_tx_sync: IOMUXC_GPIO_B1_03_SAI1_TX_SYNC { + pinmux = <0x401f8188 3 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_in17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f8188 1 0x0 0 0x401f8378>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_inout17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8188 1 0x0 0 0x401f8378>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_enet_rx_data0: IOMUXC_GPIO_B1_04_ENET_RX_DATA0 { + pinmux = <0x401f818c 3 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio2_flexio20: IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 { + pinmux = <0x401f818c 4 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio3_flexio20: IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 { + pinmux = <0x401f818c 9 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio2_io20: IOMUXC_GPIO_B1_04_GPIO2_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio7_io20: IOMUXC_GPIO_B1_04_GPIO7_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpt1_clk: IOMUXC_GPIO_B1_04_GPT1_CLK { + pinmux = <0x401f818c 8 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lpspi3_pcs0: IOMUXC_GPIO_B1_04_LPSPI3_PCS0 { + pinmux = <0x401f818c 1 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_enet_rx_data1: IOMUXC_GPIO_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f8190 3 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio2_flexio21: IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 { + pinmux = <0x401f8190 4 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio3_flexio21: IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 { + pinmux = <0x401f8190 9 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio2_io21: IOMUXC_GPIO_B1_05_GPIO2_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio7_io21: IOMUXC_GPIO_B1_05_GPIO7_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpt1_capture1: IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 { + pinmux = <0x401f8190 8 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lpspi3_sdi: IOMUXC_GPIO_B1_05_LPSPI3_SDI { + pinmux = <0x401f8190 1 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_enet_rx_en: IOMUXC_GPIO_B1_06_ENET_RX_EN { + pinmux = <0x401f8194 3 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio2_flexio22: IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 { + pinmux = <0x401f8194 4 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio3_flexio22: IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 { + pinmux = <0x401f8194 9 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio2_io22: IOMUXC_GPIO_B1_06_GPIO2_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio7_io22: IOMUXC_GPIO_B1_06_GPIO7_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpt1_capture2: IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 { + pinmux = <0x401f8194 8 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lpspi3_sdo: IOMUXC_GPIO_B1_06_LPSPI3_SDO { + pinmux = <0x401f8194 1 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_enet_tx_data0: IOMUXC_GPIO_B1_07_ENET_TX_DATA0 { + pinmux = <0x401f8198 3 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio2_flexio23: IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 { + pinmux = <0x401f8198 4 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio3_flexio23: IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 { + pinmux = <0x401f8198 9 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio2_io23: IOMUXC_GPIO_B1_07_GPIO2_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio7_io23: IOMUXC_GPIO_B1_07_GPIO7_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpt1_compare1: IOMUXC_GPIO_B1_07_GPT1_COMPARE1 { + pinmux = <0x401f8198 8 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lpspi3_sck: IOMUXC_GPIO_B1_07_LPSPI3_SCK { + pinmux = <0x401f8198 1 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_enet_tx_data1: IOMUXC_GPIO_B1_08_ENET_TX_DATA1 { + pinmux = <0x401f819c 3 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexcan2_tx: IOMUXC_GPIO_B1_08_FLEXCAN2_TX { + pinmux = <0x401f819c 6 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio2_flexio24: IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 { + pinmux = <0x401f819c 4 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio3_flexio24: IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 { + pinmux = <0x401f819c 9 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio2_io24: IOMUXC_GPIO_B1_08_GPIO2_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio7_io24: IOMUXC_GPIO_B1_08_GPIO7_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpt1_compare2: IOMUXC_GPIO_B1_08_GPT1_COMPARE2 { + pinmux = <0x401f819c 8 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_qtimer1_timer3: IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 { + pinmux = <0x401f819c 1 0x0 0 0x401f838c>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_enet_tx_en: IOMUXC_GPIO_B1_09_ENET_TX_EN { + pinmux = <0x401f81a0 3 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexcan2_rx: IOMUXC_GPIO_B1_09_FLEXCAN2_RX { + pinmux = <0x401f81a0 6 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio2_flexio25: IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 { + pinmux = <0x401f81a0 4 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio3_flexio25: IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 { + pinmux = <0x401f81a0 9 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio2_io25: IOMUXC_GPIO_B1_09_GPIO2_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio7_io25: IOMUXC_GPIO_B1_09_GPIO7_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpt1_compare3: IOMUXC_GPIO_B1_09_GPT1_COMPARE3 { + pinmux = <0x401f81a0 8 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_qtimer2_timer3: IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 { + pinmux = <0x401f81a0 1 0x0 0 0x401f8390>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_ref_clk: IOMUXC_GPIO_B1_10_ENET_REF_CLK { + pinmux = <0x401f81a4 6 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_tx_clk: IOMUXC_GPIO_B1_10_ENET_TX_CLK { + pinmux = <0x401f81a4 3 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio2_flexio26: IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 { + pinmux = <0x401f81a4 4 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio3_flexio26: IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 { + pinmux = <0x401f81a4 9 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio2_io26: IOMUXC_GPIO_B1_10_GPIO2_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio7_io26: IOMUXC_GPIO_B1_10_GPIO7_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_qtimer3_timer3: IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 { + pinmux = <0x401f81a4 1 0x0 0 0x401f8394>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_enet_rx_er: IOMUXC_GPIO_B1_11_ENET_RX_ER { + pinmux = <0x401f81a8 3 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio2_flexio27: IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 { + pinmux = <0x401f81a8 4 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio3_flexio27: IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 { + pinmux = <0x401f81a8 9 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio2_io27: IOMUXC_GPIO_B1_11_GPIO2_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio7_io27: IOMUXC_GPIO_B1_11_GPIO7_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lpspi3_pcs3: IOMUXC_GPIO_B1_11_LPSPI3_PCS3 { + pinmux = <0x401f81a8 6 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_qtimer4_timer3: IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 { + pinmux = <0x401f81a8 1 0x0 0 0x401f8398>; + gpr = <0x400ac018 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_enet_1588_event0_in: IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN { + pinmux = <0x401f81ac 3 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio2_flexio28: IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 { + pinmux = <0x401f81ac 4 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio3_flexio28: IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 { + pinmux = <0x401f81ac 9 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio2_io28: IOMUXC_GPIO_B1_12_GPIO2_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio7_io28: IOMUXC_GPIO_B1_12_GPIO7_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_lpuart5_tx: IOMUXC_GPIO_B1_12_LPUART5_TX { + pinmux = <0x401f81ac 1 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_usdhc1_cd_b: IOMUXC_GPIO_B1_12_USDHC1_CD_B { + pinmux = <0x401f81ac 6 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_enet_1588_event0_out: IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT { + pinmux = <0x401f81b0 3 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio2_flexio29: IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 { + pinmux = <0x401f81b0 4 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio3_flexio29: IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 { + pinmux = <0x401f81b0 9 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio2_io29: IOMUXC_GPIO_B1_13_GPIO2_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio7_io29: IOMUXC_GPIO_B1_13_GPIO7_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_lpuart5_rx: IOMUXC_GPIO_B1_13_LPUART5_RX { + pinmux = <0x401f81b0 1 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_semc_dqs4: IOMUXC_GPIO_B1_13_SEMC_DQS4 { + pinmux = <0x401f81b0 8 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_usdhc1_wp: IOMUXC_GPIO_B1_13_USDHC1_WP { + pinmux = <0x401f81b0 6 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_wdog1_b: IOMUXC_GPIO_B1_13_WDOG1_B { + pinmux = <0x401f81b0 0 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet_mdc: IOMUXC_GPIO_B1_14_ENET_MDC { + pinmux = <0x401f81b4 0 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio2_flexio30: IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 { + pinmux = <0x401f81b4 4 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio3_flexio30: IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 { + pinmux = <0x401f81b4 9 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexpwm4_pwma2: IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA2 { + pinmux = <0x401f81b4 1 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio2_io30: IOMUXC_GPIO_B1_14_GPIO2_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio7_io30: IOMUXC_GPIO_B1_14_GPIO7_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_usdhc1_vselect: IOMUXC_GPIO_B1_14_USDHC1_VSELECT { + pinmux = <0x401f81b4 6 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_xbar1_xbar_in02: IOMUXC_GPIO_B1_14_XBAR1_XBAR_IN02 { + pinmux = <0x401f81b4 3 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet_mdio: IOMUXC_GPIO_B1_15_ENET_MDIO { + pinmux = <0x401f81b8 0 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio2_flexio31: IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 { + pinmux = <0x401f81b8 4 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio3_flexio31: IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 { + pinmux = <0x401f81b8 9 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexpwm4_pwma3: IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA3 { + pinmux = <0x401f81b8 1 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio2_io31: IOMUXC_GPIO_B1_15_GPIO2_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio7_io31: IOMUXC_GPIO_B1_15_GPIO7_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_usdhc1_reset_b: IOMUXC_GPIO_B1_15_USDHC1_RESET_B { + pinmux = <0x401f81b8 6 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_xbar1_xbar_in03: IOMUXC_GPIO_B1_15_XBAR1_XBAR_IN03 { + pinmux = <0x401f81b8 3 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexio1_flexio00: IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8014 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexpwm4_pwma0: IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA0 { + pinmux = <0x401f8014 1 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio4_io00: IOMUXC_GPIO_EMC_00_GPIO4_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio9_io00: IOMUXC_GPIO_EMC_00_GPIO9_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 2 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_xbar1_xbar_in02: IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 { + pinmux = <0x401f8014 3 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexio1_flexio01: IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8018 4 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexpwm4_pwmb0: IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB0 { + pinmux = <0x401f8018 1 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio4_io01: IOMUXC_GPIO_EMC_01_GPIO4_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio9_io01: IOMUXC_GPIO_EMC_01_GPIO9_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 2 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_xbar1_xbar_in03: IOMUXC_GPIO_EMC_01_XBAR1_XBAR_IN03 { + pinmux = <0x401f8018 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexio1_flexio02: IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 { + pinmux = <0x401f801c 4 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexpwm4_pwma1: IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA1 { + pinmux = <0x401f801c 1 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio4_io02: IOMUXC_GPIO_EMC_02_GPIO4_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio9_io02: IOMUXC_GPIO_EMC_02_GPIO9_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 2 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_in04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_IN04 { + pinmux = <0x401f801c 3 0x0 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f801c 3 0x0 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexio1_flexio03: IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 { + pinmux = <0x401f8020 4 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexpwm4_pwmb1: IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB1 { + pinmux = <0x401f8020 1 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio4_io03: IOMUXC_GPIO_EMC_03_GPIO4_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio9_io03: IOMUXC_GPIO_EMC_03_GPIO9_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 2 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_in05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_IN05 { + pinmux = <0x401f8020 3 0x0 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8020 3 0x0 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio04: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8024 4 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexpwm4_pwma2: IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA2 { + pinmux = <0x401f8024 1 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio4_io04: IOMUXC_GPIO_EMC_04_GPIO4_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio9_io04: IOMUXC_GPIO_EMC_04_GPIO9_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_data: IOMUXC_GPIO_EMC_04_SAI2_TX_DATA { + pinmux = <0x401f8024 2 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN06 { + pinmux = <0x401f8024 3 0x0 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f8024 3 0x0 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio05: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8028 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexpwm4_pwmb2: IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB2 { + pinmux = <0x401f8028 1 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio4_io05: IOMUXC_GPIO_EMC_05_GPIO4_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio9_io05: IOMUXC_GPIO_EMC_05_GPIO9_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 2 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN07 { + pinmux = <0x401f8028 3 0x0 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8028 3 0x0 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio06: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 { + pinmux = <0x401f802c 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexpwm2_pwma0: IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f802c 1 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio4_io06: IOMUXC_GPIO_EMC_06_GPIO4_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio9_io06: IOMUXC_GPIO_EMC_06_GPIO9_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_bclk: IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK { + pinmux = <0x401f802c 2 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN08 { + pinmux = <0x401f802c 3 0x0 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f802c 3 0x0 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio07: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 { + pinmux = <0x401f8030 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8030 1 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio4_io07: IOMUXC_GPIO_EMC_07_GPIO4_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio9_io07: IOMUXC_GPIO_EMC_07_GPIO9_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_mclk: IOMUXC_GPIO_EMC_07_SAI2_MCLK { + pinmux = <0x401f8030 2 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN09 { + pinmux = <0x401f8030 3 0x0 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8030 3 0x0 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio08: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8034 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexpwm2_pwma1: IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f8034 1 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio4_io08: IOMUXC_GPIO_EMC_08_GPIO4_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio9_io08: IOMUXC_GPIO_EMC_08_GPIO9_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 2 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN17 { + pinmux = <0x401f8034 3 0x0 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8034 3 0x0 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_tx: IOMUXC_GPIO_EMC_09_FLEXCAN2_TX { + pinmux = <0x401f8038 3 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio09: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8038 4 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8038 1 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexspi2_b_ss1_b: IOMUXC_GPIO_EMC_09_FLEXSPI2_B_SS1_B { + pinmux = <0x401f8038 8 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio4_io09: IOMUXC_GPIO_EMC_09_GPIO4_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio9_io09: IOMUXC_GPIO_EMC_09_GPIO9_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_sync: IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC { + pinmux = <0x401f8038 2 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_addr00: IOMUXC_GPIO_EMC_09_SEMC_ADDR00 { + pinmux = <0x401f8038 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexcan2_rx: IOMUXC_GPIO_EMC_10_FLEXCAN2_RX { + pinmux = <0x401f803c 3 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexio1_flexio10: IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 { + pinmux = <0x401f803c 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwma2: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f803c 1 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_10_FLEXSPI2_B_SS0_B { + pinmux = <0x401f803c 8 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio4_io10: IOMUXC_GPIO_EMC_10_GPIO4_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio9_io10: IOMUXC_GPIO_EMC_10_GPIO9_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai2_rx_bclk: IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK { + pinmux = <0x401f803c 2 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_addr01: IOMUXC_GPIO_EMC_10_SEMC_ADDR01 { + pinmux = <0x401f803c 0 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexio1_flexio11: IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 { + pinmux = <0x401f8040 4 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8040 1 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexspi2_b_dqs: IOMUXC_GPIO_EMC_11_FLEXSPI2_B_DQS { + pinmux = <0x401f8040 8 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio4_io11: IOMUXC_GPIO_EMC_11_GPIO4_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio9_io11: IOMUXC_GPIO_EMC_11_GPIO9_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_sda: IOMUXC_GPIO_EMC_11_LPI2C4_SDA { + pinmux = <0x401f8040 2 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_addr02: IOMUXC_GPIO_EMC_11_SEMC_ADDR02 { + pinmux = <0x401f8040 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_usdhc2_reset_b: IOMUXC_GPIO_EMC_11_USDHC2_RESET_B { + pinmux = <0x401f8040 3 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm1_pwma3: IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f8044 4 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexspi2_b_sclk: IOMUXC_GPIO_EMC_12_FLEXSPI2_B_SCLK { + pinmux = <0x401f8044 8 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio4_io12: IOMUXC_GPIO_EMC_12_GPIO4_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio9_io12: IOMUXC_GPIO_EMC_12_GPIO9_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpi2c4_scl: IOMUXC_GPIO_EMC_12_LPI2C4_SCL { + pinmux = <0x401f8044 2 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_addr03: IOMUXC_GPIO_EMC_12_SEMC_ADDR03 { + pinmux = <0x401f8044 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_usdhc1_wp: IOMUXC_GPIO_EMC_12_USDHC1_WP { + pinmux = <0x401f8044 3 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in24: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN24 { + pinmux = <0x401f8044 1 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8048 4 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexspi2_b_data0: IOMUXC_GPIO_EMC_13_FLEXSPI2_B_DATA0 { + pinmux = <0x401f8048 8 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio4_io13: IOMUXC_GPIO_EMC_13_GPIO4_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio9_io13: IOMUXC_GPIO_EMC_13_GPIO9_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart3_tx: IOMUXC_GPIO_EMC_13_LPUART3_TX { + pinmux = <0x401f8048 2 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_mqs_right: IOMUXC_GPIO_EMC_13_MQS_RIGHT { + pinmux = <0x401f8048 3 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_addr04: IOMUXC_GPIO_EMC_13_SEMC_ADDR04 { + pinmux = <0x401f8048 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in25: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN25 { + pinmux = <0x401f8048 1 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_flexspi2_b_data1: IOMUXC_GPIO_EMC_14_FLEXSPI2_B_DATA1 { + pinmux = <0x401f804c 8 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio4_io14: IOMUXC_GPIO_EMC_14_GPIO4_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio9_io14: IOMUXC_GPIO_EMC_14_GPIO9_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart3_rx: IOMUXC_GPIO_EMC_14_LPUART3_RX { + pinmux = <0x401f804c 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_mqs_left: IOMUXC_GPIO_EMC_14_MQS_LEFT { + pinmux = <0x401f804c 3 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_addr05: IOMUXC_GPIO_EMC_14_SEMC_ADDR05 { + pinmux = <0x401f804c 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN19 { + pinmux = <0x401f804c 1 0x0 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f804c 1 0x0 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_flexspi2_b_data2: IOMUXC_GPIO_EMC_15_FLEXSPI2_B_DATA2 { + pinmux = <0x401f8050 8 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio4_io15: IOMUXC_GPIO_EMC_15_GPIO4_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio9_io15: IOMUXC_GPIO_EMC_15_GPIO9_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart3_cts_b: IOMUXC_GPIO_EMC_15_LPUART3_CTS_B { + pinmux = <0x401f8050 2 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_qtimer3_timer0: IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 { + pinmux = <0x401f8050 4 0x0 0 0x401f8240>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr06: IOMUXC_GPIO_EMC_15_SEMC_ADDR06 { + pinmux = <0x401f8050 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_spdif_out: IOMUXC_GPIO_EMC_15_SPDIF_OUT { + pinmux = <0x401f8050 3 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in20: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN20 { + pinmux = <0x401f8050 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_flexspi2_b_data3: IOMUXC_GPIO_EMC_16_FLEXSPI2_B_DATA3 { + pinmux = <0x401f8054 8 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio4_io16: IOMUXC_GPIO_EMC_16_GPIO4_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio9_io16: IOMUXC_GPIO_EMC_16_GPIO9_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_lpuart3_rts_b: IOMUXC_GPIO_EMC_16_LPUART3_RTS_B { + pinmux = <0x401f8054 2 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_qtimer3_timer1: IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 { + pinmux = <0x401f8054 4 0x0 0 0x401f8244>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr07: IOMUXC_GPIO_EMC_16_SEMC_ADDR07 { + pinmux = <0x401f8054 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_spdif_in: IOMUXC_GPIO_EMC_16_SPDIF_IN { + pinmux = <0x401f8054 3 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_xbar1_xbar_in21: IOMUXC_GPIO_EMC_16_XBAR1_XBAR_IN21 { + pinmux = <0x401f8054 1 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexcan1_tx: IOMUXC_GPIO_EMC_17_FLEXCAN1_TX { + pinmux = <0x401f8058 3 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexpwm4_pwma3: IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA3 { + pinmux = <0x401f8058 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio4_io17: IOMUXC_GPIO_EMC_17_GPIO4_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio9_io17: IOMUXC_GPIO_EMC_17_GPIO9_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_lpuart4_cts_b: IOMUXC_GPIO_EMC_17_LPUART4_CTS_B { + pinmux = <0x401f8058 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_qtimer3_timer2: IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 { + pinmux = <0x401f8058 4 0x0 0 0x401f8248>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr08: IOMUXC_GPIO_EMC_17_SEMC_ADDR08 { + pinmux = <0x401f8058 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexcan1_rx: IOMUXC_GPIO_EMC_18_FLEXCAN1_RX { + pinmux = <0x401f805c 3 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexpwm4_pwmb3: IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB3 { + pinmux = <0x401f805c 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio4_io18: IOMUXC_GPIO_EMC_18_GPIO4_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio9_io18: IOMUXC_GPIO_EMC_18_GPIO9_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpuart4_rts_b: IOMUXC_GPIO_EMC_18_LPUART4_RTS_B { + pinmux = <0x401f805c 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_qtimer3_timer3: IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 { + pinmux = <0x401f805c 4 0x0 0 0x401f824c>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr09: IOMUXC_GPIO_EMC_18_SEMC_ADDR09 { + pinmux = <0x401f805c 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_snvs_vio_5_ctl: IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL { + pinmux = <0x401f805c 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_enet_rx_data1: IOMUXC_GPIO_EMC_19_ENET_RX_DATA1 { + pinmux = <0x401f8060 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexpwm2_pwma3: IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA3 { + pinmux = <0x401f8060 1 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio4_io19: IOMUXC_GPIO_EMC_19_GPIO4_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio9_io19: IOMUXC_GPIO_EMC_19_GPIO9_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpuart4_tx: IOMUXC_GPIO_EMC_19_LPUART4_TX { + pinmux = <0x401f8060 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_qtimer2_timer0: IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 { + pinmux = <0x401f8060 4 0x0 0 0x401f8250>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr11: IOMUXC_GPIO_EMC_19_SEMC_ADDR11 { + pinmux = <0x401f8060 0 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_snvs_vio_5_b: IOMUXC_GPIO_EMC_19_SNVS_VIO_5_B { + pinmux = <0x401f8060 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_enet_rx_data0: IOMUXC_GPIO_EMC_20_ENET_RX_DATA0 { + pinmux = <0x401f8064 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB3 { + pinmux = <0x401f8064 1 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio4_io20: IOMUXC_GPIO_EMC_20_GPIO4_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio9_io20: IOMUXC_GPIO_EMC_20_GPIO9_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart4_rx: IOMUXC_GPIO_EMC_20_LPUART4_RX { + pinmux = <0x401f8064 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_qtimer2_timer1: IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 { + pinmux = <0x401f8064 4 0x0 0 0x401f8254>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr12: IOMUXC_GPIO_EMC_20_SEMC_ADDR12 { + pinmux = <0x401f8064 0 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_enet_tx_data1: IOMUXC_GPIO_EMC_21_ENET_TX_DATA1 { + pinmux = <0x401f8068 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm3_pwma3: IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA3 { + pinmux = <0x401f8068 1 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio4_io21: IOMUXC_GPIO_EMC_21_GPIO4_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio9_io21: IOMUXC_GPIO_EMC_21_GPIO9_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpi2c3_sda: IOMUXC_GPIO_EMC_21_LPI2C3_SDA { + pinmux = <0x401f8068 2 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_qtimer2_timer2: IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 { + pinmux = <0x401f8068 4 0x0 0 0x401f8258>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_ba0: IOMUXC_GPIO_EMC_21_SEMC_BA0 { + pinmux = <0x401f8068 0 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_enet_tx_data0: IOMUXC_GPIO_EMC_22_ENET_TX_DATA0 { + pinmux = <0x401f806c 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm3_pwmb3: IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB3 { + pinmux = <0x401f806c 1 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexspi2_a_ss1_b: IOMUXC_GPIO_EMC_22_FLEXSPI2_A_SS1_B { + pinmux = <0x401f806c 8 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio4_io22: IOMUXC_GPIO_EMC_22_GPIO4_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio9_io22: IOMUXC_GPIO_EMC_22_GPIO9_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpi2c3_scl: IOMUXC_GPIO_EMC_22_LPI2C3_SCL { + pinmux = <0x401f806c 2 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_qtimer2_timer3: IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 { + pinmux = <0x401f806c 4 0x0 0 0x401f825c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_ba1: IOMUXC_GPIO_EMC_22_SEMC_BA1 { + pinmux = <0x401f806c 0 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_enet_rx_en: IOMUXC_GPIO_EMC_23_ENET_RX_EN { + pinmux = <0x401f8070 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwma0: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA0 { + pinmux = <0x401f8070 1 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexspi2_a_dqs: IOMUXC_GPIO_EMC_23_FLEXSPI2_A_DQS { + pinmux = <0x401f8070 8 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio4_io23: IOMUXC_GPIO_EMC_23_GPIO4_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio9_io23: IOMUXC_GPIO_EMC_23_GPIO9_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpt1_capture2: IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 { + pinmux = <0x401f8070 4 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart5_tx: IOMUXC_GPIO_EMC_23_LPUART5_TX { + pinmux = <0x401f8070 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr10: IOMUXC_GPIO_EMC_23_SEMC_ADDR10 { + pinmux = <0x401f8070 0 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_enet_tx_en: IOMUXC_GPIO_EMC_24_ENET_TX_EN { + pinmux = <0x401f8074 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB0 { + pinmux = <0x401f8074 1 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_24_FLEXSPI2_A_SS0_B { + pinmux = <0x401f8074 8 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio4_io24: IOMUXC_GPIO_EMC_24_GPIO4_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio9_io24: IOMUXC_GPIO_EMC_24_GPIO9_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpt1_capture1: IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 { + pinmux = <0x401f8074 4 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart5_rx: IOMUXC_GPIO_EMC_24_LPUART5_RX { + pinmux = <0x401f8074 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_cas: IOMUXC_GPIO_EMC_24_SEMC_CAS { + pinmux = <0x401f8074 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_ref_clk: IOMUXC_GPIO_EMC_25_ENET_REF_CLK { + pinmux = <0x401f8078 4 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_tx_clk: IOMUXC_GPIO_EMC_25_ENET_TX_CLK { + pinmux = <0x401f8078 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwma1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA1 { + pinmux = <0x401f8078 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexspi2_a_sclk: IOMUXC_GPIO_EMC_25_FLEXSPI2_A_SCLK { + pinmux = <0x401f8078 8 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio4_io25: IOMUXC_GPIO_EMC_25_GPIO4_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio9_io25: IOMUXC_GPIO_EMC_25_GPIO9_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart6_tx: IOMUXC_GPIO_EMC_25_LPUART6_TX { + pinmux = <0x401f8078 2 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_ras: IOMUXC_GPIO_EMC_25_SEMC_RAS { + pinmux = <0x401f8078 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_enet_rx_er: IOMUXC_GPIO_EMC_26_ENET_RX_ER { + pinmux = <0x401f807c 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio12: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 { + pinmux = <0x401f807c 4 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB1 { + pinmux = <0x401f807c 1 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexspi2_a_data0: IOMUXC_GPIO_EMC_26_FLEXSPI2_A_DATA0 { + pinmux = <0x401f807c 8 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio4_io26: IOMUXC_GPIO_EMC_26_GPIO4_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio9_io26: IOMUXC_GPIO_EMC_26_GPIO9_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart6_rx: IOMUXC_GPIO_EMC_26_LPUART6_RX { + pinmux = <0x401f807c 2 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_clk: IOMUXC_GPIO_EMC_26_SEMC_CLK { + pinmux = <0x401f807c 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio13: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8080 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwma2: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA2 { + pinmux = <0x401f8080 1 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexspi2_a_data1: IOMUXC_GPIO_EMC_27_FLEXSPI2_A_DATA1 { + pinmux = <0x401f8080 8 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio4_io27: IOMUXC_GPIO_EMC_27_GPIO4_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio9_io27: IOMUXC_GPIO_EMC_27_GPIO9_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpspi1_sck: IOMUXC_GPIO_EMC_27_LPSPI1_SCK { + pinmux = <0x401f8080 3 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart5_rts_b: IOMUXC_GPIO_EMC_27_LPUART5_RTS_B { + pinmux = <0x401f8080 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_cke: IOMUXC_GPIO_EMC_27_SEMC_CKE { + pinmux = <0x401f8080 0 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexio1_flexio14: IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8084 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB2 { + pinmux = <0x401f8084 1 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexspi2_a_data2: IOMUXC_GPIO_EMC_28_FLEXSPI2_A_DATA2 { + pinmux = <0x401f8084 8 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio4_io28: IOMUXC_GPIO_EMC_28_GPIO4_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio9_io28: IOMUXC_GPIO_EMC_28_GPIO9_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpspi1_sdo: IOMUXC_GPIO_EMC_28_LPSPI1_SDO { + pinmux = <0x401f8084 3 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpuart5_cts_b: IOMUXC_GPIO_EMC_28_LPUART5_CTS_B { + pinmux = <0x401f8084 2 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_we: IOMUXC_GPIO_EMC_28_SEMC_WE { + pinmux = <0x401f8084 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexio1_flexio15: IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 { + pinmux = <0x401f8088 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm3_pwma0: IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA0 { + pinmux = <0x401f8088 1 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexspi2_a_data3: IOMUXC_GPIO_EMC_29_FLEXSPI2_A_DATA3 { + pinmux = <0x401f8088 8 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio4_io29: IOMUXC_GPIO_EMC_29_GPIO4_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio9_io29: IOMUXC_GPIO_EMC_29_GPIO9_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpspi1_sdi: IOMUXC_GPIO_EMC_29_LPSPI1_SDI { + pinmux = <0x401f8088 3 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpuart6_rts_b: IOMUXC_GPIO_EMC_29_LPUART6_RTS_B { + pinmux = <0x401f8088 2 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cs0: IOMUXC_GPIO_EMC_29_SEMC_CS0 { + pinmux = <0x401f8088 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm3_pwmb0: IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB0 { + pinmux = <0x401f808c 1 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio4_io30: IOMUXC_GPIO_EMC_30_GPIO4_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio9_io30: IOMUXC_GPIO_EMC_30_GPIO9_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpspi1_pcs0: IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 { + pinmux = <0x401f808c 3 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart6_cts_b: IOMUXC_GPIO_EMC_30_LPUART6_CTS_B { + pinmux = <0x401f808c 2 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_data08: IOMUXC_GPIO_EMC_30_SEMC_DATA08 { + pinmux = <0x401f808c 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm3_pwma1: IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA1 { + pinmux = <0x401f8090 1 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio4_io31: IOMUXC_GPIO_EMC_31_GPIO4_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio9_io31: IOMUXC_GPIO_EMC_31_GPIO9_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpspi1_pcs1: IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 { + pinmux = <0x401f8090 3 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart7_tx: IOMUXC_GPIO_EMC_31_LPUART7_TX { + pinmux = <0x401f8090 2 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_data09: IOMUXC_GPIO_EMC_31_SEMC_DATA09 { + pinmux = <0x401f8090 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ccm_pmic_rdy: IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY { + pinmux = <0x401f8094 3 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_flexpwm3_pwmb1: IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB1 { + pinmux = <0x401f8094 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io18: IOMUXC_GPIO_EMC_32_GPIO3_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio8_io18: IOMUXC_GPIO_EMC_32_GPIO8_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart7_rx: IOMUXC_GPIO_EMC_32_LPUART7_RX { + pinmux = <0x401f8094 2 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data10: IOMUXC_GPIO_EMC_32_SEMC_DATA10 { + pinmux = <0x401f8094 0 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_flexpwm3_pwma2: IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA2 { + pinmux = <0x401f8098 1 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io19: IOMUXC_GPIO_EMC_33_GPIO3_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio8_io19: IOMUXC_GPIO_EMC_33_GPIO8_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_rx_data: IOMUXC_GPIO_EMC_33_SAI3_RX_DATA { + pinmux = <0x401f8098 3 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data11: IOMUXC_GPIO_EMC_33_SEMC_DATA11 { + pinmux = <0x401f8098 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_usdhc1_reset_b: IOMUXC_GPIO_EMC_33_USDHC1_RESET_B { + pinmux = <0x401f8098 2 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_flexpwm3_pwmb2: IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB2 { + pinmux = <0x401f809c 1 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io20: IOMUXC_GPIO_EMC_34_GPIO3_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio8_io20: IOMUXC_GPIO_EMC_34_GPIO8_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_rx_sync: IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC { + pinmux = <0x401f809c 3 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data12: IOMUXC_GPIO_EMC_34_SEMC_DATA12 { + pinmux = <0x401f809c 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_usdhc1_vselect: IOMUXC_GPIO_EMC_34_USDHC1_VSELECT { + pinmux = <0x401f809c 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io21: IOMUXC_GPIO_EMC_35_GPIO3_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio8_io21: IOMUXC_GPIO_EMC_35_GPIO8_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpt1_compare1: IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 { + pinmux = <0x401f80a0 2 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_sai3_rx_bclk: IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK { + pinmux = <0x401f80a0 3 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data13: IOMUXC_GPIO_EMC_35_SEMC_DATA13 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc1_cd_b: IOMUXC_GPIO_EMC_35_USDHC1_CD_B { + pinmux = <0x401f80a0 6 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_in18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_IN18 { + pinmux = <0x401f80a0 1 0x0 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80a0 1 0x0 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexcan3_tx: IOMUXC_GPIO_EMC_36_FLEXCAN3_TX { + pinmux = <0x401f80a4 9 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io22: IOMUXC_GPIO_EMC_36_GPIO3_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio8_io22: IOMUXC_GPIO_EMC_36_GPIO8_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpt1_compare2: IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 { + pinmux = <0x401f80a4 2 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_sai3_tx_data: IOMUXC_GPIO_EMC_36_SAI3_TX_DATA { + pinmux = <0x401f80a4 3 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data14: IOMUXC_GPIO_EMC_36_SEMC_DATA14 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 6 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_xbar1_xbar_in22: IOMUXC_GPIO_EMC_36_XBAR1_XBAR_IN22 { + pinmux = <0x401f80a4 1 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexcan3_rx: IOMUXC_GPIO_EMC_37_FLEXCAN3_RX { + pinmux = <0x401f80a8 9 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io23: IOMUXC_GPIO_EMC_37_GPIO3_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio8_io23: IOMUXC_GPIO_EMC_37_GPIO8_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpt1_compare3: IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 { + pinmux = <0x401f80a8 2 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_sai3_mclk: IOMUXC_GPIO_EMC_37_SAI3_MCLK { + pinmux = <0x401f80a8 3 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data15: IOMUXC_GPIO_EMC_37_SEMC_DATA15 { + pinmux = <0x401f80a8 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc2_wp: IOMUXC_GPIO_EMC_37_USDHC2_WP { + pinmux = <0x401f80a8 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_xbar1_xbar_in23: IOMUXC_GPIO_EMC_37_XBAR1_XBAR_IN23 { + pinmux = <0x401f80a8 1 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm1_pwma3: IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA3 { + pinmux = <0x401f80ac 1 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io24: IOMUXC_GPIO_EMC_38_GPIO3_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio8_io24: IOMUXC_GPIO_EMC_38_GPIO8_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart8_tx: IOMUXC_GPIO_EMC_38_LPUART8_TX { + pinmux = <0x401f80ac 2 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_sai3_tx_bclk: IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK { + pinmux = <0x401f80ac 3 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_dm1: IOMUXC_GPIO_EMC_38_SEMC_DM1 { + pinmux = <0x401f80ac 0 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc2_vselect: IOMUXC_GPIO_EMC_38_USDHC2_VSELECT { + pinmux = <0x401f80ac 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB3 { + pinmux = <0x401f80b0 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io25: IOMUXC_GPIO_EMC_39_GPIO3_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio8_io25: IOMUXC_GPIO_EMC_39_GPIO8_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart8_rx: IOMUXC_GPIO_EMC_39_LPUART8_RX { + pinmux = <0x401f80b0 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_sai3_tx_sync: IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC { + pinmux = <0x401f80b0 3 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs: IOMUXC_GPIO_EMC_39_SEMC_DQS { + pinmux = <0x401f80b0 0 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs4: IOMUXC_GPIO_EMC_39_SEMC_DQS4 { + pinmux = <0x401f80b0 9 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usdhc2_cd_b: IOMUXC_GPIO_EMC_39_USDHC2_CD_B { + pinmux = <0x401f80b0 6 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdc: IOMUXC_GPIO_EMC_40_ENET_MDC { + pinmux = <0x401f80b4 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io26: IOMUXC_GPIO_EMC_40_GPIO3_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio8_io26: IOMUXC_GPIO_EMC_40_GPIO8_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt2_capture2: IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 { + pinmux = <0x401f80b4 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_lpspi1_pcs2: IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 { + pinmux = <0x401f80b4 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_clk5: IOMUXC_GPIO_EMC_40_SEMC_CLK5 { + pinmux = <0x401f80b4 9 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_rdy: IOMUXC_GPIO_EMC_40_SEMC_RDY { + pinmux = <0x401f80b4 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usdhc2_reset_b: IOMUXC_GPIO_EMC_40_USDHC2_RESET_B { + pinmux = <0x401f80b4 6 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdio: IOMUXC_GPIO_EMC_41_ENET_MDIO { + pinmux = <0x401f80b8 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io27: IOMUXC_GPIO_EMC_41_GPIO3_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio8_io27: IOMUXC_GPIO_EMC_41_GPIO8_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt2_capture1: IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 { + pinmux = <0x401f80b8 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_lpspi1_pcs3: IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 { + pinmux = <0x401f80b8 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_csx0: IOMUXC_GPIO_EMC_41_SEMC_CSX0 { + pinmux = <0x401f80b8 0 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usdhc1_vselect: IOMUXC_GPIO_EMC_41_USDHC1_VSELECT { + pinmux = <0x401f80b8 6 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexpwm1_pwma0: IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA0 { + pinmux = <0x401f81bc 1 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f81bc 6 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io12: IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio8_io12: IOMUXC_GPIO_SD_B0_00_GPIO8_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f81bc 2 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpspi1_sck: IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK { + pinmux = <0x401f81bc 4 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_semc_dqs4: IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 { + pinmux = <0x401f81bc 9 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_cmd: IOMUXC_GPIO_SD_B0_00_USDHC1_CMD { + pinmux = <0x401f81bc 0 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN04 { + pinmux = <0x401f81bc 3 0x0 0 0x401f83ac>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f81bc 3 0x0 0 0x401f83ac>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexpwm1_pwmb0: IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB0 { + pinmux = <0x401f81c0 1 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f81c0 6 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io13: IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio8_io13: IOMUXC_GPIO_SD_B0_01_GPIO8_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f81c0 2 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 { + pinmux = <0x401f81c0 4 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_clk: IOMUXC_GPIO_SD_B0_01_USDHC1_CLK { + pinmux = <0x401f81c0 0 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN05 { + pinmux = <0x401f81c0 3 0x0 0 0x401f83b0>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f81c0 3 0x0 0 0x401f83b0>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_flexpwm1_pwma1: IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA1 { + pinmux = <0x401f81c4 1 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io14: IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio8_io14: IOMUXC_GPIO_SD_B0_02_GPIO8_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sdo: IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO { + pinmux = <0x401f81c4 4 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart8_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B { + pinmux = <0x401f81c4 2 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_semc_clk5: IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 { + pinmux = <0x401f81c4 9 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_data0: IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 { + pinmux = <0x401f81c4 0 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN06 { + pinmux = <0x401f81c4 3 0x0 0 0x401f83b4>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f81c4 3 0x0 0 0x401f83b4>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_flexpwm1_pwmb1: IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB1 { + pinmux = <0x401f81c8 1 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io15: IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio8_io15: IOMUXC_GPIO_SD_B0_03_GPIO8_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_sdi: IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI { + pinmux = <0x401f81c8 4 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart8_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B { + pinmux = <0x401f81c8 2 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_semc_clk6: IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 { + pinmux = <0x401f81c8 9 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_data1: IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 { + pinmux = <0x401f81c8 0 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_in07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_IN07 { + pinmux = <0x401f81c8 3 0x0 0 0x401f83b8>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_inout07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f81c8 3 0x0 0 0x401f83b8>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_ccm_clko1: IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 { + pinmux = <0x401f81cc 6 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexpwm1_pwma2: IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA2 { + pinmux = <0x401f81cc 1 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f81cc 4 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io16: IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio8_io16: IOMUXC_GPIO_SD_B0_04_GPIO8_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart8_tx: IOMUXC_GPIO_SD_B0_04_LPUART8_TX { + pinmux = <0x401f81cc 2 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data2: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 { + pinmux = <0x401f81cc 0 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_in08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_IN08 { + pinmux = <0x401f81cc 3 0x0 0 0x401f83bc>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_inout08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f81cc 3 0x0 0 0x401f83bc>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_ccm_clko2: IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 { + pinmux = <0x401f81d0 6 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexpwm1_pwmb2: IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB2 { + pinmux = <0x401f81d0 1 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f81d0 4 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io17: IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio8_io17: IOMUXC_GPIO_SD_B0_05_GPIO8_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart8_rx: IOMUXC_GPIO_SD_B0_05_LPUART8_RX { + pinmux = <0x401f81d0 2 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data3: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 { + pinmux = <0x401f81d0 0 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_in09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_IN09 { + pinmux = <0x401f81d0 3 0x0 0 0x401f83c0>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_inout09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f81d0 3 0x0 0 0x401f83c0>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f81d4 2 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f81d4 1 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io00: IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio8_io00: IOMUXC_GPIO_SD_B1_00_GPIO8_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart4_tx: IOMUXC_GPIO_SD_B1_00_LPUART4_TX { + pinmux = <0x401f81d4 4 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai1_tx_data3: IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA3 { + pinmux = <0x401f81d4 3 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai3_rx_data: IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA { + pinmux = <0x401f81d4 8 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data3: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 { + pinmux = <0x401f81d4 0 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f81d8 2 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_data2: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 { + pinmux = <0x401f81d8 1 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io01: IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio8_io01: IOMUXC_GPIO_SD_B1_01_GPIO8_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart4_rx: IOMUXC_GPIO_SD_B1_01_LPUART4_RX { + pinmux = <0x401f81d8 4 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai1_tx_data2: IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA2 { + pinmux = <0x401f81d8 3 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai3_tx_data: IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA { + pinmux = <0x401f81d8 8 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data2: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 { + pinmux = <0x401f81d8 0 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_wait: IOMUXC_GPIO_SD_B1_02_CCM_WAIT { + pinmux = <0x401f81dc 6 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexcan1_tx: IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX { + pinmux = <0x401f81dc 4 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f81dc 2 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data1: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 { + pinmux = <0x401f81dc 1 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io02: IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio8_io02: IOMUXC_GPIO_SD_B1_02_GPIO8_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai1_tx_data1: IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA1 { + pinmux = <0x401f81dc 3 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai3_tx_sync: IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC { + pinmux = <0x401f81dc 8 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_data1: IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 { + pinmux = <0x401f81dc 0 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_03_CCM_PMIC_RDY { + pinmux = <0x401f81e0 6 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexcan1_rx: IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX { + pinmux = <0x401f81e0 4 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f81e0 2 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data0: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 { + pinmux = <0x401f81e0 1 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io03: IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio8_io03: IOMUXC_GPIO_SD_B1_03_GPIO8_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai1_mclk: IOMUXC_GPIO_SD_B1_03_SAI1_MCLK { + pinmux = <0x401f81e0 3 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK { + pinmux = <0x401f81e0 8 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_data0: IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 { + pinmux = <0x401f81e0 0 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_stop: IOMUXC_GPIO_SD_B1_04_CCM_STOP { + pinmux = <0x401f81e4 6 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI_A_SS1_B { + pinmux = <0x401f81e4 4 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK { + pinmux = <0x401f81e4 1 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io04: IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio8_io04: IOMUXC_GPIO_SD_B1_04_GPIO8_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_lpi2c1_scl: IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL { + pinmux = <0x401f81e4 2 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai1_rx_sync: IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f81e4 3 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai3_mclk: IOMUXC_GPIO_SD_B1_04_SAI3_MCLK { + pinmux = <0x401f81e4 8 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_clk: IOMUXC_GPIO_SD_B1_04_USDHC2_CLK { + pinmux = <0x401f81e4 0 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f81e8 1 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f81e8 4 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io05: IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio8_io05: IOMUXC_GPIO_SD_B1_05_GPIO8_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_lpi2c1_sda: IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA { + pinmux = <0x401f81e8 2 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai1_rx_bclk: IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK { + pinmux = <0x401f81e8 3 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_rx_sync: IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC { + pinmux = <0x401f81e8 8 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_cmd: IOMUXC_GPIO_SD_B1_05_USDHC2_CMD { + pinmux = <0x401f81e8 0 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B { + pinmux = <0x401f81ec 1 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io06: IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio8_io06: IOMUXC_GPIO_SD_B1_06_GPIO8_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f81ec 4 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpuart7_cts_b: IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B { + pinmux = <0x401f81ec 2 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai1_rx_data0: IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA0 { + pinmux = <0x401f81ec 3 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK { + pinmux = <0x401f81ec 8 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B { + pinmux = <0x401f81ec 0 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f81f0 1 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io07: IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio8_io07: IOMUXC_GPIO_SD_B1_07_GPIO8_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f81f0 4 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpuart7_rts_b: IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B { + pinmux = <0x401f81f0 2 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai1_tx_data0: IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA0 { + pinmux = <0x401f81f0 3 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_semc_csx1: IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 { + pinmux = <0x401f81f0 0 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f81f4 1 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io08: IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio8_io08: IOMUXC_GPIO_SD_B1_08_GPIO8_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f81f4 4 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpuart7_tx: IOMUXC_GPIO_SD_B1_08_LPUART7_TX { + pinmux = <0x401f81f4 2 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai1_tx_bclk: IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK { + pinmux = <0x401f81f4 3 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_semc_csx2: IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 { + pinmux = <0x401f81f4 6 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f81f4 0 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data1: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 { + pinmux = <0x401f81f8 1 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io09: IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio8_io09: IOMUXC_GPIO_SD_B1_09_GPIO8_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f81f8 4 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpuart7_rx: IOMUXC_GPIO_SD_B1_09_LPUART7_RX { + pinmux = <0x401f81f8 2 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai1_tx_sync: IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC { + pinmux = <0x401f81f8 3 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f81f8 0 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data2: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 { + pinmux = <0x401f81fc 1 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io10: IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio8_io10: IOMUXC_GPIO_SD_B1_10_GPIO8_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpi2c2_sda: IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA { + pinmux = <0x401f81fc 3 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f81fc 4 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpuart2_rx: IOMUXC_GPIO_SD_B1_10_LPUART2_RX { + pinmux = <0x401f81fc 2 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f81fc 0 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_data3: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 { + pinmux = <0x401f8200 1 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io11: IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio8_io11: IOMUXC_GPIO_SD_B1_11_GPIO8_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpi2c2_scl: IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL { + pinmux = <0x401f8200 3 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8200 4 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpuart2_tx: IOMUXC_GPIO_SD_B1_11_LPUART2_TX { + pinmux = <0x401f8200 2 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8200 0 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x0 0 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1041xfp5b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1041xfp5b-pinctrl.dtsi new file mode 100644 index 000000000..cfb5fec3e --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1041xfp5b-pinctrl.dtsi @@ -0,0 +1,3116 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1041XFP5B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_tx_data3: IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA3 { + pinmux = <0x401f80cc 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio6_io04: IOMUXC_GPIO_AD_B0_04_GPIO6_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_mqs_right: IOMUXC_GPIO_AD_B0_04_MQS_RIGHT { + pinmux = <0x401f80cc 1 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_pit_trigger0: IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER0 { + pinmux = <0x401f80cc 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_sai2_tx_sync: IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC { + pinmux = <0x401f80cc 3 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_src_boot_mode0: IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE0 { + pinmux = <0x401f80cc 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_tx_data2: IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA2 { + pinmux = <0x401f80d0 2 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio6_io05: IOMUXC_GPIO_AD_B0_05_GPIO6_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_mqs_left: IOMUXC_GPIO_AD_B0_05_MQS_LEFT { + pinmux = <0x401f80d0 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_sai2_tx_bclk: IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f80d0 3 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_src_boot_mode1: IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE1 { + pinmux = <0x401f80d0 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_IN17 { + pinmux = <0x401f80d0 6 0x0 0 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80d0 6 0x0 0 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_enet_rx_clk: IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK { + pinmux = <0x401f80d4 2 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio6_io06: IOMUXC_GPIO_AD_B0_06_GPIO6_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpt2_compare1: IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 { + pinmux = <0x401f80d4 1 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_jtag_tms: IOMUXC_GPIO_AD_B0_06_JTAG_TMS { + pinmux = <0x401f80d4 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_sai2_rx_bclk: IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK { + pinmux = <0x401f80d4 3 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_in18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_IN18 { + pinmux = <0x401f80d4 6 0x0 0 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_inout18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80d4 6 0x0 0 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_1588_event3_out: IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT { + pinmux = <0x401f80d8 7 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_tx_er: IOMUXC_GPIO_AD_B0_07_ENET_TX_ER { + pinmux = <0x401f80d8 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio6_io07: IOMUXC_GPIO_AD_B0_07_GPIO6_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpt2_compare2: IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 { + pinmux = <0x401f80d8 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_jtag_tck: IOMUXC_GPIO_AD_B0_07_JTAG_TCK { + pinmux = <0x401f80d8 0 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_sai2_rx_sync: IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC { + pinmux = <0x401f80d8 3 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_in19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_IN19 { + pinmux = <0x401f80d8 6 0x0 0 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_inout19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80d8 6 0x0 0 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_1588_event3_in: IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN { + pinmux = <0x401f80dc 7 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_rx_data3: IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA3 { + pinmux = <0x401f80dc 2 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio6_io08: IOMUXC_GPIO_AD_B0_08_GPIO6_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpt2_compare3: IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 { + pinmux = <0x401f80dc 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_jtag_mod: IOMUXC_GPIO_AD_B0_08_JTAG_MOD { + pinmux = <0x401f80dc 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_sai2_rx_data: IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA { + pinmux = <0x401f80dc 3 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_xbar1_xbar_in20: IOMUXC_GPIO_AD_B0_08_XBAR1_XBAR_IN20 { + pinmux = <0x401f80dc 6 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data2: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA2 { + pinmux = <0x401f80e0 2 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA3 { + pinmux = <0x401f80e0 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio6_io09: IOMUXC_GPIO_AD_B0_09_GPIO6_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpt2_clk: IOMUXC_GPIO_AD_B0_09_GPT2_CLK { + pinmux = <0x401f80e0 7 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_jtag_tdi: IOMUXC_GPIO_AD_B0_09_JTAG_TDI { + pinmux = <0x401f80e0 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_sai2_tx_data: IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA { + pinmux = <0x401f80e0 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_semc_dqs4: IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 { + pinmux = <0x401f80e0 9 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_xbar1_xbar_in21: IOMUXC_GPIO_AD_B0_09_XBAR1_XBAR_IN21 { + pinmux = <0x401f80e0 6 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_swo: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO { + pinmux = <0x401f80e4 9 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80e4 7 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_crs: IOMUXC_GPIO_AD_B0_10_ENET_CRS { + pinmux = <0x401f80e4 2 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexcan3_tx: IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX { + pinmux = <0x401f80e4 8 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm1_pwma3: IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA3 { + pinmux = <0x401f80e4 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio6_io10: IOMUXC_GPIO_AD_B0_10_GPIO6_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_jtag_tdo: IOMUXC_GPIO_AD_B0_10_JTAG_TDO { + pinmux = <0x401f80e4 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_sai2_mclk: IOMUXC_GPIO_AD_B0_10_SAI2_MCLK { + pinmux = <0x401f80e4 3 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_xbar1_xbar_in22: IOMUXC_GPIO_AD_B0_10_XBAR1_XBAR_IN22 { + pinmux = <0x401f80e4 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN { + pinmux = <0x401f80e8 7 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_col: IOMUXC_GPIO_AD_B0_11_ENET_COL { + pinmux = <0x401f80e8 2 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexcan3_rx: IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX { + pinmux = <0x401f80e8 8 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB3 { + pinmux = <0x401f80e8 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio6_io11: IOMUXC_GPIO_AD_B0_11_GPIO6_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_jtag_trstb: IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB { + pinmux = <0x401f80e8 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_semc_clk6: IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 { + pinmux = <0x401f80e8 9 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_wdog1_b: IOMUXC_GPIO_AD_B0_11_WDOG1_B { + pinmux = <0x401f80e8 3 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_xbar1_xbar_in23: IOMUXC_GPIO_AD_B0_11_XBAR1_XBAR_IN23 { + pinmux = <0x401f80e8 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in1: IOMUXC_GPIO_AD_B0_12_ADC1_IN1 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_nmi: IOMUXC_GPIO_AD_B0_12_ARM_NMI { + pinmux = <0x401f80ec 7 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_12_CCM_PMIC_RDY { + pinmux = <0x401f80ec 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_1588_event1_out: IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT { + pinmux = <0x401f80ec 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm1_pwmx2: IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX2 { + pinmux = <0x401f80ec 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio6_io12: IOMUXC_GPIO_AD_B0_12_GPIO6_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpi2c4_scl: IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL { + pinmux = <0x401f80ec 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart1_tx: IOMUXC_GPIO_AD_B0_12_LPUART1_TX { + pinmux = <0x401f80ec 2 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_wdog2_b: IOMUXC_GPIO_AD_B0_12_WDOG2_B { + pinmux = <0x401f80ec 3 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_acmp1_in2: IOMUXC_GPIO_AD_B0_13_ACMP1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc1_in2: IOMUXC_GPIO_AD_B0_13_ADC1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_1588_event1_in: IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN { + pinmux = <0x401f80f0 6 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ewm_out_b: IOMUXC_GPIO_AD_B0_13_EWM_OUT_B { + pinmux = <0x401f80f0 3 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm1_pwmx3: IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX3 { + pinmux = <0x401f80f0 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio6_io13: IOMUXC_GPIO_AD_B0_13_GPIO6_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpt1_clk: IOMUXC_GPIO_AD_B0_13_GPT1_CLK { + pinmux = <0x401f80f0 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpi2c4_sda: IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA { + pinmux = <0x401f80f0 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart1_rx: IOMUXC_GPIO_AD_B0_13_LPUART1_RX { + pinmux = <0x401f80f0 2 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ref_24m_out: IOMUXC_GPIO_AD_B0_13_REF_24M_OUT { + pinmux = <0x401f80f0 7 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in2: IOMUXC_GPIO_AD_B0_14_ACMP2_IN2 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in3: IOMUXC_GPIO_AD_B0_14_ADC1_IN3 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80f4 3 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan3_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX { + pinmux = <0x401f80f4 8 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio6_io14: IOMUXC_GPIO_AD_B0_14_GPIO6_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B { + pinmux = <0x401f80f4 2 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_xbar1_xbar_in24: IOMUXC_GPIO_AD_B0_14_XBAR1_XBAR_IN24 { + pinmux = <0x401f80f4 1 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in2: IOMUXC_GPIO_AD_B0_15_ACMP3_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in4: IOMUXC_GPIO_AD_B0_15_ADC1_IN4 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f80f8 3 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 6 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan3_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX { + pinmux = <0x401f80f8 8 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio6_io15: IOMUXC_GPIO_AD_B0_15_GPIO6_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B { + pinmux = <0x401f80f8 2 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb: IOMUXC_GPIO_AD_B0_15_WDOG1_RST_B_DEB { + pinmux = <0x401f80f8 7 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_xbar1_xbar_in25: IOMUXC_GPIO_AD_B0_15_XBAR1_XBAR_IN25 { + pinmux = <0x401f80f8 1 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp4_in2: IOMUXC_GPIO_AD_B1_00_ACMP4_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc1_in5: IOMUXC_GPIO_AD_B1_00_ADC1_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc2_in5: IOMUXC_GPIO_AD_B1_00_ADC2_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio3_flexio00: IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 { + pinmux = <0x401f80fc 9 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio6_io16: IOMUXC_GPIO_AD_B1_00_GPIO6_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpi2c1_scl: IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL { + pinmux = <0x401f80fc 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B { + pinmux = <0x401f80fc 2 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_qtimer3_timer0: IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 { + pinmux = <0x401f80fc 1 0x0 0 0x401f82ec>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usdhc1_wp: IOMUXC_GPIO_AD_B1_00_USDHC1_WP { + pinmux = <0x401f80fc 6 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_wdog1_b: IOMUXC_GPIO_AD_B1_00_WDOG1_B { + pinmux = <0x401f80fc 4 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp1_in0: IOMUXC_GPIO_AD_B1_01_ACMP1_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in0: IOMUXC_GPIO_AD_B1_01_ACMP2_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp3_in0: IOMUXC_GPIO_AD_B1_01_ACMP3_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp4_in0: IOMUXC_GPIO_AD_B1_01_ACMP4_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in6: IOMUXC_GPIO_AD_B1_01_ADC1_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc2_in6: IOMUXC_GPIO_AD_B1_01_ADC2_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_01_CCM_PMIC_RDY { + pinmux = <0x401f8100 4 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio3_flexio01: IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 { + pinmux = <0x401f8100 9 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio6_io17: IOMUXC_GPIO_AD_B1_01_GPIO6_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpi2c1_sda: IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA { + pinmux = <0x401f8100 3 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B { + pinmux = <0x401f8100 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_qtimer3_timer1: IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 { + pinmux = <0x401f8100 1 0x0 0 0x401f82f0>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR { + pinmux = <0x401f8100 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usdhc1_vselect: IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT { + pinmux = <0x401f8100 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp1_in3: IOMUXC_GPIO_AD_B1_02_ACMP1_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc1_in7: IOMUXC_GPIO_AD_B1_02_ADC1_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in7: IOMUXC_GPIO_AD_B1_02_ADC2_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT { + pinmux = <0x401f8104 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio3_flexio02: IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 { + pinmux = <0x401f8104 9 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio6_io18: IOMUXC_GPIO_AD_B1_02_GPIO6_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpt2_clk: IOMUXC_GPIO_AD_B1_02_GPT2_CLK { + pinmux = <0x401f8104 8 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpuart2_tx: IOMUXC_GPIO_AD_B1_02_LPUART2_TX { + pinmux = <0x401f8104 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_qtimer3_timer2: IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 { + pinmux = <0x401f8104 1 0x0 0 0x401f82f4>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_spdif_out: IOMUXC_GPIO_AD_B1_02_SPDIF_OUT { + pinmux = <0x401f8104 3 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usb_otg1_id: IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID { + pinmux = <0x401f8104 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B { + pinmux = <0x401f8104 6 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp2_in3: IOMUXC_GPIO_AD_B1_03_ACMP2_IN3 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in8: IOMUXC_GPIO_AD_B1_03_ADC1_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc2_in8: IOMUXC_GPIO_AD_B1_03_ADC2_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN { + pinmux = <0x401f8108 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio3_flexio03: IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 { + pinmux = <0x401f8108 9 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio6_io19: IOMUXC_GPIO_AD_B1_03_GPIO6_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpt2_capture1: IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 { + pinmux = <0x401f8108 8 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpuart2_rx: IOMUXC_GPIO_AD_B1_03_LPUART2_RX { + pinmux = <0x401f8108 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_qtimer3_timer3: IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 { + pinmux = <0x401f8108 1 0x0 0 0x401f82f8>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_spdif_in: IOMUXC_GPIO_AD_B1_03_SPDIF_IN { + pinmux = <0x401f8108 3 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usb_otg1_oc: IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC { + pinmux = <0x401f8108 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B { + pinmux = <0x401f8108 6 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp3_in3: IOMUXC_GPIO_AD_B1_04_ACMP3_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc1_in9: IOMUXC_GPIO_AD_B1_04_ADC1_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in9: IOMUXC_GPIO_AD_B1_04_ADC2_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_enet_mdc: IOMUXC_GPIO_AD_B1_04_ENET_MDC { + pinmux = <0x401f810c 1 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio3_flexio04: IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 { + pinmux = <0x401f810c 9 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_b_data3: IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 { + pinmux = <0x401f810c 0 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio6_io20: IOMUXC_GPIO_AD_B1_04_GPIO6_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpt2_capture2: IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 { + pinmux = <0x401f810c 8 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpuart3_cts_b: IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B { + pinmux = <0x401f810c 2 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_spdif_sr_clk: IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK { + pinmux = <0x401f810c 3 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_usdhc2_data0: IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f810c 6 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp4_in3: IOMUXC_GPIO_AD_B1_05_ACMP4_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in10: IOMUXC_GPIO_AD_B1_05_ADC1_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in10: IOMUXC_GPIO_AD_B1_05_ADC2_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_enet_mdio: IOMUXC_GPIO_AD_B1_05_ENET_MDIO { + pinmux = <0x401f8110 1 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio3_flexio05: IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 { + pinmux = <0x401f8110 9 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_b_data2: IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 { + pinmux = <0x401f8110 0 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio6_io21: IOMUXC_GPIO_AD_B1_05_GPIO6_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpt2_compare1: IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 { + pinmux = <0x401f8110 8 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpuart3_rts_b: IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B { + pinmux = <0x401f8110 2 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_spdif_out: IOMUXC_GPIO_AD_B1_05_SPDIF_OUT { + pinmux = <0x401f8110 3 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc2_data1: IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f8110 6 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp1_in1: IOMUXC_GPIO_AD_B1_06_ACMP1_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp2_in1: IOMUXC_GPIO_AD_B1_06_ACMP2_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in1: IOMUXC_GPIO_AD_B1_06_ACMP3_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp4_in1: IOMUXC_GPIO_AD_B1_06_ACMP4_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in11: IOMUXC_GPIO_AD_B1_06_ADC1_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in11: IOMUXC_GPIO_AD_B1_06_ADC2_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio3_flexio06: IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 { + pinmux = <0x401f8114 9 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexspi_b_data1: IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 { + pinmux = <0x401f8114 0 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio6_io22: IOMUXC_GPIO_AD_B1_06_GPIO6_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpt2_compare2: IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 { + pinmux = <0x401f8114 8 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpi2c3_sda: IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA { + pinmux = <0x401f8114 1 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart3_tx: IOMUXC_GPIO_AD_B1_06_LPUART3_TX { + pinmux = <0x401f8114 2 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_spdif_lock: IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK { + pinmux = <0x401f8114 3 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc2_data2: IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 { + pinmux = <0x401f8114 6 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp1_in5: IOMUXC_GPIO_AD_B1_07_ACMP1_IN5 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in12: IOMUXC_GPIO_AD_B1_07_ADC1_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in12: IOMUXC_GPIO_AD_B1_07_ADC2_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio3_flexio07: IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 { + pinmux = <0x401f8118 9 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexspi_b_data0: IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 { + pinmux = <0x401f8118 0 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio6_io23: IOMUXC_GPIO_AD_B1_07_GPIO6_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpt2_compare3: IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 { + pinmux = <0x401f8118 8 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpi2c3_scl: IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL { + pinmux = <0x401f8118 1 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart3_rx: IOMUXC_GPIO_AD_B1_07_LPUART3_RX { + pinmux = <0x401f8118 2 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_spdif_ext_clk: IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK { + pinmux = <0x401f8118 3 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc2_data3: IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 { + pinmux = <0x401f8118 6 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_flexio2_flexio00: IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 { + pinmux = <0x401f813c 4 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio2_io00: IOMUXC_GPIO_B0_00_GPIO2_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio7_io00: IOMUXC_GPIO_B0_00_GPIO7_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lpspi3_pcs0: IOMUXC_GPIO_B0_00_LPSPI3_PCS0 { + pinmux = <0x401f813c 3 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_mqs_right: IOMUXC_GPIO_B0_00_MQS_RIGHT { + pinmux = <0x401f813c 2 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_qtimer1_timer0: IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x0 0 0x401f832c>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_semc_csx1: IOMUXC_GPIO_B0_00_SEMC_CSX1 { + pinmux = <0x401f813c 6 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_flexio2_flexio01: IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 { + pinmux = <0x401f8140 4 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio2_io01: IOMUXC_GPIO_B0_01_GPIO2_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio7_io01: IOMUXC_GPIO_B0_01_GPIO7_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lpspi3_sdi: IOMUXC_GPIO_B0_01_LPSPI3_SDI { + pinmux = <0x401f8140 3 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_mqs_left: IOMUXC_GPIO_B0_01_MQS_LEFT { + pinmux = <0x401f8140 2 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_qtimer1_timer1: IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x0 0 0x401f8330>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_semc_csx2: IOMUXC_GPIO_B0_01_SEMC_CSX2 { + pinmux = <0x401f8140 6 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexcan1_tx: IOMUXC_GPIO_B0_02_FLEXCAN1_TX { + pinmux = <0x401f8144 2 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexio2_flexio02: IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 { + pinmux = <0x401f8144 4 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio2_io02: IOMUXC_GPIO_B0_02_GPIO2_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio7_io02: IOMUXC_GPIO_B0_02_GPIO7_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lpspi3_sdo: IOMUXC_GPIO_B0_02_LPSPI3_SDO { + pinmux = <0x401f8144 3 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_qtimer1_timer2: IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x0 0 0x401f8334>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_semc_csx3: IOMUXC_GPIO_B0_02_SEMC_CSX3 { + pinmux = <0x401f8144 6 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexcan1_rx: IOMUXC_GPIO_B0_03_FLEXCAN1_RX { + pinmux = <0x401f8148 2 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexio2_flexio03: IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 { + pinmux = <0x401f8148 4 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio2_io03: IOMUXC_GPIO_B0_03_GPIO2_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio7_io03: IOMUXC_GPIO_B0_03_GPIO7_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lpspi3_sck: IOMUXC_GPIO_B0_03_LPSPI3_SCK { + pinmux = <0x401f8148 3 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_qtimer2_timer0: IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 { + pinmux = <0x401f8148 1 0x0 0 0x401f8338>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_wdog2_rst_b_deb: IOMUXC_GPIO_B0_03_WDOG2_RST_B_DEB { + pinmux = <0x401f8148 6 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_arm_trace0: IOMUXC_GPIO_B0_04_ARM_TRACE0 { + pinmux = <0x401f814c 3 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_flexio2_flexio04: IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 { + pinmux = <0x401f814c 4 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio2_io04: IOMUXC_GPIO_B0_04_GPIO2_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio7_io04: IOMUXC_GPIO_B0_04_GPIO7_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lpi2c2_scl: IOMUXC_GPIO_B0_04_LPI2C2_SCL { + pinmux = <0x401f814c 2 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_qtimer2_timer1: IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 { + pinmux = <0x401f814c 1 0x0 0 0x401f833c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_src_bt_cfg0: IOMUXC_GPIO_B0_04_SRC_BT_CFG0 { + pinmux = <0x401f814c 6 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_arm_trace1: IOMUXC_GPIO_B0_05_ARM_TRACE1 { + pinmux = <0x401f8150 3 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_flexio2_flexio05: IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 { + pinmux = <0x401f8150 4 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio2_io05: IOMUXC_GPIO_B0_05_GPIO2_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio7_io05: IOMUXC_GPIO_B0_05_GPIO7_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lpi2c2_sda: IOMUXC_GPIO_B0_05_LPI2C2_SDA { + pinmux = <0x401f8150 2 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_qtimer2_timer2: IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 { + pinmux = <0x401f8150 1 0x0 0 0x401f8340>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_src_bt_cfg1: IOMUXC_GPIO_B0_05_SRC_BT_CFG1 { + pinmux = <0x401f8150 6 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_arm_trace2: IOMUXC_GPIO_B0_06_ARM_TRACE2 { + pinmux = <0x401f8154 3 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexio2_flexio06: IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 { + pinmux = <0x401f8154 4 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexpwm2_pwma0: IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f8154 2 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio2_io06: IOMUXC_GPIO_B0_06_GPIO2_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio7_io06: IOMUXC_GPIO_B0_06_GPIO7_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_qtimer3_timer0: IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 { + pinmux = <0x401f8154 1 0x0 0 0x401f8344>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_src_bt_cfg2: IOMUXC_GPIO_B0_06_SRC_BT_CFG2 { + pinmux = <0x401f8154 6 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_arm_trace3: IOMUXC_GPIO_B0_07_ARM_TRACE3 { + pinmux = <0x401f8158 3 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexio2_flexio07: IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 { + pinmux = <0x401f8158 4 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexpwm2_pwmb0: IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8158 2 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio2_io07: IOMUXC_GPIO_B0_07_GPIO2_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio7_io07: IOMUXC_GPIO_B0_07_GPIO7_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_qtimer3_timer1: IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 { + pinmux = <0x401f8158 1 0x0 0 0x401f8348>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_src_bt_cfg3: IOMUXC_GPIO_B0_07_SRC_BT_CFG3 { + pinmux = <0x401f8158 6 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexio2_flexio08: IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 { + pinmux = <0x401f815c 4 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexpwm2_pwma1: IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f815c 2 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio2_io08: IOMUXC_GPIO_B0_08_GPIO2_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio7_io08: IOMUXC_GPIO_B0_08_GPIO7_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lpuart3_tx: IOMUXC_GPIO_B0_08_LPUART3_TX { + pinmux = <0x401f815c 3 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_qtimer3_timer2: IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 { + pinmux = <0x401f815c 1 0x0 0 0x401f834c>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_src_bt_cfg4: IOMUXC_GPIO_B0_08_SRC_BT_CFG4 { + pinmux = <0x401f815c 6 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexio2_flexio09: IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 { + pinmux = <0x401f8160 4 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexpwm2_pwmb1: IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8160 2 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio2_io09: IOMUXC_GPIO_B0_09_GPIO2_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio7_io09: IOMUXC_GPIO_B0_09_GPIO7_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lpuart3_rx: IOMUXC_GPIO_B0_09_LPUART3_RX { + pinmux = <0x401f8160 3 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_qtimer4_timer0: IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 { + pinmux = <0x401f8160 1 0x0 0 0x401f8350>; + gpr = <0x400ac018 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_src_bt_cfg5: IOMUXC_GPIO_B0_09_SRC_BT_CFG5 { + pinmux = <0x401f8160 6 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexio2_flexio10: IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 { + pinmux = <0x401f8164 4 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f8164 2 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio2_io10: IOMUXC_GPIO_B0_10_GPIO2_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio7_io10: IOMUXC_GPIO_B0_10_GPIO7_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_qtimer4_timer1: IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 { + pinmux = <0x401f8164 1 0x0 0 0x401f8354>; + gpr = <0x400ac018 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_sai1_tx_data3: IOMUXC_GPIO_B0_10_SAI1_TX_DATA3 { + pinmux = <0x401f8164 3 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_src_bt_cfg6: IOMUXC_GPIO_B0_10_SRC_BT_CFG6 { + pinmux = <0x401f8164 6 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexio2_flexio11: IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 { + pinmux = <0x401f8168 4 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8168 2 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio2_io11: IOMUXC_GPIO_B0_11_GPIO2_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio7_io11: IOMUXC_GPIO_B0_11_GPIO7_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_qtimer4_timer2: IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 { + pinmux = <0x401f8168 1 0x0 0 0x401f8358>; + gpr = <0x400ac018 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_sai1_tx_data2: IOMUXC_GPIO_B0_11_SAI1_TX_DATA2 { + pinmux = <0x401f8168 3 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_src_bt_cfg7: IOMUXC_GPIO_B0_11_SRC_BT_CFG7 { + pinmux = <0x401f8168 6 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_arm_trace_clk: IOMUXC_GPIO_B0_12_ARM_TRACE_CLK { + pinmux = <0x401f816c 2 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_flexio2_flexio12: IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 { + pinmux = <0x401f816c 4 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio2_io12: IOMUXC_GPIO_B0_12_GPIO2_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio7_io12: IOMUXC_GPIO_B0_12_GPIO7_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_sai1_tx_data1: IOMUXC_GPIO_B0_12_SAI1_TX_DATA1 { + pinmux = <0x401f816c 3 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_src_bt_cfg8: IOMUXC_GPIO_B0_12_SRC_BT_CFG8 { + pinmux = <0x401f816c 6 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_in10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_IN10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_inout10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_arm_trace_swo: IOMUXC_GPIO_B0_13_ARM_TRACE_SWO { + pinmux = <0x401f8170 2 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_flexio2_flexio13: IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 { + pinmux = <0x401f8170 4 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio2_io13: IOMUXC_GPIO_B0_13_GPIO2_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio7_io13: IOMUXC_GPIO_B0_13_GPIO7_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_sai1_mclk: IOMUXC_GPIO_B0_13_SAI1_MCLK { + pinmux = <0x401f8170 3 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_src_bt_cfg9: IOMUXC_GPIO_B0_13_SRC_BT_CFG9 { + pinmux = <0x401f8170 6 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_in11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_IN11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_inout11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_flexio2_flexio14: IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 { + pinmux = <0x401f8174 4 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio2_io14: IOMUXC_GPIO_B0_14_GPIO2_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio7_io14: IOMUXC_GPIO_B0_14_GPIO7_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_sai1_rx_sync: IOMUXC_GPIO_B0_14_SAI1_RX_SYNC { + pinmux = <0x401f8174 3 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_src_bt_cfg10: IOMUXC_GPIO_B0_14_SRC_BT_CFG10 { + pinmux = <0x401f8174 6 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_in12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_IN12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_inout12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_flexio2_flexio15: IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 { + pinmux = <0x401f8178 4 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio2_io15: IOMUXC_GPIO_B0_15_GPIO2_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio7_io15: IOMUXC_GPIO_B0_15_GPIO7_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_sai1_rx_bclk: IOMUXC_GPIO_B0_15_SAI1_RX_BCLK { + pinmux = <0x401f8178 3 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_src_bt_cfg11: IOMUXC_GPIO_B0_15_SRC_BT_CFG11 { + pinmux = <0x401f8178 6 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_in13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_IN13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_inout13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio2_flexio16: IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 { + pinmux = <0x401f817c 4 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio3_flexio16: IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 { + pinmux = <0x401f817c 9 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f817c 6 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio2_io16: IOMUXC_GPIO_B1_00_GPIO2_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio7_io16: IOMUXC_GPIO_B1_00_GPIO7_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lpuart4_tx: IOMUXC_GPIO_B1_00_LPUART4_TX { + pinmux = <0x401f817c 2 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_sai1_rx_data0: IOMUXC_GPIO_B1_00_SAI1_RX_DATA0 { + pinmux = <0x401f817c 3 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_in14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f817c 1 0x0 0 0x401f836c>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_inout14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f817c 1 0x0 0 0x401f836c>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio2_flexio17: IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 { + pinmux = <0x401f8180 4 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio3_flexio17: IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 { + pinmux = <0x401f8180 9 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f8180 6 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio2_io17: IOMUXC_GPIO_B1_01_GPIO2_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio7_io17: IOMUXC_GPIO_B1_01_GPIO7_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lpuart4_rx: IOMUXC_GPIO_B1_01_LPUART4_RX { + pinmux = <0x401f8180 2 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_sai1_tx_data0: IOMUXC_GPIO_B1_01_SAI1_TX_DATA0 { + pinmux = <0x401f8180 3 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_in15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8180 1 0x0 0 0x401f8370>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_inout15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8180 1 0x0 0 0x401f8370>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio2_flexio18: IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 { + pinmux = <0x401f8184 4 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio3_flexio18: IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 { + pinmux = <0x401f8184 9 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f8184 6 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio2_io18: IOMUXC_GPIO_B1_02_GPIO2_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio7_io18: IOMUXC_GPIO_B1_02_GPIO7_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lpspi3_pcs2: IOMUXC_GPIO_B1_02_LPSPI3_PCS2 { + pinmux = <0x401f8184 2 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_sai1_tx_bclk: IOMUXC_GPIO_B1_02_SAI1_TX_BCLK { + pinmux = <0x401f8184 3 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_in16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8184 1 0x0 0 0x401f8374>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_inout16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8184 1 0x0 0 0x401f8374>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio2_flexio19: IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 { + pinmux = <0x401f8188 4 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio3_flexio19: IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 { + pinmux = <0x401f8188 9 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f8188 6 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio2_io19: IOMUXC_GPIO_B1_03_GPIO2_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio7_io19: IOMUXC_GPIO_B1_03_GPIO7_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lpspi3_pcs1: IOMUXC_GPIO_B1_03_LPSPI3_PCS1 { + pinmux = <0x401f8188 2 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_sai1_tx_sync: IOMUXC_GPIO_B1_03_SAI1_TX_SYNC { + pinmux = <0x401f8188 3 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_in17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f8188 1 0x0 0 0x401f8378>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_inout17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8188 1 0x0 0 0x401f8378>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_enet_rx_data0: IOMUXC_GPIO_B1_04_ENET_RX_DATA0 { + pinmux = <0x401f818c 3 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio2_flexio20: IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 { + pinmux = <0x401f818c 4 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio3_flexio20: IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 { + pinmux = <0x401f818c 9 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio2_io20: IOMUXC_GPIO_B1_04_GPIO2_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio7_io20: IOMUXC_GPIO_B1_04_GPIO7_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpt1_clk: IOMUXC_GPIO_B1_04_GPT1_CLK { + pinmux = <0x401f818c 8 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lpspi3_pcs0: IOMUXC_GPIO_B1_04_LPSPI3_PCS0 { + pinmux = <0x401f818c 1 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_enet_rx_data1: IOMUXC_GPIO_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f8190 3 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio2_flexio21: IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 { + pinmux = <0x401f8190 4 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio3_flexio21: IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 { + pinmux = <0x401f8190 9 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio2_io21: IOMUXC_GPIO_B1_05_GPIO2_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio7_io21: IOMUXC_GPIO_B1_05_GPIO7_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpt1_capture1: IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 { + pinmux = <0x401f8190 8 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lpspi3_sdi: IOMUXC_GPIO_B1_05_LPSPI3_SDI { + pinmux = <0x401f8190 1 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_enet_rx_en: IOMUXC_GPIO_B1_06_ENET_RX_EN { + pinmux = <0x401f8194 3 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio2_flexio22: IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 { + pinmux = <0x401f8194 4 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio3_flexio22: IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 { + pinmux = <0x401f8194 9 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio2_io22: IOMUXC_GPIO_B1_06_GPIO2_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio7_io22: IOMUXC_GPIO_B1_06_GPIO7_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpt1_capture2: IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 { + pinmux = <0x401f8194 8 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lpspi3_sdo: IOMUXC_GPIO_B1_06_LPSPI3_SDO { + pinmux = <0x401f8194 1 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_enet_tx_data0: IOMUXC_GPIO_B1_07_ENET_TX_DATA0 { + pinmux = <0x401f8198 3 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio2_flexio23: IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 { + pinmux = <0x401f8198 4 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio3_flexio23: IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 { + pinmux = <0x401f8198 9 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio2_io23: IOMUXC_GPIO_B1_07_GPIO2_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio7_io23: IOMUXC_GPIO_B1_07_GPIO7_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpt1_compare1: IOMUXC_GPIO_B1_07_GPT1_COMPARE1 { + pinmux = <0x401f8198 8 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lpspi3_sck: IOMUXC_GPIO_B1_07_LPSPI3_SCK { + pinmux = <0x401f8198 1 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_enet_tx_data1: IOMUXC_GPIO_B1_08_ENET_TX_DATA1 { + pinmux = <0x401f819c 3 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexcan2_tx: IOMUXC_GPIO_B1_08_FLEXCAN2_TX { + pinmux = <0x401f819c 6 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio2_flexio24: IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 { + pinmux = <0x401f819c 4 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio3_flexio24: IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 { + pinmux = <0x401f819c 9 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio2_io24: IOMUXC_GPIO_B1_08_GPIO2_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio7_io24: IOMUXC_GPIO_B1_08_GPIO7_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpt1_compare2: IOMUXC_GPIO_B1_08_GPT1_COMPARE2 { + pinmux = <0x401f819c 8 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_qtimer1_timer3: IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 { + pinmux = <0x401f819c 1 0x0 0 0x401f838c>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_enet_tx_en: IOMUXC_GPIO_B1_09_ENET_TX_EN { + pinmux = <0x401f81a0 3 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexcan2_rx: IOMUXC_GPIO_B1_09_FLEXCAN2_RX { + pinmux = <0x401f81a0 6 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio2_flexio25: IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 { + pinmux = <0x401f81a0 4 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio3_flexio25: IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 { + pinmux = <0x401f81a0 9 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio2_io25: IOMUXC_GPIO_B1_09_GPIO2_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio7_io25: IOMUXC_GPIO_B1_09_GPIO7_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpt1_compare3: IOMUXC_GPIO_B1_09_GPT1_COMPARE3 { + pinmux = <0x401f81a0 8 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_qtimer2_timer3: IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 { + pinmux = <0x401f81a0 1 0x0 0 0x401f8390>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_ref_clk: IOMUXC_GPIO_B1_10_ENET_REF_CLK { + pinmux = <0x401f81a4 6 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_tx_clk: IOMUXC_GPIO_B1_10_ENET_TX_CLK { + pinmux = <0x401f81a4 3 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio2_flexio26: IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 { + pinmux = <0x401f81a4 4 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio3_flexio26: IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 { + pinmux = <0x401f81a4 9 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio2_io26: IOMUXC_GPIO_B1_10_GPIO2_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio7_io26: IOMUXC_GPIO_B1_10_GPIO7_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_qtimer3_timer3: IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 { + pinmux = <0x401f81a4 1 0x0 0 0x401f8394>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_enet_rx_er: IOMUXC_GPIO_B1_11_ENET_RX_ER { + pinmux = <0x401f81a8 3 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio2_flexio27: IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 { + pinmux = <0x401f81a8 4 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio3_flexio27: IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 { + pinmux = <0x401f81a8 9 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio2_io27: IOMUXC_GPIO_B1_11_GPIO2_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio7_io27: IOMUXC_GPIO_B1_11_GPIO7_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lpspi3_pcs3: IOMUXC_GPIO_B1_11_LPSPI3_PCS3 { + pinmux = <0x401f81a8 6 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_qtimer4_timer3: IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 { + pinmux = <0x401f81a8 1 0x0 0 0x401f8398>; + gpr = <0x400ac018 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_enet_1588_event0_in: IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN { + pinmux = <0x401f81ac 3 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio2_flexio28: IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 { + pinmux = <0x401f81ac 4 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio3_flexio28: IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 { + pinmux = <0x401f81ac 9 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio2_io28: IOMUXC_GPIO_B1_12_GPIO2_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio7_io28: IOMUXC_GPIO_B1_12_GPIO7_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_lpuart5_tx: IOMUXC_GPIO_B1_12_LPUART5_TX { + pinmux = <0x401f81ac 1 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_usdhc1_cd_b: IOMUXC_GPIO_B1_12_USDHC1_CD_B { + pinmux = <0x401f81ac 6 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_enet_1588_event0_out: IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT { + pinmux = <0x401f81b0 3 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio2_flexio29: IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 { + pinmux = <0x401f81b0 4 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio3_flexio29: IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 { + pinmux = <0x401f81b0 9 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio2_io29: IOMUXC_GPIO_B1_13_GPIO2_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio7_io29: IOMUXC_GPIO_B1_13_GPIO7_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_lpuart5_rx: IOMUXC_GPIO_B1_13_LPUART5_RX { + pinmux = <0x401f81b0 1 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_semc_dqs4: IOMUXC_GPIO_B1_13_SEMC_DQS4 { + pinmux = <0x401f81b0 8 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_usdhc1_wp: IOMUXC_GPIO_B1_13_USDHC1_WP { + pinmux = <0x401f81b0 6 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_wdog1_b: IOMUXC_GPIO_B1_13_WDOG1_B { + pinmux = <0x401f81b0 0 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet_mdc: IOMUXC_GPIO_B1_14_ENET_MDC { + pinmux = <0x401f81b4 0 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio2_flexio30: IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 { + pinmux = <0x401f81b4 4 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio3_flexio30: IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 { + pinmux = <0x401f81b4 9 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexpwm4_pwma2: IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA2 { + pinmux = <0x401f81b4 1 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio2_io30: IOMUXC_GPIO_B1_14_GPIO2_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio7_io30: IOMUXC_GPIO_B1_14_GPIO7_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_usdhc1_vselect: IOMUXC_GPIO_B1_14_USDHC1_VSELECT { + pinmux = <0x401f81b4 6 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_xbar1_xbar_in02: IOMUXC_GPIO_B1_14_XBAR1_XBAR_IN02 { + pinmux = <0x401f81b4 3 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet_mdio: IOMUXC_GPIO_B1_15_ENET_MDIO { + pinmux = <0x401f81b8 0 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio2_flexio31: IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 { + pinmux = <0x401f81b8 4 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio3_flexio31: IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 { + pinmux = <0x401f81b8 9 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexpwm4_pwma3: IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA3 { + pinmux = <0x401f81b8 1 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio2_io31: IOMUXC_GPIO_B1_15_GPIO2_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio7_io31: IOMUXC_GPIO_B1_15_GPIO7_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_usdhc1_reset_b: IOMUXC_GPIO_B1_15_USDHC1_RESET_B { + pinmux = <0x401f81b8 6 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_xbar1_xbar_in03: IOMUXC_GPIO_B1_15_XBAR1_XBAR_IN03 { + pinmux = <0x401f81b8 3 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexio1_flexio00: IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8014 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexpwm4_pwma0: IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA0 { + pinmux = <0x401f8014 1 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio4_io00: IOMUXC_GPIO_EMC_00_GPIO4_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio9_io00: IOMUXC_GPIO_EMC_00_GPIO9_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 2 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_xbar1_xbar_in02: IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 { + pinmux = <0x401f8014 3 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexio1_flexio01: IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8018 4 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexpwm4_pwmb0: IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB0 { + pinmux = <0x401f8018 1 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio4_io01: IOMUXC_GPIO_EMC_01_GPIO4_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio9_io01: IOMUXC_GPIO_EMC_01_GPIO9_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 2 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_xbar1_xbar_in03: IOMUXC_GPIO_EMC_01_XBAR1_XBAR_IN03 { + pinmux = <0x401f8018 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexio1_flexio02: IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 { + pinmux = <0x401f801c 4 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexpwm4_pwma1: IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA1 { + pinmux = <0x401f801c 1 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio4_io02: IOMUXC_GPIO_EMC_02_GPIO4_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio9_io02: IOMUXC_GPIO_EMC_02_GPIO9_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 2 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_in04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_IN04 { + pinmux = <0x401f801c 3 0x0 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f801c 3 0x0 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexio1_flexio03: IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 { + pinmux = <0x401f8020 4 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexpwm4_pwmb1: IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB1 { + pinmux = <0x401f8020 1 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio4_io03: IOMUXC_GPIO_EMC_03_GPIO4_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio9_io03: IOMUXC_GPIO_EMC_03_GPIO9_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 2 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_in05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_IN05 { + pinmux = <0x401f8020 3 0x0 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8020 3 0x0 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio04: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8024 4 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexpwm4_pwma2: IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA2 { + pinmux = <0x401f8024 1 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio4_io04: IOMUXC_GPIO_EMC_04_GPIO4_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio9_io04: IOMUXC_GPIO_EMC_04_GPIO9_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_data: IOMUXC_GPIO_EMC_04_SAI2_TX_DATA { + pinmux = <0x401f8024 2 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN06 { + pinmux = <0x401f8024 3 0x0 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f8024 3 0x0 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio05: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8028 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexpwm4_pwmb2: IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB2 { + pinmux = <0x401f8028 1 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio4_io05: IOMUXC_GPIO_EMC_05_GPIO4_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio9_io05: IOMUXC_GPIO_EMC_05_GPIO9_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 2 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN07 { + pinmux = <0x401f8028 3 0x0 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8028 3 0x0 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio06: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 { + pinmux = <0x401f802c 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexpwm2_pwma0: IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f802c 1 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio4_io06: IOMUXC_GPIO_EMC_06_GPIO4_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio9_io06: IOMUXC_GPIO_EMC_06_GPIO9_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_bclk: IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK { + pinmux = <0x401f802c 2 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN08 { + pinmux = <0x401f802c 3 0x0 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f802c 3 0x0 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio07: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 { + pinmux = <0x401f8030 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8030 1 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio4_io07: IOMUXC_GPIO_EMC_07_GPIO4_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio9_io07: IOMUXC_GPIO_EMC_07_GPIO9_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_mclk: IOMUXC_GPIO_EMC_07_SAI2_MCLK { + pinmux = <0x401f8030 2 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN09 { + pinmux = <0x401f8030 3 0x0 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8030 3 0x0 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio08: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8034 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexpwm2_pwma1: IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f8034 1 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio4_io08: IOMUXC_GPIO_EMC_08_GPIO4_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio9_io08: IOMUXC_GPIO_EMC_08_GPIO9_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 2 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN17 { + pinmux = <0x401f8034 3 0x0 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8034 3 0x0 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_tx: IOMUXC_GPIO_EMC_09_FLEXCAN2_TX { + pinmux = <0x401f8038 3 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio09: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8038 4 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8038 1 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexspi2_b_ss1_b: IOMUXC_GPIO_EMC_09_FLEXSPI2_B_SS1_B { + pinmux = <0x401f8038 8 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio4_io09: IOMUXC_GPIO_EMC_09_GPIO4_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio9_io09: IOMUXC_GPIO_EMC_09_GPIO9_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_sync: IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC { + pinmux = <0x401f8038 2 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_addr00: IOMUXC_GPIO_EMC_09_SEMC_ADDR00 { + pinmux = <0x401f8038 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexcan2_rx: IOMUXC_GPIO_EMC_10_FLEXCAN2_RX { + pinmux = <0x401f803c 3 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexio1_flexio10: IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 { + pinmux = <0x401f803c 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwma2: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f803c 1 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_10_FLEXSPI2_B_SS0_B { + pinmux = <0x401f803c 8 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio4_io10: IOMUXC_GPIO_EMC_10_GPIO4_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio9_io10: IOMUXC_GPIO_EMC_10_GPIO9_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai2_rx_bclk: IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK { + pinmux = <0x401f803c 2 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_addr01: IOMUXC_GPIO_EMC_10_SEMC_ADDR01 { + pinmux = <0x401f803c 0 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexio1_flexio11: IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 { + pinmux = <0x401f8040 4 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8040 1 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexspi2_b_dqs: IOMUXC_GPIO_EMC_11_FLEXSPI2_B_DQS { + pinmux = <0x401f8040 8 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio4_io11: IOMUXC_GPIO_EMC_11_GPIO4_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio9_io11: IOMUXC_GPIO_EMC_11_GPIO9_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_sda: IOMUXC_GPIO_EMC_11_LPI2C4_SDA { + pinmux = <0x401f8040 2 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_addr02: IOMUXC_GPIO_EMC_11_SEMC_ADDR02 { + pinmux = <0x401f8040 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_usdhc2_reset_b: IOMUXC_GPIO_EMC_11_USDHC2_RESET_B { + pinmux = <0x401f8040 3 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm1_pwma3: IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f8044 4 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexspi2_b_sclk: IOMUXC_GPIO_EMC_12_FLEXSPI2_B_SCLK { + pinmux = <0x401f8044 8 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio4_io12: IOMUXC_GPIO_EMC_12_GPIO4_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio9_io12: IOMUXC_GPIO_EMC_12_GPIO9_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpi2c4_scl: IOMUXC_GPIO_EMC_12_LPI2C4_SCL { + pinmux = <0x401f8044 2 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_addr03: IOMUXC_GPIO_EMC_12_SEMC_ADDR03 { + pinmux = <0x401f8044 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_usdhc1_wp: IOMUXC_GPIO_EMC_12_USDHC1_WP { + pinmux = <0x401f8044 3 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in24: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN24 { + pinmux = <0x401f8044 1 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8048 4 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexspi2_b_data0: IOMUXC_GPIO_EMC_13_FLEXSPI2_B_DATA0 { + pinmux = <0x401f8048 8 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio4_io13: IOMUXC_GPIO_EMC_13_GPIO4_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio9_io13: IOMUXC_GPIO_EMC_13_GPIO9_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart3_tx: IOMUXC_GPIO_EMC_13_LPUART3_TX { + pinmux = <0x401f8048 2 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_mqs_right: IOMUXC_GPIO_EMC_13_MQS_RIGHT { + pinmux = <0x401f8048 3 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_addr04: IOMUXC_GPIO_EMC_13_SEMC_ADDR04 { + pinmux = <0x401f8048 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in25: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN25 { + pinmux = <0x401f8048 1 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_flexspi2_b_data1: IOMUXC_GPIO_EMC_14_FLEXSPI2_B_DATA1 { + pinmux = <0x401f804c 8 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio4_io14: IOMUXC_GPIO_EMC_14_GPIO4_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio9_io14: IOMUXC_GPIO_EMC_14_GPIO9_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart3_rx: IOMUXC_GPIO_EMC_14_LPUART3_RX { + pinmux = <0x401f804c 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_mqs_left: IOMUXC_GPIO_EMC_14_MQS_LEFT { + pinmux = <0x401f804c 3 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_addr05: IOMUXC_GPIO_EMC_14_SEMC_ADDR05 { + pinmux = <0x401f804c 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN19 { + pinmux = <0x401f804c 1 0x0 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f804c 1 0x0 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_flexspi2_b_data2: IOMUXC_GPIO_EMC_15_FLEXSPI2_B_DATA2 { + pinmux = <0x401f8050 8 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio4_io15: IOMUXC_GPIO_EMC_15_GPIO4_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio9_io15: IOMUXC_GPIO_EMC_15_GPIO9_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart3_cts_b: IOMUXC_GPIO_EMC_15_LPUART3_CTS_B { + pinmux = <0x401f8050 2 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_qtimer3_timer0: IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 { + pinmux = <0x401f8050 4 0x0 0 0x401f8240>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr06: IOMUXC_GPIO_EMC_15_SEMC_ADDR06 { + pinmux = <0x401f8050 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_spdif_out: IOMUXC_GPIO_EMC_15_SPDIF_OUT { + pinmux = <0x401f8050 3 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in20: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN20 { + pinmux = <0x401f8050 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_flexspi2_b_data3: IOMUXC_GPIO_EMC_16_FLEXSPI2_B_DATA3 { + pinmux = <0x401f8054 8 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio4_io16: IOMUXC_GPIO_EMC_16_GPIO4_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio9_io16: IOMUXC_GPIO_EMC_16_GPIO9_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_lpuart3_rts_b: IOMUXC_GPIO_EMC_16_LPUART3_RTS_B { + pinmux = <0x401f8054 2 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_qtimer3_timer1: IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 { + pinmux = <0x401f8054 4 0x0 0 0x401f8244>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr07: IOMUXC_GPIO_EMC_16_SEMC_ADDR07 { + pinmux = <0x401f8054 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_spdif_in: IOMUXC_GPIO_EMC_16_SPDIF_IN { + pinmux = <0x401f8054 3 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_xbar1_xbar_in21: IOMUXC_GPIO_EMC_16_XBAR1_XBAR_IN21 { + pinmux = <0x401f8054 1 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexcan1_tx: IOMUXC_GPIO_EMC_17_FLEXCAN1_TX { + pinmux = <0x401f8058 3 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexpwm4_pwma3: IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA3 { + pinmux = <0x401f8058 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio4_io17: IOMUXC_GPIO_EMC_17_GPIO4_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio9_io17: IOMUXC_GPIO_EMC_17_GPIO9_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_lpuart4_cts_b: IOMUXC_GPIO_EMC_17_LPUART4_CTS_B { + pinmux = <0x401f8058 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_qtimer3_timer2: IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 { + pinmux = <0x401f8058 4 0x0 0 0x401f8248>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr08: IOMUXC_GPIO_EMC_17_SEMC_ADDR08 { + pinmux = <0x401f8058 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexcan1_rx: IOMUXC_GPIO_EMC_18_FLEXCAN1_RX { + pinmux = <0x401f805c 3 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexpwm4_pwmb3: IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB3 { + pinmux = <0x401f805c 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio4_io18: IOMUXC_GPIO_EMC_18_GPIO4_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio9_io18: IOMUXC_GPIO_EMC_18_GPIO9_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpuart4_rts_b: IOMUXC_GPIO_EMC_18_LPUART4_RTS_B { + pinmux = <0x401f805c 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_qtimer3_timer3: IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 { + pinmux = <0x401f805c 4 0x0 0 0x401f824c>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr09: IOMUXC_GPIO_EMC_18_SEMC_ADDR09 { + pinmux = <0x401f805c 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_snvs_vio_5_ctl: IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL { + pinmux = <0x401f805c 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_enet_rx_data1: IOMUXC_GPIO_EMC_19_ENET_RX_DATA1 { + pinmux = <0x401f8060 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexpwm2_pwma3: IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA3 { + pinmux = <0x401f8060 1 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio4_io19: IOMUXC_GPIO_EMC_19_GPIO4_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio9_io19: IOMUXC_GPIO_EMC_19_GPIO9_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpuart4_tx: IOMUXC_GPIO_EMC_19_LPUART4_TX { + pinmux = <0x401f8060 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_qtimer2_timer0: IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 { + pinmux = <0x401f8060 4 0x0 0 0x401f8250>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr11: IOMUXC_GPIO_EMC_19_SEMC_ADDR11 { + pinmux = <0x401f8060 0 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_snvs_vio_5_b: IOMUXC_GPIO_EMC_19_SNVS_VIO_5_B { + pinmux = <0x401f8060 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_enet_rx_data0: IOMUXC_GPIO_EMC_20_ENET_RX_DATA0 { + pinmux = <0x401f8064 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB3 { + pinmux = <0x401f8064 1 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio4_io20: IOMUXC_GPIO_EMC_20_GPIO4_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio9_io20: IOMUXC_GPIO_EMC_20_GPIO9_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart4_rx: IOMUXC_GPIO_EMC_20_LPUART4_RX { + pinmux = <0x401f8064 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_qtimer2_timer1: IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 { + pinmux = <0x401f8064 4 0x0 0 0x401f8254>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr12: IOMUXC_GPIO_EMC_20_SEMC_ADDR12 { + pinmux = <0x401f8064 0 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_enet_tx_data1: IOMUXC_GPIO_EMC_21_ENET_TX_DATA1 { + pinmux = <0x401f8068 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm3_pwma3: IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA3 { + pinmux = <0x401f8068 1 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio4_io21: IOMUXC_GPIO_EMC_21_GPIO4_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio9_io21: IOMUXC_GPIO_EMC_21_GPIO9_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpi2c3_sda: IOMUXC_GPIO_EMC_21_LPI2C3_SDA { + pinmux = <0x401f8068 2 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_qtimer2_timer2: IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 { + pinmux = <0x401f8068 4 0x0 0 0x401f8258>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_ba0: IOMUXC_GPIO_EMC_21_SEMC_BA0 { + pinmux = <0x401f8068 0 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_enet_tx_data0: IOMUXC_GPIO_EMC_22_ENET_TX_DATA0 { + pinmux = <0x401f806c 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm3_pwmb3: IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB3 { + pinmux = <0x401f806c 1 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexspi2_a_ss1_b: IOMUXC_GPIO_EMC_22_FLEXSPI2_A_SS1_B { + pinmux = <0x401f806c 8 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio4_io22: IOMUXC_GPIO_EMC_22_GPIO4_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio9_io22: IOMUXC_GPIO_EMC_22_GPIO9_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpi2c3_scl: IOMUXC_GPIO_EMC_22_LPI2C3_SCL { + pinmux = <0x401f806c 2 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_qtimer2_timer3: IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 { + pinmux = <0x401f806c 4 0x0 0 0x401f825c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_ba1: IOMUXC_GPIO_EMC_22_SEMC_BA1 { + pinmux = <0x401f806c 0 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_enet_rx_en: IOMUXC_GPIO_EMC_23_ENET_RX_EN { + pinmux = <0x401f8070 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwma0: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA0 { + pinmux = <0x401f8070 1 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexspi2_a_dqs: IOMUXC_GPIO_EMC_23_FLEXSPI2_A_DQS { + pinmux = <0x401f8070 8 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio4_io23: IOMUXC_GPIO_EMC_23_GPIO4_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio9_io23: IOMUXC_GPIO_EMC_23_GPIO9_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpt1_capture2: IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 { + pinmux = <0x401f8070 4 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart5_tx: IOMUXC_GPIO_EMC_23_LPUART5_TX { + pinmux = <0x401f8070 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr10: IOMUXC_GPIO_EMC_23_SEMC_ADDR10 { + pinmux = <0x401f8070 0 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_enet_tx_en: IOMUXC_GPIO_EMC_24_ENET_TX_EN { + pinmux = <0x401f8074 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB0 { + pinmux = <0x401f8074 1 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_24_FLEXSPI2_A_SS0_B { + pinmux = <0x401f8074 8 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio4_io24: IOMUXC_GPIO_EMC_24_GPIO4_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio9_io24: IOMUXC_GPIO_EMC_24_GPIO9_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpt1_capture1: IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 { + pinmux = <0x401f8074 4 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart5_rx: IOMUXC_GPIO_EMC_24_LPUART5_RX { + pinmux = <0x401f8074 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_cas: IOMUXC_GPIO_EMC_24_SEMC_CAS { + pinmux = <0x401f8074 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_ref_clk: IOMUXC_GPIO_EMC_25_ENET_REF_CLK { + pinmux = <0x401f8078 4 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_tx_clk: IOMUXC_GPIO_EMC_25_ENET_TX_CLK { + pinmux = <0x401f8078 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwma1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA1 { + pinmux = <0x401f8078 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexspi2_a_sclk: IOMUXC_GPIO_EMC_25_FLEXSPI2_A_SCLK { + pinmux = <0x401f8078 8 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio4_io25: IOMUXC_GPIO_EMC_25_GPIO4_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio9_io25: IOMUXC_GPIO_EMC_25_GPIO9_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart6_tx: IOMUXC_GPIO_EMC_25_LPUART6_TX { + pinmux = <0x401f8078 2 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_ras: IOMUXC_GPIO_EMC_25_SEMC_RAS { + pinmux = <0x401f8078 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_enet_rx_er: IOMUXC_GPIO_EMC_26_ENET_RX_ER { + pinmux = <0x401f807c 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio12: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 { + pinmux = <0x401f807c 4 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB1 { + pinmux = <0x401f807c 1 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexspi2_a_data0: IOMUXC_GPIO_EMC_26_FLEXSPI2_A_DATA0 { + pinmux = <0x401f807c 8 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio4_io26: IOMUXC_GPIO_EMC_26_GPIO4_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio9_io26: IOMUXC_GPIO_EMC_26_GPIO9_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart6_rx: IOMUXC_GPIO_EMC_26_LPUART6_RX { + pinmux = <0x401f807c 2 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_clk: IOMUXC_GPIO_EMC_26_SEMC_CLK { + pinmux = <0x401f807c 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio13: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8080 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwma2: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA2 { + pinmux = <0x401f8080 1 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexspi2_a_data1: IOMUXC_GPIO_EMC_27_FLEXSPI2_A_DATA1 { + pinmux = <0x401f8080 8 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio4_io27: IOMUXC_GPIO_EMC_27_GPIO4_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio9_io27: IOMUXC_GPIO_EMC_27_GPIO9_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpspi1_sck: IOMUXC_GPIO_EMC_27_LPSPI1_SCK { + pinmux = <0x401f8080 3 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart5_rts_b: IOMUXC_GPIO_EMC_27_LPUART5_RTS_B { + pinmux = <0x401f8080 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_cke: IOMUXC_GPIO_EMC_27_SEMC_CKE { + pinmux = <0x401f8080 0 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexio1_flexio14: IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8084 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB2 { + pinmux = <0x401f8084 1 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexspi2_a_data2: IOMUXC_GPIO_EMC_28_FLEXSPI2_A_DATA2 { + pinmux = <0x401f8084 8 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio4_io28: IOMUXC_GPIO_EMC_28_GPIO4_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio9_io28: IOMUXC_GPIO_EMC_28_GPIO9_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpspi1_sdo: IOMUXC_GPIO_EMC_28_LPSPI1_SDO { + pinmux = <0x401f8084 3 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpuart5_cts_b: IOMUXC_GPIO_EMC_28_LPUART5_CTS_B { + pinmux = <0x401f8084 2 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_we: IOMUXC_GPIO_EMC_28_SEMC_WE { + pinmux = <0x401f8084 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexio1_flexio15: IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 { + pinmux = <0x401f8088 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm3_pwma0: IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA0 { + pinmux = <0x401f8088 1 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexspi2_a_data3: IOMUXC_GPIO_EMC_29_FLEXSPI2_A_DATA3 { + pinmux = <0x401f8088 8 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio4_io29: IOMUXC_GPIO_EMC_29_GPIO4_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio9_io29: IOMUXC_GPIO_EMC_29_GPIO9_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpspi1_sdi: IOMUXC_GPIO_EMC_29_LPSPI1_SDI { + pinmux = <0x401f8088 3 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpuart6_rts_b: IOMUXC_GPIO_EMC_29_LPUART6_RTS_B { + pinmux = <0x401f8088 2 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cs0: IOMUXC_GPIO_EMC_29_SEMC_CS0 { + pinmux = <0x401f8088 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm3_pwmb0: IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB0 { + pinmux = <0x401f808c 1 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio4_io30: IOMUXC_GPIO_EMC_30_GPIO4_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio9_io30: IOMUXC_GPIO_EMC_30_GPIO9_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpspi1_pcs0: IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 { + pinmux = <0x401f808c 3 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart6_cts_b: IOMUXC_GPIO_EMC_30_LPUART6_CTS_B { + pinmux = <0x401f808c 2 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_data08: IOMUXC_GPIO_EMC_30_SEMC_DATA08 { + pinmux = <0x401f808c 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm3_pwma1: IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA1 { + pinmux = <0x401f8090 1 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio4_io31: IOMUXC_GPIO_EMC_31_GPIO4_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio9_io31: IOMUXC_GPIO_EMC_31_GPIO9_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpspi1_pcs1: IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 { + pinmux = <0x401f8090 3 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart7_tx: IOMUXC_GPIO_EMC_31_LPUART7_TX { + pinmux = <0x401f8090 2 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_data09: IOMUXC_GPIO_EMC_31_SEMC_DATA09 { + pinmux = <0x401f8090 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ccm_pmic_rdy: IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY { + pinmux = <0x401f8094 3 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_flexpwm3_pwmb1: IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB1 { + pinmux = <0x401f8094 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io18: IOMUXC_GPIO_EMC_32_GPIO3_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio8_io18: IOMUXC_GPIO_EMC_32_GPIO8_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart7_rx: IOMUXC_GPIO_EMC_32_LPUART7_RX { + pinmux = <0x401f8094 2 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data10: IOMUXC_GPIO_EMC_32_SEMC_DATA10 { + pinmux = <0x401f8094 0 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_flexpwm3_pwma2: IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA2 { + pinmux = <0x401f8098 1 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io19: IOMUXC_GPIO_EMC_33_GPIO3_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio8_io19: IOMUXC_GPIO_EMC_33_GPIO8_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_rx_data: IOMUXC_GPIO_EMC_33_SAI3_RX_DATA { + pinmux = <0x401f8098 3 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data11: IOMUXC_GPIO_EMC_33_SEMC_DATA11 { + pinmux = <0x401f8098 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_usdhc1_reset_b: IOMUXC_GPIO_EMC_33_USDHC1_RESET_B { + pinmux = <0x401f8098 2 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_flexpwm3_pwmb2: IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB2 { + pinmux = <0x401f809c 1 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io20: IOMUXC_GPIO_EMC_34_GPIO3_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio8_io20: IOMUXC_GPIO_EMC_34_GPIO8_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_rx_sync: IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC { + pinmux = <0x401f809c 3 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data12: IOMUXC_GPIO_EMC_34_SEMC_DATA12 { + pinmux = <0x401f809c 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_usdhc1_vselect: IOMUXC_GPIO_EMC_34_USDHC1_VSELECT { + pinmux = <0x401f809c 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io21: IOMUXC_GPIO_EMC_35_GPIO3_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio8_io21: IOMUXC_GPIO_EMC_35_GPIO8_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpt1_compare1: IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 { + pinmux = <0x401f80a0 2 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_sai3_rx_bclk: IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK { + pinmux = <0x401f80a0 3 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data13: IOMUXC_GPIO_EMC_35_SEMC_DATA13 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc1_cd_b: IOMUXC_GPIO_EMC_35_USDHC1_CD_B { + pinmux = <0x401f80a0 6 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_in18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_IN18 { + pinmux = <0x401f80a0 1 0x0 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80a0 1 0x0 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexcan3_tx: IOMUXC_GPIO_EMC_36_FLEXCAN3_TX { + pinmux = <0x401f80a4 9 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io22: IOMUXC_GPIO_EMC_36_GPIO3_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio8_io22: IOMUXC_GPIO_EMC_36_GPIO8_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpt1_compare2: IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 { + pinmux = <0x401f80a4 2 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_sai3_tx_data: IOMUXC_GPIO_EMC_36_SAI3_TX_DATA { + pinmux = <0x401f80a4 3 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data14: IOMUXC_GPIO_EMC_36_SEMC_DATA14 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 6 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_xbar1_xbar_in22: IOMUXC_GPIO_EMC_36_XBAR1_XBAR_IN22 { + pinmux = <0x401f80a4 1 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexcan3_rx: IOMUXC_GPIO_EMC_37_FLEXCAN3_RX { + pinmux = <0x401f80a8 9 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io23: IOMUXC_GPIO_EMC_37_GPIO3_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio8_io23: IOMUXC_GPIO_EMC_37_GPIO8_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpt1_compare3: IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 { + pinmux = <0x401f80a8 2 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_sai3_mclk: IOMUXC_GPIO_EMC_37_SAI3_MCLK { + pinmux = <0x401f80a8 3 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data15: IOMUXC_GPIO_EMC_37_SEMC_DATA15 { + pinmux = <0x401f80a8 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc2_wp: IOMUXC_GPIO_EMC_37_USDHC2_WP { + pinmux = <0x401f80a8 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_xbar1_xbar_in23: IOMUXC_GPIO_EMC_37_XBAR1_XBAR_IN23 { + pinmux = <0x401f80a8 1 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm1_pwma3: IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA3 { + pinmux = <0x401f80ac 1 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io24: IOMUXC_GPIO_EMC_38_GPIO3_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio8_io24: IOMUXC_GPIO_EMC_38_GPIO8_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart8_tx: IOMUXC_GPIO_EMC_38_LPUART8_TX { + pinmux = <0x401f80ac 2 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_sai3_tx_bclk: IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK { + pinmux = <0x401f80ac 3 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_dm1: IOMUXC_GPIO_EMC_38_SEMC_DM1 { + pinmux = <0x401f80ac 0 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc2_vselect: IOMUXC_GPIO_EMC_38_USDHC2_VSELECT { + pinmux = <0x401f80ac 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB3 { + pinmux = <0x401f80b0 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io25: IOMUXC_GPIO_EMC_39_GPIO3_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio8_io25: IOMUXC_GPIO_EMC_39_GPIO8_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart8_rx: IOMUXC_GPIO_EMC_39_LPUART8_RX { + pinmux = <0x401f80b0 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_sai3_tx_sync: IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC { + pinmux = <0x401f80b0 3 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs: IOMUXC_GPIO_EMC_39_SEMC_DQS { + pinmux = <0x401f80b0 0 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs4: IOMUXC_GPIO_EMC_39_SEMC_DQS4 { + pinmux = <0x401f80b0 9 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usdhc2_cd_b: IOMUXC_GPIO_EMC_39_USDHC2_CD_B { + pinmux = <0x401f80b0 6 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdc: IOMUXC_GPIO_EMC_40_ENET_MDC { + pinmux = <0x401f80b4 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io26: IOMUXC_GPIO_EMC_40_GPIO3_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio8_io26: IOMUXC_GPIO_EMC_40_GPIO8_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt2_capture2: IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 { + pinmux = <0x401f80b4 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_lpspi1_pcs2: IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 { + pinmux = <0x401f80b4 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_clk5: IOMUXC_GPIO_EMC_40_SEMC_CLK5 { + pinmux = <0x401f80b4 9 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_rdy: IOMUXC_GPIO_EMC_40_SEMC_RDY { + pinmux = <0x401f80b4 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usdhc2_reset_b: IOMUXC_GPIO_EMC_40_USDHC2_RESET_B { + pinmux = <0x401f80b4 6 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdio: IOMUXC_GPIO_EMC_41_ENET_MDIO { + pinmux = <0x401f80b8 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io27: IOMUXC_GPIO_EMC_41_GPIO3_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio8_io27: IOMUXC_GPIO_EMC_41_GPIO8_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt2_capture1: IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 { + pinmux = <0x401f80b8 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_lpspi1_pcs3: IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 { + pinmux = <0x401f80b8 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_csx0: IOMUXC_GPIO_EMC_41_SEMC_CSX0 { + pinmux = <0x401f80b8 0 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usdhc1_vselect: IOMUXC_GPIO_EMC_41_USDHC1_VSELECT { + pinmux = <0x401f80b8 6 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexpwm1_pwma0: IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA0 { + pinmux = <0x401f81bc 1 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f81bc 6 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io12: IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio8_io12: IOMUXC_GPIO_SD_B0_00_GPIO8_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f81bc 2 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpspi1_sck: IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK { + pinmux = <0x401f81bc 4 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_semc_dqs4: IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 { + pinmux = <0x401f81bc 9 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_cmd: IOMUXC_GPIO_SD_B0_00_USDHC1_CMD { + pinmux = <0x401f81bc 0 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN04 { + pinmux = <0x401f81bc 3 0x0 0 0x401f83ac>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f81bc 3 0x0 0 0x401f83ac>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexpwm1_pwmb0: IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB0 { + pinmux = <0x401f81c0 1 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f81c0 6 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io13: IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio8_io13: IOMUXC_GPIO_SD_B0_01_GPIO8_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f81c0 2 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 { + pinmux = <0x401f81c0 4 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_clk: IOMUXC_GPIO_SD_B0_01_USDHC1_CLK { + pinmux = <0x401f81c0 0 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN05 { + pinmux = <0x401f81c0 3 0x0 0 0x401f83b0>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f81c0 3 0x0 0 0x401f83b0>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_flexpwm1_pwma1: IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA1 { + pinmux = <0x401f81c4 1 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io14: IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio8_io14: IOMUXC_GPIO_SD_B0_02_GPIO8_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sdo: IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO { + pinmux = <0x401f81c4 4 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart8_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B { + pinmux = <0x401f81c4 2 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_semc_clk5: IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 { + pinmux = <0x401f81c4 9 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_data0: IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 { + pinmux = <0x401f81c4 0 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN06 { + pinmux = <0x401f81c4 3 0x0 0 0x401f83b4>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f81c4 3 0x0 0 0x401f83b4>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_flexpwm1_pwmb1: IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB1 { + pinmux = <0x401f81c8 1 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io15: IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio8_io15: IOMUXC_GPIO_SD_B0_03_GPIO8_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_sdi: IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI { + pinmux = <0x401f81c8 4 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart8_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B { + pinmux = <0x401f81c8 2 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_semc_clk6: IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 { + pinmux = <0x401f81c8 9 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_data1: IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 { + pinmux = <0x401f81c8 0 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_in07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_IN07 { + pinmux = <0x401f81c8 3 0x0 0 0x401f83b8>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_inout07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f81c8 3 0x0 0 0x401f83b8>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_ccm_clko1: IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 { + pinmux = <0x401f81cc 6 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexpwm1_pwma2: IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA2 { + pinmux = <0x401f81cc 1 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f81cc 4 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io16: IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio8_io16: IOMUXC_GPIO_SD_B0_04_GPIO8_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart8_tx: IOMUXC_GPIO_SD_B0_04_LPUART8_TX { + pinmux = <0x401f81cc 2 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data2: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 { + pinmux = <0x401f81cc 0 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_in08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_IN08 { + pinmux = <0x401f81cc 3 0x0 0 0x401f83bc>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_inout08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f81cc 3 0x0 0 0x401f83bc>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_ccm_clko2: IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 { + pinmux = <0x401f81d0 6 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexpwm1_pwmb2: IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB2 { + pinmux = <0x401f81d0 1 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f81d0 4 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io17: IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio8_io17: IOMUXC_GPIO_SD_B0_05_GPIO8_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart8_rx: IOMUXC_GPIO_SD_B0_05_LPUART8_RX { + pinmux = <0x401f81d0 2 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data3: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 { + pinmux = <0x401f81d0 0 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_in09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_IN09 { + pinmux = <0x401f81d0 3 0x0 0 0x401f83c0>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_inout09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f81d0 3 0x0 0 0x401f83c0>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f81d4 2 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f81d4 1 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io00: IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio8_io00: IOMUXC_GPIO_SD_B1_00_GPIO8_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart4_tx: IOMUXC_GPIO_SD_B1_00_LPUART4_TX { + pinmux = <0x401f81d4 4 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai1_tx_data3: IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA3 { + pinmux = <0x401f81d4 3 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai3_rx_data: IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA { + pinmux = <0x401f81d4 8 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data3: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 { + pinmux = <0x401f81d4 0 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f81d8 2 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_data2: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 { + pinmux = <0x401f81d8 1 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io01: IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio8_io01: IOMUXC_GPIO_SD_B1_01_GPIO8_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart4_rx: IOMUXC_GPIO_SD_B1_01_LPUART4_RX { + pinmux = <0x401f81d8 4 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai1_tx_data2: IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA2 { + pinmux = <0x401f81d8 3 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai3_tx_data: IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA { + pinmux = <0x401f81d8 8 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data2: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 { + pinmux = <0x401f81d8 0 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_wait: IOMUXC_GPIO_SD_B1_02_CCM_WAIT { + pinmux = <0x401f81dc 6 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexcan1_tx: IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX { + pinmux = <0x401f81dc 4 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f81dc 2 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data1: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 { + pinmux = <0x401f81dc 1 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io02: IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio8_io02: IOMUXC_GPIO_SD_B1_02_GPIO8_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai1_tx_data1: IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA1 { + pinmux = <0x401f81dc 3 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai3_tx_sync: IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC { + pinmux = <0x401f81dc 8 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_data1: IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 { + pinmux = <0x401f81dc 0 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_03_CCM_PMIC_RDY { + pinmux = <0x401f81e0 6 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexcan1_rx: IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX { + pinmux = <0x401f81e0 4 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f81e0 2 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data0: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 { + pinmux = <0x401f81e0 1 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io03: IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio8_io03: IOMUXC_GPIO_SD_B1_03_GPIO8_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai1_mclk: IOMUXC_GPIO_SD_B1_03_SAI1_MCLK { + pinmux = <0x401f81e0 3 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK { + pinmux = <0x401f81e0 8 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_data0: IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 { + pinmux = <0x401f81e0 0 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_stop: IOMUXC_GPIO_SD_B1_04_CCM_STOP { + pinmux = <0x401f81e4 6 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI_A_SS1_B { + pinmux = <0x401f81e4 4 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK { + pinmux = <0x401f81e4 1 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io04: IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio8_io04: IOMUXC_GPIO_SD_B1_04_GPIO8_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_lpi2c1_scl: IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL { + pinmux = <0x401f81e4 2 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai1_rx_sync: IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f81e4 3 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai3_mclk: IOMUXC_GPIO_SD_B1_04_SAI3_MCLK { + pinmux = <0x401f81e4 8 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_clk: IOMUXC_GPIO_SD_B1_04_USDHC2_CLK { + pinmux = <0x401f81e4 0 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f81e8 1 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f81e8 4 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io05: IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio8_io05: IOMUXC_GPIO_SD_B1_05_GPIO8_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_lpi2c1_sda: IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA { + pinmux = <0x401f81e8 2 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai1_rx_bclk: IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK { + pinmux = <0x401f81e8 3 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_rx_sync: IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC { + pinmux = <0x401f81e8 8 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_cmd: IOMUXC_GPIO_SD_B1_05_USDHC2_CMD { + pinmux = <0x401f81e8 0 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B { + pinmux = <0x401f81ec 1 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io06: IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio8_io06: IOMUXC_GPIO_SD_B1_06_GPIO8_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f81ec 4 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpuart7_cts_b: IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B { + pinmux = <0x401f81ec 2 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai1_rx_data0: IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA0 { + pinmux = <0x401f81ec 3 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK { + pinmux = <0x401f81ec 8 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B { + pinmux = <0x401f81ec 0 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f81f0 1 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io07: IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio8_io07: IOMUXC_GPIO_SD_B1_07_GPIO8_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f81f0 4 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpuart7_rts_b: IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B { + pinmux = <0x401f81f0 2 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai1_tx_data0: IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA0 { + pinmux = <0x401f81f0 3 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_semc_csx1: IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 { + pinmux = <0x401f81f0 0 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f81f4 1 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io08: IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio8_io08: IOMUXC_GPIO_SD_B1_08_GPIO8_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f81f4 4 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpuart7_tx: IOMUXC_GPIO_SD_B1_08_LPUART7_TX { + pinmux = <0x401f81f4 2 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai1_tx_bclk: IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK { + pinmux = <0x401f81f4 3 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_semc_csx2: IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 { + pinmux = <0x401f81f4 6 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f81f4 0 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data1: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 { + pinmux = <0x401f81f8 1 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io09: IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio8_io09: IOMUXC_GPIO_SD_B1_09_GPIO8_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f81f8 4 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpuart7_rx: IOMUXC_GPIO_SD_B1_09_LPUART7_RX { + pinmux = <0x401f81f8 2 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai1_tx_sync: IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC { + pinmux = <0x401f81f8 3 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f81f8 0 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data2: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 { + pinmux = <0x401f81fc 1 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io10: IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio8_io10: IOMUXC_GPIO_SD_B1_10_GPIO8_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpi2c2_sda: IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA { + pinmux = <0x401f81fc 3 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f81fc 4 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpuart2_rx: IOMUXC_GPIO_SD_B1_10_LPUART2_RX { + pinmux = <0x401f81fc 2 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f81fc 0 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_data3: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 { + pinmux = <0x401f8200 1 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io11: IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio8_io11: IOMUXC_GPIO_SD_B1_11_GPIO8_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpi2c2_scl: IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL { + pinmux = <0x401f8200 3 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8200 4 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpuart2_tx: IOMUXC_GPIO_SD_B1_11_LPUART2_TX { + pinmux = <0x401f8200 2 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8200 0 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x0 0 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1041xjm5b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1041xjm5b-pinctrl.dtsi new file mode 100644 index 000000000..9b2cbc8ff --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1041xjm5b-pinctrl.dtsi @@ -0,0 +1,3116 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1041XJM5B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_tx_data3: IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA3 { + pinmux = <0x401f80cc 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio6_io04: IOMUXC_GPIO_AD_B0_04_GPIO6_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_mqs_right: IOMUXC_GPIO_AD_B0_04_MQS_RIGHT { + pinmux = <0x401f80cc 1 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_pit_trigger0: IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER0 { + pinmux = <0x401f80cc 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_sai2_tx_sync: IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC { + pinmux = <0x401f80cc 3 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_src_boot_mode0: IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE0 { + pinmux = <0x401f80cc 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_tx_data2: IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA2 { + pinmux = <0x401f80d0 2 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio6_io05: IOMUXC_GPIO_AD_B0_05_GPIO6_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_mqs_left: IOMUXC_GPIO_AD_B0_05_MQS_LEFT { + pinmux = <0x401f80d0 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_sai2_tx_bclk: IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f80d0 3 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_src_boot_mode1: IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE1 { + pinmux = <0x401f80d0 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_IN17 { + pinmux = <0x401f80d0 6 0x0 0 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80d0 6 0x0 0 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_enet_rx_clk: IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK { + pinmux = <0x401f80d4 2 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio6_io06: IOMUXC_GPIO_AD_B0_06_GPIO6_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpt2_compare1: IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 { + pinmux = <0x401f80d4 1 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_jtag_tms: IOMUXC_GPIO_AD_B0_06_JTAG_TMS { + pinmux = <0x401f80d4 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_sai2_rx_bclk: IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK { + pinmux = <0x401f80d4 3 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_in18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_IN18 { + pinmux = <0x401f80d4 6 0x0 0 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_inout18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80d4 6 0x0 0 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_1588_event3_out: IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT { + pinmux = <0x401f80d8 7 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_tx_er: IOMUXC_GPIO_AD_B0_07_ENET_TX_ER { + pinmux = <0x401f80d8 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio6_io07: IOMUXC_GPIO_AD_B0_07_GPIO6_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpt2_compare2: IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 { + pinmux = <0x401f80d8 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_jtag_tck: IOMUXC_GPIO_AD_B0_07_JTAG_TCK { + pinmux = <0x401f80d8 0 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_sai2_rx_sync: IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC { + pinmux = <0x401f80d8 3 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_in19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_IN19 { + pinmux = <0x401f80d8 6 0x0 0 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_inout19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80d8 6 0x0 0 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_1588_event3_in: IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN { + pinmux = <0x401f80dc 7 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_rx_data3: IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA3 { + pinmux = <0x401f80dc 2 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio6_io08: IOMUXC_GPIO_AD_B0_08_GPIO6_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpt2_compare3: IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 { + pinmux = <0x401f80dc 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_jtag_mod: IOMUXC_GPIO_AD_B0_08_JTAG_MOD { + pinmux = <0x401f80dc 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_sai2_rx_data: IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA { + pinmux = <0x401f80dc 3 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_xbar1_xbar_in20: IOMUXC_GPIO_AD_B0_08_XBAR1_XBAR_IN20 { + pinmux = <0x401f80dc 6 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data2: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA2 { + pinmux = <0x401f80e0 2 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA3 { + pinmux = <0x401f80e0 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio6_io09: IOMUXC_GPIO_AD_B0_09_GPIO6_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpt2_clk: IOMUXC_GPIO_AD_B0_09_GPT2_CLK { + pinmux = <0x401f80e0 7 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_jtag_tdi: IOMUXC_GPIO_AD_B0_09_JTAG_TDI { + pinmux = <0x401f80e0 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_sai2_tx_data: IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA { + pinmux = <0x401f80e0 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_semc_dqs4: IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 { + pinmux = <0x401f80e0 9 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_xbar1_xbar_in21: IOMUXC_GPIO_AD_B0_09_XBAR1_XBAR_IN21 { + pinmux = <0x401f80e0 6 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_swo: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO { + pinmux = <0x401f80e4 9 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80e4 7 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_crs: IOMUXC_GPIO_AD_B0_10_ENET_CRS { + pinmux = <0x401f80e4 2 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexcan3_tx: IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX { + pinmux = <0x401f80e4 8 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm1_pwma3: IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA3 { + pinmux = <0x401f80e4 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio6_io10: IOMUXC_GPIO_AD_B0_10_GPIO6_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_jtag_tdo: IOMUXC_GPIO_AD_B0_10_JTAG_TDO { + pinmux = <0x401f80e4 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_sai2_mclk: IOMUXC_GPIO_AD_B0_10_SAI2_MCLK { + pinmux = <0x401f80e4 3 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_xbar1_xbar_in22: IOMUXC_GPIO_AD_B0_10_XBAR1_XBAR_IN22 { + pinmux = <0x401f80e4 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN { + pinmux = <0x401f80e8 7 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_col: IOMUXC_GPIO_AD_B0_11_ENET_COL { + pinmux = <0x401f80e8 2 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexcan3_rx: IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX { + pinmux = <0x401f80e8 8 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB3 { + pinmux = <0x401f80e8 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio6_io11: IOMUXC_GPIO_AD_B0_11_GPIO6_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_jtag_trstb: IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB { + pinmux = <0x401f80e8 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_semc_clk6: IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 { + pinmux = <0x401f80e8 9 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_wdog1_b: IOMUXC_GPIO_AD_B0_11_WDOG1_B { + pinmux = <0x401f80e8 3 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_xbar1_xbar_in23: IOMUXC_GPIO_AD_B0_11_XBAR1_XBAR_IN23 { + pinmux = <0x401f80e8 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in1: IOMUXC_GPIO_AD_B0_12_ADC1_IN1 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_nmi: IOMUXC_GPIO_AD_B0_12_ARM_NMI { + pinmux = <0x401f80ec 7 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_12_CCM_PMIC_RDY { + pinmux = <0x401f80ec 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_1588_event1_out: IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT { + pinmux = <0x401f80ec 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm1_pwmx2: IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX2 { + pinmux = <0x401f80ec 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio6_io12: IOMUXC_GPIO_AD_B0_12_GPIO6_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpi2c4_scl: IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL { + pinmux = <0x401f80ec 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart1_tx: IOMUXC_GPIO_AD_B0_12_LPUART1_TX { + pinmux = <0x401f80ec 2 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_wdog2_b: IOMUXC_GPIO_AD_B0_12_WDOG2_B { + pinmux = <0x401f80ec 3 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_acmp1_in2: IOMUXC_GPIO_AD_B0_13_ACMP1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc1_in2: IOMUXC_GPIO_AD_B0_13_ADC1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_1588_event1_in: IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN { + pinmux = <0x401f80f0 6 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ewm_out_b: IOMUXC_GPIO_AD_B0_13_EWM_OUT_B { + pinmux = <0x401f80f0 3 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm1_pwmx3: IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX3 { + pinmux = <0x401f80f0 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio6_io13: IOMUXC_GPIO_AD_B0_13_GPIO6_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpt1_clk: IOMUXC_GPIO_AD_B0_13_GPT1_CLK { + pinmux = <0x401f80f0 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpi2c4_sda: IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA { + pinmux = <0x401f80f0 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart1_rx: IOMUXC_GPIO_AD_B0_13_LPUART1_RX { + pinmux = <0x401f80f0 2 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ref_24m_out: IOMUXC_GPIO_AD_B0_13_REF_24M_OUT { + pinmux = <0x401f80f0 7 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in2: IOMUXC_GPIO_AD_B0_14_ACMP2_IN2 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in3: IOMUXC_GPIO_AD_B0_14_ADC1_IN3 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80f4 3 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan3_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX { + pinmux = <0x401f80f4 8 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio6_io14: IOMUXC_GPIO_AD_B0_14_GPIO6_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B { + pinmux = <0x401f80f4 2 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_xbar1_xbar_in24: IOMUXC_GPIO_AD_B0_14_XBAR1_XBAR_IN24 { + pinmux = <0x401f80f4 1 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in2: IOMUXC_GPIO_AD_B0_15_ACMP3_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in4: IOMUXC_GPIO_AD_B0_15_ADC1_IN4 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f80f8 3 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 6 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan3_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX { + pinmux = <0x401f80f8 8 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio6_io15: IOMUXC_GPIO_AD_B0_15_GPIO6_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B { + pinmux = <0x401f80f8 2 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb: IOMUXC_GPIO_AD_B0_15_WDOG1_RST_B_DEB { + pinmux = <0x401f80f8 7 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_xbar1_xbar_in25: IOMUXC_GPIO_AD_B0_15_XBAR1_XBAR_IN25 { + pinmux = <0x401f80f8 1 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp4_in2: IOMUXC_GPIO_AD_B1_00_ACMP4_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc1_in5: IOMUXC_GPIO_AD_B1_00_ADC1_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc2_in5: IOMUXC_GPIO_AD_B1_00_ADC2_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio3_flexio00: IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 { + pinmux = <0x401f80fc 9 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio6_io16: IOMUXC_GPIO_AD_B1_00_GPIO6_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpi2c1_scl: IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL { + pinmux = <0x401f80fc 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B { + pinmux = <0x401f80fc 2 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_qtimer3_timer0: IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 { + pinmux = <0x401f80fc 1 0x0 0 0x401f82ec>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usdhc1_wp: IOMUXC_GPIO_AD_B1_00_USDHC1_WP { + pinmux = <0x401f80fc 6 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_wdog1_b: IOMUXC_GPIO_AD_B1_00_WDOG1_B { + pinmux = <0x401f80fc 4 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp1_in0: IOMUXC_GPIO_AD_B1_01_ACMP1_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in0: IOMUXC_GPIO_AD_B1_01_ACMP2_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp3_in0: IOMUXC_GPIO_AD_B1_01_ACMP3_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp4_in0: IOMUXC_GPIO_AD_B1_01_ACMP4_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in6: IOMUXC_GPIO_AD_B1_01_ADC1_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc2_in6: IOMUXC_GPIO_AD_B1_01_ADC2_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_01_CCM_PMIC_RDY { + pinmux = <0x401f8100 4 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio3_flexio01: IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 { + pinmux = <0x401f8100 9 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio6_io17: IOMUXC_GPIO_AD_B1_01_GPIO6_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpi2c1_sda: IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA { + pinmux = <0x401f8100 3 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B { + pinmux = <0x401f8100 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_qtimer3_timer1: IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 { + pinmux = <0x401f8100 1 0x0 0 0x401f82f0>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR { + pinmux = <0x401f8100 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usdhc1_vselect: IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT { + pinmux = <0x401f8100 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp1_in3: IOMUXC_GPIO_AD_B1_02_ACMP1_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc1_in7: IOMUXC_GPIO_AD_B1_02_ADC1_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in7: IOMUXC_GPIO_AD_B1_02_ADC2_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT { + pinmux = <0x401f8104 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio3_flexio02: IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 { + pinmux = <0x401f8104 9 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio6_io18: IOMUXC_GPIO_AD_B1_02_GPIO6_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpt2_clk: IOMUXC_GPIO_AD_B1_02_GPT2_CLK { + pinmux = <0x401f8104 8 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpuart2_tx: IOMUXC_GPIO_AD_B1_02_LPUART2_TX { + pinmux = <0x401f8104 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_qtimer3_timer2: IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 { + pinmux = <0x401f8104 1 0x0 0 0x401f82f4>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_spdif_out: IOMUXC_GPIO_AD_B1_02_SPDIF_OUT { + pinmux = <0x401f8104 3 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usb_otg1_id: IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID { + pinmux = <0x401f8104 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B { + pinmux = <0x401f8104 6 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp2_in3: IOMUXC_GPIO_AD_B1_03_ACMP2_IN3 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in8: IOMUXC_GPIO_AD_B1_03_ADC1_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc2_in8: IOMUXC_GPIO_AD_B1_03_ADC2_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN { + pinmux = <0x401f8108 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio3_flexio03: IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 { + pinmux = <0x401f8108 9 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio6_io19: IOMUXC_GPIO_AD_B1_03_GPIO6_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpt2_capture1: IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 { + pinmux = <0x401f8108 8 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpuart2_rx: IOMUXC_GPIO_AD_B1_03_LPUART2_RX { + pinmux = <0x401f8108 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_qtimer3_timer3: IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 { + pinmux = <0x401f8108 1 0x0 0 0x401f82f8>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_spdif_in: IOMUXC_GPIO_AD_B1_03_SPDIF_IN { + pinmux = <0x401f8108 3 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usb_otg1_oc: IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC { + pinmux = <0x401f8108 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B { + pinmux = <0x401f8108 6 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp3_in3: IOMUXC_GPIO_AD_B1_04_ACMP3_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc1_in9: IOMUXC_GPIO_AD_B1_04_ADC1_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in9: IOMUXC_GPIO_AD_B1_04_ADC2_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_enet_mdc: IOMUXC_GPIO_AD_B1_04_ENET_MDC { + pinmux = <0x401f810c 1 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio3_flexio04: IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 { + pinmux = <0x401f810c 9 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_b_data3: IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 { + pinmux = <0x401f810c 0 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio6_io20: IOMUXC_GPIO_AD_B1_04_GPIO6_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpt2_capture2: IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 { + pinmux = <0x401f810c 8 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpuart3_cts_b: IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B { + pinmux = <0x401f810c 2 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_spdif_sr_clk: IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK { + pinmux = <0x401f810c 3 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_usdhc2_data0: IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f810c 6 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp4_in3: IOMUXC_GPIO_AD_B1_05_ACMP4_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in10: IOMUXC_GPIO_AD_B1_05_ADC1_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in10: IOMUXC_GPIO_AD_B1_05_ADC2_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_enet_mdio: IOMUXC_GPIO_AD_B1_05_ENET_MDIO { + pinmux = <0x401f8110 1 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio3_flexio05: IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 { + pinmux = <0x401f8110 9 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_b_data2: IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 { + pinmux = <0x401f8110 0 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio6_io21: IOMUXC_GPIO_AD_B1_05_GPIO6_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpt2_compare1: IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 { + pinmux = <0x401f8110 8 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpuart3_rts_b: IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B { + pinmux = <0x401f8110 2 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_spdif_out: IOMUXC_GPIO_AD_B1_05_SPDIF_OUT { + pinmux = <0x401f8110 3 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc2_data1: IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f8110 6 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp1_in1: IOMUXC_GPIO_AD_B1_06_ACMP1_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp2_in1: IOMUXC_GPIO_AD_B1_06_ACMP2_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in1: IOMUXC_GPIO_AD_B1_06_ACMP3_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp4_in1: IOMUXC_GPIO_AD_B1_06_ACMP4_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in11: IOMUXC_GPIO_AD_B1_06_ADC1_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in11: IOMUXC_GPIO_AD_B1_06_ADC2_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio3_flexio06: IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 { + pinmux = <0x401f8114 9 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexspi_b_data1: IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 { + pinmux = <0x401f8114 0 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio6_io22: IOMUXC_GPIO_AD_B1_06_GPIO6_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpt2_compare2: IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 { + pinmux = <0x401f8114 8 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpi2c3_sda: IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA { + pinmux = <0x401f8114 1 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart3_tx: IOMUXC_GPIO_AD_B1_06_LPUART3_TX { + pinmux = <0x401f8114 2 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_spdif_lock: IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK { + pinmux = <0x401f8114 3 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc2_data2: IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 { + pinmux = <0x401f8114 6 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp1_in5: IOMUXC_GPIO_AD_B1_07_ACMP1_IN5 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in12: IOMUXC_GPIO_AD_B1_07_ADC1_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in12: IOMUXC_GPIO_AD_B1_07_ADC2_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio3_flexio07: IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 { + pinmux = <0x401f8118 9 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexspi_b_data0: IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 { + pinmux = <0x401f8118 0 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio6_io23: IOMUXC_GPIO_AD_B1_07_GPIO6_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpt2_compare3: IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 { + pinmux = <0x401f8118 8 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpi2c3_scl: IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL { + pinmux = <0x401f8118 1 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart3_rx: IOMUXC_GPIO_AD_B1_07_LPUART3_RX { + pinmux = <0x401f8118 2 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_spdif_ext_clk: IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK { + pinmux = <0x401f8118 3 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc2_data3: IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 { + pinmux = <0x401f8118 6 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_flexio2_flexio00: IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 { + pinmux = <0x401f813c 4 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio2_io00: IOMUXC_GPIO_B0_00_GPIO2_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio7_io00: IOMUXC_GPIO_B0_00_GPIO7_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lpspi3_pcs0: IOMUXC_GPIO_B0_00_LPSPI3_PCS0 { + pinmux = <0x401f813c 3 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_mqs_right: IOMUXC_GPIO_B0_00_MQS_RIGHT { + pinmux = <0x401f813c 2 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_qtimer1_timer0: IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x0 0 0x401f832c>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_semc_csx1: IOMUXC_GPIO_B0_00_SEMC_CSX1 { + pinmux = <0x401f813c 6 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_flexio2_flexio01: IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 { + pinmux = <0x401f8140 4 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio2_io01: IOMUXC_GPIO_B0_01_GPIO2_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio7_io01: IOMUXC_GPIO_B0_01_GPIO7_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lpspi3_sdi: IOMUXC_GPIO_B0_01_LPSPI3_SDI { + pinmux = <0x401f8140 3 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_mqs_left: IOMUXC_GPIO_B0_01_MQS_LEFT { + pinmux = <0x401f8140 2 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_qtimer1_timer1: IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x0 0 0x401f8330>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_semc_csx2: IOMUXC_GPIO_B0_01_SEMC_CSX2 { + pinmux = <0x401f8140 6 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexcan1_tx: IOMUXC_GPIO_B0_02_FLEXCAN1_TX { + pinmux = <0x401f8144 2 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexio2_flexio02: IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 { + pinmux = <0x401f8144 4 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio2_io02: IOMUXC_GPIO_B0_02_GPIO2_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio7_io02: IOMUXC_GPIO_B0_02_GPIO7_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lpspi3_sdo: IOMUXC_GPIO_B0_02_LPSPI3_SDO { + pinmux = <0x401f8144 3 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_qtimer1_timer2: IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x0 0 0x401f8334>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_semc_csx3: IOMUXC_GPIO_B0_02_SEMC_CSX3 { + pinmux = <0x401f8144 6 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexcan1_rx: IOMUXC_GPIO_B0_03_FLEXCAN1_RX { + pinmux = <0x401f8148 2 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexio2_flexio03: IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 { + pinmux = <0x401f8148 4 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio2_io03: IOMUXC_GPIO_B0_03_GPIO2_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio7_io03: IOMUXC_GPIO_B0_03_GPIO7_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lpspi3_sck: IOMUXC_GPIO_B0_03_LPSPI3_SCK { + pinmux = <0x401f8148 3 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_qtimer2_timer0: IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 { + pinmux = <0x401f8148 1 0x0 0 0x401f8338>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_wdog2_rst_b_deb: IOMUXC_GPIO_B0_03_WDOG2_RST_B_DEB { + pinmux = <0x401f8148 6 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_arm_trace0: IOMUXC_GPIO_B0_04_ARM_TRACE0 { + pinmux = <0x401f814c 3 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_flexio2_flexio04: IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 { + pinmux = <0x401f814c 4 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio2_io04: IOMUXC_GPIO_B0_04_GPIO2_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio7_io04: IOMUXC_GPIO_B0_04_GPIO7_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lpi2c2_scl: IOMUXC_GPIO_B0_04_LPI2C2_SCL { + pinmux = <0x401f814c 2 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_qtimer2_timer1: IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 { + pinmux = <0x401f814c 1 0x0 0 0x401f833c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_src_bt_cfg0: IOMUXC_GPIO_B0_04_SRC_BT_CFG0 { + pinmux = <0x401f814c 6 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_arm_trace1: IOMUXC_GPIO_B0_05_ARM_TRACE1 { + pinmux = <0x401f8150 3 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_flexio2_flexio05: IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 { + pinmux = <0x401f8150 4 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio2_io05: IOMUXC_GPIO_B0_05_GPIO2_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio7_io05: IOMUXC_GPIO_B0_05_GPIO7_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lpi2c2_sda: IOMUXC_GPIO_B0_05_LPI2C2_SDA { + pinmux = <0x401f8150 2 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_qtimer2_timer2: IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 { + pinmux = <0x401f8150 1 0x0 0 0x401f8340>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_src_bt_cfg1: IOMUXC_GPIO_B0_05_SRC_BT_CFG1 { + pinmux = <0x401f8150 6 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_arm_trace2: IOMUXC_GPIO_B0_06_ARM_TRACE2 { + pinmux = <0x401f8154 3 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexio2_flexio06: IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 { + pinmux = <0x401f8154 4 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexpwm2_pwma0: IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f8154 2 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio2_io06: IOMUXC_GPIO_B0_06_GPIO2_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio7_io06: IOMUXC_GPIO_B0_06_GPIO7_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_qtimer3_timer0: IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 { + pinmux = <0x401f8154 1 0x0 0 0x401f8344>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_src_bt_cfg2: IOMUXC_GPIO_B0_06_SRC_BT_CFG2 { + pinmux = <0x401f8154 6 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_arm_trace3: IOMUXC_GPIO_B0_07_ARM_TRACE3 { + pinmux = <0x401f8158 3 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexio2_flexio07: IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 { + pinmux = <0x401f8158 4 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexpwm2_pwmb0: IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8158 2 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio2_io07: IOMUXC_GPIO_B0_07_GPIO2_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio7_io07: IOMUXC_GPIO_B0_07_GPIO7_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_qtimer3_timer1: IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 { + pinmux = <0x401f8158 1 0x0 0 0x401f8348>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_src_bt_cfg3: IOMUXC_GPIO_B0_07_SRC_BT_CFG3 { + pinmux = <0x401f8158 6 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexio2_flexio08: IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 { + pinmux = <0x401f815c 4 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexpwm2_pwma1: IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f815c 2 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio2_io08: IOMUXC_GPIO_B0_08_GPIO2_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio7_io08: IOMUXC_GPIO_B0_08_GPIO7_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lpuart3_tx: IOMUXC_GPIO_B0_08_LPUART3_TX { + pinmux = <0x401f815c 3 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_qtimer3_timer2: IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 { + pinmux = <0x401f815c 1 0x0 0 0x401f834c>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_src_bt_cfg4: IOMUXC_GPIO_B0_08_SRC_BT_CFG4 { + pinmux = <0x401f815c 6 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexio2_flexio09: IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 { + pinmux = <0x401f8160 4 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexpwm2_pwmb1: IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8160 2 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio2_io09: IOMUXC_GPIO_B0_09_GPIO2_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio7_io09: IOMUXC_GPIO_B0_09_GPIO7_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lpuart3_rx: IOMUXC_GPIO_B0_09_LPUART3_RX { + pinmux = <0x401f8160 3 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_qtimer4_timer0: IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 { + pinmux = <0x401f8160 1 0x0 0 0x401f8350>; + gpr = <0x400ac018 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_src_bt_cfg5: IOMUXC_GPIO_B0_09_SRC_BT_CFG5 { + pinmux = <0x401f8160 6 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexio2_flexio10: IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 { + pinmux = <0x401f8164 4 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f8164 2 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio2_io10: IOMUXC_GPIO_B0_10_GPIO2_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio7_io10: IOMUXC_GPIO_B0_10_GPIO7_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_qtimer4_timer1: IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 { + pinmux = <0x401f8164 1 0x0 0 0x401f8354>; + gpr = <0x400ac018 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_sai1_tx_data3: IOMUXC_GPIO_B0_10_SAI1_TX_DATA3 { + pinmux = <0x401f8164 3 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_src_bt_cfg6: IOMUXC_GPIO_B0_10_SRC_BT_CFG6 { + pinmux = <0x401f8164 6 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexio2_flexio11: IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 { + pinmux = <0x401f8168 4 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8168 2 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio2_io11: IOMUXC_GPIO_B0_11_GPIO2_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio7_io11: IOMUXC_GPIO_B0_11_GPIO7_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_qtimer4_timer2: IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 { + pinmux = <0x401f8168 1 0x0 0 0x401f8358>; + gpr = <0x400ac018 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_sai1_tx_data2: IOMUXC_GPIO_B0_11_SAI1_TX_DATA2 { + pinmux = <0x401f8168 3 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_src_bt_cfg7: IOMUXC_GPIO_B0_11_SRC_BT_CFG7 { + pinmux = <0x401f8168 6 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_arm_trace_clk: IOMUXC_GPIO_B0_12_ARM_TRACE_CLK { + pinmux = <0x401f816c 2 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_flexio2_flexio12: IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 { + pinmux = <0x401f816c 4 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio2_io12: IOMUXC_GPIO_B0_12_GPIO2_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio7_io12: IOMUXC_GPIO_B0_12_GPIO7_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_sai1_tx_data1: IOMUXC_GPIO_B0_12_SAI1_TX_DATA1 { + pinmux = <0x401f816c 3 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_src_bt_cfg8: IOMUXC_GPIO_B0_12_SRC_BT_CFG8 { + pinmux = <0x401f816c 6 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_in10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_IN10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_inout10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_arm_trace_swo: IOMUXC_GPIO_B0_13_ARM_TRACE_SWO { + pinmux = <0x401f8170 2 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_flexio2_flexio13: IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 { + pinmux = <0x401f8170 4 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio2_io13: IOMUXC_GPIO_B0_13_GPIO2_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio7_io13: IOMUXC_GPIO_B0_13_GPIO7_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_sai1_mclk: IOMUXC_GPIO_B0_13_SAI1_MCLK { + pinmux = <0x401f8170 3 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_src_bt_cfg9: IOMUXC_GPIO_B0_13_SRC_BT_CFG9 { + pinmux = <0x401f8170 6 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_in11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_IN11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_inout11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_flexio2_flexio14: IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 { + pinmux = <0x401f8174 4 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio2_io14: IOMUXC_GPIO_B0_14_GPIO2_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio7_io14: IOMUXC_GPIO_B0_14_GPIO7_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_sai1_rx_sync: IOMUXC_GPIO_B0_14_SAI1_RX_SYNC { + pinmux = <0x401f8174 3 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_src_bt_cfg10: IOMUXC_GPIO_B0_14_SRC_BT_CFG10 { + pinmux = <0x401f8174 6 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_in12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_IN12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_inout12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_flexio2_flexio15: IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 { + pinmux = <0x401f8178 4 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio2_io15: IOMUXC_GPIO_B0_15_GPIO2_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio7_io15: IOMUXC_GPIO_B0_15_GPIO7_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_sai1_rx_bclk: IOMUXC_GPIO_B0_15_SAI1_RX_BCLK { + pinmux = <0x401f8178 3 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_src_bt_cfg11: IOMUXC_GPIO_B0_15_SRC_BT_CFG11 { + pinmux = <0x401f8178 6 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_in13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_IN13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_inout13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio2_flexio16: IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 { + pinmux = <0x401f817c 4 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio3_flexio16: IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 { + pinmux = <0x401f817c 9 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f817c 6 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio2_io16: IOMUXC_GPIO_B1_00_GPIO2_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio7_io16: IOMUXC_GPIO_B1_00_GPIO7_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lpuart4_tx: IOMUXC_GPIO_B1_00_LPUART4_TX { + pinmux = <0x401f817c 2 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_sai1_rx_data0: IOMUXC_GPIO_B1_00_SAI1_RX_DATA0 { + pinmux = <0x401f817c 3 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_in14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f817c 1 0x0 0 0x401f836c>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_inout14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f817c 1 0x0 0 0x401f836c>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio2_flexio17: IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 { + pinmux = <0x401f8180 4 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio3_flexio17: IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 { + pinmux = <0x401f8180 9 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f8180 6 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio2_io17: IOMUXC_GPIO_B1_01_GPIO2_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio7_io17: IOMUXC_GPIO_B1_01_GPIO7_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lpuart4_rx: IOMUXC_GPIO_B1_01_LPUART4_RX { + pinmux = <0x401f8180 2 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_sai1_tx_data0: IOMUXC_GPIO_B1_01_SAI1_TX_DATA0 { + pinmux = <0x401f8180 3 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_in15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8180 1 0x0 0 0x401f8370>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_inout15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8180 1 0x0 0 0x401f8370>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio2_flexio18: IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 { + pinmux = <0x401f8184 4 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio3_flexio18: IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 { + pinmux = <0x401f8184 9 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f8184 6 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio2_io18: IOMUXC_GPIO_B1_02_GPIO2_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio7_io18: IOMUXC_GPIO_B1_02_GPIO7_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lpspi3_pcs2: IOMUXC_GPIO_B1_02_LPSPI3_PCS2 { + pinmux = <0x401f8184 2 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_sai1_tx_bclk: IOMUXC_GPIO_B1_02_SAI1_TX_BCLK { + pinmux = <0x401f8184 3 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_in16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8184 1 0x0 0 0x401f8374>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_inout16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8184 1 0x0 0 0x401f8374>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio2_flexio19: IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 { + pinmux = <0x401f8188 4 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio3_flexio19: IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 { + pinmux = <0x401f8188 9 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f8188 6 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio2_io19: IOMUXC_GPIO_B1_03_GPIO2_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio7_io19: IOMUXC_GPIO_B1_03_GPIO7_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lpspi3_pcs1: IOMUXC_GPIO_B1_03_LPSPI3_PCS1 { + pinmux = <0x401f8188 2 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_sai1_tx_sync: IOMUXC_GPIO_B1_03_SAI1_TX_SYNC { + pinmux = <0x401f8188 3 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_in17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f8188 1 0x0 0 0x401f8378>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_inout17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8188 1 0x0 0 0x401f8378>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_enet_rx_data0: IOMUXC_GPIO_B1_04_ENET_RX_DATA0 { + pinmux = <0x401f818c 3 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio2_flexio20: IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 { + pinmux = <0x401f818c 4 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio3_flexio20: IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 { + pinmux = <0x401f818c 9 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio2_io20: IOMUXC_GPIO_B1_04_GPIO2_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio7_io20: IOMUXC_GPIO_B1_04_GPIO7_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpt1_clk: IOMUXC_GPIO_B1_04_GPT1_CLK { + pinmux = <0x401f818c 8 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lpspi3_pcs0: IOMUXC_GPIO_B1_04_LPSPI3_PCS0 { + pinmux = <0x401f818c 1 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_enet_rx_data1: IOMUXC_GPIO_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f8190 3 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio2_flexio21: IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 { + pinmux = <0x401f8190 4 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio3_flexio21: IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 { + pinmux = <0x401f8190 9 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio2_io21: IOMUXC_GPIO_B1_05_GPIO2_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio7_io21: IOMUXC_GPIO_B1_05_GPIO7_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpt1_capture1: IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 { + pinmux = <0x401f8190 8 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lpspi3_sdi: IOMUXC_GPIO_B1_05_LPSPI3_SDI { + pinmux = <0x401f8190 1 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_enet_rx_en: IOMUXC_GPIO_B1_06_ENET_RX_EN { + pinmux = <0x401f8194 3 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio2_flexio22: IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 { + pinmux = <0x401f8194 4 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio3_flexio22: IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 { + pinmux = <0x401f8194 9 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio2_io22: IOMUXC_GPIO_B1_06_GPIO2_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio7_io22: IOMUXC_GPIO_B1_06_GPIO7_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpt1_capture2: IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 { + pinmux = <0x401f8194 8 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lpspi3_sdo: IOMUXC_GPIO_B1_06_LPSPI3_SDO { + pinmux = <0x401f8194 1 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_enet_tx_data0: IOMUXC_GPIO_B1_07_ENET_TX_DATA0 { + pinmux = <0x401f8198 3 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio2_flexio23: IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 { + pinmux = <0x401f8198 4 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio3_flexio23: IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 { + pinmux = <0x401f8198 9 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio2_io23: IOMUXC_GPIO_B1_07_GPIO2_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio7_io23: IOMUXC_GPIO_B1_07_GPIO7_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpt1_compare1: IOMUXC_GPIO_B1_07_GPT1_COMPARE1 { + pinmux = <0x401f8198 8 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lpspi3_sck: IOMUXC_GPIO_B1_07_LPSPI3_SCK { + pinmux = <0x401f8198 1 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_enet_tx_data1: IOMUXC_GPIO_B1_08_ENET_TX_DATA1 { + pinmux = <0x401f819c 3 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexcan2_tx: IOMUXC_GPIO_B1_08_FLEXCAN2_TX { + pinmux = <0x401f819c 6 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio2_flexio24: IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 { + pinmux = <0x401f819c 4 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio3_flexio24: IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 { + pinmux = <0x401f819c 9 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio2_io24: IOMUXC_GPIO_B1_08_GPIO2_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio7_io24: IOMUXC_GPIO_B1_08_GPIO7_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpt1_compare2: IOMUXC_GPIO_B1_08_GPT1_COMPARE2 { + pinmux = <0x401f819c 8 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_qtimer1_timer3: IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 { + pinmux = <0x401f819c 1 0x0 0 0x401f838c>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_enet_tx_en: IOMUXC_GPIO_B1_09_ENET_TX_EN { + pinmux = <0x401f81a0 3 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexcan2_rx: IOMUXC_GPIO_B1_09_FLEXCAN2_RX { + pinmux = <0x401f81a0 6 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio2_flexio25: IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 { + pinmux = <0x401f81a0 4 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio3_flexio25: IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 { + pinmux = <0x401f81a0 9 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio2_io25: IOMUXC_GPIO_B1_09_GPIO2_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio7_io25: IOMUXC_GPIO_B1_09_GPIO7_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpt1_compare3: IOMUXC_GPIO_B1_09_GPT1_COMPARE3 { + pinmux = <0x401f81a0 8 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_qtimer2_timer3: IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 { + pinmux = <0x401f81a0 1 0x0 0 0x401f8390>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_ref_clk: IOMUXC_GPIO_B1_10_ENET_REF_CLK { + pinmux = <0x401f81a4 6 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_tx_clk: IOMUXC_GPIO_B1_10_ENET_TX_CLK { + pinmux = <0x401f81a4 3 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio2_flexio26: IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 { + pinmux = <0x401f81a4 4 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio3_flexio26: IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 { + pinmux = <0x401f81a4 9 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio2_io26: IOMUXC_GPIO_B1_10_GPIO2_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio7_io26: IOMUXC_GPIO_B1_10_GPIO7_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_qtimer3_timer3: IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 { + pinmux = <0x401f81a4 1 0x0 0 0x401f8394>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_enet_rx_er: IOMUXC_GPIO_B1_11_ENET_RX_ER { + pinmux = <0x401f81a8 3 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio2_flexio27: IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 { + pinmux = <0x401f81a8 4 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio3_flexio27: IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 { + pinmux = <0x401f81a8 9 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio2_io27: IOMUXC_GPIO_B1_11_GPIO2_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio7_io27: IOMUXC_GPIO_B1_11_GPIO7_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lpspi3_pcs3: IOMUXC_GPIO_B1_11_LPSPI3_PCS3 { + pinmux = <0x401f81a8 6 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_qtimer4_timer3: IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 { + pinmux = <0x401f81a8 1 0x0 0 0x401f8398>; + gpr = <0x400ac018 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_enet_1588_event0_in: IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN { + pinmux = <0x401f81ac 3 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio2_flexio28: IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 { + pinmux = <0x401f81ac 4 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio3_flexio28: IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 { + pinmux = <0x401f81ac 9 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio2_io28: IOMUXC_GPIO_B1_12_GPIO2_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio7_io28: IOMUXC_GPIO_B1_12_GPIO7_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_lpuart5_tx: IOMUXC_GPIO_B1_12_LPUART5_TX { + pinmux = <0x401f81ac 1 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_usdhc1_cd_b: IOMUXC_GPIO_B1_12_USDHC1_CD_B { + pinmux = <0x401f81ac 6 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_enet_1588_event0_out: IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT { + pinmux = <0x401f81b0 3 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio2_flexio29: IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 { + pinmux = <0x401f81b0 4 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio3_flexio29: IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 { + pinmux = <0x401f81b0 9 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio2_io29: IOMUXC_GPIO_B1_13_GPIO2_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio7_io29: IOMUXC_GPIO_B1_13_GPIO7_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_lpuart5_rx: IOMUXC_GPIO_B1_13_LPUART5_RX { + pinmux = <0x401f81b0 1 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_semc_dqs4: IOMUXC_GPIO_B1_13_SEMC_DQS4 { + pinmux = <0x401f81b0 8 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_usdhc1_wp: IOMUXC_GPIO_B1_13_USDHC1_WP { + pinmux = <0x401f81b0 6 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_wdog1_b: IOMUXC_GPIO_B1_13_WDOG1_B { + pinmux = <0x401f81b0 0 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet_mdc: IOMUXC_GPIO_B1_14_ENET_MDC { + pinmux = <0x401f81b4 0 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio2_flexio30: IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 { + pinmux = <0x401f81b4 4 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio3_flexio30: IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 { + pinmux = <0x401f81b4 9 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexpwm4_pwma2: IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA2 { + pinmux = <0x401f81b4 1 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio2_io30: IOMUXC_GPIO_B1_14_GPIO2_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio7_io30: IOMUXC_GPIO_B1_14_GPIO7_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_usdhc1_vselect: IOMUXC_GPIO_B1_14_USDHC1_VSELECT { + pinmux = <0x401f81b4 6 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_xbar1_xbar_in02: IOMUXC_GPIO_B1_14_XBAR1_XBAR_IN02 { + pinmux = <0x401f81b4 3 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet_mdio: IOMUXC_GPIO_B1_15_ENET_MDIO { + pinmux = <0x401f81b8 0 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio2_flexio31: IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 { + pinmux = <0x401f81b8 4 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio3_flexio31: IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 { + pinmux = <0x401f81b8 9 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexpwm4_pwma3: IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA3 { + pinmux = <0x401f81b8 1 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio2_io31: IOMUXC_GPIO_B1_15_GPIO2_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio7_io31: IOMUXC_GPIO_B1_15_GPIO7_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_usdhc1_reset_b: IOMUXC_GPIO_B1_15_USDHC1_RESET_B { + pinmux = <0x401f81b8 6 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_xbar1_xbar_in03: IOMUXC_GPIO_B1_15_XBAR1_XBAR_IN03 { + pinmux = <0x401f81b8 3 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexio1_flexio00: IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8014 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexpwm4_pwma0: IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA0 { + pinmux = <0x401f8014 1 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio4_io00: IOMUXC_GPIO_EMC_00_GPIO4_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio9_io00: IOMUXC_GPIO_EMC_00_GPIO9_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 2 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_xbar1_xbar_in02: IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 { + pinmux = <0x401f8014 3 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexio1_flexio01: IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8018 4 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexpwm4_pwmb0: IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB0 { + pinmux = <0x401f8018 1 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio4_io01: IOMUXC_GPIO_EMC_01_GPIO4_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio9_io01: IOMUXC_GPIO_EMC_01_GPIO9_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 2 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_xbar1_xbar_in03: IOMUXC_GPIO_EMC_01_XBAR1_XBAR_IN03 { + pinmux = <0x401f8018 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexio1_flexio02: IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 { + pinmux = <0x401f801c 4 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexpwm4_pwma1: IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA1 { + pinmux = <0x401f801c 1 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio4_io02: IOMUXC_GPIO_EMC_02_GPIO4_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio9_io02: IOMUXC_GPIO_EMC_02_GPIO9_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 2 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_in04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_IN04 { + pinmux = <0x401f801c 3 0x0 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f801c 3 0x0 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexio1_flexio03: IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 { + pinmux = <0x401f8020 4 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexpwm4_pwmb1: IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB1 { + pinmux = <0x401f8020 1 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio4_io03: IOMUXC_GPIO_EMC_03_GPIO4_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio9_io03: IOMUXC_GPIO_EMC_03_GPIO9_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 2 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_in05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_IN05 { + pinmux = <0x401f8020 3 0x0 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8020 3 0x0 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio04: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8024 4 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexpwm4_pwma2: IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA2 { + pinmux = <0x401f8024 1 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio4_io04: IOMUXC_GPIO_EMC_04_GPIO4_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio9_io04: IOMUXC_GPIO_EMC_04_GPIO9_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_data: IOMUXC_GPIO_EMC_04_SAI2_TX_DATA { + pinmux = <0x401f8024 2 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN06 { + pinmux = <0x401f8024 3 0x0 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f8024 3 0x0 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio05: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8028 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexpwm4_pwmb2: IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB2 { + pinmux = <0x401f8028 1 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio4_io05: IOMUXC_GPIO_EMC_05_GPIO4_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio9_io05: IOMUXC_GPIO_EMC_05_GPIO9_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 2 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN07 { + pinmux = <0x401f8028 3 0x0 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8028 3 0x0 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio06: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 { + pinmux = <0x401f802c 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexpwm2_pwma0: IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f802c 1 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio4_io06: IOMUXC_GPIO_EMC_06_GPIO4_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio9_io06: IOMUXC_GPIO_EMC_06_GPIO9_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_bclk: IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK { + pinmux = <0x401f802c 2 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN08 { + pinmux = <0x401f802c 3 0x0 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f802c 3 0x0 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio07: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 { + pinmux = <0x401f8030 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8030 1 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio4_io07: IOMUXC_GPIO_EMC_07_GPIO4_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio9_io07: IOMUXC_GPIO_EMC_07_GPIO9_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_mclk: IOMUXC_GPIO_EMC_07_SAI2_MCLK { + pinmux = <0x401f8030 2 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN09 { + pinmux = <0x401f8030 3 0x0 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8030 3 0x0 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio08: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8034 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexpwm2_pwma1: IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f8034 1 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio4_io08: IOMUXC_GPIO_EMC_08_GPIO4_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio9_io08: IOMUXC_GPIO_EMC_08_GPIO9_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 2 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN17 { + pinmux = <0x401f8034 3 0x0 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8034 3 0x0 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_tx: IOMUXC_GPIO_EMC_09_FLEXCAN2_TX { + pinmux = <0x401f8038 3 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio09: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8038 4 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8038 1 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexspi2_b_ss1_b: IOMUXC_GPIO_EMC_09_FLEXSPI2_B_SS1_B { + pinmux = <0x401f8038 8 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio4_io09: IOMUXC_GPIO_EMC_09_GPIO4_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio9_io09: IOMUXC_GPIO_EMC_09_GPIO9_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_sync: IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC { + pinmux = <0x401f8038 2 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_addr00: IOMUXC_GPIO_EMC_09_SEMC_ADDR00 { + pinmux = <0x401f8038 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexcan2_rx: IOMUXC_GPIO_EMC_10_FLEXCAN2_RX { + pinmux = <0x401f803c 3 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexio1_flexio10: IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 { + pinmux = <0x401f803c 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwma2: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f803c 1 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_10_FLEXSPI2_B_SS0_B { + pinmux = <0x401f803c 8 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio4_io10: IOMUXC_GPIO_EMC_10_GPIO4_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio9_io10: IOMUXC_GPIO_EMC_10_GPIO9_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai2_rx_bclk: IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK { + pinmux = <0x401f803c 2 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_addr01: IOMUXC_GPIO_EMC_10_SEMC_ADDR01 { + pinmux = <0x401f803c 0 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexio1_flexio11: IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 { + pinmux = <0x401f8040 4 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8040 1 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexspi2_b_dqs: IOMUXC_GPIO_EMC_11_FLEXSPI2_B_DQS { + pinmux = <0x401f8040 8 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio4_io11: IOMUXC_GPIO_EMC_11_GPIO4_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio9_io11: IOMUXC_GPIO_EMC_11_GPIO9_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_sda: IOMUXC_GPIO_EMC_11_LPI2C4_SDA { + pinmux = <0x401f8040 2 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_addr02: IOMUXC_GPIO_EMC_11_SEMC_ADDR02 { + pinmux = <0x401f8040 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_usdhc2_reset_b: IOMUXC_GPIO_EMC_11_USDHC2_RESET_B { + pinmux = <0x401f8040 3 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm1_pwma3: IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f8044 4 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexspi2_b_sclk: IOMUXC_GPIO_EMC_12_FLEXSPI2_B_SCLK { + pinmux = <0x401f8044 8 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio4_io12: IOMUXC_GPIO_EMC_12_GPIO4_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio9_io12: IOMUXC_GPIO_EMC_12_GPIO9_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpi2c4_scl: IOMUXC_GPIO_EMC_12_LPI2C4_SCL { + pinmux = <0x401f8044 2 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_addr03: IOMUXC_GPIO_EMC_12_SEMC_ADDR03 { + pinmux = <0x401f8044 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_usdhc1_wp: IOMUXC_GPIO_EMC_12_USDHC1_WP { + pinmux = <0x401f8044 3 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in24: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN24 { + pinmux = <0x401f8044 1 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8048 4 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexspi2_b_data0: IOMUXC_GPIO_EMC_13_FLEXSPI2_B_DATA0 { + pinmux = <0x401f8048 8 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio4_io13: IOMUXC_GPIO_EMC_13_GPIO4_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio9_io13: IOMUXC_GPIO_EMC_13_GPIO9_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart3_tx: IOMUXC_GPIO_EMC_13_LPUART3_TX { + pinmux = <0x401f8048 2 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_mqs_right: IOMUXC_GPIO_EMC_13_MQS_RIGHT { + pinmux = <0x401f8048 3 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_addr04: IOMUXC_GPIO_EMC_13_SEMC_ADDR04 { + pinmux = <0x401f8048 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in25: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN25 { + pinmux = <0x401f8048 1 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_flexspi2_b_data1: IOMUXC_GPIO_EMC_14_FLEXSPI2_B_DATA1 { + pinmux = <0x401f804c 8 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio4_io14: IOMUXC_GPIO_EMC_14_GPIO4_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio9_io14: IOMUXC_GPIO_EMC_14_GPIO9_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart3_rx: IOMUXC_GPIO_EMC_14_LPUART3_RX { + pinmux = <0x401f804c 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_mqs_left: IOMUXC_GPIO_EMC_14_MQS_LEFT { + pinmux = <0x401f804c 3 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_addr05: IOMUXC_GPIO_EMC_14_SEMC_ADDR05 { + pinmux = <0x401f804c 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN19 { + pinmux = <0x401f804c 1 0x0 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f804c 1 0x0 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_flexspi2_b_data2: IOMUXC_GPIO_EMC_15_FLEXSPI2_B_DATA2 { + pinmux = <0x401f8050 8 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio4_io15: IOMUXC_GPIO_EMC_15_GPIO4_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio9_io15: IOMUXC_GPIO_EMC_15_GPIO9_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart3_cts_b: IOMUXC_GPIO_EMC_15_LPUART3_CTS_B { + pinmux = <0x401f8050 2 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_qtimer3_timer0: IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 { + pinmux = <0x401f8050 4 0x0 0 0x401f8240>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr06: IOMUXC_GPIO_EMC_15_SEMC_ADDR06 { + pinmux = <0x401f8050 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_spdif_out: IOMUXC_GPIO_EMC_15_SPDIF_OUT { + pinmux = <0x401f8050 3 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in20: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN20 { + pinmux = <0x401f8050 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_flexspi2_b_data3: IOMUXC_GPIO_EMC_16_FLEXSPI2_B_DATA3 { + pinmux = <0x401f8054 8 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio4_io16: IOMUXC_GPIO_EMC_16_GPIO4_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio9_io16: IOMUXC_GPIO_EMC_16_GPIO9_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_lpuart3_rts_b: IOMUXC_GPIO_EMC_16_LPUART3_RTS_B { + pinmux = <0x401f8054 2 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_qtimer3_timer1: IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 { + pinmux = <0x401f8054 4 0x0 0 0x401f8244>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr07: IOMUXC_GPIO_EMC_16_SEMC_ADDR07 { + pinmux = <0x401f8054 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_spdif_in: IOMUXC_GPIO_EMC_16_SPDIF_IN { + pinmux = <0x401f8054 3 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_xbar1_xbar_in21: IOMUXC_GPIO_EMC_16_XBAR1_XBAR_IN21 { + pinmux = <0x401f8054 1 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexcan1_tx: IOMUXC_GPIO_EMC_17_FLEXCAN1_TX { + pinmux = <0x401f8058 3 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexpwm4_pwma3: IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA3 { + pinmux = <0x401f8058 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio4_io17: IOMUXC_GPIO_EMC_17_GPIO4_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio9_io17: IOMUXC_GPIO_EMC_17_GPIO9_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_lpuart4_cts_b: IOMUXC_GPIO_EMC_17_LPUART4_CTS_B { + pinmux = <0x401f8058 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_qtimer3_timer2: IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 { + pinmux = <0x401f8058 4 0x0 0 0x401f8248>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr08: IOMUXC_GPIO_EMC_17_SEMC_ADDR08 { + pinmux = <0x401f8058 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexcan1_rx: IOMUXC_GPIO_EMC_18_FLEXCAN1_RX { + pinmux = <0x401f805c 3 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexpwm4_pwmb3: IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB3 { + pinmux = <0x401f805c 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio4_io18: IOMUXC_GPIO_EMC_18_GPIO4_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio9_io18: IOMUXC_GPIO_EMC_18_GPIO9_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpuart4_rts_b: IOMUXC_GPIO_EMC_18_LPUART4_RTS_B { + pinmux = <0x401f805c 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_qtimer3_timer3: IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 { + pinmux = <0x401f805c 4 0x0 0 0x401f824c>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr09: IOMUXC_GPIO_EMC_18_SEMC_ADDR09 { + pinmux = <0x401f805c 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_snvs_vio_5_ctl: IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL { + pinmux = <0x401f805c 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_enet_rx_data1: IOMUXC_GPIO_EMC_19_ENET_RX_DATA1 { + pinmux = <0x401f8060 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexpwm2_pwma3: IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA3 { + pinmux = <0x401f8060 1 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio4_io19: IOMUXC_GPIO_EMC_19_GPIO4_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio9_io19: IOMUXC_GPIO_EMC_19_GPIO9_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpuart4_tx: IOMUXC_GPIO_EMC_19_LPUART4_TX { + pinmux = <0x401f8060 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_qtimer2_timer0: IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 { + pinmux = <0x401f8060 4 0x0 0 0x401f8250>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr11: IOMUXC_GPIO_EMC_19_SEMC_ADDR11 { + pinmux = <0x401f8060 0 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_snvs_vio_5_b: IOMUXC_GPIO_EMC_19_SNVS_VIO_5_B { + pinmux = <0x401f8060 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_enet_rx_data0: IOMUXC_GPIO_EMC_20_ENET_RX_DATA0 { + pinmux = <0x401f8064 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB3 { + pinmux = <0x401f8064 1 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio4_io20: IOMUXC_GPIO_EMC_20_GPIO4_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio9_io20: IOMUXC_GPIO_EMC_20_GPIO9_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart4_rx: IOMUXC_GPIO_EMC_20_LPUART4_RX { + pinmux = <0x401f8064 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_qtimer2_timer1: IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 { + pinmux = <0x401f8064 4 0x0 0 0x401f8254>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr12: IOMUXC_GPIO_EMC_20_SEMC_ADDR12 { + pinmux = <0x401f8064 0 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_enet_tx_data1: IOMUXC_GPIO_EMC_21_ENET_TX_DATA1 { + pinmux = <0x401f8068 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm3_pwma3: IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA3 { + pinmux = <0x401f8068 1 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio4_io21: IOMUXC_GPIO_EMC_21_GPIO4_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio9_io21: IOMUXC_GPIO_EMC_21_GPIO9_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpi2c3_sda: IOMUXC_GPIO_EMC_21_LPI2C3_SDA { + pinmux = <0x401f8068 2 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_qtimer2_timer2: IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 { + pinmux = <0x401f8068 4 0x0 0 0x401f8258>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_ba0: IOMUXC_GPIO_EMC_21_SEMC_BA0 { + pinmux = <0x401f8068 0 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_enet_tx_data0: IOMUXC_GPIO_EMC_22_ENET_TX_DATA0 { + pinmux = <0x401f806c 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm3_pwmb3: IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB3 { + pinmux = <0x401f806c 1 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexspi2_a_ss1_b: IOMUXC_GPIO_EMC_22_FLEXSPI2_A_SS1_B { + pinmux = <0x401f806c 8 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio4_io22: IOMUXC_GPIO_EMC_22_GPIO4_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio9_io22: IOMUXC_GPIO_EMC_22_GPIO9_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpi2c3_scl: IOMUXC_GPIO_EMC_22_LPI2C3_SCL { + pinmux = <0x401f806c 2 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_qtimer2_timer3: IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 { + pinmux = <0x401f806c 4 0x0 0 0x401f825c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_ba1: IOMUXC_GPIO_EMC_22_SEMC_BA1 { + pinmux = <0x401f806c 0 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_enet_rx_en: IOMUXC_GPIO_EMC_23_ENET_RX_EN { + pinmux = <0x401f8070 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwma0: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA0 { + pinmux = <0x401f8070 1 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexspi2_a_dqs: IOMUXC_GPIO_EMC_23_FLEXSPI2_A_DQS { + pinmux = <0x401f8070 8 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio4_io23: IOMUXC_GPIO_EMC_23_GPIO4_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio9_io23: IOMUXC_GPIO_EMC_23_GPIO9_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpt1_capture2: IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 { + pinmux = <0x401f8070 4 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart5_tx: IOMUXC_GPIO_EMC_23_LPUART5_TX { + pinmux = <0x401f8070 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr10: IOMUXC_GPIO_EMC_23_SEMC_ADDR10 { + pinmux = <0x401f8070 0 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_enet_tx_en: IOMUXC_GPIO_EMC_24_ENET_TX_EN { + pinmux = <0x401f8074 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB0 { + pinmux = <0x401f8074 1 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_24_FLEXSPI2_A_SS0_B { + pinmux = <0x401f8074 8 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio4_io24: IOMUXC_GPIO_EMC_24_GPIO4_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio9_io24: IOMUXC_GPIO_EMC_24_GPIO9_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpt1_capture1: IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 { + pinmux = <0x401f8074 4 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart5_rx: IOMUXC_GPIO_EMC_24_LPUART5_RX { + pinmux = <0x401f8074 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_cas: IOMUXC_GPIO_EMC_24_SEMC_CAS { + pinmux = <0x401f8074 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_ref_clk: IOMUXC_GPIO_EMC_25_ENET_REF_CLK { + pinmux = <0x401f8078 4 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_tx_clk: IOMUXC_GPIO_EMC_25_ENET_TX_CLK { + pinmux = <0x401f8078 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwma1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA1 { + pinmux = <0x401f8078 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexspi2_a_sclk: IOMUXC_GPIO_EMC_25_FLEXSPI2_A_SCLK { + pinmux = <0x401f8078 8 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio4_io25: IOMUXC_GPIO_EMC_25_GPIO4_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio9_io25: IOMUXC_GPIO_EMC_25_GPIO9_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart6_tx: IOMUXC_GPIO_EMC_25_LPUART6_TX { + pinmux = <0x401f8078 2 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_ras: IOMUXC_GPIO_EMC_25_SEMC_RAS { + pinmux = <0x401f8078 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_enet_rx_er: IOMUXC_GPIO_EMC_26_ENET_RX_ER { + pinmux = <0x401f807c 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio12: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 { + pinmux = <0x401f807c 4 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB1 { + pinmux = <0x401f807c 1 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexspi2_a_data0: IOMUXC_GPIO_EMC_26_FLEXSPI2_A_DATA0 { + pinmux = <0x401f807c 8 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio4_io26: IOMUXC_GPIO_EMC_26_GPIO4_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio9_io26: IOMUXC_GPIO_EMC_26_GPIO9_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart6_rx: IOMUXC_GPIO_EMC_26_LPUART6_RX { + pinmux = <0x401f807c 2 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_clk: IOMUXC_GPIO_EMC_26_SEMC_CLK { + pinmux = <0x401f807c 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio13: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8080 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwma2: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA2 { + pinmux = <0x401f8080 1 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexspi2_a_data1: IOMUXC_GPIO_EMC_27_FLEXSPI2_A_DATA1 { + pinmux = <0x401f8080 8 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio4_io27: IOMUXC_GPIO_EMC_27_GPIO4_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio9_io27: IOMUXC_GPIO_EMC_27_GPIO9_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpspi1_sck: IOMUXC_GPIO_EMC_27_LPSPI1_SCK { + pinmux = <0x401f8080 3 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart5_rts_b: IOMUXC_GPIO_EMC_27_LPUART5_RTS_B { + pinmux = <0x401f8080 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_cke: IOMUXC_GPIO_EMC_27_SEMC_CKE { + pinmux = <0x401f8080 0 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexio1_flexio14: IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8084 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB2 { + pinmux = <0x401f8084 1 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexspi2_a_data2: IOMUXC_GPIO_EMC_28_FLEXSPI2_A_DATA2 { + pinmux = <0x401f8084 8 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio4_io28: IOMUXC_GPIO_EMC_28_GPIO4_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio9_io28: IOMUXC_GPIO_EMC_28_GPIO9_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpspi1_sdo: IOMUXC_GPIO_EMC_28_LPSPI1_SDO { + pinmux = <0x401f8084 3 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpuart5_cts_b: IOMUXC_GPIO_EMC_28_LPUART5_CTS_B { + pinmux = <0x401f8084 2 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_we: IOMUXC_GPIO_EMC_28_SEMC_WE { + pinmux = <0x401f8084 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexio1_flexio15: IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 { + pinmux = <0x401f8088 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm3_pwma0: IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA0 { + pinmux = <0x401f8088 1 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexspi2_a_data3: IOMUXC_GPIO_EMC_29_FLEXSPI2_A_DATA3 { + pinmux = <0x401f8088 8 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio4_io29: IOMUXC_GPIO_EMC_29_GPIO4_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio9_io29: IOMUXC_GPIO_EMC_29_GPIO9_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpspi1_sdi: IOMUXC_GPIO_EMC_29_LPSPI1_SDI { + pinmux = <0x401f8088 3 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpuart6_rts_b: IOMUXC_GPIO_EMC_29_LPUART6_RTS_B { + pinmux = <0x401f8088 2 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cs0: IOMUXC_GPIO_EMC_29_SEMC_CS0 { + pinmux = <0x401f8088 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm3_pwmb0: IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB0 { + pinmux = <0x401f808c 1 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio4_io30: IOMUXC_GPIO_EMC_30_GPIO4_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio9_io30: IOMUXC_GPIO_EMC_30_GPIO9_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpspi1_pcs0: IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 { + pinmux = <0x401f808c 3 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart6_cts_b: IOMUXC_GPIO_EMC_30_LPUART6_CTS_B { + pinmux = <0x401f808c 2 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_data08: IOMUXC_GPIO_EMC_30_SEMC_DATA08 { + pinmux = <0x401f808c 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm3_pwma1: IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA1 { + pinmux = <0x401f8090 1 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio4_io31: IOMUXC_GPIO_EMC_31_GPIO4_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio9_io31: IOMUXC_GPIO_EMC_31_GPIO9_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpspi1_pcs1: IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 { + pinmux = <0x401f8090 3 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart7_tx: IOMUXC_GPIO_EMC_31_LPUART7_TX { + pinmux = <0x401f8090 2 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_data09: IOMUXC_GPIO_EMC_31_SEMC_DATA09 { + pinmux = <0x401f8090 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ccm_pmic_rdy: IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY { + pinmux = <0x401f8094 3 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_flexpwm3_pwmb1: IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB1 { + pinmux = <0x401f8094 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io18: IOMUXC_GPIO_EMC_32_GPIO3_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio8_io18: IOMUXC_GPIO_EMC_32_GPIO8_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart7_rx: IOMUXC_GPIO_EMC_32_LPUART7_RX { + pinmux = <0x401f8094 2 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data10: IOMUXC_GPIO_EMC_32_SEMC_DATA10 { + pinmux = <0x401f8094 0 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_flexpwm3_pwma2: IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA2 { + pinmux = <0x401f8098 1 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io19: IOMUXC_GPIO_EMC_33_GPIO3_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio8_io19: IOMUXC_GPIO_EMC_33_GPIO8_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_rx_data: IOMUXC_GPIO_EMC_33_SAI3_RX_DATA { + pinmux = <0x401f8098 3 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data11: IOMUXC_GPIO_EMC_33_SEMC_DATA11 { + pinmux = <0x401f8098 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_usdhc1_reset_b: IOMUXC_GPIO_EMC_33_USDHC1_RESET_B { + pinmux = <0x401f8098 2 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_flexpwm3_pwmb2: IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB2 { + pinmux = <0x401f809c 1 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io20: IOMUXC_GPIO_EMC_34_GPIO3_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio8_io20: IOMUXC_GPIO_EMC_34_GPIO8_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_rx_sync: IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC { + pinmux = <0x401f809c 3 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data12: IOMUXC_GPIO_EMC_34_SEMC_DATA12 { + pinmux = <0x401f809c 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_usdhc1_vselect: IOMUXC_GPIO_EMC_34_USDHC1_VSELECT { + pinmux = <0x401f809c 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io21: IOMUXC_GPIO_EMC_35_GPIO3_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio8_io21: IOMUXC_GPIO_EMC_35_GPIO8_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpt1_compare1: IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 { + pinmux = <0x401f80a0 2 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_sai3_rx_bclk: IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK { + pinmux = <0x401f80a0 3 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data13: IOMUXC_GPIO_EMC_35_SEMC_DATA13 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc1_cd_b: IOMUXC_GPIO_EMC_35_USDHC1_CD_B { + pinmux = <0x401f80a0 6 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_in18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_IN18 { + pinmux = <0x401f80a0 1 0x0 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80a0 1 0x0 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexcan3_tx: IOMUXC_GPIO_EMC_36_FLEXCAN3_TX { + pinmux = <0x401f80a4 9 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io22: IOMUXC_GPIO_EMC_36_GPIO3_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio8_io22: IOMUXC_GPIO_EMC_36_GPIO8_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpt1_compare2: IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 { + pinmux = <0x401f80a4 2 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_sai3_tx_data: IOMUXC_GPIO_EMC_36_SAI3_TX_DATA { + pinmux = <0x401f80a4 3 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data14: IOMUXC_GPIO_EMC_36_SEMC_DATA14 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 6 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_xbar1_xbar_in22: IOMUXC_GPIO_EMC_36_XBAR1_XBAR_IN22 { + pinmux = <0x401f80a4 1 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexcan3_rx: IOMUXC_GPIO_EMC_37_FLEXCAN3_RX { + pinmux = <0x401f80a8 9 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io23: IOMUXC_GPIO_EMC_37_GPIO3_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio8_io23: IOMUXC_GPIO_EMC_37_GPIO8_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpt1_compare3: IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 { + pinmux = <0x401f80a8 2 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_sai3_mclk: IOMUXC_GPIO_EMC_37_SAI3_MCLK { + pinmux = <0x401f80a8 3 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data15: IOMUXC_GPIO_EMC_37_SEMC_DATA15 { + pinmux = <0x401f80a8 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc2_wp: IOMUXC_GPIO_EMC_37_USDHC2_WP { + pinmux = <0x401f80a8 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_xbar1_xbar_in23: IOMUXC_GPIO_EMC_37_XBAR1_XBAR_IN23 { + pinmux = <0x401f80a8 1 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm1_pwma3: IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA3 { + pinmux = <0x401f80ac 1 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io24: IOMUXC_GPIO_EMC_38_GPIO3_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio8_io24: IOMUXC_GPIO_EMC_38_GPIO8_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart8_tx: IOMUXC_GPIO_EMC_38_LPUART8_TX { + pinmux = <0x401f80ac 2 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_sai3_tx_bclk: IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK { + pinmux = <0x401f80ac 3 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_dm1: IOMUXC_GPIO_EMC_38_SEMC_DM1 { + pinmux = <0x401f80ac 0 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc2_vselect: IOMUXC_GPIO_EMC_38_USDHC2_VSELECT { + pinmux = <0x401f80ac 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB3 { + pinmux = <0x401f80b0 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io25: IOMUXC_GPIO_EMC_39_GPIO3_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio8_io25: IOMUXC_GPIO_EMC_39_GPIO8_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart8_rx: IOMUXC_GPIO_EMC_39_LPUART8_RX { + pinmux = <0x401f80b0 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_sai3_tx_sync: IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC { + pinmux = <0x401f80b0 3 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs: IOMUXC_GPIO_EMC_39_SEMC_DQS { + pinmux = <0x401f80b0 0 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs4: IOMUXC_GPIO_EMC_39_SEMC_DQS4 { + pinmux = <0x401f80b0 9 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usdhc2_cd_b: IOMUXC_GPIO_EMC_39_USDHC2_CD_B { + pinmux = <0x401f80b0 6 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdc: IOMUXC_GPIO_EMC_40_ENET_MDC { + pinmux = <0x401f80b4 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io26: IOMUXC_GPIO_EMC_40_GPIO3_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio8_io26: IOMUXC_GPIO_EMC_40_GPIO8_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt2_capture2: IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 { + pinmux = <0x401f80b4 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_lpspi1_pcs2: IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 { + pinmux = <0x401f80b4 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_clk5: IOMUXC_GPIO_EMC_40_SEMC_CLK5 { + pinmux = <0x401f80b4 9 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_rdy: IOMUXC_GPIO_EMC_40_SEMC_RDY { + pinmux = <0x401f80b4 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usdhc2_reset_b: IOMUXC_GPIO_EMC_40_USDHC2_RESET_B { + pinmux = <0x401f80b4 6 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdio: IOMUXC_GPIO_EMC_41_ENET_MDIO { + pinmux = <0x401f80b8 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io27: IOMUXC_GPIO_EMC_41_GPIO3_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio8_io27: IOMUXC_GPIO_EMC_41_GPIO8_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt2_capture1: IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 { + pinmux = <0x401f80b8 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_lpspi1_pcs3: IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 { + pinmux = <0x401f80b8 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_csx0: IOMUXC_GPIO_EMC_41_SEMC_CSX0 { + pinmux = <0x401f80b8 0 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usdhc1_vselect: IOMUXC_GPIO_EMC_41_USDHC1_VSELECT { + pinmux = <0x401f80b8 6 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexpwm1_pwma0: IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA0 { + pinmux = <0x401f81bc 1 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f81bc 6 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io12: IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio8_io12: IOMUXC_GPIO_SD_B0_00_GPIO8_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f81bc 2 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpspi1_sck: IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK { + pinmux = <0x401f81bc 4 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_semc_dqs4: IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 { + pinmux = <0x401f81bc 9 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_cmd: IOMUXC_GPIO_SD_B0_00_USDHC1_CMD { + pinmux = <0x401f81bc 0 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN04 { + pinmux = <0x401f81bc 3 0x0 0 0x401f83ac>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f81bc 3 0x0 0 0x401f83ac>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexpwm1_pwmb0: IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB0 { + pinmux = <0x401f81c0 1 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f81c0 6 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io13: IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio8_io13: IOMUXC_GPIO_SD_B0_01_GPIO8_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f81c0 2 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 { + pinmux = <0x401f81c0 4 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_clk: IOMUXC_GPIO_SD_B0_01_USDHC1_CLK { + pinmux = <0x401f81c0 0 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN05 { + pinmux = <0x401f81c0 3 0x0 0 0x401f83b0>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f81c0 3 0x0 0 0x401f83b0>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_flexpwm1_pwma1: IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA1 { + pinmux = <0x401f81c4 1 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io14: IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio8_io14: IOMUXC_GPIO_SD_B0_02_GPIO8_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sdo: IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO { + pinmux = <0x401f81c4 4 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart8_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B { + pinmux = <0x401f81c4 2 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_semc_clk5: IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 { + pinmux = <0x401f81c4 9 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_data0: IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 { + pinmux = <0x401f81c4 0 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN06 { + pinmux = <0x401f81c4 3 0x0 0 0x401f83b4>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f81c4 3 0x0 0 0x401f83b4>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_flexpwm1_pwmb1: IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB1 { + pinmux = <0x401f81c8 1 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io15: IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio8_io15: IOMUXC_GPIO_SD_B0_03_GPIO8_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_sdi: IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI { + pinmux = <0x401f81c8 4 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart8_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B { + pinmux = <0x401f81c8 2 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_semc_clk6: IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 { + pinmux = <0x401f81c8 9 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_data1: IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 { + pinmux = <0x401f81c8 0 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_in07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_IN07 { + pinmux = <0x401f81c8 3 0x0 0 0x401f83b8>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_inout07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f81c8 3 0x0 0 0x401f83b8>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_ccm_clko1: IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 { + pinmux = <0x401f81cc 6 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexpwm1_pwma2: IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA2 { + pinmux = <0x401f81cc 1 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f81cc 4 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io16: IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio8_io16: IOMUXC_GPIO_SD_B0_04_GPIO8_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart8_tx: IOMUXC_GPIO_SD_B0_04_LPUART8_TX { + pinmux = <0x401f81cc 2 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data2: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 { + pinmux = <0x401f81cc 0 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_in08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_IN08 { + pinmux = <0x401f81cc 3 0x0 0 0x401f83bc>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_inout08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f81cc 3 0x0 0 0x401f83bc>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_ccm_clko2: IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 { + pinmux = <0x401f81d0 6 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexpwm1_pwmb2: IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB2 { + pinmux = <0x401f81d0 1 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f81d0 4 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io17: IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio8_io17: IOMUXC_GPIO_SD_B0_05_GPIO8_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart8_rx: IOMUXC_GPIO_SD_B0_05_LPUART8_RX { + pinmux = <0x401f81d0 2 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data3: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 { + pinmux = <0x401f81d0 0 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_in09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_IN09 { + pinmux = <0x401f81d0 3 0x0 0 0x401f83c0>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_inout09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f81d0 3 0x0 0 0x401f83c0>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f81d4 2 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f81d4 1 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io00: IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio8_io00: IOMUXC_GPIO_SD_B1_00_GPIO8_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart4_tx: IOMUXC_GPIO_SD_B1_00_LPUART4_TX { + pinmux = <0x401f81d4 4 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai1_tx_data3: IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA3 { + pinmux = <0x401f81d4 3 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai3_rx_data: IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA { + pinmux = <0x401f81d4 8 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data3: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 { + pinmux = <0x401f81d4 0 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f81d8 2 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_data2: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 { + pinmux = <0x401f81d8 1 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io01: IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio8_io01: IOMUXC_GPIO_SD_B1_01_GPIO8_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart4_rx: IOMUXC_GPIO_SD_B1_01_LPUART4_RX { + pinmux = <0x401f81d8 4 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai1_tx_data2: IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA2 { + pinmux = <0x401f81d8 3 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai3_tx_data: IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA { + pinmux = <0x401f81d8 8 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data2: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 { + pinmux = <0x401f81d8 0 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_wait: IOMUXC_GPIO_SD_B1_02_CCM_WAIT { + pinmux = <0x401f81dc 6 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexcan1_tx: IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX { + pinmux = <0x401f81dc 4 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f81dc 2 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data1: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 { + pinmux = <0x401f81dc 1 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io02: IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio8_io02: IOMUXC_GPIO_SD_B1_02_GPIO8_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai1_tx_data1: IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA1 { + pinmux = <0x401f81dc 3 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai3_tx_sync: IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC { + pinmux = <0x401f81dc 8 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_data1: IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 { + pinmux = <0x401f81dc 0 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_03_CCM_PMIC_RDY { + pinmux = <0x401f81e0 6 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexcan1_rx: IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX { + pinmux = <0x401f81e0 4 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f81e0 2 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data0: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 { + pinmux = <0x401f81e0 1 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io03: IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio8_io03: IOMUXC_GPIO_SD_B1_03_GPIO8_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai1_mclk: IOMUXC_GPIO_SD_B1_03_SAI1_MCLK { + pinmux = <0x401f81e0 3 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK { + pinmux = <0x401f81e0 8 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_data0: IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 { + pinmux = <0x401f81e0 0 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_stop: IOMUXC_GPIO_SD_B1_04_CCM_STOP { + pinmux = <0x401f81e4 6 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI_A_SS1_B { + pinmux = <0x401f81e4 4 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK { + pinmux = <0x401f81e4 1 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io04: IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio8_io04: IOMUXC_GPIO_SD_B1_04_GPIO8_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_lpi2c1_scl: IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL { + pinmux = <0x401f81e4 2 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai1_rx_sync: IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f81e4 3 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai3_mclk: IOMUXC_GPIO_SD_B1_04_SAI3_MCLK { + pinmux = <0x401f81e4 8 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_clk: IOMUXC_GPIO_SD_B1_04_USDHC2_CLK { + pinmux = <0x401f81e4 0 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f81e8 1 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f81e8 4 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io05: IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio8_io05: IOMUXC_GPIO_SD_B1_05_GPIO8_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_lpi2c1_sda: IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA { + pinmux = <0x401f81e8 2 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai1_rx_bclk: IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK { + pinmux = <0x401f81e8 3 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_rx_sync: IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC { + pinmux = <0x401f81e8 8 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_cmd: IOMUXC_GPIO_SD_B1_05_USDHC2_CMD { + pinmux = <0x401f81e8 0 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B { + pinmux = <0x401f81ec 1 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io06: IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio8_io06: IOMUXC_GPIO_SD_B1_06_GPIO8_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f81ec 4 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpuart7_cts_b: IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B { + pinmux = <0x401f81ec 2 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai1_rx_data0: IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA0 { + pinmux = <0x401f81ec 3 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK { + pinmux = <0x401f81ec 8 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B { + pinmux = <0x401f81ec 0 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f81f0 1 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io07: IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio8_io07: IOMUXC_GPIO_SD_B1_07_GPIO8_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f81f0 4 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpuart7_rts_b: IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B { + pinmux = <0x401f81f0 2 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai1_tx_data0: IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA0 { + pinmux = <0x401f81f0 3 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_semc_csx1: IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 { + pinmux = <0x401f81f0 0 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f81f4 1 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io08: IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio8_io08: IOMUXC_GPIO_SD_B1_08_GPIO8_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f81f4 4 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpuart7_tx: IOMUXC_GPIO_SD_B1_08_LPUART7_TX { + pinmux = <0x401f81f4 2 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai1_tx_bclk: IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK { + pinmux = <0x401f81f4 3 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_semc_csx2: IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 { + pinmux = <0x401f81f4 6 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f81f4 0 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data1: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 { + pinmux = <0x401f81f8 1 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io09: IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio8_io09: IOMUXC_GPIO_SD_B1_09_GPIO8_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f81f8 4 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpuart7_rx: IOMUXC_GPIO_SD_B1_09_LPUART7_RX { + pinmux = <0x401f81f8 2 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai1_tx_sync: IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC { + pinmux = <0x401f81f8 3 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f81f8 0 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data2: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 { + pinmux = <0x401f81fc 1 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io10: IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio8_io10: IOMUXC_GPIO_SD_B1_10_GPIO8_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpi2c2_sda: IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA { + pinmux = <0x401f81fc 3 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f81fc 4 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpuart2_rx: IOMUXC_GPIO_SD_B1_10_LPUART2_RX { + pinmux = <0x401f81fc 2 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f81fc 0 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_data3: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 { + pinmux = <0x401f8200 1 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io11: IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio8_io11: IOMUXC_GPIO_SD_B1_11_GPIO8_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpi2c2_scl: IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL { + pinmux = <0x401f8200 3 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8200 4 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpuart2_tx: IOMUXC_GPIO_SD_B1_11_LPUART2_TX { + pinmux = <0x401f8200 2 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8200 0 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x0 0 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1042djm6b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1042djm6b-pinctrl.dtsi new file mode 100644 index 000000000..ba6ad70cb --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1042djm6b-pinctrl.dtsi @@ -0,0 +1,3200 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1042DJM6B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_tx_data3: IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA3 { + pinmux = <0x401f80cc 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio6_io04: IOMUXC_GPIO_AD_B0_04_GPIO6_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_mqs_right: IOMUXC_GPIO_AD_B0_04_MQS_RIGHT { + pinmux = <0x401f80cc 1 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_pit_trigger0: IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER0 { + pinmux = <0x401f80cc 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_sai2_tx_sync: IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC { + pinmux = <0x401f80cc 3 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_src_boot_mode0: IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE0 { + pinmux = <0x401f80cc 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_tx_data2: IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA2 { + pinmux = <0x401f80d0 2 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio6_io05: IOMUXC_GPIO_AD_B0_05_GPIO6_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_mqs_left: IOMUXC_GPIO_AD_B0_05_MQS_LEFT { + pinmux = <0x401f80d0 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_sai2_tx_bclk: IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f80d0 3 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_src_boot_mode1: IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE1 { + pinmux = <0x401f80d0 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_IN17 { + pinmux = <0x401f80d0 6 0x0 0 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80d0 6 0x0 0 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_enet_rx_clk: IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK { + pinmux = <0x401f80d4 2 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio6_io06: IOMUXC_GPIO_AD_B0_06_GPIO6_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpt2_compare1: IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 { + pinmux = <0x401f80d4 1 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_jtag_tms: IOMUXC_GPIO_AD_B0_06_JTAG_TMS { + pinmux = <0x401f80d4 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_sai2_rx_bclk: IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK { + pinmux = <0x401f80d4 3 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_in18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_IN18 { + pinmux = <0x401f80d4 6 0x0 0 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_inout18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80d4 6 0x0 0 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_1588_event3_out: IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT { + pinmux = <0x401f80d8 7 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_tx_er: IOMUXC_GPIO_AD_B0_07_ENET_TX_ER { + pinmux = <0x401f80d8 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio6_io07: IOMUXC_GPIO_AD_B0_07_GPIO6_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpt2_compare2: IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 { + pinmux = <0x401f80d8 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_jtag_tck: IOMUXC_GPIO_AD_B0_07_JTAG_TCK { + pinmux = <0x401f80d8 0 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_sai2_rx_sync: IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC { + pinmux = <0x401f80d8 3 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_in19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_IN19 { + pinmux = <0x401f80d8 6 0x0 0 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_inout19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80d8 6 0x0 0 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_1588_event3_in: IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN { + pinmux = <0x401f80dc 7 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_rx_data3: IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA3 { + pinmux = <0x401f80dc 2 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio6_io08: IOMUXC_GPIO_AD_B0_08_GPIO6_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpt2_compare3: IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 { + pinmux = <0x401f80dc 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_jtag_mod: IOMUXC_GPIO_AD_B0_08_JTAG_MOD { + pinmux = <0x401f80dc 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_sai2_rx_data: IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA { + pinmux = <0x401f80dc 3 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_xbar1_xbar_in20: IOMUXC_GPIO_AD_B0_08_XBAR1_XBAR_IN20 { + pinmux = <0x401f80dc 6 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data2: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA2 { + pinmux = <0x401f80e0 2 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA3 { + pinmux = <0x401f80e0 1 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio6_io09: IOMUXC_GPIO_AD_B0_09_GPIO6_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpt2_clk: IOMUXC_GPIO_AD_B0_09_GPT2_CLK { + pinmux = <0x401f80e0 7 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_jtag_tdi: IOMUXC_GPIO_AD_B0_09_JTAG_TDI { + pinmux = <0x401f80e0 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_sai2_tx_data: IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA { + pinmux = <0x401f80e0 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_semc_dqs4: IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 { + pinmux = <0x401f80e0 9 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_xbar1_xbar_in21: IOMUXC_GPIO_AD_B0_09_XBAR1_XBAR_IN21 { + pinmux = <0x401f80e0 6 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_swo: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO { + pinmux = <0x401f80e4 9 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80e4 7 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_crs: IOMUXC_GPIO_AD_B0_10_ENET_CRS { + pinmux = <0x401f80e4 2 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexcan3_tx: IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX { + pinmux = <0x401f80e4 8 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm1_pwma3: IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA3 { + pinmux = <0x401f80e4 1 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio6_io10: IOMUXC_GPIO_AD_B0_10_GPIO6_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_jtag_tdo: IOMUXC_GPIO_AD_B0_10_JTAG_TDO { + pinmux = <0x401f80e4 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_sai2_mclk: IOMUXC_GPIO_AD_B0_10_SAI2_MCLK { + pinmux = <0x401f80e4 3 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_xbar1_xbar_in22: IOMUXC_GPIO_AD_B0_10_XBAR1_XBAR_IN22 { + pinmux = <0x401f80e4 6 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN { + pinmux = <0x401f80e8 7 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_col: IOMUXC_GPIO_AD_B0_11_ENET_COL { + pinmux = <0x401f80e8 2 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexcan3_rx: IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX { + pinmux = <0x401f80e8 8 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB3 { + pinmux = <0x401f80e8 1 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio6_io11: IOMUXC_GPIO_AD_B0_11_GPIO6_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_jtag_trstb: IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB { + pinmux = <0x401f80e8 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_semc_clk6: IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 { + pinmux = <0x401f80e8 9 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_wdog1_b: IOMUXC_GPIO_AD_B0_11_WDOG1_B { + pinmux = <0x401f80e8 3 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_xbar1_xbar_in23: IOMUXC_GPIO_AD_B0_11_XBAR1_XBAR_IN23 { + pinmux = <0x401f80e8 6 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in1: IOMUXC_GPIO_AD_B0_12_ADC1_IN1 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_nmi: IOMUXC_GPIO_AD_B0_12_ARM_NMI { + pinmux = <0x401f80ec 7 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_12_CCM_PMIC_RDY { + pinmux = <0x401f80ec 1 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_1588_event1_out: IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT { + pinmux = <0x401f80ec 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm1_pwmx2: IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX2 { + pinmux = <0x401f80ec 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio6_io12: IOMUXC_GPIO_AD_B0_12_GPIO6_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpi2c4_scl: IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL { + pinmux = <0x401f80ec 0 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart1_tx: IOMUXC_GPIO_AD_B0_12_LPUART1_TX { + pinmux = <0x401f80ec 2 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_wdog2_b: IOMUXC_GPIO_AD_B0_12_WDOG2_B { + pinmux = <0x401f80ec 3 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_acmp1_in2: IOMUXC_GPIO_AD_B0_13_ACMP1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc1_in2: IOMUXC_GPIO_AD_B0_13_ADC1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_1588_event1_in: IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN { + pinmux = <0x401f80f0 6 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ewm_out_b: IOMUXC_GPIO_AD_B0_13_EWM_OUT_B { + pinmux = <0x401f80f0 3 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm1_pwmx3: IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX3 { + pinmux = <0x401f80f0 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio6_io13: IOMUXC_GPIO_AD_B0_13_GPIO6_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpt1_clk: IOMUXC_GPIO_AD_B0_13_GPT1_CLK { + pinmux = <0x401f80f0 1 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpi2c4_sda: IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA { + pinmux = <0x401f80f0 0 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart1_rx: IOMUXC_GPIO_AD_B0_13_LPUART1_RX { + pinmux = <0x401f80f0 2 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ref_24m_out: IOMUXC_GPIO_AD_B0_13_REF_24M_OUT { + pinmux = <0x401f80f0 7 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in2: IOMUXC_GPIO_AD_B0_14_ACMP2_IN2 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in3: IOMUXC_GPIO_AD_B0_14_ADC1_IN3 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80f4 3 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan3_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX { + pinmux = <0x401f80f4 8 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio6_io14: IOMUXC_GPIO_AD_B0_14_GPIO6_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B { + pinmux = <0x401f80f4 2 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_xbar1_xbar_in24: IOMUXC_GPIO_AD_B0_14_XBAR1_XBAR_IN24 { + pinmux = <0x401f80f4 1 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in2: IOMUXC_GPIO_AD_B0_15_ACMP3_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in4: IOMUXC_GPIO_AD_B0_15_ADC1_IN4 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f80f8 3 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 6 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan3_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX { + pinmux = <0x401f80f8 8 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio6_io15: IOMUXC_GPIO_AD_B0_15_GPIO6_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B { + pinmux = <0x401f80f8 2 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb: IOMUXC_GPIO_AD_B0_15_WDOG1_RST_B_DEB { + pinmux = <0x401f80f8 7 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_xbar1_xbar_in25: IOMUXC_GPIO_AD_B0_15_XBAR1_XBAR_IN25 { + pinmux = <0x401f80f8 1 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp4_in2: IOMUXC_GPIO_AD_B1_00_ACMP4_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc1_in5: IOMUXC_GPIO_AD_B1_00_ADC1_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc2_in5: IOMUXC_GPIO_AD_B1_00_ADC2_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio3_flexio00: IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 { + pinmux = <0x401f80fc 9 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio6_io16: IOMUXC_GPIO_AD_B1_00_GPIO6_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpi2c1_scl: IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL { + pinmux = <0x401f80fc 3 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B { + pinmux = <0x401f80fc 2 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_qtimer3_timer0: IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 { + pinmux = <0x401f80fc 1 0x0 0 0x401f82ec>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usdhc1_wp: IOMUXC_GPIO_AD_B1_00_USDHC1_WP { + pinmux = <0x401f80fc 6 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_wdog1_b: IOMUXC_GPIO_AD_B1_00_WDOG1_B { + pinmux = <0x401f80fc 4 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp1_in0: IOMUXC_GPIO_AD_B1_01_ACMP1_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in0: IOMUXC_GPIO_AD_B1_01_ACMP2_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp3_in0: IOMUXC_GPIO_AD_B1_01_ACMP3_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp4_in0: IOMUXC_GPIO_AD_B1_01_ACMP4_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in6: IOMUXC_GPIO_AD_B1_01_ADC1_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc2_in6: IOMUXC_GPIO_AD_B1_01_ADC2_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_01_CCM_PMIC_RDY { + pinmux = <0x401f8100 4 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio3_flexio01: IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 { + pinmux = <0x401f8100 9 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio6_io17: IOMUXC_GPIO_AD_B1_01_GPIO6_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpi2c1_sda: IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA { + pinmux = <0x401f8100 3 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B { + pinmux = <0x401f8100 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_qtimer3_timer1: IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 { + pinmux = <0x401f8100 1 0x0 0 0x401f82f0>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR { + pinmux = <0x401f8100 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usdhc1_vselect: IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT { + pinmux = <0x401f8100 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp1_in3: IOMUXC_GPIO_AD_B1_02_ACMP1_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc1_in7: IOMUXC_GPIO_AD_B1_02_ADC1_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in7: IOMUXC_GPIO_AD_B1_02_ADC2_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT { + pinmux = <0x401f8104 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio3_flexio02: IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 { + pinmux = <0x401f8104 9 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio6_io18: IOMUXC_GPIO_AD_B1_02_GPIO6_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpt2_clk: IOMUXC_GPIO_AD_B1_02_GPT2_CLK { + pinmux = <0x401f8104 8 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpuart2_tx: IOMUXC_GPIO_AD_B1_02_LPUART2_TX { + pinmux = <0x401f8104 2 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_qtimer3_timer2: IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 { + pinmux = <0x401f8104 1 0x0 0 0x401f82f4>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_spdif_out: IOMUXC_GPIO_AD_B1_02_SPDIF_OUT { + pinmux = <0x401f8104 3 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usb_otg1_id: IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID { + pinmux = <0x401f8104 0 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B { + pinmux = <0x401f8104 6 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp2_in3: IOMUXC_GPIO_AD_B1_03_ACMP2_IN3 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in8: IOMUXC_GPIO_AD_B1_03_ADC1_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc2_in8: IOMUXC_GPIO_AD_B1_03_ADC2_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN { + pinmux = <0x401f8108 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio3_flexio03: IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 { + pinmux = <0x401f8108 9 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio6_io19: IOMUXC_GPIO_AD_B1_03_GPIO6_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpt2_capture1: IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 { + pinmux = <0x401f8108 8 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpuart2_rx: IOMUXC_GPIO_AD_B1_03_LPUART2_RX { + pinmux = <0x401f8108 2 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_qtimer3_timer3: IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 { + pinmux = <0x401f8108 1 0x0 0 0x401f82f8>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_spdif_in: IOMUXC_GPIO_AD_B1_03_SPDIF_IN { + pinmux = <0x401f8108 3 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usb_otg1_oc: IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC { + pinmux = <0x401f8108 0 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B { + pinmux = <0x401f8108 6 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp3_in3: IOMUXC_GPIO_AD_B1_04_ACMP3_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc1_in9: IOMUXC_GPIO_AD_B1_04_ADC1_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in9: IOMUXC_GPIO_AD_B1_04_ADC2_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_enet_mdc: IOMUXC_GPIO_AD_B1_04_ENET_MDC { + pinmux = <0x401f810c 1 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio3_flexio04: IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 { + pinmux = <0x401f810c 9 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_b_data3: IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 { + pinmux = <0x401f810c 0 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio6_io20: IOMUXC_GPIO_AD_B1_04_GPIO6_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpt2_capture2: IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 { + pinmux = <0x401f810c 8 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpuart3_cts_b: IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B { + pinmux = <0x401f810c 2 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_spdif_sr_clk: IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK { + pinmux = <0x401f810c 3 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_usdhc2_data0: IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f810c 6 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp4_in3: IOMUXC_GPIO_AD_B1_05_ACMP4_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in10: IOMUXC_GPIO_AD_B1_05_ADC1_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in10: IOMUXC_GPIO_AD_B1_05_ADC2_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_enet_mdio: IOMUXC_GPIO_AD_B1_05_ENET_MDIO { + pinmux = <0x401f8110 1 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio3_flexio05: IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 { + pinmux = <0x401f8110 9 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_b_data2: IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 { + pinmux = <0x401f8110 0 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio6_io21: IOMUXC_GPIO_AD_B1_05_GPIO6_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpt2_compare1: IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 { + pinmux = <0x401f8110 8 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpuart3_rts_b: IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B { + pinmux = <0x401f8110 2 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_spdif_out: IOMUXC_GPIO_AD_B1_05_SPDIF_OUT { + pinmux = <0x401f8110 3 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc2_data1: IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f8110 6 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp1_in1: IOMUXC_GPIO_AD_B1_06_ACMP1_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp2_in1: IOMUXC_GPIO_AD_B1_06_ACMP2_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in1: IOMUXC_GPIO_AD_B1_06_ACMP3_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp4_in1: IOMUXC_GPIO_AD_B1_06_ACMP4_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in11: IOMUXC_GPIO_AD_B1_06_ADC1_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in11: IOMUXC_GPIO_AD_B1_06_ADC2_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio3_flexio06: IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 { + pinmux = <0x401f8114 9 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexspi_b_data1: IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 { + pinmux = <0x401f8114 0 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio6_io22: IOMUXC_GPIO_AD_B1_06_GPIO6_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpt2_compare2: IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 { + pinmux = <0x401f8114 8 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpi2c3_sda: IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA { + pinmux = <0x401f8114 1 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart3_tx: IOMUXC_GPIO_AD_B1_06_LPUART3_TX { + pinmux = <0x401f8114 2 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_spdif_lock: IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK { + pinmux = <0x401f8114 3 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc2_data2: IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 { + pinmux = <0x401f8114 6 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp1_in5: IOMUXC_GPIO_AD_B1_07_ACMP1_IN5 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in12: IOMUXC_GPIO_AD_B1_07_ADC1_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in12: IOMUXC_GPIO_AD_B1_07_ADC2_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio3_flexio07: IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 { + pinmux = <0x401f8118 9 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexspi_b_data0: IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 { + pinmux = <0x401f8118 0 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio6_io23: IOMUXC_GPIO_AD_B1_07_GPIO6_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpt2_compare3: IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 { + pinmux = <0x401f8118 8 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpi2c3_scl: IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL { + pinmux = <0x401f8118 1 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart3_rx: IOMUXC_GPIO_AD_B1_07_LPUART3_RX { + pinmux = <0x401f8118 2 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_spdif_ext_clk: IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK { + pinmux = <0x401f8118 3 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc2_data3: IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 { + pinmux = <0x401f8118 6 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_flexio2_flexio00: IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 { + pinmux = <0x401f813c 4 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio2_io00: IOMUXC_GPIO_B0_00_GPIO2_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio7_io00: IOMUXC_GPIO_B0_00_GPIO7_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lcdif_clk: IOMUXC_GPIO_B0_00_LCDIF_CLK { + pinmux = <0x401f813c 0 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lpspi3_pcs0: IOMUXC_GPIO_B0_00_LPSPI3_PCS0 { + pinmux = <0x401f813c 3 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_mqs_right: IOMUXC_GPIO_B0_00_MQS_RIGHT { + pinmux = <0x401f813c 2 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_qtimer1_timer0: IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x0 0 0x401f832c>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_semc_csx1: IOMUXC_GPIO_B0_00_SEMC_CSX1 { + pinmux = <0x401f813c 6 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_flexio2_flexio01: IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 { + pinmux = <0x401f8140 4 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio2_io01: IOMUXC_GPIO_B0_01_GPIO2_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio7_io01: IOMUXC_GPIO_B0_01_GPIO7_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lcdif_enable: IOMUXC_GPIO_B0_01_LCDIF_ENABLE { + pinmux = <0x401f8140 0 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lpspi3_sdi: IOMUXC_GPIO_B0_01_LPSPI3_SDI { + pinmux = <0x401f8140 3 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_mqs_left: IOMUXC_GPIO_B0_01_MQS_LEFT { + pinmux = <0x401f8140 2 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_qtimer1_timer1: IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x0 0 0x401f8330>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_semc_csx2: IOMUXC_GPIO_B0_01_SEMC_CSX2 { + pinmux = <0x401f8140 6 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexcan1_tx: IOMUXC_GPIO_B0_02_FLEXCAN1_TX { + pinmux = <0x401f8144 2 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexio2_flexio02: IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 { + pinmux = <0x401f8144 4 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio2_io02: IOMUXC_GPIO_B0_02_GPIO2_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio7_io02: IOMUXC_GPIO_B0_02_GPIO7_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lcdif_hsync: IOMUXC_GPIO_B0_02_LCDIF_HSYNC { + pinmux = <0x401f8144 0 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lpspi3_sdo: IOMUXC_GPIO_B0_02_LPSPI3_SDO { + pinmux = <0x401f8144 3 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_qtimer1_timer2: IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x0 0 0x401f8334>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_semc_csx3: IOMUXC_GPIO_B0_02_SEMC_CSX3 { + pinmux = <0x401f8144 6 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexcan1_rx: IOMUXC_GPIO_B0_03_FLEXCAN1_RX { + pinmux = <0x401f8148 2 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexio2_flexio03: IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 { + pinmux = <0x401f8148 4 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio2_io03: IOMUXC_GPIO_B0_03_GPIO2_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio7_io03: IOMUXC_GPIO_B0_03_GPIO7_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lcdif_vsync: IOMUXC_GPIO_B0_03_LCDIF_VSYNC { + pinmux = <0x401f8148 0 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lpspi3_sck: IOMUXC_GPIO_B0_03_LPSPI3_SCK { + pinmux = <0x401f8148 3 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_qtimer2_timer0: IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 { + pinmux = <0x401f8148 1 0x0 0 0x401f8338>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_wdog2_rst_b_deb: IOMUXC_GPIO_B0_03_WDOG2_RST_B_DEB { + pinmux = <0x401f8148 6 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_arm_trace0: IOMUXC_GPIO_B0_04_ARM_TRACE0 { + pinmux = <0x401f814c 3 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_flexio2_flexio04: IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 { + pinmux = <0x401f814c 4 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio2_io04: IOMUXC_GPIO_B0_04_GPIO2_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio7_io04: IOMUXC_GPIO_B0_04_GPIO7_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lcdif_data00: IOMUXC_GPIO_B0_04_LCDIF_DATA00 { + pinmux = <0x401f814c 0 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lpi2c2_scl: IOMUXC_GPIO_B0_04_LPI2C2_SCL { + pinmux = <0x401f814c 2 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_qtimer2_timer1: IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 { + pinmux = <0x401f814c 1 0x0 0 0x401f833c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_src_bt_cfg0: IOMUXC_GPIO_B0_04_SRC_BT_CFG0 { + pinmux = <0x401f814c 6 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_arm_trace1: IOMUXC_GPIO_B0_05_ARM_TRACE1 { + pinmux = <0x401f8150 3 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_flexio2_flexio05: IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 { + pinmux = <0x401f8150 4 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio2_io05: IOMUXC_GPIO_B0_05_GPIO2_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio7_io05: IOMUXC_GPIO_B0_05_GPIO7_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lcdif_data01: IOMUXC_GPIO_B0_05_LCDIF_DATA01 { + pinmux = <0x401f8150 0 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lpi2c2_sda: IOMUXC_GPIO_B0_05_LPI2C2_SDA { + pinmux = <0x401f8150 2 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_qtimer2_timer2: IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 { + pinmux = <0x401f8150 1 0x0 0 0x401f8340>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_src_bt_cfg1: IOMUXC_GPIO_B0_05_SRC_BT_CFG1 { + pinmux = <0x401f8150 6 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_arm_trace2: IOMUXC_GPIO_B0_06_ARM_TRACE2 { + pinmux = <0x401f8154 3 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexio2_flexio06: IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 { + pinmux = <0x401f8154 4 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexpwm2_pwma0: IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f8154 2 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio2_io06: IOMUXC_GPIO_B0_06_GPIO2_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio7_io06: IOMUXC_GPIO_B0_06_GPIO7_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_lcdif_data02: IOMUXC_GPIO_B0_06_LCDIF_DATA02 { + pinmux = <0x401f8154 0 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_qtimer3_timer0: IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 { + pinmux = <0x401f8154 1 0x0 0 0x401f8344>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_src_bt_cfg2: IOMUXC_GPIO_B0_06_SRC_BT_CFG2 { + pinmux = <0x401f8154 6 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_arm_trace3: IOMUXC_GPIO_B0_07_ARM_TRACE3 { + pinmux = <0x401f8158 3 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexio2_flexio07: IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 { + pinmux = <0x401f8158 4 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexpwm2_pwmb0: IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8158 2 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio2_io07: IOMUXC_GPIO_B0_07_GPIO2_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio7_io07: IOMUXC_GPIO_B0_07_GPIO7_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_lcdif_data03: IOMUXC_GPIO_B0_07_LCDIF_DATA03 { + pinmux = <0x401f8158 0 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_qtimer3_timer1: IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 { + pinmux = <0x401f8158 1 0x0 0 0x401f8348>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_src_bt_cfg3: IOMUXC_GPIO_B0_07_SRC_BT_CFG3 { + pinmux = <0x401f8158 6 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexio2_flexio08: IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 { + pinmux = <0x401f815c 4 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexpwm2_pwma1: IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f815c 2 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio2_io08: IOMUXC_GPIO_B0_08_GPIO2_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio7_io08: IOMUXC_GPIO_B0_08_GPIO7_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lcdif_data04: IOMUXC_GPIO_B0_08_LCDIF_DATA04 { + pinmux = <0x401f815c 0 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lpuart3_tx: IOMUXC_GPIO_B0_08_LPUART3_TX { + pinmux = <0x401f815c 3 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_qtimer3_timer2: IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 { + pinmux = <0x401f815c 1 0x0 0 0x401f834c>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_src_bt_cfg4: IOMUXC_GPIO_B0_08_SRC_BT_CFG4 { + pinmux = <0x401f815c 6 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexio2_flexio09: IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 { + pinmux = <0x401f8160 4 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexpwm2_pwmb1: IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8160 2 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio2_io09: IOMUXC_GPIO_B0_09_GPIO2_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio7_io09: IOMUXC_GPIO_B0_09_GPIO7_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lcdif_data05: IOMUXC_GPIO_B0_09_LCDIF_DATA05 { + pinmux = <0x401f8160 0 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lpuart3_rx: IOMUXC_GPIO_B0_09_LPUART3_RX { + pinmux = <0x401f8160 3 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_qtimer4_timer0: IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 { + pinmux = <0x401f8160 1 0x0 0 0x401f8350>; + gpr = <0x400ac018 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_src_bt_cfg5: IOMUXC_GPIO_B0_09_SRC_BT_CFG5 { + pinmux = <0x401f8160 6 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexio2_flexio10: IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 { + pinmux = <0x401f8164 4 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f8164 2 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio2_io10: IOMUXC_GPIO_B0_10_GPIO2_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio7_io10: IOMUXC_GPIO_B0_10_GPIO7_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_lcdif_data06: IOMUXC_GPIO_B0_10_LCDIF_DATA06 { + pinmux = <0x401f8164 0 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_qtimer4_timer1: IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 { + pinmux = <0x401f8164 1 0x0 0 0x401f8354>; + gpr = <0x400ac018 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_sai1_tx_data3: IOMUXC_GPIO_B0_10_SAI1_TX_DATA3 { + pinmux = <0x401f8164 3 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_src_bt_cfg6: IOMUXC_GPIO_B0_10_SRC_BT_CFG6 { + pinmux = <0x401f8164 6 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexio2_flexio11: IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 { + pinmux = <0x401f8168 4 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8168 2 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio2_io11: IOMUXC_GPIO_B0_11_GPIO2_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio7_io11: IOMUXC_GPIO_B0_11_GPIO7_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_lcdif_data07: IOMUXC_GPIO_B0_11_LCDIF_DATA07 { + pinmux = <0x401f8168 0 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_qtimer4_timer2: IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 { + pinmux = <0x401f8168 1 0x0 0 0x401f8358>; + gpr = <0x400ac018 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_sai1_tx_data2: IOMUXC_GPIO_B0_11_SAI1_TX_DATA2 { + pinmux = <0x401f8168 3 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_src_bt_cfg7: IOMUXC_GPIO_B0_11_SRC_BT_CFG7 { + pinmux = <0x401f8168 6 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_arm_trace_clk: IOMUXC_GPIO_B0_12_ARM_TRACE_CLK { + pinmux = <0x401f816c 2 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_flexio2_flexio12: IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 { + pinmux = <0x401f816c 4 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio2_io12: IOMUXC_GPIO_B0_12_GPIO2_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio7_io12: IOMUXC_GPIO_B0_12_GPIO7_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_lcdif_data08: IOMUXC_GPIO_B0_12_LCDIF_DATA08 { + pinmux = <0x401f816c 0 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_sai1_tx_data1: IOMUXC_GPIO_B0_12_SAI1_TX_DATA1 { + pinmux = <0x401f816c 3 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_src_bt_cfg8: IOMUXC_GPIO_B0_12_SRC_BT_CFG8 { + pinmux = <0x401f816c 6 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_in10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_IN10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_inout10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_arm_trace_swo: IOMUXC_GPIO_B0_13_ARM_TRACE_SWO { + pinmux = <0x401f8170 2 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_flexio2_flexio13: IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 { + pinmux = <0x401f8170 4 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio2_io13: IOMUXC_GPIO_B0_13_GPIO2_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio7_io13: IOMUXC_GPIO_B0_13_GPIO7_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_lcdif_data09: IOMUXC_GPIO_B0_13_LCDIF_DATA09 { + pinmux = <0x401f8170 0 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_sai1_mclk: IOMUXC_GPIO_B0_13_SAI1_MCLK { + pinmux = <0x401f8170 3 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_src_bt_cfg9: IOMUXC_GPIO_B0_13_SRC_BT_CFG9 { + pinmux = <0x401f8170 6 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_in11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_IN11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_inout11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_flexio2_flexio14: IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 { + pinmux = <0x401f8174 4 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio2_io14: IOMUXC_GPIO_B0_14_GPIO2_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio7_io14: IOMUXC_GPIO_B0_14_GPIO7_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_lcdif_data10: IOMUXC_GPIO_B0_14_LCDIF_DATA10 { + pinmux = <0x401f8174 0 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_sai1_rx_sync: IOMUXC_GPIO_B0_14_SAI1_RX_SYNC { + pinmux = <0x401f8174 3 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_src_bt_cfg10: IOMUXC_GPIO_B0_14_SRC_BT_CFG10 { + pinmux = <0x401f8174 6 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_in12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_IN12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_inout12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_flexio2_flexio15: IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 { + pinmux = <0x401f8178 4 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio2_io15: IOMUXC_GPIO_B0_15_GPIO2_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio7_io15: IOMUXC_GPIO_B0_15_GPIO7_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_lcdif_data11: IOMUXC_GPIO_B0_15_LCDIF_DATA11 { + pinmux = <0x401f8178 0 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_sai1_rx_bclk: IOMUXC_GPIO_B0_15_SAI1_RX_BCLK { + pinmux = <0x401f8178 3 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_src_bt_cfg11: IOMUXC_GPIO_B0_15_SRC_BT_CFG11 { + pinmux = <0x401f8178 6 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_in13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_IN13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_inout13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio2_flexio16: IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 { + pinmux = <0x401f817c 4 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio3_flexio16: IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 { + pinmux = <0x401f817c 9 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f817c 6 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio2_io16: IOMUXC_GPIO_B1_00_GPIO2_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio7_io16: IOMUXC_GPIO_B1_00_GPIO7_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lcdif_data12: IOMUXC_GPIO_B1_00_LCDIF_DATA12 { + pinmux = <0x401f817c 0 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lpuart4_tx: IOMUXC_GPIO_B1_00_LPUART4_TX { + pinmux = <0x401f817c 2 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_sai1_rx_data0: IOMUXC_GPIO_B1_00_SAI1_RX_DATA0 { + pinmux = <0x401f817c 3 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_in14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f817c 1 0x0 0 0x401f836c>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_inout14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f817c 1 0x0 0 0x401f836c>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio2_flexio17: IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 { + pinmux = <0x401f8180 4 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio3_flexio17: IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 { + pinmux = <0x401f8180 9 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f8180 6 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio2_io17: IOMUXC_GPIO_B1_01_GPIO2_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio7_io17: IOMUXC_GPIO_B1_01_GPIO7_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lcdif_data13: IOMUXC_GPIO_B1_01_LCDIF_DATA13 { + pinmux = <0x401f8180 0 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lpuart4_rx: IOMUXC_GPIO_B1_01_LPUART4_RX { + pinmux = <0x401f8180 2 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_sai1_tx_data0: IOMUXC_GPIO_B1_01_SAI1_TX_DATA0 { + pinmux = <0x401f8180 3 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_in15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8180 1 0x0 0 0x401f8370>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_inout15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8180 1 0x0 0 0x401f8370>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio2_flexio18: IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 { + pinmux = <0x401f8184 4 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio3_flexio18: IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 { + pinmux = <0x401f8184 9 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f8184 6 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio2_io18: IOMUXC_GPIO_B1_02_GPIO2_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio7_io18: IOMUXC_GPIO_B1_02_GPIO7_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lcdif_data14: IOMUXC_GPIO_B1_02_LCDIF_DATA14 { + pinmux = <0x401f8184 0 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lpspi3_pcs2: IOMUXC_GPIO_B1_02_LPSPI3_PCS2 { + pinmux = <0x401f8184 2 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_sai1_tx_bclk: IOMUXC_GPIO_B1_02_SAI1_TX_BCLK { + pinmux = <0x401f8184 3 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_in16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8184 1 0x0 0 0x401f8374>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_inout16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8184 1 0x0 0 0x401f8374>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio2_flexio19: IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 { + pinmux = <0x401f8188 4 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio3_flexio19: IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 { + pinmux = <0x401f8188 9 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f8188 6 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio2_io19: IOMUXC_GPIO_B1_03_GPIO2_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio7_io19: IOMUXC_GPIO_B1_03_GPIO7_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lcdif_data15: IOMUXC_GPIO_B1_03_LCDIF_DATA15 { + pinmux = <0x401f8188 0 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lpspi3_pcs1: IOMUXC_GPIO_B1_03_LPSPI3_PCS1 { + pinmux = <0x401f8188 2 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_sai1_tx_sync: IOMUXC_GPIO_B1_03_SAI1_TX_SYNC { + pinmux = <0x401f8188 3 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_in17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f8188 1 0x0 0 0x401f8378>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_inout17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8188 1 0x0 0 0x401f8378>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_enet_rx_data0: IOMUXC_GPIO_B1_04_ENET_RX_DATA0 { + pinmux = <0x401f818c 3 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio2_flexio20: IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 { + pinmux = <0x401f818c 4 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio3_flexio20: IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 { + pinmux = <0x401f818c 9 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio2_io20: IOMUXC_GPIO_B1_04_GPIO2_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio7_io20: IOMUXC_GPIO_B1_04_GPIO7_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpt1_clk: IOMUXC_GPIO_B1_04_GPT1_CLK { + pinmux = <0x401f818c 8 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lcdif_data16: IOMUXC_GPIO_B1_04_LCDIF_DATA16 { + pinmux = <0x401f818c 0 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lpspi3_pcs0: IOMUXC_GPIO_B1_04_LPSPI3_PCS0 { + pinmux = <0x401f818c 1 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_enet_rx_data1: IOMUXC_GPIO_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f8190 3 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio2_flexio21: IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 { + pinmux = <0x401f8190 4 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio3_flexio21: IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 { + pinmux = <0x401f8190 9 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio2_io21: IOMUXC_GPIO_B1_05_GPIO2_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio7_io21: IOMUXC_GPIO_B1_05_GPIO7_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpt1_capture1: IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 { + pinmux = <0x401f8190 8 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lcdif_data17: IOMUXC_GPIO_B1_05_LCDIF_DATA17 { + pinmux = <0x401f8190 0 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lpspi3_sdi: IOMUXC_GPIO_B1_05_LPSPI3_SDI { + pinmux = <0x401f8190 1 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_enet_rx_en: IOMUXC_GPIO_B1_06_ENET_RX_EN { + pinmux = <0x401f8194 3 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio2_flexio22: IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 { + pinmux = <0x401f8194 4 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio3_flexio22: IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 { + pinmux = <0x401f8194 9 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio2_io22: IOMUXC_GPIO_B1_06_GPIO2_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio7_io22: IOMUXC_GPIO_B1_06_GPIO7_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpt1_capture2: IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 { + pinmux = <0x401f8194 8 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lcdif_data18: IOMUXC_GPIO_B1_06_LCDIF_DATA18 { + pinmux = <0x401f8194 0 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lpspi3_sdo: IOMUXC_GPIO_B1_06_LPSPI3_SDO { + pinmux = <0x401f8194 1 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_enet_tx_data0: IOMUXC_GPIO_B1_07_ENET_TX_DATA0 { + pinmux = <0x401f8198 3 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio2_flexio23: IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 { + pinmux = <0x401f8198 4 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio3_flexio23: IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 { + pinmux = <0x401f8198 9 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio2_io23: IOMUXC_GPIO_B1_07_GPIO2_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio7_io23: IOMUXC_GPIO_B1_07_GPIO7_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpt1_compare1: IOMUXC_GPIO_B1_07_GPT1_COMPARE1 { + pinmux = <0x401f8198 8 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lcdif_data19: IOMUXC_GPIO_B1_07_LCDIF_DATA19 { + pinmux = <0x401f8198 0 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lpspi3_sck: IOMUXC_GPIO_B1_07_LPSPI3_SCK { + pinmux = <0x401f8198 1 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_enet_tx_data1: IOMUXC_GPIO_B1_08_ENET_TX_DATA1 { + pinmux = <0x401f819c 3 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexcan2_tx: IOMUXC_GPIO_B1_08_FLEXCAN2_TX { + pinmux = <0x401f819c 6 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio2_flexio24: IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 { + pinmux = <0x401f819c 4 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio3_flexio24: IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 { + pinmux = <0x401f819c 9 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio2_io24: IOMUXC_GPIO_B1_08_GPIO2_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio7_io24: IOMUXC_GPIO_B1_08_GPIO7_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpt1_compare2: IOMUXC_GPIO_B1_08_GPT1_COMPARE2 { + pinmux = <0x401f819c 8 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_lcdif_data20: IOMUXC_GPIO_B1_08_LCDIF_DATA20 { + pinmux = <0x401f819c 0 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_qtimer1_timer3: IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 { + pinmux = <0x401f819c 1 0x0 0 0x401f838c>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_enet_tx_en: IOMUXC_GPIO_B1_09_ENET_TX_EN { + pinmux = <0x401f81a0 3 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexcan2_rx: IOMUXC_GPIO_B1_09_FLEXCAN2_RX { + pinmux = <0x401f81a0 6 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio2_flexio25: IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 { + pinmux = <0x401f81a0 4 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio3_flexio25: IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 { + pinmux = <0x401f81a0 9 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio2_io25: IOMUXC_GPIO_B1_09_GPIO2_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio7_io25: IOMUXC_GPIO_B1_09_GPIO7_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpt1_compare3: IOMUXC_GPIO_B1_09_GPT1_COMPARE3 { + pinmux = <0x401f81a0 8 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_lcdif_data21: IOMUXC_GPIO_B1_09_LCDIF_DATA21 { + pinmux = <0x401f81a0 0 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_qtimer2_timer3: IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 { + pinmux = <0x401f81a0 1 0x0 0 0x401f8390>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_ref_clk: IOMUXC_GPIO_B1_10_ENET_REF_CLK { + pinmux = <0x401f81a4 6 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_tx_clk: IOMUXC_GPIO_B1_10_ENET_TX_CLK { + pinmux = <0x401f81a4 3 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio2_flexio26: IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 { + pinmux = <0x401f81a4 4 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio3_flexio26: IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 { + pinmux = <0x401f81a4 9 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio2_io26: IOMUXC_GPIO_B1_10_GPIO2_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio7_io26: IOMUXC_GPIO_B1_10_GPIO7_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_lcdif_data22: IOMUXC_GPIO_B1_10_LCDIF_DATA22 { + pinmux = <0x401f81a4 0 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_qtimer3_timer3: IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 { + pinmux = <0x401f81a4 1 0x0 0 0x401f8394>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_enet_rx_er: IOMUXC_GPIO_B1_11_ENET_RX_ER { + pinmux = <0x401f81a8 3 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio2_flexio27: IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 { + pinmux = <0x401f81a8 4 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio3_flexio27: IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 { + pinmux = <0x401f81a8 9 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio2_io27: IOMUXC_GPIO_B1_11_GPIO2_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio7_io27: IOMUXC_GPIO_B1_11_GPIO7_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lcdif_data23: IOMUXC_GPIO_B1_11_LCDIF_DATA23 { + pinmux = <0x401f81a8 0 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lpspi3_pcs3: IOMUXC_GPIO_B1_11_LPSPI3_PCS3 { + pinmux = <0x401f81a8 6 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_qtimer4_timer3: IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 { + pinmux = <0x401f81a8 1 0x0 0 0x401f8398>; + gpr = <0x400ac018 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_enet_1588_event0_in: IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN { + pinmux = <0x401f81ac 3 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio2_flexio28: IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 { + pinmux = <0x401f81ac 4 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio3_flexio28: IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 { + pinmux = <0x401f81ac 9 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio2_io28: IOMUXC_GPIO_B1_12_GPIO2_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio7_io28: IOMUXC_GPIO_B1_12_GPIO7_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_lpuart5_tx: IOMUXC_GPIO_B1_12_LPUART5_TX { + pinmux = <0x401f81ac 1 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_usdhc1_cd_b: IOMUXC_GPIO_B1_12_USDHC1_CD_B { + pinmux = <0x401f81ac 6 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_enet_1588_event0_out: IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT { + pinmux = <0x401f81b0 3 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio2_flexio29: IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 { + pinmux = <0x401f81b0 4 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio3_flexio29: IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 { + pinmux = <0x401f81b0 9 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio2_io29: IOMUXC_GPIO_B1_13_GPIO2_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio7_io29: IOMUXC_GPIO_B1_13_GPIO7_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_lpuart5_rx: IOMUXC_GPIO_B1_13_LPUART5_RX { + pinmux = <0x401f81b0 1 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_semc_dqs4: IOMUXC_GPIO_B1_13_SEMC_DQS4 { + pinmux = <0x401f81b0 8 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_usdhc1_wp: IOMUXC_GPIO_B1_13_USDHC1_WP { + pinmux = <0x401f81b0 6 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_wdog1_b: IOMUXC_GPIO_B1_13_WDOG1_B { + pinmux = <0x401f81b0 0 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet_mdc: IOMUXC_GPIO_B1_14_ENET_MDC { + pinmux = <0x401f81b4 0 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio2_flexio30: IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 { + pinmux = <0x401f81b4 4 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio3_flexio30: IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 { + pinmux = <0x401f81b4 9 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexpwm4_pwma2: IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA2 { + pinmux = <0x401f81b4 1 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio2_io30: IOMUXC_GPIO_B1_14_GPIO2_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio7_io30: IOMUXC_GPIO_B1_14_GPIO7_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_usdhc1_vselect: IOMUXC_GPIO_B1_14_USDHC1_VSELECT { + pinmux = <0x401f81b4 6 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_xbar1_xbar_in02: IOMUXC_GPIO_B1_14_XBAR1_XBAR_IN02 { + pinmux = <0x401f81b4 3 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet_mdio: IOMUXC_GPIO_B1_15_ENET_MDIO { + pinmux = <0x401f81b8 0 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio2_flexio31: IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 { + pinmux = <0x401f81b8 4 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio3_flexio31: IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 { + pinmux = <0x401f81b8 9 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexpwm4_pwma3: IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA3 { + pinmux = <0x401f81b8 1 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio2_io31: IOMUXC_GPIO_B1_15_GPIO2_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio7_io31: IOMUXC_GPIO_B1_15_GPIO7_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_usdhc1_reset_b: IOMUXC_GPIO_B1_15_USDHC1_RESET_B { + pinmux = <0x401f81b8 6 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_xbar1_xbar_in03: IOMUXC_GPIO_B1_15_XBAR1_XBAR_IN03 { + pinmux = <0x401f81b8 3 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexio1_flexio00: IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8014 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexpwm4_pwma0: IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA0 { + pinmux = <0x401f8014 1 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio4_io00: IOMUXC_GPIO_EMC_00_GPIO4_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio9_io00: IOMUXC_GPIO_EMC_00_GPIO9_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 2 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_xbar1_xbar_in02: IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 { + pinmux = <0x401f8014 3 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexio1_flexio01: IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8018 4 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexpwm4_pwmb0: IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB0 { + pinmux = <0x401f8018 1 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio4_io01: IOMUXC_GPIO_EMC_01_GPIO4_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio9_io01: IOMUXC_GPIO_EMC_01_GPIO9_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 2 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_xbar1_xbar_in03: IOMUXC_GPIO_EMC_01_XBAR1_XBAR_IN03 { + pinmux = <0x401f8018 3 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexio1_flexio02: IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 { + pinmux = <0x401f801c 4 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexpwm4_pwma1: IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA1 { + pinmux = <0x401f801c 1 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio4_io02: IOMUXC_GPIO_EMC_02_GPIO4_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio9_io02: IOMUXC_GPIO_EMC_02_GPIO9_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 2 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_in04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_IN04 { + pinmux = <0x401f801c 3 0x0 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f801c 3 0x0 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexio1_flexio03: IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 { + pinmux = <0x401f8020 4 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexpwm4_pwmb1: IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB1 { + pinmux = <0x401f8020 1 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio4_io03: IOMUXC_GPIO_EMC_03_GPIO4_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio9_io03: IOMUXC_GPIO_EMC_03_GPIO9_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 2 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_in05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_IN05 { + pinmux = <0x401f8020 3 0x0 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8020 3 0x0 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio04: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8024 4 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexpwm4_pwma2: IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA2 { + pinmux = <0x401f8024 1 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio4_io04: IOMUXC_GPIO_EMC_04_GPIO4_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio9_io04: IOMUXC_GPIO_EMC_04_GPIO9_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_data: IOMUXC_GPIO_EMC_04_SAI2_TX_DATA { + pinmux = <0x401f8024 2 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN06 { + pinmux = <0x401f8024 3 0x0 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f8024 3 0x0 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio05: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8028 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexpwm4_pwmb2: IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB2 { + pinmux = <0x401f8028 1 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio4_io05: IOMUXC_GPIO_EMC_05_GPIO4_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio9_io05: IOMUXC_GPIO_EMC_05_GPIO9_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 2 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN07 { + pinmux = <0x401f8028 3 0x0 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8028 3 0x0 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio06: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 { + pinmux = <0x401f802c 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexpwm2_pwma0: IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f802c 1 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio4_io06: IOMUXC_GPIO_EMC_06_GPIO4_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio9_io06: IOMUXC_GPIO_EMC_06_GPIO9_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_bclk: IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK { + pinmux = <0x401f802c 2 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN08 { + pinmux = <0x401f802c 3 0x0 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f802c 3 0x0 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio07: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 { + pinmux = <0x401f8030 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8030 1 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio4_io07: IOMUXC_GPIO_EMC_07_GPIO4_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio9_io07: IOMUXC_GPIO_EMC_07_GPIO9_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_mclk: IOMUXC_GPIO_EMC_07_SAI2_MCLK { + pinmux = <0x401f8030 2 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN09 { + pinmux = <0x401f8030 3 0x0 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8030 3 0x0 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio08: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8034 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexpwm2_pwma1: IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f8034 1 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio4_io08: IOMUXC_GPIO_EMC_08_GPIO4_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio9_io08: IOMUXC_GPIO_EMC_08_GPIO9_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 2 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN17 { + pinmux = <0x401f8034 3 0x0 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8034 3 0x0 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_tx: IOMUXC_GPIO_EMC_09_FLEXCAN2_TX { + pinmux = <0x401f8038 3 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio09: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8038 4 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8038 1 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexspi2_b_ss1_b: IOMUXC_GPIO_EMC_09_FLEXSPI2_B_SS1_B { + pinmux = <0x401f8038 8 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio4_io09: IOMUXC_GPIO_EMC_09_GPIO4_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio9_io09: IOMUXC_GPIO_EMC_09_GPIO9_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_sync: IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC { + pinmux = <0x401f8038 2 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_addr00: IOMUXC_GPIO_EMC_09_SEMC_ADDR00 { + pinmux = <0x401f8038 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexcan2_rx: IOMUXC_GPIO_EMC_10_FLEXCAN2_RX { + pinmux = <0x401f803c 3 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexio1_flexio10: IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 { + pinmux = <0x401f803c 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwma2: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f803c 1 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_10_FLEXSPI2_B_SS0_B { + pinmux = <0x401f803c 8 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio4_io10: IOMUXC_GPIO_EMC_10_GPIO4_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio9_io10: IOMUXC_GPIO_EMC_10_GPIO9_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai2_rx_bclk: IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK { + pinmux = <0x401f803c 2 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_addr01: IOMUXC_GPIO_EMC_10_SEMC_ADDR01 { + pinmux = <0x401f803c 0 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexio1_flexio11: IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 { + pinmux = <0x401f8040 4 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8040 1 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexspi2_b_dqs: IOMUXC_GPIO_EMC_11_FLEXSPI2_B_DQS { + pinmux = <0x401f8040 8 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio4_io11: IOMUXC_GPIO_EMC_11_GPIO4_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio9_io11: IOMUXC_GPIO_EMC_11_GPIO9_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_sda: IOMUXC_GPIO_EMC_11_LPI2C4_SDA { + pinmux = <0x401f8040 2 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_addr02: IOMUXC_GPIO_EMC_11_SEMC_ADDR02 { + pinmux = <0x401f8040 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_usdhc2_reset_b: IOMUXC_GPIO_EMC_11_USDHC2_RESET_B { + pinmux = <0x401f8040 3 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm1_pwma3: IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f8044 4 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexspi2_b_sclk: IOMUXC_GPIO_EMC_12_FLEXSPI2_B_SCLK { + pinmux = <0x401f8044 8 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio4_io12: IOMUXC_GPIO_EMC_12_GPIO4_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio9_io12: IOMUXC_GPIO_EMC_12_GPIO9_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpi2c4_scl: IOMUXC_GPIO_EMC_12_LPI2C4_SCL { + pinmux = <0x401f8044 2 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_addr03: IOMUXC_GPIO_EMC_12_SEMC_ADDR03 { + pinmux = <0x401f8044 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_usdhc1_wp: IOMUXC_GPIO_EMC_12_USDHC1_WP { + pinmux = <0x401f8044 3 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in24: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN24 { + pinmux = <0x401f8044 1 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8048 4 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexspi2_b_data0: IOMUXC_GPIO_EMC_13_FLEXSPI2_B_DATA0 { + pinmux = <0x401f8048 8 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio4_io13: IOMUXC_GPIO_EMC_13_GPIO4_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio9_io13: IOMUXC_GPIO_EMC_13_GPIO9_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart3_tx: IOMUXC_GPIO_EMC_13_LPUART3_TX { + pinmux = <0x401f8048 2 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_mqs_right: IOMUXC_GPIO_EMC_13_MQS_RIGHT { + pinmux = <0x401f8048 3 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_addr04: IOMUXC_GPIO_EMC_13_SEMC_ADDR04 { + pinmux = <0x401f8048 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in25: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN25 { + pinmux = <0x401f8048 1 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_flexspi2_b_data1: IOMUXC_GPIO_EMC_14_FLEXSPI2_B_DATA1 { + pinmux = <0x401f804c 8 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio4_io14: IOMUXC_GPIO_EMC_14_GPIO4_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio9_io14: IOMUXC_GPIO_EMC_14_GPIO9_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart3_rx: IOMUXC_GPIO_EMC_14_LPUART3_RX { + pinmux = <0x401f804c 2 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_mqs_left: IOMUXC_GPIO_EMC_14_MQS_LEFT { + pinmux = <0x401f804c 3 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_addr05: IOMUXC_GPIO_EMC_14_SEMC_ADDR05 { + pinmux = <0x401f804c 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN19 { + pinmux = <0x401f804c 1 0x0 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f804c 1 0x0 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_flexspi2_b_data2: IOMUXC_GPIO_EMC_15_FLEXSPI2_B_DATA2 { + pinmux = <0x401f8050 8 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio4_io15: IOMUXC_GPIO_EMC_15_GPIO4_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio9_io15: IOMUXC_GPIO_EMC_15_GPIO9_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart3_cts_b: IOMUXC_GPIO_EMC_15_LPUART3_CTS_B { + pinmux = <0x401f8050 2 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_qtimer3_timer0: IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 { + pinmux = <0x401f8050 4 0x0 0 0x401f8240>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr06: IOMUXC_GPIO_EMC_15_SEMC_ADDR06 { + pinmux = <0x401f8050 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_spdif_out: IOMUXC_GPIO_EMC_15_SPDIF_OUT { + pinmux = <0x401f8050 3 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in20: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN20 { + pinmux = <0x401f8050 1 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_flexspi2_b_data3: IOMUXC_GPIO_EMC_16_FLEXSPI2_B_DATA3 { + pinmux = <0x401f8054 8 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio4_io16: IOMUXC_GPIO_EMC_16_GPIO4_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio9_io16: IOMUXC_GPIO_EMC_16_GPIO9_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_lpuart3_rts_b: IOMUXC_GPIO_EMC_16_LPUART3_RTS_B { + pinmux = <0x401f8054 2 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_qtimer3_timer1: IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 { + pinmux = <0x401f8054 4 0x0 0 0x401f8244>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr07: IOMUXC_GPIO_EMC_16_SEMC_ADDR07 { + pinmux = <0x401f8054 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_spdif_in: IOMUXC_GPIO_EMC_16_SPDIF_IN { + pinmux = <0x401f8054 3 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_xbar1_xbar_in21: IOMUXC_GPIO_EMC_16_XBAR1_XBAR_IN21 { + pinmux = <0x401f8054 1 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexcan1_tx: IOMUXC_GPIO_EMC_17_FLEXCAN1_TX { + pinmux = <0x401f8058 3 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexpwm4_pwma3: IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA3 { + pinmux = <0x401f8058 1 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio4_io17: IOMUXC_GPIO_EMC_17_GPIO4_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio9_io17: IOMUXC_GPIO_EMC_17_GPIO9_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_lpuart4_cts_b: IOMUXC_GPIO_EMC_17_LPUART4_CTS_B { + pinmux = <0x401f8058 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_qtimer3_timer2: IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 { + pinmux = <0x401f8058 4 0x0 0 0x401f8248>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr08: IOMUXC_GPIO_EMC_17_SEMC_ADDR08 { + pinmux = <0x401f8058 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexcan1_rx: IOMUXC_GPIO_EMC_18_FLEXCAN1_RX { + pinmux = <0x401f805c 3 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexpwm4_pwmb3: IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB3 { + pinmux = <0x401f805c 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio4_io18: IOMUXC_GPIO_EMC_18_GPIO4_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio9_io18: IOMUXC_GPIO_EMC_18_GPIO9_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpuart4_rts_b: IOMUXC_GPIO_EMC_18_LPUART4_RTS_B { + pinmux = <0x401f805c 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_qtimer3_timer3: IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 { + pinmux = <0x401f805c 4 0x0 0 0x401f824c>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr09: IOMUXC_GPIO_EMC_18_SEMC_ADDR09 { + pinmux = <0x401f805c 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_snvs_vio_5_ctl: IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL { + pinmux = <0x401f805c 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_enet_rx_data1: IOMUXC_GPIO_EMC_19_ENET_RX_DATA1 { + pinmux = <0x401f8060 3 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexpwm2_pwma3: IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA3 { + pinmux = <0x401f8060 1 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio4_io19: IOMUXC_GPIO_EMC_19_GPIO4_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio9_io19: IOMUXC_GPIO_EMC_19_GPIO9_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpuart4_tx: IOMUXC_GPIO_EMC_19_LPUART4_TX { + pinmux = <0x401f8060 2 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_qtimer2_timer0: IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 { + pinmux = <0x401f8060 4 0x0 0 0x401f8250>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr11: IOMUXC_GPIO_EMC_19_SEMC_ADDR11 { + pinmux = <0x401f8060 0 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_snvs_vio_5_b: IOMUXC_GPIO_EMC_19_SNVS_VIO_5_B { + pinmux = <0x401f8060 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_enet_rx_data0: IOMUXC_GPIO_EMC_20_ENET_RX_DATA0 { + pinmux = <0x401f8064 3 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB3 { + pinmux = <0x401f8064 1 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio4_io20: IOMUXC_GPIO_EMC_20_GPIO4_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio9_io20: IOMUXC_GPIO_EMC_20_GPIO9_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart4_rx: IOMUXC_GPIO_EMC_20_LPUART4_RX { + pinmux = <0x401f8064 2 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_qtimer2_timer1: IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 { + pinmux = <0x401f8064 4 0x0 0 0x401f8254>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr12: IOMUXC_GPIO_EMC_20_SEMC_ADDR12 { + pinmux = <0x401f8064 0 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_enet_tx_data1: IOMUXC_GPIO_EMC_21_ENET_TX_DATA1 { + pinmux = <0x401f8068 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm3_pwma3: IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA3 { + pinmux = <0x401f8068 1 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio4_io21: IOMUXC_GPIO_EMC_21_GPIO4_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio9_io21: IOMUXC_GPIO_EMC_21_GPIO9_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpi2c3_sda: IOMUXC_GPIO_EMC_21_LPI2C3_SDA { + pinmux = <0x401f8068 2 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_qtimer2_timer2: IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 { + pinmux = <0x401f8068 4 0x0 0 0x401f8258>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_ba0: IOMUXC_GPIO_EMC_21_SEMC_BA0 { + pinmux = <0x401f8068 0 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_enet_tx_data0: IOMUXC_GPIO_EMC_22_ENET_TX_DATA0 { + pinmux = <0x401f806c 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm3_pwmb3: IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB3 { + pinmux = <0x401f806c 1 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexspi2_a_ss1_b: IOMUXC_GPIO_EMC_22_FLEXSPI2_A_SS1_B { + pinmux = <0x401f806c 8 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio4_io22: IOMUXC_GPIO_EMC_22_GPIO4_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio9_io22: IOMUXC_GPIO_EMC_22_GPIO9_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpi2c3_scl: IOMUXC_GPIO_EMC_22_LPI2C3_SCL { + pinmux = <0x401f806c 2 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_qtimer2_timer3: IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 { + pinmux = <0x401f806c 4 0x0 0 0x401f825c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_ba1: IOMUXC_GPIO_EMC_22_SEMC_BA1 { + pinmux = <0x401f806c 0 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_enet_rx_en: IOMUXC_GPIO_EMC_23_ENET_RX_EN { + pinmux = <0x401f8070 3 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwma0: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA0 { + pinmux = <0x401f8070 1 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexspi2_a_dqs: IOMUXC_GPIO_EMC_23_FLEXSPI2_A_DQS { + pinmux = <0x401f8070 8 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio4_io23: IOMUXC_GPIO_EMC_23_GPIO4_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio9_io23: IOMUXC_GPIO_EMC_23_GPIO9_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpt1_capture2: IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 { + pinmux = <0x401f8070 4 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart5_tx: IOMUXC_GPIO_EMC_23_LPUART5_TX { + pinmux = <0x401f8070 2 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr10: IOMUXC_GPIO_EMC_23_SEMC_ADDR10 { + pinmux = <0x401f8070 0 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_enet_tx_en: IOMUXC_GPIO_EMC_24_ENET_TX_EN { + pinmux = <0x401f8074 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB0 { + pinmux = <0x401f8074 1 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_24_FLEXSPI2_A_SS0_B { + pinmux = <0x401f8074 8 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio4_io24: IOMUXC_GPIO_EMC_24_GPIO4_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio9_io24: IOMUXC_GPIO_EMC_24_GPIO9_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpt1_capture1: IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 { + pinmux = <0x401f8074 4 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart5_rx: IOMUXC_GPIO_EMC_24_LPUART5_RX { + pinmux = <0x401f8074 2 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_cas: IOMUXC_GPIO_EMC_24_SEMC_CAS { + pinmux = <0x401f8074 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_ref_clk: IOMUXC_GPIO_EMC_25_ENET_REF_CLK { + pinmux = <0x401f8078 4 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_tx_clk: IOMUXC_GPIO_EMC_25_ENET_TX_CLK { + pinmux = <0x401f8078 3 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwma1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA1 { + pinmux = <0x401f8078 1 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexspi2_a_sclk: IOMUXC_GPIO_EMC_25_FLEXSPI2_A_SCLK { + pinmux = <0x401f8078 8 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio4_io25: IOMUXC_GPIO_EMC_25_GPIO4_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio9_io25: IOMUXC_GPIO_EMC_25_GPIO9_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart6_tx: IOMUXC_GPIO_EMC_25_LPUART6_TX { + pinmux = <0x401f8078 2 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_ras: IOMUXC_GPIO_EMC_25_SEMC_RAS { + pinmux = <0x401f8078 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_enet_rx_er: IOMUXC_GPIO_EMC_26_ENET_RX_ER { + pinmux = <0x401f807c 3 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio12: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 { + pinmux = <0x401f807c 4 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB1 { + pinmux = <0x401f807c 1 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexspi2_a_data0: IOMUXC_GPIO_EMC_26_FLEXSPI2_A_DATA0 { + pinmux = <0x401f807c 8 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio4_io26: IOMUXC_GPIO_EMC_26_GPIO4_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio9_io26: IOMUXC_GPIO_EMC_26_GPIO9_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart6_rx: IOMUXC_GPIO_EMC_26_LPUART6_RX { + pinmux = <0x401f807c 2 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_clk: IOMUXC_GPIO_EMC_26_SEMC_CLK { + pinmux = <0x401f807c 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio13: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8080 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwma2: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA2 { + pinmux = <0x401f8080 1 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexspi2_a_data1: IOMUXC_GPIO_EMC_27_FLEXSPI2_A_DATA1 { + pinmux = <0x401f8080 8 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio4_io27: IOMUXC_GPIO_EMC_27_GPIO4_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio9_io27: IOMUXC_GPIO_EMC_27_GPIO9_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpspi1_sck: IOMUXC_GPIO_EMC_27_LPSPI1_SCK { + pinmux = <0x401f8080 3 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart5_rts_b: IOMUXC_GPIO_EMC_27_LPUART5_RTS_B { + pinmux = <0x401f8080 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_cke: IOMUXC_GPIO_EMC_27_SEMC_CKE { + pinmux = <0x401f8080 0 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexio1_flexio14: IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8084 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB2 { + pinmux = <0x401f8084 1 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexspi2_a_data2: IOMUXC_GPIO_EMC_28_FLEXSPI2_A_DATA2 { + pinmux = <0x401f8084 8 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio4_io28: IOMUXC_GPIO_EMC_28_GPIO4_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio9_io28: IOMUXC_GPIO_EMC_28_GPIO9_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpspi1_sdo: IOMUXC_GPIO_EMC_28_LPSPI1_SDO { + pinmux = <0x401f8084 3 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpuart5_cts_b: IOMUXC_GPIO_EMC_28_LPUART5_CTS_B { + pinmux = <0x401f8084 2 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_we: IOMUXC_GPIO_EMC_28_SEMC_WE { + pinmux = <0x401f8084 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexio1_flexio15: IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 { + pinmux = <0x401f8088 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm3_pwma0: IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA0 { + pinmux = <0x401f8088 1 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexspi2_a_data3: IOMUXC_GPIO_EMC_29_FLEXSPI2_A_DATA3 { + pinmux = <0x401f8088 8 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio4_io29: IOMUXC_GPIO_EMC_29_GPIO4_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio9_io29: IOMUXC_GPIO_EMC_29_GPIO9_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpspi1_sdi: IOMUXC_GPIO_EMC_29_LPSPI1_SDI { + pinmux = <0x401f8088 3 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpuart6_rts_b: IOMUXC_GPIO_EMC_29_LPUART6_RTS_B { + pinmux = <0x401f8088 2 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cs0: IOMUXC_GPIO_EMC_29_SEMC_CS0 { + pinmux = <0x401f8088 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm3_pwmb0: IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB0 { + pinmux = <0x401f808c 1 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio4_io30: IOMUXC_GPIO_EMC_30_GPIO4_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio9_io30: IOMUXC_GPIO_EMC_30_GPIO9_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpspi1_pcs0: IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 { + pinmux = <0x401f808c 3 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart6_cts_b: IOMUXC_GPIO_EMC_30_LPUART6_CTS_B { + pinmux = <0x401f808c 2 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_data08: IOMUXC_GPIO_EMC_30_SEMC_DATA08 { + pinmux = <0x401f808c 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm3_pwma1: IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA1 { + pinmux = <0x401f8090 1 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio4_io31: IOMUXC_GPIO_EMC_31_GPIO4_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio9_io31: IOMUXC_GPIO_EMC_31_GPIO9_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpspi1_pcs1: IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 { + pinmux = <0x401f8090 3 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart7_tx: IOMUXC_GPIO_EMC_31_LPUART7_TX { + pinmux = <0x401f8090 2 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_data09: IOMUXC_GPIO_EMC_31_SEMC_DATA09 { + pinmux = <0x401f8090 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ccm_pmic_rdy: IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY { + pinmux = <0x401f8094 3 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_flexpwm3_pwmb1: IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB1 { + pinmux = <0x401f8094 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io18: IOMUXC_GPIO_EMC_32_GPIO3_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio8_io18: IOMUXC_GPIO_EMC_32_GPIO8_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart7_rx: IOMUXC_GPIO_EMC_32_LPUART7_RX { + pinmux = <0x401f8094 2 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data10: IOMUXC_GPIO_EMC_32_SEMC_DATA10 { + pinmux = <0x401f8094 0 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_flexpwm3_pwma2: IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA2 { + pinmux = <0x401f8098 1 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io19: IOMUXC_GPIO_EMC_33_GPIO3_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio8_io19: IOMUXC_GPIO_EMC_33_GPIO8_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_rx_data: IOMUXC_GPIO_EMC_33_SAI3_RX_DATA { + pinmux = <0x401f8098 3 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data11: IOMUXC_GPIO_EMC_33_SEMC_DATA11 { + pinmux = <0x401f8098 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_usdhc1_reset_b: IOMUXC_GPIO_EMC_33_USDHC1_RESET_B { + pinmux = <0x401f8098 2 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_flexpwm3_pwmb2: IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB2 { + pinmux = <0x401f809c 1 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io20: IOMUXC_GPIO_EMC_34_GPIO3_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio8_io20: IOMUXC_GPIO_EMC_34_GPIO8_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_rx_sync: IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC { + pinmux = <0x401f809c 3 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data12: IOMUXC_GPIO_EMC_34_SEMC_DATA12 { + pinmux = <0x401f809c 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_usdhc1_vselect: IOMUXC_GPIO_EMC_34_USDHC1_VSELECT { + pinmux = <0x401f809c 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io21: IOMUXC_GPIO_EMC_35_GPIO3_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio8_io21: IOMUXC_GPIO_EMC_35_GPIO8_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpt1_compare1: IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 { + pinmux = <0x401f80a0 2 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_sai3_rx_bclk: IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK { + pinmux = <0x401f80a0 3 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data13: IOMUXC_GPIO_EMC_35_SEMC_DATA13 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc1_cd_b: IOMUXC_GPIO_EMC_35_USDHC1_CD_B { + pinmux = <0x401f80a0 6 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_in18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_IN18 { + pinmux = <0x401f80a0 1 0x0 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80a0 1 0x0 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexcan3_tx: IOMUXC_GPIO_EMC_36_FLEXCAN3_TX { + pinmux = <0x401f80a4 9 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io22: IOMUXC_GPIO_EMC_36_GPIO3_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio8_io22: IOMUXC_GPIO_EMC_36_GPIO8_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpt1_compare2: IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 { + pinmux = <0x401f80a4 2 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_sai3_tx_data: IOMUXC_GPIO_EMC_36_SAI3_TX_DATA { + pinmux = <0x401f80a4 3 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data14: IOMUXC_GPIO_EMC_36_SEMC_DATA14 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 6 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_xbar1_xbar_in22: IOMUXC_GPIO_EMC_36_XBAR1_XBAR_IN22 { + pinmux = <0x401f80a4 1 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexcan3_rx: IOMUXC_GPIO_EMC_37_FLEXCAN3_RX { + pinmux = <0x401f80a8 9 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io23: IOMUXC_GPIO_EMC_37_GPIO3_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio8_io23: IOMUXC_GPIO_EMC_37_GPIO8_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpt1_compare3: IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 { + pinmux = <0x401f80a8 2 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_sai3_mclk: IOMUXC_GPIO_EMC_37_SAI3_MCLK { + pinmux = <0x401f80a8 3 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data15: IOMUXC_GPIO_EMC_37_SEMC_DATA15 { + pinmux = <0x401f80a8 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc2_wp: IOMUXC_GPIO_EMC_37_USDHC2_WP { + pinmux = <0x401f80a8 6 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_xbar1_xbar_in23: IOMUXC_GPIO_EMC_37_XBAR1_XBAR_IN23 { + pinmux = <0x401f80a8 1 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm1_pwma3: IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA3 { + pinmux = <0x401f80ac 1 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io24: IOMUXC_GPIO_EMC_38_GPIO3_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio8_io24: IOMUXC_GPIO_EMC_38_GPIO8_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart8_tx: IOMUXC_GPIO_EMC_38_LPUART8_TX { + pinmux = <0x401f80ac 2 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_sai3_tx_bclk: IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK { + pinmux = <0x401f80ac 3 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_dm1: IOMUXC_GPIO_EMC_38_SEMC_DM1 { + pinmux = <0x401f80ac 0 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc2_vselect: IOMUXC_GPIO_EMC_38_USDHC2_VSELECT { + pinmux = <0x401f80ac 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB3 { + pinmux = <0x401f80b0 1 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io25: IOMUXC_GPIO_EMC_39_GPIO3_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio8_io25: IOMUXC_GPIO_EMC_39_GPIO8_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart8_rx: IOMUXC_GPIO_EMC_39_LPUART8_RX { + pinmux = <0x401f80b0 2 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_sai3_tx_sync: IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC { + pinmux = <0x401f80b0 3 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs: IOMUXC_GPIO_EMC_39_SEMC_DQS { + pinmux = <0x401f80b0 0 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs4: IOMUXC_GPIO_EMC_39_SEMC_DQS4 { + pinmux = <0x401f80b0 9 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usdhc2_cd_b: IOMUXC_GPIO_EMC_39_USDHC2_CD_B { + pinmux = <0x401f80b0 6 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdc: IOMUXC_GPIO_EMC_40_ENET_MDC { + pinmux = <0x401f80b4 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io26: IOMUXC_GPIO_EMC_40_GPIO3_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio8_io26: IOMUXC_GPIO_EMC_40_GPIO8_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt2_capture2: IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 { + pinmux = <0x401f80b4 1 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_lpspi1_pcs2: IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 { + pinmux = <0x401f80b4 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_clk5: IOMUXC_GPIO_EMC_40_SEMC_CLK5 { + pinmux = <0x401f80b4 9 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_rdy: IOMUXC_GPIO_EMC_40_SEMC_RDY { + pinmux = <0x401f80b4 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usdhc2_reset_b: IOMUXC_GPIO_EMC_40_USDHC2_RESET_B { + pinmux = <0x401f80b4 6 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdio: IOMUXC_GPIO_EMC_41_ENET_MDIO { + pinmux = <0x401f80b8 4 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io27: IOMUXC_GPIO_EMC_41_GPIO3_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio8_io27: IOMUXC_GPIO_EMC_41_GPIO8_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt2_capture1: IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 { + pinmux = <0x401f80b8 1 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_lpspi1_pcs3: IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 { + pinmux = <0x401f80b8 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_csx0: IOMUXC_GPIO_EMC_41_SEMC_CSX0 { + pinmux = <0x401f80b8 0 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usdhc1_vselect: IOMUXC_GPIO_EMC_41_USDHC1_VSELECT { + pinmux = <0x401f80b8 6 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexpwm1_pwma0: IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA0 { + pinmux = <0x401f81bc 1 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f81bc 6 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io12: IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio8_io12: IOMUXC_GPIO_SD_B0_00_GPIO8_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f81bc 2 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpspi1_sck: IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK { + pinmux = <0x401f81bc 4 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_semc_dqs4: IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 { + pinmux = <0x401f81bc 9 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_cmd: IOMUXC_GPIO_SD_B0_00_USDHC1_CMD { + pinmux = <0x401f81bc 0 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN04 { + pinmux = <0x401f81bc 3 0x0 0 0x401f83ac>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f81bc 3 0x0 0 0x401f83ac>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexpwm1_pwmb0: IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB0 { + pinmux = <0x401f81c0 1 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f81c0 6 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io13: IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio8_io13: IOMUXC_GPIO_SD_B0_01_GPIO8_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f81c0 2 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 { + pinmux = <0x401f81c0 4 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_clk: IOMUXC_GPIO_SD_B0_01_USDHC1_CLK { + pinmux = <0x401f81c0 0 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN05 { + pinmux = <0x401f81c0 3 0x0 0 0x401f83b0>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f81c0 3 0x0 0 0x401f83b0>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_flexpwm1_pwma1: IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA1 { + pinmux = <0x401f81c4 1 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io14: IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio8_io14: IOMUXC_GPIO_SD_B0_02_GPIO8_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sdo: IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO { + pinmux = <0x401f81c4 4 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart8_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B { + pinmux = <0x401f81c4 2 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_semc_clk5: IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 { + pinmux = <0x401f81c4 9 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_data0: IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 { + pinmux = <0x401f81c4 0 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN06 { + pinmux = <0x401f81c4 3 0x0 0 0x401f83b4>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f81c4 3 0x0 0 0x401f83b4>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_flexpwm1_pwmb1: IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB1 { + pinmux = <0x401f81c8 1 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io15: IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio8_io15: IOMUXC_GPIO_SD_B0_03_GPIO8_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_sdi: IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI { + pinmux = <0x401f81c8 4 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart8_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B { + pinmux = <0x401f81c8 2 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_semc_clk6: IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 { + pinmux = <0x401f81c8 9 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_data1: IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 { + pinmux = <0x401f81c8 0 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_in07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_IN07 { + pinmux = <0x401f81c8 3 0x0 0 0x401f83b8>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_inout07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f81c8 3 0x0 0 0x401f83b8>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_ccm_clko1: IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 { + pinmux = <0x401f81cc 6 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexpwm1_pwma2: IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA2 { + pinmux = <0x401f81cc 1 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f81cc 4 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io16: IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio8_io16: IOMUXC_GPIO_SD_B0_04_GPIO8_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart8_tx: IOMUXC_GPIO_SD_B0_04_LPUART8_TX { + pinmux = <0x401f81cc 2 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data2: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 { + pinmux = <0x401f81cc 0 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_in08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_IN08 { + pinmux = <0x401f81cc 3 0x0 0 0x401f83bc>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_inout08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f81cc 3 0x0 0 0x401f83bc>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_ccm_clko2: IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 { + pinmux = <0x401f81d0 6 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexpwm1_pwmb2: IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB2 { + pinmux = <0x401f81d0 1 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f81d0 4 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io17: IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio8_io17: IOMUXC_GPIO_SD_B0_05_GPIO8_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart8_rx: IOMUXC_GPIO_SD_B0_05_LPUART8_RX { + pinmux = <0x401f81d0 2 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data3: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 { + pinmux = <0x401f81d0 0 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_in09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_IN09 { + pinmux = <0x401f81d0 3 0x0 0 0x401f83c0>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_inout09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f81d0 3 0x0 0 0x401f83c0>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f81d4 2 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f81d4 1 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io00: IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio8_io00: IOMUXC_GPIO_SD_B1_00_GPIO8_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart4_tx: IOMUXC_GPIO_SD_B1_00_LPUART4_TX { + pinmux = <0x401f81d4 4 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai1_tx_data3: IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA3 { + pinmux = <0x401f81d4 3 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai3_rx_data: IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA { + pinmux = <0x401f81d4 8 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data3: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 { + pinmux = <0x401f81d4 0 0x0 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f81d8 2 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_data2: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 { + pinmux = <0x401f81d8 1 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io01: IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio8_io01: IOMUXC_GPIO_SD_B1_01_GPIO8_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart4_rx: IOMUXC_GPIO_SD_B1_01_LPUART4_RX { + pinmux = <0x401f81d8 4 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai1_tx_data2: IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA2 { + pinmux = <0x401f81d8 3 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai3_tx_data: IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA { + pinmux = <0x401f81d8 8 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data2: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 { + pinmux = <0x401f81d8 0 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_wait: IOMUXC_GPIO_SD_B1_02_CCM_WAIT { + pinmux = <0x401f81dc 6 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexcan1_tx: IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX { + pinmux = <0x401f81dc 4 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f81dc 2 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data1: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 { + pinmux = <0x401f81dc 1 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io02: IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio8_io02: IOMUXC_GPIO_SD_B1_02_GPIO8_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai1_tx_data1: IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA1 { + pinmux = <0x401f81dc 3 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai3_tx_sync: IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC { + pinmux = <0x401f81dc 8 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_data1: IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 { + pinmux = <0x401f81dc 0 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_03_CCM_PMIC_RDY { + pinmux = <0x401f81e0 6 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexcan1_rx: IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX { + pinmux = <0x401f81e0 4 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f81e0 2 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data0: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 { + pinmux = <0x401f81e0 1 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io03: IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio8_io03: IOMUXC_GPIO_SD_B1_03_GPIO8_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai1_mclk: IOMUXC_GPIO_SD_B1_03_SAI1_MCLK { + pinmux = <0x401f81e0 3 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK { + pinmux = <0x401f81e0 8 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_data0: IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 { + pinmux = <0x401f81e0 0 0x0 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_stop: IOMUXC_GPIO_SD_B1_04_CCM_STOP { + pinmux = <0x401f81e4 6 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI_A_SS1_B { + pinmux = <0x401f81e4 4 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK { + pinmux = <0x401f81e4 1 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io04: IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio8_io04: IOMUXC_GPIO_SD_B1_04_GPIO8_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_lpi2c1_scl: IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL { + pinmux = <0x401f81e4 2 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai1_rx_sync: IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f81e4 3 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai3_mclk: IOMUXC_GPIO_SD_B1_04_SAI3_MCLK { + pinmux = <0x401f81e4 8 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_clk: IOMUXC_GPIO_SD_B1_04_USDHC2_CLK { + pinmux = <0x401f81e4 0 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f81e8 1 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f81e8 4 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io05: IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio8_io05: IOMUXC_GPIO_SD_B1_05_GPIO8_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_lpi2c1_sda: IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA { + pinmux = <0x401f81e8 2 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai1_rx_bclk: IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK { + pinmux = <0x401f81e8 3 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_rx_sync: IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC { + pinmux = <0x401f81e8 8 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_cmd: IOMUXC_GPIO_SD_B1_05_USDHC2_CMD { + pinmux = <0x401f81e8 0 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B { + pinmux = <0x401f81ec 1 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io06: IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio8_io06: IOMUXC_GPIO_SD_B1_06_GPIO8_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f81ec 4 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpuart7_cts_b: IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B { + pinmux = <0x401f81ec 2 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai1_rx_data0: IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA0 { + pinmux = <0x401f81ec 3 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK { + pinmux = <0x401f81ec 8 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B { + pinmux = <0x401f81ec 0 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f81f0 1 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io07: IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio8_io07: IOMUXC_GPIO_SD_B1_07_GPIO8_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f81f0 4 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpuart7_rts_b: IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B { + pinmux = <0x401f81f0 2 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai1_tx_data0: IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA0 { + pinmux = <0x401f81f0 3 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_semc_csx1: IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 { + pinmux = <0x401f81f0 0 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f81f4 1 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io08: IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio8_io08: IOMUXC_GPIO_SD_B1_08_GPIO8_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f81f4 4 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpuart7_tx: IOMUXC_GPIO_SD_B1_08_LPUART7_TX { + pinmux = <0x401f81f4 2 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai1_tx_bclk: IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK { + pinmux = <0x401f81f4 3 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_semc_csx2: IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 { + pinmux = <0x401f81f4 6 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f81f4 0 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data1: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 { + pinmux = <0x401f81f8 1 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io09: IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio8_io09: IOMUXC_GPIO_SD_B1_09_GPIO8_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f81f8 4 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpuart7_rx: IOMUXC_GPIO_SD_B1_09_LPUART7_RX { + pinmux = <0x401f81f8 2 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai1_tx_sync: IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC { + pinmux = <0x401f81f8 3 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f81f8 0 0x0 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data2: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 { + pinmux = <0x401f81fc 1 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io10: IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio8_io10: IOMUXC_GPIO_SD_B1_10_GPIO8_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpi2c2_sda: IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA { + pinmux = <0x401f81fc 3 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f81fc 4 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpuart2_rx: IOMUXC_GPIO_SD_B1_10_LPUART2_RX { + pinmux = <0x401f81fc 2 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f81fc 0 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_data3: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 { + pinmux = <0x401f8200 1 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io11: IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio8_io11: IOMUXC_GPIO_SD_B1_11_GPIO8_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpi2c2_scl: IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL { + pinmux = <0x401f8200 3 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8200 4 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpuart2_tx: IOMUXC_GPIO_SD_B1_11_LPUART2_TX { + pinmux = <0x401f8200 2 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8200 0 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x0 0 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1064cvj5b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1064cvj5b-pinctrl.dtsi new file mode 100644 index 000000000..27227c814 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1064cvj5b-pinctrl.dtsi @@ -0,0 +1,3925 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1064CVJ5B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_acmp1_in4: IOMUXC_GPIO_AD_B0_00_ACMP1_IN4 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA3 { + pinmux = <0x401f80bc 0 0x401f8474 2 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + gpr = <0x400ac068 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio6_io00: IOMUXC_GPIO_AD_B0_00_GPIO6_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + gpr = <0x400ac068 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_lpi2c1_scls: IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS { + pinmux = <0x401f80bc 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_lpspi3_sck: IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK { + pinmux = <0x401f80bc 7 0x401f8510 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_ref_32k_out: IOMUXC_GPIO_AD_B0_00_REF_32K_OUT { + pinmux = <0x401f80bc 2 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_usb_otg2_id: IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID { + pinmux = <0x401f80bc 3 0x401f83f8 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_usdhc1_reset_b: IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B { + pinmux = <0x401f80bc 6 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_xbar1_xbar_in14: IOMUXC_GPIO_AD_B0_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f80bc 1 0x401f8644 0 0x401f82ac>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_xbar1_xbar_inout14: IOMUXC_GPIO_AD_B0_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f80bc 1 0x401f8644 0 0x401f82ac>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_acmp2_in4: IOMUXC_GPIO_AD_B0_01_ACMP2_IN4 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_ewm_out_b: IOMUXC_GPIO_AD_B0_01_EWM_OUT_B { + pinmux = <0x401f80c0 6 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_flexpwm2_pwmb3: IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB3 { + pinmux = <0x401f80c0 0 0x401f8484 2 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + gpr = <0x400ac068 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio6_io01: IOMUXC_GPIO_AD_B0_01_GPIO6_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + gpr = <0x400ac068 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_lpi2c1_sdas: IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS { + pinmux = <0x401f80c0 4 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_lpspi3_sdo: IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO { + pinmux = <0x401f80c0 7 0x401f8518 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_ref_24m_out: IOMUXC_GPIO_AD_B0_01_REF_24M_OUT { + pinmux = <0x401f80c0 2 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_usb_otg1_id: IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID { + pinmux = <0x401f80c0 3 0x401f83f4 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_xbar1_xbar_in15: IOMUXC_GPIO_AD_B0_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f80c0 1 0x401f8648 0 0x401f82b0>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_xbar1_xbar_inout15: IOMUXC_GPIO_AD_B0_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f80c0 1 0x401f8648 0 0x401f82b0>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_acmp3_in4: IOMUXC_GPIO_AD_B0_02_ACMP3_IN4 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_flexcan2_tx: IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX { + pinmux = <0x401f80c4 0 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_flexpwm1_pwmx0: IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX0 { + pinmux = <0x401f80c4 4 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + gpr = <0x400ac068 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio6_io02: IOMUXC_GPIO_AD_B0_02_GPIO6_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + gpr = <0x400ac068 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpi2c1_hreq: IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ { + pinmux = <0x401f80c4 6 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpspi3_sdi: IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI { + pinmux = <0x401f80c4 7 0x401f8514 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpuart6_tx: IOMUXC_GPIO_AD_B0_02_LPUART6_TX { + pinmux = <0x401f80c4 2 0x401f8554 1 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR { + pinmux = <0x401f80c4 3 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_xbar1_xbar_in16: IOMUXC_GPIO_AD_B0_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f80c4 1 0x401f864c 0 0x401f82b4>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_xbar1_xbar_inout16: IOMUXC_GPIO_AD_B0_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f80c4 1 0x401f864c 0 0x401f82b4>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_acmp4_in4: IOMUXC_GPIO_AD_B0_03_ACMP4_IN4 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_flexcan2_rx: IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX { + pinmux = <0x401f80c8 0 0x401f8450 1 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_flexpwm1_pwmx1: IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX1 { + pinmux = <0x401f80c8 4 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + gpr = <0x400ac068 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio6_io03: IOMUXC_GPIO_AD_B0_03_GPIO6_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + gpr = <0x400ac068 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_lpspi3_pcs0: IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 { + pinmux = <0x401f80c8 7 0x401f850c 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_lpuart6_rx: IOMUXC_GPIO_AD_B0_03_LPUART6_RX { + pinmux = <0x401f80c8 2 0x401f8550 1 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ref_24m_out: IOMUXC_GPIO_AD_B0_03_REF_24M_OUT { + pinmux = <0x401f80c8 6 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 3 0x401f85d0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f80c8 1 0x401f862c 1 0x401f82b8>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80c8 1 0x401f862c 1 0x401f82b8>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_csi_data09: IOMUXC_GPIO_AD_B0_04_CSI_DATA09 { + pinmux = <0x401f80cc 4 0x401f841c 1 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_tx_data3: IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA3 { + pinmux = <0x401f80cc 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio6_io04: IOMUXC_GPIO_AD_B0_04_GPIO6_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_lpspi3_pcs1: IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 { + pinmux = <0x401f80cc 7 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_mqs_right: IOMUXC_GPIO_AD_B0_04_MQS_RIGHT { + pinmux = <0x401f80cc 1 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_pit_trigger0: IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER0 { + pinmux = <0x401f80cc 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_sai2_tx_sync: IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC { + pinmux = <0x401f80cc 3 0x401f85c4 1 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_src_boot_mode0: IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE0 { + pinmux = <0x401f80cc 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_csi_data08: IOMUXC_GPIO_AD_B0_05_CSI_DATA08 { + pinmux = <0x401f80d0 4 0x401f8418 1 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_tx_data2: IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA2 { + pinmux = <0x401f80d0 2 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio6_io05: IOMUXC_GPIO_AD_B0_05_GPIO6_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_lpspi3_pcs2: IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 { + pinmux = <0x401f80d0 7 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_mqs_left: IOMUXC_GPIO_AD_B0_05_MQS_LEFT { + pinmux = <0x401f80d0 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_sai2_tx_bclk: IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f80d0 3 0x401f85c0 1 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_src_boot_mode1: IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE1 { + pinmux = <0x401f80d0 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_IN17 { + pinmux = <0x401f80d0 6 0x401f862c 2 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80d0 6 0x401f862c 2 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_csi_data07: IOMUXC_GPIO_AD_B0_06_CSI_DATA07 { + pinmux = <0x401f80d4 4 0x401f8414 1 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_enet_rx_clk: IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK { + pinmux = <0x401f80d4 2 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio6_io06: IOMUXC_GPIO_AD_B0_06_GPIO6_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpt2_compare1: IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 { + pinmux = <0x401f80d4 1 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_jtag_tms: IOMUXC_GPIO_AD_B0_06_JTAG_TMS { + pinmux = <0x401f80d4 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpspi3_pcs3: IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 { + pinmux = <0x401f80d4 7 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_sai2_rx_bclk: IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK { + pinmux = <0x401f80d4 3 0x401f85b4 1 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_in18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_IN18 { + pinmux = <0x401f80d4 6 0x401f8630 1 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_inout18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80d4 6 0x401f8630 1 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_csi_data06: IOMUXC_GPIO_AD_B0_07_CSI_DATA06 { + pinmux = <0x401f80d8 4 0x401f8410 1 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_1588_event3_out: IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT { + pinmux = <0x401f80d8 7 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_tx_er: IOMUXC_GPIO_AD_B0_07_ENET_TX_ER { + pinmux = <0x401f80d8 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio6_io07: IOMUXC_GPIO_AD_B0_07_GPIO6_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpt2_compare2: IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 { + pinmux = <0x401f80d8 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_jtag_tck: IOMUXC_GPIO_AD_B0_07_JTAG_TCK { + pinmux = <0x401f80d8 0 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_sai2_rx_sync: IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC { + pinmux = <0x401f80d8 3 0x401f85bc 1 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_in19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_IN19 { + pinmux = <0x401f80d8 6 0x401f8654 1 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_inout19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80d8 6 0x401f8654 1 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_csi_data05: IOMUXC_GPIO_AD_B0_08_CSI_DATA05 { + pinmux = <0x401f80dc 4 0x401f840c 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_1588_event3_in: IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN { + pinmux = <0x401f80dc 7 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_rx_data3: IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA3 { + pinmux = <0x401f80dc 2 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio6_io08: IOMUXC_GPIO_AD_B0_08_GPIO6_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpt2_compare3: IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 { + pinmux = <0x401f80dc 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_jtag_mod: IOMUXC_GPIO_AD_B0_08_JTAG_MOD { + pinmux = <0x401f80dc 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_sai2_rx_data: IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA { + pinmux = <0x401f80dc 3 0x401f85b8 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_xbar1_xbar_in20: IOMUXC_GPIO_AD_B0_08_XBAR1_XBAR_IN20 { + pinmux = <0x401f80dc 6 0x401f8634 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_csi_data04: IOMUXC_GPIO_AD_B0_09_CSI_DATA04 { + pinmux = <0x401f80e0 4 0x401f8408 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data2: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA2 { + pinmux = <0x401f80e0 2 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA3 { + pinmux = <0x401f80e0 1 0x401f8474 3 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio6_io09: IOMUXC_GPIO_AD_B0_09_GPIO6_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpt2_clk: IOMUXC_GPIO_AD_B0_09_GPT2_CLK { + pinmux = <0x401f80e0 7 0x401f876c 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_jtag_tdi: IOMUXC_GPIO_AD_B0_09_JTAG_TDI { + pinmux = <0x401f80e0 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_sai2_tx_data: IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA { + pinmux = <0x401f80e0 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_semc_dqs4: IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 { + pinmux = <0x401f80e0 9 0x401f8788 2 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_xbar1_xbar_in21: IOMUXC_GPIO_AD_B0_09_XBAR1_XBAR_IN21 { + pinmux = <0x401f80e0 6 0x401f8658 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_swo: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO { + pinmux = <0x401f80e4 9 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_csi_data03: IOMUXC_GPIO_AD_B0_10_CSI_DATA03 { + pinmux = <0x401f80e4 4 0x401f8404 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80e4 7 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_crs: IOMUXC_GPIO_AD_B0_10_ENET_CRS { + pinmux = <0x401f80e4 2 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexcan3_tx: IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX { + pinmux = <0x401f80e4 8 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm1_pwma3: IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA3 { + pinmux = <0x401f80e4 1 0x401f8454 3 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio6_io10: IOMUXC_GPIO_AD_B0_10_GPIO6_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_jtag_tdo: IOMUXC_GPIO_AD_B0_10_JTAG_TDO { + pinmux = <0x401f80e4 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_sai2_mclk: IOMUXC_GPIO_AD_B0_10_SAI2_MCLK { + pinmux = <0x401f80e4 3 0x401f85b0 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_xbar1_xbar_in22: IOMUXC_GPIO_AD_B0_10_XBAR1_XBAR_IN22 { + pinmux = <0x401f80e4 6 0x401f8638 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_csi_data02: IOMUXC_GPIO_AD_B0_11_CSI_DATA02 { + pinmux = <0x401f80e8 4 0x401f8400 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN { + pinmux = <0x401f80e8 7 0x401f8444 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_col: IOMUXC_GPIO_AD_B0_11_ENET_COL { + pinmux = <0x401f80e8 2 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexcan3_rx: IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX { + pinmux = <0x401f80e8 8 0x401f878c 2 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB3 { + pinmux = <0x401f80e8 1 0x401f8464 3 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio6_io11: IOMUXC_GPIO_AD_B0_11_GPIO6_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_jtag_trstb: IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB { + pinmux = <0x401f80e8 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_semc_clk6: IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 { + pinmux = <0x401f80e8 9 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_wdog1_b: IOMUXC_GPIO_AD_B0_11_WDOG1_B { + pinmux = <0x401f80e8 3 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_xbar1_xbar_in23: IOMUXC_GPIO_AD_B0_11_XBAR1_XBAR_IN23 { + pinmux = <0x401f80e8 6 0x401f863c 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in1: IOMUXC_GPIO_AD_B0_12_ADC1_IN1 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_nmi: IOMUXC_GPIO_AD_B0_12_ARM_NMI { + pinmux = <0x401f80ec 7 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_12_CCM_PMIC_RDY { + pinmux = <0x401f80ec 1 0x401f83fc 1 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_1588_event1_out: IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT { + pinmux = <0x401f80ec 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm1_pwmx2: IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX2 { + pinmux = <0x401f80ec 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio6_io12: IOMUXC_GPIO_AD_B0_12_GPIO6_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpi2c4_scl: IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL { + pinmux = <0x401f80ec 0 0x401f84e4 1 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart1_tx: IOMUXC_GPIO_AD_B0_12_LPUART1_TX { + pinmux = <0x401f80ec 2 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_wdog2_b: IOMUXC_GPIO_AD_B0_12_WDOG2_B { + pinmux = <0x401f80ec 3 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_acmp1_in2: IOMUXC_GPIO_AD_B0_13_ACMP1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc1_in2: IOMUXC_GPIO_AD_B0_13_ADC1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_1588_event1_in: IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN { + pinmux = <0x401f80f0 6 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ewm_out_b: IOMUXC_GPIO_AD_B0_13_EWM_OUT_B { + pinmux = <0x401f80f0 3 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm1_pwmx3: IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX3 { + pinmux = <0x401f80f0 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio6_io13: IOMUXC_GPIO_AD_B0_13_GPIO6_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpt1_clk: IOMUXC_GPIO_AD_B0_13_GPT1_CLK { + pinmux = <0x401f80f0 1 0x401f8760 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpi2c4_sda: IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA { + pinmux = <0x401f80f0 0 0x401f84e8 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart1_rx: IOMUXC_GPIO_AD_B0_13_LPUART1_RX { + pinmux = <0x401f80f0 2 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ref_24m_out: IOMUXC_GPIO_AD_B0_13_REF_24M_OUT { + pinmux = <0x401f80f0 7 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in2: IOMUXC_GPIO_AD_B0_14_ACMP2_IN2 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in3: IOMUXC_GPIO_AD_B0_14_ADC1_IN3 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_csi_vsync: IOMUXC_GPIO_AD_B0_14_CSI_VSYNC { + pinmux = <0x401f80f4 4 0x401f8428 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80f4 3 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan3_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX { + pinmux = <0x401f80f4 8 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio6_io14: IOMUXC_GPIO_AD_B0_14_GPIO6_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B { + pinmux = <0x401f80f4 2 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_usb_otg2_oc: IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC { + pinmux = <0x401f80f4 0 0x401f85cc 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_xbar1_xbar_in24: IOMUXC_GPIO_AD_B0_14_XBAR1_XBAR_IN24 { + pinmux = <0x401f80f4 1 0x401f8640 1 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in2: IOMUXC_GPIO_AD_B0_15_ACMP3_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in4: IOMUXC_GPIO_AD_B0_15_ADC1_IN4 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_csi_hsync: IOMUXC_GPIO_AD_B0_15_CSI_HSYNC { + pinmux = <0x401f80f8 4 0x401f8420 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f80f8 3 0x401f8444 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 6 0x401f8450 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan3_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX { + pinmux = <0x401f80f8 8 0x401f878c 1 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio6_io15: IOMUXC_GPIO_AD_B0_15_GPIO6_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B { + pinmux = <0x401f80f8 2 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_usb_otg2_pwr: IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR { + pinmux = <0x401f80f8 0 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb: IOMUXC_GPIO_AD_B0_15_WDOG1_RST_B_DEB { + pinmux = <0x401f80f8 7 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_xbar1_xbar_in25: IOMUXC_GPIO_AD_B0_15_XBAR1_XBAR_IN25 { + pinmux = <0x401f80f8 1 0x401f8650 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp4_in2: IOMUXC_GPIO_AD_B1_00_ACMP4_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc1_in5: IOMUXC_GPIO_AD_B1_00_ADC1_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc2_in5: IOMUXC_GPIO_AD_B1_00_ADC2_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_enet2_1588_event0_out: IOMUXC_GPIO_AD_B1_00_ENET2_1588_EVENT0_OUT { + pinmux = <0x401f80fc 8 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio3_flexio00: IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 { + pinmux = <0x401f80fc 9 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio6_io16: IOMUXC_GPIO_AD_B1_00_GPIO6_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_kpp_row7: IOMUXC_GPIO_AD_B1_00_KPP_ROW7 { + pinmux = <0x401f80fc 7 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpi2c1_scl: IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL { + pinmux = <0x401f80fc 3 0x401f84cc 1 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B { + pinmux = <0x401f80fc 2 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_qtimer3_timer0: IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 { + pinmux = <0x401f80fc 1 0x401f857c 1 0x401f82ec>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usb_otg2_id: IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID { + pinmux = <0x401f80fc 0 0x401f83f8 1 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usdhc1_wp: IOMUXC_GPIO_AD_B1_00_USDHC1_WP { + pinmux = <0x401f80fc 6 0x401f85d8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_wdog1_b: IOMUXC_GPIO_AD_B1_00_WDOG1_B { + pinmux = <0x401f80fc 4 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp1_in0: IOMUXC_GPIO_AD_B1_01_ACMP1_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in0: IOMUXC_GPIO_AD_B1_01_ACMP2_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp3_in0: IOMUXC_GPIO_AD_B1_01_ACMP3_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp4_in0: IOMUXC_GPIO_AD_B1_01_ACMP4_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in6: IOMUXC_GPIO_AD_B1_01_ADC1_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc2_in6: IOMUXC_GPIO_AD_B1_01_ADC2_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_01_CCM_PMIC_RDY { + pinmux = <0x401f8100 4 0x401f83fc 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_enet2_1588_event0_in: IOMUXC_GPIO_AD_B1_01_ENET2_1588_EVENT0_IN { + pinmux = <0x401f8100 8 0x401f8724 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio3_flexio01: IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 { + pinmux = <0x401f8100 9 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio6_io17: IOMUXC_GPIO_AD_B1_01_GPIO6_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_kpp_col7: IOMUXC_GPIO_AD_B1_01_KPP_COL7 { + pinmux = <0x401f8100 7 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpi2c1_sda: IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA { + pinmux = <0x401f8100 3 0x401f84d0 1 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B { + pinmux = <0x401f8100 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_qtimer3_timer1: IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 { + pinmux = <0x401f8100 1 0x401f8580 0 0x401f82f0>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR { + pinmux = <0x401f8100 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usdhc1_vselect: IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT { + pinmux = <0x401f8100 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp1_in3: IOMUXC_GPIO_AD_B1_02_ACMP1_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc1_in7: IOMUXC_GPIO_AD_B1_02_ADC1_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in7: IOMUXC_GPIO_AD_B1_02_ADC2_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT { + pinmux = <0x401f8104 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio3_flexio02: IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 { + pinmux = <0x401f8104 9 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio6_io18: IOMUXC_GPIO_AD_B1_02_GPIO6_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpt2_clk: IOMUXC_GPIO_AD_B1_02_GPT2_CLK { + pinmux = <0x401f8104 8 0x401f876c 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_kpp_row6: IOMUXC_GPIO_AD_B1_02_KPP_ROW6 { + pinmux = <0x401f8104 7 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpuart2_tx: IOMUXC_GPIO_AD_B1_02_LPUART2_TX { + pinmux = <0x401f8104 2 0x401f8530 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_qtimer3_timer2: IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 { + pinmux = <0x401f8104 1 0x401f8584 1 0x401f82f4>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_spdif_out: IOMUXC_GPIO_AD_B1_02_SPDIF_OUT { + pinmux = <0x401f8104 3 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usb_otg1_id: IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID { + pinmux = <0x401f8104 0 0x401f83f4 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B { + pinmux = <0x401f8104 6 0x401f85d4 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp2_in3: IOMUXC_GPIO_AD_B1_03_ACMP2_IN3 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in8: IOMUXC_GPIO_AD_B1_03_ADC1_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc2_in8: IOMUXC_GPIO_AD_B1_03_ADC2_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN { + pinmux = <0x401f8108 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio3_flexio03: IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 { + pinmux = <0x401f8108 9 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio6_io19: IOMUXC_GPIO_AD_B1_03_GPIO6_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpt2_capture1: IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 { + pinmux = <0x401f8108 8 0x401f8764 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_kpp_col6: IOMUXC_GPIO_AD_B1_03_KPP_COL6 { + pinmux = <0x401f8108 7 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpuart2_rx: IOMUXC_GPIO_AD_B1_03_LPUART2_RX { + pinmux = <0x401f8108 2 0x401f852c 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_qtimer3_timer3: IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 { + pinmux = <0x401f8108 1 0x401f8588 1 0x401f82f8>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_spdif_in: IOMUXC_GPIO_AD_B1_03_SPDIF_IN { + pinmux = <0x401f8108 3 0x401f85c8 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usb_otg1_oc: IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC { + pinmux = <0x401f8108 0 0x401f85d0 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B { + pinmux = <0x401f8108 6 0x401f85e0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp3_in3: IOMUXC_GPIO_AD_B1_04_ACMP3_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc1_in9: IOMUXC_GPIO_AD_B1_04_ADC1_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in9: IOMUXC_GPIO_AD_B1_04_ADC2_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_csi_pixclk: IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK { + pinmux = <0x401f810c 4 0x401f8424 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_enet_mdc: IOMUXC_GPIO_AD_B1_04_ENET_MDC { + pinmux = <0x401f810c 1 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio3_flexio04: IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 { + pinmux = <0x401f810c 9 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_b_data3: IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 { + pinmux = <0x401f810c 0 0x401f84c4 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio6_io20: IOMUXC_GPIO_AD_B1_04_GPIO6_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpt2_capture2: IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 { + pinmux = <0x401f810c 8 0x401f8768 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_kpp_row5: IOMUXC_GPIO_AD_B1_04_KPP_ROW5 { + pinmux = <0x401f810c 7 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpuart3_cts_b: IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B { + pinmux = <0x401f810c 2 0x401f8534 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_spdif_sr_clk: IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK { + pinmux = <0x401f810c 3 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_usdhc2_data0: IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f810c 6 0x401f85e8 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp4_in3: IOMUXC_GPIO_AD_B1_05_ACMP4_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in10: IOMUXC_GPIO_AD_B1_05_ADC1_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in10: IOMUXC_GPIO_AD_B1_05_ADC2_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_csi_mclk: IOMUXC_GPIO_AD_B1_05_CSI_MCLK { + pinmux = <0x401f8110 4 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_enet_mdio: IOMUXC_GPIO_AD_B1_05_ENET_MDIO { + pinmux = <0x401f8110 1 0x401f8430 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio3_flexio05: IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 { + pinmux = <0x401f8110 9 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_b_data2: IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 { + pinmux = <0x401f8110 0 0x401f84c0 1 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio6_io21: IOMUXC_GPIO_AD_B1_05_GPIO6_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpt2_compare1: IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 { + pinmux = <0x401f8110 8 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_kpp_col5: IOMUXC_GPIO_AD_B1_05_KPP_COL5 { + pinmux = <0x401f8110 7 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpuart3_rts_b: IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B { + pinmux = <0x401f8110 2 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_spdif_out: IOMUXC_GPIO_AD_B1_05_SPDIF_OUT { + pinmux = <0x401f8110 3 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc2_data1: IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f8110 6 0x401f85ec 1 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp1_in1: IOMUXC_GPIO_AD_B1_06_ACMP1_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp2_in1: IOMUXC_GPIO_AD_B1_06_ACMP2_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in1: IOMUXC_GPIO_AD_B1_06_ACMP3_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp4_in1: IOMUXC_GPIO_AD_B1_06_ACMP4_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in11: IOMUXC_GPIO_AD_B1_06_ADC1_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in11: IOMUXC_GPIO_AD_B1_06_ADC2_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_csi_vsync: IOMUXC_GPIO_AD_B1_06_CSI_VSYNC { + pinmux = <0x401f8114 4 0x401f8428 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio3_flexio06: IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 { + pinmux = <0x401f8114 9 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexspi_b_data1: IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 { + pinmux = <0x401f8114 0 0x401f84bc 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio6_io22: IOMUXC_GPIO_AD_B1_06_GPIO6_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpt2_compare2: IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 { + pinmux = <0x401f8114 8 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_kpp_row4: IOMUXC_GPIO_AD_B1_06_KPP_ROW4 { + pinmux = <0x401f8114 7 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpi2c3_sda: IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA { + pinmux = <0x401f8114 1 0x401f84e0 2 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart3_tx: IOMUXC_GPIO_AD_B1_06_LPUART3_TX { + pinmux = <0x401f8114 2 0x401f853c 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_spdif_lock: IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK { + pinmux = <0x401f8114 3 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc2_data2: IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 { + pinmux = <0x401f8114 6 0x401f85f0 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp1_in5: IOMUXC_GPIO_AD_B1_07_ACMP1_IN5 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in12: IOMUXC_GPIO_AD_B1_07_ADC1_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in12: IOMUXC_GPIO_AD_B1_07_ADC2_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_csi_hsync: IOMUXC_GPIO_AD_B1_07_CSI_HSYNC { + pinmux = <0x401f8118 4 0x401f8420 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio3_flexio07: IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 { + pinmux = <0x401f8118 9 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexspi_b_data0: IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 { + pinmux = <0x401f8118 0 0x401f84b8 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio6_io23: IOMUXC_GPIO_AD_B1_07_GPIO6_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpt2_compare3: IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 { + pinmux = <0x401f8118 8 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_kpp_col4: IOMUXC_GPIO_AD_B1_07_KPP_COL4 { + pinmux = <0x401f8118 7 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpi2c3_scl: IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL { + pinmux = <0x401f8118 1 0x401f84dc 2 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart3_rx: IOMUXC_GPIO_AD_B1_07_LPUART3_RX { + pinmux = <0x401f8118 2 0x401f8538 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_spdif_ext_clk: IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK { + pinmux = <0x401f8118 3 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc2_data3: IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 { + pinmux = <0x401f8118 6 0x401f85f4 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_acmp2_in5: IOMUXC_GPIO_AD_B1_08_ACMP2_IN5 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc1_in13: IOMUXC_GPIO_AD_B1_08_ADC1_IN13 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc2_in13: IOMUXC_GPIO_AD_B1_08_ADC2_IN13 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_08_CCM_PMIC_RDY { + pinmux = <0x401f811c 3 0x401f83fc 3 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_csi_data09: IOMUXC_GPIO_AD_B1_08_CSI_DATA09 { + pinmux = <0x401f811c 4 0x401f841c 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexcan1_tx: IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX { + pinmux = <0x401f811c 2 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexio3_flexio08: IOMUXC_GPIO_AD_B1_08_FLEXIO3_FLEXIO08 { + pinmux = <0x401f811c 9 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexpwm4_pwma0: IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA0 { + pinmux = <0x401f811c 1 0x401f8494 1 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexspi_a_ss1_b: IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B { + pinmux = <0x401f811c 0 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio1_io24: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + gpr = <0x400ac068 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio6_io24: IOMUXC_GPIO_AD_B1_08_GPIO6_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + gpr = <0x400ac068 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_kpp_row3: IOMUXC_GPIO_AD_B1_08_KPP_ROW3 { + pinmux = <0x401f811c 7 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_usdhc2_cmd: IOMUXC_GPIO_AD_B1_08_USDHC2_CMD { + pinmux = <0x401f811c 6 0x401f85e4 1 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_acmp3_in5: IOMUXC_GPIO_AD_B1_09_ACMP3_IN5 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc1_in14: IOMUXC_GPIO_AD_B1_09_ADC1_IN14 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc2_in14: IOMUXC_GPIO_AD_B1_09_ADC2_IN14 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_csi_data08: IOMUXC_GPIO_AD_B1_09_CSI_DATA08 { + pinmux = <0x401f8120 4 0x401f8418 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexcan1_rx: IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX { + pinmux = <0x401f8120 2 0x401f844c 2 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexio3_flexio09: IOMUXC_GPIO_AD_B1_09_FLEXIO3_FLEXIO09 { + pinmux = <0x401f8120 9 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexpwm4_pwma1: IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA1 { + pinmux = <0x401f8120 1 0x401f8498 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexspi_a_dqs: IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS { + pinmux = <0x401f8120 0 0x401f84a4 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio1_io25: IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + gpr = <0x400ac068 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio6_io25: IOMUXC_GPIO_AD_B1_09_GPIO6_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + gpr = <0x400ac068 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_kpp_col3: IOMUXC_GPIO_AD_B1_09_KPP_COL3 { + pinmux = <0x401f8120 7 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_sai1_mclk: IOMUXC_GPIO_AD_B1_09_SAI1_MCLK { + pinmux = <0x401f8120 3 0x401f858c 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_usdhc2_clk: IOMUXC_GPIO_AD_B1_09_USDHC2_CLK { + pinmux = <0x401f8120 6 0x401f85dc 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_acmp4_in5: IOMUXC_GPIO_AD_B1_10_ACMP4_IN5 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in15: IOMUXC_GPIO_AD_B1_10_ADC1_IN15 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc2_in15: IOMUXC_GPIO_AD_B1_10_ADC2_IN15 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_csi_data07: IOMUXC_GPIO_AD_B1_10_CSI_DATA07 { + pinmux = <0x401f8124 4 0x401f8414 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_enet2_1588_event1_out: IOMUXC_GPIO_AD_B1_10_ENET2_1588_EVENT1_OUT { + pinmux = <0x401f8124 8 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio3_flexio10: IOMUXC_GPIO_AD_B1_10_FLEXIO3_FLEXIO10 { + pinmux = <0x401f8124 9 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexspi_a_data3: IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 { + pinmux = <0x401f8124 0 0x401f84b4 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + gpr = <0x400ac068 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio6_io26: IOMUXC_GPIO_AD_B1_10_GPIO6_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + gpr = <0x400ac068 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_kpp_row2: IOMUXC_GPIO_AD_B1_10_KPP_ROW2 { + pinmux = <0x401f8124 7 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart8_tx: IOMUXC_GPIO_AD_B1_10_LPUART8_TX { + pinmux = <0x401f8124 2 0x401f8564 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_sai1_rx_sync: IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC { + pinmux = <0x401f8124 3 0x401f85a4 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usdhc2_wp: IOMUXC_GPIO_AD_B1_10_USDHC2_WP { + pinmux = <0x401f8124 6 0x401f8608 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_wdog1_b: IOMUXC_GPIO_AD_B1_10_WDOG1_B { + pinmux = <0x401f8124 1 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_acmp1_in6: IOMUXC_GPIO_AD_B1_11_ACMP1_IN6 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in0: IOMUXC_GPIO_AD_B1_11_ADC1_IN0 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc2_in0: IOMUXC_GPIO_AD_B1_11_ADC2_IN0 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_csi_data06: IOMUXC_GPIO_AD_B1_11_CSI_DATA06 { + pinmux = <0x401f8128 4 0x401f8410 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_enet2_1588_event1_in: IOMUXC_GPIO_AD_B1_11_ENET2_1588_EVENT1_IN { + pinmux = <0x401f8128 8 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_ewm_out_b: IOMUXC_GPIO_AD_B1_11_EWM_OUT_B { + pinmux = <0x401f8128 1 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio3_flexio11: IOMUXC_GPIO_AD_B1_11_FLEXIO3_FLEXIO11 { + pinmux = <0x401f8128 9 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexspi_a_data2: IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 { + pinmux = <0x401f8128 0 0x401f84b0 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + gpr = <0x400ac068 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio6_io27: IOMUXC_GPIO_AD_B1_11_GPIO6_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + gpr = <0x400ac068 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_kpp_col2: IOMUXC_GPIO_AD_B1_11_KPP_COL2 { + pinmux = <0x401f8128 7 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart8_rx: IOMUXC_GPIO_AD_B1_11_LPUART8_RX { + pinmux = <0x401f8128 2 0x401f8560 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_sai1_rx_bclk: IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK { + pinmux = <0x401f8128 3 0x401f8590 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usdhc2_reset_b: IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B { + pinmux = <0x401f8128 6 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_out: IOMUXC_GPIO_AD_B1_12_ACMP1_OUT { + pinmux = <0x401f812c 1 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp2_in6: IOMUXC_GPIO_AD_B1_12_ACMP2_IN6 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc2_in1: IOMUXC_GPIO_AD_B1_12_ADC2_IN1 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_csi_data05: IOMUXC_GPIO_AD_B1_12_CSI_DATA05 { + pinmux = <0x401f812c 4 0x401f840c 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_enet2_1588_event2_out: IOMUXC_GPIO_AD_B1_12_ENET2_1588_EVENT2_OUT { + pinmux = <0x401f812c 8 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio3_flexio12: IOMUXC_GPIO_AD_B1_12_FLEXIO3_FLEXIO12 { + pinmux = <0x401f812c 9 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexspi_a_data1: IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 { + pinmux = <0x401f812c 0 0x401f84ac 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + gpr = <0x400ac068 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio6_io28: IOMUXC_GPIO_AD_B1_12_GPIO6_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + gpr = <0x400ac068 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_kpp_row1: IOMUXC_GPIO_AD_B1_12_KPP_ROW1 { + pinmux = <0x401f812c 7 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_lpspi3_pcs0: IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 { + pinmux = <0x401f812c 2 0x401f850c 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_sai1_rx_data0: IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA0 { + pinmux = <0x401f812c 3 0x401f8594 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usdhc2_data4: IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 { + pinmux = <0x401f812c 6 0x401f85f8 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_out: IOMUXC_GPIO_AD_B1_13_ACMP2_OUT { + pinmux = <0x401f8130 1 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp3_in6: IOMUXC_GPIO_AD_B1_13_ACMP3_IN6 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc2_in2: IOMUXC_GPIO_AD_B1_13_ADC2_IN2 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_csi_data04: IOMUXC_GPIO_AD_B1_13_CSI_DATA04 { + pinmux = <0x401f8130 4 0x401f8408 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_enet2_1588_event2_in: IOMUXC_GPIO_AD_B1_13_ENET2_1588_EVENT2_IN { + pinmux = <0x401f8130 8 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio3_flexio13: IOMUXC_GPIO_AD_B1_13_FLEXIO3_FLEXIO13 { + pinmux = <0x401f8130 9 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexspi_a_data0: IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 { + pinmux = <0x401f8130 0 0x401f84a8 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + gpr = <0x400ac068 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio6_io29: IOMUXC_GPIO_AD_B1_13_GPIO6_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + gpr = <0x400ac068 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_kpp_col1: IOMUXC_GPIO_AD_B1_13_KPP_COL1 { + pinmux = <0x401f8130 7 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpspi3_sdi: IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI { + pinmux = <0x401f8130 2 0x401f8514 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_sai1_tx_data0: IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA0 { + pinmux = <0x401f8130 3 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_usdhc2_data5: IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 { + pinmux = <0x401f8130 6 0x401f85fc 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_out: IOMUXC_GPIO_AD_B1_14_ACMP3_OUT { + pinmux = <0x401f8134 1 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp4_in6: IOMUXC_GPIO_AD_B1_14_ACMP4_IN6 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc2_in3: IOMUXC_GPIO_AD_B1_14_ADC2_IN3 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_csi_data03: IOMUXC_GPIO_AD_B1_14_CSI_DATA03 { + pinmux = <0x401f8134 4 0x401f8404 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_enet2_1588_event3_out: IOMUXC_GPIO_AD_B1_14_ENET2_1588_EVENT3_OUT { + pinmux = <0x401f8134 8 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio3_flexio14: IOMUXC_GPIO_AD_B1_14_FLEXIO3_FLEXIO14 { + pinmux = <0x401f8134 9 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexspi_a_sclk: IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK { + pinmux = <0x401f8134 0 0x401f84c8 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + gpr = <0x400ac068 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio6_io30: IOMUXC_GPIO_AD_B1_14_GPIO6_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + gpr = <0x400ac068 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_kpp_row0: IOMUXC_GPIO_AD_B1_14_KPP_ROW0 { + pinmux = <0x401f8134 7 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpspi3_sdo: IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO { + pinmux = <0x401f8134 2 0x401f8518 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_sai1_tx_bclk: IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK { + pinmux = <0x401f8134 3 0x401f85a8 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_usdhc2_data6: IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 { + pinmux = <0x401f8134 6 0x401f8600 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_out: IOMUXC_GPIO_AD_B1_15_ACMP4_OUT { + pinmux = <0x401f8138 1 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc2_in4: IOMUXC_GPIO_AD_B1_15_ADC2_IN4 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_csi_data02: IOMUXC_GPIO_AD_B1_15_CSI_DATA02 { + pinmux = <0x401f8138 4 0x401f8400 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_enet2_1588_event3_in: IOMUXC_GPIO_AD_B1_15_ENET2_1588_EVENT3_IN { + pinmux = <0x401f8138 8 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio3_flexio15: IOMUXC_GPIO_AD_B1_15_FLEXIO3_FLEXIO15 { + pinmux = <0x401f8138 9 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexspi_a_ss0_b: IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B { + pinmux = <0x401f8138 0 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + gpr = <0x400ac068 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio6_io31: IOMUXC_GPIO_AD_B1_15_GPIO6_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + gpr = <0x400ac068 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_kpp_col0: IOMUXC_GPIO_AD_B1_15_KPP_COL0 { + pinmux = <0x401f8138 7 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpspi3_sck: IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK { + pinmux = <0x401f8138 2 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_sai1_tx_sync: IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC { + pinmux = <0x401f8138 3 0x401f85ac 1 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_usdhc2_data7: IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 { + pinmux = <0x401f8138 6 0x401f8604 1 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_enet2_mdc: IOMUXC_GPIO_B0_00_ENET2_MDC { + pinmux = <0x401f813c 8 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_flexio2_flexio00: IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 { + pinmux = <0x401f813c 4 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio2_io00: IOMUXC_GPIO_B0_00_GPIO2_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio7_io00: IOMUXC_GPIO_B0_00_GPIO7_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lcdif_clk: IOMUXC_GPIO_B0_00_LCDIF_CLK { + pinmux = <0x401f813c 0 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lpspi4_pcs0: IOMUXC_GPIO_B0_00_LPSPI4_PCS0 { + pinmux = <0x401f813c 3 0x401f851c 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_mqs_right: IOMUXC_GPIO_B0_00_MQS_RIGHT { + pinmux = <0x401f813c 2 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_qtimer1_timer0: IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x0 0 0x401f832c>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_semc_csx1: IOMUXC_GPIO_B0_00_SEMC_CSX1 { + pinmux = <0x401f813c 6 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_enet2_mdio: IOMUXC_GPIO_B0_01_ENET2_MDIO { + pinmux = <0x401f8140 8 0x401f8710 1 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_flexio2_flexio01: IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 { + pinmux = <0x401f8140 4 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio2_io01: IOMUXC_GPIO_B0_01_GPIO2_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio7_io01: IOMUXC_GPIO_B0_01_GPIO7_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lcdif_enable: IOMUXC_GPIO_B0_01_LCDIF_ENABLE { + pinmux = <0x401f8140 0 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lpspi4_sdi: IOMUXC_GPIO_B0_01_LPSPI4_SDI { + pinmux = <0x401f8140 3 0x401f8524 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_mqs_left: IOMUXC_GPIO_B0_01_MQS_LEFT { + pinmux = <0x401f8140 2 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_qtimer1_timer1: IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x0 0 0x401f8330>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_semc_csx2: IOMUXC_GPIO_B0_01_SEMC_CSX2 { + pinmux = <0x401f8140 6 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_enet2_1588_event0_out: IOMUXC_GPIO_B0_02_ENET2_1588_EVENT0_OUT { + pinmux = <0x401f8144 8 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexcan1_tx: IOMUXC_GPIO_B0_02_FLEXCAN1_TX { + pinmux = <0x401f8144 2 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexio2_flexio02: IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 { + pinmux = <0x401f8144 4 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio2_io02: IOMUXC_GPIO_B0_02_GPIO2_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio7_io02: IOMUXC_GPIO_B0_02_GPIO7_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lcdif_hsync: IOMUXC_GPIO_B0_02_LCDIF_HSYNC { + pinmux = <0x401f8144 0 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lpspi4_sdo: IOMUXC_GPIO_B0_02_LPSPI4_SDO { + pinmux = <0x401f8144 3 0x401f8528 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_qtimer1_timer2: IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x0 0 0x401f8334>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_semc_csx3: IOMUXC_GPIO_B0_02_SEMC_CSX3 { + pinmux = <0x401f8144 6 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_enet2_1588_event0_in: IOMUXC_GPIO_B0_03_ENET2_1588_EVENT0_IN { + pinmux = <0x401f8148 8 0x401f8724 1 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexcan1_rx: IOMUXC_GPIO_B0_03_FLEXCAN1_RX { + pinmux = <0x401f8148 2 0x401f844c 3 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexio2_flexio03: IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 { + pinmux = <0x401f8148 4 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio2_io03: IOMUXC_GPIO_B0_03_GPIO2_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio7_io03: IOMUXC_GPIO_B0_03_GPIO7_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lcdif_vsync: IOMUXC_GPIO_B0_03_LCDIF_VSYNC { + pinmux = <0x401f8148 0 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lpspi4_sck: IOMUXC_GPIO_B0_03_LPSPI4_SCK { + pinmux = <0x401f8148 3 0x401f8520 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_qtimer2_timer0: IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 { + pinmux = <0x401f8148 1 0x401f856c 1 0x401f8338>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_wdog2_rst_b_deb: IOMUXC_GPIO_B0_03_WDOG2_RST_B_DEB { + pinmux = <0x401f8148 6 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_arm_trace0: IOMUXC_GPIO_B0_04_ARM_TRACE0 { + pinmux = <0x401f814c 3 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_enet2_tx_data3: IOMUXC_GPIO_B0_04_ENET2_TX_DATA3 { + pinmux = <0x401f814c 8 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_flexio2_flexio04: IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 { + pinmux = <0x401f814c 4 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio2_io04: IOMUXC_GPIO_B0_04_GPIO2_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio7_io04: IOMUXC_GPIO_B0_04_GPIO7_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lcdif_data00: IOMUXC_GPIO_B0_04_LCDIF_DATA00 { + pinmux = <0x401f814c 0 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lpi2c2_scl: IOMUXC_GPIO_B0_04_LPI2C2_SCL { + pinmux = <0x401f814c 2 0x401f84d4 1 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_qtimer2_timer1: IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 { + pinmux = <0x401f814c 1 0x401f8570 1 0x401f833c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_src_bt_cfg0: IOMUXC_GPIO_B0_04_SRC_BT_CFG0 { + pinmux = <0x401f814c 6 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_arm_trace1: IOMUXC_GPIO_B0_05_ARM_TRACE1 { + pinmux = <0x401f8150 3 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_enet2_tx_data2: IOMUXC_GPIO_B0_05_ENET2_TX_DATA2 { + pinmux = <0x401f8150 8 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_flexio2_flexio05: IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 { + pinmux = <0x401f8150 4 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio2_io05: IOMUXC_GPIO_B0_05_GPIO2_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio7_io05: IOMUXC_GPIO_B0_05_GPIO7_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lcdif_data01: IOMUXC_GPIO_B0_05_LCDIF_DATA01 { + pinmux = <0x401f8150 0 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lpi2c2_sda: IOMUXC_GPIO_B0_05_LPI2C2_SDA { + pinmux = <0x401f8150 2 0x401f84d8 1 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_qtimer2_timer2: IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 { + pinmux = <0x401f8150 1 0x401f8574 1 0x401f8340>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_src_bt_cfg1: IOMUXC_GPIO_B0_05_SRC_BT_CFG1 { + pinmux = <0x401f8150 6 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_arm_trace2: IOMUXC_GPIO_B0_06_ARM_TRACE2 { + pinmux = <0x401f8154 3 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_enet2_rx_clk: IOMUXC_GPIO_B0_06_ENET2_RX_CLK { + pinmux = <0x401f8154 8 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexio2_flexio06: IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 { + pinmux = <0x401f8154 4 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexpwm2_pwma0: IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f8154 2 0x401f8478 1 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio2_io06: IOMUXC_GPIO_B0_06_GPIO2_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio7_io06: IOMUXC_GPIO_B0_06_GPIO7_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_lcdif_data02: IOMUXC_GPIO_B0_06_LCDIF_DATA02 { + pinmux = <0x401f8154 0 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_qtimer3_timer0: IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 { + pinmux = <0x401f8154 1 0x401f857c 2 0x401f8344>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_src_bt_cfg2: IOMUXC_GPIO_B0_06_SRC_BT_CFG2 { + pinmux = <0x401f8154 6 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_arm_trace3: IOMUXC_GPIO_B0_07_ARM_TRACE3 { + pinmux = <0x401f8158 3 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_enet2_tx_er: IOMUXC_GPIO_B0_07_ENET2_TX_ER { + pinmux = <0x401f8158 8 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexio2_flexio07: IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 { + pinmux = <0x401f8158 4 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexpwm2_pwmb0: IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8158 2 0x401f8488 1 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio2_io07: IOMUXC_GPIO_B0_07_GPIO2_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio7_io07: IOMUXC_GPIO_B0_07_GPIO7_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_lcdif_data03: IOMUXC_GPIO_B0_07_LCDIF_DATA03 { + pinmux = <0x401f8158 0 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_qtimer3_timer1: IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 { + pinmux = <0x401f8158 1 0x401f8580 2 0x401f8348>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_src_bt_cfg3: IOMUXC_GPIO_B0_07_SRC_BT_CFG3 { + pinmux = <0x401f8158 6 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_enet2_rx_data3: IOMUXC_GPIO_B0_08_ENET2_RX_DATA3 { + pinmux = <0x401f815c 8 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexio2_flexio08: IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 { + pinmux = <0x401f815c 4 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexpwm2_pwma1: IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f815c 2 0x401f847c 1 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio2_io08: IOMUXC_GPIO_B0_08_GPIO2_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio7_io08: IOMUXC_GPIO_B0_08_GPIO7_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lcdif_data04: IOMUXC_GPIO_B0_08_LCDIF_DATA04 { + pinmux = <0x401f815c 0 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lpuart3_tx: IOMUXC_GPIO_B0_08_LPUART3_TX { + pinmux = <0x401f815c 3 0x401f853c 2 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_qtimer3_timer2: IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 { + pinmux = <0x401f815c 1 0x401f8584 2 0x401f834c>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_src_bt_cfg4: IOMUXC_GPIO_B0_08_SRC_BT_CFG4 { + pinmux = <0x401f815c 6 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_enet2_rx_data2: IOMUXC_GPIO_B0_09_ENET2_RX_DATA2 { + pinmux = <0x401f8160 8 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexio2_flexio09: IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 { + pinmux = <0x401f8160 4 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexpwm2_pwmb1: IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8160 2 0x401f848c 1 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio2_io09: IOMUXC_GPIO_B0_09_GPIO2_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio7_io09: IOMUXC_GPIO_B0_09_GPIO7_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lcdif_data05: IOMUXC_GPIO_B0_09_LCDIF_DATA05 { + pinmux = <0x401f8160 0 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lpuart3_rx: IOMUXC_GPIO_B0_09_LPUART3_RX { + pinmux = <0x401f8160 3 0x401f8538 2 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_qtimer4_timer0: IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 { + pinmux = <0x401f8160 1 0x0 0 0x401f8350>; + gpr = <0x400ac018 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_src_bt_cfg5: IOMUXC_GPIO_B0_09_SRC_BT_CFG5 { + pinmux = <0x401f8160 6 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_enet2_crs: IOMUXC_GPIO_B0_10_ENET2_CRS { + pinmux = <0x401f8164 8 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexio2_flexio10: IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 { + pinmux = <0x401f8164 4 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f8164 2 0x401f8480 1 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio2_io10: IOMUXC_GPIO_B0_10_GPIO2_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio7_io10: IOMUXC_GPIO_B0_10_GPIO7_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_lcdif_data06: IOMUXC_GPIO_B0_10_LCDIF_DATA06 { + pinmux = <0x401f8164 0 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_qtimer4_timer1: IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 { + pinmux = <0x401f8164 1 0x0 0 0x401f8354>; + gpr = <0x400ac018 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_sai1_tx_data3: IOMUXC_GPIO_B0_10_SAI1_TX_DATA3 { + pinmux = <0x401f8164 3 0x401f8598 1 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_src_bt_cfg6: IOMUXC_GPIO_B0_10_SRC_BT_CFG6 { + pinmux = <0x401f8164 6 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_enet2_col: IOMUXC_GPIO_B0_11_ENET2_COL { + pinmux = <0x401f8168 8 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexio2_flexio11: IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 { + pinmux = <0x401f8168 4 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8168 2 0x401f8490 1 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio2_io11: IOMUXC_GPIO_B0_11_GPIO2_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio7_io11: IOMUXC_GPIO_B0_11_GPIO7_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_lcdif_data07: IOMUXC_GPIO_B0_11_LCDIF_DATA07 { + pinmux = <0x401f8168 0 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_qtimer4_timer2: IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 { + pinmux = <0x401f8168 1 0x0 0 0x401f8358>; + gpr = <0x400ac018 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_sai1_tx_data2: IOMUXC_GPIO_B0_11_SAI1_TX_DATA2 { + pinmux = <0x401f8168 3 0x401f859c 1 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_src_bt_cfg7: IOMUXC_GPIO_B0_11_SRC_BT_CFG7 { + pinmux = <0x401f8168 6 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_arm_trace_clk: IOMUXC_GPIO_B0_12_ARM_TRACE_CLK { + pinmux = <0x401f816c 2 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_enet2_tx_data0: IOMUXC_GPIO_B0_12_ENET2_TX_DATA0 { + pinmux = <0x401f816c 8 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_flexio2_flexio12: IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 { + pinmux = <0x401f816c 4 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio2_io12: IOMUXC_GPIO_B0_12_GPIO2_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio7_io12: IOMUXC_GPIO_B0_12_GPIO7_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_lcdif_data08: IOMUXC_GPIO_B0_12_LCDIF_DATA08 { + pinmux = <0x401f816c 0 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_sai1_tx_data1: IOMUXC_GPIO_B0_12_SAI1_TX_DATA1 { + pinmux = <0x401f816c 3 0x401f85a0 1 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_src_bt_cfg8: IOMUXC_GPIO_B0_12_SRC_BT_CFG8 { + pinmux = <0x401f816c 6 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_in10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_IN10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_inout10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_arm_trace_swo: IOMUXC_GPIO_B0_13_ARM_TRACE_SWO { + pinmux = <0x401f8170 2 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_enet2_tx_data1: IOMUXC_GPIO_B0_13_ENET2_TX_DATA1 { + pinmux = <0x401f8170 8 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_flexio2_flexio13: IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 { + pinmux = <0x401f8170 4 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio2_io13: IOMUXC_GPIO_B0_13_GPIO2_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio7_io13: IOMUXC_GPIO_B0_13_GPIO7_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_lcdif_data09: IOMUXC_GPIO_B0_13_LCDIF_DATA09 { + pinmux = <0x401f8170 0 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_sai1_mclk: IOMUXC_GPIO_B0_13_SAI1_MCLK { + pinmux = <0x401f8170 3 0x401f858c 2 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_src_bt_cfg9: IOMUXC_GPIO_B0_13_SRC_BT_CFG9 { + pinmux = <0x401f8170 6 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_in11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_IN11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_inout11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_arm_txev: IOMUXC_GPIO_B0_14_ARM_TXEV { + pinmux = <0x401f8174 2 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_enet2_tx_en: IOMUXC_GPIO_B0_14_ENET2_TX_EN { + pinmux = <0x401f8174 8 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_flexio2_flexio14: IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 { + pinmux = <0x401f8174 4 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio2_io14: IOMUXC_GPIO_B0_14_GPIO2_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio7_io14: IOMUXC_GPIO_B0_14_GPIO7_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_lcdif_data10: IOMUXC_GPIO_B0_14_LCDIF_DATA10 { + pinmux = <0x401f8174 0 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_sai1_rx_sync: IOMUXC_GPIO_B0_14_SAI1_RX_SYNC { + pinmux = <0x401f8174 3 0x401f85a4 2 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_src_bt_cfg10: IOMUXC_GPIO_B0_14_SRC_BT_CFG10 { + pinmux = <0x401f8174 6 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_in12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_IN12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_inout12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_arm_rxev: IOMUXC_GPIO_B0_15_ARM_RXEV { + pinmux = <0x401f8178 2 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_enet2_ref_clk2: IOMUXC_GPIO_B0_15_ENET2_REF_CLK2 { + pinmux = <0x401f8178 9 0x401f870c 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_enet2_tx_clk: IOMUXC_GPIO_B0_15_ENET2_TX_CLK { + pinmux = <0x401f8178 8 0x401f8728 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_flexio2_flexio15: IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 { + pinmux = <0x401f8178 4 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio2_io15: IOMUXC_GPIO_B0_15_GPIO2_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio7_io15: IOMUXC_GPIO_B0_15_GPIO7_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_lcdif_data11: IOMUXC_GPIO_B0_15_LCDIF_DATA11 { + pinmux = <0x401f8178 0 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_sai1_rx_bclk: IOMUXC_GPIO_B0_15_SAI1_RX_BCLK { + pinmux = <0x401f8178 3 0x401f8590 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_src_bt_cfg11: IOMUXC_GPIO_B0_15_SRC_BT_CFG11 { + pinmux = <0x401f8178 6 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_in13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_IN13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_inout13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_enet2_rx_er: IOMUXC_GPIO_B1_00_ENET2_RX_ER { + pinmux = <0x401f817c 8 0x401f8720 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio2_flexio16: IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 { + pinmux = <0x401f817c 4 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio3_flexio16: IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 { + pinmux = <0x401f817c 9 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f817c 6 0x401f8454 4 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio2_io16: IOMUXC_GPIO_B1_00_GPIO2_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio7_io16: IOMUXC_GPIO_B1_00_GPIO7_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lcdif_data12: IOMUXC_GPIO_B1_00_LCDIF_DATA12 { + pinmux = <0x401f817c 0 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lpuart4_tx: IOMUXC_GPIO_B1_00_LPUART4_TX { + pinmux = <0x401f817c 2 0x401f8544 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_sai1_rx_data0: IOMUXC_GPIO_B1_00_SAI1_RX_DATA0 { + pinmux = <0x401f817c 3 0x401f8594 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_in14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f817c 1 0x401f8644 1 0x401f836c>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_inout14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f817c 1 0x401f8644 1 0x401f836c>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_enet2_rx_data0: IOMUXC_GPIO_B1_01_ENET2_RX_DATA0 { + pinmux = <0x401f8180 8 0x401f8714 2 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio2_flexio17: IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 { + pinmux = <0x401f8180 4 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio3_flexio17: IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 { + pinmux = <0x401f8180 9 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f8180 6 0x401f8464 4 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio2_io17: IOMUXC_GPIO_B1_01_GPIO2_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio7_io17: IOMUXC_GPIO_B1_01_GPIO7_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lcdif_data13: IOMUXC_GPIO_B1_01_LCDIF_DATA13 { + pinmux = <0x401f8180 0 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lpuart4_rx: IOMUXC_GPIO_B1_01_LPUART4_RX { + pinmux = <0x401f8180 2 0x401f8540 2 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_sai1_tx_data0: IOMUXC_GPIO_B1_01_SAI1_TX_DATA0 { + pinmux = <0x401f8180 3 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_in15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8180 1 0x401f8648 1 0x401f8370>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_inout15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8180 1 0x401f8648 1 0x401f8370>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_enet2_rx_data1: IOMUXC_GPIO_B1_02_ENET2_RX_DATA1 { + pinmux = <0x401f8184 8 0x401f8718 2 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio2_flexio18: IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 { + pinmux = <0x401f8184 4 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio3_flexio18: IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 { + pinmux = <0x401f8184 9 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f8184 6 0x401f8474 4 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio2_io18: IOMUXC_GPIO_B1_02_GPIO2_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio7_io18: IOMUXC_GPIO_B1_02_GPIO7_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lcdif_data14: IOMUXC_GPIO_B1_02_LCDIF_DATA14 { + pinmux = <0x401f8184 0 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lpspi4_pcs2: IOMUXC_GPIO_B1_02_LPSPI4_PCS2 { + pinmux = <0x401f8184 2 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_sai1_tx_bclk: IOMUXC_GPIO_B1_02_SAI1_TX_BCLK { + pinmux = <0x401f8184 3 0x401f85a8 2 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_in16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8184 1 0x401f864c 1 0x401f8374>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_inout16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8184 1 0x401f864c 1 0x401f8374>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_enet2_rx_en: IOMUXC_GPIO_B1_03_ENET2_RX_EN { + pinmux = <0x401f8188 8 0x401f871c 2 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio2_flexio19: IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 { + pinmux = <0x401f8188 4 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio3_flexio19: IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 { + pinmux = <0x401f8188 9 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f8188 6 0x401f8484 3 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio2_io19: IOMUXC_GPIO_B1_03_GPIO2_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio7_io19: IOMUXC_GPIO_B1_03_GPIO7_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lcdif_data15: IOMUXC_GPIO_B1_03_LCDIF_DATA15 { + pinmux = <0x401f8188 0 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lpspi4_pcs1: IOMUXC_GPIO_B1_03_LPSPI4_PCS1 { + pinmux = <0x401f8188 2 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_sai1_tx_sync: IOMUXC_GPIO_B1_03_SAI1_TX_SYNC { + pinmux = <0x401f8188 3 0x401f85ac 2 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_in17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f8188 1 0x401f862c 3 0x401f8378>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_inout17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8188 1 0x401f862c 3 0x401f8378>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_csi_data15: IOMUXC_GPIO_B1_04_CSI_DATA15 { + pinmux = <0x401f818c 2 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_enet_rx_data0: IOMUXC_GPIO_B1_04_ENET_RX_DATA0 { + pinmux = <0x401f818c 3 0x401f8434 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio2_flexio20: IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 { + pinmux = <0x401f818c 4 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio3_flexio20: IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 { + pinmux = <0x401f818c 9 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio2_io20: IOMUXC_GPIO_B1_04_GPIO2_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio7_io20: IOMUXC_GPIO_B1_04_GPIO7_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpt1_clk: IOMUXC_GPIO_B1_04_GPT1_CLK { + pinmux = <0x401f818c 8 0x401f8760 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lcdif_data16: IOMUXC_GPIO_B1_04_LCDIF_DATA16 { + pinmux = <0x401f818c 0 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lpspi4_pcs0: IOMUXC_GPIO_B1_04_LPSPI4_PCS0 { + pinmux = <0x401f818c 1 0x401f851c 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_csi_data14: IOMUXC_GPIO_B1_05_CSI_DATA14 { + pinmux = <0x401f8190 2 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_enet_rx_data1: IOMUXC_GPIO_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f8190 3 0x401f8438 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio2_flexio21: IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 { + pinmux = <0x401f8190 4 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio3_flexio21: IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 { + pinmux = <0x401f8190 9 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio2_io21: IOMUXC_GPIO_B1_05_GPIO2_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio7_io21: IOMUXC_GPIO_B1_05_GPIO7_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpt1_capture1: IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 { + pinmux = <0x401f8190 8 0x401f8758 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lcdif_data17: IOMUXC_GPIO_B1_05_LCDIF_DATA17 { + pinmux = <0x401f8190 0 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lpspi4_sdi: IOMUXC_GPIO_B1_05_LPSPI4_SDI { + pinmux = <0x401f8190 1 0x401f8524 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_csi_data13: IOMUXC_GPIO_B1_06_CSI_DATA13 { + pinmux = <0x401f8194 2 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_enet_rx_en: IOMUXC_GPIO_B1_06_ENET_RX_EN { + pinmux = <0x401f8194 3 0x401f843c 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio2_flexio22: IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 { + pinmux = <0x401f8194 4 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio3_flexio22: IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 { + pinmux = <0x401f8194 9 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio2_io22: IOMUXC_GPIO_B1_06_GPIO2_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio7_io22: IOMUXC_GPIO_B1_06_GPIO7_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpt1_capture2: IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 { + pinmux = <0x401f8194 8 0x401f875c 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lcdif_data18: IOMUXC_GPIO_B1_06_LCDIF_DATA18 { + pinmux = <0x401f8194 0 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lpspi4_sdo: IOMUXC_GPIO_B1_06_LPSPI4_SDO { + pinmux = <0x401f8194 1 0x401f8528 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_csi_data12: IOMUXC_GPIO_B1_07_CSI_DATA12 { + pinmux = <0x401f8198 2 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_enet_tx_data0: IOMUXC_GPIO_B1_07_ENET_TX_DATA0 { + pinmux = <0x401f8198 3 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio2_flexio23: IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 { + pinmux = <0x401f8198 4 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio3_flexio23: IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 { + pinmux = <0x401f8198 9 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio2_io23: IOMUXC_GPIO_B1_07_GPIO2_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio7_io23: IOMUXC_GPIO_B1_07_GPIO7_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpt1_compare1: IOMUXC_GPIO_B1_07_GPT1_COMPARE1 { + pinmux = <0x401f8198 8 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lcdif_data19: IOMUXC_GPIO_B1_07_LCDIF_DATA19 { + pinmux = <0x401f8198 0 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lpspi4_sck: IOMUXC_GPIO_B1_07_LPSPI4_SCK { + pinmux = <0x401f8198 1 0x401f8520 1 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_csi_data11: IOMUXC_GPIO_B1_08_CSI_DATA11 { + pinmux = <0x401f819c 2 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_enet_tx_data1: IOMUXC_GPIO_B1_08_ENET_TX_DATA1 { + pinmux = <0x401f819c 3 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexcan2_tx: IOMUXC_GPIO_B1_08_FLEXCAN2_TX { + pinmux = <0x401f819c 6 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio2_flexio24: IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 { + pinmux = <0x401f819c 4 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio3_flexio24: IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 { + pinmux = <0x401f819c 9 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio2_io24: IOMUXC_GPIO_B1_08_GPIO2_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio7_io24: IOMUXC_GPIO_B1_08_GPIO7_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpt1_compare2: IOMUXC_GPIO_B1_08_GPT1_COMPARE2 { + pinmux = <0x401f819c 8 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_lcdif_data20: IOMUXC_GPIO_B1_08_LCDIF_DATA20 { + pinmux = <0x401f819c 0 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_qtimer1_timer3: IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 { + pinmux = <0x401f819c 1 0x0 0 0x401f838c>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_csi_data10: IOMUXC_GPIO_B1_09_CSI_DATA10 { + pinmux = <0x401f81a0 2 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_enet_tx_en: IOMUXC_GPIO_B1_09_ENET_TX_EN { + pinmux = <0x401f81a0 3 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexcan2_rx: IOMUXC_GPIO_B1_09_FLEXCAN2_RX { + pinmux = <0x401f81a0 6 0x401f8450 3 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio2_flexio25: IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 { + pinmux = <0x401f81a0 4 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio3_flexio25: IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 { + pinmux = <0x401f81a0 9 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio2_io25: IOMUXC_GPIO_B1_09_GPIO2_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio7_io25: IOMUXC_GPIO_B1_09_GPIO7_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpt1_compare3: IOMUXC_GPIO_B1_09_GPT1_COMPARE3 { + pinmux = <0x401f81a0 8 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_lcdif_data21: IOMUXC_GPIO_B1_09_LCDIF_DATA21 { + pinmux = <0x401f81a0 0 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_qtimer2_timer3: IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 { + pinmux = <0x401f81a0 1 0x401f8578 1 0x401f8390>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_csi_data00: IOMUXC_GPIO_B1_10_CSI_DATA00 { + pinmux = <0x401f81a4 2 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_ref_clk: IOMUXC_GPIO_B1_10_ENET_REF_CLK { + pinmux = <0x401f81a4 6 0x401f842c 1 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_tx_clk: IOMUXC_GPIO_B1_10_ENET_TX_CLK { + pinmux = <0x401f81a4 3 0x401f8448 1 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio2_flexio26: IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 { + pinmux = <0x401f81a4 4 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio3_flexio26: IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 { + pinmux = <0x401f81a4 9 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio2_io26: IOMUXC_GPIO_B1_10_GPIO2_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio7_io26: IOMUXC_GPIO_B1_10_GPIO7_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_lcdif_data22: IOMUXC_GPIO_B1_10_LCDIF_DATA22 { + pinmux = <0x401f81a4 0 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_qtimer3_timer3: IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 { + pinmux = <0x401f81a4 1 0x401f8588 2 0x401f8394>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_csi_data01: IOMUXC_GPIO_B1_11_CSI_DATA01 { + pinmux = <0x401f81a8 2 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_enet_rx_er: IOMUXC_GPIO_B1_11_ENET_RX_ER { + pinmux = <0x401f81a8 3 0x401f8440 1 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio2_flexio27: IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 { + pinmux = <0x401f81a8 4 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio3_flexio27: IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 { + pinmux = <0x401f81a8 9 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio2_io27: IOMUXC_GPIO_B1_11_GPIO2_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio7_io27: IOMUXC_GPIO_B1_11_GPIO7_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lcdif_data23: IOMUXC_GPIO_B1_11_LCDIF_DATA23 { + pinmux = <0x401f81a8 0 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lpspi4_pcs3: IOMUXC_GPIO_B1_11_LPSPI4_PCS3 { + pinmux = <0x401f81a8 6 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_qtimer4_timer3: IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 { + pinmux = <0x401f81a8 1 0x0 0 0x401f8398>; + gpr = <0x400ac018 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_csi_pixclk: IOMUXC_GPIO_B1_12_CSI_PIXCLK { + pinmux = <0x401f81ac 2 0x401f8424 1 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_enet_1588_event0_in: IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN { + pinmux = <0x401f81ac 3 0x401f8444 2 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio2_flexio28: IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 { + pinmux = <0x401f81ac 4 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio3_flexio28: IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 { + pinmux = <0x401f81ac 9 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio2_io28: IOMUXC_GPIO_B1_12_GPIO2_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio7_io28: IOMUXC_GPIO_B1_12_GPIO7_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_lpuart5_tx: IOMUXC_GPIO_B1_12_LPUART5_TX { + pinmux = <0x401f81ac 1 0x401f854c 1 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_usdhc1_cd_b: IOMUXC_GPIO_B1_12_USDHC1_CD_B { + pinmux = <0x401f81ac 6 0x401f85d4 2 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_csi_vsync: IOMUXC_GPIO_B1_13_CSI_VSYNC { + pinmux = <0x401f81b0 2 0x401f8428 2 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_enet_1588_event0_out: IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT { + pinmux = <0x401f81b0 3 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio2_flexio29: IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 { + pinmux = <0x401f81b0 4 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio3_flexio29: IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 { + pinmux = <0x401f81b0 9 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio2_io29: IOMUXC_GPIO_B1_13_GPIO2_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio7_io29: IOMUXC_GPIO_B1_13_GPIO7_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_lpuart5_rx: IOMUXC_GPIO_B1_13_LPUART5_RX { + pinmux = <0x401f81b0 1 0x401f8548 1 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_semc_dqs4: IOMUXC_GPIO_B1_13_SEMC_DQS4 { + pinmux = <0x401f81b0 8 0x401f8788 3 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_usdhc1_wp: IOMUXC_GPIO_B1_13_USDHC1_WP { + pinmux = <0x401f81b0 6 0x401f85d8 3 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_wdog1_b: IOMUXC_GPIO_B1_13_WDOG1_B { + pinmux = <0x401f81b0 0 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_csi_hsync: IOMUXC_GPIO_B1_14_CSI_HSYNC { + pinmux = <0x401f81b4 2 0x401f8420 2 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet2_tx_data0: IOMUXC_GPIO_B1_14_ENET2_TX_DATA0 { + pinmux = <0x401f81b4 8 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet_mdc: IOMUXC_GPIO_B1_14_ENET_MDC { + pinmux = <0x401f81b4 0 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio2_flexio30: IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 { + pinmux = <0x401f81b4 4 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio3_flexio30: IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 { + pinmux = <0x401f81b4 9 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexpwm4_pwma2: IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA2 { + pinmux = <0x401f81b4 1 0x401f849c 1 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio2_io30: IOMUXC_GPIO_B1_14_GPIO2_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio7_io30: IOMUXC_GPIO_B1_14_GPIO7_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_usdhc1_vselect: IOMUXC_GPIO_B1_14_USDHC1_VSELECT { + pinmux = <0x401f81b4 6 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_xbar1_xbar_in02: IOMUXC_GPIO_B1_14_XBAR1_XBAR_IN02 { + pinmux = <0x401f81b4 3 0x401f860c 1 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_csi_mclk: IOMUXC_GPIO_B1_15_CSI_MCLK { + pinmux = <0x401f81b8 2 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet2_tx_data1: IOMUXC_GPIO_B1_15_ENET2_TX_DATA1 { + pinmux = <0x401f81b8 8 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet_mdio: IOMUXC_GPIO_B1_15_ENET_MDIO { + pinmux = <0x401f81b8 0 0x401f8430 2 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio2_flexio31: IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 { + pinmux = <0x401f81b8 4 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio3_flexio31: IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 { + pinmux = <0x401f81b8 9 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexpwm4_pwma3: IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA3 { + pinmux = <0x401f81b8 1 0x401f84a0 1 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio2_io31: IOMUXC_GPIO_B1_15_GPIO2_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio7_io31: IOMUXC_GPIO_B1_15_GPIO7_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_usdhc1_reset_b: IOMUXC_GPIO_B1_15_USDHC1_RESET_B { + pinmux = <0x401f81b8 6 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_xbar1_xbar_in03: IOMUXC_GPIO_B1_15_XBAR1_XBAR_IN03 { + pinmux = <0x401f81b8 3 0x401f8610 1 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexio1_flexio00: IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8014 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexpwm4_pwma0: IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA0 { + pinmux = <0x401f8014 1 0x401f8494 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio4_io00: IOMUXC_GPIO_EMC_00_GPIO4_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio9_io00: IOMUXC_GPIO_EMC_00_GPIO9_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 2 0x401f8500 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_xbar1_xbar_in02: IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 { + pinmux = <0x401f8014 3 0x401f860c 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexio1_flexio01: IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8018 4 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexpwm4_pwmb0: IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB0 { + pinmux = <0x401f8018 1 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio4_io01: IOMUXC_GPIO_EMC_01_GPIO4_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio9_io01: IOMUXC_GPIO_EMC_01_GPIO9_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 2 0x401f84fc 1 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_xbar1_xbar_in03: IOMUXC_GPIO_EMC_01_XBAR1_XBAR_IN03 { + pinmux = <0x401f8018 3 0x401f8610 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexio1_flexio02: IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 { + pinmux = <0x401f801c 4 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexpwm4_pwma1: IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA1 { + pinmux = <0x401f801c 1 0x401f8498 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio4_io02: IOMUXC_GPIO_EMC_02_GPIO4_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio9_io02: IOMUXC_GPIO_EMC_02_GPIO9_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 2 0x401f8508 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_in04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_IN04 { + pinmux = <0x401f801c 3 0x401f8614 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f801c 3 0x401f8614 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexio1_flexio03: IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 { + pinmux = <0x401f8020 4 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexpwm4_pwmb1: IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB1 { + pinmux = <0x401f8020 1 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio4_io03: IOMUXC_GPIO_EMC_03_GPIO4_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio9_io03: IOMUXC_GPIO_EMC_03_GPIO9_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 2 0x401f8504 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_in05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_IN05 { + pinmux = <0x401f8020 3 0x401f8618 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8020 3 0x401f8618 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio04: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8024 4 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexpwm4_pwma2: IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA2 { + pinmux = <0x401f8024 1 0x401f849c 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio4_io04: IOMUXC_GPIO_EMC_04_GPIO4_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio9_io04: IOMUXC_GPIO_EMC_04_GPIO9_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_data: IOMUXC_GPIO_EMC_04_SAI2_TX_DATA { + pinmux = <0x401f8024 2 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN06 { + pinmux = <0x401f8024 3 0x401f861c 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f8024 3 0x401f861c 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio05: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8028 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexpwm4_pwmb2: IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB2 { + pinmux = <0x401f8028 1 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio4_io05: IOMUXC_GPIO_EMC_05_GPIO4_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio9_io05: IOMUXC_GPIO_EMC_05_GPIO9_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 2 0x401f85c4 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN07 { + pinmux = <0x401f8028 3 0x401f8620 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8028 3 0x401f8620 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio06: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 { + pinmux = <0x401f802c 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexpwm2_pwma0: IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f802c 1 0x401f8478 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio4_io06: IOMUXC_GPIO_EMC_06_GPIO4_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio9_io06: IOMUXC_GPIO_EMC_06_GPIO9_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_bclk: IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK { + pinmux = <0x401f802c 2 0x401f85c0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN08 { + pinmux = <0x401f802c 3 0x401f8624 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f802c 3 0x401f8624 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio07: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 { + pinmux = <0x401f8030 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8030 1 0x401f8488 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio4_io07: IOMUXC_GPIO_EMC_07_GPIO4_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio9_io07: IOMUXC_GPIO_EMC_07_GPIO9_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_mclk: IOMUXC_GPIO_EMC_07_SAI2_MCLK { + pinmux = <0x401f8030 2 0x401f85b0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN09 { + pinmux = <0x401f8030 3 0x401f8628 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8030 3 0x401f8628 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio08: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8034 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexpwm2_pwma1: IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f8034 1 0x401f847c 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio4_io08: IOMUXC_GPIO_EMC_08_GPIO4_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio9_io08: IOMUXC_GPIO_EMC_08_GPIO9_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 2 0x401f85b8 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN17 { + pinmux = <0x401f8034 3 0x401f862c 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8034 3 0x401f862c 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_tx: IOMUXC_GPIO_EMC_09_FLEXCAN2_TX { + pinmux = <0x401f8038 3 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio09: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8038 4 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8038 1 0x401f848c 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio4_io09: IOMUXC_GPIO_EMC_09_GPIO4_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio9_io09: IOMUXC_GPIO_EMC_09_GPIO9_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_sync: IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC { + pinmux = <0x401f8038 2 0x401f85bc 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_addr00: IOMUXC_GPIO_EMC_09_SEMC_ADDR00 { + pinmux = <0x401f8038 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexcan2_rx: IOMUXC_GPIO_EMC_10_FLEXCAN2_RX { + pinmux = <0x401f803c 3 0x401f8450 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexio1_flexio10: IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 { + pinmux = <0x401f803c 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwma2: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f803c 1 0x401f8480 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio4_io10: IOMUXC_GPIO_EMC_10_GPIO4_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio9_io10: IOMUXC_GPIO_EMC_10_GPIO9_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai2_rx_bclk: IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK { + pinmux = <0x401f803c 2 0x401f85b4 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_addr01: IOMUXC_GPIO_EMC_10_SEMC_ADDR01 { + pinmux = <0x401f803c 0 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexio1_flexio11: IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 { + pinmux = <0x401f8040 4 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8040 1 0x401f8490 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio4_io11: IOMUXC_GPIO_EMC_11_GPIO4_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio9_io11: IOMUXC_GPIO_EMC_11_GPIO9_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_sda: IOMUXC_GPIO_EMC_11_LPI2C4_SDA { + pinmux = <0x401f8040 2 0x401f84e8 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_addr02: IOMUXC_GPIO_EMC_11_SEMC_ADDR02 { + pinmux = <0x401f8040 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_usdhc2_reset_b: IOMUXC_GPIO_EMC_11_USDHC2_RESET_B { + pinmux = <0x401f8040 3 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm1_pwma3: IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f8044 4 0x401f8454 1 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio4_io12: IOMUXC_GPIO_EMC_12_GPIO4_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio9_io12: IOMUXC_GPIO_EMC_12_GPIO9_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpi2c4_scl: IOMUXC_GPIO_EMC_12_LPI2C4_SCL { + pinmux = <0x401f8044 2 0x401f84e4 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_addr03: IOMUXC_GPIO_EMC_12_SEMC_ADDR03 { + pinmux = <0x401f8044 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_usdhc1_wp: IOMUXC_GPIO_EMC_12_USDHC1_WP { + pinmux = <0x401f8044 3 0x401f85d8 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in24: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN24 { + pinmux = <0x401f8044 1 0x401f8640 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8048 4 0x401f8464 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio4_io13: IOMUXC_GPIO_EMC_13_GPIO4_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio9_io13: IOMUXC_GPIO_EMC_13_GPIO9_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart3_tx: IOMUXC_GPIO_EMC_13_LPUART3_TX { + pinmux = <0x401f8048 2 0x401f853c 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_mqs_right: IOMUXC_GPIO_EMC_13_MQS_RIGHT { + pinmux = <0x401f8048 3 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_addr04: IOMUXC_GPIO_EMC_13_SEMC_ADDR04 { + pinmux = <0x401f8048 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in25: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN25 { + pinmux = <0x401f8048 1 0x401f8650 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio4_io14: IOMUXC_GPIO_EMC_14_GPIO4_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio9_io14: IOMUXC_GPIO_EMC_14_GPIO9_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart3_rx: IOMUXC_GPIO_EMC_14_LPUART3_RX { + pinmux = <0x401f804c 2 0x401f8538 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_mqs_left: IOMUXC_GPIO_EMC_14_MQS_LEFT { + pinmux = <0x401f804c 3 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_addr05: IOMUXC_GPIO_EMC_14_SEMC_ADDR05 { + pinmux = <0x401f804c 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN19 { + pinmux = <0x401f804c 1 0x401f8654 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f804c 1 0x401f8654 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio4_io15: IOMUXC_GPIO_EMC_15_GPIO4_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio9_io15: IOMUXC_GPIO_EMC_15_GPIO9_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart3_cts_b: IOMUXC_GPIO_EMC_15_LPUART3_CTS_B { + pinmux = <0x401f8050 2 0x401f8534 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_qtimer3_timer0: IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 { + pinmux = <0x401f8050 4 0x401f857c 0 0x401f8240>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr06: IOMUXC_GPIO_EMC_15_SEMC_ADDR06 { + pinmux = <0x401f8050 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_spdif_out: IOMUXC_GPIO_EMC_15_SPDIF_OUT { + pinmux = <0x401f8050 3 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in20: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN20 { + pinmux = <0x401f8050 1 0x401f8634 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio4_io16: IOMUXC_GPIO_EMC_16_GPIO4_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio9_io16: IOMUXC_GPIO_EMC_16_GPIO9_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_lpuart3_rts_b: IOMUXC_GPIO_EMC_16_LPUART3_RTS_B { + pinmux = <0x401f8054 2 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_qtimer3_timer1: IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 { + pinmux = <0x401f8054 4 0x401f8580 1 0x401f8244>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr07: IOMUXC_GPIO_EMC_16_SEMC_ADDR07 { + pinmux = <0x401f8054 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_spdif_in: IOMUXC_GPIO_EMC_16_SPDIF_IN { + pinmux = <0x401f8054 3 0x401f85c8 1 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_xbar1_xbar_in21: IOMUXC_GPIO_EMC_16_XBAR1_XBAR_IN21 { + pinmux = <0x401f8054 1 0x401f8658 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexcan1_tx: IOMUXC_GPIO_EMC_17_FLEXCAN1_TX { + pinmux = <0x401f8058 3 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexpwm4_pwma3: IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA3 { + pinmux = <0x401f8058 1 0x401f84a0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio4_io17: IOMUXC_GPIO_EMC_17_GPIO4_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio9_io17: IOMUXC_GPIO_EMC_17_GPIO9_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_lpuart4_cts_b: IOMUXC_GPIO_EMC_17_LPUART4_CTS_B { + pinmux = <0x401f8058 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_qtimer3_timer2: IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 { + pinmux = <0x401f8058 4 0x401f8584 0 0x401f8248>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr08: IOMUXC_GPIO_EMC_17_SEMC_ADDR08 { + pinmux = <0x401f8058 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexcan1_rx: IOMUXC_GPIO_EMC_18_FLEXCAN1_RX { + pinmux = <0x401f805c 3 0x401f844c 1 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexpwm4_pwmb3: IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB3 { + pinmux = <0x401f805c 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio4_io18: IOMUXC_GPIO_EMC_18_GPIO4_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio9_io18: IOMUXC_GPIO_EMC_18_GPIO9_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpuart4_rts_b: IOMUXC_GPIO_EMC_18_LPUART4_RTS_B { + pinmux = <0x401f805c 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_qtimer3_timer3: IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 { + pinmux = <0x401f805c 4 0x401f8588 0 0x401f824c>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr09: IOMUXC_GPIO_EMC_18_SEMC_ADDR09 { + pinmux = <0x401f805c 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_snvs_vio_5_ctl: IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL { + pinmux = <0x401f805c 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_enet_rx_data1: IOMUXC_GPIO_EMC_19_ENET_RX_DATA1 { + pinmux = <0x401f8060 3 0x401f8438 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexpwm2_pwma3: IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA3 { + pinmux = <0x401f8060 1 0x401f8474 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio4_io19: IOMUXC_GPIO_EMC_19_GPIO4_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio9_io19: IOMUXC_GPIO_EMC_19_GPIO9_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpuart4_tx: IOMUXC_GPIO_EMC_19_LPUART4_TX { + pinmux = <0x401f8060 2 0x401f8544 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_qtimer2_timer0: IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 { + pinmux = <0x401f8060 4 0x401f856c 0 0x401f8250>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr11: IOMUXC_GPIO_EMC_19_SEMC_ADDR11 { + pinmux = <0x401f8060 0 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_snvs_vio_5_b: IOMUXC_GPIO_EMC_19_SNVS_VIO_5_B { + pinmux = <0x401f8060 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_enet_rx_data0: IOMUXC_GPIO_EMC_20_ENET_RX_DATA0 { + pinmux = <0x401f8064 3 0x401f8434 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB3 { + pinmux = <0x401f8064 1 0x401f8484 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio4_io20: IOMUXC_GPIO_EMC_20_GPIO4_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio9_io20: IOMUXC_GPIO_EMC_20_GPIO9_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart4_rx: IOMUXC_GPIO_EMC_20_LPUART4_RX { + pinmux = <0x401f8064 2 0x401f8540 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_qtimer2_timer1: IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 { + pinmux = <0x401f8064 4 0x401f8570 0 0x401f8254>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr12: IOMUXC_GPIO_EMC_20_SEMC_ADDR12 { + pinmux = <0x401f8064 0 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_enet_tx_data1: IOMUXC_GPIO_EMC_21_ENET_TX_DATA1 { + pinmux = <0x401f8068 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm3_pwma3: IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA3 { + pinmux = <0x401f8068 1 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio4_io21: IOMUXC_GPIO_EMC_21_GPIO4_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio9_io21: IOMUXC_GPIO_EMC_21_GPIO9_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpi2c3_sda: IOMUXC_GPIO_EMC_21_LPI2C3_SDA { + pinmux = <0x401f8068 2 0x401f84e0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_qtimer2_timer2: IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 { + pinmux = <0x401f8068 4 0x401f8574 0 0x401f8258>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_ba0: IOMUXC_GPIO_EMC_21_SEMC_BA0 { + pinmux = <0x401f8068 0 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_enet_tx_data0: IOMUXC_GPIO_EMC_22_ENET_TX_DATA0 { + pinmux = <0x401f806c 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm3_pwmb3: IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB3 { + pinmux = <0x401f806c 1 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio4_io22: IOMUXC_GPIO_EMC_22_GPIO4_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio9_io22: IOMUXC_GPIO_EMC_22_GPIO9_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpi2c3_scl: IOMUXC_GPIO_EMC_22_LPI2C3_SCL { + pinmux = <0x401f806c 2 0x401f84dc 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_qtimer2_timer3: IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 { + pinmux = <0x401f806c 4 0x401f8578 0 0x401f825c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_ba1: IOMUXC_GPIO_EMC_22_SEMC_BA1 { + pinmux = <0x401f806c 0 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_enet_rx_en: IOMUXC_GPIO_EMC_23_ENET_RX_EN { + pinmux = <0x401f8070 3 0x401f843c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwma0: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA0 { + pinmux = <0x401f8070 1 0x401f8458 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio4_io23: IOMUXC_GPIO_EMC_23_GPIO4_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio9_io23: IOMUXC_GPIO_EMC_23_GPIO9_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpt1_capture2: IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 { + pinmux = <0x401f8070 4 0x401f875c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart5_tx: IOMUXC_GPIO_EMC_23_LPUART5_TX { + pinmux = <0x401f8070 2 0x401f854c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr10: IOMUXC_GPIO_EMC_23_SEMC_ADDR10 { + pinmux = <0x401f8070 0 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_enet_tx_en: IOMUXC_GPIO_EMC_24_ENET_TX_EN { + pinmux = <0x401f8074 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB0 { + pinmux = <0x401f8074 1 0x401f8468 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio4_io24: IOMUXC_GPIO_EMC_24_GPIO4_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio9_io24: IOMUXC_GPIO_EMC_24_GPIO9_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpt1_capture1: IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 { + pinmux = <0x401f8074 4 0x401f8758 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart5_rx: IOMUXC_GPIO_EMC_24_LPUART5_RX { + pinmux = <0x401f8074 2 0x401f8548 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_cas: IOMUXC_GPIO_EMC_24_SEMC_CAS { + pinmux = <0x401f8074 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_ref_clk: IOMUXC_GPIO_EMC_25_ENET_REF_CLK { + pinmux = <0x401f8078 4 0x401f842c 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_tx_clk: IOMUXC_GPIO_EMC_25_ENET_TX_CLK { + pinmux = <0x401f8078 3 0x401f8448 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwma1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA1 { + pinmux = <0x401f8078 1 0x401f845c 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio4_io25: IOMUXC_GPIO_EMC_25_GPIO4_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio9_io25: IOMUXC_GPIO_EMC_25_GPIO9_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart6_tx: IOMUXC_GPIO_EMC_25_LPUART6_TX { + pinmux = <0x401f8078 2 0x401f8554 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_ras: IOMUXC_GPIO_EMC_25_SEMC_RAS { + pinmux = <0x401f8078 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_enet_rx_er: IOMUXC_GPIO_EMC_26_ENET_RX_ER { + pinmux = <0x401f807c 3 0x401f8440 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio12: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 { + pinmux = <0x401f807c 4 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB1 { + pinmux = <0x401f807c 1 0x401f846c 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio4_io26: IOMUXC_GPIO_EMC_26_GPIO4_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio9_io26: IOMUXC_GPIO_EMC_26_GPIO9_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart6_rx: IOMUXC_GPIO_EMC_26_LPUART6_RX { + pinmux = <0x401f807c 2 0x401f8550 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_clk: IOMUXC_GPIO_EMC_26_SEMC_CLK { + pinmux = <0x401f807c 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio13: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8080 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwma2: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA2 { + pinmux = <0x401f8080 1 0x401f8460 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio4_io27: IOMUXC_GPIO_EMC_27_GPIO4_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio9_io27: IOMUXC_GPIO_EMC_27_GPIO9_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpspi1_sck: IOMUXC_GPIO_EMC_27_LPSPI1_SCK { + pinmux = <0x401f8080 3 0x401f84f0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart5_rts_b: IOMUXC_GPIO_EMC_27_LPUART5_RTS_B { + pinmux = <0x401f8080 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_cke: IOMUXC_GPIO_EMC_27_SEMC_CKE { + pinmux = <0x401f8080 0 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexio1_flexio14: IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8084 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB2 { + pinmux = <0x401f8084 1 0x401f8470 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio4_io28: IOMUXC_GPIO_EMC_28_GPIO4_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio9_io28: IOMUXC_GPIO_EMC_28_GPIO9_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpspi1_sdo: IOMUXC_GPIO_EMC_28_LPSPI1_SDO { + pinmux = <0x401f8084 3 0x401f84f8 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpuart5_cts_b: IOMUXC_GPIO_EMC_28_LPUART5_CTS_B { + pinmux = <0x401f8084 2 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_we: IOMUXC_GPIO_EMC_28_SEMC_WE { + pinmux = <0x401f8084 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexio1_flexio15: IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 { + pinmux = <0x401f8088 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm3_pwma0: IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA0 { + pinmux = <0x401f8088 1 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio4_io29: IOMUXC_GPIO_EMC_29_GPIO4_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio9_io29: IOMUXC_GPIO_EMC_29_GPIO9_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpspi1_sdi: IOMUXC_GPIO_EMC_29_LPSPI1_SDI { + pinmux = <0x401f8088 3 0x401f84f4 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpuart6_rts_b: IOMUXC_GPIO_EMC_29_LPUART6_RTS_B { + pinmux = <0x401f8088 2 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cs0: IOMUXC_GPIO_EMC_29_SEMC_CS0 { + pinmux = <0x401f8088 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_csi_data23: IOMUXC_GPIO_EMC_30_CSI_DATA23 { + pinmux = <0x401f808c 4 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_enet2_tx_data0: IOMUXC_GPIO_EMC_30_ENET2_TX_DATA0 { + pinmux = <0x401f808c 8 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm3_pwmb0: IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB0 { + pinmux = <0x401f808c 1 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio4_io30: IOMUXC_GPIO_EMC_30_GPIO4_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio9_io30: IOMUXC_GPIO_EMC_30_GPIO9_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpspi1_pcs0: IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 { + pinmux = <0x401f808c 3 0x401f84ec 1 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart6_cts_b: IOMUXC_GPIO_EMC_30_LPUART6_CTS_B { + pinmux = <0x401f808c 2 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_data08: IOMUXC_GPIO_EMC_30_SEMC_DATA08 { + pinmux = <0x401f808c 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_csi_data22: IOMUXC_GPIO_EMC_31_CSI_DATA22 { + pinmux = <0x401f8090 4 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_enet2_tx_data1: IOMUXC_GPIO_EMC_31_ENET2_TX_DATA1 { + pinmux = <0x401f8090 8 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm3_pwma1: IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA1 { + pinmux = <0x401f8090 1 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio4_io31: IOMUXC_GPIO_EMC_31_GPIO4_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio9_io31: IOMUXC_GPIO_EMC_31_GPIO9_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpspi1_pcs1: IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 { + pinmux = <0x401f8090 3 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart7_tx: IOMUXC_GPIO_EMC_31_LPUART7_TX { + pinmux = <0x401f8090 2 0x401f855c 1 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_data09: IOMUXC_GPIO_EMC_31_SEMC_DATA09 { + pinmux = <0x401f8090 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ccm_pmic_rdy: IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY { + pinmux = <0x401f8094 3 0x401f83fc 4 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_csi_data21: IOMUXC_GPIO_EMC_32_CSI_DATA21 { + pinmux = <0x401f8094 4 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_enet2_tx_en: IOMUXC_GPIO_EMC_32_ENET2_TX_EN { + pinmux = <0x401f8094 8 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_flexpwm3_pwmb1: IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB1 { + pinmux = <0x401f8094 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io18: IOMUXC_GPIO_EMC_32_GPIO3_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio8_io18: IOMUXC_GPIO_EMC_32_GPIO8_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart7_rx: IOMUXC_GPIO_EMC_32_LPUART7_RX { + pinmux = <0x401f8094 2 0x401f8558 1 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data10: IOMUXC_GPIO_EMC_32_SEMC_DATA10 { + pinmux = <0x401f8094 0 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_csi_data20: IOMUXC_GPIO_EMC_33_CSI_DATA20 { + pinmux = <0x401f8098 4 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_enet2_ref_clk2: IOMUXC_GPIO_EMC_33_ENET2_REF_CLK2 { + pinmux = <0x401f8098 9 0x401f870c 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_enet2_tx_clk: IOMUXC_GPIO_EMC_33_ENET2_TX_CLK { + pinmux = <0x401f8098 8 0x401f8728 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_flexpwm3_pwma2: IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA2 { + pinmux = <0x401f8098 1 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io19: IOMUXC_GPIO_EMC_33_GPIO3_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio8_io19: IOMUXC_GPIO_EMC_33_GPIO8_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_rx_data: IOMUXC_GPIO_EMC_33_SAI3_RX_DATA { + pinmux = <0x401f8098 3 0x401f8778 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data11: IOMUXC_GPIO_EMC_33_SEMC_DATA11 { + pinmux = <0x401f8098 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_usdhc1_reset_b: IOMUXC_GPIO_EMC_33_USDHC1_RESET_B { + pinmux = <0x401f8098 2 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_csi_data19: IOMUXC_GPIO_EMC_34_CSI_DATA19 { + pinmux = <0x401f809c 4 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_enet2_rx_er: IOMUXC_GPIO_EMC_34_ENET2_RX_ER { + pinmux = <0x401f809c 8 0x401f8720 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_flexpwm3_pwmb2: IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB2 { + pinmux = <0x401f809c 1 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io20: IOMUXC_GPIO_EMC_34_GPIO3_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio8_io20: IOMUXC_GPIO_EMC_34_GPIO8_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_rx_sync: IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC { + pinmux = <0x401f809c 3 0x401f877c 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data12: IOMUXC_GPIO_EMC_34_SEMC_DATA12 { + pinmux = <0x401f809c 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_usdhc1_vselect: IOMUXC_GPIO_EMC_34_USDHC1_VSELECT { + pinmux = <0x401f809c 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_csi_data18: IOMUXC_GPIO_EMC_35_CSI_DATA18 { + pinmux = <0x401f80a0 4 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_enet2_rx_data0: IOMUXC_GPIO_EMC_35_ENET2_RX_DATA0 { + pinmux = <0x401f80a0 8 0x401f8714 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io21: IOMUXC_GPIO_EMC_35_GPIO3_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio8_io21: IOMUXC_GPIO_EMC_35_GPIO8_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpt1_compare1: IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 { + pinmux = <0x401f80a0 2 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_sai3_rx_bclk: IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK { + pinmux = <0x401f80a0 3 0x401f8774 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data13: IOMUXC_GPIO_EMC_35_SEMC_DATA13 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc1_cd_b: IOMUXC_GPIO_EMC_35_USDHC1_CD_B { + pinmux = <0x401f80a0 6 0x401f85d4 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_in18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_IN18 { + pinmux = <0x401f80a0 1 0x401f8630 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80a0 1 0x401f8630 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_csi_data17: IOMUXC_GPIO_EMC_36_CSI_DATA17 { + pinmux = <0x401f80a4 4 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_enet2_rx_data1: IOMUXC_GPIO_EMC_36_ENET2_RX_DATA1 { + pinmux = <0x401f80a4 8 0x401f8718 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexcan3_tx: IOMUXC_GPIO_EMC_36_FLEXCAN3_TX { + pinmux = <0x401f80a4 9 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io22: IOMUXC_GPIO_EMC_36_GPIO3_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio8_io22: IOMUXC_GPIO_EMC_36_GPIO8_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpt1_compare2: IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 { + pinmux = <0x401f80a4 2 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_sai3_tx_data: IOMUXC_GPIO_EMC_36_SAI3_TX_DATA { + pinmux = <0x401f80a4 3 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data14: IOMUXC_GPIO_EMC_36_SEMC_DATA14 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 6 0x401f85d8 1 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_xbar1_xbar_in22: IOMUXC_GPIO_EMC_36_XBAR1_XBAR_IN22 { + pinmux = <0x401f80a4 1 0x401f8638 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_csi_data16: IOMUXC_GPIO_EMC_37_CSI_DATA16 { + pinmux = <0x401f80a8 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_enet2_rx_en: IOMUXC_GPIO_EMC_37_ENET2_RX_EN { + pinmux = <0x401f80a8 8 0x401f871c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexcan3_rx: IOMUXC_GPIO_EMC_37_FLEXCAN3_RX { + pinmux = <0x401f80a8 9 0x401f878c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io23: IOMUXC_GPIO_EMC_37_GPIO3_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio8_io23: IOMUXC_GPIO_EMC_37_GPIO8_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpt1_compare3: IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 { + pinmux = <0x401f80a8 2 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_sai3_mclk: IOMUXC_GPIO_EMC_37_SAI3_MCLK { + pinmux = <0x401f80a8 3 0x401f8770 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data15: IOMUXC_GPIO_EMC_37_SEMC_DATA15 { + pinmux = <0x401f80a8 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc2_wp: IOMUXC_GPIO_EMC_37_USDHC2_WP { + pinmux = <0x401f80a8 6 0x401f8608 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_xbar1_xbar_in23: IOMUXC_GPIO_EMC_37_XBAR1_XBAR_IN23 { + pinmux = <0x401f80a8 1 0x401f863c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_csi_field: IOMUXC_GPIO_EMC_38_CSI_FIELD { + pinmux = <0x401f80ac 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_enet2_mdc: IOMUXC_GPIO_EMC_38_ENET2_MDC { + pinmux = <0x401f80ac 8 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm1_pwma3: IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA3 { + pinmux = <0x401f80ac 1 0x401f8454 2 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io24: IOMUXC_GPIO_EMC_38_GPIO3_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio8_io24: IOMUXC_GPIO_EMC_38_GPIO8_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart8_tx: IOMUXC_GPIO_EMC_38_LPUART8_TX { + pinmux = <0x401f80ac 2 0x401f8564 2 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_sai3_tx_bclk: IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK { + pinmux = <0x401f80ac 3 0x401f8780 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_dm1: IOMUXC_GPIO_EMC_38_SEMC_DM1 { + pinmux = <0x401f80ac 0 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc2_vselect: IOMUXC_GPIO_EMC_38_USDHC2_VSELECT { + pinmux = <0x401f80ac 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_enet2_mdio: IOMUXC_GPIO_EMC_39_ENET2_MDIO { + pinmux = <0x401f80b0 8 0x401f8710 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB3 { + pinmux = <0x401f80b0 1 0x401f8464 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io25: IOMUXC_GPIO_EMC_39_GPIO3_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio8_io25: IOMUXC_GPIO_EMC_39_GPIO8_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart8_rx: IOMUXC_GPIO_EMC_39_LPUART8_RX { + pinmux = <0x401f80b0 2 0x401f8560 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_sai3_tx_sync: IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC { + pinmux = <0x401f80b0 3 0x401f8784 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs: IOMUXC_GPIO_EMC_39_SEMC_DQS { + pinmux = <0x401f80b0 0 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs4: IOMUXC_GPIO_EMC_39_SEMC_DQS4 { + pinmux = <0x401f80b0 9 0x401f8788 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usdhc2_cd_b: IOMUXC_GPIO_EMC_39_USDHC2_CD_B { + pinmux = <0x401f80b0 6 0x401f85e0 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdc: IOMUXC_GPIO_EMC_40_ENET_MDC { + pinmux = <0x401f80b4 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io26: IOMUXC_GPIO_EMC_40_GPIO3_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio8_io26: IOMUXC_GPIO_EMC_40_GPIO8_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt2_capture2: IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 { + pinmux = <0x401f80b4 1 0x401f8768 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_lpspi1_pcs2: IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 { + pinmux = <0x401f80b4 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_clk5: IOMUXC_GPIO_EMC_40_SEMC_CLK5 { + pinmux = <0x401f80b4 9 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_rdy: IOMUXC_GPIO_EMC_40_SEMC_RDY { + pinmux = <0x401f80b4 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usb_otg2_oc: IOMUXC_GPIO_EMC_40_USB_OTG2_OC { + pinmux = <0x401f80b4 3 0x401f85cc 1 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usdhc2_reset_b: IOMUXC_GPIO_EMC_40_USDHC2_RESET_B { + pinmux = <0x401f80b4 6 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdio: IOMUXC_GPIO_EMC_41_ENET_MDIO { + pinmux = <0x401f80b8 4 0x401f8430 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io27: IOMUXC_GPIO_EMC_41_GPIO3_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio8_io27: IOMUXC_GPIO_EMC_41_GPIO8_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt2_capture1: IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 { + pinmux = <0x401f80b8 1 0x401f8764 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_lpspi1_pcs3: IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 { + pinmux = <0x401f80b8 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_csx0: IOMUXC_GPIO_EMC_41_SEMC_CSX0 { + pinmux = <0x401f80b8 0 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usb_otg2_pwr: IOMUXC_GPIO_EMC_41_USB_OTG2_PWR { + pinmux = <0x401f80b8 3 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usdhc1_vselect: IOMUXC_GPIO_EMC_41_USDHC1_VSELECT { + pinmux = <0x401f80b8 6 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_enet2_tx_en: IOMUXC_GPIO_SD_B0_00_ENET2_TX_EN { + pinmux = <0x401f81bc 8 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexpwm1_pwma0: IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA0 { + pinmux = <0x401f81bc 1 0x401f8458 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f81bc 6 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io12: IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio8_io12: IOMUXC_GPIO_SD_B0_00_GPIO8_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f81bc 2 0x401f84dc 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpspi1_sck: IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK { + pinmux = <0x401f81bc 4 0x401f84f0 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_semc_dqs4: IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 { + pinmux = <0x401f81bc 9 0x401f8788 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_cmd: IOMUXC_GPIO_SD_B0_00_USDHC1_CMD { + pinmux = <0x401f81bc 0 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN04 { + pinmux = <0x401f81bc 3 0x401f8614 1 0x401f83ac>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f81bc 3 0x401f8614 1 0x401f83ac>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_enet2_ref_clk2: IOMUXC_GPIO_SD_B0_01_ENET2_REF_CLK2 { + pinmux = <0x401f81c0 9 0x401f870c 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_enet2_tx_clk: IOMUXC_GPIO_SD_B0_01_ENET2_TX_CLK { + pinmux = <0x401f81c0 8 0x401f8728 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexpwm1_pwmb0: IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB0 { + pinmux = <0x401f81c0 1 0x401f8468 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f81c0 6 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io13: IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio8_io13: IOMUXC_GPIO_SD_B0_01_GPIO8_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f81c0 2 0x401f84e0 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 { + pinmux = <0x401f81c0 4 0x401f84ec 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_clk: IOMUXC_GPIO_SD_B0_01_USDHC1_CLK { + pinmux = <0x401f81c0 0 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN05 { + pinmux = <0x401f81c0 3 0x401f8618 1 0x401f83b0>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f81c0 3 0x401f8618 1 0x401f83b0>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_enet2_rx_er: IOMUXC_GPIO_SD_B0_02_ENET2_RX_ER { + pinmux = <0x401f81c4 8 0x401f8720 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_flexpwm1_pwma1: IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA1 { + pinmux = <0x401f81c4 1 0x401f845c 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io14: IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio8_io14: IOMUXC_GPIO_SD_B0_02_GPIO8_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sdo: IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO { + pinmux = <0x401f81c4 4 0x401f84f8 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart8_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B { + pinmux = <0x401f81c4 2 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_semc_clk5: IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 { + pinmux = <0x401f81c4 9 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_data0: IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 { + pinmux = <0x401f81c4 0 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN06 { + pinmux = <0x401f81c4 3 0x401f861c 1 0x401f83b4>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f81c4 3 0x401f861c 1 0x401f83b4>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_enet2_rx_data0: IOMUXC_GPIO_SD_B0_03_ENET2_RX_DATA0 { + pinmux = <0x401f81c8 8 0x401f8714 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_flexpwm1_pwmb1: IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB1 { + pinmux = <0x401f81c8 1 0x401f846c 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io15: IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio8_io15: IOMUXC_GPIO_SD_B0_03_GPIO8_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_sdi: IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI { + pinmux = <0x401f81c8 4 0x401f84f4 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart8_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B { + pinmux = <0x401f81c8 2 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_semc_clk6: IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 { + pinmux = <0x401f81c8 9 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_data1: IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 { + pinmux = <0x401f81c8 0 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_in07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_IN07 { + pinmux = <0x401f81c8 3 0x401f8620 1 0x401f83b8>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_inout07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f81c8 3 0x401f8620 1 0x401f83b8>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_ccm_clko1: IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 { + pinmux = <0x401f81cc 6 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_enet2_rx_data1: IOMUXC_GPIO_SD_B0_04_ENET2_RX_DATA1 { + pinmux = <0x401f81cc 8 0x401f8718 1 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexpwm1_pwma2: IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA2 { + pinmux = <0x401f81cc 1 0x401f8460 1 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f81cc 4 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io16: IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio8_io16: IOMUXC_GPIO_SD_B0_04_GPIO8_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart8_tx: IOMUXC_GPIO_SD_B0_04_LPUART8_TX { + pinmux = <0x401f81cc 2 0x401f8564 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data2: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 { + pinmux = <0x401f81cc 0 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_in08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_IN08 { + pinmux = <0x401f81cc 3 0x401f8624 1 0x401f83bc>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_inout08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f81cc 3 0x401f8624 1 0x401f83bc>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_ccm_clko2: IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 { + pinmux = <0x401f81d0 6 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_enet2_rx_en: IOMUXC_GPIO_SD_B0_05_ENET2_RX_EN { + pinmux = <0x401f81d0 8 0x401f871c 1 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexpwm1_pwmb2: IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB2 { + pinmux = <0x401f81d0 1 0x401f8470 1 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f81d0 4 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io17: IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio8_io17: IOMUXC_GPIO_SD_B0_05_GPIO8_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart8_rx: IOMUXC_GPIO_SD_B0_05_LPUART8_RX { + pinmux = <0x401f81d0 2 0x401f8560 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data3: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 { + pinmux = <0x401f81d0 0 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_in09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_IN09 { + pinmux = <0x401f81d0 3 0x401f8628 1 0x401f83c0>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_inout09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f81d0 3 0x401f8628 1 0x401f83c0>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f81d4 2 0x401f8454 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f81d4 1 0x401f84c4 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io00: IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio8_io00: IOMUXC_GPIO_SD_B1_00_GPIO8_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart4_tx: IOMUXC_GPIO_SD_B1_00_LPUART4_TX { + pinmux = <0x401f81d4 4 0x401f8544 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai1_tx_data3: IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA3 { + pinmux = <0x401f81d4 3 0x401f8598 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai3_rx_data: IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA { + pinmux = <0x401f81d4 8 0x401f8778 1 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data3: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 { + pinmux = <0x401f81d4 0 0x401f85f4 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f81d8 2 0x401f8464 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_data2: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 { + pinmux = <0x401f81d8 1 0x401f84c0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io01: IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio8_io01: IOMUXC_GPIO_SD_B1_01_GPIO8_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart4_rx: IOMUXC_GPIO_SD_B1_01_LPUART4_RX { + pinmux = <0x401f81d8 4 0x401f8540 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai1_tx_data2: IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA2 { + pinmux = <0x401f81d8 3 0x401f859c 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai3_tx_data: IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA { + pinmux = <0x401f81d8 8 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data2: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 { + pinmux = <0x401f81d8 0 0x401f85f0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_wait: IOMUXC_GPIO_SD_B1_02_CCM_WAIT { + pinmux = <0x401f81dc 6 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexcan1_tx: IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX { + pinmux = <0x401f81dc 4 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f81dc 2 0x401f8474 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data1: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 { + pinmux = <0x401f81dc 1 0x401f84bc 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io02: IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio8_io02: IOMUXC_GPIO_SD_B1_02_GPIO8_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai1_tx_data1: IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA1 { + pinmux = <0x401f81dc 3 0x401f85a0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai3_tx_sync: IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC { + pinmux = <0x401f81dc 8 0x401f8784 1 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_data1: IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 { + pinmux = <0x401f81dc 0 0x401f85ec 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_03_CCM_PMIC_RDY { + pinmux = <0x401f81e0 6 0x401f83fc 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexcan1_rx: IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX { + pinmux = <0x401f81e0 4 0x401f844c 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f81e0 2 0x401f8484 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data0: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 { + pinmux = <0x401f81e0 1 0x401f84b8 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io03: IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio8_io03: IOMUXC_GPIO_SD_B1_03_GPIO8_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai1_mclk: IOMUXC_GPIO_SD_B1_03_SAI1_MCLK { + pinmux = <0x401f81e0 3 0x401f858c 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK { + pinmux = <0x401f81e0 8 0x401f8780 1 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_data0: IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 { + pinmux = <0x401f81e0 0 0x401f85e8 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_stop: IOMUXC_GPIO_SD_B1_04_CCM_STOP { + pinmux = <0x401f81e4 6 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI_A_SS1_B { + pinmux = <0x401f81e4 4 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK { + pinmux = <0x401f81e4 1 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io04: IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio8_io04: IOMUXC_GPIO_SD_B1_04_GPIO8_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_lpi2c1_scl: IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL { + pinmux = <0x401f81e4 2 0x401f84cc 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai1_rx_sync: IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f81e4 3 0x401f85a4 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai3_mclk: IOMUXC_GPIO_SD_B1_04_SAI3_MCLK { + pinmux = <0x401f81e4 8 0x401f8770 1 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_clk: IOMUXC_GPIO_SD_B1_04_USDHC2_CLK { + pinmux = <0x401f81e4 0 0x401f85dc 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f81e8 1 0x401f84a4 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f81e8 4 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io05: IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio8_io05: IOMUXC_GPIO_SD_B1_05_GPIO8_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_lpi2c1_sda: IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA { + pinmux = <0x401f81e8 2 0x401f84d0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai1_rx_bclk: IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK { + pinmux = <0x401f81e8 3 0x401f8590 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_rx_sync: IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC { + pinmux = <0x401f81e8 8 0x401f877c 1 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_cmd: IOMUXC_GPIO_SD_B1_05_USDHC2_CMD { + pinmux = <0x401f81e8 0 0x401f85e4 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B { + pinmux = <0x401f81ec 1 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io06: IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio8_io06: IOMUXC_GPIO_SD_B1_06_GPIO8_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f81ec 4 0x401f84fc 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpuart7_cts_b: IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B { + pinmux = <0x401f81ec 2 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai1_rx_data0: IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA0 { + pinmux = <0x401f81ec 3 0x401f8594 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK { + pinmux = <0x401f81ec 8 0x401f8774 1 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B { + pinmux = <0x401f81ec 0 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f81f0 1 0x401f84c8 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io07: IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio8_io07: IOMUXC_GPIO_SD_B1_07_GPIO8_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f81f0 4 0x401f8500 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpuart7_rts_b: IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B { + pinmux = <0x401f81f0 2 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai1_tx_data0: IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA0 { + pinmux = <0x401f81f0 3 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_semc_csx1: IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 { + pinmux = <0x401f81f0 0 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f81f4 1 0x401f84a8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io08: IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio8_io08: IOMUXC_GPIO_SD_B1_08_GPIO8_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f81f4 4 0x401f8508 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpuart7_tx: IOMUXC_GPIO_SD_B1_08_LPUART7_TX { + pinmux = <0x401f81f4 2 0x401f855c 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai1_tx_bclk: IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK { + pinmux = <0x401f81f4 3 0x401f85a8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_semc_csx2: IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 { + pinmux = <0x401f81f4 6 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f81f4 0 0x401f85f8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data1: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 { + pinmux = <0x401f81f8 1 0x401f84ac 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io09: IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio8_io09: IOMUXC_GPIO_SD_B1_09_GPIO8_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f81f8 4 0x401f8504 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpuart7_rx: IOMUXC_GPIO_SD_B1_09_LPUART7_RX { + pinmux = <0x401f81f8 2 0x401f8558 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai1_tx_sync: IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC { + pinmux = <0x401f81f8 3 0x401f85ac 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f81f8 0 0x401f85fc 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data2: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 { + pinmux = <0x401f81fc 1 0x401f84b0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io10: IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio8_io10: IOMUXC_GPIO_SD_B1_10_GPIO8_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpi2c2_sda: IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA { + pinmux = <0x401f81fc 3 0x401f84d8 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f81fc 4 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpuart2_rx: IOMUXC_GPIO_SD_B1_10_LPUART2_RX { + pinmux = <0x401f81fc 2 0x401f852c 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f81fc 0 0x401f8600 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_data3: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 { + pinmux = <0x401f8200 1 0x401f84b4 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io11: IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio8_io11: IOMUXC_GPIO_SD_B1_11_GPIO8_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpi2c2_scl: IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL { + pinmux = <0x401f8200 3 0x401f84d4 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8200 4 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpuart2_tx: IOMUXC_GPIO_SD_B1_11_LPUART2_TX { + pinmux = <0x401f8200 2 0x401f8530 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8200 0 0x401f8604 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_ccm_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ { + pinmux = <0x400a8008 0 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_gpio5_io02: IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 { + pinmux = <0x400a8008 5 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x0 0 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1064cvl5b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1064cvl5b-pinctrl.dtsi new file mode 100644 index 000000000..451006b1b --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1064cvl5b-pinctrl.dtsi @@ -0,0 +1,3925 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1064CVL5B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_acmp1_in4: IOMUXC_GPIO_AD_B0_00_ACMP1_IN4 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA3 { + pinmux = <0x401f80bc 0 0x401f8474 2 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + gpr = <0x400ac068 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio6_io00: IOMUXC_GPIO_AD_B0_00_GPIO6_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + gpr = <0x400ac068 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_lpi2c1_scls: IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS { + pinmux = <0x401f80bc 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_lpspi3_sck: IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK { + pinmux = <0x401f80bc 7 0x401f8510 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_ref_32k_out: IOMUXC_GPIO_AD_B0_00_REF_32K_OUT { + pinmux = <0x401f80bc 2 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_usb_otg2_id: IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID { + pinmux = <0x401f80bc 3 0x401f83f8 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_usdhc1_reset_b: IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B { + pinmux = <0x401f80bc 6 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_xbar1_xbar_in14: IOMUXC_GPIO_AD_B0_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f80bc 1 0x401f8644 0 0x401f82ac>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_xbar1_xbar_inout14: IOMUXC_GPIO_AD_B0_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f80bc 1 0x401f8644 0 0x401f82ac>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_acmp2_in4: IOMUXC_GPIO_AD_B0_01_ACMP2_IN4 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_ewm_out_b: IOMUXC_GPIO_AD_B0_01_EWM_OUT_B { + pinmux = <0x401f80c0 6 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_flexpwm2_pwmb3: IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB3 { + pinmux = <0x401f80c0 0 0x401f8484 2 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + gpr = <0x400ac068 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio6_io01: IOMUXC_GPIO_AD_B0_01_GPIO6_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + gpr = <0x400ac068 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_lpi2c1_sdas: IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS { + pinmux = <0x401f80c0 4 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_lpspi3_sdo: IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO { + pinmux = <0x401f80c0 7 0x401f8518 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_ref_24m_out: IOMUXC_GPIO_AD_B0_01_REF_24M_OUT { + pinmux = <0x401f80c0 2 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_usb_otg1_id: IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID { + pinmux = <0x401f80c0 3 0x401f83f4 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_xbar1_xbar_in15: IOMUXC_GPIO_AD_B0_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f80c0 1 0x401f8648 0 0x401f82b0>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_xbar1_xbar_inout15: IOMUXC_GPIO_AD_B0_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f80c0 1 0x401f8648 0 0x401f82b0>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_acmp3_in4: IOMUXC_GPIO_AD_B0_02_ACMP3_IN4 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_flexcan2_tx: IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX { + pinmux = <0x401f80c4 0 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_flexpwm1_pwmx0: IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX0 { + pinmux = <0x401f80c4 4 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + gpr = <0x400ac068 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio6_io02: IOMUXC_GPIO_AD_B0_02_GPIO6_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + gpr = <0x400ac068 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpi2c1_hreq: IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ { + pinmux = <0x401f80c4 6 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpspi3_sdi: IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI { + pinmux = <0x401f80c4 7 0x401f8514 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpuart6_tx: IOMUXC_GPIO_AD_B0_02_LPUART6_TX { + pinmux = <0x401f80c4 2 0x401f8554 1 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR { + pinmux = <0x401f80c4 3 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_xbar1_xbar_in16: IOMUXC_GPIO_AD_B0_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f80c4 1 0x401f864c 0 0x401f82b4>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_xbar1_xbar_inout16: IOMUXC_GPIO_AD_B0_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f80c4 1 0x401f864c 0 0x401f82b4>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_acmp4_in4: IOMUXC_GPIO_AD_B0_03_ACMP4_IN4 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_flexcan2_rx: IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX { + pinmux = <0x401f80c8 0 0x401f8450 1 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_flexpwm1_pwmx1: IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX1 { + pinmux = <0x401f80c8 4 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + gpr = <0x400ac068 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio6_io03: IOMUXC_GPIO_AD_B0_03_GPIO6_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + gpr = <0x400ac068 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_lpspi3_pcs0: IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 { + pinmux = <0x401f80c8 7 0x401f850c 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_lpuart6_rx: IOMUXC_GPIO_AD_B0_03_LPUART6_RX { + pinmux = <0x401f80c8 2 0x401f8550 1 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ref_24m_out: IOMUXC_GPIO_AD_B0_03_REF_24M_OUT { + pinmux = <0x401f80c8 6 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 3 0x401f85d0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f80c8 1 0x401f862c 1 0x401f82b8>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80c8 1 0x401f862c 1 0x401f82b8>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_csi_data09: IOMUXC_GPIO_AD_B0_04_CSI_DATA09 { + pinmux = <0x401f80cc 4 0x401f841c 1 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_tx_data3: IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA3 { + pinmux = <0x401f80cc 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio6_io04: IOMUXC_GPIO_AD_B0_04_GPIO6_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_lpspi3_pcs1: IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 { + pinmux = <0x401f80cc 7 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_mqs_right: IOMUXC_GPIO_AD_B0_04_MQS_RIGHT { + pinmux = <0x401f80cc 1 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_pit_trigger0: IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER0 { + pinmux = <0x401f80cc 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_sai2_tx_sync: IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC { + pinmux = <0x401f80cc 3 0x401f85c4 1 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_src_boot_mode0: IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE0 { + pinmux = <0x401f80cc 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_csi_data08: IOMUXC_GPIO_AD_B0_05_CSI_DATA08 { + pinmux = <0x401f80d0 4 0x401f8418 1 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_tx_data2: IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA2 { + pinmux = <0x401f80d0 2 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio6_io05: IOMUXC_GPIO_AD_B0_05_GPIO6_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_lpspi3_pcs2: IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 { + pinmux = <0x401f80d0 7 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_mqs_left: IOMUXC_GPIO_AD_B0_05_MQS_LEFT { + pinmux = <0x401f80d0 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_sai2_tx_bclk: IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f80d0 3 0x401f85c0 1 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_src_boot_mode1: IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE1 { + pinmux = <0x401f80d0 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_IN17 { + pinmux = <0x401f80d0 6 0x401f862c 2 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80d0 6 0x401f862c 2 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_csi_data07: IOMUXC_GPIO_AD_B0_06_CSI_DATA07 { + pinmux = <0x401f80d4 4 0x401f8414 1 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_enet_rx_clk: IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK { + pinmux = <0x401f80d4 2 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio6_io06: IOMUXC_GPIO_AD_B0_06_GPIO6_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpt2_compare1: IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 { + pinmux = <0x401f80d4 1 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_jtag_tms: IOMUXC_GPIO_AD_B0_06_JTAG_TMS { + pinmux = <0x401f80d4 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpspi3_pcs3: IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 { + pinmux = <0x401f80d4 7 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_sai2_rx_bclk: IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK { + pinmux = <0x401f80d4 3 0x401f85b4 1 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_in18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_IN18 { + pinmux = <0x401f80d4 6 0x401f8630 1 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_inout18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80d4 6 0x401f8630 1 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_csi_data06: IOMUXC_GPIO_AD_B0_07_CSI_DATA06 { + pinmux = <0x401f80d8 4 0x401f8410 1 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_1588_event3_out: IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT { + pinmux = <0x401f80d8 7 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_tx_er: IOMUXC_GPIO_AD_B0_07_ENET_TX_ER { + pinmux = <0x401f80d8 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio6_io07: IOMUXC_GPIO_AD_B0_07_GPIO6_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpt2_compare2: IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 { + pinmux = <0x401f80d8 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_jtag_tck: IOMUXC_GPIO_AD_B0_07_JTAG_TCK { + pinmux = <0x401f80d8 0 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_sai2_rx_sync: IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC { + pinmux = <0x401f80d8 3 0x401f85bc 1 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_in19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_IN19 { + pinmux = <0x401f80d8 6 0x401f8654 1 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_inout19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80d8 6 0x401f8654 1 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_csi_data05: IOMUXC_GPIO_AD_B0_08_CSI_DATA05 { + pinmux = <0x401f80dc 4 0x401f840c 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_1588_event3_in: IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN { + pinmux = <0x401f80dc 7 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_rx_data3: IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA3 { + pinmux = <0x401f80dc 2 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio6_io08: IOMUXC_GPIO_AD_B0_08_GPIO6_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpt2_compare3: IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 { + pinmux = <0x401f80dc 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_jtag_mod: IOMUXC_GPIO_AD_B0_08_JTAG_MOD { + pinmux = <0x401f80dc 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_sai2_rx_data: IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA { + pinmux = <0x401f80dc 3 0x401f85b8 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_xbar1_xbar_in20: IOMUXC_GPIO_AD_B0_08_XBAR1_XBAR_IN20 { + pinmux = <0x401f80dc 6 0x401f8634 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_csi_data04: IOMUXC_GPIO_AD_B0_09_CSI_DATA04 { + pinmux = <0x401f80e0 4 0x401f8408 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data2: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA2 { + pinmux = <0x401f80e0 2 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA3 { + pinmux = <0x401f80e0 1 0x401f8474 3 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio6_io09: IOMUXC_GPIO_AD_B0_09_GPIO6_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpt2_clk: IOMUXC_GPIO_AD_B0_09_GPT2_CLK { + pinmux = <0x401f80e0 7 0x401f876c 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_jtag_tdi: IOMUXC_GPIO_AD_B0_09_JTAG_TDI { + pinmux = <0x401f80e0 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_sai2_tx_data: IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA { + pinmux = <0x401f80e0 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_semc_dqs4: IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 { + pinmux = <0x401f80e0 9 0x401f8788 2 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_xbar1_xbar_in21: IOMUXC_GPIO_AD_B0_09_XBAR1_XBAR_IN21 { + pinmux = <0x401f80e0 6 0x401f8658 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_swo: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO { + pinmux = <0x401f80e4 9 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_csi_data03: IOMUXC_GPIO_AD_B0_10_CSI_DATA03 { + pinmux = <0x401f80e4 4 0x401f8404 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80e4 7 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_crs: IOMUXC_GPIO_AD_B0_10_ENET_CRS { + pinmux = <0x401f80e4 2 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexcan3_tx: IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX { + pinmux = <0x401f80e4 8 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm1_pwma3: IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA3 { + pinmux = <0x401f80e4 1 0x401f8454 3 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio6_io10: IOMUXC_GPIO_AD_B0_10_GPIO6_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_jtag_tdo: IOMUXC_GPIO_AD_B0_10_JTAG_TDO { + pinmux = <0x401f80e4 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_sai2_mclk: IOMUXC_GPIO_AD_B0_10_SAI2_MCLK { + pinmux = <0x401f80e4 3 0x401f85b0 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_xbar1_xbar_in22: IOMUXC_GPIO_AD_B0_10_XBAR1_XBAR_IN22 { + pinmux = <0x401f80e4 6 0x401f8638 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_csi_data02: IOMUXC_GPIO_AD_B0_11_CSI_DATA02 { + pinmux = <0x401f80e8 4 0x401f8400 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN { + pinmux = <0x401f80e8 7 0x401f8444 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_col: IOMUXC_GPIO_AD_B0_11_ENET_COL { + pinmux = <0x401f80e8 2 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexcan3_rx: IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX { + pinmux = <0x401f80e8 8 0x401f878c 2 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB3 { + pinmux = <0x401f80e8 1 0x401f8464 3 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio6_io11: IOMUXC_GPIO_AD_B0_11_GPIO6_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_jtag_trstb: IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB { + pinmux = <0x401f80e8 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_semc_clk6: IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 { + pinmux = <0x401f80e8 9 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_wdog1_b: IOMUXC_GPIO_AD_B0_11_WDOG1_B { + pinmux = <0x401f80e8 3 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_xbar1_xbar_in23: IOMUXC_GPIO_AD_B0_11_XBAR1_XBAR_IN23 { + pinmux = <0x401f80e8 6 0x401f863c 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in1: IOMUXC_GPIO_AD_B0_12_ADC1_IN1 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_nmi: IOMUXC_GPIO_AD_B0_12_ARM_NMI { + pinmux = <0x401f80ec 7 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_12_CCM_PMIC_RDY { + pinmux = <0x401f80ec 1 0x401f83fc 1 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_1588_event1_out: IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT { + pinmux = <0x401f80ec 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm1_pwmx2: IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX2 { + pinmux = <0x401f80ec 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio6_io12: IOMUXC_GPIO_AD_B0_12_GPIO6_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpi2c4_scl: IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL { + pinmux = <0x401f80ec 0 0x401f84e4 1 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart1_tx: IOMUXC_GPIO_AD_B0_12_LPUART1_TX { + pinmux = <0x401f80ec 2 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_wdog2_b: IOMUXC_GPIO_AD_B0_12_WDOG2_B { + pinmux = <0x401f80ec 3 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_acmp1_in2: IOMUXC_GPIO_AD_B0_13_ACMP1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc1_in2: IOMUXC_GPIO_AD_B0_13_ADC1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_1588_event1_in: IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN { + pinmux = <0x401f80f0 6 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ewm_out_b: IOMUXC_GPIO_AD_B0_13_EWM_OUT_B { + pinmux = <0x401f80f0 3 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm1_pwmx3: IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX3 { + pinmux = <0x401f80f0 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio6_io13: IOMUXC_GPIO_AD_B0_13_GPIO6_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpt1_clk: IOMUXC_GPIO_AD_B0_13_GPT1_CLK { + pinmux = <0x401f80f0 1 0x401f8760 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpi2c4_sda: IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA { + pinmux = <0x401f80f0 0 0x401f84e8 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart1_rx: IOMUXC_GPIO_AD_B0_13_LPUART1_RX { + pinmux = <0x401f80f0 2 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ref_24m_out: IOMUXC_GPIO_AD_B0_13_REF_24M_OUT { + pinmux = <0x401f80f0 7 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in2: IOMUXC_GPIO_AD_B0_14_ACMP2_IN2 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in3: IOMUXC_GPIO_AD_B0_14_ADC1_IN3 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_csi_vsync: IOMUXC_GPIO_AD_B0_14_CSI_VSYNC { + pinmux = <0x401f80f4 4 0x401f8428 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80f4 3 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan3_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX { + pinmux = <0x401f80f4 8 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio6_io14: IOMUXC_GPIO_AD_B0_14_GPIO6_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B { + pinmux = <0x401f80f4 2 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_usb_otg2_oc: IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC { + pinmux = <0x401f80f4 0 0x401f85cc 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_xbar1_xbar_in24: IOMUXC_GPIO_AD_B0_14_XBAR1_XBAR_IN24 { + pinmux = <0x401f80f4 1 0x401f8640 1 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in2: IOMUXC_GPIO_AD_B0_15_ACMP3_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in4: IOMUXC_GPIO_AD_B0_15_ADC1_IN4 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_csi_hsync: IOMUXC_GPIO_AD_B0_15_CSI_HSYNC { + pinmux = <0x401f80f8 4 0x401f8420 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f80f8 3 0x401f8444 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 6 0x401f8450 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan3_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX { + pinmux = <0x401f80f8 8 0x401f878c 1 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio6_io15: IOMUXC_GPIO_AD_B0_15_GPIO6_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B { + pinmux = <0x401f80f8 2 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_usb_otg2_pwr: IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR { + pinmux = <0x401f80f8 0 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb: IOMUXC_GPIO_AD_B0_15_WDOG1_RST_B_DEB { + pinmux = <0x401f80f8 7 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_xbar1_xbar_in25: IOMUXC_GPIO_AD_B0_15_XBAR1_XBAR_IN25 { + pinmux = <0x401f80f8 1 0x401f8650 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp4_in2: IOMUXC_GPIO_AD_B1_00_ACMP4_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc1_in5: IOMUXC_GPIO_AD_B1_00_ADC1_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc2_in5: IOMUXC_GPIO_AD_B1_00_ADC2_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_enet2_1588_event0_out: IOMUXC_GPIO_AD_B1_00_ENET2_1588_EVENT0_OUT { + pinmux = <0x401f80fc 8 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio3_flexio00: IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 { + pinmux = <0x401f80fc 9 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio6_io16: IOMUXC_GPIO_AD_B1_00_GPIO6_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_kpp_row7: IOMUXC_GPIO_AD_B1_00_KPP_ROW7 { + pinmux = <0x401f80fc 7 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpi2c1_scl: IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL { + pinmux = <0x401f80fc 3 0x401f84cc 1 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B { + pinmux = <0x401f80fc 2 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_qtimer3_timer0: IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 { + pinmux = <0x401f80fc 1 0x401f857c 1 0x401f82ec>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usb_otg2_id: IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID { + pinmux = <0x401f80fc 0 0x401f83f8 1 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usdhc1_wp: IOMUXC_GPIO_AD_B1_00_USDHC1_WP { + pinmux = <0x401f80fc 6 0x401f85d8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_wdog1_b: IOMUXC_GPIO_AD_B1_00_WDOG1_B { + pinmux = <0x401f80fc 4 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp1_in0: IOMUXC_GPIO_AD_B1_01_ACMP1_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in0: IOMUXC_GPIO_AD_B1_01_ACMP2_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp3_in0: IOMUXC_GPIO_AD_B1_01_ACMP3_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp4_in0: IOMUXC_GPIO_AD_B1_01_ACMP4_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in6: IOMUXC_GPIO_AD_B1_01_ADC1_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc2_in6: IOMUXC_GPIO_AD_B1_01_ADC2_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_01_CCM_PMIC_RDY { + pinmux = <0x401f8100 4 0x401f83fc 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_enet2_1588_event0_in: IOMUXC_GPIO_AD_B1_01_ENET2_1588_EVENT0_IN { + pinmux = <0x401f8100 8 0x401f8724 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio3_flexio01: IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 { + pinmux = <0x401f8100 9 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio6_io17: IOMUXC_GPIO_AD_B1_01_GPIO6_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_kpp_col7: IOMUXC_GPIO_AD_B1_01_KPP_COL7 { + pinmux = <0x401f8100 7 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpi2c1_sda: IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA { + pinmux = <0x401f8100 3 0x401f84d0 1 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B { + pinmux = <0x401f8100 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_qtimer3_timer1: IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 { + pinmux = <0x401f8100 1 0x401f8580 0 0x401f82f0>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR { + pinmux = <0x401f8100 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usdhc1_vselect: IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT { + pinmux = <0x401f8100 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp1_in3: IOMUXC_GPIO_AD_B1_02_ACMP1_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc1_in7: IOMUXC_GPIO_AD_B1_02_ADC1_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in7: IOMUXC_GPIO_AD_B1_02_ADC2_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT { + pinmux = <0x401f8104 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio3_flexio02: IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 { + pinmux = <0x401f8104 9 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio6_io18: IOMUXC_GPIO_AD_B1_02_GPIO6_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpt2_clk: IOMUXC_GPIO_AD_B1_02_GPT2_CLK { + pinmux = <0x401f8104 8 0x401f876c 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_kpp_row6: IOMUXC_GPIO_AD_B1_02_KPP_ROW6 { + pinmux = <0x401f8104 7 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpuart2_tx: IOMUXC_GPIO_AD_B1_02_LPUART2_TX { + pinmux = <0x401f8104 2 0x401f8530 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_qtimer3_timer2: IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 { + pinmux = <0x401f8104 1 0x401f8584 1 0x401f82f4>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_spdif_out: IOMUXC_GPIO_AD_B1_02_SPDIF_OUT { + pinmux = <0x401f8104 3 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usb_otg1_id: IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID { + pinmux = <0x401f8104 0 0x401f83f4 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B { + pinmux = <0x401f8104 6 0x401f85d4 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp2_in3: IOMUXC_GPIO_AD_B1_03_ACMP2_IN3 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in8: IOMUXC_GPIO_AD_B1_03_ADC1_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc2_in8: IOMUXC_GPIO_AD_B1_03_ADC2_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN { + pinmux = <0x401f8108 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio3_flexio03: IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 { + pinmux = <0x401f8108 9 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio6_io19: IOMUXC_GPIO_AD_B1_03_GPIO6_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpt2_capture1: IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 { + pinmux = <0x401f8108 8 0x401f8764 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_kpp_col6: IOMUXC_GPIO_AD_B1_03_KPP_COL6 { + pinmux = <0x401f8108 7 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpuart2_rx: IOMUXC_GPIO_AD_B1_03_LPUART2_RX { + pinmux = <0x401f8108 2 0x401f852c 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_qtimer3_timer3: IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 { + pinmux = <0x401f8108 1 0x401f8588 1 0x401f82f8>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_spdif_in: IOMUXC_GPIO_AD_B1_03_SPDIF_IN { + pinmux = <0x401f8108 3 0x401f85c8 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usb_otg1_oc: IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC { + pinmux = <0x401f8108 0 0x401f85d0 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B { + pinmux = <0x401f8108 6 0x401f85e0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp3_in3: IOMUXC_GPIO_AD_B1_04_ACMP3_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc1_in9: IOMUXC_GPIO_AD_B1_04_ADC1_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in9: IOMUXC_GPIO_AD_B1_04_ADC2_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_csi_pixclk: IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK { + pinmux = <0x401f810c 4 0x401f8424 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_enet_mdc: IOMUXC_GPIO_AD_B1_04_ENET_MDC { + pinmux = <0x401f810c 1 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio3_flexio04: IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 { + pinmux = <0x401f810c 9 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_b_data3: IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 { + pinmux = <0x401f810c 0 0x401f84c4 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio6_io20: IOMUXC_GPIO_AD_B1_04_GPIO6_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpt2_capture2: IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 { + pinmux = <0x401f810c 8 0x401f8768 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_kpp_row5: IOMUXC_GPIO_AD_B1_04_KPP_ROW5 { + pinmux = <0x401f810c 7 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpuart3_cts_b: IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B { + pinmux = <0x401f810c 2 0x401f8534 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_spdif_sr_clk: IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK { + pinmux = <0x401f810c 3 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_usdhc2_data0: IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f810c 6 0x401f85e8 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp4_in3: IOMUXC_GPIO_AD_B1_05_ACMP4_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in10: IOMUXC_GPIO_AD_B1_05_ADC1_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in10: IOMUXC_GPIO_AD_B1_05_ADC2_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_csi_mclk: IOMUXC_GPIO_AD_B1_05_CSI_MCLK { + pinmux = <0x401f8110 4 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_enet_mdio: IOMUXC_GPIO_AD_B1_05_ENET_MDIO { + pinmux = <0x401f8110 1 0x401f8430 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio3_flexio05: IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 { + pinmux = <0x401f8110 9 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_b_data2: IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 { + pinmux = <0x401f8110 0 0x401f84c0 1 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio6_io21: IOMUXC_GPIO_AD_B1_05_GPIO6_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpt2_compare1: IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 { + pinmux = <0x401f8110 8 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_kpp_col5: IOMUXC_GPIO_AD_B1_05_KPP_COL5 { + pinmux = <0x401f8110 7 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpuart3_rts_b: IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B { + pinmux = <0x401f8110 2 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_spdif_out: IOMUXC_GPIO_AD_B1_05_SPDIF_OUT { + pinmux = <0x401f8110 3 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc2_data1: IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f8110 6 0x401f85ec 1 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp1_in1: IOMUXC_GPIO_AD_B1_06_ACMP1_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp2_in1: IOMUXC_GPIO_AD_B1_06_ACMP2_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in1: IOMUXC_GPIO_AD_B1_06_ACMP3_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp4_in1: IOMUXC_GPIO_AD_B1_06_ACMP4_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in11: IOMUXC_GPIO_AD_B1_06_ADC1_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in11: IOMUXC_GPIO_AD_B1_06_ADC2_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_csi_vsync: IOMUXC_GPIO_AD_B1_06_CSI_VSYNC { + pinmux = <0x401f8114 4 0x401f8428 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio3_flexio06: IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 { + pinmux = <0x401f8114 9 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexspi_b_data1: IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 { + pinmux = <0x401f8114 0 0x401f84bc 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio6_io22: IOMUXC_GPIO_AD_B1_06_GPIO6_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpt2_compare2: IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 { + pinmux = <0x401f8114 8 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_kpp_row4: IOMUXC_GPIO_AD_B1_06_KPP_ROW4 { + pinmux = <0x401f8114 7 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpi2c3_sda: IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA { + pinmux = <0x401f8114 1 0x401f84e0 2 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart3_tx: IOMUXC_GPIO_AD_B1_06_LPUART3_TX { + pinmux = <0x401f8114 2 0x401f853c 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_spdif_lock: IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK { + pinmux = <0x401f8114 3 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc2_data2: IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 { + pinmux = <0x401f8114 6 0x401f85f0 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp1_in5: IOMUXC_GPIO_AD_B1_07_ACMP1_IN5 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in12: IOMUXC_GPIO_AD_B1_07_ADC1_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in12: IOMUXC_GPIO_AD_B1_07_ADC2_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_csi_hsync: IOMUXC_GPIO_AD_B1_07_CSI_HSYNC { + pinmux = <0x401f8118 4 0x401f8420 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio3_flexio07: IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 { + pinmux = <0x401f8118 9 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexspi_b_data0: IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 { + pinmux = <0x401f8118 0 0x401f84b8 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio6_io23: IOMUXC_GPIO_AD_B1_07_GPIO6_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpt2_compare3: IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 { + pinmux = <0x401f8118 8 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_kpp_col4: IOMUXC_GPIO_AD_B1_07_KPP_COL4 { + pinmux = <0x401f8118 7 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpi2c3_scl: IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL { + pinmux = <0x401f8118 1 0x401f84dc 2 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart3_rx: IOMUXC_GPIO_AD_B1_07_LPUART3_RX { + pinmux = <0x401f8118 2 0x401f8538 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_spdif_ext_clk: IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK { + pinmux = <0x401f8118 3 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc2_data3: IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 { + pinmux = <0x401f8118 6 0x401f85f4 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_acmp2_in5: IOMUXC_GPIO_AD_B1_08_ACMP2_IN5 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc1_in13: IOMUXC_GPIO_AD_B1_08_ADC1_IN13 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc2_in13: IOMUXC_GPIO_AD_B1_08_ADC2_IN13 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_08_CCM_PMIC_RDY { + pinmux = <0x401f811c 3 0x401f83fc 3 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_csi_data09: IOMUXC_GPIO_AD_B1_08_CSI_DATA09 { + pinmux = <0x401f811c 4 0x401f841c 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexcan1_tx: IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX { + pinmux = <0x401f811c 2 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexio3_flexio08: IOMUXC_GPIO_AD_B1_08_FLEXIO3_FLEXIO08 { + pinmux = <0x401f811c 9 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexpwm4_pwma0: IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA0 { + pinmux = <0x401f811c 1 0x401f8494 1 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexspi_a_ss1_b: IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B { + pinmux = <0x401f811c 0 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio1_io24: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + gpr = <0x400ac068 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio6_io24: IOMUXC_GPIO_AD_B1_08_GPIO6_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + gpr = <0x400ac068 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_kpp_row3: IOMUXC_GPIO_AD_B1_08_KPP_ROW3 { + pinmux = <0x401f811c 7 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_usdhc2_cmd: IOMUXC_GPIO_AD_B1_08_USDHC2_CMD { + pinmux = <0x401f811c 6 0x401f85e4 1 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_acmp3_in5: IOMUXC_GPIO_AD_B1_09_ACMP3_IN5 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc1_in14: IOMUXC_GPIO_AD_B1_09_ADC1_IN14 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc2_in14: IOMUXC_GPIO_AD_B1_09_ADC2_IN14 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_csi_data08: IOMUXC_GPIO_AD_B1_09_CSI_DATA08 { + pinmux = <0x401f8120 4 0x401f8418 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexcan1_rx: IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX { + pinmux = <0x401f8120 2 0x401f844c 2 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexio3_flexio09: IOMUXC_GPIO_AD_B1_09_FLEXIO3_FLEXIO09 { + pinmux = <0x401f8120 9 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexpwm4_pwma1: IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA1 { + pinmux = <0x401f8120 1 0x401f8498 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexspi_a_dqs: IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS { + pinmux = <0x401f8120 0 0x401f84a4 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio1_io25: IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + gpr = <0x400ac068 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio6_io25: IOMUXC_GPIO_AD_B1_09_GPIO6_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + gpr = <0x400ac068 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_kpp_col3: IOMUXC_GPIO_AD_B1_09_KPP_COL3 { + pinmux = <0x401f8120 7 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_sai1_mclk: IOMUXC_GPIO_AD_B1_09_SAI1_MCLK { + pinmux = <0x401f8120 3 0x401f858c 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_usdhc2_clk: IOMUXC_GPIO_AD_B1_09_USDHC2_CLK { + pinmux = <0x401f8120 6 0x401f85dc 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_acmp4_in5: IOMUXC_GPIO_AD_B1_10_ACMP4_IN5 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in15: IOMUXC_GPIO_AD_B1_10_ADC1_IN15 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc2_in15: IOMUXC_GPIO_AD_B1_10_ADC2_IN15 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_csi_data07: IOMUXC_GPIO_AD_B1_10_CSI_DATA07 { + pinmux = <0x401f8124 4 0x401f8414 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_enet2_1588_event1_out: IOMUXC_GPIO_AD_B1_10_ENET2_1588_EVENT1_OUT { + pinmux = <0x401f8124 8 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio3_flexio10: IOMUXC_GPIO_AD_B1_10_FLEXIO3_FLEXIO10 { + pinmux = <0x401f8124 9 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexspi_a_data3: IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 { + pinmux = <0x401f8124 0 0x401f84b4 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + gpr = <0x400ac068 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio6_io26: IOMUXC_GPIO_AD_B1_10_GPIO6_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + gpr = <0x400ac068 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_kpp_row2: IOMUXC_GPIO_AD_B1_10_KPP_ROW2 { + pinmux = <0x401f8124 7 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart8_tx: IOMUXC_GPIO_AD_B1_10_LPUART8_TX { + pinmux = <0x401f8124 2 0x401f8564 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_sai1_rx_sync: IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC { + pinmux = <0x401f8124 3 0x401f85a4 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usdhc2_wp: IOMUXC_GPIO_AD_B1_10_USDHC2_WP { + pinmux = <0x401f8124 6 0x401f8608 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_wdog1_b: IOMUXC_GPIO_AD_B1_10_WDOG1_B { + pinmux = <0x401f8124 1 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_acmp1_in6: IOMUXC_GPIO_AD_B1_11_ACMP1_IN6 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in0: IOMUXC_GPIO_AD_B1_11_ADC1_IN0 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc2_in0: IOMUXC_GPIO_AD_B1_11_ADC2_IN0 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_csi_data06: IOMUXC_GPIO_AD_B1_11_CSI_DATA06 { + pinmux = <0x401f8128 4 0x401f8410 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_enet2_1588_event1_in: IOMUXC_GPIO_AD_B1_11_ENET2_1588_EVENT1_IN { + pinmux = <0x401f8128 8 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_ewm_out_b: IOMUXC_GPIO_AD_B1_11_EWM_OUT_B { + pinmux = <0x401f8128 1 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio3_flexio11: IOMUXC_GPIO_AD_B1_11_FLEXIO3_FLEXIO11 { + pinmux = <0x401f8128 9 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexspi_a_data2: IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 { + pinmux = <0x401f8128 0 0x401f84b0 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + gpr = <0x400ac068 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio6_io27: IOMUXC_GPIO_AD_B1_11_GPIO6_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + gpr = <0x400ac068 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_kpp_col2: IOMUXC_GPIO_AD_B1_11_KPP_COL2 { + pinmux = <0x401f8128 7 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart8_rx: IOMUXC_GPIO_AD_B1_11_LPUART8_RX { + pinmux = <0x401f8128 2 0x401f8560 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_sai1_rx_bclk: IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK { + pinmux = <0x401f8128 3 0x401f8590 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usdhc2_reset_b: IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B { + pinmux = <0x401f8128 6 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_out: IOMUXC_GPIO_AD_B1_12_ACMP1_OUT { + pinmux = <0x401f812c 1 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp2_in6: IOMUXC_GPIO_AD_B1_12_ACMP2_IN6 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc2_in1: IOMUXC_GPIO_AD_B1_12_ADC2_IN1 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_csi_data05: IOMUXC_GPIO_AD_B1_12_CSI_DATA05 { + pinmux = <0x401f812c 4 0x401f840c 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_enet2_1588_event2_out: IOMUXC_GPIO_AD_B1_12_ENET2_1588_EVENT2_OUT { + pinmux = <0x401f812c 8 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio3_flexio12: IOMUXC_GPIO_AD_B1_12_FLEXIO3_FLEXIO12 { + pinmux = <0x401f812c 9 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexspi_a_data1: IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 { + pinmux = <0x401f812c 0 0x401f84ac 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + gpr = <0x400ac068 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio6_io28: IOMUXC_GPIO_AD_B1_12_GPIO6_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + gpr = <0x400ac068 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_kpp_row1: IOMUXC_GPIO_AD_B1_12_KPP_ROW1 { + pinmux = <0x401f812c 7 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_lpspi3_pcs0: IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 { + pinmux = <0x401f812c 2 0x401f850c 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_sai1_rx_data0: IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA0 { + pinmux = <0x401f812c 3 0x401f8594 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usdhc2_data4: IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 { + pinmux = <0x401f812c 6 0x401f85f8 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_out: IOMUXC_GPIO_AD_B1_13_ACMP2_OUT { + pinmux = <0x401f8130 1 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp3_in6: IOMUXC_GPIO_AD_B1_13_ACMP3_IN6 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc2_in2: IOMUXC_GPIO_AD_B1_13_ADC2_IN2 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_csi_data04: IOMUXC_GPIO_AD_B1_13_CSI_DATA04 { + pinmux = <0x401f8130 4 0x401f8408 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_enet2_1588_event2_in: IOMUXC_GPIO_AD_B1_13_ENET2_1588_EVENT2_IN { + pinmux = <0x401f8130 8 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio3_flexio13: IOMUXC_GPIO_AD_B1_13_FLEXIO3_FLEXIO13 { + pinmux = <0x401f8130 9 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexspi_a_data0: IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 { + pinmux = <0x401f8130 0 0x401f84a8 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + gpr = <0x400ac068 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio6_io29: IOMUXC_GPIO_AD_B1_13_GPIO6_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + gpr = <0x400ac068 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_kpp_col1: IOMUXC_GPIO_AD_B1_13_KPP_COL1 { + pinmux = <0x401f8130 7 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpspi3_sdi: IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI { + pinmux = <0x401f8130 2 0x401f8514 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_sai1_tx_data0: IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA0 { + pinmux = <0x401f8130 3 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_usdhc2_data5: IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 { + pinmux = <0x401f8130 6 0x401f85fc 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_out: IOMUXC_GPIO_AD_B1_14_ACMP3_OUT { + pinmux = <0x401f8134 1 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp4_in6: IOMUXC_GPIO_AD_B1_14_ACMP4_IN6 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc2_in3: IOMUXC_GPIO_AD_B1_14_ADC2_IN3 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_csi_data03: IOMUXC_GPIO_AD_B1_14_CSI_DATA03 { + pinmux = <0x401f8134 4 0x401f8404 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_enet2_1588_event3_out: IOMUXC_GPIO_AD_B1_14_ENET2_1588_EVENT3_OUT { + pinmux = <0x401f8134 8 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio3_flexio14: IOMUXC_GPIO_AD_B1_14_FLEXIO3_FLEXIO14 { + pinmux = <0x401f8134 9 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexspi_a_sclk: IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK { + pinmux = <0x401f8134 0 0x401f84c8 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + gpr = <0x400ac068 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio6_io30: IOMUXC_GPIO_AD_B1_14_GPIO6_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + gpr = <0x400ac068 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_kpp_row0: IOMUXC_GPIO_AD_B1_14_KPP_ROW0 { + pinmux = <0x401f8134 7 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpspi3_sdo: IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO { + pinmux = <0x401f8134 2 0x401f8518 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_sai1_tx_bclk: IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK { + pinmux = <0x401f8134 3 0x401f85a8 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_usdhc2_data6: IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 { + pinmux = <0x401f8134 6 0x401f8600 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_out: IOMUXC_GPIO_AD_B1_15_ACMP4_OUT { + pinmux = <0x401f8138 1 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc2_in4: IOMUXC_GPIO_AD_B1_15_ADC2_IN4 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_csi_data02: IOMUXC_GPIO_AD_B1_15_CSI_DATA02 { + pinmux = <0x401f8138 4 0x401f8400 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_enet2_1588_event3_in: IOMUXC_GPIO_AD_B1_15_ENET2_1588_EVENT3_IN { + pinmux = <0x401f8138 8 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio3_flexio15: IOMUXC_GPIO_AD_B1_15_FLEXIO3_FLEXIO15 { + pinmux = <0x401f8138 9 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexspi_a_ss0_b: IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B { + pinmux = <0x401f8138 0 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + gpr = <0x400ac068 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio6_io31: IOMUXC_GPIO_AD_B1_15_GPIO6_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + gpr = <0x400ac068 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_kpp_col0: IOMUXC_GPIO_AD_B1_15_KPP_COL0 { + pinmux = <0x401f8138 7 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpspi3_sck: IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK { + pinmux = <0x401f8138 2 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_sai1_tx_sync: IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC { + pinmux = <0x401f8138 3 0x401f85ac 1 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_usdhc2_data7: IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 { + pinmux = <0x401f8138 6 0x401f8604 1 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_enet2_mdc: IOMUXC_GPIO_B0_00_ENET2_MDC { + pinmux = <0x401f813c 8 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_flexio2_flexio00: IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 { + pinmux = <0x401f813c 4 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio2_io00: IOMUXC_GPIO_B0_00_GPIO2_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio7_io00: IOMUXC_GPIO_B0_00_GPIO7_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lcdif_clk: IOMUXC_GPIO_B0_00_LCDIF_CLK { + pinmux = <0x401f813c 0 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lpspi4_pcs0: IOMUXC_GPIO_B0_00_LPSPI4_PCS0 { + pinmux = <0x401f813c 3 0x401f851c 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_mqs_right: IOMUXC_GPIO_B0_00_MQS_RIGHT { + pinmux = <0x401f813c 2 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_qtimer1_timer0: IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x0 0 0x401f832c>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_semc_csx1: IOMUXC_GPIO_B0_00_SEMC_CSX1 { + pinmux = <0x401f813c 6 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_enet2_mdio: IOMUXC_GPIO_B0_01_ENET2_MDIO { + pinmux = <0x401f8140 8 0x401f8710 1 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_flexio2_flexio01: IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 { + pinmux = <0x401f8140 4 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio2_io01: IOMUXC_GPIO_B0_01_GPIO2_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio7_io01: IOMUXC_GPIO_B0_01_GPIO7_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lcdif_enable: IOMUXC_GPIO_B0_01_LCDIF_ENABLE { + pinmux = <0x401f8140 0 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lpspi4_sdi: IOMUXC_GPIO_B0_01_LPSPI4_SDI { + pinmux = <0x401f8140 3 0x401f8524 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_mqs_left: IOMUXC_GPIO_B0_01_MQS_LEFT { + pinmux = <0x401f8140 2 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_qtimer1_timer1: IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x0 0 0x401f8330>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_semc_csx2: IOMUXC_GPIO_B0_01_SEMC_CSX2 { + pinmux = <0x401f8140 6 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_enet2_1588_event0_out: IOMUXC_GPIO_B0_02_ENET2_1588_EVENT0_OUT { + pinmux = <0x401f8144 8 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexcan1_tx: IOMUXC_GPIO_B0_02_FLEXCAN1_TX { + pinmux = <0x401f8144 2 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexio2_flexio02: IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 { + pinmux = <0x401f8144 4 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio2_io02: IOMUXC_GPIO_B0_02_GPIO2_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio7_io02: IOMUXC_GPIO_B0_02_GPIO7_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lcdif_hsync: IOMUXC_GPIO_B0_02_LCDIF_HSYNC { + pinmux = <0x401f8144 0 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lpspi4_sdo: IOMUXC_GPIO_B0_02_LPSPI4_SDO { + pinmux = <0x401f8144 3 0x401f8528 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_qtimer1_timer2: IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x0 0 0x401f8334>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_semc_csx3: IOMUXC_GPIO_B0_02_SEMC_CSX3 { + pinmux = <0x401f8144 6 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_enet2_1588_event0_in: IOMUXC_GPIO_B0_03_ENET2_1588_EVENT0_IN { + pinmux = <0x401f8148 8 0x401f8724 1 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexcan1_rx: IOMUXC_GPIO_B0_03_FLEXCAN1_RX { + pinmux = <0x401f8148 2 0x401f844c 3 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexio2_flexio03: IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 { + pinmux = <0x401f8148 4 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio2_io03: IOMUXC_GPIO_B0_03_GPIO2_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio7_io03: IOMUXC_GPIO_B0_03_GPIO7_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lcdif_vsync: IOMUXC_GPIO_B0_03_LCDIF_VSYNC { + pinmux = <0x401f8148 0 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lpspi4_sck: IOMUXC_GPIO_B0_03_LPSPI4_SCK { + pinmux = <0x401f8148 3 0x401f8520 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_qtimer2_timer0: IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 { + pinmux = <0x401f8148 1 0x401f856c 1 0x401f8338>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_wdog2_rst_b_deb: IOMUXC_GPIO_B0_03_WDOG2_RST_B_DEB { + pinmux = <0x401f8148 6 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_arm_trace0: IOMUXC_GPIO_B0_04_ARM_TRACE0 { + pinmux = <0x401f814c 3 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_enet2_tx_data3: IOMUXC_GPIO_B0_04_ENET2_TX_DATA3 { + pinmux = <0x401f814c 8 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_flexio2_flexio04: IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 { + pinmux = <0x401f814c 4 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio2_io04: IOMUXC_GPIO_B0_04_GPIO2_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio7_io04: IOMUXC_GPIO_B0_04_GPIO7_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lcdif_data00: IOMUXC_GPIO_B0_04_LCDIF_DATA00 { + pinmux = <0x401f814c 0 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lpi2c2_scl: IOMUXC_GPIO_B0_04_LPI2C2_SCL { + pinmux = <0x401f814c 2 0x401f84d4 1 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_qtimer2_timer1: IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 { + pinmux = <0x401f814c 1 0x401f8570 1 0x401f833c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_src_bt_cfg0: IOMUXC_GPIO_B0_04_SRC_BT_CFG0 { + pinmux = <0x401f814c 6 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_arm_trace1: IOMUXC_GPIO_B0_05_ARM_TRACE1 { + pinmux = <0x401f8150 3 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_enet2_tx_data2: IOMUXC_GPIO_B0_05_ENET2_TX_DATA2 { + pinmux = <0x401f8150 8 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_flexio2_flexio05: IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 { + pinmux = <0x401f8150 4 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio2_io05: IOMUXC_GPIO_B0_05_GPIO2_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio7_io05: IOMUXC_GPIO_B0_05_GPIO7_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lcdif_data01: IOMUXC_GPIO_B0_05_LCDIF_DATA01 { + pinmux = <0x401f8150 0 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lpi2c2_sda: IOMUXC_GPIO_B0_05_LPI2C2_SDA { + pinmux = <0x401f8150 2 0x401f84d8 1 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_qtimer2_timer2: IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 { + pinmux = <0x401f8150 1 0x401f8574 1 0x401f8340>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_src_bt_cfg1: IOMUXC_GPIO_B0_05_SRC_BT_CFG1 { + pinmux = <0x401f8150 6 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_arm_trace2: IOMUXC_GPIO_B0_06_ARM_TRACE2 { + pinmux = <0x401f8154 3 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_enet2_rx_clk: IOMUXC_GPIO_B0_06_ENET2_RX_CLK { + pinmux = <0x401f8154 8 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexio2_flexio06: IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 { + pinmux = <0x401f8154 4 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexpwm2_pwma0: IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f8154 2 0x401f8478 1 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio2_io06: IOMUXC_GPIO_B0_06_GPIO2_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio7_io06: IOMUXC_GPIO_B0_06_GPIO7_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_lcdif_data02: IOMUXC_GPIO_B0_06_LCDIF_DATA02 { + pinmux = <0x401f8154 0 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_qtimer3_timer0: IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 { + pinmux = <0x401f8154 1 0x401f857c 2 0x401f8344>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_src_bt_cfg2: IOMUXC_GPIO_B0_06_SRC_BT_CFG2 { + pinmux = <0x401f8154 6 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_arm_trace3: IOMUXC_GPIO_B0_07_ARM_TRACE3 { + pinmux = <0x401f8158 3 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_enet2_tx_er: IOMUXC_GPIO_B0_07_ENET2_TX_ER { + pinmux = <0x401f8158 8 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexio2_flexio07: IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 { + pinmux = <0x401f8158 4 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexpwm2_pwmb0: IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8158 2 0x401f8488 1 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio2_io07: IOMUXC_GPIO_B0_07_GPIO2_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio7_io07: IOMUXC_GPIO_B0_07_GPIO7_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_lcdif_data03: IOMUXC_GPIO_B0_07_LCDIF_DATA03 { + pinmux = <0x401f8158 0 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_qtimer3_timer1: IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 { + pinmux = <0x401f8158 1 0x401f8580 2 0x401f8348>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_src_bt_cfg3: IOMUXC_GPIO_B0_07_SRC_BT_CFG3 { + pinmux = <0x401f8158 6 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_enet2_rx_data3: IOMUXC_GPIO_B0_08_ENET2_RX_DATA3 { + pinmux = <0x401f815c 8 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexio2_flexio08: IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 { + pinmux = <0x401f815c 4 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexpwm2_pwma1: IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f815c 2 0x401f847c 1 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio2_io08: IOMUXC_GPIO_B0_08_GPIO2_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio7_io08: IOMUXC_GPIO_B0_08_GPIO7_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lcdif_data04: IOMUXC_GPIO_B0_08_LCDIF_DATA04 { + pinmux = <0x401f815c 0 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lpuart3_tx: IOMUXC_GPIO_B0_08_LPUART3_TX { + pinmux = <0x401f815c 3 0x401f853c 2 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_qtimer3_timer2: IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 { + pinmux = <0x401f815c 1 0x401f8584 2 0x401f834c>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_src_bt_cfg4: IOMUXC_GPIO_B0_08_SRC_BT_CFG4 { + pinmux = <0x401f815c 6 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_enet2_rx_data2: IOMUXC_GPIO_B0_09_ENET2_RX_DATA2 { + pinmux = <0x401f8160 8 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexio2_flexio09: IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 { + pinmux = <0x401f8160 4 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexpwm2_pwmb1: IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8160 2 0x401f848c 1 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio2_io09: IOMUXC_GPIO_B0_09_GPIO2_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio7_io09: IOMUXC_GPIO_B0_09_GPIO7_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lcdif_data05: IOMUXC_GPIO_B0_09_LCDIF_DATA05 { + pinmux = <0x401f8160 0 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lpuart3_rx: IOMUXC_GPIO_B0_09_LPUART3_RX { + pinmux = <0x401f8160 3 0x401f8538 2 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_qtimer4_timer0: IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 { + pinmux = <0x401f8160 1 0x0 0 0x401f8350>; + gpr = <0x400ac018 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_src_bt_cfg5: IOMUXC_GPIO_B0_09_SRC_BT_CFG5 { + pinmux = <0x401f8160 6 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_enet2_crs: IOMUXC_GPIO_B0_10_ENET2_CRS { + pinmux = <0x401f8164 8 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexio2_flexio10: IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 { + pinmux = <0x401f8164 4 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f8164 2 0x401f8480 1 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio2_io10: IOMUXC_GPIO_B0_10_GPIO2_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio7_io10: IOMUXC_GPIO_B0_10_GPIO7_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_lcdif_data06: IOMUXC_GPIO_B0_10_LCDIF_DATA06 { + pinmux = <0x401f8164 0 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_qtimer4_timer1: IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 { + pinmux = <0x401f8164 1 0x0 0 0x401f8354>; + gpr = <0x400ac018 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_sai1_tx_data3: IOMUXC_GPIO_B0_10_SAI1_TX_DATA3 { + pinmux = <0x401f8164 3 0x401f8598 1 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_src_bt_cfg6: IOMUXC_GPIO_B0_10_SRC_BT_CFG6 { + pinmux = <0x401f8164 6 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_enet2_col: IOMUXC_GPIO_B0_11_ENET2_COL { + pinmux = <0x401f8168 8 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexio2_flexio11: IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 { + pinmux = <0x401f8168 4 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8168 2 0x401f8490 1 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio2_io11: IOMUXC_GPIO_B0_11_GPIO2_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio7_io11: IOMUXC_GPIO_B0_11_GPIO7_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_lcdif_data07: IOMUXC_GPIO_B0_11_LCDIF_DATA07 { + pinmux = <0x401f8168 0 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_qtimer4_timer2: IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 { + pinmux = <0x401f8168 1 0x0 0 0x401f8358>; + gpr = <0x400ac018 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_sai1_tx_data2: IOMUXC_GPIO_B0_11_SAI1_TX_DATA2 { + pinmux = <0x401f8168 3 0x401f859c 1 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_src_bt_cfg7: IOMUXC_GPIO_B0_11_SRC_BT_CFG7 { + pinmux = <0x401f8168 6 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_arm_trace_clk: IOMUXC_GPIO_B0_12_ARM_TRACE_CLK { + pinmux = <0x401f816c 2 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_enet2_tx_data0: IOMUXC_GPIO_B0_12_ENET2_TX_DATA0 { + pinmux = <0x401f816c 8 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_flexio2_flexio12: IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 { + pinmux = <0x401f816c 4 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio2_io12: IOMUXC_GPIO_B0_12_GPIO2_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio7_io12: IOMUXC_GPIO_B0_12_GPIO7_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_lcdif_data08: IOMUXC_GPIO_B0_12_LCDIF_DATA08 { + pinmux = <0x401f816c 0 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_sai1_tx_data1: IOMUXC_GPIO_B0_12_SAI1_TX_DATA1 { + pinmux = <0x401f816c 3 0x401f85a0 1 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_src_bt_cfg8: IOMUXC_GPIO_B0_12_SRC_BT_CFG8 { + pinmux = <0x401f816c 6 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_in10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_IN10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_inout10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_arm_trace_swo: IOMUXC_GPIO_B0_13_ARM_TRACE_SWO { + pinmux = <0x401f8170 2 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_enet2_tx_data1: IOMUXC_GPIO_B0_13_ENET2_TX_DATA1 { + pinmux = <0x401f8170 8 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_flexio2_flexio13: IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 { + pinmux = <0x401f8170 4 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio2_io13: IOMUXC_GPIO_B0_13_GPIO2_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio7_io13: IOMUXC_GPIO_B0_13_GPIO7_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_lcdif_data09: IOMUXC_GPIO_B0_13_LCDIF_DATA09 { + pinmux = <0x401f8170 0 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_sai1_mclk: IOMUXC_GPIO_B0_13_SAI1_MCLK { + pinmux = <0x401f8170 3 0x401f858c 2 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_src_bt_cfg9: IOMUXC_GPIO_B0_13_SRC_BT_CFG9 { + pinmux = <0x401f8170 6 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_in11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_IN11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_inout11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_arm_txev: IOMUXC_GPIO_B0_14_ARM_TXEV { + pinmux = <0x401f8174 2 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_enet2_tx_en: IOMUXC_GPIO_B0_14_ENET2_TX_EN { + pinmux = <0x401f8174 8 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_flexio2_flexio14: IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 { + pinmux = <0x401f8174 4 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio2_io14: IOMUXC_GPIO_B0_14_GPIO2_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio7_io14: IOMUXC_GPIO_B0_14_GPIO7_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_lcdif_data10: IOMUXC_GPIO_B0_14_LCDIF_DATA10 { + pinmux = <0x401f8174 0 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_sai1_rx_sync: IOMUXC_GPIO_B0_14_SAI1_RX_SYNC { + pinmux = <0x401f8174 3 0x401f85a4 2 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_src_bt_cfg10: IOMUXC_GPIO_B0_14_SRC_BT_CFG10 { + pinmux = <0x401f8174 6 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_in12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_IN12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_inout12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_arm_rxev: IOMUXC_GPIO_B0_15_ARM_RXEV { + pinmux = <0x401f8178 2 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_enet2_ref_clk2: IOMUXC_GPIO_B0_15_ENET2_REF_CLK2 { + pinmux = <0x401f8178 9 0x401f870c 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_enet2_tx_clk: IOMUXC_GPIO_B0_15_ENET2_TX_CLK { + pinmux = <0x401f8178 8 0x401f8728 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_flexio2_flexio15: IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 { + pinmux = <0x401f8178 4 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio2_io15: IOMUXC_GPIO_B0_15_GPIO2_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio7_io15: IOMUXC_GPIO_B0_15_GPIO7_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_lcdif_data11: IOMUXC_GPIO_B0_15_LCDIF_DATA11 { + pinmux = <0x401f8178 0 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_sai1_rx_bclk: IOMUXC_GPIO_B0_15_SAI1_RX_BCLK { + pinmux = <0x401f8178 3 0x401f8590 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_src_bt_cfg11: IOMUXC_GPIO_B0_15_SRC_BT_CFG11 { + pinmux = <0x401f8178 6 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_in13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_IN13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_inout13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_enet2_rx_er: IOMUXC_GPIO_B1_00_ENET2_RX_ER { + pinmux = <0x401f817c 8 0x401f8720 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio2_flexio16: IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 { + pinmux = <0x401f817c 4 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio3_flexio16: IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 { + pinmux = <0x401f817c 9 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f817c 6 0x401f8454 4 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio2_io16: IOMUXC_GPIO_B1_00_GPIO2_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio7_io16: IOMUXC_GPIO_B1_00_GPIO7_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lcdif_data12: IOMUXC_GPIO_B1_00_LCDIF_DATA12 { + pinmux = <0x401f817c 0 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lpuart4_tx: IOMUXC_GPIO_B1_00_LPUART4_TX { + pinmux = <0x401f817c 2 0x401f8544 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_sai1_rx_data0: IOMUXC_GPIO_B1_00_SAI1_RX_DATA0 { + pinmux = <0x401f817c 3 0x401f8594 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_in14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f817c 1 0x401f8644 1 0x401f836c>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_inout14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f817c 1 0x401f8644 1 0x401f836c>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_enet2_rx_data0: IOMUXC_GPIO_B1_01_ENET2_RX_DATA0 { + pinmux = <0x401f8180 8 0x401f8714 2 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio2_flexio17: IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 { + pinmux = <0x401f8180 4 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio3_flexio17: IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 { + pinmux = <0x401f8180 9 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f8180 6 0x401f8464 4 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio2_io17: IOMUXC_GPIO_B1_01_GPIO2_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio7_io17: IOMUXC_GPIO_B1_01_GPIO7_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lcdif_data13: IOMUXC_GPIO_B1_01_LCDIF_DATA13 { + pinmux = <0x401f8180 0 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lpuart4_rx: IOMUXC_GPIO_B1_01_LPUART4_RX { + pinmux = <0x401f8180 2 0x401f8540 2 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_sai1_tx_data0: IOMUXC_GPIO_B1_01_SAI1_TX_DATA0 { + pinmux = <0x401f8180 3 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_in15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8180 1 0x401f8648 1 0x401f8370>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_inout15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8180 1 0x401f8648 1 0x401f8370>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_enet2_rx_data1: IOMUXC_GPIO_B1_02_ENET2_RX_DATA1 { + pinmux = <0x401f8184 8 0x401f8718 2 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio2_flexio18: IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 { + pinmux = <0x401f8184 4 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio3_flexio18: IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 { + pinmux = <0x401f8184 9 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f8184 6 0x401f8474 4 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio2_io18: IOMUXC_GPIO_B1_02_GPIO2_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio7_io18: IOMUXC_GPIO_B1_02_GPIO7_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lcdif_data14: IOMUXC_GPIO_B1_02_LCDIF_DATA14 { + pinmux = <0x401f8184 0 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lpspi4_pcs2: IOMUXC_GPIO_B1_02_LPSPI4_PCS2 { + pinmux = <0x401f8184 2 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_sai1_tx_bclk: IOMUXC_GPIO_B1_02_SAI1_TX_BCLK { + pinmux = <0x401f8184 3 0x401f85a8 2 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_in16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8184 1 0x401f864c 1 0x401f8374>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_inout16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8184 1 0x401f864c 1 0x401f8374>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_enet2_rx_en: IOMUXC_GPIO_B1_03_ENET2_RX_EN { + pinmux = <0x401f8188 8 0x401f871c 2 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio2_flexio19: IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 { + pinmux = <0x401f8188 4 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio3_flexio19: IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 { + pinmux = <0x401f8188 9 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f8188 6 0x401f8484 3 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio2_io19: IOMUXC_GPIO_B1_03_GPIO2_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio7_io19: IOMUXC_GPIO_B1_03_GPIO7_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lcdif_data15: IOMUXC_GPIO_B1_03_LCDIF_DATA15 { + pinmux = <0x401f8188 0 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lpspi4_pcs1: IOMUXC_GPIO_B1_03_LPSPI4_PCS1 { + pinmux = <0x401f8188 2 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_sai1_tx_sync: IOMUXC_GPIO_B1_03_SAI1_TX_SYNC { + pinmux = <0x401f8188 3 0x401f85ac 2 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_in17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f8188 1 0x401f862c 3 0x401f8378>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_inout17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8188 1 0x401f862c 3 0x401f8378>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_csi_data15: IOMUXC_GPIO_B1_04_CSI_DATA15 { + pinmux = <0x401f818c 2 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_enet_rx_data0: IOMUXC_GPIO_B1_04_ENET_RX_DATA0 { + pinmux = <0x401f818c 3 0x401f8434 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio2_flexio20: IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 { + pinmux = <0x401f818c 4 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio3_flexio20: IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 { + pinmux = <0x401f818c 9 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio2_io20: IOMUXC_GPIO_B1_04_GPIO2_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio7_io20: IOMUXC_GPIO_B1_04_GPIO7_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpt1_clk: IOMUXC_GPIO_B1_04_GPT1_CLK { + pinmux = <0x401f818c 8 0x401f8760 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lcdif_data16: IOMUXC_GPIO_B1_04_LCDIF_DATA16 { + pinmux = <0x401f818c 0 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lpspi4_pcs0: IOMUXC_GPIO_B1_04_LPSPI4_PCS0 { + pinmux = <0x401f818c 1 0x401f851c 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_csi_data14: IOMUXC_GPIO_B1_05_CSI_DATA14 { + pinmux = <0x401f8190 2 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_enet_rx_data1: IOMUXC_GPIO_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f8190 3 0x401f8438 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio2_flexio21: IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 { + pinmux = <0x401f8190 4 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio3_flexio21: IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 { + pinmux = <0x401f8190 9 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio2_io21: IOMUXC_GPIO_B1_05_GPIO2_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio7_io21: IOMUXC_GPIO_B1_05_GPIO7_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpt1_capture1: IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 { + pinmux = <0x401f8190 8 0x401f8758 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lcdif_data17: IOMUXC_GPIO_B1_05_LCDIF_DATA17 { + pinmux = <0x401f8190 0 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lpspi4_sdi: IOMUXC_GPIO_B1_05_LPSPI4_SDI { + pinmux = <0x401f8190 1 0x401f8524 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_csi_data13: IOMUXC_GPIO_B1_06_CSI_DATA13 { + pinmux = <0x401f8194 2 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_enet_rx_en: IOMUXC_GPIO_B1_06_ENET_RX_EN { + pinmux = <0x401f8194 3 0x401f843c 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio2_flexio22: IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 { + pinmux = <0x401f8194 4 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio3_flexio22: IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 { + pinmux = <0x401f8194 9 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio2_io22: IOMUXC_GPIO_B1_06_GPIO2_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio7_io22: IOMUXC_GPIO_B1_06_GPIO7_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpt1_capture2: IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 { + pinmux = <0x401f8194 8 0x401f875c 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lcdif_data18: IOMUXC_GPIO_B1_06_LCDIF_DATA18 { + pinmux = <0x401f8194 0 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lpspi4_sdo: IOMUXC_GPIO_B1_06_LPSPI4_SDO { + pinmux = <0x401f8194 1 0x401f8528 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_csi_data12: IOMUXC_GPIO_B1_07_CSI_DATA12 { + pinmux = <0x401f8198 2 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_enet_tx_data0: IOMUXC_GPIO_B1_07_ENET_TX_DATA0 { + pinmux = <0x401f8198 3 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio2_flexio23: IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 { + pinmux = <0x401f8198 4 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio3_flexio23: IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 { + pinmux = <0x401f8198 9 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio2_io23: IOMUXC_GPIO_B1_07_GPIO2_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio7_io23: IOMUXC_GPIO_B1_07_GPIO7_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpt1_compare1: IOMUXC_GPIO_B1_07_GPT1_COMPARE1 { + pinmux = <0x401f8198 8 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lcdif_data19: IOMUXC_GPIO_B1_07_LCDIF_DATA19 { + pinmux = <0x401f8198 0 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lpspi4_sck: IOMUXC_GPIO_B1_07_LPSPI4_SCK { + pinmux = <0x401f8198 1 0x401f8520 1 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_csi_data11: IOMUXC_GPIO_B1_08_CSI_DATA11 { + pinmux = <0x401f819c 2 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_enet_tx_data1: IOMUXC_GPIO_B1_08_ENET_TX_DATA1 { + pinmux = <0x401f819c 3 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexcan2_tx: IOMUXC_GPIO_B1_08_FLEXCAN2_TX { + pinmux = <0x401f819c 6 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio2_flexio24: IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 { + pinmux = <0x401f819c 4 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio3_flexio24: IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 { + pinmux = <0x401f819c 9 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio2_io24: IOMUXC_GPIO_B1_08_GPIO2_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio7_io24: IOMUXC_GPIO_B1_08_GPIO7_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpt1_compare2: IOMUXC_GPIO_B1_08_GPT1_COMPARE2 { + pinmux = <0x401f819c 8 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_lcdif_data20: IOMUXC_GPIO_B1_08_LCDIF_DATA20 { + pinmux = <0x401f819c 0 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_qtimer1_timer3: IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 { + pinmux = <0x401f819c 1 0x0 0 0x401f838c>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_csi_data10: IOMUXC_GPIO_B1_09_CSI_DATA10 { + pinmux = <0x401f81a0 2 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_enet_tx_en: IOMUXC_GPIO_B1_09_ENET_TX_EN { + pinmux = <0x401f81a0 3 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexcan2_rx: IOMUXC_GPIO_B1_09_FLEXCAN2_RX { + pinmux = <0x401f81a0 6 0x401f8450 3 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio2_flexio25: IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 { + pinmux = <0x401f81a0 4 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio3_flexio25: IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 { + pinmux = <0x401f81a0 9 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio2_io25: IOMUXC_GPIO_B1_09_GPIO2_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio7_io25: IOMUXC_GPIO_B1_09_GPIO7_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpt1_compare3: IOMUXC_GPIO_B1_09_GPT1_COMPARE3 { + pinmux = <0x401f81a0 8 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_lcdif_data21: IOMUXC_GPIO_B1_09_LCDIF_DATA21 { + pinmux = <0x401f81a0 0 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_qtimer2_timer3: IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 { + pinmux = <0x401f81a0 1 0x401f8578 1 0x401f8390>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_csi_data00: IOMUXC_GPIO_B1_10_CSI_DATA00 { + pinmux = <0x401f81a4 2 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_ref_clk: IOMUXC_GPIO_B1_10_ENET_REF_CLK { + pinmux = <0x401f81a4 6 0x401f842c 1 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_tx_clk: IOMUXC_GPIO_B1_10_ENET_TX_CLK { + pinmux = <0x401f81a4 3 0x401f8448 1 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio2_flexio26: IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 { + pinmux = <0x401f81a4 4 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio3_flexio26: IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 { + pinmux = <0x401f81a4 9 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio2_io26: IOMUXC_GPIO_B1_10_GPIO2_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio7_io26: IOMUXC_GPIO_B1_10_GPIO7_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_lcdif_data22: IOMUXC_GPIO_B1_10_LCDIF_DATA22 { + pinmux = <0x401f81a4 0 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_qtimer3_timer3: IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 { + pinmux = <0x401f81a4 1 0x401f8588 2 0x401f8394>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_csi_data01: IOMUXC_GPIO_B1_11_CSI_DATA01 { + pinmux = <0x401f81a8 2 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_enet_rx_er: IOMUXC_GPIO_B1_11_ENET_RX_ER { + pinmux = <0x401f81a8 3 0x401f8440 1 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio2_flexio27: IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 { + pinmux = <0x401f81a8 4 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio3_flexio27: IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 { + pinmux = <0x401f81a8 9 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio2_io27: IOMUXC_GPIO_B1_11_GPIO2_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio7_io27: IOMUXC_GPIO_B1_11_GPIO7_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lcdif_data23: IOMUXC_GPIO_B1_11_LCDIF_DATA23 { + pinmux = <0x401f81a8 0 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lpspi4_pcs3: IOMUXC_GPIO_B1_11_LPSPI4_PCS3 { + pinmux = <0x401f81a8 6 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_qtimer4_timer3: IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 { + pinmux = <0x401f81a8 1 0x0 0 0x401f8398>; + gpr = <0x400ac018 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_csi_pixclk: IOMUXC_GPIO_B1_12_CSI_PIXCLK { + pinmux = <0x401f81ac 2 0x401f8424 1 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_enet_1588_event0_in: IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN { + pinmux = <0x401f81ac 3 0x401f8444 2 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio2_flexio28: IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 { + pinmux = <0x401f81ac 4 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio3_flexio28: IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 { + pinmux = <0x401f81ac 9 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio2_io28: IOMUXC_GPIO_B1_12_GPIO2_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio7_io28: IOMUXC_GPIO_B1_12_GPIO7_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_lpuart5_tx: IOMUXC_GPIO_B1_12_LPUART5_TX { + pinmux = <0x401f81ac 1 0x401f854c 1 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_usdhc1_cd_b: IOMUXC_GPIO_B1_12_USDHC1_CD_B { + pinmux = <0x401f81ac 6 0x401f85d4 2 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_csi_vsync: IOMUXC_GPIO_B1_13_CSI_VSYNC { + pinmux = <0x401f81b0 2 0x401f8428 2 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_enet_1588_event0_out: IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT { + pinmux = <0x401f81b0 3 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio2_flexio29: IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 { + pinmux = <0x401f81b0 4 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio3_flexio29: IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 { + pinmux = <0x401f81b0 9 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio2_io29: IOMUXC_GPIO_B1_13_GPIO2_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio7_io29: IOMUXC_GPIO_B1_13_GPIO7_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_lpuart5_rx: IOMUXC_GPIO_B1_13_LPUART5_RX { + pinmux = <0x401f81b0 1 0x401f8548 1 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_semc_dqs4: IOMUXC_GPIO_B1_13_SEMC_DQS4 { + pinmux = <0x401f81b0 8 0x401f8788 3 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_usdhc1_wp: IOMUXC_GPIO_B1_13_USDHC1_WP { + pinmux = <0x401f81b0 6 0x401f85d8 3 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_wdog1_b: IOMUXC_GPIO_B1_13_WDOG1_B { + pinmux = <0x401f81b0 0 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_csi_hsync: IOMUXC_GPIO_B1_14_CSI_HSYNC { + pinmux = <0x401f81b4 2 0x401f8420 2 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet2_tx_data0: IOMUXC_GPIO_B1_14_ENET2_TX_DATA0 { + pinmux = <0x401f81b4 8 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet_mdc: IOMUXC_GPIO_B1_14_ENET_MDC { + pinmux = <0x401f81b4 0 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio2_flexio30: IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 { + pinmux = <0x401f81b4 4 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio3_flexio30: IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 { + pinmux = <0x401f81b4 9 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexpwm4_pwma2: IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA2 { + pinmux = <0x401f81b4 1 0x401f849c 1 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio2_io30: IOMUXC_GPIO_B1_14_GPIO2_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio7_io30: IOMUXC_GPIO_B1_14_GPIO7_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_usdhc1_vselect: IOMUXC_GPIO_B1_14_USDHC1_VSELECT { + pinmux = <0x401f81b4 6 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_xbar1_xbar_in02: IOMUXC_GPIO_B1_14_XBAR1_XBAR_IN02 { + pinmux = <0x401f81b4 3 0x401f860c 1 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_csi_mclk: IOMUXC_GPIO_B1_15_CSI_MCLK { + pinmux = <0x401f81b8 2 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet2_tx_data1: IOMUXC_GPIO_B1_15_ENET2_TX_DATA1 { + pinmux = <0x401f81b8 8 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet_mdio: IOMUXC_GPIO_B1_15_ENET_MDIO { + pinmux = <0x401f81b8 0 0x401f8430 2 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio2_flexio31: IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 { + pinmux = <0x401f81b8 4 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio3_flexio31: IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 { + pinmux = <0x401f81b8 9 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexpwm4_pwma3: IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA3 { + pinmux = <0x401f81b8 1 0x401f84a0 1 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio2_io31: IOMUXC_GPIO_B1_15_GPIO2_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio7_io31: IOMUXC_GPIO_B1_15_GPIO7_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_usdhc1_reset_b: IOMUXC_GPIO_B1_15_USDHC1_RESET_B { + pinmux = <0x401f81b8 6 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_xbar1_xbar_in03: IOMUXC_GPIO_B1_15_XBAR1_XBAR_IN03 { + pinmux = <0x401f81b8 3 0x401f8610 1 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexio1_flexio00: IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8014 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexpwm4_pwma0: IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA0 { + pinmux = <0x401f8014 1 0x401f8494 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio4_io00: IOMUXC_GPIO_EMC_00_GPIO4_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio9_io00: IOMUXC_GPIO_EMC_00_GPIO9_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 2 0x401f8500 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_xbar1_xbar_in02: IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 { + pinmux = <0x401f8014 3 0x401f860c 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexio1_flexio01: IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8018 4 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexpwm4_pwmb0: IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB0 { + pinmux = <0x401f8018 1 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio4_io01: IOMUXC_GPIO_EMC_01_GPIO4_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio9_io01: IOMUXC_GPIO_EMC_01_GPIO9_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 2 0x401f84fc 1 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_xbar1_xbar_in03: IOMUXC_GPIO_EMC_01_XBAR1_XBAR_IN03 { + pinmux = <0x401f8018 3 0x401f8610 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexio1_flexio02: IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 { + pinmux = <0x401f801c 4 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexpwm4_pwma1: IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA1 { + pinmux = <0x401f801c 1 0x401f8498 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio4_io02: IOMUXC_GPIO_EMC_02_GPIO4_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio9_io02: IOMUXC_GPIO_EMC_02_GPIO9_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 2 0x401f8508 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_in04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_IN04 { + pinmux = <0x401f801c 3 0x401f8614 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f801c 3 0x401f8614 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexio1_flexio03: IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 { + pinmux = <0x401f8020 4 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexpwm4_pwmb1: IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB1 { + pinmux = <0x401f8020 1 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio4_io03: IOMUXC_GPIO_EMC_03_GPIO4_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio9_io03: IOMUXC_GPIO_EMC_03_GPIO9_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 2 0x401f8504 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_in05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_IN05 { + pinmux = <0x401f8020 3 0x401f8618 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8020 3 0x401f8618 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio04: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8024 4 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexpwm4_pwma2: IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA2 { + pinmux = <0x401f8024 1 0x401f849c 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio4_io04: IOMUXC_GPIO_EMC_04_GPIO4_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio9_io04: IOMUXC_GPIO_EMC_04_GPIO9_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_data: IOMUXC_GPIO_EMC_04_SAI2_TX_DATA { + pinmux = <0x401f8024 2 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN06 { + pinmux = <0x401f8024 3 0x401f861c 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f8024 3 0x401f861c 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio05: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8028 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexpwm4_pwmb2: IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB2 { + pinmux = <0x401f8028 1 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio4_io05: IOMUXC_GPIO_EMC_05_GPIO4_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio9_io05: IOMUXC_GPIO_EMC_05_GPIO9_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 2 0x401f85c4 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN07 { + pinmux = <0x401f8028 3 0x401f8620 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8028 3 0x401f8620 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio06: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 { + pinmux = <0x401f802c 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexpwm2_pwma0: IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f802c 1 0x401f8478 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio4_io06: IOMUXC_GPIO_EMC_06_GPIO4_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio9_io06: IOMUXC_GPIO_EMC_06_GPIO9_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_bclk: IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK { + pinmux = <0x401f802c 2 0x401f85c0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN08 { + pinmux = <0x401f802c 3 0x401f8624 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f802c 3 0x401f8624 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio07: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 { + pinmux = <0x401f8030 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8030 1 0x401f8488 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio4_io07: IOMUXC_GPIO_EMC_07_GPIO4_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio9_io07: IOMUXC_GPIO_EMC_07_GPIO9_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_mclk: IOMUXC_GPIO_EMC_07_SAI2_MCLK { + pinmux = <0x401f8030 2 0x401f85b0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN09 { + pinmux = <0x401f8030 3 0x401f8628 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8030 3 0x401f8628 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio08: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8034 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexpwm2_pwma1: IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f8034 1 0x401f847c 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio4_io08: IOMUXC_GPIO_EMC_08_GPIO4_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio9_io08: IOMUXC_GPIO_EMC_08_GPIO9_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 2 0x401f85b8 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN17 { + pinmux = <0x401f8034 3 0x401f862c 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8034 3 0x401f862c 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_tx: IOMUXC_GPIO_EMC_09_FLEXCAN2_TX { + pinmux = <0x401f8038 3 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio09: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8038 4 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8038 1 0x401f848c 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio4_io09: IOMUXC_GPIO_EMC_09_GPIO4_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio9_io09: IOMUXC_GPIO_EMC_09_GPIO9_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_sync: IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC { + pinmux = <0x401f8038 2 0x401f85bc 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_addr00: IOMUXC_GPIO_EMC_09_SEMC_ADDR00 { + pinmux = <0x401f8038 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexcan2_rx: IOMUXC_GPIO_EMC_10_FLEXCAN2_RX { + pinmux = <0x401f803c 3 0x401f8450 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexio1_flexio10: IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 { + pinmux = <0x401f803c 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwma2: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f803c 1 0x401f8480 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio4_io10: IOMUXC_GPIO_EMC_10_GPIO4_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio9_io10: IOMUXC_GPIO_EMC_10_GPIO9_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai2_rx_bclk: IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK { + pinmux = <0x401f803c 2 0x401f85b4 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_addr01: IOMUXC_GPIO_EMC_10_SEMC_ADDR01 { + pinmux = <0x401f803c 0 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexio1_flexio11: IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 { + pinmux = <0x401f8040 4 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8040 1 0x401f8490 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio4_io11: IOMUXC_GPIO_EMC_11_GPIO4_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio9_io11: IOMUXC_GPIO_EMC_11_GPIO9_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_sda: IOMUXC_GPIO_EMC_11_LPI2C4_SDA { + pinmux = <0x401f8040 2 0x401f84e8 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_addr02: IOMUXC_GPIO_EMC_11_SEMC_ADDR02 { + pinmux = <0x401f8040 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_usdhc2_reset_b: IOMUXC_GPIO_EMC_11_USDHC2_RESET_B { + pinmux = <0x401f8040 3 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm1_pwma3: IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f8044 4 0x401f8454 1 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio4_io12: IOMUXC_GPIO_EMC_12_GPIO4_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio9_io12: IOMUXC_GPIO_EMC_12_GPIO9_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpi2c4_scl: IOMUXC_GPIO_EMC_12_LPI2C4_SCL { + pinmux = <0x401f8044 2 0x401f84e4 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_addr03: IOMUXC_GPIO_EMC_12_SEMC_ADDR03 { + pinmux = <0x401f8044 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_usdhc1_wp: IOMUXC_GPIO_EMC_12_USDHC1_WP { + pinmux = <0x401f8044 3 0x401f85d8 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in24: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN24 { + pinmux = <0x401f8044 1 0x401f8640 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8048 4 0x401f8464 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio4_io13: IOMUXC_GPIO_EMC_13_GPIO4_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio9_io13: IOMUXC_GPIO_EMC_13_GPIO9_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart3_tx: IOMUXC_GPIO_EMC_13_LPUART3_TX { + pinmux = <0x401f8048 2 0x401f853c 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_mqs_right: IOMUXC_GPIO_EMC_13_MQS_RIGHT { + pinmux = <0x401f8048 3 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_addr04: IOMUXC_GPIO_EMC_13_SEMC_ADDR04 { + pinmux = <0x401f8048 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in25: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN25 { + pinmux = <0x401f8048 1 0x401f8650 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio4_io14: IOMUXC_GPIO_EMC_14_GPIO4_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio9_io14: IOMUXC_GPIO_EMC_14_GPIO9_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart3_rx: IOMUXC_GPIO_EMC_14_LPUART3_RX { + pinmux = <0x401f804c 2 0x401f8538 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_mqs_left: IOMUXC_GPIO_EMC_14_MQS_LEFT { + pinmux = <0x401f804c 3 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_addr05: IOMUXC_GPIO_EMC_14_SEMC_ADDR05 { + pinmux = <0x401f804c 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN19 { + pinmux = <0x401f804c 1 0x401f8654 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f804c 1 0x401f8654 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio4_io15: IOMUXC_GPIO_EMC_15_GPIO4_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio9_io15: IOMUXC_GPIO_EMC_15_GPIO9_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart3_cts_b: IOMUXC_GPIO_EMC_15_LPUART3_CTS_B { + pinmux = <0x401f8050 2 0x401f8534 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_qtimer3_timer0: IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 { + pinmux = <0x401f8050 4 0x401f857c 0 0x401f8240>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr06: IOMUXC_GPIO_EMC_15_SEMC_ADDR06 { + pinmux = <0x401f8050 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_spdif_out: IOMUXC_GPIO_EMC_15_SPDIF_OUT { + pinmux = <0x401f8050 3 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in20: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN20 { + pinmux = <0x401f8050 1 0x401f8634 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio4_io16: IOMUXC_GPIO_EMC_16_GPIO4_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio9_io16: IOMUXC_GPIO_EMC_16_GPIO9_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_lpuart3_rts_b: IOMUXC_GPIO_EMC_16_LPUART3_RTS_B { + pinmux = <0x401f8054 2 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_qtimer3_timer1: IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 { + pinmux = <0x401f8054 4 0x401f8580 1 0x401f8244>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr07: IOMUXC_GPIO_EMC_16_SEMC_ADDR07 { + pinmux = <0x401f8054 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_spdif_in: IOMUXC_GPIO_EMC_16_SPDIF_IN { + pinmux = <0x401f8054 3 0x401f85c8 1 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_xbar1_xbar_in21: IOMUXC_GPIO_EMC_16_XBAR1_XBAR_IN21 { + pinmux = <0x401f8054 1 0x401f8658 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexcan1_tx: IOMUXC_GPIO_EMC_17_FLEXCAN1_TX { + pinmux = <0x401f8058 3 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexpwm4_pwma3: IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA3 { + pinmux = <0x401f8058 1 0x401f84a0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio4_io17: IOMUXC_GPIO_EMC_17_GPIO4_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio9_io17: IOMUXC_GPIO_EMC_17_GPIO9_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_lpuart4_cts_b: IOMUXC_GPIO_EMC_17_LPUART4_CTS_B { + pinmux = <0x401f8058 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_qtimer3_timer2: IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 { + pinmux = <0x401f8058 4 0x401f8584 0 0x401f8248>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr08: IOMUXC_GPIO_EMC_17_SEMC_ADDR08 { + pinmux = <0x401f8058 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexcan1_rx: IOMUXC_GPIO_EMC_18_FLEXCAN1_RX { + pinmux = <0x401f805c 3 0x401f844c 1 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexpwm4_pwmb3: IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB3 { + pinmux = <0x401f805c 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio4_io18: IOMUXC_GPIO_EMC_18_GPIO4_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio9_io18: IOMUXC_GPIO_EMC_18_GPIO9_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpuart4_rts_b: IOMUXC_GPIO_EMC_18_LPUART4_RTS_B { + pinmux = <0x401f805c 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_qtimer3_timer3: IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 { + pinmux = <0x401f805c 4 0x401f8588 0 0x401f824c>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr09: IOMUXC_GPIO_EMC_18_SEMC_ADDR09 { + pinmux = <0x401f805c 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_snvs_vio_5_ctl: IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL { + pinmux = <0x401f805c 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_enet_rx_data1: IOMUXC_GPIO_EMC_19_ENET_RX_DATA1 { + pinmux = <0x401f8060 3 0x401f8438 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexpwm2_pwma3: IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA3 { + pinmux = <0x401f8060 1 0x401f8474 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio4_io19: IOMUXC_GPIO_EMC_19_GPIO4_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio9_io19: IOMUXC_GPIO_EMC_19_GPIO9_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpuart4_tx: IOMUXC_GPIO_EMC_19_LPUART4_TX { + pinmux = <0x401f8060 2 0x401f8544 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_qtimer2_timer0: IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 { + pinmux = <0x401f8060 4 0x401f856c 0 0x401f8250>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr11: IOMUXC_GPIO_EMC_19_SEMC_ADDR11 { + pinmux = <0x401f8060 0 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_snvs_vio_5_b: IOMUXC_GPIO_EMC_19_SNVS_VIO_5_B { + pinmux = <0x401f8060 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_enet_rx_data0: IOMUXC_GPIO_EMC_20_ENET_RX_DATA0 { + pinmux = <0x401f8064 3 0x401f8434 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB3 { + pinmux = <0x401f8064 1 0x401f8484 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio4_io20: IOMUXC_GPIO_EMC_20_GPIO4_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio9_io20: IOMUXC_GPIO_EMC_20_GPIO9_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart4_rx: IOMUXC_GPIO_EMC_20_LPUART4_RX { + pinmux = <0x401f8064 2 0x401f8540 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_qtimer2_timer1: IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 { + pinmux = <0x401f8064 4 0x401f8570 0 0x401f8254>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr12: IOMUXC_GPIO_EMC_20_SEMC_ADDR12 { + pinmux = <0x401f8064 0 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_enet_tx_data1: IOMUXC_GPIO_EMC_21_ENET_TX_DATA1 { + pinmux = <0x401f8068 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm3_pwma3: IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA3 { + pinmux = <0x401f8068 1 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio4_io21: IOMUXC_GPIO_EMC_21_GPIO4_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio9_io21: IOMUXC_GPIO_EMC_21_GPIO9_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpi2c3_sda: IOMUXC_GPIO_EMC_21_LPI2C3_SDA { + pinmux = <0x401f8068 2 0x401f84e0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_qtimer2_timer2: IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 { + pinmux = <0x401f8068 4 0x401f8574 0 0x401f8258>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_ba0: IOMUXC_GPIO_EMC_21_SEMC_BA0 { + pinmux = <0x401f8068 0 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_enet_tx_data0: IOMUXC_GPIO_EMC_22_ENET_TX_DATA0 { + pinmux = <0x401f806c 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm3_pwmb3: IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB3 { + pinmux = <0x401f806c 1 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio4_io22: IOMUXC_GPIO_EMC_22_GPIO4_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio9_io22: IOMUXC_GPIO_EMC_22_GPIO9_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpi2c3_scl: IOMUXC_GPIO_EMC_22_LPI2C3_SCL { + pinmux = <0x401f806c 2 0x401f84dc 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_qtimer2_timer3: IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 { + pinmux = <0x401f806c 4 0x401f8578 0 0x401f825c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_ba1: IOMUXC_GPIO_EMC_22_SEMC_BA1 { + pinmux = <0x401f806c 0 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_enet_rx_en: IOMUXC_GPIO_EMC_23_ENET_RX_EN { + pinmux = <0x401f8070 3 0x401f843c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwma0: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA0 { + pinmux = <0x401f8070 1 0x401f8458 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio4_io23: IOMUXC_GPIO_EMC_23_GPIO4_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio9_io23: IOMUXC_GPIO_EMC_23_GPIO9_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpt1_capture2: IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 { + pinmux = <0x401f8070 4 0x401f875c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart5_tx: IOMUXC_GPIO_EMC_23_LPUART5_TX { + pinmux = <0x401f8070 2 0x401f854c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr10: IOMUXC_GPIO_EMC_23_SEMC_ADDR10 { + pinmux = <0x401f8070 0 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_enet_tx_en: IOMUXC_GPIO_EMC_24_ENET_TX_EN { + pinmux = <0x401f8074 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB0 { + pinmux = <0x401f8074 1 0x401f8468 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio4_io24: IOMUXC_GPIO_EMC_24_GPIO4_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio9_io24: IOMUXC_GPIO_EMC_24_GPIO9_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpt1_capture1: IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 { + pinmux = <0x401f8074 4 0x401f8758 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart5_rx: IOMUXC_GPIO_EMC_24_LPUART5_RX { + pinmux = <0x401f8074 2 0x401f8548 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_cas: IOMUXC_GPIO_EMC_24_SEMC_CAS { + pinmux = <0x401f8074 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_ref_clk: IOMUXC_GPIO_EMC_25_ENET_REF_CLK { + pinmux = <0x401f8078 4 0x401f842c 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_tx_clk: IOMUXC_GPIO_EMC_25_ENET_TX_CLK { + pinmux = <0x401f8078 3 0x401f8448 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwma1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA1 { + pinmux = <0x401f8078 1 0x401f845c 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio4_io25: IOMUXC_GPIO_EMC_25_GPIO4_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio9_io25: IOMUXC_GPIO_EMC_25_GPIO9_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart6_tx: IOMUXC_GPIO_EMC_25_LPUART6_TX { + pinmux = <0x401f8078 2 0x401f8554 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_ras: IOMUXC_GPIO_EMC_25_SEMC_RAS { + pinmux = <0x401f8078 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_enet_rx_er: IOMUXC_GPIO_EMC_26_ENET_RX_ER { + pinmux = <0x401f807c 3 0x401f8440 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio12: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 { + pinmux = <0x401f807c 4 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB1 { + pinmux = <0x401f807c 1 0x401f846c 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio4_io26: IOMUXC_GPIO_EMC_26_GPIO4_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio9_io26: IOMUXC_GPIO_EMC_26_GPIO9_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart6_rx: IOMUXC_GPIO_EMC_26_LPUART6_RX { + pinmux = <0x401f807c 2 0x401f8550 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_clk: IOMUXC_GPIO_EMC_26_SEMC_CLK { + pinmux = <0x401f807c 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio13: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8080 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwma2: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA2 { + pinmux = <0x401f8080 1 0x401f8460 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio4_io27: IOMUXC_GPIO_EMC_27_GPIO4_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio9_io27: IOMUXC_GPIO_EMC_27_GPIO9_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpspi1_sck: IOMUXC_GPIO_EMC_27_LPSPI1_SCK { + pinmux = <0x401f8080 3 0x401f84f0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart5_rts_b: IOMUXC_GPIO_EMC_27_LPUART5_RTS_B { + pinmux = <0x401f8080 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_cke: IOMUXC_GPIO_EMC_27_SEMC_CKE { + pinmux = <0x401f8080 0 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexio1_flexio14: IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8084 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB2 { + pinmux = <0x401f8084 1 0x401f8470 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio4_io28: IOMUXC_GPIO_EMC_28_GPIO4_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio9_io28: IOMUXC_GPIO_EMC_28_GPIO9_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpspi1_sdo: IOMUXC_GPIO_EMC_28_LPSPI1_SDO { + pinmux = <0x401f8084 3 0x401f84f8 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpuart5_cts_b: IOMUXC_GPIO_EMC_28_LPUART5_CTS_B { + pinmux = <0x401f8084 2 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_we: IOMUXC_GPIO_EMC_28_SEMC_WE { + pinmux = <0x401f8084 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexio1_flexio15: IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 { + pinmux = <0x401f8088 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm3_pwma0: IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA0 { + pinmux = <0x401f8088 1 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio4_io29: IOMUXC_GPIO_EMC_29_GPIO4_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio9_io29: IOMUXC_GPIO_EMC_29_GPIO9_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpspi1_sdi: IOMUXC_GPIO_EMC_29_LPSPI1_SDI { + pinmux = <0x401f8088 3 0x401f84f4 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpuart6_rts_b: IOMUXC_GPIO_EMC_29_LPUART6_RTS_B { + pinmux = <0x401f8088 2 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cs0: IOMUXC_GPIO_EMC_29_SEMC_CS0 { + pinmux = <0x401f8088 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_csi_data23: IOMUXC_GPIO_EMC_30_CSI_DATA23 { + pinmux = <0x401f808c 4 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_enet2_tx_data0: IOMUXC_GPIO_EMC_30_ENET2_TX_DATA0 { + pinmux = <0x401f808c 8 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm3_pwmb0: IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB0 { + pinmux = <0x401f808c 1 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio4_io30: IOMUXC_GPIO_EMC_30_GPIO4_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio9_io30: IOMUXC_GPIO_EMC_30_GPIO9_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpspi1_pcs0: IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 { + pinmux = <0x401f808c 3 0x401f84ec 1 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart6_cts_b: IOMUXC_GPIO_EMC_30_LPUART6_CTS_B { + pinmux = <0x401f808c 2 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_data08: IOMUXC_GPIO_EMC_30_SEMC_DATA08 { + pinmux = <0x401f808c 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_csi_data22: IOMUXC_GPIO_EMC_31_CSI_DATA22 { + pinmux = <0x401f8090 4 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_enet2_tx_data1: IOMUXC_GPIO_EMC_31_ENET2_TX_DATA1 { + pinmux = <0x401f8090 8 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm3_pwma1: IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA1 { + pinmux = <0x401f8090 1 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio4_io31: IOMUXC_GPIO_EMC_31_GPIO4_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio9_io31: IOMUXC_GPIO_EMC_31_GPIO9_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpspi1_pcs1: IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 { + pinmux = <0x401f8090 3 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart7_tx: IOMUXC_GPIO_EMC_31_LPUART7_TX { + pinmux = <0x401f8090 2 0x401f855c 1 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_data09: IOMUXC_GPIO_EMC_31_SEMC_DATA09 { + pinmux = <0x401f8090 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ccm_pmic_rdy: IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY { + pinmux = <0x401f8094 3 0x401f83fc 4 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_csi_data21: IOMUXC_GPIO_EMC_32_CSI_DATA21 { + pinmux = <0x401f8094 4 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_enet2_tx_en: IOMUXC_GPIO_EMC_32_ENET2_TX_EN { + pinmux = <0x401f8094 8 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_flexpwm3_pwmb1: IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB1 { + pinmux = <0x401f8094 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io18: IOMUXC_GPIO_EMC_32_GPIO3_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio8_io18: IOMUXC_GPIO_EMC_32_GPIO8_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart7_rx: IOMUXC_GPIO_EMC_32_LPUART7_RX { + pinmux = <0x401f8094 2 0x401f8558 1 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data10: IOMUXC_GPIO_EMC_32_SEMC_DATA10 { + pinmux = <0x401f8094 0 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_csi_data20: IOMUXC_GPIO_EMC_33_CSI_DATA20 { + pinmux = <0x401f8098 4 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_enet2_ref_clk2: IOMUXC_GPIO_EMC_33_ENET2_REF_CLK2 { + pinmux = <0x401f8098 9 0x401f870c 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_enet2_tx_clk: IOMUXC_GPIO_EMC_33_ENET2_TX_CLK { + pinmux = <0x401f8098 8 0x401f8728 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_flexpwm3_pwma2: IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA2 { + pinmux = <0x401f8098 1 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io19: IOMUXC_GPIO_EMC_33_GPIO3_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio8_io19: IOMUXC_GPIO_EMC_33_GPIO8_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_rx_data: IOMUXC_GPIO_EMC_33_SAI3_RX_DATA { + pinmux = <0x401f8098 3 0x401f8778 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data11: IOMUXC_GPIO_EMC_33_SEMC_DATA11 { + pinmux = <0x401f8098 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_usdhc1_reset_b: IOMUXC_GPIO_EMC_33_USDHC1_RESET_B { + pinmux = <0x401f8098 2 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_csi_data19: IOMUXC_GPIO_EMC_34_CSI_DATA19 { + pinmux = <0x401f809c 4 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_enet2_rx_er: IOMUXC_GPIO_EMC_34_ENET2_RX_ER { + pinmux = <0x401f809c 8 0x401f8720 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_flexpwm3_pwmb2: IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB2 { + pinmux = <0x401f809c 1 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io20: IOMUXC_GPIO_EMC_34_GPIO3_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio8_io20: IOMUXC_GPIO_EMC_34_GPIO8_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_rx_sync: IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC { + pinmux = <0x401f809c 3 0x401f877c 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data12: IOMUXC_GPIO_EMC_34_SEMC_DATA12 { + pinmux = <0x401f809c 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_usdhc1_vselect: IOMUXC_GPIO_EMC_34_USDHC1_VSELECT { + pinmux = <0x401f809c 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_csi_data18: IOMUXC_GPIO_EMC_35_CSI_DATA18 { + pinmux = <0x401f80a0 4 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_enet2_rx_data0: IOMUXC_GPIO_EMC_35_ENET2_RX_DATA0 { + pinmux = <0x401f80a0 8 0x401f8714 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io21: IOMUXC_GPIO_EMC_35_GPIO3_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio8_io21: IOMUXC_GPIO_EMC_35_GPIO8_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpt1_compare1: IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 { + pinmux = <0x401f80a0 2 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_sai3_rx_bclk: IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK { + pinmux = <0x401f80a0 3 0x401f8774 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data13: IOMUXC_GPIO_EMC_35_SEMC_DATA13 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc1_cd_b: IOMUXC_GPIO_EMC_35_USDHC1_CD_B { + pinmux = <0x401f80a0 6 0x401f85d4 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_in18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_IN18 { + pinmux = <0x401f80a0 1 0x401f8630 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80a0 1 0x401f8630 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_csi_data17: IOMUXC_GPIO_EMC_36_CSI_DATA17 { + pinmux = <0x401f80a4 4 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_enet2_rx_data1: IOMUXC_GPIO_EMC_36_ENET2_RX_DATA1 { + pinmux = <0x401f80a4 8 0x401f8718 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexcan3_tx: IOMUXC_GPIO_EMC_36_FLEXCAN3_TX { + pinmux = <0x401f80a4 9 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io22: IOMUXC_GPIO_EMC_36_GPIO3_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio8_io22: IOMUXC_GPIO_EMC_36_GPIO8_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpt1_compare2: IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 { + pinmux = <0x401f80a4 2 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_sai3_tx_data: IOMUXC_GPIO_EMC_36_SAI3_TX_DATA { + pinmux = <0x401f80a4 3 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data14: IOMUXC_GPIO_EMC_36_SEMC_DATA14 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 6 0x401f85d8 1 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_xbar1_xbar_in22: IOMUXC_GPIO_EMC_36_XBAR1_XBAR_IN22 { + pinmux = <0x401f80a4 1 0x401f8638 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_csi_data16: IOMUXC_GPIO_EMC_37_CSI_DATA16 { + pinmux = <0x401f80a8 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_enet2_rx_en: IOMUXC_GPIO_EMC_37_ENET2_RX_EN { + pinmux = <0x401f80a8 8 0x401f871c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexcan3_rx: IOMUXC_GPIO_EMC_37_FLEXCAN3_RX { + pinmux = <0x401f80a8 9 0x401f878c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io23: IOMUXC_GPIO_EMC_37_GPIO3_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio8_io23: IOMUXC_GPIO_EMC_37_GPIO8_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpt1_compare3: IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 { + pinmux = <0x401f80a8 2 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_sai3_mclk: IOMUXC_GPIO_EMC_37_SAI3_MCLK { + pinmux = <0x401f80a8 3 0x401f8770 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data15: IOMUXC_GPIO_EMC_37_SEMC_DATA15 { + pinmux = <0x401f80a8 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc2_wp: IOMUXC_GPIO_EMC_37_USDHC2_WP { + pinmux = <0x401f80a8 6 0x401f8608 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_xbar1_xbar_in23: IOMUXC_GPIO_EMC_37_XBAR1_XBAR_IN23 { + pinmux = <0x401f80a8 1 0x401f863c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_csi_field: IOMUXC_GPIO_EMC_38_CSI_FIELD { + pinmux = <0x401f80ac 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_enet2_mdc: IOMUXC_GPIO_EMC_38_ENET2_MDC { + pinmux = <0x401f80ac 8 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm1_pwma3: IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA3 { + pinmux = <0x401f80ac 1 0x401f8454 2 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io24: IOMUXC_GPIO_EMC_38_GPIO3_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio8_io24: IOMUXC_GPIO_EMC_38_GPIO8_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart8_tx: IOMUXC_GPIO_EMC_38_LPUART8_TX { + pinmux = <0x401f80ac 2 0x401f8564 2 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_sai3_tx_bclk: IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK { + pinmux = <0x401f80ac 3 0x401f8780 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_dm1: IOMUXC_GPIO_EMC_38_SEMC_DM1 { + pinmux = <0x401f80ac 0 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc2_vselect: IOMUXC_GPIO_EMC_38_USDHC2_VSELECT { + pinmux = <0x401f80ac 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_enet2_mdio: IOMUXC_GPIO_EMC_39_ENET2_MDIO { + pinmux = <0x401f80b0 8 0x401f8710 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB3 { + pinmux = <0x401f80b0 1 0x401f8464 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io25: IOMUXC_GPIO_EMC_39_GPIO3_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio8_io25: IOMUXC_GPIO_EMC_39_GPIO8_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart8_rx: IOMUXC_GPIO_EMC_39_LPUART8_RX { + pinmux = <0x401f80b0 2 0x401f8560 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_sai3_tx_sync: IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC { + pinmux = <0x401f80b0 3 0x401f8784 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs: IOMUXC_GPIO_EMC_39_SEMC_DQS { + pinmux = <0x401f80b0 0 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs4: IOMUXC_GPIO_EMC_39_SEMC_DQS4 { + pinmux = <0x401f80b0 9 0x401f8788 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usdhc2_cd_b: IOMUXC_GPIO_EMC_39_USDHC2_CD_B { + pinmux = <0x401f80b0 6 0x401f85e0 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdc: IOMUXC_GPIO_EMC_40_ENET_MDC { + pinmux = <0x401f80b4 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io26: IOMUXC_GPIO_EMC_40_GPIO3_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio8_io26: IOMUXC_GPIO_EMC_40_GPIO8_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt2_capture2: IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 { + pinmux = <0x401f80b4 1 0x401f8768 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_lpspi1_pcs2: IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 { + pinmux = <0x401f80b4 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_clk5: IOMUXC_GPIO_EMC_40_SEMC_CLK5 { + pinmux = <0x401f80b4 9 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_rdy: IOMUXC_GPIO_EMC_40_SEMC_RDY { + pinmux = <0x401f80b4 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usb_otg2_oc: IOMUXC_GPIO_EMC_40_USB_OTG2_OC { + pinmux = <0x401f80b4 3 0x401f85cc 1 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usdhc2_reset_b: IOMUXC_GPIO_EMC_40_USDHC2_RESET_B { + pinmux = <0x401f80b4 6 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdio: IOMUXC_GPIO_EMC_41_ENET_MDIO { + pinmux = <0x401f80b8 4 0x401f8430 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io27: IOMUXC_GPIO_EMC_41_GPIO3_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio8_io27: IOMUXC_GPIO_EMC_41_GPIO8_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt2_capture1: IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 { + pinmux = <0x401f80b8 1 0x401f8764 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_lpspi1_pcs3: IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 { + pinmux = <0x401f80b8 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_csx0: IOMUXC_GPIO_EMC_41_SEMC_CSX0 { + pinmux = <0x401f80b8 0 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usb_otg2_pwr: IOMUXC_GPIO_EMC_41_USB_OTG2_PWR { + pinmux = <0x401f80b8 3 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usdhc1_vselect: IOMUXC_GPIO_EMC_41_USDHC1_VSELECT { + pinmux = <0x401f80b8 6 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_enet2_tx_en: IOMUXC_GPIO_SD_B0_00_ENET2_TX_EN { + pinmux = <0x401f81bc 8 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexpwm1_pwma0: IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA0 { + pinmux = <0x401f81bc 1 0x401f8458 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f81bc 6 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io12: IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio8_io12: IOMUXC_GPIO_SD_B0_00_GPIO8_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f81bc 2 0x401f84dc 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpspi1_sck: IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK { + pinmux = <0x401f81bc 4 0x401f84f0 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_semc_dqs4: IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 { + pinmux = <0x401f81bc 9 0x401f8788 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_cmd: IOMUXC_GPIO_SD_B0_00_USDHC1_CMD { + pinmux = <0x401f81bc 0 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN04 { + pinmux = <0x401f81bc 3 0x401f8614 1 0x401f83ac>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f81bc 3 0x401f8614 1 0x401f83ac>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_enet2_ref_clk2: IOMUXC_GPIO_SD_B0_01_ENET2_REF_CLK2 { + pinmux = <0x401f81c0 9 0x401f870c 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_enet2_tx_clk: IOMUXC_GPIO_SD_B0_01_ENET2_TX_CLK { + pinmux = <0x401f81c0 8 0x401f8728 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexpwm1_pwmb0: IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB0 { + pinmux = <0x401f81c0 1 0x401f8468 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f81c0 6 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io13: IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio8_io13: IOMUXC_GPIO_SD_B0_01_GPIO8_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f81c0 2 0x401f84e0 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 { + pinmux = <0x401f81c0 4 0x401f84ec 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_clk: IOMUXC_GPIO_SD_B0_01_USDHC1_CLK { + pinmux = <0x401f81c0 0 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN05 { + pinmux = <0x401f81c0 3 0x401f8618 1 0x401f83b0>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f81c0 3 0x401f8618 1 0x401f83b0>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_enet2_rx_er: IOMUXC_GPIO_SD_B0_02_ENET2_RX_ER { + pinmux = <0x401f81c4 8 0x401f8720 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_flexpwm1_pwma1: IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA1 { + pinmux = <0x401f81c4 1 0x401f845c 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io14: IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio8_io14: IOMUXC_GPIO_SD_B0_02_GPIO8_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sdo: IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO { + pinmux = <0x401f81c4 4 0x401f84f8 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart8_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B { + pinmux = <0x401f81c4 2 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_semc_clk5: IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 { + pinmux = <0x401f81c4 9 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_data0: IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 { + pinmux = <0x401f81c4 0 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN06 { + pinmux = <0x401f81c4 3 0x401f861c 1 0x401f83b4>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f81c4 3 0x401f861c 1 0x401f83b4>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_enet2_rx_data0: IOMUXC_GPIO_SD_B0_03_ENET2_RX_DATA0 { + pinmux = <0x401f81c8 8 0x401f8714 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_flexpwm1_pwmb1: IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB1 { + pinmux = <0x401f81c8 1 0x401f846c 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io15: IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio8_io15: IOMUXC_GPIO_SD_B0_03_GPIO8_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_sdi: IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI { + pinmux = <0x401f81c8 4 0x401f84f4 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart8_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B { + pinmux = <0x401f81c8 2 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_semc_clk6: IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 { + pinmux = <0x401f81c8 9 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_data1: IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 { + pinmux = <0x401f81c8 0 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_in07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_IN07 { + pinmux = <0x401f81c8 3 0x401f8620 1 0x401f83b8>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_inout07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f81c8 3 0x401f8620 1 0x401f83b8>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_ccm_clko1: IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 { + pinmux = <0x401f81cc 6 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_enet2_rx_data1: IOMUXC_GPIO_SD_B0_04_ENET2_RX_DATA1 { + pinmux = <0x401f81cc 8 0x401f8718 1 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexpwm1_pwma2: IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA2 { + pinmux = <0x401f81cc 1 0x401f8460 1 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f81cc 4 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io16: IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio8_io16: IOMUXC_GPIO_SD_B0_04_GPIO8_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart8_tx: IOMUXC_GPIO_SD_B0_04_LPUART8_TX { + pinmux = <0x401f81cc 2 0x401f8564 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data2: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 { + pinmux = <0x401f81cc 0 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_in08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_IN08 { + pinmux = <0x401f81cc 3 0x401f8624 1 0x401f83bc>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_inout08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f81cc 3 0x401f8624 1 0x401f83bc>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_ccm_clko2: IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 { + pinmux = <0x401f81d0 6 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_enet2_rx_en: IOMUXC_GPIO_SD_B0_05_ENET2_RX_EN { + pinmux = <0x401f81d0 8 0x401f871c 1 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexpwm1_pwmb2: IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB2 { + pinmux = <0x401f81d0 1 0x401f8470 1 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f81d0 4 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io17: IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio8_io17: IOMUXC_GPIO_SD_B0_05_GPIO8_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart8_rx: IOMUXC_GPIO_SD_B0_05_LPUART8_RX { + pinmux = <0x401f81d0 2 0x401f8560 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data3: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 { + pinmux = <0x401f81d0 0 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_in09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_IN09 { + pinmux = <0x401f81d0 3 0x401f8628 1 0x401f83c0>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_inout09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f81d0 3 0x401f8628 1 0x401f83c0>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f81d4 2 0x401f8454 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f81d4 1 0x401f84c4 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io00: IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio8_io00: IOMUXC_GPIO_SD_B1_00_GPIO8_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart4_tx: IOMUXC_GPIO_SD_B1_00_LPUART4_TX { + pinmux = <0x401f81d4 4 0x401f8544 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai1_tx_data3: IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA3 { + pinmux = <0x401f81d4 3 0x401f8598 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai3_rx_data: IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA { + pinmux = <0x401f81d4 8 0x401f8778 1 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data3: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 { + pinmux = <0x401f81d4 0 0x401f85f4 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f81d8 2 0x401f8464 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_data2: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 { + pinmux = <0x401f81d8 1 0x401f84c0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io01: IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio8_io01: IOMUXC_GPIO_SD_B1_01_GPIO8_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart4_rx: IOMUXC_GPIO_SD_B1_01_LPUART4_RX { + pinmux = <0x401f81d8 4 0x401f8540 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai1_tx_data2: IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA2 { + pinmux = <0x401f81d8 3 0x401f859c 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai3_tx_data: IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA { + pinmux = <0x401f81d8 8 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data2: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 { + pinmux = <0x401f81d8 0 0x401f85f0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_wait: IOMUXC_GPIO_SD_B1_02_CCM_WAIT { + pinmux = <0x401f81dc 6 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexcan1_tx: IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX { + pinmux = <0x401f81dc 4 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f81dc 2 0x401f8474 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data1: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 { + pinmux = <0x401f81dc 1 0x401f84bc 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io02: IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio8_io02: IOMUXC_GPIO_SD_B1_02_GPIO8_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai1_tx_data1: IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA1 { + pinmux = <0x401f81dc 3 0x401f85a0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai3_tx_sync: IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC { + pinmux = <0x401f81dc 8 0x401f8784 1 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_data1: IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 { + pinmux = <0x401f81dc 0 0x401f85ec 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_03_CCM_PMIC_RDY { + pinmux = <0x401f81e0 6 0x401f83fc 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexcan1_rx: IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX { + pinmux = <0x401f81e0 4 0x401f844c 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f81e0 2 0x401f8484 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data0: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 { + pinmux = <0x401f81e0 1 0x401f84b8 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io03: IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio8_io03: IOMUXC_GPIO_SD_B1_03_GPIO8_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai1_mclk: IOMUXC_GPIO_SD_B1_03_SAI1_MCLK { + pinmux = <0x401f81e0 3 0x401f858c 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK { + pinmux = <0x401f81e0 8 0x401f8780 1 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_data0: IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 { + pinmux = <0x401f81e0 0 0x401f85e8 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_stop: IOMUXC_GPIO_SD_B1_04_CCM_STOP { + pinmux = <0x401f81e4 6 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI_A_SS1_B { + pinmux = <0x401f81e4 4 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK { + pinmux = <0x401f81e4 1 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io04: IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio8_io04: IOMUXC_GPIO_SD_B1_04_GPIO8_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_lpi2c1_scl: IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL { + pinmux = <0x401f81e4 2 0x401f84cc 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai1_rx_sync: IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f81e4 3 0x401f85a4 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai3_mclk: IOMUXC_GPIO_SD_B1_04_SAI3_MCLK { + pinmux = <0x401f81e4 8 0x401f8770 1 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_clk: IOMUXC_GPIO_SD_B1_04_USDHC2_CLK { + pinmux = <0x401f81e4 0 0x401f85dc 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f81e8 1 0x401f84a4 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f81e8 4 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io05: IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio8_io05: IOMUXC_GPIO_SD_B1_05_GPIO8_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_lpi2c1_sda: IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA { + pinmux = <0x401f81e8 2 0x401f84d0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai1_rx_bclk: IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK { + pinmux = <0x401f81e8 3 0x401f8590 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_rx_sync: IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC { + pinmux = <0x401f81e8 8 0x401f877c 1 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_cmd: IOMUXC_GPIO_SD_B1_05_USDHC2_CMD { + pinmux = <0x401f81e8 0 0x401f85e4 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B { + pinmux = <0x401f81ec 1 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io06: IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio8_io06: IOMUXC_GPIO_SD_B1_06_GPIO8_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f81ec 4 0x401f84fc 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpuart7_cts_b: IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B { + pinmux = <0x401f81ec 2 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai1_rx_data0: IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA0 { + pinmux = <0x401f81ec 3 0x401f8594 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK { + pinmux = <0x401f81ec 8 0x401f8774 1 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B { + pinmux = <0x401f81ec 0 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f81f0 1 0x401f84c8 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io07: IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio8_io07: IOMUXC_GPIO_SD_B1_07_GPIO8_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f81f0 4 0x401f8500 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpuart7_rts_b: IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B { + pinmux = <0x401f81f0 2 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai1_tx_data0: IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA0 { + pinmux = <0x401f81f0 3 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_semc_csx1: IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 { + pinmux = <0x401f81f0 0 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f81f4 1 0x401f84a8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io08: IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio8_io08: IOMUXC_GPIO_SD_B1_08_GPIO8_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f81f4 4 0x401f8508 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpuart7_tx: IOMUXC_GPIO_SD_B1_08_LPUART7_TX { + pinmux = <0x401f81f4 2 0x401f855c 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai1_tx_bclk: IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK { + pinmux = <0x401f81f4 3 0x401f85a8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_semc_csx2: IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 { + pinmux = <0x401f81f4 6 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f81f4 0 0x401f85f8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data1: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 { + pinmux = <0x401f81f8 1 0x401f84ac 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io09: IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio8_io09: IOMUXC_GPIO_SD_B1_09_GPIO8_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f81f8 4 0x401f8504 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpuart7_rx: IOMUXC_GPIO_SD_B1_09_LPUART7_RX { + pinmux = <0x401f81f8 2 0x401f8558 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai1_tx_sync: IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC { + pinmux = <0x401f81f8 3 0x401f85ac 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f81f8 0 0x401f85fc 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data2: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 { + pinmux = <0x401f81fc 1 0x401f84b0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io10: IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio8_io10: IOMUXC_GPIO_SD_B1_10_GPIO8_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpi2c2_sda: IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA { + pinmux = <0x401f81fc 3 0x401f84d8 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f81fc 4 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpuart2_rx: IOMUXC_GPIO_SD_B1_10_LPUART2_RX { + pinmux = <0x401f81fc 2 0x401f852c 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f81fc 0 0x401f8600 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_data3: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 { + pinmux = <0x401f8200 1 0x401f84b4 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io11: IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio8_io11: IOMUXC_GPIO_SD_B1_11_GPIO8_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpi2c2_scl: IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL { + pinmux = <0x401f8200 3 0x401f84d4 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8200 4 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpuart2_tx: IOMUXC_GPIO_SD_B1_11_LPUART2_TX { + pinmux = <0x401f8200 2 0x401f8530 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8200 0 0x401f8604 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_ccm_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ { + pinmux = <0x400a8008 0 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_gpio5_io02: IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 { + pinmux = <0x400a8008 5 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x0 0 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1064dvj6b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1064dvj6b-pinctrl.dtsi new file mode 100644 index 000000000..9717c5e9b --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1064dvj6b-pinctrl.dtsi @@ -0,0 +1,3925 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1064DVJ6B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_acmp1_in4: IOMUXC_GPIO_AD_B0_00_ACMP1_IN4 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA3 { + pinmux = <0x401f80bc 0 0x401f8474 2 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + gpr = <0x400ac068 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio6_io00: IOMUXC_GPIO_AD_B0_00_GPIO6_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + gpr = <0x400ac068 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_lpi2c1_scls: IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS { + pinmux = <0x401f80bc 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_lpspi3_sck: IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK { + pinmux = <0x401f80bc 7 0x401f8510 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_ref_32k_out: IOMUXC_GPIO_AD_B0_00_REF_32K_OUT { + pinmux = <0x401f80bc 2 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_usb_otg2_id: IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID { + pinmux = <0x401f80bc 3 0x401f83f8 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_usdhc1_reset_b: IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B { + pinmux = <0x401f80bc 6 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_xbar1_xbar_in14: IOMUXC_GPIO_AD_B0_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f80bc 1 0x401f8644 0 0x401f82ac>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_xbar1_xbar_inout14: IOMUXC_GPIO_AD_B0_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f80bc 1 0x401f8644 0 0x401f82ac>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_acmp2_in4: IOMUXC_GPIO_AD_B0_01_ACMP2_IN4 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_ewm_out_b: IOMUXC_GPIO_AD_B0_01_EWM_OUT_B { + pinmux = <0x401f80c0 6 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_flexpwm2_pwmb3: IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB3 { + pinmux = <0x401f80c0 0 0x401f8484 2 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + gpr = <0x400ac068 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio6_io01: IOMUXC_GPIO_AD_B0_01_GPIO6_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + gpr = <0x400ac068 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_lpi2c1_sdas: IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS { + pinmux = <0x401f80c0 4 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_lpspi3_sdo: IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO { + pinmux = <0x401f80c0 7 0x401f8518 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_ref_24m_out: IOMUXC_GPIO_AD_B0_01_REF_24M_OUT { + pinmux = <0x401f80c0 2 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_usb_otg1_id: IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID { + pinmux = <0x401f80c0 3 0x401f83f4 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_xbar1_xbar_in15: IOMUXC_GPIO_AD_B0_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f80c0 1 0x401f8648 0 0x401f82b0>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_xbar1_xbar_inout15: IOMUXC_GPIO_AD_B0_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f80c0 1 0x401f8648 0 0x401f82b0>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_acmp3_in4: IOMUXC_GPIO_AD_B0_02_ACMP3_IN4 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_flexcan2_tx: IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX { + pinmux = <0x401f80c4 0 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_flexpwm1_pwmx0: IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX0 { + pinmux = <0x401f80c4 4 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + gpr = <0x400ac068 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio6_io02: IOMUXC_GPIO_AD_B0_02_GPIO6_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + gpr = <0x400ac068 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpi2c1_hreq: IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ { + pinmux = <0x401f80c4 6 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpspi3_sdi: IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI { + pinmux = <0x401f80c4 7 0x401f8514 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpuart6_tx: IOMUXC_GPIO_AD_B0_02_LPUART6_TX { + pinmux = <0x401f80c4 2 0x401f8554 1 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR { + pinmux = <0x401f80c4 3 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_xbar1_xbar_in16: IOMUXC_GPIO_AD_B0_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f80c4 1 0x401f864c 0 0x401f82b4>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_xbar1_xbar_inout16: IOMUXC_GPIO_AD_B0_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f80c4 1 0x401f864c 0 0x401f82b4>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_acmp4_in4: IOMUXC_GPIO_AD_B0_03_ACMP4_IN4 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_flexcan2_rx: IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX { + pinmux = <0x401f80c8 0 0x401f8450 1 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_flexpwm1_pwmx1: IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX1 { + pinmux = <0x401f80c8 4 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + gpr = <0x400ac068 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio6_io03: IOMUXC_GPIO_AD_B0_03_GPIO6_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + gpr = <0x400ac068 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_lpspi3_pcs0: IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 { + pinmux = <0x401f80c8 7 0x401f850c 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_lpuart6_rx: IOMUXC_GPIO_AD_B0_03_LPUART6_RX { + pinmux = <0x401f80c8 2 0x401f8550 1 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ref_24m_out: IOMUXC_GPIO_AD_B0_03_REF_24M_OUT { + pinmux = <0x401f80c8 6 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 3 0x401f85d0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f80c8 1 0x401f862c 1 0x401f82b8>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80c8 1 0x401f862c 1 0x401f82b8>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_csi_data09: IOMUXC_GPIO_AD_B0_04_CSI_DATA09 { + pinmux = <0x401f80cc 4 0x401f841c 1 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_tx_data3: IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA3 { + pinmux = <0x401f80cc 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio6_io04: IOMUXC_GPIO_AD_B0_04_GPIO6_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_lpspi3_pcs1: IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 { + pinmux = <0x401f80cc 7 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_mqs_right: IOMUXC_GPIO_AD_B0_04_MQS_RIGHT { + pinmux = <0x401f80cc 1 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_pit_trigger0: IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER0 { + pinmux = <0x401f80cc 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_sai2_tx_sync: IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC { + pinmux = <0x401f80cc 3 0x401f85c4 1 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_src_boot_mode0: IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE0 { + pinmux = <0x401f80cc 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_csi_data08: IOMUXC_GPIO_AD_B0_05_CSI_DATA08 { + pinmux = <0x401f80d0 4 0x401f8418 1 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_tx_data2: IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA2 { + pinmux = <0x401f80d0 2 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio6_io05: IOMUXC_GPIO_AD_B0_05_GPIO6_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_lpspi3_pcs2: IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 { + pinmux = <0x401f80d0 7 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_mqs_left: IOMUXC_GPIO_AD_B0_05_MQS_LEFT { + pinmux = <0x401f80d0 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_sai2_tx_bclk: IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f80d0 3 0x401f85c0 1 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_src_boot_mode1: IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE1 { + pinmux = <0x401f80d0 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_IN17 { + pinmux = <0x401f80d0 6 0x401f862c 2 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80d0 6 0x401f862c 2 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_csi_data07: IOMUXC_GPIO_AD_B0_06_CSI_DATA07 { + pinmux = <0x401f80d4 4 0x401f8414 1 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_enet_rx_clk: IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK { + pinmux = <0x401f80d4 2 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio6_io06: IOMUXC_GPIO_AD_B0_06_GPIO6_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpt2_compare1: IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 { + pinmux = <0x401f80d4 1 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_jtag_tms: IOMUXC_GPIO_AD_B0_06_JTAG_TMS { + pinmux = <0x401f80d4 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpspi3_pcs3: IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 { + pinmux = <0x401f80d4 7 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_sai2_rx_bclk: IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK { + pinmux = <0x401f80d4 3 0x401f85b4 1 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_in18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_IN18 { + pinmux = <0x401f80d4 6 0x401f8630 1 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_inout18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80d4 6 0x401f8630 1 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_csi_data06: IOMUXC_GPIO_AD_B0_07_CSI_DATA06 { + pinmux = <0x401f80d8 4 0x401f8410 1 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_1588_event3_out: IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT { + pinmux = <0x401f80d8 7 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_tx_er: IOMUXC_GPIO_AD_B0_07_ENET_TX_ER { + pinmux = <0x401f80d8 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio6_io07: IOMUXC_GPIO_AD_B0_07_GPIO6_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpt2_compare2: IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 { + pinmux = <0x401f80d8 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_jtag_tck: IOMUXC_GPIO_AD_B0_07_JTAG_TCK { + pinmux = <0x401f80d8 0 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_sai2_rx_sync: IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC { + pinmux = <0x401f80d8 3 0x401f85bc 1 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_in19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_IN19 { + pinmux = <0x401f80d8 6 0x401f8654 1 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_inout19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80d8 6 0x401f8654 1 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_csi_data05: IOMUXC_GPIO_AD_B0_08_CSI_DATA05 { + pinmux = <0x401f80dc 4 0x401f840c 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_1588_event3_in: IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN { + pinmux = <0x401f80dc 7 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_rx_data3: IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA3 { + pinmux = <0x401f80dc 2 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio6_io08: IOMUXC_GPIO_AD_B0_08_GPIO6_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpt2_compare3: IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 { + pinmux = <0x401f80dc 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_jtag_mod: IOMUXC_GPIO_AD_B0_08_JTAG_MOD { + pinmux = <0x401f80dc 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_sai2_rx_data: IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA { + pinmux = <0x401f80dc 3 0x401f85b8 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_xbar1_xbar_in20: IOMUXC_GPIO_AD_B0_08_XBAR1_XBAR_IN20 { + pinmux = <0x401f80dc 6 0x401f8634 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_csi_data04: IOMUXC_GPIO_AD_B0_09_CSI_DATA04 { + pinmux = <0x401f80e0 4 0x401f8408 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data2: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA2 { + pinmux = <0x401f80e0 2 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA3 { + pinmux = <0x401f80e0 1 0x401f8474 3 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio6_io09: IOMUXC_GPIO_AD_B0_09_GPIO6_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpt2_clk: IOMUXC_GPIO_AD_B0_09_GPT2_CLK { + pinmux = <0x401f80e0 7 0x401f876c 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_jtag_tdi: IOMUXC_GPIO_AD_B0_09_JTAG_TDI { + pinmux = <0x401f80e0 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_sai2_tx_data: IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA { + pinmux = <0x401f80e0 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_semc_dqs4: IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 { + pinmux = <0x401f80e0 9 0x401f8788 2 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_xbar1_xbar_in21: IOMUXC_GPIO_AD_B0_09_XBAR1_XBAR_IN21 { + pinmux = <0x401f80e0 6 0x401f8658 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_swo: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO { + pinmux = <0x401f80e4 9 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_csi_data03: IOMUXC_GPIO_AD_B0_10_CSI_DATA03 { + pinmux = <0x401f80e4 4 0x401f8404 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80e4 7 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_crs: IOMUXC_GPIO_AD_B0_10_ENET_CRS { + pinmux = <0x401f80e4 2 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexcan3_tx: IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX { + pinmux = <0x401f80e4 8 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm1_pwma3: IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA3 { + pinmux = <0x401f80e4 1 0x401f8454 3 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio6_io10: IOMUXC_GPIO_AD_B0_10_GPIO6_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_jtag_tdo: IOMUXC_GPIO_AD_B0_10_JTAG_TDO { + pinmux = <0x401f80e4 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_sai2_mclk: IOMUXC_GPIO_AD_B0_10_SAI2_MCLK { + pinmux = <0x401f80e4 3 0x401f85b0 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_xbar1_xbar_in22: IOMUXC_GPIO_AD_B0_10_XBAR1_XBAR_IN22 { + pinmux = <0x401f80e4 6 0x401f8638 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_csi_data02: IOMUXC_GPIO_AD_B0_11_CSI_DATA02 { + pinmux = <0x401f80e8 4 0x401f8400 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN { + pinmux = <0x401f80e8 7 0x401f8444 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_col: IOMUXC_GPIO_AD_B0_11_ENET_COL { + pinmux = <0x401f80e8 2 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexcan3_rx: IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX { + pinmux = <0x401f80e8 8 0x401f878c 2 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB3 { + pinmux = <0x401f80e8 1 0x401f8464 3 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio6_io11: IOMUXC_GPIO_AD_B0_11_GPIO6_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_jtag_trstb: IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB { + pinmux = <0x401f80e8 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_semc_clk6: IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 { + pinmux = <0x401f80e8 9 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_wdog1_b: IOMUXC_GPIO_AD_B0_11_WDOG1_B { + pinmux = <0x401f80e8 3 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_xbar1_xbar_in23: IOMUXC_GPIO_AD_B0_11_XBAR1_XBAR_IN23 { + pinmux = <0x401f80e8 6 0x401f863c 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in1: IOMUXC_GPIO_AD_B0_12_ADC1_IN1 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_nmi: IOMUXC_GPIO_AD_B0_12_ARM_NMI { + pinmux = <0x401f80ec 7 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_12_CCM_PMIC_RDY { + pinmux = <0x401f80ec 1 0x401f83fc 1 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_1588_event1_out: IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT { + pinmux = <0x401f80ec 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm1_pwmx2: IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX2 { + pinmux = <0x401f80ec 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio6_io12: IOMUXC_GPIO_AD_B0_12_GPIO6_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpi2c4_scl: IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL { + pinmux = <0x401f80ec 0 0x401f84e4 1 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart1_tx: IOMUXC_GPIO_AD_B0_12_LPUART1_TX { + pinmux = <0x401f80ec 2 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_wdog2_b: IOMUXC_GPIO_AD_B0_12_WDOG2_B { + pinmux = <0x401f80ec 3 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_acmp1_in2: IOMUXC_GPIO_AD_B0_13_ACMP1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc1_in2: IOMUXC_GPIO_AD_B0_13_ADC1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_1588_event1_in: IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN { + pinmux = <0x401f80f0 6 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ewm_out_b: IOMUXC_GPIO_AD_B0_13_EWM_OUT_B { + pinmux = <0x401f80f0 3 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm1_pwmx3: IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX3 { + pinmux = <0x401f80f0 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio6_io13: IOMUXC_GPIO_AD_B0_13_GPIO6_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpt1_clk: IOMUXC_GPIO_AD_B0_13_GPT1_CLK { + pinmux = <0x401f80f0 1 0x401f8760 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpi2c4_sda: IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA { + pinmux = <0x401f80f0 0 0x401f84e8 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart1_rx: IOMUXC_GPIO_AD_B0_13_LPUART1_RX { + pinmux = <0x401f80f0 2 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ref_24m_out: IOMUXC_GPIO_AD_B0_13_REF_24M_OUT { + pinmux = <0x401f80f0 7 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in2: IOMUXC_GPIO_AD_B0_14_ACMP2_IN2 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in3: IOMUXC_GPIO_AD_B0_14_ADC1_IN3 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_csi_vsync: IOMUXC_GPIO_AD_B0_14_CSI_VSYNC { + pinmux = <0x401f80f4 4 0x401f8428 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80f4 3 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan3_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX { + pinmux = <0x401f80f4 8 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio6_io14: IOMUXC_GPIO_AD_B0_14_GPIO6_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B { + pinmux = <0x401f80f4 2 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_usb_otg2_oc: IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC { + pinmux = <0x401f80f4 0 0x401f85cc 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_xbar1_xbar_in24: IOMUXC_GPIO_AD_B0_14_XBAR1_XBAR_IN24 { + pinmux = <0x401f80f4 1 0x401f8640 1 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in2: IOMUXC_GPIO_AD_B0_15_ACMP3_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in4: IOMUXC_GPIO_AD_B0_15_ADC1_IN4 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_csi_hsync: IOMUXC_GPIO_AD_B0_15_CSI_HSYNC { + pinmux = <0x401f80f8 4 0x401f8420 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f80f8 3 0x401f8444 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 6 0x401f8450 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan3_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX { + pinmux = <0x401f80f8 8 0x401f878c 1 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio6_io15: IOMUXC_GPIO_AD_B0_15_GPIO6_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B { + pinmux = <0x401f80f8 2 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_usb_otg2_pwr: IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR { + pinmux = <0x401f80f8 0 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb: IOMUXC_GPIO_AD_B0_15_WDOG1_RST_B_DEB { + pinmux = <0x401f80f8 7 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_xbar1_xbar_in25: IOMUXC_GPIO_AD_B0_15_XBAR1_XBAR_IN25 { + pinmux = <0x401f80f8 1 0x401f8650 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp4_in2: IOMUXC_GPIO_AD_B1_00_ACMP4_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc1_in5: IOMUXC_GPIO_AD_B1_00_ADC1_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc2_in5: IOMUXC_GPIO_AD_B1_00_ADC2_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_enet2_1588_event0_out: IOMUXC_GPIO_AD_B1_00_ENET2_1588_EVENT0_OUT { + pinmux = <0x401f80fc 8 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio3_flexio00: IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 { + pinmux = <0x401f80fc 9 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio6_io16: IOMUXC_GPIO_AD_B1_00_GPIO6_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_kpp_row7: IOMUXC_GPIO_AD_B1_00_KPP_ROW7 { + pinmux = <0x401f80fc 7 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpi2c1_scl: IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL { + pinmux = <0x401f80fc 3 0x401f84cc 1 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B { + pinmux = <0x401f80fc 2 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_qtimer3_timer0: IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 { + pinmux = <0x401f80fc 1 0x401f857c 1 0x401f82ec>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usb_otg2_id: IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID { + pinmux = <0x401f80fc 0 0x401f83f8 1 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usdhc1_wp: IOMUXC_GPIO_AD_B1_00_USDHC1_WP { + pinmux = <0x401f80fc 6 0x401f85d8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_wdog1_b: IOMUXC_GPIO_AD_B1_00_WDOG1_B { + pinmux = <0x401f80fc 4 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp1_in0: IOMUXC_GPIO_AD_B1_01_ACMP1_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in0: IOMUXC_GPIO_AD_B1_01_ACMP2_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp3_in0: IOMUXC_GPIO_AD_B1_01_ACMP3_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp4_in0: IOMUXC_GPIO_AD_B1_01_ACMP4_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in6: IOMUXC_GPIO_AD_B1_01_ADC1_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc2_in6: IOMUXC_GPIO_AD_B1_01_ADC2_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_01_CCM_PMIC_RDY { + pinmux = <0x401f8100 4 0x401f83fc 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_enet2_1588_event0_in: IOMUXC_GPIO_AD_B1_01_ENET2_1588_EVENT0_IN { + pinmux = <0x401f8100 8 0x401f8724 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio3_flexio01: IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 { + pinmux = <0x401f8100 9 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio6_io17: IOMUXC_GPIO_AD_B1_01_GPIO6_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_kpp_col7: IOMUXC_GPIO_AD_B1_01_KPP_COL7 { + pinmux = <0x401f8100 7 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpi2c1_sda: IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA { + pinmux = <0x401f8100 3 0x401f84d0 1 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B { + pinmux = <0x401f8100 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_qtimer3_timer1: IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 { + pinmux = <0x401f8100 1 0x401f8580 0 0x401f82f0>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR { + pinmux = <0x401f8100 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usdhc1_vselect: IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT { + pinmux = <0x401f8100 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp1_in3: IOMUXC_GPIO_AD_B1_02_ACMP1_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc1_in7: IOMUXC_GPIO_AD_B1_02_ADC1_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in7: IOMUXC_GPIO_AD_B1_02_ADC2_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT { + pinmux = <0x401f8104 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio3_flexio02: IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 { + pinmux = <0x401f8104 9 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio6_io18: IOMUXC_GPIO_AD_B1_02_GPIO6_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpt2_clk: IOMUXC_GPIO_AD_B1_02_GPT2_CLK { + pinmux = <0x401f8104 8 0x401f876c 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_kpp_row6: IOMUXC_GPIO_AD_B1_02_KPP_ROW6 { + pinmux = <0x401f8104 7 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpuart2_tx: IOMUXC_GPIO_AD_B1_02_LPUART2_TX { + pinmux = <0x401f8104 2 0x401f8530 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_qtimer3_timer2: IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 { + pinmux = <0x401f8104 1 0x401f8584 1 0x401f82f4>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_spdif_out: IOMUXC_GPIO_AD_B1_02_SPDIF_OUT { + pinmux = <0x401f8104 3 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usb_otg1_id: IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID { + pinmux = <0x401f8104 0 0x401f83f4 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B { + pinmux = <0x401f8104 6 0x401f85d4 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp2_in3: IOMUXC_GPIO_AD_B1_03_ACMP2_IN3 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in8: IOMUXC_GPIO_AD_B1_03_ADC1_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc2_in8: IOMUXC_GPIO_AD_B1_03_ADC2_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN { + pinmux = <0x401f8108 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio3_flexio03: IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 { + pinmux = <0x401f8108 9 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio6_io19: IOMUXC_GPIO_AD_B1_03_GPIO6_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpt2_capture1: IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 { + pinmux = <0x401f8108 8 0x401f8764 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_kpp_col6: IOMUXC_GPIO_AD_B1_03_KPP_COL6 { + pinmux = <0x401f8108 7 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpuart2_rx: IOMUXC_GPIO_AD_B1_03_LPUART2_RX { + pinmux = <0x401f8108 2 0x401f852c 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_qtimer3_timer3: IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 { + pinmux = <0x401f8108 1 0x401f8588 1 0x401f82f8>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_spdif_in: IOMUXC_GPIO_AD_B1_03_SPDIF_IN { + pinmux = <0x401f8108 3 0x401f85c8 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usb_otg1_oc: IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC { + pinmux = <0x401f8108 0 0x401f85d0 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B { + pinmux = <0x401f8108 6 0x401f85e0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp3_in3: IOMUXC_GPIO_AD_B1_04_ACMP3_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc1_in9: IOMUXC_GPIO_AD_B1_04_ADC1_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in9: IOMUXC_GPIO_AD_B1_04_ADC2_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_csi_pixclk: IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK { + pinmux = <0x401f810c 4 0x401f8424 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_enet_mdc: IOMUXC_GPIO_AD_B1_04_ENET_MDC { + pinmux = <0x401f810c 1 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio3_flexio04: IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 { + pinmux = <0x401f810c 9 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_b_data3: IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 { + pinmux = <0x401f810c 0 0x401f84c4 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio6_io20: IOMUXC_GPIO_AD_B1_04_GPIO6_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpt2_capture2: IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 { + pinmux = <0x401f810c 8 0x401f8768 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_kpp_row5: IOMUXC_GPIO_AD_B1_04_KPP_ROW5 { + pinmux = <0x401f810c 7 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpuart3_cts_b: IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B { + pinmux = <0x401f810c 2 0x401f8534 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_spdif_sr_clk: IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK { + pinmux = <0x401f810c 3 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_usdhc2_data0: IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f810c 6 0x401f85e8 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp4_in3: IOMUXC_GPIO_AD_B1_05_ACMP4_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in10: IOMUXC_GPIO_AD_B1_05_ADC1_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in10: IOMUXC_GPIO_AD_B1_05_ADC2_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_csi_mclk: IOMUXC_GPIO_AD_B1_05_CSI_MCLK { + pinmux = <0x401f8110 4 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_enet_mdio: IOMUXC_GPIO_AD_B1_05_ENET_MDIO { + pinmux = <0x401f8110 1 0x401f8430 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio3_flexio05: IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 { + pinmux = <0x401f8110 9 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_b_data2: IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 { + pinmux = <0x401f8110 0 0x401f84c0 1 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio6_io21: IOMUXC_GPIO_AD_B1_05_GPIO6_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpt2_compare1: IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 { + pinmux = <0x401f8110 8 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_kpp_col5: IOMUXC_GPIO_AD_B1_05_KPP_COL5 { + pinmux = <0x401f8110 7 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpuart3_rts_b: IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B { + pinmux = <0x401f8110 2 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_spdif_out: IOMUXC_GPIO_AD_B1_05_SPDIF_OUT { + pinmux = <0x401f8110 3 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc2_data1: IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f8110 6 0x401f85ec 1 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp1_in1: IOMUXC_GPIO_AD_B1_06_ACMP1_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp2_in1: IOMUXC_GPIO_AD_B1_06_ACMP2_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in1: IOMUXC_GPIO_AD_B1_06_ACMP3_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp4_in1: IOMUXC_GPIO_AD_B1_06_ACMP4_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in11: IOMUXC_GPIO_AD_B1_06_ADC1_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in11: IOMUXC_GPIO_AD_B1_06_ADC2_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_csi_vsync: IOMUXC_GPIO_AD_B1_06_CSI_VSYNC { + pinmux = <0x401f8114 4 0x401f8428 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio3_flexio06: IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 { + pinmux = <0x401f8114 9 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexspi_b_data1: IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 { + pinmux = <0x401f8114 0 0x401f84bc 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio6_io22: IOMUXC_GPIO_AD_B1_06_GPIO6_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpt2_compare2: IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 { + pinmux = <0x401f8114 8 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_kpp_row4: IOMUXC_GPIO_AD_B1_06_KPP_ROW4 { + pinmux = <0x401f8114 7 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpi2c3_sda: IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA { + pinmux = <0x401f8114 1 0x401f84e0 2 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart3_tx: IOMUXC_GPIO_AD_B1_06_LPUART3_TX { + pinmux = <0x401f8114 2 0x401f853c 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_spdif_lock: IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK { + pinmux = <0x401f8114 3 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc2_data2: IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 { + pinmux = <0x401f8114 6 0x401f85f0 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp1_in5: IOMUXC_GPIO_AD_B1_07_ACMP1_IN5 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in12: IOMUXC_GPIO_AD_B1_07_ADC1_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in12: IOMUXC_GPIO_AD_B1_07_ADC2_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_csi_hsync: IOMUXC_GPIO_AD_B1_07_CSI_HSYNC { + pinmux = <0x401f8118 4 0x401f8420 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio3_flexio07: IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 { + pinmux = <0x401f8118 9 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexspi_b_data0: IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 { + pinmux = <0x401f8118 0 0x401f84b8 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio6_io23: IOMUXC_GPIO_AD_B1_07_GPIO6_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpt2_compare3: IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 { + pinmux = <0x401f8118 8 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_kpp_col4: IOMUXC_GPIO_AD_B1_07_KPP_COL4 { + pinmux = <0x401f8118 7 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpi2c3_scl: IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL { + pinmux = <0x401f8118 1 0x401f84dc 2 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart3_rx: IOMUXC_GPIO_AD_B1_07_LPUART3_RX { + pinmux = <0x401f8118 2 0x401f8538 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_spdif_ext_clk: IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK { + pinmux = <0x401f8118 3 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc2_data3: IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 { + pinmux = <0x401f8118 6 0x401f85f4 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_acmp2_in5: IOMUXC_GPIO_AD_B1_08_ACMP2_IN5 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc1_in13: IOMUXC_GPIO_AD_B1_08_ADC1_IN13 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc2_in13: IOMUXC_GPIO_AD_B1_08_ADC2_IN13 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_08_CCM_PMIC_RDY { + pinmux = <0x401f811c 3 0x401f83fc 3 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_csi_data09: IOMUXC_GPIO_AD_B1_08_CSI_DATA09 { + pinmux = <0x401f811c 4 0x401f841c 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexcan1_tx: IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX { + pinmux = <0x401f811c 2 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexio3_flexio08: IOMUXC_GPIO_AD_B1_08_FLEXIO3_FLEXIO08 { + pinmux = <0x401f811c 9 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexpwm4_pwma0: IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA0 { + pinmux = <0x401f811c 1 0x401f8494 1 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexspi_a_ss1_b: IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B { + pinmux = <0x401f811c 0 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio1_io24: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + gpr = <0x400ac068 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio6_io24: IOMUXC_GPIO_AD_B1_08_GPIO6_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + gpr = <0x400ac068 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_kpp_row3: IOMUXC_GPIO_AD_B1_08_KPP_ROW3 { + pinmux = <0x401f811c 7 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_usdhc2_cmd: IOMUXC_GPIO_AD_B1_08_USDHC2_CMD { + pinmux = <0x401f811c 6 0x401f85e4 1 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_acmp3_in5: IOMUXC_GPIO_AD_B1_09_ACMP3_IN5 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc1_in14: IOMUXC_GPIO_AD_B1_09_ADC1_IN14 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc2_in14: IOMUXC_GPIO_AD_B1_09_ADC2_IN14 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_csi_data08: IOMUXC_GPIO_AD_B1_09_CSI_DATA08 { + pinmux = <0x401f8120 4 0x401f8418 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexcan1_rx: IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX { + pinmux = <0x401f8120 2 0x401f844c 2 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexio3_flexio09: IOMUXC_GPIO_AD_B1_09_FLEXIO3_FLEXIO09 { + pinmux = <0x401f8120 9 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexpwm4_pwma1: IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA1 { + pinmux = <0x401f8120 1 0x401f8498 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexspi_a_dqs: IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS { + pinmux = <0x401f8120 0 0x401f84a4 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio1_io25: IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + gpr = <0x400ac068 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio6_io25: IOMUXC_GPIO_AD_B1_09_GPIO6_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + gpr = <0x400ac068 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_kpp_col3: IOMUXC_GPIO_AD_B1_09_KPP_COL3 { + pinmux = <0x401f8120 7 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_sai1_mclk: IOMUXC_GPIO_AD_B1_09_SAI1_MCLK { + pinmux = <0x401f8120 3 0x401f858c 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_usdhc2_clk: IOMUXC_GPIO_AD_B1_09_USDHC2_CLK { + pinmux = <0x401f8120 6 0x401f85dc 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_acmp4_in5: IOMUXC_GPIO_AD_B1_10_ACMP4_IN5 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in15: IOMUXC_GPIO_AD_B1_10_ADC1_IN15 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc2_in15: IOMUXC_GPIO_AD_B1_10_ADC2_IN15 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_csi_data07: IOMUXC_GPIO_AD_B1_10_CSI_DATA07 { + pinmux = <0x401f8124 4 0x401f8414 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_enet2_1588_event1_out: IOMUXC_GPIO_AD_B1_10_ENET2_1588_EVENT1_OUT { + pinmux = <0x401f8124 8 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio3_flexio10: IOMUXC_GPIO_AD_B1_10_FLEXIO3_FLEXIO10 { + pinmux = <0x401f8124 9 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexspi_a_data3: IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 { + pinmux = <0x401f8124 0 0x401f84b4 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + gpr = <0x400ac068 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio6_io26: IOMUXC_GPIO_AD_B1_10_GPIO6_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + gpr = <0x400ac068 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_kpp_row2: IOMUXC_GPIO_AD_B1_10_KPP_ROW2 { + pinmux = <0x401f8124 7 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart8_tx: IOMUXC_GPIO_AD_B1_10_LPUART8_TX { + pinmux = <0x401f8124 2 0x401f8564 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_sai1_rx_sync: IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC { + pinmux = <0x401f8124 3 0x401f85a4 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usdhc2_wp: IOMUXC_GPIO_AD_B1_10_USDHC2_WP { + pinmux = <0x401f8124 6 0x401f8608 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_wdog1_b: IOMUXC_GPIO_AD_B1_10_WDOG1_B { + pinmux = <0x401f8124 1 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_acmp1_in6: IOMUXC_GPIO_AD_B1_11_ACMP1_IN6 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in0: IOMUXC_GPIO_AD_B1_11_ADC1_IN0 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc2_in0: IOMUXC_GPIO_AD_B1_11_ADC2_IN0 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_csi_data06: IOMUXC_GPIO_AD_B1_11_CSI_DATA06 { + pinmux = <0x401f8128 4 0x401f8410 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_enet2_1588_event1_in: IOMUXC_GPIO_AD_B1_11_ENET2_1588_EVENT1_IN { + pinmux = <0x401f8128 8 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_ewm_out_b: IOMUXC_GPIO_AD_B1_11_EWM_OUT_B { + pinmux = <0x401f8128 1 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio3_flexio11: IOMUXC_GPIO_AD_B1_11_FLEXIO3_FLEXIO11 { + pinmux = <0x401f8128 9 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexspi_a_data2: IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 { + pinmux = <0x401f8128 0 0x401f84b0 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + gpr = <0x400ac068 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio6_io27: IOMUXC_GPIO_AD_B1_11_GPIO6_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + gpr = <0x400ac068 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_kpp_col2: IOMUXC_GPIO_AD_B1_11_KPP_COL2 { + pinmux = <0x401f8128 7 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart8_rx: IOMUXC_GPIO_AD_B1_11_LPUART8_RX { + pinmux = <0x401f8128 2 0x401f8560 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_sai1_rx_bclk: IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK { + pinmux = <0x401f8128 3 0x401f8590 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usdhc2_reset_b: IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B { + pinmux = <0x401f8128 6 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_out: IOMUXC_GPIO_AD_B1_12_ACMP1_OUT { + pinmux = <0x401f812c 1 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp2_in6: IOMUXC_GPIO_AD_B1_12_ACMP2_IN6 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc2_in1: IOMUXC_GPIO_AD_B1_12_ADC2_IN1 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_csi_data05: IOMUXC_GPIO_AD_B1_12_CSI_DATA05 { + pinmux = <0x401f812c 4 0x401f840c 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_enet2_1588_event2_out: IOMUXC_GPIO_AD_B1_12_ENET2_1588_EVENT2_OUT { + pinmux = <0x401f812c 8 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio3_flexio12: IOMUXC_GPIO_AD_B1_12_FLEXIO3_FLEXIO12 { + pinmux = <0x401f812c 9 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexspi_a_data1: IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 { + pinmux = <0x401f812c 0 0x401f84ac 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + gpr = <0x400ac068 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio6_io28: IOMUXC_GPIO_AD_B1_12_GPIO6_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + gpr = <0x400ac068 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_kpp_row1: IOMUXC_GPIO_AD_B1_12_KPP_ROW1 { + pinmux = <0x401f812c 7 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_lpspi3_pcs0: IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 { + pinmux = <0x401f812c 2 0x401f850c 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_sai1_rx_data0: IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA0 { + pinmux = <0x401f812c 3 0x401f8594 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usdhc2_data4: IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 { + pinmux = <0x401f812c 6 0x401f85f8 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_out: IOMUXC_GPIO_AD_B1_13_ACMP2_OUT { + pinmux = <0x401f8130 1 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp3_in6: IOMUXC_GPIO_AD_B1_13_ACMP3_IN6 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc2_in2: IOMUXC_GPIO_AD_B1_13_ADC2_IN2 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_csi_data04: IOMUXC_GPIO_AD_B1_13_CSI_DATA04 { + pinmux = <0x401f8130 4 0x401f8408 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_enet2_1588_event2_in: IOMUXC_GPIO_AD_B1_13_ENET2_1588_EVENT2_IN { + pinmux = <0x401f8130 8 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio3_flexio13: IOMUXC_GPIO_AD_B1_13_FLEXIO3_FLEXIO13 { + pinmux = <0x401f8130 9 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexspi_a_data0: IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 { + pinmux = <0x401f8130 0 0x401f84a8 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + gpr = <0x400ac068 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio6_io29: IOMUXC_GPIO_AD_B1_13_GPIO6_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + gpr = <0x400ac068 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_kpp_col1: IOMUXC_GPIO_AD_B1_13_KPP_COL1 { + pinmux = <0x401f8130 7 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpspi3_sdi: IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI { + pinmux = <0x401f8130 2 0x401f8514 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_sai1_tx_data0: IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA0 { + pinmux = <0x401f8130 3 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_usdhc2_data5: IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 { + pinmux = <0x401f8130 6 0x401f85fc 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_out: IOMUXC_GPIO_AD_B1_14_ACMP3_OUT { + pinmux = <0x401f8134 1 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp4_in6: IOMUXC_GPIO_AD_B1_14_ACMP4_IN6 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc2_in3: IOMUXC_GPIO_AD_B1_14_ADC2_IN3 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_csi_data03: IOMUXC_GPIO_AD_B1_14_CSI_DATA03 { + pinmux = <0x401f8134 4 0x401f8404 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_enet2_1588_event3_out: IOMUXC_GPIO_AD_B1_14_ENET2_1588_EVENT3_OUT { + pinmux = <0x401f8134 8 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio3_flexio14: IOMUXC_GPIO_AD_B1_14_FLEXIO3_FLEXIO14 { + pinmux = <0x401f8134 9 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexspi_a_sclk: IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK { + pinmux = <0x401f8134 0 0x401f84c8 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + gpr = <0x400ac068 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio6_io30: IOMUXC_GPIO_AD_B1_14_GPIO6_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + gpr = <0x400ac068 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_kpp_row0: IOMUXC_GPIO_AD_B1_14_KPP_ROW0 { + pinmux = <0x401f8134 7 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpspi3_sdo: IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO { + pinmux = <0x401f8134 2 0x401f8518 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_sai1_tx_bclk: IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK { + pinmux = <0x401f8134 3 0x401f85a8 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_usdhc2_data6: IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 { + pinmux = <0x401f8134 6 0x401f8600 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_out: IOMUXC_GPIO_AD_B1_15_ACMP4_OUT { + pinmux = <0x401f8138 1 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc2_in4: IOMUXC_GPIO_AD_B1_15_ADC2_IN4 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_csi_data02: IOMUXC_GPIO_AD_B1_15_CSI_DATA02 { + pinmux = <0x401f8138 4 0x401f8400 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_enet2_1588_event3_in: IOMUXC_GPIO_AD_B1_15_ENET2_1588_EVENT3_IN { + pinmux = <0x401f8138 8 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio3_flexio15: IOMUXC_GPIO_AD_B1_15_FLEXIO3_FLEXIO15 { + pinmux = <0x401f8138 9 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexspi_a_ss0_b: IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B { + pinmux = <0x401f8138 0 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + gpr = <0x400ac068 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio6_io31: IOMUXC_GPIO_AD_B1_15_GPIO6_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + gpr = <0x400ac068 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_kpp_col0: IOMUXC_GPIO_AD_B1_15_KPP_COL0 { + pinmux = <0x401f8138 7 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpspi3_sck: IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK { + pinmux = <0x401f8138 2 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_sai1_tx_sync: IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC { + pinmux = <0x401f8138 3 0x401f85ac 1 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_usdhc2_data7: IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 { + pinmux = <0x401f8138 6 0x401f8604 1 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_enet2_mdc: IOMUXC_GPIO_B0_00_ENET2_MDC { + pinmux = <0x401f813c 8 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_flexio2_flexio00: IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 { + pinmux = <0x401f813c 4 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio2_io00: IOMUXC_GPIO_B0_00_GPIO2_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio7_io00: IOMUXC_GPIO_B0_00_GPIO7_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lcdif_clk: IOMUXC_GPIO_B0_00_LCDIF_CLK { + pinmux = <0x401f813c 0 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lpspi4_pcs0: IOMUXC_GPIO_B0_00_LPSPI4_PCS0 { + pinmux = <0x401f813c 3 0x401f851c 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_mqs_right: IOMUXC_GPIO_B0_00_MQS_RIGHT { + pinmux = <0x401f813c 2 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_qtimer1_timer0: IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x0 0 0x401f832c>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_semc_csx1: IOMUXC_GPIO_B0_00_SEMC_CSX1 { + pinmux = <0x401f813c 6 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_enet2_mdio: IOMUXC_GPIO_B0_01_ENET2_MDIO { + pinmux = <0x401f8140 8 0x401f8710 1 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_flexio2_flexio01: IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 { + pinmux = <0x401f8140 4 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio2_io01: IOMUXC_GPIO_B0_01_GPIO2_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio7_io01: IOMUXC_GPIO_B0_01_GPIO7_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lcdif_enable: IOMUXC_GPIO_B0_01_LCDIF_ENABLE { + pinmux = <0x401f8140 0 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lpspi4_sdi: IOMUXC_GPIO_B0_01_LPSPI4_SDI { + pinmux = <0x401f8140 3 0x401f8524 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_mqs_left: IOMUXC_GPIO_B0_01_MQS_LEFT { + pinmux = <0x401f8140 2 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_qtimer1_timer1: IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x0 0 0x401f8330>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_semc_csx2: IOMUXC_GPIO_B0_01_SEMC_CSX2 { + pinmux = <0x401f8140 6 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_enet2_1588_event0_out: IOMUXC_GPIO_B0_02_ENET2_1588_EVENT0_OUT { + pinmux = <0x401f8144 8 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexcan1_tx: IOMUXC_GPIO_B0_02_FLEXCAN1_TX { + pinmux = <0x401f8144 2 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexio2_flexio02: IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 { + pinmux = <0x401f8144 4 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio2_io02: IOMUXC_GPIO_B0_02_GPIO2_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio7_io02: IOMUXC_GPIO_B0_02_GPIO7_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lcdif_hsync: IOMUXC_GPIO_B0_02_LCDIF_HSYNC { + pinmux = <0x401f8144 0 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lpspi4_sdo: IOMUXC_GPIO_B0_02_LPSPI4_SDO { + pinmux = <0x401f8144 3 0x401f8528 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_qtimer1_timer2: IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x0 0 0x401f8334>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_semc_csx3: IOMUXC_GPIO_B0_02_SEMC_CSX3 { + pinmux = <0x401f8144 6 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_enet2_1588_event0_in: IOMUXC_GPIO_B0_03_ENET2_1588_EVENT0_IN { + pinmux = <0x401f8148 8 0x401f8724 1 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexcan1_rx: IOMUXC_GPIO_B0_03_FLEXCAN1_RX { + pinmux = <0x401f8148 2 0x401f844c 3 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexio2_flexio03: IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 { + pinmux = <0x401f8148 4 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio2_io03: IOMUXC_GPIO_B0_03_GPIO2_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio7_io03: IOMUXC_GPIO_B0_03_GPIO7_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lcdif_vsync: IOMUXC_GPIO_B0_03_LCDIF_VSYNC { + pinmux = <0x401f8148 0 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lpspi4_sck: IOMUXC_GPIO_B0_03_LPSPI4_SCK { + pinmux = <0x401f8148 3 0x401f8520 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_qtimer2_timer0: IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 { + pinmux = <0x401f8148 1 0x401f856c 1 0x401f8338>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_wdog2_rst_b_deb: IOMUXC_GPIO_B0_03_WDOG2_RST_B_DEB { + pinmux = <0x401f8148 6 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_arm_trace0: IOMUXC_GPIO_B0_04_ARM_TRACE0 { + pinmux = <0x401f814c 3 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_enet2_tx_data3: IOMUXC_GPIO_B0_04_ENET2_TX_DATA3 { + pinmux = <0x401f814c 8 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_flexio2_flexio04: IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 { + pinmux = <0x401f814c 4 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio2_io04: IOMUXC_GPIO_B0_04_GPIO2_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio7_io04: IOMUXC_GPIO_B0_04_GPIO7_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lcdif_data00: IOMUXC_GPIO_B0_04_LCDIF_DATA00 { + pinmux = <0x401f814c 0 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lpi2c2_scl: IOMUXC_GPIO_B0_04_LPI2C2_SCL { + pinmux = <0x401f814c 2 0x401f84d4 1 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_qtimer2_timer1: IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 { + pinmux = <0x401f814c 1 0x401f8570 1 0x401f833c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_src_bt_cfg0: IOMUXC_GPIO_B0_04_SRC_BT_CFG0 { + pinmux = <0x401f814c 6 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_arm_trace1: IOMUXC_GPIO_B0_05_ARM_TRACE1 { + pinmux = <0x401f8150 3 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_enet2_tx_data2: IOMUXC_GPIO_B0_05_ENET2_TX_DATA2 { + pinmux = <0x401f8150 8 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_flexio2_flexio05: IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 { + pinmux = <0x401f8150 4 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio2_io05: IOMUXC_GPIO_B0_05_GPIO2_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio7_io05: IOMUXC_GPIO_B0_05_GPIO7_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lcdif_data01: IOMUXC_GPIO_B0_05_LCDIF_DATA01 { + pinmux = <0x401f8150 0 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lpi2c2_sda: IOMUXC_GPIO_B0_05_LPI2C2_SDA { + pinmux = <0x401f8150 2 0x401f84d8 1 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_qtimer2_timer2: IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 { + pinmux = <0x401f8150 1 0x401f8574 1 0x401f8340>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_src_bt_cfg1: IOMUXC_GPIO_B0_05_SRC_BT_CFG1 { + pinmux = <0x401f8150 6 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_arm_trace2: IOMUXC_GPIO_B0_06_ARM_TRACE2 { + pinmux = <0x401f8154 3 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_enet2_rx_clk: IOMUXC_GPIO_B0_06_ENET2_RX_CLK { + pinmux = <0x401f8154 8 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexio2_flexio06: IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 { + pinmux = <0x401f8154 4 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexpwm2_pwma0: IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f8154 2 0x401f8478 1 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio2_io06: IOMUXC_GPIO_B0_06_GPIO2_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio7_io06: IOMUXC_GPIO_B0_06_GPIO7_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_lcdif_data02: IOMUXC_GPIO_B0_06_LCDIF_DATA02 { + pinmux = <0x401f8154 0 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_qtimer3_timer0: IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 { + pinmux = <0x401f8154 1 0x401f857c 2 0x401f8344>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_src_bt_cfg2: IOMUXC_GPIO_B0_06_SRC_BT_CFG2 { + pinmux = <0x401f8154 6 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_arm_trace3: IOMUXC_GPIO_B0_07_ARM_TRACE3 { + pinmux = <0x401f8158 3 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_enet2_tx_er: IOMUXC_GPIO_B0_07_ENET2_TX_ER { + pinmux = <0x401f8158 8 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexio2_flexio07: IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 { + pinmux = <0x401f8158 4 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexpwm2_pwmb0: IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8158 2 0x401f8488 1 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio2_io07: IOMUXC_GPIO_B0_07_GPIO2_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio7_io07: IOMUXC_GPIO_B0_07_GPIO7_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_lcdif_data03: IOMUXC_GPIO_B0_07_LCDIF_DATA03 { + pinmux = <0x401f8158 0 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_qtimer3_timer1: IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 { + pinmux = <0x401f8158 1 0x401f8580 2 0x401f8348>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_src_bt_cfg3: IOMUXC_GPIO_B0_07_SRC_BT_CFG3 { + pinmux = <0x401f8158 6 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_enet2_rx_data3: IOMUXC_GPIO_B0_08_ENET2_RX_DATA3 { + pinmux = <0x401f815c 8 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexio2_flexio08: IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 { + pinmux = <0x401f815c 4 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexpwm2_pwma1: IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f815c 2 0x401f847c 1 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio2_io08: IOMUXC_GPIO_B0_08_GPIO2_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio7_io08: IOMUXC_GPIO_B0_08_GPIO7_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lcdif_data04: IOMUXC_GPIO_B0_08_LCDIF_DATA04 { + pinmux = <0x401f815c 0 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lpuart3_tx: IOMUXC_GPIO_B0_08_LPUART3_TX { + pinmux = <0x401f815c 3 0x401f853c 2 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_qtimer3_timer2: IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 { + pinmux = <0x401f815c 1 0x401f8584 2 0x401f834c>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_src_bt_cfg4: IOMUXC_GPIO_B0_08_SRC_BT_CFG4 { + pinmux = <0x401f815c 6 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_enet2_rx_data2: IOMUXC_GPIO_B0_09_ENET2_RX_DATA2 { + pinmux = <0x401f8160 8 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexio2_flexio09: IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 { + pinmux = <0x401f8160 4 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexpwm2_pwmb1: IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8160 2 0x401f848c 1 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio2_io09: IOMUXC_GPIO_B0_09_GPIO2_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio7_io09: IOMUXC_GPIO_B0_09_GPIO7_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lcdif_data05: IOMUXC_GPIO_B0_09_LCDIF_DATA05 { + pinmux = <0x401f8160 0 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lpuart3_rx: IOMUXC_GPIO_B0_09_LPUART3_RX { + pinmux = <0x401f8160 3 0x401f8538 2 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_qtimer4_timer0: IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 { + pinmux = <0x401f8160 1 0x0 0 0x401f8350>; + gpr = <0x400ac018 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_src_bt_cfg5: IOMUXC_GPIO_B0_09_SRC_BT_CFG5 { + pinmux = <0x401f8160 6 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_enet2_crs: IOMUXC_GPIO_B0_10_ENET2_CRS { + pinmux = <0x401f8164 8 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexio2_flexio10: IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 { + pinmux = <0x401f8164 4 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f8164 2 0x401f8480 1 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio2_io10: IOMUXC_GPIO_B0_10_GPIO2_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio7_io10: IOMUXC_GPIO_B0_10_GPIO7_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_lcdif_data06: IOMUXC_GPIO_B0_10_LCDIF_DATA06 { + pinmux = <0x401f8164 0 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_qtimer4_timer1: IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 { + pinmux = <0x401f8164 1 0x0 0 0x401f8354>; + gpr = <0x400ac018 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_sai1_tx_data3: IOMUXC_GPIO_B0_10_SAI1_TX_DATA3 { + pinmux = <0x401f8164 3 0x401f8598 1 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_src_bt_cfg6: IOMUXC_GPIO_B0_10_SRC_BT_CFG6 { + pinmux = <0x401f8164 6 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_enet2_col: IOMUXC_GPIO_B0_11_ENET2_COL { + pinmux = <0x401f8168 8 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexio2_flexio11: IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 { + pinmux = <0x401f8168 4 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8168 2 0x401f8490 1 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio2_io11: IOMUXC_GPIO_B0_11_GPIO2_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio7_io11: IOMUXC_GPIO_B0_11_GPIO7_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_lcdif_data07: IOMUXC_GPIO_B0_11_LCDIF_DATA07 { + pinmux = <0x401f8168 0 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_qtimer4_timer2: IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 { + pinmux = <0x401f8168 1 0x0 0 0x401f8358>; + gpr = <0x400ac018 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_sai1_tx_data2: IOMUXC_GPIO_B0_11_SAI1_TX_DATA2 { + pinmux = <0x401f8168 3 0x401f859c 1 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_src_bt_cfg7: IOMUXC_GPIO_B0_11_SRC_BT_CFG7 { + pinmux = <0x401f8168 6 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_arm_trace_clk: IOMUXC_GPIO_B0_12_ARM_TRACE_CLK { + pinmux = <0x401f816c 2 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_enet2_tx_data0: IOMUXC_GPIO_B0_12_ENET2_TX_DATA0 { + pinmux = <0x401f816c 8 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_flexio2_flexio12: IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 { + pinmux = <0x401f816c 4 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio2_io12: IOMUXC_GPIO_B0_12_GPIO2_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio7_io12: IOMUXC_GPIO_B0_12_GPIO7_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_lcdif_data08: IOMUXC_GPIO_B0_12_LCDIF_DATA08 { + pinmux = <0x401f816c 0 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_sai1_tx_data1: IOMUXC_GPIO_B0_12_SAI1_TX_DATA1 { + pinmux = <0x401f816c 3 0x401f85a0 1 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_src_bt_cfg8: IOMUXC_GPIO_B0_12_SRC_BT_CFG8 { + pinmux = <0x401f816c 6 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_in10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_IN10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_inout10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_arm_trace_swo: IOMUXC_GPIO_B0_13_ARM_TRACE_SWO { + pinmux = <0x401f8170 2 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_enet2_tx_data1: IOMUXC_GPIO_B0_13_ENET2_TX_DATA1 { + pinmux = <0x401f8170 8 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_flexio2_flexio13: IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 { + pinmux = <0x401f8170 4 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio2_io13: IOMUXC_GPIO_B0_13_GPIO2_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio7_io13: IOMUXC_GPIO_B0_13_GPIO7_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_lcdif_data09: IOMUXC_GPIO_B0_13_LCDIF_DATA09 { + pinmux = <0x401f8170 0 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_sai1_mclk: IOMUXC_GPIO_B0_13_SAI1_MCLK { + pinmux = <0x401f8170 3 0x401f858c 2 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_src_bt_cfg9: IOMUXC_GPIO_B0_13_SRC_BT_CFG9 { + pinmux = <0x401f8170 6 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_in11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_IN11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_inout11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_arm_txev: IOMUXC_GPIO_B0_14_ARM_TXEV { + pinmux = <0x401f8174 2 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_enet2_tx_en: IOMUXC_GPIO_B0_14_ENET2_TX_EN { + pinmux = <0x401f8174 8 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_flexio2_flexio14: IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 { + pinmux = <0x401f8174 4 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio2_io14: IOMUXC_GPIO_B0_14_GPIO2_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio7_io14: IOMUXC_GPIO_B0_14_GPIO7_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_lcdif_data10: IOMUXC_GPIO_B0_14_LCDIF_DATA10 { + pinmux = <0x401f8174 0 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_sai1_rx_sync: IOMUXC_GPIO_B0_14_SAI1_RX_SYNC { + pinmux = <0x401f8174 3 0x401f85a4 2 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_src_bt_cfg10: IOMUXC_GPIO_B0_14_SRC_BT_CFG10 { + pinmux = <0x401f8174 6 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_in12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_IN12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_inout12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_arm_rxev: IOMUXC_GPIO_B0_15_ARM_RXEV { + pinmux = <0x401f8178 2 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_enet2_ref_clk2: IOMUXC_GPIO_B0_15_ENET2_REF_CLK2 { + pinmux = <0x401f8178 9 0x401f870c 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_enet2_tx_clk: IOMUXC_GPIO_B0_15_ENET2_TX_CLK { + pinmux = <0x401f8178 8 0x401f8728 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_flexio2_flexio15: IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 { + pinmux = <0x401f8178 4 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio2_io15: IOMUXC_GPIO_B0_15_GPIO2_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio7_io15: IOMUXC_GPIO_B0_15_GPIO7_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_lcdif_data11: IOMUXC_GPIO_B0_15_LCDIF_DATA11 { + pinmux = <0x401f8178 0 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_sai1_rx_bclk: IOMUXC_GPIO_B0_15_SAI1_RX_BCLK { + pinmux = <0x401f8178 3 0x401f8590 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_src_bt_cfg11: IOMUXC_GPIO_B0_15_SRC_BT_CFG11 { + pinmux = <0x401f8178 6 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_in13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_IN13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_inout13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_enet2_rx_er: IOMUXC_GPIO_B1_00_ENET2_RX_ER { + pinmux = <0x401f817c 8 0x401f8720 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio2_flexio16: IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 { + pinmux = <0x401f817c 4 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio3_flexio16: IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 { + pinmux = <0x401f817c 9 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f817c 6 0x401f8454 4 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio2_io16: IOMUXC_GPIO_B1_00_GPIO2_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio7_io16: IOMUXC_GPIO_B1_00_GPIO7_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lcdif_data12: IOMUXC_GPIO_B1_00_LCDIF_DATA12 { + pinmux = <0x401f817c 0 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lpuart4_tx: IOMUXC_GPIO_B1_00_LPUART4_TX { + pinmux = <0x401f817c 2 0x401f8544 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_sai1_rx_data0: IOMUXC_GPIO_B1_00_SAI1_RX_DATA0 { + pinmux = <0x401f817c 3 0x401f8594 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_in14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f817c 1 0x401f8644 1 0x401f836c>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_inout14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f817c 1 0x401f8644 1 0x401f836c>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_enet2_rx_data0: IOMUXC_GPIO_B1_01_ENET2_RX_DATA0 { + pinmux = <0x401f8180 8 0x401f8714 2 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio2_flexio17: IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 { + pinmux = <0x401f8180 4 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio3_flexio17: IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 { + pinmux = <0x401f8180 9 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f8180 6 0x401f8464 4 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio2_io17: IOMUXC_GPIO_B1_01_GPIO2_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio7_io17: IOMUXC_GPIO_B1_01_GPIO7_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lcdif_data13: IOMUXC_GPIO_B1_01_LCDIF_DATA13 { + pinmux = <0x401f8180 0 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lpuart4_rx: IOMUXC_GPIO_B1_01_LPUART4_RX { + pinmux = <0x401f8180 2 0x401f8540 2 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_sai1_tx_data0: IOMUXC_GPIO_B1_01_SAI1_TX_DATA0 { + pinmux = <0x401f8180 3 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_in15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8180 1 0x401f8648 1 0x401f8370>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_inout15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8180 1 0x401f8648 1 0x401f8370>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_enet2_rx_data1: IOMUXC_GPIO_B1_02_ENET2_RX_DATA1 { + pinmux = <0x401f8184 8 0x401f8718 2 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio2_flexio18: IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 { + pinmux = <0x401f8184 4 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio3_flexio18: IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 { + pinmux = <0x401f8184 9 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f8184 6 0x401f8474 4 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio2_io18: IOMUXC_GPIO_B1_02_GPIO2_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio7_io18: IOMUXC_GPIO_B1_02_GPIO7_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lcdif_data14: IOMUXC_GPIO_B1_02_LCDIF_DATA14 { + pinmux = <0x401f8184 0 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lpspi4_pcs2: IOMUXC_GPIO_B1_02_LPSPI4_PCS2 { + pinmux = <0x401f8184 2 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_sai1_tx_bclk: IOMUXC_GPIO_B1_02_SAI1_TX_BCLK { + pinmux = <0x401f8184 3 0x401f85a8 2 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_in16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8184 1 0x401f864c 1 0x401f8374>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_inout16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8184 1 0x401f864c 1 0x401f8374>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_enet2_rx_en: IOMUXC_GPIO_B1_03_ENET2_RX_EN { + pinmux = <0x401f8188 8 0x401f871c 2 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio2_flexio19: IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 { + pinmux = <0x401f8188 4 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio3_flexio19: IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 { + pinmux = <0x401f8188 9 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f8188 6 0x401f8484 3 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio2_io19: IOMUXC_GPIO_B1_03_GPIO2_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio7_io19: IOMUXC_GPIO_B1_03_GPIO7_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lcdif_data15: IOMUXC_GPIO_B1_03_LCDIF_DATA15 { + pinmux = <0x401f8188 0 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lpspi4_pcs1: IOMUXC_GPIO_B1_03_LPSPI4_PCS1 { + pinmux = <0x401f8188 2 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_sai1_tx_sync: IOMUXC_GPIO_B1_03_SAI1_TX_SYNC { + pinmux = <0x401f8188 3 0x401f85ac 2 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_in17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f8188 1 0x401f862c 3 0x401f8378>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_inout17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8188 1 0x401f862c 3 0x401f8378>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_csi_data15: IOMUXC_GPIO_B1_04_CSI_DATA15 { + pinmux = <0x401f818c 2 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_enet_rx_data0: IOMUXC_GPIO_B1_04_ENET_RX_DATA0 { + pinmux = <0x401f818c 3 0x401f8434 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio2_flexio20: IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 { + pinmux = <0x401f818c 4 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio3_flexio20: IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 { + pinmux = <0x401f818c 9 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio2_io20: IOMUXC_GPIO_B1_04_GPIO2_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio7_io20: IOMUXC_GPIO_B1_04_GPIO7_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpt1_clk: IOMUXC_GPIO_B1_04_GPT1_CLK { + pinmux = <0x401f818c 8 0x401f8760 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lcdif_data16: IOMUXC_GPIO_B1_04_LCDIF_DATA16 { + pinmux = <0x401f818c 0 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lpspi4_pcs0: IOMUXC_GPIO_B1_04_LPSPI4_PCS0 { + pinmux = <0x401f818c 1 0x401f851c 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_csi_data14: IOMUXC_GPIO_B1_05_CSI_DATA14 { + pinmux = <0x401f8190 2 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_enet_rx_data1: IOMUXC_GPIO_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f8190 3 0x401f8438 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio2_flexio21: IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 { + pinmux = <0x401f8190 4 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio3_flexio21: IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 { + pinmux = <0x401f8190 9 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio2_io21: IOMUXC_GPIO_B1_05_GPIO2_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio7_io21: IOMUXC_GPIO_B1_05_GPIO7_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpt1_capture1: IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 { + pinmux = <0x401f8190 8 0x401f8758 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lcdif_data17: IOMUXC_GPIO_B1_05_LCDIF_DATA17 { + pinmux = <0x401f8190 0 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lpspi4_sdi: IOMUXC_GPIO_B1_05_LPSPI4_SDI { + pinmux = <0x401f8190 1 0x401f8524 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_csi_data13: IOMUXC_GPIO_B1_06_CSI_DATA13 { + pinmux = <0x401f8194 2 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_enet_rx_en: IOMUXC_GPIO_B1_06_ENET_RX_EN { + pinmux = <0x401f8194 3 0x401f843c 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio2_flexio22: IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 { + pinmux = <0x401f8194 4 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio3_flexio22: IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 { + pinmux = <0x401f8194 9 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio2_io22: IOMUXC_GPIO_B1_06_GPIO2_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio7_io22: IOMUXC_GPIO_B1_06_GPIO7_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpt1_capture2: IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 { + pinmux = <0x401f8194 8 0x401f875c 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lcdif_data18: IOMUXC_GPIO_B1_06_LCDIF_DATA18 { + pinmux = <0x401f8194 0 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lpspi4_sdo: IOMUXC_GPIO_B1_06_LPSPI4_SDO { + pinmux = <0x401f8194 1 0x401f8528 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_csi_data12: IOMUXC_GPIO_B1_07_CSI_DATA12 { + pinmux = <0x401f8198 2 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_enet_tx_data0: IOMUXC_GPIO_B1_07_ENET_TX_DATA0 { + pinmux = <0x401f8198 3 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio2_flexio23: IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 { + pinmux = <0x401f8198 4 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio3_flexio23: IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 { + pinmux = <0x401f8198 9 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio2_io23: IOMUXC_GPIO_B1_07_GPIO2_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio7_io23: IOMUXC_GPIO_B1_07_GPIO7_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpt1_compare1: IOMUXC_GPIO_B1_07_GPT1_COMPARE1 { + pinmux = <0x401f8198 8 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lcdif_data19: IOMUXC_GPIO_B1_07_LCDIF_DATA19 { + pinmux = <0x401f8198 0 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lpspi4_sck: IOMUXC_GPIO_B1_07_LPSPI4_SCK { + pinmux = <0x401f8198 1 0x401f8520 1 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_csi_data11: IOMUXC_GPIO_B1_08_CSI_DATA11 { + pinmux = <0x401f819c 2 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_enet_tx_data1: IOMUXC_GPIO_B1_08_ENET_TX_DATA1 { + pinmux = <0x401f819c 3 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexcan2_tx: IOMUXC_GPIO_B1_08_FLEXCAN2_TX { + pinmux = <0x401f819c 6 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio2_flexio24: IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 { + pinmux = <0x401f819c 4 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio3_flexio24: IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 { + pinmux = <0x401f819c 9 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio2_io24: IOMUXC_GPIO_B1_08_GPIO2_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio7_io24: IOMUXC_GPIO_B1_08_GPIO7_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpt1_compare2: IOMUXC_GPIO_B1_08_GPT1_COMPARE2 { + pinmux = <0x401f819c 8 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_lcdif_data20: IOMUXC_GPIO_B1_08_LCDIF_DATA20 { + pinmux = <0x401f819c 0 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_qtimer1_timer3: IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 { + pinmux = <0x401f819c 1 0x0 0 0x401f838c>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_csi_data10: IOMUXC_GPIO_B1_09_CSI_DATA10 { + pinmux = <0x401f81a0 2 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_enet_tx_en: IOMUXC_GPIO_B1_09_ENET_TX_EN { + pinmux = <0x401f81a0 3 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexcan2_rx: IOMUXC_GPIO_B1_09_FLEXCAN2_RX { + pinmux = <0x401f81a0 6 0x401f8450 3 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio2_flexio25: IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 { + pinmux = <0x401f81a0 4 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio3_flexio25: IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 { + pinmux = <0x401f81a0 9 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio2_io25: IOMUXC_GPIO_B1_09_GPIO2_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio7_io25: IOMUXC_GPIO_B1_09_GPIO7_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpt1_compare3: IOMUXC_GPIO_B1_09_GPT1_COMPARE3 { + pinmux = <0x401f81a0 8 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_lcdif_data21: IOMUXC_GPIO_B1_09_LCDIF_DATA21 { + pinmux = <0x401f81a0 0 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_qtimer2_timer3: IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 { + pinmux = <0x401f81a0 1 0x401f8578 1 0x401f8390>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_csi_data00: IOMUXC_GPIO_B1_10_CSI_DATA00 { + pinmux = <0x401f81a4 2 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_ref_clk: IOMUXC_GPIO_B1_10_ENET_REF_CLK { + pinmux = <0x401f81a4 6 0x401f842c 1 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_tx_clk: IOMUXC_GPIO_B1_10_ENET_TX_CLK { + pinmux = <0x401f81a4 3 0x401f8448 1 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio2_flexio26: IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 { + pinmux = <0x401f81a4 4 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio3_flexio26: IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 { + pinmux = <0x401f81a4 9 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio2_io26: IOMUXC_GPIO_B1_10_GPIO2_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio7_io26: IOMUXC_GPIO_B1_10_GPIO7_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_lcdif_data22: IOMUXC_GPIO_B1_10_LCDIF_DATA22 { + pinmux = <0x401f81a4 0 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_qtimer3_timer3: IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 { + pinmux = <0x401f81a4 1 0x401f8588 2 0x401f8394>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_csi_data01: IOMUXC_GPIO_B1_11_CSI_DATA01 { + pinmux = <0x401f81a8 2 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_enet_rx_er: IOMUXC_GPIO_B1_11_ENET_RX_ER { + pinmux = <0x401f81a8 3 0x401f8440 1 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio2_flexio27: IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 { + pinmux = <0x401f81a8 4 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio3_flexio27: IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 { + pinmux = <0x401f81a8 9 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio2_io27: IOMUXC_GPIO_B1_11_GPIO2_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio7_io27: IOMUXC_GPIO_B1_11_GPIO7_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lcdif_data23: IOMUXC_GPIO_B1_11_LCDIF_DATA23 { + pinmux = <0x401f81a8 0 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lpspi4_pcs3: IOMUXC_GPIO_B1_11_LPSPI4_PCS3 { + pinmux = <0x401f81a8 6 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_qtimer4_timer3: IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 { + pinmux = <0x401f81a8 1 0x0 0 0x401f8398>; + gpr = <0x400ac018 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_csi_pixclk: IOMUXC_GPIO_B1_12_CSI_PIXCLK { + pinmux = <0x401f81ac 2 0x401f8424 1 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_enet_1588_event0_in: IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN { + pinmux = <0x401f81ac 3 0x401f8444 2 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio2_flexio28: IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 { + pinmux = <0x401f81ac 4 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio3_flexio28: IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 { + pinmux = <0x401f81ac 9 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio2_io28: IOMUXC_GPIO_B1_12_GPIO2_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio7_io28: IOMUXC_GPIO_B1_12_GPIO7_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_lpuart5_tx: IOMUXC_GPIO_B1_12_LPUART5_TX { + pinmux = <0x401f81ac 1 0x401f854c 1 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_usdhc1_cd_b: IOMUXC_GPIO_B1_12_USDHC1_CD_B { + pinmux = <0x401f81ac 6 0x401f85d4 2 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_csi_vsync: IOMUXC_GPIO_B1_13_CSI_VSYNC { + pinmux = <0x401f81b0 2 0x401f8428 2 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_enet_1588_event0_out: IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT { + pinmux = <0x401f81b0 3 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio2_flexio29: IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 { + pinmux = <0x401f81b0 4 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio3_flexio29: IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 { + pinmux = <0x401f81b0 9 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio2_io29: IOMUXC_GPIO_B1_13_GPIO2_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio7_io29: IOMUXC_GPIO_B1_13_GPIO7_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_lpuart5_rx: IOMUXC_GPIO_B1_13_LPUART5_RX { + pinmux = <0x401f81b0 1 0x401f8548 1 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_semc_dqs4: IOMUXC_GPIO_B1_13_SEMC_DQS4 { + pinmux = <0x401f81b0 8 0x401f8788 3 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_usdhc1_wp: IOMUXC_GPIO_B1_13_USDHC1_WP { + pinmux = <0x401f81b0 6 0x401f85d8 3 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_wdog1_b: IOMUXC_GPIO_B1_13_WDOG1_B { + pinmux = <0x401f81b0 0 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_csi_hsync: IOMUXC_GPIO_B1_14_CSI_HSYNC { + pinmux = <0x401f81b4 2 0x401f8420 2 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet2_tx_data0: IOMUXC_GPIO_B1_14_ENET2_TX_DATA0 { + pinmux = <0x401f81b4 8 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet_mdc: IOMUXC_GPIO_B1_14_ENET_MDC { + pinmux = <0x401f81b4 0 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio2_flexio30: IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 { + pinmux = <0x401f81b4 4 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio3_flexio30: IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 { + pinmux = <0x401f81b4 9 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexpwm4_pwma2: IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA2 { + pinmux = <0x401f81b4 1 0x401f849c 1 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio2_io30: IOMUXC_GPIO_B1_14_GPIO2_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio7_io30: IOMUXC_GPIO_B1_14_GPIO7_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_usdhc1_vselect: IOMUXC_GPIO_B1_14_USDHC1_VSELECT { + pinmux = <0x401f81b4 6 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_xbar1_xbar_in02: IOMUXC_GPIO_B1_14_XBAR1_XBAR_IN02 { + pinmux = <0x401f81b4 3 0x401f860c 1 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_csi_mclk: IOMUXC_GPIO_B1_15_CSI_MCLK { + pinmux = <0x401f81b8 2 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet2_tx_data1: IOMUXC_GPIO_B1_15_ENET2_TX_DATA1 { + pinmux = <0x401f81b8 8 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet_mdio: IOMUXC_GPIO_B1_15_ENET_MDIO { + pinmux = <0x401f81b8 0 0x401f8430 2 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio2_flexio31: IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 { + pinmux = <0x401f81b8 4 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio3_flexio31: IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 { + pinmux = <0x401f81b8 9 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexpwm4_pwma3: IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA3 { + pinmux = <0x401f81b8 1 0x401f84a0 1 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio2_io31: IOMUXC_GPIO_B1_15_GPIO2_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio7_io31: IOMUXC_GPIO_B1_15_GPIO7_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_usdhc1_reset_b: IOMUXC_GPIO_B1_15_USDHC1_RESET_B { + pinmux = <0x401f81b8 6 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_xbar1_xbar_in03: IOMUXC_GPIO_B1_15_XBAR1_XBAR_IN03 { + pinmux = <0x401f81b8 3 0x401f8610 1 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexio1_flexio00: IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8014 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexpwm4_pwma0: IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA0 { + pinmux = <0x401f8014 1 0x401f8494 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio4_io00: IOMUXC_GPIO_EMC_00_GPIO4_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio9_io00: IOMUXC_GPIO_EMC_00_GPIO9_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 2 0x401f8500 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_xbar1_xbar_in02: IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 { + pinmux = <0x401f8014 3 0x401f860c 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexio1_flexio01: IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8018 4 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexpwm4_pwmb0: IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB0 { + pinmux = <0x401f8018 1 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio4_io01: IOMUXC_GPIO_EMC_01_GPIO4_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio9_io01: IOMUXC_GPIO_EMC_01_GPIO9_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 2 0x401f84fc 1 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_xbar1_xbar_in03: IOMUXC_GPIO_EMC_01_XBAR1_XBAR_IN03 { + pinmux = <0x401f8018 3 0x401f8610 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexio1_flexio02: IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 { + pinmux = <0x401f801c 4 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexpwm4_pwma1: IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA1 { + pinmux = <0x401f801c 1 0x401f8498 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio4_io02: IOMUXC_GPIO_EMC_02_GPIO4_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio9_io02: IOMUXC_GPIO_EMC_02_GPIO9_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 2 0x401f8508 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_in04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_IN04 { + pinmux = <0x401f801c 3 0x401f8614 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f801c 3 0x401f8614 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexio1_flexio03: IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 { + pinmux = <0x401f8020 4 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexpwm4_pwmb1: IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB1 { + pinmux = <0x401f8020 1 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio4_io03: IOMUXC_GPIO_EMC_03_GPIO4_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio9_io03: IOMUXC_GPIO_EMC_03_GPIO9_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 2 0x401f8504 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_in05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_IN05 { + pinmux = <0x401f8020 3 0x401f8618 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8020 3 0x401f8618 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio04: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8024 4 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexpwm4_pwma2: IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA2 { + pinmux = <0x401f8024 1 0x401f849c 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio4_io04: IOMUXC_GPIO_EMC_04_GPIO4_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio9_io04: IOMUXC_GPIO_EMC_04_GPIO9_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_data: IOMUXC_GPIO_EMC_04_SAI2_TX_DATA { + pinmux = <0x401f8024 2 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN06 { + pinmux = <0x401f8024 3 0x401f861c 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f8024 3 0x401f861c 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio05: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8028 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexpwm4_pwmb2: IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB2 { + pinmux = <0x401f8028 1 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio4_io05: IOMUXC_GPIO_EMC_05_GPIO4_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio9_io05: IOMUXC_GPIO_EMC_05_GPIO9_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 2 0x401f85c4 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN07 { + pinmux = <0x401f8028 3 0x401f8620 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8028 3 0x401f8620 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio06: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 { + pinmux = <0x401f802c 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexpwm2_pwma0: IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f802c 1 0x401f8478 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio4_io06: IOMUXC_GPIO_EMC_06_GPIO4_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio9_io06: IOMUXC_GPIO_EMC_06_GPIO9_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_bclk: IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK { + pinmux = <0x401f802c 2 0x401f85c0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN08 { + pinmux = <0x401f802c 3 0x401f8624 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f802c 3 0x401f8624 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio07: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 { + pinmux = <0x401f8030 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8030 1 0x401f8488 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio4_io07: IOMUXC_GPIO_EMC_07_GPIO4_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio9_io07: IOMUXC_GPIO_EMC_07_GPIO9_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_mclk: IOMUXC_GPIO_EMC_07_SAI2_MCLK { + pinmux = <0x401f8030 2 0x401f85b0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN09 { + pinmux = <0x401f8030 3 0x401f8628 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8030 3 0x401f8628 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio08: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8034 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexpwm2_pwma1: IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f8034 1 0x401f847c 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio4_io08: IOMUXC_GPIO_EMC_08_GPIO4_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio9_io08: IOMUXC_GPIO_EMC_08_GPIO9_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 2 0x401f85b8 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN17 { + pinmux = <0x401f8034 3 0x401f862c 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8034 3 0x401f862c 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_tx: IOMUXC_GPIO_EMC_09_FLEXCAN2_TX { + pinmux = <0x401f8038 3 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio09: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8038 4 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8038 1 0x401f848c 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio4_io09: IOMUXC_GPIO_EMC_09_GPIO4_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio9_io09: IOMUXC_GPIO_EMC_09_GPIO9_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_sync: IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC { + pinmux = <0x401f8038 2 0x401f85bc 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_addr00: IOMUXC_GPIO_EMC_09_SEMC_ADDR00 { + pinmux = <0x401f8038 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexcan2_rx: IOMUXC_GPIO_EMC_10_FLEXCAN2_RX { + pinmux = <0x401f803c 3 0x401f8450 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexio1_flexio10: IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 { + pinmux = <0x401f803c 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwma2: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f803c 1 0x401f8480 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio4_io10: IOMUXC_GPIO_EMC_10_GPIO4_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio9_io10: IOMUXC_GPIO_EMC_10_GPIO9_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai2_rx_bclk: IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK { + pinmux = <0x401f803c 2 0x401f85b4 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_addr01: IOMUXC_GPIO_EMC_10_SEMC_ADDR01 { + pinmux = <0x401f803c 0 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexio1_flexio11: IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 { + pinmux = <0x401f8040 4 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8040 1 0x401f8490 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio4_io11: IOMUXC_GPIO_EMC_11_GPIO4_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio9_io11: IOMUXC_GPIO_EMC_11_GPIO9_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_sda: IOMUXC_GPIO_EMC_11_LPI2C4_SDA { + pinmux = <0x401f8040 2 0x401f84e8 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_addr02: IOMUXC_GPIO_EMC_11_SEMC_ADDR02 { + pinmux = <0x401f8040 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_usdhc2_reset_b: IOMUXC_GPIO_EMC_11_USDHC2_RESET_B { + pinmux = <0x401f8040 3 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm1_pwma3: IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f8044 4 0x401f8454 1 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio4_io12: IOMUXC_GPIO_EMC_12_GPIO4_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio9_io12: IOMUXC_GPIO_EMC_12_GPIO9_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpi2c4_scl: IOMUXC_GPIO_EMC_12_LPI2C4_SCL { + pinmux = <0x401f8044 2 0x401f84e4 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_addr03: IOMUXC_GPIO_EMC_12_SEMC_ADDR03 { + pinmux = <0x401f8044 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_usdhc1_wp: IOMUXC_GPIO_EMC_12_USDHC1_WP { + pinmux = <0x401f8044 3 0x401f85d8 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in24: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN24 { + pinmux = <0x401f8044 1 0x401f8640 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8048 4 0x401f8464 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio4_io13: IOMUXC_GPIO_EMC_13_GPIO4_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio9_io13: IOMUXC_GPIO_EMC_13_GPIO9_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart3_tx: IOMUXC_GPIO_EMC_13_LPUART3_TX { + pinmux = <0x401f8048 2 0x401f853c 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_mqs_right: IOMUXC_GPIO_EMC_13_MQS_RIGHT { + pinmux = <0x401f8048 3 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_addr04: IOMUXC_GPIO_EMC_13_SEMC_ADDR04 { + pinmux = <0x401f8048 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in25: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN25 { + pinmux = <0x401f8048 1 0x401f8650 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio4_io14: IOMUXC_GPIO_EMC_14_GPIO4_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio9_io14: IOMUXC_GPIO_EMC_14_GPIO9_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart3_rx: IOMUXC_GPIO_EMC_14_LPUART3_RX { + pinmux = <0x401f804c 2 0x401f8538 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_mqs_left: IOMUXC_GPIO_EMC_14_MQS_LEFT { + pinmux = <0x401f804c 3 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_addr05: IOMUXC_GPIO_EMC_14_SEMC_ADDR05 { + pinmux = <0x401f804c 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN19 { + pinmux = <0x401f804c 1 0x401f8654 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f804c 1 0x401f8654 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio4_io15: IOMUXC_GPIO_EMC_15_GPIO4_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio9_io15: IOMUXC_GPIO_EMC_15_GPIO9_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart3_cts_b: IOMUXC_GPIO_EMC_15_LPUART3_CTS_B { + pinmux = <0x401f8050 2 0x401f8534 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_qtimer3_timer0: IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 { + pinmux = <0x401f8050 4 0x401f857c 0 0x401f8240>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr06: IOMUXC_GPIO_EMC_15_SEMC_ADDR06 { + pinmux = <0x401f8050 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_spdif_out: IOMUXC_GPIO_EMC_15_SPDIF_OUT { + pinmux = <0x401f8050 3 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in20: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN20 { + pinmux = <0x401f8050 1 0x401f8634 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio4_io16: IOMUXC_GPIO_EMC_16_GPIO4_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio9_io16: IOMUXC_GPIO_EMC_16_GPIO9_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_lpuart3_rts_b: IOMUXC_GPIO_EMC_16_LPUART3_RTS_B { + pinmux = <0x401f8054 2 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_qtimer3_timer1: IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 { + pinmux = <0x401f8054 4 0x401f8580 1 0x401f8244>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr07: IOMUXC_GPIO_EMC_16_SEMC_ADDR07 { + pinmux = <0x401f8054 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_spdif_in: IOMUXC_GPIO_EMC_16_SPDIF_IN { + pinmux = <0x401f8054 3 0x401f85c8 1 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_xbar1_xbar_in21: IOMUXC_GPIO_EMC_16_XBAR1_XBAR_IN21 { + pinmux = <0x401f8054 1 0x401f8658 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexcan1_tx: IOMUXC_GPIO_EMC_17_FLEXCAN1_TX { + pinmux = <0x401f8058 3 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexpwm4_pwma3: IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA3 { + pinmux = <0x401f8058 1 0x401f84a0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio4_io17: IOMUXC_GPIO_EMC_17_GPIO4_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio9_io17: IOMUXC_GPIO_EMC_17_GPIO9_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_lpuart4_cts_b: IOMUXC_GPIO_EMC_17_LPUART4_CTS_B { + pinmux = <0x401f8058 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_qtimer3_timer2: IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 { + pinmux = <0x401f8058 4 0x401f8584 0 0x401f8248>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr08: IOMUXC_GPIO_EMC_17_SEMC_ADDR08 { + pinmux = <0x401f8058 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexcan1_rx: IOMUXC_GPIO_EMC_18_FLEXCAN1_RX { + pinmux = <0x401f805c 3 0x401f844c 1 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexpwm4_pwmb3: IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB3 { + pinmux = <0x401f805c 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio4_io18: IOMUXC_GPIO_EMC_18_GPIO4_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio9_io18: IOMUXC_GPIO_EMC_18_GPIO9_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpuart4_rts_b: IOMUXC_GPIO_EMC_18_LPUART4_RTS_B { + pinmux = <0x401f805c 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_qtimer3_timer3: IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 { + pinmux = <0x401f805c 4 0x401f8588 0 0x401f824c>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr09: IOMUXC_GPIO_EMC_18_SEMC_ADDR09 { + pinmux = <0x401f805c 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_snvs_vio_5_ctl: IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL { + pinmux = <0x401f805c 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_enet_rx_data1: IOMUXC_GPIO_EMC_19_ENET_RX_DATA1 { + pinmux = <0x401f8060 3 0x401f8438 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexpwm2_pwma3: IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA3 { + pinmux = <0x401f8060 1 0x401f8474 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio4_io19: IOMUXC_GPIO_EMC_19_GPIO4_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio9_io19: IOMUXC_GPIO_EMC_19_GPIO9_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpuart4_tx: IOMUXC_GPIO_EMC_19_LPUART4_TX { + pinmux = <0x401f8060 2 0x401f8544 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_qtimer2_timer0: IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 { + pinmux = <0x401f8060 4 0x401f856c 0 0x401f8250>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr11: IOMUXC_GPIO_EMC_19_SEMC_ADDR11 { + pinmux = <0x401f8060 0 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_snvs_vio_5_b: IOMUXC_GPIO_EMC_19_SNVS_VIO_5_B { + pinmux = <0x401f8060 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_enet_rx_data0: IOMUXC_GPIO_EMC_20_ENET_RX_DATA0 { + pinmux = <0x401f8064 3 0x401f8434 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB3 { + pinmux = <0x401f8064 1 0x401f8484 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio4_io20: IOMUXC_GPIO_EMC_20_GPIO4_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio9_io20: IOMUXC_GPIO_EMC_20_GPIO9_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart4_rx: IOMUXC_GPIO_EMC_20_LPUART4_RX { + pinmux = <0x401f8064 2 0x401f8540 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_qtimer2_timer1: IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 { + pinmux = <0x401f8064 4 0x401f8570 0 0x401f8254>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr12: IOMUXC_GPIO_EMC_20_SEMC_ADDR12 { + pinmux = <0x401f8064 0 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_enet_tx_data1: IOMUXC_GPIO_EMC_21_ENET_TX_DATA1 { + pinmux = <0x401f8068 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm3_pwma3: IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA3 { + pinmux = <0x401f8068 1 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio4_io21: IOMUXC_GPIO_EMC_21_GPIO4_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio9_io21: IOMUXC_GPIO_EMC_21_GPIO9_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpi2c3_sda: IOMUXC_GPIO_EMC_21_LPI2C3_SDA { + pinmux = <0x401f8068 2 0x401f84e0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_qtimer2_timer2: IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 { + pinmux = <0x401f8068 4 0x401f8574 0 0x401f8258>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_ba0: IOMUXC_GPIO_EMC_21_SEMC_BA0 { + pinmux = <0x401f8068 0 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_enet_tx_data0: IOMUXC_GPIO_EMC_22_ENET_TX_DATA0 { + pinmux = <0x401f806c 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm3_pwmb3: IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB3 { + pinmux = <0x401f806c 1 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio4_io22: IOMUXC_GPIO_EMC_22_GPIO4_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio9_io22: IOMUXC_GPIO_EMC_22_GPIO9_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpi2c3_scl: IOMUXC_GPIO_EMC_22_LPI2C3_SCL { + pinmux = <0x401f806c 2 0x401f84dc 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_qtimer2_timer3: IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 { + pinmux = <0x401f806c 4 0x401f8578 0 0x401f825c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_ba1: IOMUXC_GPIO_EMC_22_SEMC_BA1 { + pinmux = <0x401f806c 0 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_enet_rx_en: IOMUXC_GPIO_EMC_23_ENET_RX_EN { + pinmux = <0x401f8070 3 0x401f843c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwma0: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA0 { + pinmux = <0x401f8070 1 0x401f8458 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio4_io23: IOMUXC_GPIO_EMC_23_GPIO4_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio9_io23: IOMUXC_GPIO_EMC_23_GPIO9_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpt1_capture2: IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 { + pinmux = <0x401f8070 4 0x401f875c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart5_tx: IOMUXC_GPIO_EMC_23_LPUART5_TX { + pinmux = <0x401f8070 2 0x401f854c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr10: IOMUXC_GPIO_EMC_23_SEMC_ADDR10 { + pinmux = <0x401f8070 0 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_enet_tx_en: IOMUXC_GPIO_EMC_24_ENET_TX_EN { + pinmux = <0x401f8074 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB0 { + pinmux = <0x401f8074 1 0x401f8468 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio4_io24: IOMUXC_GPIO_EMC_24_GPIO4_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio9_io24: IOMUXC_GPIO_EMC_24_GPIO9_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpt1_capture1: IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 { + pinmux = <0x401f8074 4 0x401f8758 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart5_rx: IOMUXC_GPIO_EMC_24_LPUART5_RX { + pinmux = <0x401f8074 2 0x401f8548 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_cas: IOMUXC_GPIO_EMC_24_SEMC_CAS { + pinmux = <0x401f8074 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_ref_clk: IOMUXC_GPIO_EMC_25_ENET_REF_CLK { + pinmux = <0x401f8078 4 0x401f842c 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_tx_clk: IOMUXC_GPIO_EMC_25_ENET_TX_CLK { + pinmux = <0x401f8078 3 0x401f8448 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwma1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA1 { + pinmux = <0x401f8078 1 0x401f845c 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio4_io25: IOMUXC_GPIO_EMC_25_GPIO4_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio9_io25: IOMUXC_GPIO_EMC_25_GPIO9_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart6_tx: IOMUXC_GPIO_EMC_25_LPUART6_TX { + pinmux = <0x401f8078 2 0x401f8554 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_ras: IOMUXC_GPIO_EMC_25_SEMC_RAS { + pinmux = <0x401f8078 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_enet_rx_er: IOMUXC_GPIO_EMC_26_ENET_RX_ER { + pinmux = <0x401f807c 3 0x401f8440 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio12: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 { + pinmux = <0x401f807c 4 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB1 { + pinmux = <0x401f807c 1 0x401f846c 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio4_io26: IOMUXC_GPIO_EMC_26_GPIO4_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio9_io26: IOMUXC_GPIO_EMC_26_GPIO9_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart6_rx: IOMUXC_GPIO_EMC_26_LPUART6_RX { + pinmux = <0x401f807c 2 0x401f8550 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_clk: IOMUXC_GPIO_EMC_26_SEMC_CLK { + pinmux = <0x401f807c 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio13: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8080 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwma2: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA2 { + pinmux = <0x401f8080 1 0x401f8460 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio4_io27: IOMUXC_GPIO_EMC_27_GPIO4_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio9_io27: IOMUXC_GPIO_EMC_27_GPIO9_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpspi1_sck: IOMUXC_GPIO_EMC_27_LPSPI1_SCK { + pinmux = <0x401f8080 3 0x401f84f0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart5_rts_b: IOMUXC_GPIO_EMC_27_LPUART5_RTS_B { + pinmux = <0x401f8080 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_cke: IOMUXC_GPIO_EMC_27_SEMC_CKE { + pinmux = <0x401f8080 0 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexio1_flexio14: IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8084 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB2 { + pinmux = <0x401f8084 1 0x401f8470 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio4_io28: IOMUXC_GPIO_EMC_28_GPIO4_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio9_io28: IOMUXC_GPIO_EMC_28_GPIO9_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpspi1_sdo: IOMUXC_GPIO_EMC_28_LPSPI1_SDO { + pinmux = <0x401f8084 3 0x401f84f8 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpuart5_cts_b: IOMUXC_GPIO_EMC_28_LPUART5_CTS_B { + pinmux = <0x401f8084 2 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_we: IOMUXC_GPIO_EMC_28_SEMC_WE { + pinmux = <0x401f8084 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexio1_flexio15: IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 { + pinmux = <0x401f8088 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm3_pwma0: IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA0 { + pinmux = <0x401f8088 1 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio4_io29: IOMUXC_GPIO_EMC_29_GPIO4_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio9_io29: IOMUXC_GPIO_EMC_29_GPIO9_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpspi1_sdi: IOMUXC_GPIO_EMC_29_LPSPI1_SDI { + pinmux = <0x401f8088 3 0x401f84f4 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpuart6_rts_b: IOMUXC_GPIO_EMC_29_LPUART6_RTS_B { + pinmux = <0x401f8088 2 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cs0: IOMUXC_GPIO_EMC_29_SEMC_CS0 { + pinmux = <0x401f8088 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_csi_data23: IOMUXC_GPIO_EMC_30_CSI_DATA23 { + pinmux = <0x401f808c 4 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_enet2_tx_data0: IOMUXC_GPIO_EMC_30_ENET2_TX_DATA0 { + pinmux = <0x401f808c 8 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm3_pwmb0: IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB0 { + pinmux = <0x401f808c 1 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio4_io30: IOMUXC_GPIO_EMC_30_GPIO4_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio9_io30: IOMUXC_GPIO_EMC_30_GPIO9_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpspi1_pcs0: IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 { + pinmux = <0x401f808c 3 0x401f84ec 1 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart6_cts_b: IOMUXC_GPIO_EMC_30_LPUART6_CTS_B { + pinmux = <0x401f808c 2 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_data08: IOMUXC_GPIO_EMC_30_SEMC_DATA08 { + pinmux = <0x401f808c 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_csi_data22: IOMUXC_GPIO_EMC_31_CSI_DATA22 { + pinmux = <0x401f8090 4 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_enet2_tx_data1: IOMUXC_GPIO_EMC_31_ENET2_TX_DATA1 { + pinmux = <0x401f8090 8 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm3_pwma1: IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA1 { + pinmux = <0x401f8090 1 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio4_io31: IOMUXC_GPIO_EMC_31_GPIO4_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio9_io31: IOMUXC_GPIO_EMC_31_GPIO9_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpspi1_pcs1: IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 { + pinmux = <0x401f8090 3 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart7_tx: IOMUXC_GPIO_EMC_31_LPUART7_TX { + pinmux = <0x401f8090 2 0x401f855c 1 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_data09: IOMUXC_GPIO_EMC_31_SEMC_DATA09 { + pinmux = <0x401f8090 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ccm_pmic_rdy: IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY { + pinmux = <0x401f8094 3 0x401f83fc 4 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_csi_data21: IOMUXC_GPIO_EMC_32_CSI_DATA21 { + pinmux = <0x401f8094 4 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_enet2_tx_en: IOMUXC_GPIO_EMC_32_ENET2_TX_EN { + pinmux = <0x401f8094 8 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_flexpwm3_pwmb1: IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB1 { + pinmux = <0x401f8094 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io18: IOMUXC_GPIO_EMC_32_GPIO3_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio8_io18: IOMUXC_GPIO_EMC_32_GPIO8_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart7_rx: IOMUXC_GPIO_EMC_32_LPUART7_RX { + pinmux = <0x401f8094 2 0x401f8558 1 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data10: IOMUXC_GPIO_EMC_32_SEMC_DATA10 { + pinmux = <0x401f8094 0 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_csi_data20: IOMUXC_GPIO_EMC_33_CSI_DATA20 { + pinmux = <0x401f8098 4 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_enet2_ref_clk2: IOMUXC_GPIO_EMC_33_ENET2_REF_CLK2 { + pinmux = <0x401f8098 9 0x401f870c 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_enet2_tx_clk: IOMUXC_GPIO_EMC_33_ENET2_TX_CLK { + pinmux = <0x401f8098 8 0x401f8728 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_flexpwm3_pwma2: IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA2 { + pinmux = <0x401f8098 1 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io19: IOMUXC_GPIO_EMC_33_GPIO3_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio8_io19: IOMUXC_GPIO_EMC_33_GPIO8_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_rx_data: IOMUXC_GPIO_EMC_33_SAI3_RX_DATA { + pinmux = <0x401f8098 3 0x401f8778 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data11: IOMUXC_GPIO_EMC_33_SEMC_DATA11 { + pinmux = <0x401f8098 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_usdhc1_reset_b: IOMUXC_GPIO_EMC_33_USDHC1_RESET_B { + pinmux = <0x401f8098 2 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_csi_data19: IOMUXC_GPIO_EMC_34_CSI_DATA19 { + pinmux = <0x401f809c 4 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_enet2_rx_er: IOMUXC_GPIO_EMC_34_ENET2_RX_ER { + pinmux = <0x401f809c 8 0x401f8720 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_flexpwm3_pwmb2: IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB2 { + pinmux = <0x401f809c 1 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io20: IOMUXC_GPIO_EMC_34_GPIO3_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio8_io20: IOMUXC_GPIO_EMC_34_GPIO8_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_rx_sync: IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC { + pinmux = <0x401f809c 3 0x401f877c 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data12: IOMUXC_GPIO_EMC_34_SEMC_DATA12 { + pinmux = <0x401f809c 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_usdhc1_vselect: IOMUXC_GPIO_EMC_34_USDHC1_VSELECT { + pinmux = <0x401f809c 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_csi_data18: IOMUXC_GPIO_EMC_35_CSI_DATA18 { + pinmux = <0x401f80a0 4 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_enet2_rx_data0: IOMUXC_GPIO_EMC_35_ENET2_RX_DATA0 { + pinmux = <0x401f80a0 8 0x401f8714 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io21: IOMUXC_GPIO_EMC_35_GPIO3_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio8_io21: IOMUXC_GPIO_EMC_35_GPIO8_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpt1_compare1: IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 { + pinmux = <0x401f80a0 2 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_sai3_rx_bclk: IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK { + pinmux = <0x401f80a0 3 0x401f8774 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data13: IOMUXC_GPIO_EMC_35_SEMC_DATA13 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc1_cd_b: IOMUXC_GPIO_EMC_35_USDHC1_CD_B { + pinmux = <0x401f80a0 6 0x401f85d4 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_in18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_IN18 { + pinmux = <0x401f80a0 1 0x401f8630 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80a0 1 0x401f8630 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_csi_data17: IOMUXC_GPIO_EMC_36_CSI_DATA17 { + pinmux = <0x401f80a4 4 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_enet2_rx_data1: IOMUXC_GPIO_EMC_36_ENET2_RX_DATA1 { + pinmux = <0x401f80a4 8 0x401f8718 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexcan3_tx: IOMUXC_GPIO_EMC_36_FLEXCAN3_TX { + pinmux = <0x401f80a4 9 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io22: IOMUXC_GPIO_EMC_36_GPIO3_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio8_io22: IOMUXC_GPIO_EMC_36_GPIO8_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpt1_compare2: IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 { + pinmux = <0x401f80a4 2 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_sai3_tx_data: IOMUXC_GPIO_EMC_36_SAI3_TX_DATA { + pinmux = <0x401f80a4 3 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data14: IOMUXC_GPIO_EMC_36_SEMC_DATA14 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 6 0x401f85d8 1 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_xbar1_xbar_in22: IOMUXC_GPIO_EMC_36_XBAR1_XBAR_IN22 { + pinmux = <0x401f80a4 1 0x401f8638 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_csi_data16: IOMUXC_GPIO_EMC_37_CSI_DATA16 { + pinmux = <0x401f80a8 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_enet2_rx_en: IOMUXC_GPIO_EMC_37_ENET2_RX_EN { + pinmux = <0x401f80a8 8 0x401f871c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexcan3_rx: IOMUXC_GPIO_EMC_37_FLEXCAN3_RX { + pinmux = <0x401f80a8 9 0x401f878c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io23: IOMUXC_GPIO_EMC_37_GPIO3_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio8_io23: IOMUXC_GPIO_EMC_37_GPIO8_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpt1_compare3: IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 { + pinmux = <0x401f80a8 2 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_sai3_mclk: IOMUXC_GPIO_EMC_37_SAI3_MCLK { + pinmux = <0x401f80a8 3 0x401f8770 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data15: IOMUXC_GPIO_EMC_37_SEMC_DATA15 { + pinmux = <0x401f80a8 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc2_wp: IOMUXC_GPIO_EMC_37_USDHC2_WP { + pinmux = <0x401f80a8 6 0x401f8608 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_xbar1_xbar_in23: IOMUXC_GPIO_EMC_37_XBAR1_XBAR_IN23 { + pinmux = <0x401f80a8 1 0x401f863c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_csi_field: IOMUXC_GPIO_EMC_38_CSI_FIELD { + pinmux = <0x401f80ac 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_enet2_mdc: IOMUXC_GPIO_EMC_38_ENET2_MDC { + pinmux = <0x401f80ac 8 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm1_pwma3: IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA3 { + pinmux = <0x401f80ac 1 0x401f8454 2 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io24: IOMUXC_GPIO_EMC_38_GPIO3_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio8_io24: IOMUXC_GPIO_EMC_38_GPIO8_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart8_tx: IOMUXC_GPIO_EMC_38_LPUART8_TX { + pinmux = <0x401f80ac 2 0x401f8564 2 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_sai3_tx_bclk: IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK { + pinmux = <0x401f80ac 3 0x401f8780 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_dm1: IOMUXC_GPIO_EMC_38_SEMC_DM1 { + pinmux = <0x401f80ac 0 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc2_vselect: IOMUXC_GPIO_EMC_38_USDHC2_VSELECT { + pinmux = <0x401f80ac 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_enet2_mdio: IOMUXC_GPIO_EMC_39_ENET2_MDIO { + pinmux = <0x401f80b0 8 0x401f8710 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB3 { + pinmux = <0x401f80b0 1 0x401f8464 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io25: IOMUXC_GPIO_EMC_39_GPIO3_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio8_io25: IOMUXC_GPIO_EMC_39_GPIO8_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart8_rx: IOMUXC_GPIO_EMC_39_LPUART8_RX { + pinmux = <0x401f80b0 2 0x401f8560 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_sai3_tx_sync: IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC { + pinmux = <0x401f80b0 3 0x401f8784 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs: IOMUXC_GPIO_EMC_39_SEMC_DQS { + pinmux = <0x401f80b0 0 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs4: IOMUXC_GPIO_EMC_39_SEMC_DQS4 { + pinmux = <0x401f80b0 9 0x401f8788 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usdhc2_cd_b: IOMUXC_GPIO_EMC_39_USDHC2_CD_B { + pinmux = <0x401f80b0 6 0x401f85e0 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdc: IOMUXC_GPIO_EMC_40_ENET_MDC { + pinmux = <0x401f80b4 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io26: IOMUXC_GPIO_EMC_40_GPIO3_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio8_io26: IOMUXC_GPIO_EMC_40_GPIO8_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt2_capture2: IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 { + pinmux = <0x401f80b4 1 0x401f8768 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_lpspi1_pcs2: IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 { + pinmux = <0x401f80b4 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_clk5: IOMUXC_GPIO_EMC_40_SEMC_CLK5 { + pinmux = <0x401f80b4 9 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_rdy: IOMUXC_GPIO_EMC_40_SEMC_RDY { + pinmux = <0x401f80b4 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usb_otg2_oc: IOMUXC_GPIO_EMC_40_USB_OTG2_OC { + pinmux = <0x401f80b4 3 0x401f85cc 1 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usdhc2_reset_b: IOMUXC_GPIO_EMC_40_USDHC2_RESET_B { + pinmux = <0x401f80b4 6 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdio: IOMUXC_GPIO_EMC_41_ENET_MDIO { + pinmux = <0x401f80b8 4 0x401f8430 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io27: IOMUXC_GPIO_EMC_41_GPIO3_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio8_io27: IOMUXC_GPIO_EMC_41_GPIO8_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt2_capture1: IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 { + pinmux = <0x401f80b8 1 0x401f8764 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_lpspi1_pcs3: IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 { + pinmux = <0x401f80b8 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_csx0: IOMUXC_GPIO_EMC_41_SEMC_CSX0 { + pinmux = <0x401f80b8 0 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usb_otg2_pwr: IOMUXC_GPIO_EMC_41_USB_OTG2_PWR { + pinmux = <0x401f80b8 3 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usdhc1_vselect: IOMUXC_GPIO_EMC_41_USDHC1_VSELECT { + pinmux = <0x401f80b8 6 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_enet2_tx_en: IOMUXC_GPIO_SD_B0_00_ENET2_TX_EN { + pinmux = <0x401f81bc 8 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexpwm1_pwma0: IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA0 { + pinmux = <0x401f81bc 1 0x401f8458 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f81bc 6 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io12: IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio8_io12: IOMUXC_GPIO_SD_B0_00_GPIO8_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f81bc 2 0x401f84dc 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpspi1_sck: IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK { + pinmux = <0x401f81bc 4 0x401f84f0 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_semc_dqs4: IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 { + pinmux = <0x401f81bc 9 0x401f8788 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_cmd: IOMUXC_GPIO_SD_B0_00_USDHC1_CMD { + pinmux = <0x401f81bc 0 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN04 { + pinmux = <0x401f81bc 3 0x401f8614 1 0x401f83ac>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f81bc 3 0x401f8614 1 0x401f83ac>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_enet2_ref_clk2: IOMUXC_GPIO_SD_B0_01_ENET2_REF_CLK2 { + pinmux = <0x401f81c0 9 0x401f870c 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_enet2_tx_clk: IOMUXC_GPIO_SD_B0_01_ENET2_TX_CLK { + pinmux = <0x401f81c0 8 0x401f8728 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexpwm1_pwmb0: IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB0 { + pinmux = <0x401f81c0 1 0x401f8468 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f81c0 6 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io13: IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio8_io13: IOMUXC_GPIO_SD_B0_01_GPIO8_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f81c0 2 0x401f84e0 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 { + pinmux = <0x401f81c0 4 0x401f84ec 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_clk: IOMUXC_GPIO_SD_B0_01_USDHC1_CLK { + pinmux = <0x401f81c0 0 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN05 { + pinmux = <0x401f81c0 3 0x401f8618 1 0x401f83b0>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f81c0 3 0x401f8618 1 0x401f83b0>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_enet2_rx_er: IOMUXC_GPIO_SD_B0_02_ENET2_RX_ER { + pinmux = <0x401f81c4 8 0x401f8720 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_flexpwm1_pwma1: IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA1 { + pinmux = <0x401f81c4 1 0x401f845c 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io14: IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio8_io14: IOMUXC_GPIO_SD_B0_02_GPIO8_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sdo: IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO { + pinmux = <0x401f81c4 4 0x401f84f8 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart8_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B { + pinmux = <0x401f81c4 2 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_semc_clk5: IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 { + pinmux = <0x401f81c4 9 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_data0: IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 { + pinmux = <0x401f81c4 0 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN06 { + pinmux = <0x401f81c4 3 0x401f861c 1 0x401f83b4>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f81c4 3 0x401f861c 1 0x401f83b4>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_enet2_rx_data0: IOMUXC_GPIO_SD_B0_03_ENET2_RX_DATA0 { + pinmux = <0x401f81c8 8 0x401f8714 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_flexpwm1_pwmb1: IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB1 { + pinmux = <0x401f81c8 1 0x401f846c 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io15: IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio8_io15: IOMUXC_GPIO_SD_B0_03_GPIO8_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_sdi: IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI { + pinmux = <0x401f81c8 4 0x401f84f4 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart8_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B { + pinmux = <0x401f81c8 2 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_semc_clk6: IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 { + pinmux = <0x401f81c8 9 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_data1: IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 { + pinmux = <0x401f81c8 0 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_in07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_IN07 { + pinmux = <0x401f81c8 3 0x401f8620 1 0x401f83b8>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_inout07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f81c8 3 0x401f8620 1 0x401f83b8>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_ccm_clko1: IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 { + pinmux = <0x401f81cc 6 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_enet2_rx_data1: IOMUXC_GPIO_SD_B0_04_ENET2_RX_DATA1 { + pinmux = <0x401f81cc 8 0x401f8718 1 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexpwm1_pwma2: IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA2 { + pinmux = <0x401f81cc 1 0x401f8460 1 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f81cc 4 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io16: IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio8_io16: IOMUXC_GPIO_SD_B0_04_GPIO8_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart8_tx: IOMUXC_GPIO_SD_B0_04_LPUART8_TX { + pinmux = <0x401f81cc 2 0x401f8564 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data2: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 { + pinmux = <0x401f81cc 0 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_in08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_IN08 { + pinmux = <0x401f81cc 3 0x401f8624 1 0x401f83bc>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_inout08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f81cc 3 0x401f8624 1 0x401f83bc>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_ccm_clko2: IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 { + pinmux = <0x401f81d0 6 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_enet2_rx_en: IOMUXC_GPIO_SD_B0_05_ENET2_RX_EN { + pinmux = <0x401f81d0 8 0x401f871c 1 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexpwm1_pwmb2: IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB2 { + pinmux = <0x401f81d0 1 0x401f8470 1 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f81d0 4 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io17: IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio8_io17: IOMUXC_GPIO_SD_B0_05_GPIO8_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart8_rx: IOMUXC_GPIO_SD_B0_05_LPUART8_RX { + pinmux = <0x401f81d0 2 0x401f8560 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data3: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 { + pinmux = <0x401f81d0 0 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_in09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_IN09 { + pinmux = <0x401f81d0 3 0x401f8628 1 0x401f83c0>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_inout09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f81d0 3 0x401f8628 1 0x401f83c0>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f81d4 2 0x401f8454 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f81d4 1 0x401f84c4 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io00: IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio8_io00: IOMUXC_GPIO_SD_B1_00_GPIO8_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart4_tx: IOMUXC_GPIO_SD_B1_00_LPUART4_TX { + pinmux = <0x401f81d4 4 0x401f8544 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai1_tx_data3: IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA3 { + pinmux = <0x401f81d4 3 0x401f8598 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai3_rx_data: IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA { + pinmux = <0x401f81d4 8 0x401f8778 1 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data3: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 { + pinmux = <0x401f81d4 0 0x401f85f4 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f81d8 2 0x401f8464 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_data2: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 { + pinmux = <0x401f81d8 1 0x401f84c0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io01: IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio8_io01: IOMUXC_GPIO_SD_B1_01_GPIO8_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart4_rx: IOMUXC_GPIO_SD_B1_01_LPUART4_RX { + pinmux = <0x401f81d8 4 0x401f8540 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai1_tx_data2: IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA2 { + pinmux = <0x401f81d8 3 0x401f859c 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai3_tx_data: IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA { + pinmux = <0x401f81d8 8 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data2: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 { + pinmux = <0x401f81d8 0 0x401f85f0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_wait: IOMUXC_GPIO_SD_B1_02_CCM_WAIT { + pinmux = <0x401f81dc 6 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexcan1_tx: IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX { + pinmux = <0x401f81dc 4 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f81dc 2 0x401f8474 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data1: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 { + pinmux = <0x401f81dc 1 0x401f84bc 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io02: IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio8_io02: IOMUXC_GPIO_SD_B1_02_GPIO8_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai1_tx_data1: IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA1 { + pinmux = <0x401f81dc 3 0x401f85a0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai3_tx_sync: IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC { + pinmux = <0x401f81dc 8 0x401f8784 1 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_data1: IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 { + pinmux = <0x401f81dc 0 0x401f85ec 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_03_CCM_PMIC_RDY { + pinmux = <0x401f81e0 6 0x401f83fc 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexcan1_rx: IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX { + pinmux = <0x401f81e0 4 0x401f844c 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f81e0 2 0x401f8484 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data0: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 { + pinmux = <0x401f81e0 1 0x401f84b8 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io03: IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio8_io03: IOMUXC_GPIO_SD_B1_03_GPIO8_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai1_mclk: IOMUXC_GPIO_SD_B1_03_SAI1_MCLK { + pinmux = <0x401f81e0 3 0x401f858c 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK { + pinmux = <0x401f81e0 8 0x401f8780 1 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_data0: IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 { + pinmux = <0x401f81e0 0 0x401f85e8 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_stop: IOMUXC_GPIO_SD_B1_04_CCM_STOP { + pinmux = <0x401f81e4 6 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI_A_SS1_B { + pinmux = <0x401f81e4 4 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK { + pinmux = <0x401f81e4 1 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io04: IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio8_io04: IOMUXC_GPIO_SD_B1_04_GPIO8_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_lpi2c1_scl: IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL { + pinmux = <0x401f81e4 2 0x401f84cc 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai1_rx_sync: IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f81e4 3 0x401f85a4 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai3_mclk: IOMUXC_GPIO_SD_B1_04_SAI3_MCLK { + pinmux = <0x401f81e4 8 0x401f8770 1 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_clk: IOMUXC_GPIO_SD_B1_04_USDHC2_CLK { + pinmux = <0x401f81e4 0 0x401f85dc 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f81e8 1 0x401f84a4 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f81e8 4 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io05: IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio8_io05: IOMUXC_GPIO_SD_B1_05_GPIO8_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_lpi2c1_sda: IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA { + pinmux = <0x401f81e8 2 0x401f84d0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai1_rx_bclk: IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK { + pinmux = <0x401f81e8 3 0x401f8590 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_rx_sync: IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC { + pinmux = <0x401f81e8 8 0x401f877c 1 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_cmd: IOMUXC_GPIO_SD_B1_05_USDHC2_CMD { + pinmux = <0x401f81e8 0 0x401f85e4 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B { + pinmux = <0x401f81ec 1 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io06: IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio8_io06: IOMUXC_GPIO_SD_B1_06_GPIO8_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f81ec 4 0x401f84fc 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpuart7_cts_b: IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B { + pinmux = <0x401f81ec 2 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai1_rx_data0: IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA0 { + pinmux = <0x401f81ec 3 0x401f8594 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK { + pinmux = <0x401f81ec 8 0x401f8774 1 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B { + pinmux = <0x401f81ec 0 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f81f0 1 0x401f84c8 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io07: IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio8_io07: IOMUXC_GPIO_SD_B1_07_GPIO8_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f81f0 4 0x401f8500 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpuart7_rts_b: IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B { + pinmux = <0x401f81f0 2 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai1_tx_data0: IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA0 { + pinmux = <0x401f81f0 3 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_semc_csx1: IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 { + pinmux = <0x401f81f0 0 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f81f4 1 0x401f84a8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io08: IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio8_io08: IOMUXC_GPIO_SD_B1_08_GPIO8_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f81f4 4 0x401f8508 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpuart7_tx: IOMUXC_GPIO_SD_B1_08_LPUART7_TX { + pinmux = <0x401f81f4 2 0x401f855c 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai1_tx_bclk: IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK { + pinmux = <0x401f81f4 3 0x401f85a8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_semc_csx2: IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 { + pinmux = <0x401f81f4 6 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f81f4 0 0x401f85f8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data1: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 { + pinmux = <0x401f81f8 1 0x401f84ac 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io09: IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio8_io09: IOMUXC_GPIO_SD_B1_09_GPIO8_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f81f8 4 0x401f8504 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpuart7_rx: IOMUXC_GPIO_SD_B1_09_LPUART7_RX { + pinmux = <0x401f81f8 2 0x401f8558 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai1_tx_sync: IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC { + pinmux = <0x401f81f8 3 0x401f85ac 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f81f8 0 0x401f85fc 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data2: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 { + pinmux = <0x401f81fc 1 0x401f84b0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io10: IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio8_io10: IOMUXC_GPIO_SD_B1_10_GPIO8_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpi2c2_sda: IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA { + pinmux = <0x401f81fc 3 0x401f84d8 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f81fc 4 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpuart2_rx: IOMUXC_GPIO_SD_B1_10_LPUART2_RX { + pinmux = <0x401f81fc 2 0x401f852c 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f81fc 0 0x401f8600 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_data3: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 { + pinmux = <0x401f8200 1 0x401f84b4 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io11: IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio8_io11: IOMUXC_GPIO_SD_B1_11_GPIO8_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpi2c2_scl: IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL { + pinmux = <0x401f8200 3 0x401f84d4 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8200 4 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpuart2_tx: IOMUXC_GPIO_SD_B1_11_LPUART2_TX { + pinmux = <0x401f8200 2 0x401f8530 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8200 0 0x401f8604 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_ccm_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ { + pinmux = <0x400a8008 0 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_gpio5_io02: IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 { + pinmux = <0x400a8008 5 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x0 0 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1064dvl6b-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1064dvl6b-pinctrl.dtsi new file mode 100644 index 000000000..2cc44e9c7 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1064dvl6b-pinctrl.dtsi @@ -0,0 +1,3925 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1064DVL6B + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_acmp1_in4: IOMUXC_GPIO_AD_B0_00_ACMP1_IN4 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA3 { + pinmux = <0x401f80bc 0 0x401f8474 2 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio1_io00: IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + gpr = <0x400ac068 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_gpio6_io00: IOMUXC_GPIO_AD_B0_00_GPIO6_IO00 { + pinmux = <0x401f80bc 5 0x0 0 0x401f82ac>; + gpr = <0x400ac068 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_lpi2c1_scls: IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS { + pinmux = <0x401f80bc 4 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_lpspi3_sck: IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK { + pinmux = <0x401f80bc 7 0x401f8510 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_ref_32k_out: IOMUXC_GPIO_AD_B0_00_REF_32K_OUT { + pinmux = <0x401f80bc 2 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_usb_otg2_id: IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID { + pinmux = <0x401f80bc 3 0x401f83f8 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_usdhc1_reset_b: IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B { + pinmux = <0x401f80bc 6 0x0 0 0x401f82ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_xbar1_xbar_in14: IOMUXC_GPIO_AD_B0_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f80bc 1 0x401f8644 0 0x401f82ac>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_00_xbar1_xbar_inout14: IOMUXC_GPIO_AD_B0_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f80bc 1 0x401f8644 0 0x401f82ac>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_acmp2_in4: IOMUXC_GPIO_AD_B0_01_ACMP2_IN4 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_ewm_out_b: IOMUXC_GPIO_AD_B0_01_EWM_OUT_B { + pinmux = <0x401f80c0 6 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_flexpwm2_pwmb3: IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB3 { + pinmux = <0x401f80c0 0 0x401f8484 2 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio1_io01: IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + gpr = <0x400ac068 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_gpio6_io01: IOMUXC_GPIO_AD_B0_01_GPIO6_IO01 { + pinmux = <0x401f80c0 5 0x0 0 0x401f82b0>; + gpr = <0x400ac068 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_lpi2c1_sdas: IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS { + pinmux = <0x401f80c0 4 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_lpspi3_sdo: IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO { + pinmux = <0x401f80c0 7 0x401f8518 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_ref_24m_out: IOMUXC_GPIO_AD_B0_01_REF_24M_OUT { + pinmux = <0x401f80c0 2 0x0 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_usb_otg1_id: IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID { + pinmux = <0x401f80c0 3 0x401f83f4 0 0x401f82b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_xbar1_xbar_in15: IOMUXC_GPIO_AD_B0_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f80c0 1 0x401f8648 0 0x401f82b0>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_01_xbar1_xbar_inout15: IOMUXC_GPIO_AD_B0_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f80c0 1 0x401f8648 0 0x401f82b0>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_acmp3_in4: IOMUXC_GPIO_AD_B0_02_ACMP3_IN4 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_flexcan2_tx: IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX { + pinmux = <0x401f80c4 0 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_flexpwm1_pwmx0: IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX0 { + pinmux = <0x401f80c4 4 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio1_io02: IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + gpr = <0x400ac068 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_gpio6_io02: IOMUXC_GPIO_AD_B0_02_GPIO6_IO02 { + pinmux = <0x401f80c4 5 0x0 0 0x401f82b4>; + gpr = <0x400ac068 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpi2c1_hreq: IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ { + pinmux = <0x401f80c4 6 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpspi3_sdi: IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI { + pinmux = <0x401f80c4 7 0x401f8514 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_lpuart6_tx: IOMUXC_GPIO_AD_B0_02_LPUART6_TX { + pinmux = <0x401f80c4 2 0x401f8554 1 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_usb_otg1_pwr: IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR { + pinmux = <0x401f80c4 3 0x0 0 0x401f82b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_xbar1_xbar_in16: IOMUXC_GPIO_AD_B0_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f80c4 1 0x401f864c 0 0x401f82b4>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_02_xbar1_xbar_inout16: IOMUXC_GPIO_AD_B0_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f80c4 1 0x401f864c 0 0x401f82b4>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_acmp4_in4: IOMUXC_GPIO_AD_B0_03_ACMP4_IN4 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_flexcan2_rx: IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX { + pinmux = <0x401f80c8 0 0x401f8450 1 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_flexpwm1_pwmx1: IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX1 { + pinmux = <0x401f80c8 4 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio1_io03: IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + gpr = <0x400ac068 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_gpio6_io03: IOMUXC_GPIO_AD_B0_03_GPIO6_IO03 { + pinmux = <0x401f80c8 5 0x0 0 0x401f82b8>; + gpr = <0x400ac068 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_lpspi3_pcs0: IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 { + pinmux = <0x401f80c8 7 0x401f850c 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_lpuart6_rx: IOMUXC_GPIO_AD_B0_03_LPUART6_RX { + pinmux = <0x401f80c8 2 0x401f8550 1 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_ref_24m_out: IOMUXC_GPIO_AD_B0_03_REF_24M_OUT { + pinmux = <0x401f80c8 6 0x0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_usb_otg1_oc: IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC { + pinmux = <0x401f80c8 3 0x401f85d0 0 0x401f82b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f80c8 1 0x401f862c 1 0x401f82b8>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_03_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80c8 1 0x401f862c 1 0x401f82b8>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_csi_data09: IOMUXC_GPIO_AD_B0_04_CSI_DATA09 { + pinmux = <0x401f80cc 4 0x401f841c 1 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_enet_tx_data3: IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA3 { + pinmux = <0x401f80cc 2 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio1_io04: IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_gpio6_io04: IOMUXC_GPIO_AD_B0_04_GPIO6_IO04 { + pinmux = <0x401f80cc 5 0x0 0 0x401f82bc>; + gpr = <0x400ac068 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_lpspi3_pcs1: IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 { + pinmux = <0x401f80cc 7 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_mqs_right: IOMUXC_GPIO_AD_B0_04_MQS_RIGHT { + pinmux = <0x401f80cc 1 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_pit_trigger0: IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER0 { + pinmux = <0x401f80cc 6 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_sai2_tx_sync: IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC { + pinmux = <0x401f80cc 3 0x401f85c4 1 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_04_src_boot_mode0: IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE0 { + pinmux = <0x401f80cc 0 0x0 0 0x401f82bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_csi_data08: IOMUXC_GPIO_AD_B0_05_CSI_DATA08 { + pinmux = <0x401f80d0 4 0x401f8418 1 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_enet_tx_data2: IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA2 { + pinmux = <0x401f80d0 2 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio1_io05: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_gpio6_io05: IOMUXC_GPIO_AD_B0_05_GPIO6_IO05 { + pinmux = <0x401f80d0 5 0x0 0 0x401f82c0>; + gpr = <0x400ac068 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_lpspi3_pcs2: IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 { + pinmux = <0x401f80d0 7 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_mqs_left: IOMUXC_GPIO_AD_B0_05_MQS_LEFT { + pinmux = <0x401f80d0 1 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_sai2_tx_bclk: IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK { + pinmux = <0x401f80d0 3 0x401f85c0 1 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_src_boot_mode1: IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE1 { + pinmux = <0x401f80d0 0 0x0 0 0x401f82c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_in17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_IN17 { + pinmux = <0x401f80d0 6 0x401f862c 2 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_05_xbar1_xbar_inout17: IOMUXC_GPIO_AD_B0_05_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f80d0 6 0x401f862c 2 0x401f82c0>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_csi_data07: IOMUXC_GPIO_AD_B0_06_CSI_DATA07 { + pinmux = <0x401f80d4 4 0x401f8414 1 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_enet_rx_clk: IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK { + pinmux = <0x401f80d4 2 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio1_io06: IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpio6_io06: IOMUXC_GPIO_AD_B0_06_GPIO6_IO06 { + pinmux = <0x401f80d4 5 0x0 0 0x401f82c4>; + gpr = <0x400ac068 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_gpt2_compare1: IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 { + pinmux = <0x401f80d4 1 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_jtag_tms: IOMUXC_GPIO_AD_B0_06_JTAG_TMS { + pinmux = <0x401f80d4 0 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_lpspi3_pcs3: IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 { + pinmux = <0x401f80d4 7 0x0 0 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_sai2_rx_bclk: IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK { + pinmux = <0x401f80d4 3 0x401f85b4 1 0x401f82c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_in18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_IN18 { + pinmux = <0x401f80d4 6 0x401f8630 1 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_06_xbar1_xbar_inout18: IOMUXC_GPIO_AD_B0_06_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80d4 6 0x401f8630 1 0x401f82c4>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_csi_data06: IOMUXC_GPIO_AD_B0_07_CSI_DATA06 { + pinmux = <0x401f80d8 4 0x401f8410 1 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_1588_event3_out: IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT { + pinmux = <0x401f80d8 7 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_enet_tx_er: IOMUXC_GPIO_AD_B0_07_ENET_TX_ER { + pinmux = <0x401f80d8 2 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio1_io07: IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpio6_io07: IOMUXC_GPIO_AD_B0_07_GPIO6_IO07 { + pinmux = <0x401f80d8 5 0x0 0 0x401f82c8>; + gpr = <0x400ac068 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_gpt2_compare2: IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 { + pinmux = <0x401f80d8 1 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_jtag_tck: IOMUXC_GPIO_AD_B0_07_JTAG_TCK { + pinmux = <0x401f80d8 0 0x0 0 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_sai2_rx_sync: IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC { + pinmux = <0x401f80d8 3 0x401f85bc 1 0x401f82c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_in19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_IN19 { + pinmux = <0x401f80d8 6 0x401f8654 1 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_07_xbar1_xbar_inout19: IOMUXC_GPIO_AD_B0_07_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f80d8 6 0x401f8654 1 0x401f82c8>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_csi_data05: IOMUXC_GPIO_AD_B0_08_CSI_DATA05 { + pinmux = <0x401f80dc 4 0x401f840c 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_1588_event3_in: IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN { + pinmux = <0x401f80dc 7 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_enet_rx_data3: IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA3 { + pinmux = <0x401f80dc 2 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio1_io08: IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpio6_io08: IOMUXC_GPIO_AD_B0_08_GPIO6_IO08 { + pinmux = <0x401f80dc 5 0x0 0 0x401f82cc>; + gpr = <0x400ac068 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_gpt2_compare3: IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 { + pinmux = <0x401f80dc 1 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_jtag_mod: IOMUXC_GPIO_AD_B0_08_JTAG_MOD { + pinmux = <0x401f80dc 0 0x0 0 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_sai2_rx_data: IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA { + pinmux = <0x401f80dc 3 0x401f85b8 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_08_xbar1_xbar_in20: IOMUXC_GPIO_AD_B0_08_XBAR1_XBAR_IN20 { + pinmux = <0x401f80dc 6 0x401f8634 1 0x401f82cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_csi_data04: IOMUXC_GPIO_AD_B0_09_CSI_DATA04 { + pinmux = <0x401f80e0 4 0x401f8408 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_enet_rx_data2: IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA2 { + pinmux = <0x401f80e0 2 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_flexpwm2_pwma3: IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA3 { + pinmux = <0x401f80e0 1 0x401f8474 3 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio1_io09: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpio6_io09: IOMUXC_GPIO_AD_B0_09_GPIO6_IO09 { + pinmux = <0x401f80e0 5 0x0 0 0x401f82d0>; + gpr = <0x400ac068 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_gpt2_clk: IOMUXC_GPIO_AD_B0_09_GPT2_CLK { + pinmux = <0x401f80e0 7 0x401f876c 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_jtag_tdi: IOMUXC_GPIO_AD_B0_09_JTAG_TDI { + pinmux = <0x401f80e0 0 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_sai2_tx_data: IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA { + pinmux = <0x401f80e0 3 0x0 0 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_semc_dqs4: IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 { + pinmux = <0x401f80e0 9 0x401f8788 2 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_09_xbar1_xbar_in21: IOMUXC_GPIO_AD_B0_09_XBAR1_XBAR_IN21 { + pinmux = <0x401f80e0 6 0x401f8658 1 0x401f82d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_arm_trace_swo: IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO { + pinmux = <0x401f80e4 9 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_csi_data03: IOMUXC_GPIO_AD_B0_10_CSI_DATA03 { + pinmux = <0x401f80e4 4 0x401f8404 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80e4 7 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_enet_crs: IOMUXC_GPIO_AD_B0_10_ENET_CRS { + pinmux = <0x401f80e4 2 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexcan3_tx: IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX { + pinmux = <0x401f80e4 8 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_flexpwm1_pwma3: IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA3 { + pinmux = <0x401f80e4 1 0x401f8454 3 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio1_io10: IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_gpio6_io10: IOMUXC_GPIO_AD_B0_10_GPIO6_IO10 { + pinmux = <0x401f80e4 5 0x0 0 0x401f82d4>; + gpr = <0x400ac068 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_jtag_tdo: IOMUXC_GPIO_AD_B0_10_JTAG_TDO { + pinmux = <0x401f80e4 0 0x0 0 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_sai2_mclk: IOMUXC_GPIO_AD_B0_10_SAI2_MCLK { + pinmux = <0x401f80e4 3 0x401f85b0 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_10_xbar1_xbar_in22: IOMUXC_GPIO_AD_B0_10_XBAR1_XBAR_IN22 { + pinmux = <0x401f80e4 6 0x401f8638 1 0x401f82d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_csi_data02: IOMUXC_GPIO_AD_B0_11_CSI_DATA02 { + pinmux = <0x401f80e8 4 0x401f8400 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN { + pinmux = <0x401f80e8 7 0x401f8444 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_enet_col: IOMUXC_GPIO_AD_B0_11_ENET_COL { + pinmux = <0x401f80e8 2 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexcan3_rx: IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX { + pinmux = <0x401f80e8 8 0x401f878c 2 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_flexpwm1_pwmb3: IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB3 { + pinmux = <0x401f80e8 1 0x401f8464 3 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio1_io11: IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_gpio6_io11: IOMUXC_GPIO_AD_B0_11_GPIO6_IO11 { + pinmux = <0x401f80e8 5 0x0 0 0x401f82d8>; + gpr = <0x400ac068 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_jtag_trstb: IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB { + pinmux = <0x401f80e8 0 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_semc_clk6: IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 { + pinmux = <0x401f80e8 9 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_wdog1_b: IOMUXC_GPIO_AD_B0_11_WDOG1_B { + pinmux = <0x401f80e8 3 0x0 0 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_11_xbar1_xbar_in23: IOMUXC_GPIO_AD_B0_11_XBAR1_XBAR_IN23 { + pinmux = <0x401f80e8 6 0x401f863c 1 0x401f82d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_adc1_in1: IOMUXC_GPIO_AD_B0_12_ADC1_IN1 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_arm_nmi: IOMUXC_GPIO_AD_B0_12_ARM_NMI { + pinmux = <0x401f80ec 7 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_ccm_pmic_rdy: IOMUXC_GPIO_AD_B0_12_CCM_PMIC_RDY { + pinmux = <0x401f80ec 1 0x401f83fc 1 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_enet_1588_event1_out: IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT { + pinmux = <0x401f80ec 6 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_flexpwm1_pwmx2: IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX2 { + pinmux = <0x401f80ec 4 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio1_io12: IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_gpio6_io12: IOMUXC_GPIO_AD_B0_12_GPIO6_IO12 { + pinmux = <0x401f80ec 5 0x0 0 0x401f82dc>; + gpr = <0x400ac068 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpi2c4_scl: IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL { + pinmux = <0x401f80ec 0 0x401f84e4 1 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_lpuart1_tx: IOMUXC_GPIO_AD_B0_12_LPUART1_TX { + pinmux = <0x401f80ec 2 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_12_wdog2_b: IOMUXC_GPIO_AD_B0_12_WDOG2_B { + pinmux = <0x401f80ec 3 0x0 0 0x401f82dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_acmp1_in2: IOMUXC_GPIO_AD_B0_13_ACMP1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_adc1_in2: IOMUXC_GPIO_AD_B0_13_ADC1_IN2 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_enet_1588_event1_in: IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN { + pinmux = <0x401f80f0 6 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ewm_out_b: IOMUXC_GPIO_AD_B0_13_EWM_OUT_B { + pinmux = <0x401f80f0 3 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_flexpwm1_pwmx3: IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX3 { + pinmux = <0x401f80f0 4 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio1_io13: IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpio6_io13: IOMUXC_GPIO_AD_B0_13_GPIO6_IO13 { + pinmux = <0x401f80f0 5 0x0 0 0x401f82e0>; + gpr = <0x400ac068 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_gpt1_clk: IOMUXC_GPIO_AD_B0_13_GPT1_CLK { + pinmux = <0x401f80f0 1 0x401f8760 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpi2c4_sda: IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA { + pinmux = <0x401f80f0 0 0x401f84e8 1 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_lpuart1_rx: IOMUXC_GPIO_AD_B0_13_LPUART1_RX { + pinmux = <0x401f80f0 2 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_13_ref_24m_out: IOMUXC_GPIO_AD_B0_13_REF_24M_OUT { + pinmux = <0x401f80f0 7 0x0 0 0x401f82e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_acmp2_in2: IOMUXC_GPIO_AD_B0_14_ACMP2_IN2 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_adc1_in3: IOMUXC_GPIO_AD_B0_14_ADC1_IN3 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_csi_vsync: IOMUXC_GPIO_AD_B0_14_CSI_VSYNC { + pinmux = <0x401f80f4 4 0x401f8428 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_enet_1588_event0_out: IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT { + pinmux = <0x401f80f4 3 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan2_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX { + pinmux = <0x401f80f4 6 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_flexcan3_tx: IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX { + pinmux = <0x401f80f4 8 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio1_io14: IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_gpio6_io14: IOMUXC_GPIO_AD_B0_14_GPIO6_IO14 { + pinmux = <0x401f80f4 5 0x0 0 0x401f82e4>; + gpr = <0x400ac068 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_lpuart1_cts_b: IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B { + pinmux = <0x401f80f4 2 0x0 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_usb_otg2_oc: IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC { + pinmux = <0x401f80f4 0 0x401f85cc 0 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_14_xbar1_xbar_in24: IOMUXC_GPIO_AD_B0_14_XBAR1_XBAR_IN24 { + pinmux = <0x401f80f4 1 0x401f8640 1 0x401f82e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_acmp3_in2: IOMUXC_GPIO_AD_B0_15_ACMP3_IN2 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_adc1_in4: IOMUXC_GPIO_AD_B0_15_ADC1_IN4 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_csi_hsync: IOMUXC_GPIO_AD_B0_15_CSI_HSYNC { + pinmux = <0x401f80f8 4 0x401f8420 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_enet_1588_event0_in: IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN { + pinmux = <0x401f80f8 3 0x401f8444 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan2_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX { + pinmux = <0x401f80f8 6 0x401f8450 2 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_flexcan3_rx: IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX { + pinmux = <0x401f80f8 8 0x401f878c 1 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio1_io15: IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_gpio6_io15: IOMUXC_GPIO_AD_B0_15_GPIO6_IO15 { + pinmux = <0x401f80f8 5 0x0 0 0x401f82e8>; + gpr = <0x400ac068 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_lpuart1_rts_b: IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B { + pinmux = <0x401f80f8 2 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_usb_otg2_pwr: IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR { + pinmux = <0x401f80f8 0 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb: IOMUXC_GPIO_AD_B0_15_WDOG1_RST_B_DEB { + pinmux = <0x401f80f8 7 0x0 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b0_15_xbar1_xbar_in25: IOMUXC_GPIO_AD_B0_15_XBAR1_XBAR_IN25 { + pinmux = <0x401f80f8 1 0x401f8650 0 0x401f82e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_acmp4_in2: IOMUXC_GPIO_AD_B1_00_ACMP4_IN2 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc1_in5: IOMUXC_GPIO_AD_B1_00_ADC1_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_adc2_in5: IOMUXC_GPIO_AD_B1_00_ADC2_IN5 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_enet2_1588_event0_out: IOMUXC_GPIO_AD_B1_00_ENET2_1588_EVENT0_OUT { + pinmux = <0x401f80fc 8 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_flexio3_flexio00: IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 { + pinmux = <0x401f80fc 9 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio1_io16: IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_gpio6_io16: IOMUXC_GPIO_AD_B1_00_GPIO6_IO16 { + pinmux = <0x401f80fc 5 0x0 0 0x401f82ec>; + gpr = <0x400ac068 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_kpp_row7: IOMUXC_GPIO_AD_B1_00_KPP_ROW7 { + pinmux = <0x401f80fc 7 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpi2c1_scl: IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL { + pinmux = <0x401f80fc 3 0x401f84cc 1 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_lpuart2_cts_b: IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B { + pinmux = <0x401f80fc 2 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_qtimer3_timer0: IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 { + pinmux = <0x401f80fc 1 0x401f857c 1 0x401f82ec>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usb_otg2_id: IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID { + pinmux = <0x401f80fc 0 0x401f83f8 1 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_usdhc1_wp: IOMUXC_GPIO_AD_B1_00_USDHC1_WP { + pinmux = <0x401f80fc 6 0x401f85d8 2 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_00_wdog1_b: IOMUXC_GPIO_AD_B1_00_WDOG1_B { + pinmux = <0x401f80fc 4 0x0 0 0x401f82ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp1_in0: IOMUXC_GPIO_AD_B1_01_ACMP1_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp2_in0: IOMUXC_GPIO_AD_B1_01_ACMP2_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp3_in0: IOMUXC_GPIO_AD_B1_01_ACMP3_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_acmp4_in0: IOMUXC_GPIO_AD_B1_01_ACMP4_IN0 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc1_in6: IOMUXC_GPIO_AD_B1_01_ADC1_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_adc2_in6: IOMUXC_GPIO_AD_B1_01_ADC2_IN6 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_01_CCM_PMIC_RDY { + pinmux = <0x401f8100 4 0x401f83fc 2 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_enet2_1588_event0_in: IOMUXC_GPIO_AD_B1_01_ENET2_1588_EVENT0_IN { + pinmux = <0x401f8100 8 0x401f8724 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_flexio3_flexio01: IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 { + pinmux = <0x401f8100 9 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio1_io17: IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_gpio6_io17: IOMUXC_GPIO_AD_B1_01_GPIO6_IO17 { + pinmux = <0x401f8100 5 0x0 0 0x401f82f0>; + gpr = <0x400ac068 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_kpp_col7: IOMUXC_GPIO_AD_B1_01_KPP_COL7 { + pinmux = <0x401f8100 7 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpi2c1_sda: IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA { + pinmux = <0x401f8100 3 0x401f84d0 1 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_lpuart2_rts_b: IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B { + pinmux = <0x401f8100 2 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_qtimer3_timer1: IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 { + pinmux = <0x401f8100 1 0x401f8580 0 0x401f82f0>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usb_otg1_pwr: IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR { + pinmux = <0x401f8100 0 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_01_usdhc1_vselect: IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT { + pinmux = <0x401f8100 6 0x0 0 0x401f82f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_acmp1_in3: IOMUXC_GPIO_AD_B1_02_ACMP1_IN3 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc1_in7: IOMUXC_GPIO_AD_B1_02_ADC1_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_adc2_in7: IOMUXC_GPIO_AD_B1_02_ADC2_IN7 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_enet_1588_event2_out: IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT { + pinmux = <0x401f8104 4 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_flexio3_flexio02: IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 { + pinmux = <0x401f8104 9 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio1_io18: IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpio6_io18: IOMUXC_GPIO_AD_B1_02_GPIO6_IO18 { + pinmux = <0x401f8104 5 0x0 0 0x401f82f4>; + gpr = <0x400ac068 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_gpt2_clk: IOMUXC_GPIO_AD_B1_02_GPT2_CLK { + pinmux = <0x401f8104 8 0x401f876c 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_kpp_row6: IOMUXC_GPIO_AD_B1_02_KPP_ROW6 { + pinmux = <0x401f8104 7 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_lpuart2_tx: IOMUXC_GPIO_AD_B1_02_LPUART2_TX { + pinmux = <0x401f8104 2 0x401f8530 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_qtimer3_timer2: IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 { + pinmux = <0x401f8104 1 0x401f8584 1 0x401f82f4>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_spdif_out: IOMUXC_GPIO_AD_B1_02_SPDIF_OUT { + pinmux = <0x401f8104 3 0x0 0 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usb_otg1_id: IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID { + pinmux = <0x401f8104 0 0x401f83f4 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_02_usdhc1_cd_b: IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B { + pinmux = <0x401f8104 6 0x401f85d4 1 0x401f82f4>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_acmp2_in3: IOMUXC_GPIO_AD_B1_03_ACMP2_IN3 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc1_in8: IOMUXC_GPIO_AD_B1_03_ADC1_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_adc2_in8: IOMUXC_GPIO_AD_B1_03_ADC2_IN8 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_enet_1588_event2_in: IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN { + pinmux = <0x401f8108 4 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_flexio3_flexio03: IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 { + pinmux = <0x401f8108 9 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio1_io19: IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpio6_io19: IOMUXC_GPIO_AD_B1_03_GPIO6_IO19 { + pinmux = <0x401f8108 5 0x0 0 0x401f82f8>; + gpr = <0x400ac068 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_gpt2_capture1: IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 { + pinmux = <0x401f8108 8 0x401f8764 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_kpp_col6: IOMUXC_GPIO_AD_B1_03_KPP_COL6 { + pinmux = <0x401f8108 7 0x0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_lpuart2_rx: IOMUXC_GPIO_AD_B1_03_LPUART2_RX { + pinmux = <0x401f8108 2 0x401f852c 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_qtimer3_timer3: IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 { + pinmux = <0x401f8108 1 0x401f8588 1 0x401f82f8>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_spdif_in: IOMUXC_GPIO_AD_B1_03_SPDIF_IN { + pinmux = <0x401f8108 3 0x401f85c8 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usb_otg1_oc: IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC { + pinmux = <0x401f8108 0 0x401f85d0 1 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_03_usdhc2_cd_b: IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B { + pinmux = <0x401f8108 6 0x401f85e0 0 0x401f82f8>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_acmp3_in3: IOMUXC_GPIO_AD_B1_04_ACMP3_IN3 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc1_in9: IOMUXC_GPIO_AD_B1_04_ADC1_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_adc2_in9: IOMUXC_GPIO_AD_B1_04_ADC2_IN9 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_csi_pixclk: IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK { + pinmux = <0x401f810c 4 0x401f8424 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_enet_mdc: IOMUXC_GPIO_AD_B1_04_ENET_MDC { + pinmux = <0x401f810c 1 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexio3_flexio04: IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 { + pinmux = <0x401f810c 9 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_flexspi_b_data3: IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 { + pinmux = <0x401f810c 0 0x401f84c4 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio1_io20: IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpio6_io20: IOMUXC_GPIO_AD_B1_04_GPIO6_IO20 { + pinmux = <0x401f810c 5 0x0 0 0x401f82fc>; + gpr = <0x400ac068 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_gpt2_capture2: IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 { + pinmux = <0x401f810c 8 0x401f8768 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_kpp_row5: IOMUXC_GPIO_AD_B1_04_KPP_ROW5 { + pinmux = <0x401f810c 7 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_lpuart3_cts_b: IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B { + pinmux = <0x401f810c 2 0x401f8534 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_spdif_sr_clk: IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK { + pinmux = <0x401f810c 3 0x0 0 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_04_usdhc2_data0: IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 { + pinmux = <0x401f810c 6 0x401f85e8 1 0x401f82fc>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_acmp4_in3: IOMUXC_GPIO_AD_B1_05_ACMP4_IN3 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc1_in10: IOMUXC_GPIO_AD_B1_05_ADC1_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_adc2_in10: IOMUXC_GPIO_AD_B1_05_ADC2_IN10 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_csi_mclk: IOMUXC_GPIO_AD_B1_05_CSI_MCLK { + pinmux = <0x401f8110 4 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_enet_mdio: IOMUXC_GPIO_AD_B1_05_ENET_MDIO { + pinmux = <0x401f8110 1 0x401f8430 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexio3_flexio05: IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 { + pinmux = <0x401f8110 9 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_flexspi_b_data2: IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 { + pinmux = <0x401f8110 0 0x401f84c0 1 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio1_io21: IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpio6_io21: IOMUXC_GPIO_AD_B1_05_GPIO6_IO21 { + pinmux = <0x401f8110 5 0x0 0 0x401f8300>; + gpr = <0x400ac068 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_gpt2_compare1: IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 { + pinmux = <0x401f8110 8 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_kpp_col5: IOMUXC_GPIO_AD_B1_05_KPP_COL5 { + pinmux = <0x401f8110 7 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_lpuart3_rts_b: IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B { + pinmux = <0x401f8110 2 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_spdif_out: IOMUXC_GPIO_AD_B1_05_SPDIF_OUT { + pinmux = <0x401f8110 3 0x0 0 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_05_usdhc2_data1: IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 { + pinmux = <0x401f8110 6 0x401f85ec 1 0x401f8300>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp1_in1: IOMUXC_GPIO_AD_B1_06_ACMP1_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp2_in1: IOMUXC_GPIO_AD_B1_06_ACMP2_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp3_in1: IOMUXC_GPIO_AD_B1_06_ACMP3_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_acmp4_in1: IOMUXC_GPIO_AD_B1_06_ACMP4_IN1 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc1_in11: IOMUXC_GPIO_AD_B1_06_ADC1_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_adc2_in11: IOMUXC_GPIO_AD_B1_06_ADC2_IN11 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_csi_vsync: IOMUXC_GPIO_AD_B1_06_CSI_VSYNC { + pinmux = <0x401f8114 4 0x401f8428 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexio3_flexio06: IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 { + pinmux = <0x401f8114 9 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_flexspi_b_data1: IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 { + pinmux = <0x401f8114 0 0x401f84bc 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio1_io22: IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpio6_io22: IOMUXC_GPIO_AD_B1_06_GPIO6_IO22 { + pinmux = <0x401f8114 5 0x0 0 0x401f8304>; + gpr = <0x400ac068 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_gpt2_compare2: IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 { + pinmux = <0x401f8114 8 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_kpp_row4: IOMUXC_GPIO_AD_B1_06_KPP_ROW4 { + pinmux = <0x401f8114 7 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpi2c3_sda: IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA { + pinmux = <0x401f8114 1 0x401f84e0 2 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_lpuart3_tx: IOMUXC_GPIO_AD_B1_06_LPUART3_TX { + pinmux = <0x401f8114 2 0x401f853c 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_spdif_lock: IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK { + pinmux = <0x401f8114 3 0x0 0 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_06_usdhc2_data2: IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 { + pinmux = <0x401f8114 6 0x401f85f0 1 0x401f8304>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_acmp1_in5: IOMUXC_GPIO_AD_B1_07_ACMP1_IN5 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc1_in12: IOMUXC_GPIO_AD_B1_07_ADC1_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_adc2_in12: IOMUXC_GPIO_AD_B1_07_ADC2_IN12 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_csi_hsync: IOMUXC_GPIO_AD_B1_07_CSI_HSYNC { + pinmux = <0x401f8118 4 0x401f8420 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexio3_flexio07: IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 { + pinmux = <0x401f8118 9 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_flexspi_b_data0: IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 { + pinmux = <0x401f8118 0 0x401f84b8 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio1_io23: IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpio6_io23: IOMUXC_GPIO_AD_B1_07_GPIO6_IO23 { + pinmux = <0x401f8118 5 0x0 0 0x401f8308>; + gpr = <0x400ac068 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_gpt2_compare3: IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 { + pinmux = <0x401f8118 8 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_kpp_col4: IOMUXC_GPIO_AD_B1_07_KPP_COL4 { + pinmux = <0x401f8118 7 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpi2c3_scl: IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL { + pinmux = <0x401f8118 1 0x401f84dc 2 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_lpuart3_rx: IOMUXC_GPIO_AD_B1_07_LPUART3_RX { + pinmux = <0x401f8118 2 0x401f8538 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_spdif_ext_clk: IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK { + pinmux = <0x401f8118 3 0x0 0 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_07_usdhc2_data3: IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 { + pinmux = <0x401f8118 6 0x401f85f4 1 0x401f8308>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_acmp2_in5: IOMUXC_GPIO_AD_B1_08_ACMP2_IN5 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc1_in13: IOMUXC_GPIO_AD_B1_08_ADC1_IN13 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_adc2_in13: IOMUXC_GPIO_AD_B1_08_ADC2_IN13 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_ccm_pmic_rdy: IOMUXC_GPIO_AD_B1_08_CCM_PMIC_RDY { + pinmux = <0x401f811c 3 0x401f83fc 3 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_csi_data09: IOMUXC_GPIO_AD_B1_08_CSI_DATA09 { + pinmux = <0x401f811c 4 0x401f841c 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexcan1_tx: IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX { + pinmux = <0x401f811c 2 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexio3_flexio08: IOMUXC_GPIO_AD_B1_08_FLEXIO3_FLEXIO08 { + pinmux = <0x401f811c 9 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexpwm4_pwma0: IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA0 { + pinmux = <0x401f811c 1 0x401f8494 1 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_flexspi_a_ss1_b: IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B { + pinmux = <0x401f811c 0 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio1_io24: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + gpr = <0x400ac068 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_gpio6_io24: IOMUXC_GPIO_AD_B1_08_GPIO6_IO24 { + pinmux = <0x401f811c 5 0x0 0 0x401f830c>; + gpr = <0x400ac068 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_kpp_row3: IOMUXC_GPIO_AD_B1_08_KPP_ROW3 { + pinmux = <0x401f811c 7 0x0 0 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_08_usdhc2_cmd: IOMUXC_GPIO_AD_B1_08_USDHC2_CMD { + pinmux = <0x401f811c 6 0x401f85e4 1 0x401f830c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_acmp3_in5: IOMUXC_GPIO_AD_B1_09_ACMP3_IN5 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc1_in14: IOMUXC_GPIO_AD_B1_09_ADC1_IN14 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_adc2_in14: IOMUXC_GPIO_AD_B1_09_ADC2_IN14 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_csi_data08: IOMUXC_GPIO_AD_B1_09_CSI_DATA08 { + pinmux = <0x401f8120 4 0x401f8418 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexcan1_rx: IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX { + pinmux = <0x401f8120 2 0x401f844c 2 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexio3_flexio09: IOMUXC_GPIO_AD_B1_09_FLEXIO3_FLEXIO09 { + pinmux = <0x401f8120 9 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexpwm4_pwma1: IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA1 { + pinmux = <0x401f8120 1 0x401f8498 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_flexspi_a_dqs: IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS { + pinmux = <0x401f8120 0 0x401f84a4 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio1_io25: IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + gpr = <0x400ac068 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_gpio6_io25: IOMUXC_GPIO_AD_B1_09_GPIO6_IO25 { + pinmux = <0x401f8120 5 0x0 0 0x401f8310>; + gpr = <0x400ac068 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_kpp_col3: IOMUXC_GPIO_AD_B1_09_KPP_COL3 { + pinmux = <0x401f8120 7 0x0 0 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_sai1_mclk: IOMUXC_GPIO_AD_B1_09_SAI1_MCLK { + pinmux = <0x401f8120 3 0x401f858c 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_09_usdhc2_clk: IOMUXC_GPIO_AD_B1_09_USDHC2_CLK { + pinmux = <0x401f8120 6 0x401f85dc 1 0x401f8310>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_acmp4_in5: IOMUXC_GPIO_AD_B1_10_ACMP4_IN5 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc1_in15: IOMUXC_GPIO_AD_B1_10_ADC1_IN15 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_adc2_in15: IOMUXC_GPIO_AD_B1_10_ADC2_IN15 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_csi_data07: IOMUXC_GPIO_AD_B1_10_CSI_DATA07 { + pinmux = <0x401f8124 4 0x401f8414 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_enet2_1588_event1_out: IOMUXC_GPIO_AD_B1_10_ENET2_1588_EVENT1_OUT { + pinmux = <0x401f8124 8 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexio3_flexio10: IOMUXC_GPIO_AD_B1_10_FLEXIO3_FLEXIO10 { + pinmux = <0x401f8124 9 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_flexspi_a_data3: IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 { + pinmux = <0x401f8124 0 0x401f84b4 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio1_io26: IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + gpr = <0x400ac068 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_gpio6_io26: IOMUXC_GPIO_AD_B1_10_GPIO6_IO26 { + pinmux = <0x401f8124 5 0x0 0 0x401f8314>; + gpr = <0x400ac068 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_kpp_row2: IOMUXC_GPIO_AD_B1_10_KPP_ROW2 { + pinmux = <0x401f8124 7 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_lpuart8_tx: IOMUXC_GPIO_AD_B1_10_LPUART8_TX { + pinmux = <0x401f8124 2 0x401f8564 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_sai1_rx_sync: IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC { + pinmux = <0x401f8124 3 0x401f85a4 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_usdhc2_wp: IOMUXC_GPIO_AD_B1_10_USDHC2_WP { + pinmux = <0x401f8124 6 0x401f8608 1 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_10_wdog1_b: IOMUXC_GPIO_AD_B1_10_WDOG1_B { + pinmux = <0x401f8124 1 0x0 0 0x401f8314>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_acmp1_in6: IOMUXC_GPIO_AD_B1_11_ACMP1_IN6 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc1_in0: IOMUXC_GPIO_AD_B1_11_ADC1_IN0 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_adc2_in0: IOMUXC_GPIO_AD_B1_11_ADC2_IN0 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_csi_data06: IOMUXC_GPIO_AD_B1_11_CSI_DATA06 { + pinmux = <0x401f8128 4 0x401f8410 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_enet2_1588_event1_in: IOMUXC_GPIO_AD_B1_11_ENET2_1588_EVENT1_IN { + pinmux = <0x401f8128 8 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_ewm_out_b: IOMUXC_GPIO_AD_B1_11_EWM_OUT_B { + pinmux = <0x401f8128 1 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexio3_flexio11: IOMUXC_GPIO_AD_B1_11_FLEXIO3_FLEXIO11 { + pinmux = <0x401f8128 9 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_flexspi_a_data2: IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 { + pinmux = <0x401f8128 0 0x401f84b0 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio1_io27: IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + gpr = <0x400ac068 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_gpio6_io27: IOMUXC_GPIO_AD_B1_11_GPIO6_IO27 { + pinmux = <0x401f8128 5 0x0 0 0x401f8318>; + gpr = <0x400ac068 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_kpp_col2: IOMUXC_GPIO_AD_B1_11_KPP_COL2 { + pinmux = <0x401f8128 7 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_lpuart8_rx: IOMUXC_GPIO_AD_B1_11_LPUART8_RX { + pinmux = <0x401f8128 2 0x401f8560 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_sai1_rx_bclk: IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK { + pinmux = <0x401f8128 3 0x401f8590 1 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_11_usdhc2_reset_b: IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B { + pinmux = <0x401f8128 6 0x0 0 0x401f8318>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp1_out: IOMUXC_GPIO_AD_B1_12_ACMP1_OUT { + pinmux = <0x401f812c 1 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_acmp2_in6: IOMUXC_GPIO_AD_B1_12_ACMP2_IN6 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_adc2_in1: IOMUXC_GPIO_AD_B1_12_ADC2_IN1 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_csi_data05: IOMUXC_GPIO_AD_B1_12_CSI_DATA05 { + pinmux = <0x401f812c 4 0x401f840c 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_enet2_1588_event2_out: IOMUXC_GPIO_AD_B1_12_ENET2_1588_EVENT2_OUT { + pinmux = <0x401f812c 8 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexio3_flexio12: IOMUXC_GPIO_AD_B1_12_FLEXIO3_FLEXIO12 { + pinmux = <0x401f812c 9 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_flexspi_a_data1: IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 { + pinmux = <0x401f812c 0 0x401f84ac 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio1_io28: IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + gpr = <0x400ac068 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_gpio6_io28: IOMUXC_GPIO_AD_B1_12_GPIO6_IO28 { + pinmux = <0x401f812c 5 0x0 0 0x401f831c>; + gpr = <0x400ac068 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_kpp_row1: IOMUXC_GPIO_AD_B1_12_KPP_ROW1 { + pinmux = <0x401f812c 7 0x0 0 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_lpspi3_pcs0: IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 { + pinmux = <0x401f812c 2 0x401f850c 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_sai1_rx_data0: IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA0 { + pinmux = <0x401f812c 3 0x401f8594 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_12_usdhc2_data4: IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 { + pinmux = <0x401f812c 6 0x401f85f8 1 0x401f831c>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp2_out: IOMUXC_GPIO_AD_B1_13_ACMP2_OUT { + pinmux = <0x401f8130 1 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_acmp3_in6: IOMUXC_GPIO_AD_B1_13_ACMP3_IN6 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_adc2_in2: IOMUXC_GPIO_AD_B1_13_ADC2_IN2 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_csi_data04: IOMUXC_GPIO_AD_B1_13_CSI_DATA04 { + pinmux = <0x401f8130 4 0x401f8408 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_enet2_1588_event2_in: IOMUXC_GPIO_AD_B1_13_ENET2_1588_EVENT2_IN { + pinmux = <0x401f8130 8 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexio3_flexio13: IOMUXC_GPIO_AD_B1_13_FLEXIO3_FLEXIO13 { + pinmux = <0x401f8130 9 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_flexspi_a_data0: IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 { + pinmux = <0x401f8130 0 0x401f84a8 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio1_io29: IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + gpr = <0x400ac068 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_gpio6_io29: IOMUXC_GPIO_AD_B1_13_GPIO6_IO29 { + pinmux = <0x401f8130 5 0x0 0 0x401f8320>; + gpr = <0x400ac068 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_kpp_col1: IOMUXC_GPIO_AD_B1_13_KPP_COL1 { + pinmux = <0x401f8130 7 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_lpspi3_sdi: IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI { + pinmux = <0x401f8130 2 0x401f8514 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_sai1_tx_data0: IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA0 { + pinmux = <0x401f8130 3 0x0 0 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_13_usdhc2_data5: IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 { + pinmux = <0x401f8130 6 0x401f85fc 1 0x401f8320>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp3_out: IOMUXC_GPIO_AD_B1_14_ACMP3_OUT { + pinmux = <0x401f8134 1 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_acmp4_in6: IOMUXC_GPIO_AD_B1_14_ACMP4_IN6 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_adc2_in3: IOMUXC_GPIO_AD_B1_14_ADC2_IN3 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_csi_data03: IOMUXC_GPIO_AD_B1_14_CSI_DATA03 { + pinmux = <0x401f8134 4 0x401f8404 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_enet2_1588_event3_out: IOMUXC_GPIO_AD_B1_14_ENET2_1588_EVENT3_OUT { + pinmux = <0x401f8134 8 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexio3_flexio14: IOMUXC_GPIO_AD_B1_14_FLEXIO3_FLEXIO14 { + pinmux = <0x401f8134 9 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_flexspi_a_sclk: IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK { + pinmux = <0x401f8134 0 0x401f84c8 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio1_io30: IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + gpr = <0x400ac068 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_gpio6_io30: IOMUXC_GPIO_AD_B1_14_GPIO6_IO30 { + pinmux = <0x401f8134 5 0x0 0 0x401f8324>; + gpr = <0x400ac068 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_kpp_row0: IOMUXC_GPIO_AD_B1_14_KPP_ROW0 { + pinmux = <0x401f8134 7 0x0 0 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_lpspi3_sdo: IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO { + pinmux = <0x401f8134 2 0x401f8518 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_sai1_tx_bclk: IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK { + pinmux = <0x401f8134 3 0x401f85a8 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_14_usdhc2_data6: IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 { + pinmux = <0x401f8134 6 0x401f8600 1 0x401f8324>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_acmp4_out: IOMUXC_GPIO_AD_B1_15_ACMP4_OUT { + pinmux = <0x401f8138 1 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_adc2_in4: IOMUXC_GPIO_AD_B1_15_ADC2_IN4 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_csi_data02: IOMUXC_GPIO_AD_B1_15_CSI_DATA02 { + pinmux = <0x401f8138 4 0x401f8400 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_enet2_1588_event3_in: IOMUXC_GPIO_AD_B1_15_ENET2_1588_EVENT3_IN { + pinmux = <0x401f8138 8 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexio3_flexio15: IOMUXC_GPIO_AD_B1_15_FLEXIO3_FLEXIO15 { + pinmux = <0x401f8138 9 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_flexspi_a_ss0_b: IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B { + pinmux = <0x401f8138 0 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio1_io31: IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + gpr = <0x400ac068 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_gpio6_io31: IOMUXC_GPIO_AD_B1_15_GPIO6_IO31 { + pinmux = <0x401f8138 5 0x0 0 0x401f8328>; + gpr = <0x400ac068 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_kpp_col0: IOMUXC_GPIO_AD_B1_15_KPP_COL0 { + pinmux = <0x401f8138 7 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_lpspi3_sck: IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK { + pinmux = <0x401f8138 2 0x0 0 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_sai1_tx_sync: IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC { + pinmux = <0x401f8138 3 0x401f85ac 1 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_b1_15_usdhc2_data7: IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 { + pinmux = <0x401f8138 6 0x401f8604 1 0x401f8328>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_enet2_mdc: IOMUXC_GPIO_B0_00_ENET2_MDC { + pinmux = <0x401f813c 8 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_flexio2_flexio00: IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 { + pinmux = <0x401f813c 4 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio2_io00: IOMUXC_GPIO_B0_00_GPIO2_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_gpio7_io00: IOMUXC_GPIO_B0_00_GPIO7_IO00 { + pinmux = <0x401f813c 5 0x0 0 0x401f832c>; + gpr = <0x400ac06c 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lcdif_clk: IOMUXC_GPIO_B0_00_LCDIF_CLK { + pinmux = <0x401f813c 0 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_lpspi4_pcs0: IOMUXC_GPIO_B0_00_LPSPI4_PCS0 { + pinmux = <0x401f813c 3 0x401f851c 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_mqs_right: IOMUXC_GPIO_B0_00_MQS_RIGHT { + pinmux = <0x401f813c 2 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_qtimer1_timer0: IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 { + pinmux = <0x401f813c 1 0x0 0 0x401f832c>; + gpr = <0x400ac018 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_00_semc_csx1: IOMUXC_GPIO_B0_00_SEMC_CSX1 { + pinmux = <0x401f813c 6 0x0 0 0x401f832c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_enet2_mdio: IOMUXC_GPIO_B0_01_ENET2_MDIO { + pinmux = <0x401f8140 8 0x401f8710 1 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_flexio2_flexio01: IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 { + pinmux = <0x401f8140 4 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio2_io01: IOMUXC_GPIO_B0_01_GPIO2_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_gpio7_io01: IOMUXC_GPIO_B0_01_GPIO7_IO01 { + pinmux = <0x401f8140 5 0x0 0 0x401f8330>; + gpr = <0x400ac06c 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lcdif_enable: IOMUXC_GPIO_B0_01_LCDIF_ENABLE { + pinmux = <0x401f8140 0 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_lpspi4_sdi: IOMUXC_GPIO_B0_01_LPSPI4_SDI { + pinmux = <0x401f8140 3 0x401f8524 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_mqs_left: IOMUXC_GPIO_B0_01_MQS_LEFT { + pinmux = <0x401f8140 2 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_qtimer1_timer1: IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 { + pinmux = <0x401f8140 1 0x0 0 0x401f8330>; + gpr = <0x400ac018 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_01_semc_csx2: IOMUXC_GPIO_B0_01_SEMC_CSX2 { + pinmux = <0x401f8140 6 0x0 0 0x401f8330>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_enet2_1588_event0_out: IOMUXC_GPIO_B0_02_ENET2_1588_EVENT0_OUT { + pinmux = <0x401f8144 8 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexcan1_tx: IOMUXC_GPIO_B0_02_FLEXCAN1_TX { + pinmux = <0x401f8144 2 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_flexio2_flexio02: IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 { + pinmux = <0x401f8144 4 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio2_io02: IOMUXC_GPIO_B0_02_GPIO2_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_gpio7_io02: IOMUXC_GPIO_B0_02_GPIO7_IO02 { + pinmux = <0x401f8144 5 0x0 0 0x401f8334>; + gpr = <0x400ac06c 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lcdif_hsync: IOMUXC_GPIO_B0_02_LCDIF_HSYNC { + pinmux = <0x401f8144 0 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_lpspi4_sdo: IOMUXC_GPIO_B0_02_LPSPI4_SDO { + pinmux = <0x401f8144 3 0x401f8528 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_qtimer1_timer2: IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 { + pinmux = <0x401f8144 1 0x0 0 0x401f8334>; + gpr = <0x400ac018 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_02_semc_csx3: IOMUXC_GPIO_B0_02_SEMC_CSX3 { + pinmux = <0x401f8144 6 0x0 0 0x401f8334>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_enet2_1588_event0_in: IOMUXC_GPIO_B0_03_ENET2_1588_EVENT0_IN { + pinmux = <0x401f8148 8 0x401f8724 1 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexcan1_rx: IOMUXC_GPIO_B0_03_FLEXCAN1_RX { + pinmux = <0x401f8148 2 0x401f844c 3 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_flexio2_flexio03: IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 { + pinmux = <0x401f8148 4 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio2_io03: IOMUXC_GPIO_B0_03_GPIO2_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_gpio7_io03: IOMUXC_GPIO_B0_03_GPIO7_IO03 { + pinmux = <0x401f8148 5 0x0 0 0x401f8338>; + gpr = <0x400ac06c 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lcdif_vsync: IOMUXC_GPIO_B0_03_LCDIF_VSYNC { + pinmux = <0x401f8148 0 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_lpspi4_sck: IOMUXC_GPIO_B0_03_LPSPI4_SCK { + pinmux = <0x401f8148 3 0x401f8520 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_qtimer2_timer0: IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 { + pinmux = <0x401f8148 1 0x401f856c 1 0x401f8338>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_03_wdog2_rst_b_deb: IOMUXC_GPIO_B0_03_WDOG2_RST_B_DEB { + pinmux = <0x401f8148 6 0x0 0 0x401f8338>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_arm_trace0: IOMUXC_GPIO_B0_04_ARM_TRACE0 { + pinmux = <0x401f814c 3 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_enet2_tx_data3: IOMUXC_GPIO_B0_04_ENET2_TX_DATA3 { + pinmux = <0x401f814c 8 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_flexio2_flexio04: IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 { + pinmux = <0x401f814c 4 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio2_io04: IOMUXC_GPIO_B0_04_GPIO2_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_gpio7_io04: IOMUXC_GPIO_B0_04_GPIO7_IO04 { + pinmux = <0x401f814c 5 0x0 0 0x401f833c>; + gpr = <0x400ac06c 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lcdif_data00: IOMUXC_GPIO_B0_04_LCDIF_DATA00 { + pinmux = <0x401f814c 0 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_lpi2c2_scl: IOMUXC_GPIO_B0_04_LPI2C2_SCL { + pinmux = <0x401f814c 2 0x401f84d4 1 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_qtimer2_timer1: IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 { + pinmux = <0x401f814c 1 0x401f8570 1 0x401f833c>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_04_src_bt_cfg0: IOMUXC_GPIO_B0_04_SRC_BT_CFG0 { + pinmux = <0x401f814c 6 0x0 0 0x401f833c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_arm_trace1: IOMUXC_GPIO_B0_05_ARM_TRACE1 { + pinmux = <0x401f8150 3 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_enet2_tx_data2: IOMUXC_GPIO_B0_05_ENET2_TX_DATA2 { + pinmux = <0x401f8150 8 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_flexio2_flexio05: IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 { + pinmux = <0x401f8150 4 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio2_io05: IOMUXC_GPIO_B0_05_GPIO2_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_gpio7_io05: IOMUXC_GPIO_B0_05_GPIO7_IO05 { + pinmux = <0x401f8150 5 0x0 0 0x401f8340>; + gpr = <0x400ac06c 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lcdif_data01: IOMUXC_GPIO_B0_05_LCDIF_DATA01 { + pinmux = <0x401f8150 0 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_lpi2c2_sda: IOMUXC_GPIO_B0_05_LPI2C2_SDA { + pinmux = <0x401f8150 2 0x401f84d8 1 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_qtimer2_timer2: IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 { + pinmux = <0x401f8150 1 0x401f8574 1 0x401f8340>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_05_src_bt_cfg1: IOMUXC_GPIO_B0_05_SRC_BT_CFG1 { + pinmux = <0x401f8150 6 0x0 0 0x401f8340>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_arm_trace2: IOMUXC_GPIO_B0_06_ARM_TRACE2 { + pinmux = <0x401f8154 3 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_enet2_rx_clk: IOMUXC_GPIO_B0_06_ENET2_RX_CLK { + pinmux = <0x401f8154 8 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexio2_flexio06: IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 { + pinmux = <0x401f8154 4 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_flexpwm2_pwma0: IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f8154 2 0x401f8478 1 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio2_io06: IOMUXC_GPIO_B0_06_GPIO2_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_gpio7_io06: IOMUXC_GPIO_B0_06_GPIO7_IO06 { + pinmux = <0x401f8154 5 0x0 0 0x401f8344>; + gpr = <0x400ac06c 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_lcdif_data02: IOMUXC_GPIO_B0_06_LCDIF_DATA02 { + pinmux = <0x401f8154 0 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_qtimer3_timer0: IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 { + pinmux = <0x401f8154 1 0x401f857c 2 0x401f8344>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_06_src_bt_cfg2: IOMUXC_GPIO_B0_06_SRC_BT_CFG2 { + pinmux = <0x401f8154 6 0x0 0 0x401f8344>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_arm_trace3: IOMUXC_GPIO_B0_07_ARM_TRACE3 { + pinmux = <0x401f8158 3 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_enet2_tx_er: IOMUXC_GPIO_B0_07_ENET2_TX_ER { + pinmux = <0x401f8158 8 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexio2_flexio07: IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 { + pinmux = <0x401f8158 4 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_flexpwm2_pwmb0: IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8158 2 0x401f8488 1 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio2_io07: IOMUXC_GPIO_B0_07_GPIO2_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_gpio7_io07: IOMUXC_GPIO_B0_07_GPIO7_IO07 { + pinmux = <0x401f8158 5 0x0 0 0x401f8348>; + gpr = <0x400ac06c 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_lcdif_data03: IOMUXC_GPIO_B0_07_LCDIF_DATA03 { + pinmux = <0x401f8158 0 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_qtimer3_timer1: IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 { + pinmux = <0x401f8158 1 0x401f8580 2 0x401f8348>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_07_src_bt_cfg3: IOMUXC_GPIO_B0_07_SRC_BT_CFG3 { + pinmux = <0x401f8158 6 0x0 0 0x401f8348>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_enet2_rx_data3: IOMUXC_GPIO_B0_08_ENET2_RX_DATA3 { + pinmux = <0x401f815c 8 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexio2_flexio08: IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 { + pinmux = <0x401f815c 4 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_flexpwm2_pwma1: IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f815c 2 0x401f847c 1 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio2_io08: IOMUXC_GPIO_B0_08_GPIO2_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_gpio7_io08: IOMUXC_GPIO_B0_08_GPIO7_IO08 { + pinmux = <0x401f815c 5 0x0 0 0x401f834c>; + gpr = <0x400ac06c 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lcdif_data04: IOMUXC_GPIO_B0_08_LCDIF_DATA04 { + pinmux = <0x401f815c 0 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_lpuart3_tx: IOMUXC_GPIO_B0_08_LPUART3_TX { + pinmux = <0x401f815c 3 0x401f853c 2 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_qtimer3_timer2: IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 { + pinmux = <0x401f815c 1 0x401f8584 2 0x401f834c>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_08_src_bt_cfg4: IOMUXC_GPIO_B0_08_SRC_BT_CFG4 { + pinmux = <0x401f815c 6 0x0 0 0x401f834c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_enet2_rx_data2: IOMUXC_GPIO_B0_09_ENET2_RX_DATA2 { + pinmux = <0x401f8160 8 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexio2_flexio09: IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 { + pinmux = <0x401f8160 4 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_flexpwm2_pwmb1: IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8160 2 0x401f848c 1 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio2_io09: IOMUXC_GPIO_B0_09_GPIO2_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_gpio7_io09: IOMUXC_GPIO_B0_09_GPIO7_IO09 { + pinmux = <0x401f8160 5 0x0 0 0x401f8350>; + gpr = <0x400ac06c 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lcdif_data05: IOMUXC_GPIO_B0_09_LCDIF_DATA05 { + pinmux = <0x401f8160 0 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_lpuart3_rx: IOMUXC_GPIO_B0_09_LPUART3_RX { + pinmux = <0x401f8160 3 0x401f8538 2 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_qtimer4_timer0: IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 { + pinmux = <0x401f8160 1 0x0 0 0x401f8350>; + gpr = <0x400ac018 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_09_src_bt_cfg5: IOMUXC_GPIO_B0_09_SRC_BT_CFG5 { + pinmux = <0x401f8160 6 0x0 0 0x401f8350>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_enet2_crs: IOMUXC_GPIO_B0_10_ENET2_CRS { + pinmux = <0x401f8164 8 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexio2_flexio10: IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 { + pinmux = <0x401f8164 4 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_flexpwm2_pwma2: IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f8164 2 0x401f8480 1 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio2_io10: IOMUXC_GPIO_B0_10_GPIO2_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_gpio7_io10: IOMUXC_GPIO_B0_10_GPIO7_IO10 { + pinmux = <0x401f8164 5 0x0 0 0x401f8354>; + gpr = <0x400ac06c 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_lcdif_data06: IOMUXC_GPIO_B0_10_LCDIF_DATA06 { + pinmux = <0x401f8164 0 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_qtimer4_timer1: IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 { + pinmux = <0x401f8164 1 0x0 0 0x401f8354>; + gpr = <0x400ac018 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_sai1_tx_data3: IOMUXC_GPIO_B0_10_SAI1_TX_DATA3 { + pinmux = <0x401f8164 3 0x401f8598 1 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_10_src_bt_cfg6: IOMUXC_GPIO_B0_10_SRC_BT_CFG6 { + pinmux = <0x401f8164 6 0x0 0 0x401f8354>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_enet2_col: IOMUXC_GPIO_B0_11_ENET2_COL { + pinmux = <0x401f8168 8 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexio2_flexio11: IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 { + pinmux = <0x401f8168 4 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_flexpwm2_pwmb2: IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8168 2 0x401f8490 1 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio2_io11: IOMUXC_GPIO_B0_11_GPIO2_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_gpio7_io11: IOMUXC_GPIO_B0_11_GPIO7_IO11 { + pinmux = <0x401f8168 5 0x0 0 0x401f8358>; + gpr = <0x400ac06c 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_lcdif_data07: IOMUXC_GPIO_B0_11_LCDIF_DATA07 { + pinmux = <0x401f8168 0 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_qtimer4_timer2: IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 { + pinmux = <0x401f8168 1 0x0 0 0x401f8358>; + gpr = <0x400ac018 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_sai1_tx_data2: IOMUXC_GPIO_B0_11_SAI1_TX_DATA2 { + pinmux = <0x401f8168 3 0x401f859c 1 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_11_src_bt_cfg7: IOMUXC_GPIO_B0_11_SRC_BT_CFG7 { + pinmux = <0x401f8168 6 0x0 0 0x401f8358>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_arm_trace_clk: IOMUXC_GPIO_B0_12_ARM_TRACE_CLK { + pinmux = <0x401f816c 2 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_enet2_tx_data0: IOMUXC_GPIO_B0_12_ENET2_TX_DATA0 { + pinmux = <0x401f816c 8 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_flexio2_flexio12: IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 { + pinmux = <0x401f816c 4 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio2_io12: IOMUXC_GPIO_B0_12_GPIO2_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_gpio7_io12: IOMUXC_GPIO_B0_12_GPIO7_IO12 { + pinmux = <0x401f816c 5 0x0 0 0x401f835c>; + gpr = <0x400ac06c 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_lcdif_data08: IOMUXC_GPIO_B0_12_LCDIF_DATA08 { + pinmux = <0x401f816c 0 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_sai1_tx_data1: IOMUXC_GPIO_B0_12_SAI1_TX_DATA1 { + pinmux = <0x401f816c 3 0x401f85a0 1 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_src_bt_cfg8: IOMUXC_GPIO_B0_12_SRC_BT_CFG8 { + pinmux = <0x401f816c 6 0x0 0 0x401f835c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_in10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_IN10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_12_xbar1_xbar_inout10: IOMUXC_GPIO_B0_12_XBAR1_XBAR_INOUT10 { + pinmux = <0x401f816c 1 0x0 0 0x401f835c>; + gpr = <0x400ac018 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_arm_trace_swo: IOMUXC_GPIO_B0_13_ARM_TRACE_SWO { + pinmux = <0x401f8170 2 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_enet2_tx_data1: IOMUXC_GPIO_B0_13_ENET2_TX_DATA1 { + pinmux = <0x401f8170 8 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_flexio2_flexio13: IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 { + pinmux = <0x401f8170 4 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio2_io13: IOMUXC_GPIO_B0_13_GPIO2_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_gpio7_io13: IOMUXC_GPIO_B0_13_GPIO7_IO13 { + pinmux = <0x401f8170 5 0x0 0 0x401f8360>; + gpr = <0x400ac06c 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_lcdif_data09: IOMUXC_GPIO_B0_13_LCDIF_DATA09 { + pinmux = <0x401f8170 0 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_sai1_mclk: IOMUXC_GPIO_B0_13_SAI1_MCLK { + pinmux = <0x401f8170 3 0x401f858c 2 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_src_bt_cfg9: IOMUXC_GPIO_B0_13_SRC_BT_CFG9 { + pinmux = <0x401f8170 6 0x0 0 0x401f8360>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_in11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_IN11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_13_xbar1_xbar_inout11: IOMUXC_GPIO_B0_13_XBAR1_XBAR_INOUT11 { + pinmux = <0x401f8170 1 0x0 0 0x401f8360>; + gpr = <0x400ac018 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_arm_txev: IOMUXC_GPIO_B0_14_ARM_TXEV { + pinmux = <0x401f8174 2 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_enet2_tx_en: IOMUXC_GPIO_B0_14_ENET2_TX_EN { + pinmux = <0x401f8174 8 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_flexio2_flexio14: IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 { + pinmux = <0x401f8174 4 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio2_io14: IOMUXC_GPIO_B0_14_GPIO2_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_gpio7_io14: IOMUXC_GPIO_B0_14_GPIO7_IO14 { + pinmux = <0x401f8174 5 0x0 0 0x401f8364>; + gpr = <0x400ac06c 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_lcdif_data10: IOMUXC_GPIO_B0_14_LCDIF_DATA10 { + pinmux = <0x401f8174 0 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_sai1_rx_sync: IOMUXC_GPIO_B0_14_SAI1_RX_SYNC { + pinmux = <0x401f8174 3 0x401f85a4 2 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_src_bt_cfg10: IOMUXC_GPIO_B0_14_SRC_BT_CFG10 { + pinmux = <0x401f8174 6 0x0 0 0x401f8364>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_in12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_IN12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_14_xbar1_xbar_inout12: IOMUXC_GPIO_B0_14_XBAR1_XBAR_INOUT12 { + pinmux = <0x401f8174 1 0x0 0 0x401f8364>; + gpr = <0x400ac018 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_arm_rxev: IOMUXC_GPIO_B0_15_ARM_RXEV { + pinmux = <0x401f8178 2 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_enet2_ref_clk2: IOMUXC_GPIO_B0_15_ENET2_REF_CLK2 { + pinmux = <0x401f8178 9 0x401f870c 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_enet2_tx_clk: IOMUXC_GPIO_B0_15_ENET2_TX_CLK { + pinmux = <0x401f8178 8 0x401f8728 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_flexio2_flexio15: IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 { + pinmux = <0x401f8178 4 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio2_io15: IOMUXC_GPIO_B0_15_GPIO2_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_gpio7_io15: IOMUXC_GPIO_B0_15_GPIO7_IO15 { + pinmux = <0x401f8178 5 0x0 0 0x401f8368>; + gpr = <0x400ac06c 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_lcdif_data11: IOMUXC_GPIO_B0_15_LCDIF_DATA11 { + pinmux = <0x401f8178 0 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_sai1_rx_bclk: IOMUXC_GPIO_B0_15_SAI1_RX_BCLK { + pinmux = <0x401f8178 3 0x401f8590 2 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_src_bt_cfg11: IOMUXC_GPIO_B0_15_SRC_BT_CFG11 { + pinmux = <0x401f8178 6 0x0 0 0x401f8368>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_in13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_IN13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b0_15_xbar1_xbar_inout13: IOMUXC_GPIO_B0_15_XBAR1_XBAR_INOUT13 { + pinmux = <0x401f8178 1 0x0 0 0x401f8368>; + gpr = <0x400ac018 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_enet2_rx_er: IOMUXC_GPIO_B1_00_ENET2_RX_ER { + pinmux = <0x401f817c 8 0x401f8720 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio2_flexio16: IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 { + pinmux = <0x401f817c 4 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexio3_flexio16: IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 { + pinmux = <0x401f817c 9 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f817c 6 0x401f8454 4 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio2_io16: IOMUXC_GPIO_B1_00_GPIO2_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_gpio7_io16: IOMUXC_GPIO_B1_00_GPIO7_IO16 { + pinmux = <0x401f817c 5 0x0 0 0x401f836c>; + gpr = <0x400ac06c 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lcdif_data12: IOMUXC_GPIO_B1_00_LCDIF_DATA12 { + pinmux = <0x401f817c 0 0x0 0 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_lpuart4_tx: IOMUXC_GPIO_B1_00_LPUART4_TX { + pinmux = <0x401f817c 2 0x401f8544 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_sai1_rx_data0: IOMUXC_GPIO_B1_00_SAI1_RX_DATA0 { + pinmux = <0x401f817c 3 0x401f8594 2 0x401f836c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_in14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_IN14 { + pinmux = <0x401f817c 1 0x401f8644 1 0x401f836c>; + gpr = <0x400ac018 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_00_xbar1_xbar_inout14: IOMUXC_GPIO_B1_00_XBAR1_XBAR_INOUT14 { + pinmux = <0x401f817c 1 0x401f8644 1 0x401f836c>; + gpr = <0x400ac018 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_enet2_rx_data0: IOMUXC_GPIO_B1_01_ENET2_RX_DATA0 { + pinmux = <0x401f8180 8 0x401f8714 2 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio2_flexio17: IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 { + pinmux = <0x401f8180 4 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexio3_flexio17: IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 { + pinmux = <0x401f8180 9 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f8180 6 0x401f8464 4 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio2_io17: IOMUXC_GPIO_B1_01_GPIO2_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_gpio7_io17: IOMUXC_GPIO_B1_01_GPIO7_IO17 { + pinmux = <0x401f8180 5 0x0 0 0x401f8370>; + gpr = <0x400ac06c 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lcdif_data13: IOMUXC_GPIO_B1_01_LCDIF_DATA13 { + pinmux = <0x401f8180 0 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_lpuart4_rx: IOMUXC_GPIO_B1_01_LPUART4_RX { + pinmux = <0x401f8180 2 0x401f8540 2 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_sai1_tx_data0: IOMUXC_GPIO_B1_01_SAI1_TX_DATA0 { + pinmux = <0x401f8180 3 0x0 0 0x401f8370>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_in15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_IN15 { + pinmux = <0x401f8180 1 0x401f8648 1 0x401f8370>; + gpr = <0x400ac018 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_01_xbar1_xbar_inout15: IOMUXC_GPIO_B1_01_XBAR1_XBAR_INOUT15 { + pinmux = <0x401f8180 1 0x401f8648 1 0x401f8370>; + gpr = <0x400ac018 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_enet2_rx_data1: IOMUXC_GPIO_B1_02_ENET2_RX_DATA1 { + pinmux = <0x401f8184 8 0x401f8718 2 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio2_flexio18: IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 { + pinmux = <0x401f8184 4 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexio3_flexio18: IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 { + pinmux = <0x401f8184 9 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f8184 6 0x401f8474 4 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio2_io18: IOMUXC_GPIO_B1_02_GPIO2_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_gpio7_io18: IOMUXC_GPIO_B1_02_GPIO7_IO18 { + pinmux = <0x401f8184 5 0x0 0 0x401f8374>; + gpr = <0x400ac06c 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lcdif_data14: IOMUXC_GPIO_B1_02_LCDIF_DATA14 { + pinmux = <0x401f8184 0 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_lpspi4_pcs2: IOMUXC_GPIO_B1_02_LPSPI4_PCS2 { + pinmux = <0x401f8184 2 0x0 0 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_sai1_tx_bclk: IOMUXC_GPIO_B1_02_SAI1_TX_BCLK { + pinmux = <0x401f8184 3 0x401f85a8 2 0x401f8374>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_in16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_IN16 { + pinmux = <0x401f8184 1 0x401f864c 1 0x401f8374>; + gpr = <0x400ac018 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_02_xbar1_xbar_inout16: IOMUXC_GPIO_B1_02_XBAR1_XBAR_INOUT16 { + pinmux = <0x401f8184 1 0x401f864c 1 0x401f8374>; + gpr = <0x400ac018 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_enet2_rx_en: IOMUXC_GPIO_B1_03_ENET2_RX_EN { + pinmux = <0x401f8188 8 0x401f871c 2 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio2_flexio19: IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 { + pinmux = <0x401f8188 4 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexio3_flexio19: IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 { + pinmux = <0x401f8188 9 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f8188 6 0x401f8484 3 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio2_io19: IOMUXC_GPIO_B1_03_GPIO2_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_gpio7_io19: IOMUXC_GPIO_B1_03_GPIO7_IO19 { + pinmux = <0x401f8188 5 0x0 0 0x401f8378>; + gpr = <0x400ac06c 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lcdif_data15: IOMUXC_GPIO_B1_03_LCDIF_DATA15 { + pinmux = <0x401f8188 0 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_lpspi4_pcs1: IOMUXC_GPIO_B1_03_LPSPI4_PCS1 { + pinmux = <0x401f8188 2 0x0 0 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_sai1_tx_sync: IOMUXC_GPIO_B1_03_SAI1_TX_SYNC { + pinmux = <0x401f8188 3 0x401f85ac 2 0x401f8378>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_in17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_IN17 { + pinmux = <0x401f8188 1 0x401f862c 3 0x401f8378>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_03_xbar1_xbar_inout17: IOMUXC_GPIO_B1_03_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8188 1 0x401f862c 3 0x401f8378>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_csi_data15: IOMUXC_GPIO_B1_04_CSI_DATA15 { + pinmux = <0x401f818c 2 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_enet_rx_data0: IOMUXC_GPIO_B1_04_ENET_RX_DATA0 { + pinmux = <0x401f818c 3 0x401f8434 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio2_flexio20: IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 { + pinmux = <0x401f818c 4 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_flexio3_flexio20: IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 { + pinmux = <0x401f818c 9 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio2_io20: IOMUXC_GPIO_B1_04_GPIO2_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpio7_io20: IOMUXC_GPIO_B1_04_GPIO7_IO20 { + pinmux = <0x401f818c 5 0x0 0 0x401f837c>; + gpr = <0x400ac06c 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_gpt1_clk: IOMUXC_GPIO_B1_04_GPT1_CLK { + pinmux = <0x401f818c 8 0x401f8760 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lcdif_data16: IOMUXC_GPIO_B1_04_LCDIF_DATA16 { + pinmux = <0x401f818c 0 0x0 0 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_04_lpspi4_pcs0: IOMUXC_GPIO_B1_04_LPSPI4_PCS0 { + pinmux = <0x401f818c 1 0x401f851c 1 0x401f837c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_csi_data14: IOMUXC_GPIO_B1_05_CSI_DATA14 { + pinmux = <0x401f8190 2 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_enet_rx_data1: IOMUXC_GPIO_B1_05_ENET_RX_DATA1 { + pinmux = <0x401f8190 3 0x401f8438 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio2_flexio21: IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 { + pinmux = <0x401f8190 4 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_flexio3_flexio21: IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 { + pinmux = <0x401f8190 9 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio2_io21: IOMUXC_GPIO_B1_05_GPIO2_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpio7_io21: IOMUXC_GPIO_B1_05_GPIO7_IO21 { + pinmux = <0x401f8190 5 0x0 0 0x401f8380>; + gpr = <0x400ac06c 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_gpt1_capture1: IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 { + pinmux = <0x401f8190 8 0x401f8758 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lcdif_data17: IOMUXC_GPIO_B1_05_LCDIF_DATA17 { + pinmux = <0x401f8190 0 0x0 0 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_05_lpspi4_sdi: IOMUXC_GPIO_B1_05_LPSPI4_SDI { + pinmux = <0x401f8190 1 0x401f8524 1 0x401f8380>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_csi_data13: IOMUXC_GPIO_B1_06_CSI_DATA13 { + pinmux = <0x401f8194 2 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_enet_rx_en: IOMUXC_GPIO_B1_06_ENET_RX_EN { + pinmux = <0x401f8194 3 0x401f843c 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio2_flexio22: IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 { + pinmux = <0x401f8194 4 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_flexio3_flexio22: IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 { + pinmux = <0x401f8194 9 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio2_io22: IOMUXC_GPIO_B1_06_GPIO2_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpio7_io22: IOMUXC_GPIO_B1_06_GPIO7_IO22 { + pinmux = <0x401f8194 5 0x0 0 0x401f8384>; + gpr = <0x400ac06c 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_gpt1_capture2: IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 { + pinmux = <0x401f8194 8 0x401f875c 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lcdif_data18: IOMUXC_GPIO_B1_06_LCDIF_DATA18 { + pinmux = <0x401f8194 0 0x0 0 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_06_lpspi4_sdo: IOMUXC_GPIO_B1_06_LPSPI4_SDO { + pinmux = <0x401f8194 1 0x401f8528 1 0x401f8384>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_csi_data12: IOMUXC_GPIO_B1_07_CSI_DATA12 { + pinmux = <0x401f8198 2 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_enet_tx_data0: IOMUXC_GPIO_B1_07_ENET_TX_DATA0 { + pinmux = <0x401f8198 3 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio2_flexio23: IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 { + pinmux = <0x401f8198 4 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_flexio3_flexio23: IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 { + pinmux = <0x401f8198 9 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio2_io23: IOMUXC_GPIO_B1_07_GPIO2_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpio7_io23: IOMUXC_GPIO_B1_07_GPIO7_IO23 { + pinmux = <0x401f8198 5 0x0 0 0x401f8388>; + gpr = <0x400ac06c 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_gpt1_compare1: IOMUXC_GPIO_B1_07_GPT1_COMPARE1 { + pinmux = <0x401f8198 8 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lcdif_data19: IOMUXC_GPIO_B1_07_LCDIF_DATA19 { + pinmux = <0x401f8198 0 0x0 0 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_07_lpspi4_sck: IOMUXC_GPIO_B1_07_LPSPI4_SCK { + pinmux = <0x401f8198 1 0x401f8520 1 0x401f8388>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_csi_data11: IOMUXC_GPIO_B1_08_CSI_DATA11 { + pinmux = <0x401f819c 2 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_enet_tx_data1: IOMUXC_GPIO_B1_08_ENET_TX_DATA1 { + pinmux = <0x401f819c 3 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexcan2_tx: IOMUXC_GPIO_B1_08_FLEXCAN2_TX { + pinmux = <0x401f819c 6 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio2_flexio24: IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 { + pinmux = <0x401f819c 4 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_flexio3_flexio24: IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 { + pinmux = <0x401f819c 9 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio2_io24: IOMUXC_GPIO_B1_08_GPIO2_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpio7_io24: IOMUXC_GPIO_B1_08_GPIO7_IO24 { + pinmux = <0x401f819c 5 0x0 0 0x401f838c>; + gpr = <0x400ac06c 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_gpt1_compare2: IOMUXC_GPIO_B1_08_GPT1_COMPARE2 { + pinmux = <0x401f819c 8 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_lcdif_data20: IOMUXC_GPIO_B1_08_LCDIF_DATA20 { + pinmux = <0x401f819c 0 0x0 0 0x401f838c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_08_qtimer1_timer3: IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 { + pinmux = <0x401f819c 1 0x0 0 0x401f838c>; + gpr = <0x400ac018 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_csi_data10: IOMUXC_GPIO_B1_09_CSI_DATA10 { + pinmux = <0x401f81a0 2 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_enet_tx_en: IOMUXC_GPIO_B1_09_ENET_TX_EN { + pinmux = <0x401f81a0 3 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexcan2_rx: IOMUXC_GPIO_B1_09_FLEXCAN2_RX { + pinmux = <0x401f81a0 6 0x401f8450 3 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio2_flexio25: IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 { + pinmux = <0x401f81a0 4 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_flexio3_flexio25: IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 { + pinmux = <0x401f81a0 9 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio2_io25: IOMUXC_GPIO_B1_09_GPIO2_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpio7_io25: IOMUXC_GPIO_B1_09_GPIO7_IO25 { + pinmux = <0x401f81a0 5 0x0 0 0x401f8390>; + gpr = <0x400ac06c 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_gpt1_compare3: IOMUXC_GPIO_B1_09_GPT1_COMPARE3 { + pinmux = <0x401f81a0 8 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_lcdif_data21: IOMUXC_GPIO_B1_09_LCDIF_DATA21 { + pinmux = <0x401f81a0 0 0x0 0 0x401f8390>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_09_qtimer2_timer3: IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 { + pinmux = <0x401f81a0 1 0x401f8578 1 0x401f8390>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_csi_data00: IOMUXC_GPIO_B1_10_CSI_DATA00 { + pinmux = <0x401f81a4 2 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_ref_clk: IOMUXC_GPIO_B1_10_ENET_REF_CLK { + pinmux = <0x401f81a4 6 0x401f842c 1 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_enet_tx_clk: IOMUXC_GPIO_B1_10_ENET_TX_CLK { + pinmux = <0x401f81a4 3 0x401f8448 1 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio2_flexio26: IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 { + pinmux = <0x401f81a4 4 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_flexio3_flexio26: IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 { + pinmux = <0x401f81a4 9 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio2_io26: IOMUXC_GPIO_B1_10_GPIO2_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_gpio7_io26: IOMUXC_GPIO_B1_10_GPIO7_IO26 { + pinmux = <0x401f81a4 5 0x0 0 0x401f8394>; + gpr = <0x400ac06c 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_lcdif_data22: IOMUXC_GPIO_B1_10_LCDIF_DATA22 { + pinmux = <0x401f81a4 0 0x0 0 0x401f8394>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_10_qtimer3_timer3: IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 { + pinmux = <0x401f81a4 1 0x401f8588 2 0x401f8394>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_csi_data01: IOMUXC_GPIO_B1_11_CSI_DATA01 { + pinmux = <0x401f81a8 2 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_enet_rx_er: IOMUXC_GPIO_B1_11_ENET_RX_ER { + pinmux = <0x401f81a8 3 0x401f8440 1 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio2_flexio27: IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 { + pinmux = <0x401f81a8 4 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_flexio3_flexio27: IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 { + pinmux = <0x401f81a8 9 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio2_io27: IOMUXC_GPIO_B1_11_GPIO2_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_gpio7_io27: IOMUXC_GPIO_B1_11_GPIO7_IO27 { + pinmux = <0x401f81a8 5 0x0 0 0x401f8398>; + gpr = <0x400ac06c 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lcdif_data23: IOMUXC_GPIO_B1_11_LCDIF_DATA23 { + pinmux = <0x401f81a8 0 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_lpspi4_pcs3: IOMUXC_GPIO_B1_11_LPSPI4_PCS3 { + pinmux = <0x401f81a8 6 0x0 0 0x401f8398>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_11_qtimer4_timer3: IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 { + pinmux = <0x401f81a8 1 0x0 0 0x401f8398>; + gpr = <0x400ac018 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_csi_pixclk: IOMUXC_GPIO_B1_12_CSI_PIXCLK { + pinmux = <0x401f81ac 2 0x401f8424 1 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_enet_1588_event0_in: IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN { + pinmux = <0x401f81ac 3 0x401f8444 2 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio2_flexio28: IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 { + pinmux = <0x401f81ac 4 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_flexio3_flexio28: IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 { + pinmux = <0x401f81ac 9 0x0 0 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio2_io28: IOMUXC_GPIO_B1_12_GPIO2_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_gpio7_io28: IOMUXC_GPIO_B1_12_GPIO7_IO28 { + pinmux = <0x401f81ac 5 0x0 0 0x401f839c>; + gpr = <0x400ac06c 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_lpuart5_tx: IOMUXC_GPIO_B1_12_LPUART5_TX { + pinmux = <0x401f81ac 1 0x401f854c 1 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_12_usdhc1_cd_b: IOMUXC_GPIO_B1_12_USDHC1_CD_B { + pinmux = <0x401f81ac 6 0x401f85d4 2 0x401f839c>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_csi_vsync: IOMUXC_GPIO_B1_13_CSI_VSYNC { + pinmux = <0x401f81b0 2 0x401f8428 2 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_enet_1588_event0_out: IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT { + pinmux = <0x401f81b0 3 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio2_flexio29: IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 { + pinmux = <0x401f81b0 4 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_flexio3_flexio29: IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 { + pinmux = <0x401f81b0 9 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio2_io29: IOMUXC_GPIO_B1_13_GPIO2_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_gpio7_io29: IOMUXC_GPIO_B1_13_GPIO7_IO29 { + pinmux = <0x401f81b0 5 0x0 0 0x401f83a0>; + gpr = <0x400ac06c 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_lpuart5_rx: IOMUXC_GPIO_B1_13_LPUART5_RX { + pinmux = <0x401f81b0 1 0x401f8548 1 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_semc_dqs4: IOMUXC_GPIO_B1_13_SEMC_DQS4 { + pinmux = <0x401f81b0 8 0x401f8788 3 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_usdhc1_wp: IOMUXC_GPIO_B1_13_USDHC1_WP { + pinmux = <0x401f81b0 6 0x401f85d8 3 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_13_wdog1_b: IOMUXC_GPIO_B1_13_WDOG1_B { + pinmux = <0x401f81b0 0 0x0 0 0x401f83a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_csi_hsync: IOMUXC_GPIO_B1_14_CSI_HSYNC { + pinmux = <0x401f81b4 2 0x401f8420 2 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet2_tx_data0: IOMUXC_GPIO_B1_14_ENET2_TX_DATA0 { + pinmux = <0x401f81b4 8 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_enet_mdc: IOMUXC_GPIO_B1_14_ENET_MDC { + pinmux = <0x401f81b4 0 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio2_flexio30: IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 { + pinmux = <0x401f81b4 4 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexio3_flexio30: IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 { + pinmux = <0x401f81b4 9 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_flexpwm4_pwma2: IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA2 { + pinmux = <0x401f81b4 1 0x401f849c 1 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio2_io30: IOMUXC_GPIO_B1_14_GPIO2_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_gpio7_io30: IOMUXC_GPIO_B1_14_GPIO7_IO30 { + pinmux = <0x401f81b4 5 0x0 0 0x401f83a4>; + gpr = <0x400ac06c 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_usdhc1_vselect: IOMUXC_GPIO_B1_14_USDHC1_VSELECT { + pinmux = <0x401f81b4 6 0x0 0 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_14_xbar1_xbar_in02: IOMUXC_GPIO_B1_14_XBAR1_XBAR_IN02 { + pinmux = <0x401f81b4 3 0x401f860c 1 0x401f83a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_csi_mclk: IOMUXC_GPIO_B1_15_CSI_MCLK { + pinmux = <0x401f81b8 2 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet2_tx_data1: IOMUXC_GPIO_B1_15_ENET2_TX_DATA1 { + pinmux = <0x401f81b8 8 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_enet_mdio: IOMUXC_GPIO_B1_15_ENET_MDIO { + pinmux = <0x401f81b8 0 0x401f8430 2 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio2_flexio31: IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 { + pinmux = <0x401f81b8 4 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexio3_flexio31: IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 { + pinmux = <0x401f81b8 9 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_flexpwm4_pwma3: IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA3 { + pinmux = <0x401f81b8 1 0x401f84a0 1 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio2_io31: IOMUXC_GPIO_B1_15_GPIO2_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_gpio7_io31: IOMUXC_GPIO_B1_15_GPIO7_IO31 { + pinmux = <0x401f81b8 5 0x0 0 0x401f83a8>; + gpr = <0x400ac06c 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_usdhc1_reset_b: IOMUXC_GPIO_B1_15_USDHC1_RESET_B { + pinmux = <0x401f81b8 6 0x0 0 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_b1_15_xbar1_xbar_in03: IOMUXC_GPIO_B1_15_XBAR1_XBAR_IN03 { + pinmux = <0x401f81b8 3 0x401f8610 1 0x401f83a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexio1_flexio00: IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 { + pinmux = <0x401f8014 4 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_flexpwm4_pwma0: IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA0 { + pinmux = <0x401f8014 1 0x401f8494 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio4_io00: IOMUXC_GPIO_EMC_00_GPIO4_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_gpio9_io00: IOMUXC_GPIO_EMC_00_GPIO9_IO00 { + pinmux = <0x401f8014 5 0x0 0 0x401f8204>; + gpr = <0x400ac074 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_lpspi2_sck: IOMUXC_GPIO_EMC_00_LPSPI2_SCK { + pinmux = <0x401f8014 2 0x401f8500 1 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_semc_data00: IOMUXC_GPIO_EMC_00_SEMC_DATA00 { + pinmux = <0x401f8014 0 0x0 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_00_xbar1_xbar_in02: IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 { + pinmux = <0x401f8014 3 0x401f860c 0 0x401f8204>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexio1_flexio01: IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 { + pinmux = <0x401f8018 4 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_flexpwm4_pwmb0: IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB0 { + pinmux = <0x401f8018 1 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio4_io01: IOMUXC_GPIO_EMC_01_GPIO4_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_gpio9_io01: IOMUXC_GPIO_EMC_01_GPIO9_IO01 { + pinmux = <0x401f8018 5 0x0 0 0x401f8208>; + gpr = <0x400ac074 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_lpspi2_pcs0: IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 { + pinmux = <0x401f8018 2 0x401f84fc 1 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_semc_data01: IOMUXC_GPIO_EMC_01_SEMC_DATA01 { + pinmux = <0x401f8018 0 0x0 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_01_xbar1_xbar_in03: IOMUXC_GPIO_EMC_01_XBAR1_XBAR_IN03 { + pinmux = <0x401f8018 3 0x401f8610 0 0x401f8208>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexio1_flexio02: IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 { + pinmux = <0x401f801c 4 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_flexpwm4_pwma1: IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA1 { + pinmux = <0x401f801c 1 0x401f8498 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio4_io02: IOMUXC_GPIO_EMC_02_GPIO4_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_gpio9_io02: IOMUXC_GPIO_EMC_02_GPIO9_IO02 { + pinmux = <0x401f801c 5 0x0 0 0x401f820c>; + gpr = <0x400ac074 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_lpspi2_sdo: IOMUXC_GPIO_EMC_02_LPSPI2_SDO { + pinmux = <0x401f801c 2 0x401f8508 1 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_semc_data02: IOMUXC_GPIO_EMC_02_SEMC_DATA02 { + pinmux = <0x401f801c 0 0x0 0 0x401f820c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_in04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_IN04 { + pinmux = <0x401f801c 3 0x401f8614 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_02_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_02_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f801c 3 0x401f8614 0 0x401f820c>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexio1_flexio03: IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 { + pinmux = <0x401f8020 4 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_flexpwm4_pwmb1: IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB1 { + pinmux = <0x401f8020 1 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio4_io03: IOMUXC_GPIO_EMC_03_GPIO4_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_gpio9_io03: IOMUXC_GPIO_EMC_03_GPIO9_IO03 { + pinmux = <0x401f8020 5 0x0 0 0x401f8210>; + gpr = <0x400ac074 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_lpspi2_sdi: IOMUXC_GPIO_EMC_03_LPSPI2_SDI { + pinmux = <0x401f8020 2 0x401f8504 1 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_semc_data03: IOMUXC_GPIO_EMC_03_SEMC_DATA03 { + pinmux = <0x401f8020 0 0x0 0 0x401f8210>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_in05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_IN05 { + pinmux = <0x401f8020 3 0x401f8618 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_03_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_03_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f8020 3 0x401f8618 0 0x401f8210>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexio1_flexio04: IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 { + pinmux = <0x401f8024 4 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_flexpwm4_pwma2: IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA2 { + pinmux = <0x401f8024 1 0x401f849c 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio4_io04: IOMUXC_GPIO_EMC_04_GPIO4_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_gpio9_io04: IOMUXC_GPIO_EMC_04_GPIO9_IO04 { + pinmux = <0x401f8024 5 0x0 0 0x401f8214>; + gpr = <0x400ac074 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_sai2_tx_data: IOMUXC_GPIO_EMC_04_SAI2_TX_DATA { + pinmux = <0x401f8024 2 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_semc_data04: IOMUXC_GPIO_EMC_04_SEMC_DATA04 { + pinmux = <0x401f8024 0 0x0 0 0x401f8214>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_in06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_IN06 { + pinmux = <0x401f8024 3 0x401f861c 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_04_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f8024 3 0x401f861c 0 0x401f8214>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexio1_flexio05: IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 { + pinmux = <0x401f8028 4 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_flexpwm4_pwmb2: IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB2 { + pinmux = <0x401f8028 1 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio4_io05: IOMUXC_GPIO_EMC_05_GPIO4_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_gpio9_io05: IOMUXC_GPIO_EMC_05_GPIO9_IO05 { + pinmux = <0x401f8028 5 0x0 0 0x401f8218>; + gpr = <0x400ac074 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_sai2_tx_sync: IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC { + pinmux = <0x401f8028 2 0x401f85c4 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_semc_data05: IOMUXC_GPIO_EMC_05_SEMC_DATA05 { + pinmux = <0x401f8028 0 0x0 0 0x401f8218>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_in07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_IN07 { + pinmux = <0x401f8028 3 0x401f8620 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_05_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f8028 3 0x401f8620 0 0x401f8218>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexio1_flexio06: IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 { + pinmux = <0x401f802c 4 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_flexpwm2_pwma0: IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA0 { + pinmux = <0x401f802c 1 0x401f8478 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio4_io06: IOMUXC_GPIO_EMC_06_GPIO4_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_gpio9_io06: IOMUXC_GPIO_EMC_06_GPIO9_IO06 { + pinmux = <0x401f802c 5 0x0 0 0x401f821c>; + gpr = <0x400ac074 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_sai2_tx_bclk: IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK { + pinmux = <0x401f802c 2 0x401f85c0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_semc_data06: IOMUXC_GPIO_EMC_06_SEMC_DATA06 { + pinmux = <0x401f802c 0 0x0 0 0x401f821c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_in08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_IN08 { + pinmux = <0x401f802c 3 0x401f8624 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_06_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f802c 3 0x401f8624 0 0x401f821c>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexio1_flexio07: IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 { + pinmux = <0x401f8030 4 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_flexpwm2_pwmb0: IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB0 { + pinmux = <0x401f8030 1 0x401f8488 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio4_io07: IOMUXC_GPIO_EMC_07_GPIO4_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_gpio9_io07: IOMUXC_GPIO_EMC_07_GPIO9_IO07 { + pinmux = <0x401f8030 5 0x0 0 0x401f8220>; + gpr = <0x400ac074 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_sai2_mclk: IOMUXC_GPIO_EMC_07_SAI2_MCLK { + pinmux = <0x401f8030 2 0x401f85b0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_semc_data07: IOMUXC_GPIO_EMC_07_SEMC_DATA07 { + pinmux = <0x401f8030 0 0x0 0 0x401f8220>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_in09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_IN09 { + pinmux = <0x401f8030 3 0x401f8628 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_07_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f8030 3 0x401f8628 0 0x401f8220>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexio1_flexio08: IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 { + pinmux = <0x401f8034 4 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_flexpwm2_pwma1: IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA1 { + pinmux = <0x401f8034 1 0x401f847c 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio4_io08: IOMUXC_GPIO_EMC_08_GPIO4_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_gpio9_io08: IOMUXC_GPIO_EMC_08_GPIO9_IO08 { + pinmux = <0x401f8034 5 0x0 0 0x401f8224>; + gpr = <0x400ac074 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_sai2_rx_data: IOMUXC_GPIO_EMC_08_SAI2_RX_DATA { + pinmux = <0x401f8034 2 0x401f85b8 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_semc_dm0: IOMUXC_GPIO_EMC_08_SEMC_DM0 { + pinmux = <0x401f8034 0 0x0 0 0x401f8224>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_in17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_IN17 { + pinmux = <0x401f8034 3 0x401f862c 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_08_xbar1_xbar_inout17: IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT17 { + pinmux = <0x401f8034 3 0x401f862c 0 0x401f8224>; + gpr = <0x400ac018 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexcan2_tx: IOMUXC_GPIO_EMC_09_FLEXCAN2_TX { + pinmux = <0x401f8038 3 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexio1_flexio09: IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 { + pinmux = <0x401f8038 4 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_flexpwm2_pwmb1: IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB1 { + pinmux = <0x401f8038 1 0x401f848c 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio4_io09: IOMUXC_GPIO_EMC_09_GPIO4_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_gpio9_io09: IOMUXC_GPIO_EMC_09_GPIO9_IO09 { + pinmux = <0x401f8038 5 0x0 0 0x401f8228>; + gpr = <0x400ac074 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_sai2_rx_sync: IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC { + pinmux = <0x401f8038 2 0x401f85bc 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_09_semc_addr00: IOMUXC_GPIO_EMC_09_SEMC_ADDR00 { + pinmux = <0x401f8038 0 0x0 0 0x401f8228>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexcan2_rx: IOMUXC_GPIO_EMC_10_FLEXCAN2_RX { + pinmux = <0x401f803c 3 0x401f8450 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexio1_flexio10: IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 { + pinmux = <0x401f803c 4 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_flexpwm2_pwma2: IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA2 { + pinmux = <0x401f803c 1 0x401f8480 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio4_io10: IOMUXC_GPIO_EMC_10_GPIO4_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_gpio9_io10: IOMUXC_GPIO_EMC_10_GPIO9_IO10 { + pinmux = <0x401f803c 5 0x0 0 0x401f822c>; + gpr = <0x400ac074 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_sai2_rx_bclk: IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK { + pinmux = <0x401f803c 2 0x401f85b4 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_10_semc_addr01: IOMUXC_GPIO_EMC_10_SEMC_ADDR01 { + pinmux = <0x401f803c 0 0x0 0 0x401f822c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexio1_flexio11: IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 { + pinmux = <0x401f8040 4 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_flexpwm2_pwmb2: IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB2 { + pinmux = <0x401f8040 1 0x401f8490 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio4_io11: IOMUXC_GPIO_EMC_11_GPIO4_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_gpio9_io11: IOMUXC_GPIO_EMC_11_GPIO9_IO11 { + pinmux = <0x401f8040 5 0x0 0 0x401f8230>; + gpr = <0x400ac074 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_lpi2c4_sda: IOMUXC_GPIO_EMC_11_LPI2C4_SDA { + pinmux = <0x401f8040 2 0x401f84e8 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_semc_addr02: IOMUXC_GPIO_EMC_11_SEMC_ADDR02 { + pinmux = <0x401f8040 0 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_11_usdhc2_reset_b: IOMUXC_GPIO_EMC_11_USDHC2_RESET_B { + pinmux = <0x401f8040 3 0x0 0 0x401f8230>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_flexpwm1_pwma3: IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA3 { + pinmux = <0x401f8044 4 0x401f8454 1 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio4_io12: IOMUXC_GPIO_EMC_12_GPIO4_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_gpio9_io12: IOMUXC_GPIO_EMC_12_GPIO9_IO12 { + pinmux = <0x401f8044 5 0x0 0 0x401f8234>; + gpr = <0x400ac074 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_lpi2c4_scl: IOMUXC_GPIO_EMC_12_LPI2C4_SCL { + pinmux = <0x401f8044 2 0x401f84e4 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_semc_addr03: IOMUXC_GPIO_EMC_12_SEMC_ADDR03 { + pinmux = <0x401f8044 0 0x0 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_usdhc1_wp: IOMUXC_GPIO_EMC_12_USDHC1_WP { + pinmux = <0x401f8044 3 0x401f85d8 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_12_xbar1_xbar_in24: IOMUXC_GPIO_EMC_12_XBAR1_XBAR_IN24 { + pinmux = <0x401f8044 1 0x401f8640 0 0x401f8234>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB3 { + pinmux = <0x401f8048 4 0x401f8464 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio4_io13: IOMUXC_GPIO_EMC_13_GPIO4_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_gpio9_io13: IOMUXC_GPIO_EMC_13_GPIO9_IO13 { + pinmux = <0x401f8048 5 0x0 0 0x401f8238>; + gpr = <0x400ac074 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_lpuart3_tx: IOMUXC_GPIO_EMC_13_LPUART3_TX { + pinmux = <0x401f8048 2 0x401f853c 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_mqs_right: IOMUXC_GPIO_EMC_13_MQS_RIGHT { + pinmux = <0x401f8048 3 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_semc_addr04: IOMUXC_GPIO_EMC_13_SEMC_ADDR04 { + pinmux = <0x401f8048 0 0x0 0 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_13_xbar1_xbar_in25: IOMUXC_GPIO_EMC_13_XBAR1_XBAR_IN25 { + pinmux = <0x401f8048 1 0x401f8650 1 0x401f8238>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio4_io14: IOMUXC_GPIO_EMC_14_GPIO4_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_gpio9_io14: IOMUXC_GPIO_EMC_14_GPIO9_IO14 { + pinmux = <0x401f804c 5 0x0 0 0x401f823c>; + gpr = <0x400ac074 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpspi2_pcs1: IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 { + pinmux = <0x401f804c 4 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_lpuart3_rx: IOMUXC_GPIO_EMC_14_LPUART3_RX { + pinmux = <0x401f804c 2 0x401f8538 1 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_mqs_left: IOMUXC_GPIO_EMC_14_MQS_LEFT { + pinmux = <0x401f804c 3 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_semc_addr05: IOMUXC_GPIO_EMC_14_SEMC_ADDR05 { + pinmux = <0x401f804c 0 0x0 0 0x401f823c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_in19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_IN19 { + pinmux = <0x401f804c 1 0x401f8654 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_14_xbar1_xbar_inout19: IOMUXC_GPIO_EMC_14_XBAR1_XBAR_INOUT19 { + pinmux = <0x401f804c 1 0x401f8654 0 0x401f823c>; + gpr = <0x400ac018 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio4_io15: IOMUXC_GPIO_EMC_15_GPIO4_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_gpio9_io15: IOMUXC_GPIO_EMC_15_GPIO9_IO15 { + pinmux = <0x401f8050 5 0x0 0 0x401f8240>; + gpr = <0x400ac074 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_lpuart3_cts_b: IOMUXC_GPIO_EMC_15_LPUART3_CTS_B { + pinmux = <0x401f8050 2 0x401f8534 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_qtimer3_timer0: IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 { + pinmux = <0x401f8050 4 0x401f857c 0 0x401f8240>; + gpr = <0x400ac018 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_semc_addr06: IOMUXC_GPIO_EMC_15_SEMC_ADDR06 { + pinmux = <0x401f8050 0 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_spdif_out: IOMUXC_GPIO_EMC_15_SPDIF_OUT { + pinmux = <0x401f8050 3 0x0 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_15_xbar1_xbar_in20: IOMUXC_GPIO_EMC_15_XBAR1_XBAR_IN20 { + pinmux = <0x401f8050 1 0x401f8634 0 0x401f8240>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio4_io16: IOMUXC_GPIO_EMC_16_GPIO4_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_gpio9_io16: IOMUXC_GPIO_EMC_16_GPIO9_IO16 { + pinmux = <0x401f8054 5 0x0 0 0x401f8244>; + gpr = <0x400ac074 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_lpuart3_rts_b: IOMUXC_GPIO_EMC_16_LPUART3_RTS_B { + pinmux = <0x401f8054 2 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_qtimer3_timer1: IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 { + pinmux = <0x401f8054 4 0x401f8580 1 0x401f8244>; + gpr = <0x400ac018 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_semc_addr07: IOMUXC_GPIO_EMC_16_SEMC_ADDR07 { + pinmux = <0x401f8054 0 0x0 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_spdif_in: IOMUXC_GPIO_EMC_16_SPDIF_IN { + pinmux = <0x401f8054 3 0x401f85c8 1 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_16_xbar1_xbar_in21: IOMUXC_GPIO_EMC_16_XBAR1_XBAR_IN21 { + pinmux = <0x401f8054 1 0x401f8658 0 0x401f8244>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexcan1_tx: IOMUXC_GPIO_EMC_17_FLEXCAN1_TX { + pinmux = <0x401f8058 3 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_flexpwm4_pwma3: IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA3 { + pinmux = <0x401f8058 1 0x401f84a0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio4_io17: IOMUXC_GPIO_EMC_17_GPIO4_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_gpio9_io17: IOMUXC_GPIO_EMC_17_GPIO9_IO17 { + pinmux = <0x401f8058 5 0x0 0 0x401f8248>; + gpr = <0x400ac074 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_lpuart4_cts_b: IOMUXC_GPIO_EMC_17_LPUART4_CTS_B { + pinmux = <0x401f8058 2 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_qtimer3_timer2: IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 { + pinmux = <0x401f8058 4 0x401f8584 0 0x401f8248>; + gpr = <0x400ac018 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_17_semc_addr08: IOMUXC_GPIO_EMC_17_SEMC_ADDR08 { + pinmux = <0x401f8058 0 0x0 0 0x401f8248>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexcan1_rx: IOMUXC_GPIO_EMC_18_FLEXCAN1_RX { + pinmux = <0x401f805c 3 0x401f844c 1 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_flexpwm4_pwmb3: IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB3 { + pinmux = <0x401f805c 1 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio4_io18: IOMUXC_GPIO_EMC_18_GPIO4_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_gpio9_io18: IOMUXC_GPIO_EMC_18_GPIO9_IO18 { + pinmux = <0x401f805c 5 0x0 0 0x401f824c>; + gpr = <0x400ac074 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_lpuart4_rts_b: IOMUXC_GPIO_EMC_18_LPUART4_RTS_B { + pinmux = <0x401f805c 2 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_qtimer3_timer3: IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 { + pinmux = <0x401f805c 4 0x401f8588 0 0x401f824c>; + gpr = <0x400ac018 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_semc_addr09: IOMUXC_GPIO_EMC_18_SEMC_ADDR09 { + pinmux = <0x401f805c 0 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_18_snvs_vio_5_ctl: IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL { + pinmux = <0x401f805c 6 0x0 0 0x401f824c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_enet_rx_data1: IOMUXC_GPIO_EMC_19_ENET_RX_DATA1 { + pinmux = <0x401f8060 3 0x401f8438 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_flexpwm2_pwma3: IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA3 { + pinmux = <0x401f8060 1 0x401f8474 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio4_io19: IOMUXC_GPIO_EMC_19_GPIO4_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_gpio9_io19: IOMUXC_GPIO_EMC_19_GPIO9_IO19 { + pinmux = <0x401f8060 5 0x0 0 0x401f8250>; + gpr = <0x400ac074 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_lpuart4_tx: IOMUXC_GPIO_EMC_19_LPUART4_TX { + pinmux = <0x401f8060 2 0x401f8544 1 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_qtimer2_timer0: IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 { + pinmux = <0x401f8060 4 0x401f856c 0 0x401f8250>; + gpr = <0x400ac018 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_semc_addr11: IOMUXC_GPIO_EMC_19_SEMC_ADDR11 { + pinmux = <0x401f8060 0 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_19_snvs_vio_5_b: IOMUXC_GPIO_EMC_19_SNVS_VIO_5_B { + pinmux = <0x401f8060 6 0x0 0 0x401f8250>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_enet_rx_data0: IOMUXC_GPIO_EMC_20_ENET_RX_DATA0 { + pinmux = <0x401f8064 3 0x401f8434 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_flexpwm2_pwmb3: IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB3 { + pinmux = <0x401f8064 1 0x401f8484 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio4_io20: IOMUXC_GPIO_EMC_20_GPIO4_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_gpio9_io20: IOMUXC_GPIO_EMC_20_GPIO9_IO20 { + pinmux = <0x401f8064 5 0x0 0 0x401f8254>; + gpr = <0x400ac074 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_lpuart4_rx: IOMUXC_GPIO_EMC_20_LPUART4_RX { + pinmux = <0x401f8064 2 0x401f8540 1 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_qtimer2_timer1: IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 { + pinmux = <0x401f8064 4 0x401f8570 0 0x401f8254>; + gpr = <0x400ac018 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_20_semc_addr12: IOMUXC_GPIO_EMC_20_SEMC_ADDR12 { + pinmux = <0x401f8064 0 0x0 0 0x401f8254>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_enet_tx_data1: IOMUXC_GPIO_EMC_21_ENET_TX_DATA1 { + pinmux = <0x401f8068 3 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_flexpwm3_pwma3: IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA3 { + pinmux = <0x401f8068 1 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio4_io21: IOMUXC_GPIO_EMC_21_GPIO4_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_gpio9_io21: IOMUXC_GPIO_EMC_21_GPIO9_IO21 { + pinmux = <0x401f8068 5 0x0 0 0x401f8258>; + gpr = <0x400ac074 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_lpi2c3_sda: IOMUXC_GPIO_EMC_21_LPI2C3_SDA { + pinmux = <0x401f8068 2 0x401f84e0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_qtimer2_timer2: IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 { + pinmux = <0x401f8068 4 0x401f8574 0 0x401f8258>; + gpr = <0x400ac018 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_21_semc_ba0: IOMUXC_GPIO_EMC_21_SEMC_BA0 { + pinmux = <0x401f8068 0 0x0 0 0x401f8258>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_enet_tx_data0: IOMUXC_GPIO_EMC_22_ENET_TX_DATA0 { + pinmux = <0x401f806c 3 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_flexpwm3_pwmb3: IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB3 { + pinmux = <0x401f806c 1 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio4_io22: IOMUXC_GPIO_EMC_22_GPIO4_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_gpio9_io22: IOMUXC_GPIO_EMC_22_GPIO9_IO22 { + pinmux = <0x401f806c 5 0x0 0 0x401f825c>; + gpr = <0x400ac074 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_lpi2c3_scl: IOMUXC_GPIO_EMC_22_LPI2C3_SCL { + pinmux = <0x401f806c 2 0x401f84dc 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_qtimer2_timer3: IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 { + pinmux = <0x401f806c 4 0x401f8578 0 0x401f825c>; + gpr = <0x400ac018 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_22_semc_ba1: IOMUXC_GPIO_EMC_22_SEMC_BA1 { + pinmux = <0x401f806c 0 0x0 0 0x401f825c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_enet_rx_en: IOMUXC_GPIO_EMC_23_ENET_RX_EN { + pinmux = <0x401f8070 3 0x401f843c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_flexpwm1_pwma0: IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA0 { + pinmux = <0x401f8070 1 0x401f8458 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio4_io23: IOMUXC_GPIO_EMC_23_GPIO4_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpio9_io23: IOMUXC_GPIO_EMC_23_GPIO9_IO23 { + pinmux = <0x401f8070 5 0x0 0 0x401f8260>; + gpr = <0x400ac074 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_gpt1_capture2: IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 { + pinmux = <0x401f8070 4 0x401f875c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_lpuart5_tx: IOMUXC_GPIO_EMC_23_LPUART5_TX { + pinmux = <0x401f8070 2 0x401f854c 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_23_semc_addr10: IOMUXC_GPIO_EMC_23_SEMC_ADDR10 { + pinmux = <0x401f8070 0 0x0 0 0x401f8260>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_enet_tx_en: IOMUXC_GPIO_EMC_24_ENET_TX_EN { + pinmux = <0x401f8074 3 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_flexpwm1_pwmb0: IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB0 { + pinmux = <0x401f8074 1 0x401f8468 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio4_io24: IOMUXC_GPIO_EMC_24_GPIO4_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpio9_io24: IOMUXC_GPIO_EMC_24_GPIO9_IO24 { + pinmux = <0x401f8074 5 0x0 0 0x401f8264>; + gpr = <0x400ac074 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_gpt1_capture1: IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 { + pinmux = <0x401f8074 4 0x401f8758 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_lpuart5_rx: IOMUXC_GPIO_EMC_24_LPUART5_RX { + pinmux = <0x401f8074 2 0x401f8548 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_24_semc_cas: IOMUXC_GPIO_EMC_24_SEMC_CAS { + pinmux = <0x401f8074 0 0x0 0 0x401f8264>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_ref_clk: IOMUXC_GPIO_EMC_25_ENET_REF_CLK { + pinmux = <0x401f8078 4 0x401f842c 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_enet_tx_clk: IOMUXC_GPIO_EMC_25_ENET_TX_CLK { + pinmux = <0x401f8078 3 0x401f8448 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_flexpwm1_pwma1: IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA1 { + pinmux = <0x401f8078 1 0x401f845c 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio4_io25: IOMUXC_GPIO_EMC_25_GPIO4_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_gpio9_io25: IOMUXC_GPIO_EMC_25_GPIO9_IO25 { + pinmux = <0x401f8078 5 0x0 0 0x401f8268>; + gpr = <0x400ac074 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_lpuart6_tx: IOMUXC_GPIO_EMC_25_LPUART6_TX { + pinmux = <0x401f8078 2 0x401f8554 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_25_semc_ras: IOMUXC_GPIO_EMC_25_SEMC_RAS { + pinmux = <0x401f8078 0 0x0 0 0x401f8268>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_enet_rx_er: IOMUXC_GPIO_EMC_26_ENET_RX_ER { + pinmux = <0x401f807c 3 0x401f8440 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexio1_flexio12: IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 { + pinmux = <0x401f807c 4 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_flexpwm1_pwmb1: IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB1 { + pinmux = <0x401f807c 1 0x401f846c 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio4_io26: IOMUXC_GPIO_EMC_26_GPIO4_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_gpio9_io26: IOMUXC_GPIO_EMC_26_GPIO9_IO26 { + pinmux = <0x401f807c 5 0x0 0 0x401f826c>; + gpr = <0x400ac074 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_lpuart6_rx: IOMUXC_GPIO_EMC_26_LPUART6_RX { + pinmux = <0x401f807c 2 0x401f8550 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_26_semc_clk: IOMUXC_GPIO_EMC_26_SEMC_CLK { + pinmux = <0x401f807c 0 0x0 0 0x401f826c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexio1_flexio13: IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 { + pinmux = <0x401f8080 4 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_flexpwm1_pwma2: IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA2 { + pinmux = <0x401f8080 1 0x401f8460 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio4_io27: IOMUXC_GPIO_EMC_27_GPIO4_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_gpio9_io27: IOMUXC_GPIO_EMC_27_GPIO9_IO27 { + pinmux = <0x401f8080 5 0x0 0 0x401f8270>; + gpr = <0x400ac074 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpspi1_sck: IOMUXC_GPIO_EMC_27_LPSPI1_SCK { + pinmux = <0x401f8080 3 0x401f84f0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_lpuart5_rts_b: IOMUXC_GPIO_EMC_27_LPUART5_RTS_B { + pinmux = <0x401f8080 2 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_27_semc_cke: IOMUXC_GPIO_EMC_27_SEMC_CKE { + pinmux = <0x401f8080 0 0x0 0 0x401f8270>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexio1_flexio14: IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 { + pinmux = <0x401f8084 4 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_flexpwm1_pwmb2: IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB2 { + pinmux = <0x401f8084 1 0x401f8470 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio4_io28: IOMUXC_GPIO_EMC_28_GPIO4_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_gpio9_io28: IOMUXC_GPIO_EMC_28_GPIO9_IO28 { + pinmux = <0x401f8084 5 0x0 0 0x401f8274>; + gpr = <0x400ac074 0x1c 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpspi1_sdo: IOMUXC_GPIO_EMC_28_LPSPI1_SDO { + pinmux = <0x401f8084 3 0x401f84f8 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_lpuart5_cts_b: IOMUXC_GPIO_EMC_28_LPUART5_CTS_B { + pinmux = <0x401f8084 2 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_28_semc_we: IOMUXC_GPIO_EMC_28_SEMC_WE { + pinmux = <0x401f8084 0 0x0 0 0x401f8274>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexio1_flexio15: IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 { + pinmux = <0x401f8088 4 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_flexpwm3_pwma0: IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA0 { + pinmux = <0x401f8088 1 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio4_io29: IOMUXC_GPIO_EMC_29_GPIO4_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_gpio9_io29: IOMUXC_GPIO_EMC_29_GPIO9_IO29 { + pinmux = <0x401f8088 5 0x0 0 0x401f8278>; + gpr = <0x400ac074 0x1d 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpspi1_sdi: IOMUXC_GPIO_EMC_29_LPSPI1_SDI { + pinmux = <0x401f8088 3 0x401f84f4 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_lpuart6_rts_b: IOMUXC_GPIO_EMC_29_LPUART6_RTS_B { + pinmux = <0x401f8088 2 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_29_semc_cs0: IOMUXC_GPIO_EMC_29_SEMC_CS0 { + pinmux = <0x401f8088 0 0x0 0 0x401f8278>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_csi_data23: IOMUXC_GPIO_EMC_30_CSI_DATA23 { + pinmux = <0x401f808c 4 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_enet2_tx_data0: IOMUXC_GPIO_EMC_30_ENET2_TX_DATA0 { + pinmux = <0x401f808c 8 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_flexpwm3_pwmb0: IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB0 { + pinmux = <0x401f808c 1 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio4_io30: IOMUXC_GPIO_EMC_30_GPIO4_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_gpio9_io30: IOMUXC_GPIO_EMC_30_GPIO9_IO30 { + pinmux = <0x401f808c 5 0x0 0 0x401f827c>; + gpr = <0x400ac074 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpspi1_pcs0: IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 { + pinmux = <0x401f808c 3 0x401f84ec 1 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_lpuart6_cts_b: IOMUXC_GPIO_EMC_30_LPUART6_CTS_B { + pinmux = <0x401f808c 2 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_30_semc_data08: IOMUXC_GPIO_EMC_30_SEMC_DATA08 { + pinmux = <0x401f808c 0 0x0 0 0x401f827c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_csi_data22: IOMUXC_GPIO_EMC_31_CSI_DATA22 { + pinmux = <0x401f8090 4 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_enet2_tx_data1: IOMUXC_GPIO_EMC_31_ENET2_TX_DATA1 { + pinmux = <0x401f8090 8 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_flexpwm3_pwma1: IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA1 { + pinmux = <0x401f8090 1 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio4_io31: IOMUXC_GPIO_EMC_31_GPIO4_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_gpio9_io31: IOMUXC_GPIO_EMC_31_GPIO9_IO31 { + pinmux = <0x401f8090 5 0x0 0 0x401f8280>; + gpr = <0x400ac074 0x1f 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpspi1_pcs1: IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 { + pinmux = <0x401f8090 3 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_lpuart7_tx: IOMUXC_GPIO_EMC_31_LPUART7_TX { + pinmux = <0x401f8090 2 0x401f855c 1 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_31_semc_data09: IOMUXC_GPIO_EMC_31_SEMC_DATA09 { + pinmux = <0x401f8090 0 0x0 0 0x401f8280>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_ccm_pmic_rdy: IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY { + pinmux = <0x401f8094 3 0x401f83fc 4 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_csi_data21: IOMUXC_GPIO_EMC_32_CSI_DATA21 { + pinmux = <0x401f8094 4 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_enet2_tx_en: IOMUXC_GPIO_EMC_32_ENET2_TX_EN { + pinmux = <0x401f8094 8 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_flexpwm3_pwmb1: IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB1 { + pinmux = <0x401f8094 1 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio3_io18: IOMUXC_GPIO_EMC_32_GPIO3_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_gpio8_io18: IOMUXC_GPIO_EMC_32_GPIO8_IO18 { + pinmux = <0x401f8094 5 0x0 0 0x401f8284>; + gpr = <0x400ac070 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_lpuart7_rx: IOMUXC_GPIO_EMC_32_LPUART7_RX { + pinmux = <0x401f8094 2 0x401f8558 1 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_32_semc_data10: IOMUXC_GPIO_EMC_32_SEMC_DATA10 { + pinmux = <0x401f8094 0 0x0 0 0x401f8284>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_csi_data20: IOMUXC_GPIO_EMC_33_CSI_DATA20 { + pinmux = <0x401f8098 4 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_enet2_ref_clk2: IOMUXC_GPIO_EMC_33_ENET2_REF_CLK2 { + pinmux = <0x401f8098 9 0x401f870c 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_enet2_tx_clk: IOMUXC_GPIO_EMC_33_ENET2_TX_CLK { + pinmux = <0x401f8098 8 0x401f8728 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_flexpwm3_pwma2: IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA2 { + pinmux = <0x401f8098 1 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio3_io19: IOMUXC_GPIO_EMC_33_GPIO3_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_gpio8_io19: IOMUXC_GPIO_EMC_33_GPIO8_IO19 { + pinmux = <0x401f8098 5 0x0 0 0x401f8288>; + gpr = <0x400ac070 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_sai3_rx_data: IOMUXC_GPIO_EMC_33_SAI3_RX_DATA { + pinmux = <0x401f8098 3 0x401f8778 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_semc_data11: IOMUXC_GPIO_EMC_33_SEMC_DATA11 { + pinmux = <0x401f8098 0 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_33_usdhc1_reset_b: IOMUXC_GPIO_EMC_33_USDHC1_RESET_B { + pinmux = <0x401f8098 2 0x0 0 0x401f8288>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_csi_data19: IOMUXC_GPIO_EMC_34_CSI_DATA19 { + pinmux = <0x401f809c 4 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_enet2_rx_er: IOMUXC_GPIO_EMC_34_ENET2_RX_ER { + pinmux = <0x401f809c 8 0x401f8720 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_flexpwm3_pwmb2: IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB2 { + pinmux = <0x401f809c 1 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio3_io20: IOMUXC_GPIO_EMC_34_GPIO3_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_gpio8_io20: IOMUXC_GPIO_EMC_34_GPIO8_IO20 { + pinmux = <0x401f809c 5 0x0 0 0x401f828c>; + gpr = <0x400ac070 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_sai3_rx_sync: IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC { + pinmux = <0x401f809c 3 0x401f877c 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_semc_data12: IOMUXC_GPIO_EMC_34_SEMC_DATA12 { + pinmux = <0x401f809c 0 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_34_usdhc1_vselect: IOMUXC_GPIO_EMC_34_USDHC1_VSELECT { + pinmux = <0x401f809c 2 0x0 0 0x401f828c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_csi_data18: IOMUXC_GPIO_EMC_35_CSI_DATA18 { + pinmux = <0x401f80a0 4 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_enet2_rx_data0: IOMUXC_GPIO_EMC_35_ENET2_RX_DATA0 { + pinmux = <0x401f80a0 8 0x401f8714 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio3_io21: IOMUXC_GPIO_EMC_35_GPIO3_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpio8_io21: IOMUXC_GPIO_EMC_35_GPIO8_IO21 { + pinmux = <0x401f80a0 5 0x0 0 0x401f8290>; + gpr = <0x400ac070 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_gpt1_compare1: IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 { + pinmux = <0x401f80a0 2 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_sai3_rx_bclk: IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK { + pinmux = <0x401f80a0 3 0x401f8774 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_semc_data13: IOMUXC_GPIO_EMC_35_SEMC_DATA13 { + pinmux = <0x401f80a0 0 0x0 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_usdhc1_cd_b: IOMUXC_GPIO_EMC_35_USDHC1_CD_B { + pinmux = <0x401f80a0 6 0x401f85d4 0 0x401f8290>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_in18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_IN18 { + pinmux = <0x401f80a0 1 0x401f8630 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_35_xbar1_xbar_inout18: IOMUXC_GPIO_EMC_35_XBAR1_XBAR_INOUT18 { + pinmux = <0x401f80a0 1 0x401f8630 0 0x401f8290>; + gpr = <0x400ac018 0x1e 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_csi_data17: IOMUXC_GPIO_EMC_36_CSI_DATA17 { + pinmux = <0x401f80a4 4 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_enet2_rx_data1: IOMUXC_GPIO_EMC_36_ENET2_RX_DATA1 { + pinmux = <0x401f80a4 8 0x401f8718 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_flexcan3_tx: IOMUXC_GPIO_EMC_36_FLEXCAN3_TX { + pinmux = <0x401f80a4 9 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio3_io22: IOMUXC_GPIO_EMC_36_GPIO3_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpio8_io22: IOMUXC_GPIO_EMC_36_GPIO8_IO22 { + pinmux = <0x401f80a4 5 0x0 0 0x401f8294>; + gpr = <0x400ac070 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_gpt1_compare2: IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 { + pinmux = <0x401f80a4 2 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_sai3_tx_data: IOMUXC_GPIO_EMC_36_SAI3_TX_DATA { + pinmux = <0x401f80a4 3 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_semc_data14: IOMUXC_GPIO_EMC_36_SEMC_DATA14 { + pinmux = <0x401f80a4 0 0x0 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_usdhc1_wp: IOMUXC_GPIO_EMC_36_USDHC1_WP { + pinmux = <0x401f80a4 6 0x401f85d8 1 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_36_xbar1_xbar_in22: IOMUXC_GPIO_EMC_36_XBAR1_XBAR_IN22 { + pinmux = <0x401f80a4 1 0x401f8638 0 0x401f8294>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_csi_data16: IOMUXC_GPIO_EMC_37_CSI_DATA16 { + pinmux = <0x401f80a8 4 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_enet2_rx_en: IOMUXC_GPIO_EMC_37_ENET2_RX_EN { + pinmux = <0x401f80a8 8 0x401f871c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_flexcan3_rx: IOMUXC_GPIO_EMC_37_FLEXCAN3_RX { + pinmux = <0x401f80a8 9 0x401f878c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio3_io23: IOMUXC_GPIO_EMC_37_GPIO3_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpio8_io23: IOMUXC_GPIO_EMC_37_GPIO8_IO23 { + pinmux = <0x401f80a8 5 0x0 0 0x401f8298>; + gpr = <0x400ac070 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_gpt1_compare3: IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 { + pinmux = <0x401f80a8 2 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_sai3_mclk: IOMUXC_GPIO_EMC_37_SAI3_MCLK { + pinmux = <0x401f80a8 3 0x401f8770 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_semc_data15: IOMUXC_GPIO_EMC_37_SEMC_DATA15 { + pinmux = <0x401f80a8 0 0x0 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_usdhc2_wp: IOMUXC_GPIO_EMC_37_USDHC2_WP { + pinmux = <0x401f80a8 6 0x401f8608 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_37_xbar1_xbar_in23: IOMUXC_GPIO_EMC_37_XBAR1_XBAR_IN23 { + pinmux = <0x401f80a8 1 0x401f863c 0 0x401f8298>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_csi_field: IOMUXC_GPIO_EMC_38_CSI_FIELD { + pinmux = <0x401f80ac 4 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_enet2_mdc: IOMUXC_GPIO_EMC_38_ENET2_MDC { + pinmux = <0x401f80ac 8 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_flexpwm1_pwma3: IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA3 { + pinmux = <0x401f80ac 1 0x401f8454 2 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio3_io24: IOMUXC_GPIO_EMC_38_GPIO3_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_gpio8_io24: IOMUXC_GPIO_EMC_38_GPIO8_IO24 { + pinmux = <0x401f80ac 5 0x0 0 0x401f829c>; + gpr = <0x400ac070 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_lpuart8_tx: IOMUXC_GPIO_EMC_38_LPUART8_TX { + pinmux = <0x401f80ac 2 0x401f8564 2 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_sai3_tx_bclk: IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK { + pinmux = <0x401f80ac 3 0x401f8780 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_semc_dm1: IOMUXC_GPIO_EMC_38_SEMC_DM1 { + pinmux = <0x401f80ac 0 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_38_usdhc2_vselect: IOMUXC_GPIO_EMC_38_USDHC2_VSELECT { + pinmux = <0x401f80ac 6 0x0 0 0x401f829c>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_enet2_mdio: IOMUXC_GPIO_EMC_39_ENET2_MDIO { + pinmux = <0x401f80b0 8 0x401f8710 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_flexpwm1_pwmb3: IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB3 { + pinmux = <0x401f80b0 1 0x401f8464 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio3_io25: IOMUXC_GPIO_EMC_39_GPIO3_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_gpio8_io25: IOMUXC_GPIO_EMC_39_GPIO8_IO25 { + pinmux = <0x401f80b0 5 0x0 0 0x401f82a0>; + gpr = <0x400ac070 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_lpuart8_rx: IOMUXC_GPIO_EMC_39_LPUART8_RX { + pinmux = <0x401f80b0 2 0x401f8560 2 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_sai3_tx_sync: IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC { + pinmux = <0x401f80b0 3 0x401f8784 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs: IOMUXC_GPIO_EMC_39_SEMC_DQS { + pinmux = <0x401f80b0 0 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_semc_dqs4: IOMUXC_GPIO_EMC_39_SEMC_DQS4 { + pinmux = <0x401f80b0 9 0x401f8788 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_usdhc2_cd_b: IOMUXC_GPIO_EMC_39_USDHC2_CD_B { + pinmux = <0x401f80b0 6 0x401f85e0 1 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_39_wdog1_b: IOMUXC_GPIO_EMC_39_WDOG1_B { + pinmux = <0x401f80b0 4 0x0 0 0x401f82a0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_enet_mdc: IOMUXC_GPIO_EMC_40_ENET_MDC { + pinmux = <0x401f80b4 4 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio3_io26: IOMUXC_GPIO_EMC_40_GPIO3_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpio8_io26: IOMUXC_GPIO_EMC_40_GPIO8_IO26 { + pinmux = <0x401f80b4 5 0x0 0 0x401f82a4>; + gpr = <0x400ac070 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_gpt2_capture2: IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 { + pinmux = <0x401f80b4 1 0x401f8768 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_lpspi1_pcs2: IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 { + pinmux = <0x401f80b4 2 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_clk5: IOMUXC_GPIO_EMC_40_SEMC_CLK5 { + pinmux = <0x401f80b4 9 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_semc_rdy: IOMUXC_GPIO_EMC_40_SEMC_RDY { + pinmux = <0x401f80b4 0 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usb_otg2_oc: IOMUXC_GPIO_EMC_40_USB_OTG2_OC { + pinmux = <0x401f80b4 3 0x401f85cc 1 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_40_usdhc2_reset_b: IOMUXC_GPIO_EMC_40_USDHC2_RESET_B { + pinmux = <0x401f80b4 6 0x0 0 0x401f82a4>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_enet_mdio: IOMUXC_GPIO_EMC_41_ENET_MDIO { + pinmux = <0x401f80b8 4 0x401f8430 1 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio3_io27: IOMUXC_GPIO_EMC_41_GPIO3_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpio8_io27: IOMUXC_GPIO_EMC_41_GPIO8_IO27 { + pinmux = <0x401f80b8 5 0x0 0 0x401f82a8>; + gpr = <0x400ac070 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_gpt2_capture1: IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 { + pinmux = <0x401f80b8 1 0x401f8764 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_lpspi1_pcs3: IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 { + pinmux = <0x401f80b8 2 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_semc_csx0: IOMUXC_GPIO_EMC_41_SEMC_CSX0 { + pinmux = <0x401f80b8 0 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usb_otg2_pwr: IOMUXC_GPIO_EMC_41_USB_OTG2_PWR { + pinmux = <0x401f80b8 3 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_41_usdhc1_vselect: IOMUXC_GPIO_EMC_41_USDHC1_VSELECT { + pinmux = <0x401f80b8 6 0x0 0 0x401f82a8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_enet2_tx_en: IOMUXC_GPIO_SD_B0_00_ENET2_TX_EN { + pinmux = <0x401f81bc 8 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexpwm1_pwma0: IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA0 { + pinmux = <0x401f81bc 1 0x401f8458 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B { + pinmux = <0x401f81bc 6 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio3_io12: IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_gpio8_io12: IOMUXC_GPIO_SD_B0_00_GPIO8_IO12 { + pinmux = <0x401f81bc 5 0x0 0 0x401f83ac>; + gpr = <0x400ac070 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpi2c3_scl: IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL { + pinmux = <0x401f81bc 2 0x401f84dc 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_lpspi1_sck: IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK { + pinmux = <0x401f81bc 4 0x401f84f0 1 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_semc_dqs4: IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 { + pinmux = <0x401f81bc 9 0x401f8788 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_usdhc1_cmd: IOMUXC_GPIO_SD_B0_00_USDHC1_CMD { + pinmux = <0x401f81bc 0 0x0 0 0x401f83ac>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_in04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_IN04 { + pinmux = <0x401f81bc 3 0x401f8614 1 0x401f83ac>; + gpr = <0x400ac018 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_00_xbar1_xbar_inout04: IOMUXC_GPIO_SD_B0_00_XBAR1_XBAR_INOUT04 { + pinmux = <0x401f81bc 3 0x401f8614 1 0x401f83ac>; + gpr = <0x400ac018 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_enet2_ref_clk2: IOMUXC_GPIO_SD_B0_01_ENET2_REF_CLK2 { + pinmux = <0x401f81c0 9 0x401f870c 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_enet2_tx_clk: IOMUXC_GPIO_SD_B0_01_ENET2_TX_CLK { + pinmux = <0x401f81c0 8 0x401f8728 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexpwm1_pwmb0: IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB0 { + pinmux = <0x401f81c0 1 0x401f8468 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_flexspi_b_ss1_b: IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B { + pinmux = <0x401f81c0 6 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio3_io13: IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_gpio8_io13: IOMUXC_GPIO_SD_B0_01_GPIO8_IO13 { + pinmux = <0x401f81c0 5 0x0 0 0x401f83b0>; + gpr = <0x400ac070 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpi2c3_sda: IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA { + pinmux = <0x401f81c0 2 0x401f84e0 1 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_lpspi1_pcs0: IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 { + pinmux = <0x401f81c0 4 0x401f84ec 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_usdhc1_clk: IOMUXC_GPIO_SD_B0_01_USDHC1_CLK { + pinmux = <0x401f81c0 0 0x0 0 0x401f83b0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_in05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_IN05 { + pinmux = <0x401f81c0 3 0x401f8618 1 0x401f83b0>; + gpr = <0x400ac018 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_01_xbar1_xbar_inout05: IOMUXC_GPIO_SD_B0_01_XBAR1_XBAR_INOUT05 { + pinmux = <0x401f81c0 3 0x401f8618 1 0x401f83b0>; + gpr = <0x400ac018 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_enet2_rx_er: IOMUXC_GPIO_SD_B0_02_ENET2_RX_ER { + pinmux = <0x401f81c4 8 0x401f8720 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_flexpwm1_pwma1: IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA1 { + pinmux = <0x401f81c4 1 0x401f845c 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio3_io14: IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_gpio8_io14: IOMUXC_GPIO_SD_B0_02_GPIO8_IO14 { + pinmux = <0x401f81c4 5 0x0 0 0x401f83b4>; + gpr = <0x400ac070 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpspi1_sdo: IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO { + pinmux = <0x401f81c4 4 0x401f84f8 1 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_lpuart8_cts_b: IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B { + pinmux = <0x401f81c4 2 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_semc_clk5: IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 { + pinmux = <0x401f81c4 9 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_usdhc1_data0: IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 { + pinmux = <0x401f81c4 0 0x0 0 0x401f83b4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_in06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_IN06 { + pinmux = <0x401f81c4 3 0x401f861c 1 0x401f83b4>; + gpr = <0x400ac018 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_02_xbar1_xbar_inout06: IOMUXC_GPIO_SD_B0_02_XBAR1_XBAR_INOUT06 { + pinmux = <0x401f81c4 3 0x401f861c 1 0x401f83b4>; + gpr = <0x400ac018 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_enet2_rx_data0: IOMUXC_GPIO_SD_B0_03_ENET2_RX_DATA0 { + pinmux = <0x401f81c8 8 0x401f8714 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_flexpwm1_pwmb1: IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB1 { + pinmux = <0x401f81c8 1 0x401f846c 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio3_io15: IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_gpio8_io15: IOMUXC_GPIO_SD_B0_03_GPIO8_IO15 { + pinmux = <0x401f81c8 5 0x0 0 0x401f83b8>; + gpr = <0x400ac070 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpspi1_sdi: IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI { + pinmux = <0x401f81c8 4 0x401f84f4 1 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_lpuart8_rts_b: IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B { + pinmux = <0x401f81c8 2 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_semc_clk6: IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 { + pinmux = <0x401f81c8 9 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_usdhc1_data1: IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 { + pinmux = <0x401f81c8 0 0x0 0 0x401f83b8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_in07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_IN07 { + pinmux = <0x401f81c8 3 0x401f8620 1 0x401f83b8>; + gpr = <0x400ac018 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_03_xbar1_xbar_inout07: IOMUXC_GPIO_SD_B0_03_XBAR1_XBAR_INOUT07 { + pinmux = <0x401f81c8 3 0x401f8620 1 0x401f83b8>; + gpr = <0x400ac018 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_ccm_clko1: IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 { + pinmux = <0x401f81cc 6 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_enet2_rx_data1: IOMUXC_GPIO_SD_B0_04_ENET2_RX_DATA1 { + pinmux = <0x401f81cc 8 0x401f8718 1 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexpwm1_pwma2: IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA2 { + pinmux = <0x401f81cc 1 0x401f8460 1 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B { + pinmux = <0x401f81cc 4 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio3_io16: IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_gpio8_io16: IOMUXC_GPIO_SD_B0_04_GPIO8_IO16 { + pinmux = <0x401f81cc 5 0x0 0 0x401f83bc>; + gpr = <0x400ac070 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_lpuart8_tx: IOMUXC_GPIO_SD_B0_04_LPUART8_TX { + pinmux = <0x401f81cc 2 0x401f8564 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_usdhc1_data2: IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 { + pinmux = <0x401f81cc 0 0x0 0 0x401f83bc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_in08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_IN08 { + pinmux = <0x401f81cc 3 0x401f8624 1 0x401f83bc>; + gpr = <0x400ac018 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_04_xbar1_xbar_inout08: IOMUXC_GPIO_SD_B0_04_XBAR1_XBAR_INOUT08 { + pinmux = <0x401f81cc 3 0x401f8624 1 0x401f83bc>; + gpr = <0x400ac018 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_ccm_clko2: IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 { + pinmux = <0x401f81d0 6 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_enet2_rx_en: IOMUXC_GPIO_SD_B0_05_ENET2_RX_EN { + pinmux = <0x401f81d0 8 0x401f871c 1 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexpwm1_pwmb2: IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB2 { + pinmux = <0x401f81d0 1 0x401f8470 1 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_flexspi_b_dqs: IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS { + pinmux = <0x401f81d0 4 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio3_io17: IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_gpio8_io17: IOMUXC_GPIO_SD_B0_05_GPIO8_IO17 { + pinmux = <0x401f81d0 5 0x0 0 0x401f83c0>; + gpr = <0x400ac070 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_lpuart8_rx: IOMUXC_GPIO_SD_B0_05_LPUART8_RX { + pinmux = <0x401f81d0 2 0x401f8560 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_usdhc1_data3: IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 { + pinmux = <0x401f81d0 0 0x0 0 0x401f83c0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_in09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_IN09 { + pinmux = <0x401f81d0 3 0x401f8628 1 0x401f83c0>; + gpr = <0x400ac018 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b0_05_xbar1_xbar_inout09: IOMUXC_GPIO_SD_B0_05_XBAR1_XBAR_INOUT09 { + pinmux = <0x401f81d0 3 0x401f8628 1 0x401f83c0>; + gpr = <0x400ac018 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexpwm1_pwma3: IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA3 { + pinmux = <0x401f81d4 2 0x401f8454 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi_b_data3: IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 { + pinmux = <0x401f81d4 1 0x401f84c4 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio3_io00: IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio8_io00: IOMUXC_GPIO_SD_B1_00_GPIO8_IO00 { + pinmux = <0x401f81d4 5 0x0 0 0x401f83c4>; + gpr = <0x400ac070 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_lpuart4_tx: IOMUXC_GPIO_SD_B1_00_LPUART4_TX { + pinmux = <0x401f81d4 4 0x401f8544 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai1_tx_data3: IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA3 { + pinmux = <0x401f81d4 3 0x401f8598 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_sai3_rx_data: IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA { + pinmux = <0x401f81d4 8 0x401f8778 1 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc2_data3: IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 { + pinmux = <0x401f81d4 0 0x401f85f4 0 0x401f83c4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexpwm1_pwmb3: IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB3 { + pinmux = <0x401f81d8 2 0x401f8464 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi_b_data2: IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 { + pinmux = <0x401f81d8 1 0x401f84c0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio3_io01: IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio8_io01: IOMUXC_GPIO_SD_B1_01_GPIO8_IO01 { + pinmux = <0x401f81d8 5 0x0 0 0x401f83c8>; + gpr = <0x400ac070 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_lpuart4_rx: IOMUXC_GPIO_SD_B1_01_LPUART4_RX { + pinmux = <0x401f81d8 4 0x401f8540 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai1_tx_data2: IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA2 { + pinmux = <0x401f81d8 3 0x401f859c 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_sai3_tx_data: IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA { + pinmux = <0x401f81d8 8 0x0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc2_data2: IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 { + pinmux = <0x401f81d8 0 0x401f85f0 0 0x401f83c8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_ccm_wait: IOMUXC_GPIO_SD_B1_02_CCM_WAIT { + pinmux = <0x401f81dc 6 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexcan1_tx: IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX { + pinmux = <0x401f81dc 4 0x0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexpwm2_pwma3: IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA3 { + pinmux = <0x401f81dc 2 0x401f8474 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi_b_data1: IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 { + pinmux = <0x401f81dc 1 0x401f84bc 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio3_io02: IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio8_io02: IOMUXC_GPIO_SD_B1_02_GPIO8_IO02 { + pinmux = <0x401f81dc 5 0x0 0 0x401f83cc>; + gpr = <0x400ac070 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai1_tx_data1: IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA1 { + pinmux = <0x401f81dc 3 0x401f85a0 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_sai3_tx_sync: IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC { + pinmux = <0x401f81dc 8 0x401f8784 1 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc2_data1: IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 { + pinmux = <0x401f81dc 0 0x401f85ec 0 0x401f83cc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_ccm_pmic_rdy: IOMUXC_GPIO_SD_B1_03_CCM_PMIC_RDY { + pinmux = <0x401f81e0 6 0x401f83fc 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexcan1_rx: IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX { + pinmux = <0x401f81e0 4 0x401f844c 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexpwm2_pwmb3: IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB3 { + pinmux = <0x401f81e0 2 0x401f8484 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi_b_data0: IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 { + pinmux = <0x401f81e0 1 0x401f84b8 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio3_io03: IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio8_io03: IOMUXC_GPIO_SD_B1_03_GPIO8_IO03 { + pinmux = <0x401f81e0 5 0x0 0 0x401f83d0>; + gpr = <0x400ac070 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai1_mclk: IOMUXC_GPIO_SD_B1_03_SAI1_MCLK { + pinmux = <0x401f81e0 3 0x401f858c 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_sai3_tx_bclk: IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK { + pinmux = <0x401f81e0 8 0x401f8780 1 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc2_data0: IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 { + pinmux = <0x401f81e0 0 0x401f85e8 0 0x401f83d0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_ccm_stop: IOMUXC_GPIO_SD_B1_04_CCM_STOP { + pinmux = <0x401f81e4 6 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_a_ss1_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI_A_SS1_B { + pinmux = <0x401f81e4 4 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi_b_sclk: IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK { + pinmux = <0x401f81e4 1 0x0 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio3_io04: IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio8_io04: IOMUXC_GPIO_SD_B1_04_GPIO8_IO04 { + pinmux = <0x401f81e4 5 0x0 0 0x401f83d4>; + gpr = <0x400ac070 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_lpi2c1_scl: IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL { + pinmux = <0x401f81e4 2 0x401f84cc 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai1_rx_sync: IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC { + pinmux = <0x401f81e4 3 0x401f85a4 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_sai3_mclk: IOMUXC_GPIO_SD_B1_04_SAI3_MCLK { + pinmux = <0x401f81e4 8 0x401f8770 1 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc2_clk: IOMUXC_GPIO_SD_B1_04_USDHC2_CLK { + pinmux = <0x401f81e4 0 0x401f85dc 0 0x401f83d4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_a_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS { + pinmux = <0x401f81e8 1 0x401f84a4 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi_b_ss0_b: IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B { + pinmux = <0x401f81e8 4 0x0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio3_io05: IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio8_io05: IOMUXC_GPIO_SD_B1_05_GPIO8_IO05 { + pinmux = <0x401f81e8 5 0x0 0 0x401f83d8>; + gpr = <0x400ac070 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_lpi2c1_sda: IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA { + pinmux = <0x401f81e8 2 0x401f84d0 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai1_rx_bclk: IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK { + pinmux = <0x401f81e8 3 0x401f8590 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_sai3_rx_sync: IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC { + pinmux = <0x401f81e8 8 0x401f877c 1 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc2_cmd: IOMUXC_GPIO_SD_B1_05_USDHC2_CMD { + pinmux = <0x401f81e8 0 0x401f85e4 0 0x401f83d8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b: IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B { + pinmux = <0x401f81ec 1 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio3_io06: IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_gpio8_io06: IOMUXC_GPIO_SD_B1_06_GPIO8_IO06 { + pinmux = <0x401f81ec 5 0x0 0 0x401f83dc>; + gpr = <0x400ac070 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpspi2_pcs0: IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 { + pinmux = <0x401f81ec 4 0x401f84fc 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_lpuart7_cts_b: IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B { + pinmux = <0x401f81ec 2 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai1_rx_data0: IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA0 { + pinmux = <0x401f81ec 3 0x401f8594 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_sai3_rx_bclk: IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK { + pinmux = <0x401f81ec 8 0x401f8774 1 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B { + pinmux = <0x401f81ec 0 0x0 0 0x401f83dc>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_flexspi_a_sclk: IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK { + pinmux = <0x401f81f0 1 0x401f84c8 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio3_io07: IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_gpio8_io07: IOMUXC_GPIO_SD_B1_07_GPIO8_IO07 { + pinmux = <0x401f81f0 5 0x0 0 0x401f83e0>; + gpr = <0x400ac070 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpspi2_sck: IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK { + pinmux = <0x401f81f0 4 0x401f8500 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_lpuart7_rts_b: IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B { + pinmux = <0x401f81f0 2 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_sai1_tx_data0: IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA0 { + pinmux = <0x401f81f0 3 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_07_semc_csx1: IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 { + pinmux = <0x401f81f0 0 0x0 0 0x401f83e0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_flexspi_a_data0: IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 { + pinmux = <0x401f81f4 1 0x401f84a8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio3_io08: IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_gpio8_io08: IOMUXC_GPIO_SD_B1_08_GPIO8_IO08 { + pinmux = <0x401f81f4 5 0x0 0 0x401f83e4>; + gpr = <0x400ac070 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpspi2_sdo: IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO { + pinmux = <0x401f81f4 4 0x401f8508 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_lpuart7_tx: IOMUXC_GPIO_SD_B1_08_LPUART7_TX { + pinmux = <0x401f81f4 2 0x401f855c 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_sai1_tx_bclk: IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK { + pinmux = <0x401f81f4 3 0x401f85a8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_semc_csx2: IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 { + pinmux = <0x401f81f4 6 0x0 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_08_usdhc2_data4: IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 { + pinmux = <0x401f81f4 0 0x401f85f8 0 0x401f83e4>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_flexspi_a_data1: IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 { + pinmux = <0x401f81f8 1 0x401f84ac 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio3_io09: IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_gpio8_io09: IOMUXC_GPIO_SD_B1_09_GPIO8_IO09 { + pinmux = <0x401f81f8 5 0x0 0 0x401f83e8>; + gpr = <0x400ac070 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpspi2_sdi: IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI { + pinmux = <0x401f81f8 4 0x401f8504 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_lpuart7_rx: IOMUXC_GPIO_SD_B1_09_LPUART7_RX { + pinmux = <0x401f81f8 2 0x401f8558 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_sai1_tx_sync: IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC { + pinmux = <0x401f81f8 3 0x401f85ac 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_09_usdhc2_data5: IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 { + pinmux = <0x401f81f8 0 0x401f85fc 0 0x401f83e8>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_flexspi_a_data2: IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 { + pinmux = <0x401f81fc 1 0x401f84b0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio3_io10: IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_gpio8_io10: IOMUXC_GPIO_SD_B1_10_GPIO8_IO10 { + pinmux = <0x401f81fc 5 0x0 0 0x401f83ec>; + gpr = <0x400ac070 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpi2c2_sda: IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA { + pinmux = <0x401f81fc 3 0x401f84d8 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpspi2_pcs2: IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 { + pinmux = <0x401f81fc 4 0x0 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_lpuart2_rx: IOMUXC_GPIO_SD_B1_10_LPUART2_RX { + pinmux = <0x401f81fc 2 0x401f852c 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_10_usdhc2_data6: IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 { + pinmux = <0x401f81fc 0 0x401f8600 0 0x401f83ec>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_flexspi_a_data3: IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 { + pinmux = <0x401f8200 1 0x401f84b4 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio3_io11: IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_gpio8_io11: IOMUXC_GPIO_SD_B1_11_GPIO8_IO11 { + pinmux = <0x401f8200 5 0x0 0 0x401f83f0>; + gpr = <0x400ac070 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpi2c2_scl: IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL { + pinmux = <0x401f8200 3 0x401f84d4 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpspi2_pcs3: IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 { + pinmux = <0x401f8200 4 0x0 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_lpuart2_tx: IOMUXC_GPIO_SD_B1_11_LPUART2_TX { + pinmux = <0x401f8200 2 0x401f8530 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_11_usdhc2_data7: IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 { + pinmux = <0x401f8200 0 0x401f8604 0 0x401f83f0>; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_src_reset_b: IOMUXC_SNVS_ONOFF_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x400a8014>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_gpio5_io01: IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 { + pinmux = <0x400a8004 5 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_snvs_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ { + pinmux = <0x400a8004 0 0x0 0 0x400a801c>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_ccm_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ { + pinmux = <0x400a8008 0 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_gpio5_io02: IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 { + pinmux = <0x400a8008 5 0x0 0 0x400a8020>; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_src_por_b: IOMUXC_SNVS_POR_B_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x400a8010>; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_test_mode: IOMUXC_SNVS_TEST_MODE_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x400a800c>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_arm_nmi: IOMUXC_SNVS_WAKEUP_ARM_NMI { + pinmux = <0x400a8000 7 0x0 0 0x400a8018>; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_gpio5_io00: IOMUXC_SNVS_WAKEUP_GPIO5_IO00 { + pinmux = <0x400a8000 5 0x0 0 0x400a8018>; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1165cvm5a-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1165cvm5a-pinctrl.dtsi new file mode 100644 index 000000000..35d40a81d --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1165cvm5a-pinctrl.dtsi @@ -0,0 +1,5984 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1165CVM5A + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_00_acmp1_in1: IOMUXC_GPIO_AD_00_ACMP1_IN1 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_can2_tx: IOMUXC_GPIO_AD_00_CAN2_TX { + pinmux = <0x400e810c 1 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_enet_1g_1588_event1_in: IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN { + pinmux = <0x400e810c 2 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexio2_flexio00: IOMUXC_GPIO_AD_00_FLEXIO2_FLEXIO00 { + pinmux = <0x400e810c 8 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexpwm1_pwm0_a: IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A { + pinmux = <0x400e810c 4 0x400e8500 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexspi2_b_ss1_b: IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B { + pinmux = <0x400e810c 9 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio8_io31: IOMUXC_GPIO_AD_00_GPIO8_IO31 { + pinmux = <0x400e810c 10 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31_cm7: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31_CM7 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpt2_capture1: IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 { + pinmux = <0x400e810c 3 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_lpuart7_tx: IOMUXC_GPIO_AD_00_LPUART7_TX { + pinmux = <0x400e810c 6 0x400e8630 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_sim1_trxd: IOMUXC_GPIO_AD_00_SIM1_TRXD { + pinmux = <0x400e810c 0 0x400e869c 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_acmp1_in2: IOMUXC_GPIO_AD_01_ACMP1_IN2 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_can2_rx: IOMUXC_GPIO_AD_01_CAN2_RX { + pinmux = <0x400e8110 1 0x400e849c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_enet_1g_1588_event1_out: IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT { + pinmux = <0x400e8110 2 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexio2_flexio01: IOMUXC_GPIO_AD_01_FLEXIO2_FLEXIO01 { + pinmux = <0x400e8110 8 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexpwm1_pwm0_b: IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B { + pinmux = <0x400e8110 4 0x400e850c 1 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexspi2_a_ss1_b: IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B { + pinmux = <0x400e8110 9 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio9_io00: IOMUXC_GPIO_AD_01_GPIO9_IO00 { + pinmux = <0x400e8110 10 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00_cm7: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00_CM7 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpt2_capture2: IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 { + pinmux = <0x400e8110 3 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_lpuart7_rx: IOMUXC_GPIO_AD_01_LPUART7_RX { + pinmux = <0x400e8110 6 0x400e862c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_sim1_clk: IOMUXC_GPIO_AD_01_SIM1_CLK { + pinmux = <0x400e8110 0 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_acmp1_in3: IOMUXC_GPIO_AD_02_ACMP1_IN3 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_enet_1g_1588_event2_in: IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN { + pinmux = <0x400e8114 2 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexio2_flexio02: IOMUXC_GPIO_AD_02_FLEXIO2_FLEXIO02 { + pinmux = <0x400e8114 8 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexpwm1_pwm1_a: IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A { + pinmux = <0x400e8114 4 0x400e8504 1 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio9_io01: IOMUXC_GPIO_AD_02_GPIO9_IO01 { + pinmux = <0x400e8114 10 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01_cm7: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01_CM7 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpt2_compare1: IOMUXC_GPIO_AD_02_GPT2_COMPARE1 { + pinmux = <0x400e8114 3 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart7_cts_b: IOMUXC_GPIO_AD_02_LPUART7_CTS_B { + pinmux = <0x400e8114 1 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart8_tx: IOMUXC_GPIO_AD_02_LPUART8_TX { + pinmux = <0x400e8114 6 0x400e8638 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_sim1_rst_b: IOMUXC_GPIO_AD_02_SIM1_RST_B { + pinmux = <0x400e8114 0 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_video_mux_ext_dcic1: IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e8114 9 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_acmp1_in4: IOMUXC_GPIO_AD_03_ACMP1_IN4 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_enet_1g_1588_event2_out: IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT { + pinmux = <0x400e8118 2 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexio2_flexio03: IOMUXC_GPIO_AD_03_FLEXIO2_FLEXIO03 { + pinmux = <0x400e8118 8 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexpwm1_pwm1_b: IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B { + pinmux = <0x400e8118 4 0x400e8510 1 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio9_io02: IOMUXC_GPIO_AD_03_GPIO9_IO02 { + pinmux = <0x400e8118 10 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02_cm7: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02_CM7 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpt2_compare2: IOMUXC_GPIO_AD_03_GPT2_COMPARE2 { + pinmux = <0x400e8118 3 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart7_rts_b: IOMUXC_GPIO_AD_03_LPUART7_RTS_B { + pinmux = <0x400e8118 1 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart8_rx: IOMUXC_GPIO_AD_03_LPUART8_RX { + pinmux = <0x400e8118 6 0x400e8634 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_sim1_sven: IOMUXC_GPIO_AD_03_SIM1_SVEN { + pinmux = <0x400e8118 0 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_video_mux_ext_dcic2: IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8118 9 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_acmp2_in1: IOMUXC_GPIO_AD_04_ACMP2_IN1 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_enet_1g_1588_event3_in: IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN { + pinmux = <0x400e811c 2 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexio2_flexio04: IOMUXC_GPIO_AD_04_FLEXIO2_FLEXIO04 { + pinmux = <0x400e811c 8 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexpwm1_pwm2_a: IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A { + pinmux = <0x400e811c 4 0x400e8508 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio9_io03: IOMUXC_GPIO_AD_04_GPIO9_IO03 { + pinmux = <0x400e811c 10 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03_cm7: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03_CM7 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpt2_compare3: IOMUXC_GPIO_AD_04_GPT2_COMPARE3 { + pinmux = <0x400e811c 3 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_lpuart8_cts_b: IOMUXC_GPIO_AD_04_LPUART8_CTS_B { + pinmux = <0x400e811c 1 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_qtimer4_timer0: IOMUXC_GPIO_AD_04_QTIMER4_TIMER0 { + pinmux = <0x400e811c 9 0x400e8660 1 0x400e8360>; + pin-pue; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_sim1_pd: IOMUXC_GPIO_AD_04_SIM1_PD { + pinmux = <0x400e811c 0 0x400e86a0 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_wdog1_wdog_b: IOMUXC_GPIO_AD_04_WDOG1_WDOG_B { + pinmux = <0x400e811c 6 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_acmp2_in2: IOMUXC_GPIO_AD_05_ACMP2_IN2 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_enet_1g_1588_event3_out: IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT { + pinmux = <0x400e8120 2 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexio2_flexio05: IOMUXC_GPIO_AD_05_FLEXIO2_FLEXIO05 { + pinmux = <0x400e8120 8 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexpwm1_pwm2_b: IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B { + pinmux = <0x400e8120 4 0x400e8514 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio9_io04: IOMUXC_GPIO_AD_05_GPIO9_IO04 { + pinmux = <0x400e8120 10 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04_cm7: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04_CM7 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpt2_clk: IOMUXC_GPIO_AD_05_GPT2_CLK { + pinmux = <0x400e8120 3 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_lpuart8_rts_b: IOMUXC_GPIO_AD_05_LPUART8_RTS_B { + pinmux = <0x400e8120 1 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_qtimer4_timer1: IOMUXC_GPIO_AD_05_QTIMER4_TIMER1 { + pinmux = <0x400e8120 9 0x400e8664 1 0x400e8364>; + pin-pue; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_sim1_power_fail: IOMUXC_GPIO_AD_05_SIM1_POWER_FAIL { + pinmux = <0x400e8120 0 0x400e86a4 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_wdog2_wdog_b: IOMUXC_GPIO_AD_05_WDOG2_WDOG_B { + pinmux = <0x400e8120 6 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_adc1_ch0a: IOMUXC_GPIO_AD_06_ADC1_CH0A { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_can1_tx: IOMUXC_GPIO_AD_06_CAN1_TX { + pinmux = <0x400e8124 1 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_enet_1588_event1_in: IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN { + pinmux = <0x400e8124 6 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexio2_flexio06: IOMUXC_GPIO_AD_06_FLEXIO2_FLEXIO06 { + pinmux = <0x400e8124 8 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexpwm1_pwm0_x: IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X { + pinmux = <0x400e8124 11 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio9_io05: IOMUXC_GPIO_AD_06_GPIO9_IO05 { + pinmux = <0x400e8124 10 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05_cm7: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05_CM7 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpt3_capture1: IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 { + pinmux = <0x400e8124 3 0x400e8590 1 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_qtimer4_timer2: IOMUXC_GPIO_AD_06_QTIMER4_TIMER2 { + pinmux = <0x400e8124 9 0x400e8668 0 0x400e8368>; + pin-pue; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_sim2_trxd: IOMUXC_GPIO_AD_06_SIM2_TRXD { + pinmux = <0x400e8124 2 0x400e86a8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_usb_otg2_oc: IOMUXC_GPIO_AD_06_USB_OTG2_OC { + pinmux = <0x400e8124 0 0x400e86b8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_adc1_ch0b: IOMUXC_GPIO_AD_07_ADC1_CH0B { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_can1_rx: IOMUXC_GPIO_AD_07_CAN1_RX { + pinmux = <0x400e8128 1 0x400e8498 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_enet_1588_event1_out: IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT { + pinmux = <0x400e8128 6 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexio2_flexio07: IOMUXC_GPIO_AD_07_FLEXIO2_FLEXIO07 { + pinmux = <0x400e8128 8 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexpwm1_pwm1_x: IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X { + pinmux = <0x400e8128 11 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio9_io06: IOMUXC_GPIO_AD_07_GPIO9_IO06 { + pinmux = <0x400e8128 10 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06_cm7: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06_CM7 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpt3_capture2: IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 { + pinmux = <0x400e8128 3 0x400e8594 1 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_qtimer4_timer3: IOMUXC_GPIO_AD_07_QTIMER4_TIMER3 { + pinmux = <0x400e8128 9 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e403c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_sim2_clk: IOMUXC_GPIO_AD_07_SIM2_CLK { + pinmux = <0x400e8128 2 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_usb_otg2_pwr: IOMUXC_GPIO_AD_07_USB_OTG2_PWR { + pinmux = <0x400e8128 0 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_adc1_ch1a: IOMUXC_GPIO_AD_08_ADC1_CH1A { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_enet_1588_event2_in: IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN { + pinmux = <0x400e812c 6 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexio2_flexio08: IOMUXC_GPIO_AD_08_FLEXIO2_FLEXIO08 { + pinmux = <0x400e812c 8 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexpwm1_pwm2_x: IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X { + pinmux = <0x400e812c 11 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio9_io07: IOMUXC_GPIO_AD_08_GPIO9_IO07 { + pinmux = <0x400e812c 10 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07_cm7: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07_CM7 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpt3_compare1: IOMUXC_GPIO_AD_08_GPT3_COMPARE1 { + pinmux = <0x400e812c 3 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_lpi2c1_scl: IOMUXC_GPIO_AD_08_LPI2C1_SCL { + pinmux = <0x400e812c 1 0x400e85ac 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_sim2_rst_b: IOMUXC_GPIO_AD_08_SIM2_RST_B { + pinmux = <0x400e812c 2 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_usbphy2_otg_id: IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID { + pinmux = <0x400e812c 0 0x400e86c4 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_adc1_ch1b: IOMUXC_GPIO_AD_09_ADC1_CH1B { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_enet_1588_event2_out: IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT { + pinmux = <0x400e8130 6 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexio2_flexio09: IOMUXC_GPIO_AD_09_FLEXIO2_FLEXIO09 { + pinmux = <0x400e8130 8 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexpwm1_pwm3_x: IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X { + pinmux = <0x400e8130 11 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio9_io08: IOMUXC_GPIO_AD_09_GPIO9_IO08 { + pinmux = <0x400e8130 10 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08_cm7: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08_CM7 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpt3_compare2: IOMUXC_GPIO_AD_09_GPT3_COMPARE2 { + pinmux = <0x400e8130 3 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_lpi2c1_sda: IOMUXC_GPIO_AD_09_LPI2C1_SDA { + pinmux = <0x400e8130 1 0x400e85b0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_sim2_sven: IOMUXC_GPIO_AD_09_SIM2_SVEN { + pinmux = <0x400e8130 2 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_usbphy1_otg_id: IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID { + pinmux = <0x400e8130 0 0x400e86c0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_adc1_ch2a: IOMUXC_GPIO_AD_10_ADC1_CH2A { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_enet_1588_event3_in: IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN { + pinmux = <0x400e8134 6 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexio2_flexio10: IOMUXC_GPIO_AD_10_FLEXIO2_FLEXIO10 { + pinmux = <0x400e8134 8 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexpwm2_pwm0_x: IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X { + pinmux = <0x400e8134 11 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio9_io09: IOMUXC_GPIO_AD_10_GPIO9_IO09 { + pinmux = <0x400e8134 10 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09_cm7: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09_CM7 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpt3_compare3: IOMUXC_GPIO_AD_10_GPT3_COMPARE3 { + pinmux = <0x400e8134 3 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_lpi2c1_scls: IOMUXC_GPIO_AD_10_LPI2C1_SCLS { + pinmux = <0x400e8134 1 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_sim2_pd: IOMUXC_GPIO_AD_10_SIM2_PD { + pinmux = <0x400e8134 2 0x400e86ac 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_usb_otg1_pwr: IOMUXC_GPIO_AD_10_USB_OTG1_PWR { + pinmux = <0x400e8134 0 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_adc1_ch2b: IOMUXC_GPIO_AD_11_ADC1_CH2B { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_enet_1588_event3_out: IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT { + pinmux = <0x400e8138 6 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexio2_flexio11: IOMUXC_GPIO_AD_11_FLEXIO2_FLEXIO11 { + pinmux = <0x400e8138 8 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexpwm2_pwm1_x: IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X { + pinmux = <0x400e8138 11 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio9_io10: IOMUXC_GPIO_AD_11_GPIO9_IO10 { + pinmux = <0x400e8138 10 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10_cm7: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10_CM7 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpt3_clk: IOMUXC_GPIO_AD_11_GPT3_CLK { + pinmux = <0x400e8138 3 0x400e8598 1 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_lpi2c1_sdas: IOMUXC_GPIO_AD_11_LPI2C1_SDAS { + pinmux = <0x400e8138 1 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_sim2_power_fail: IOMUXC_GPIO_AD_11_SIM2_POWER_FAIL { + pinmux = <0x400e8138 2 0x400e86b0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_usb_otg1_oc: IOMUXC_GPIO_AD_11_USB_OTG1_OC { + pinmux = <0x400e8138 0 0x400e86bc 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc1_ch3a: IOMUXC_GPIO_AD_12_ADC1_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc2_ch3a: IOMUXC_GPIO_AD_12_ADC2_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_enet_tdata03: IOMUXC_GPIO_AD_12_ENET_TDATA03 { + pinmux = <0x400e813c 6 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_ewm_ewm_out_b: IOMUXC_GPIO_AD_12_EWM_EWM_OUT_B { + pinmux = <0x400e813c 9 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexio2_flexio12: IOMUXC_GPIO_AD_12_FLEXIO2_FLEXIO12 { + pinmux = <0x400e813c 8 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexpwm2_pwm2_x: IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X { + pinmux = <0x400e813c 11 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexspi1_b_data03: IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 { + pinmux = <0x400e813c 3 0x400e8570 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio9_io11: IOMUXC_GPIO_AD_12_GPIO9_IO11 { + pinmux = <0x400e813c 10 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11_cm7: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11_CM7 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpt1_capture1: IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 { + pinmux = <0x400e813c 2 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_lpi2c1_hreq: IOMUXC_GPIO_AD_12_LPI2C1_HREQ { + pinmux = <0x400e813c 1 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_spdif_lock: IOMUXC_GPIO_AD_12_SPDIF_LOCK { + pinmux = <0x400e813c 0 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc1_ch3b: IOMUXC_GPIO_AD_13_ADC1_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc2_ch3b: IOMUXC_GPIO_AD_13_ADC2_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_enet_tdata02: IOMUXC_GPIO_AD_13_ENET_TDATA02 { + pinmux = <0x400e8140 6 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexio2_flexio13: IOMUXC_GPIO_AD_13_FLEXIO2_FLEXIO13 { + pinmux = <0x400e8140 8 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexpwm2_pwm3_x: IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X { + pinmux = <0x400e8140 11 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexspi1_b_data02: IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 { + pinmux = <0x400e8140 3 0x400e856c 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio9_io12: IOMUXC_GPIO_AD_13_GPIO9_IO12 { + pinmux = <0x400e8140 10 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12_cm7: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12_CM7 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpt1_capture2: IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 { + pinmux = <0x400e8140 2 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_pit1_trigger00: IOMUXC_GPIO_AD_13_PIT1_TRIGGER00 { + pinmux = <0x400e8140 1 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_spdif_sr_clk: IOMUXC_GPIO_AD_13_SPDIF_SR_CLK { + pinmux = <0x400e8140 0 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc1_ch4a: IOMUXC_GPIO_AD_14_ADC1_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc2_ch4a: IOMUXC_GPIO_AD_14_ADC2_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_ccm_enet_ref_clk_25m: IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8144 9 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_enet_rx_clk: IOMUXC_GPIO_AD_14_ENET_RX_CLK { + pinmux = <0x400e8144 6 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexio2_flexio14: IOMUXC_GPIO_AD_14_FLEXIO2_FLEXIO14 { + pinmux = <0x400e8144 8 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexpwm3_pwm0_x: IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X { + pinmux = <0x400e8144 11 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexspi1_b_data01: IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 { + pinmux = <0x400e8144 3 0x400e8568 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio9_io13: IOMUXC_GPIO_AD_14_GPIO9_IO13 { + pinmux = <0x400e8144 10 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13_cm7: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13_CM7 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpt1_compare1: IOMUXC_GPIO_AD_14_GPT1_COMPARE1 { + pinmux = <0x400e8144 2 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_spdif_ext_clk: IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK { + pinmux = <0x400e8144 0 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc1_ch4b: IOMUXC_GPIO_AD_15_ADC1_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc2_ch4b: IOMUXC_GPIO_AD_15_ADC2_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_enet_tx_er: IOMUXC_GPIO_AD_15_ENET_TX_ER { + pinmux = <0x400e8148 6 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexio2_flexio15: IOMUXC_GPIO_AD_15_FLEXIO2_FLEXIO15 { + pinmux = <0x400e8148 8 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexpwm3_pwm1_x: IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X { + pinmux = <0x400e8148 11 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexspi1_b_data00: IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 { + pinmux = <0x400e8148 3 0x400e8564 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio9_io14: IOMUXC_GPIO_AD_15_GPIO9_IO14 { + pinmux = <0x400e8148 10 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14_cm7: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14_CM7 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpt1_compare2: IOMUXC_GPIO_AD_15_GPT1_COMPARE2 { + pinmux = <0x400e8148 2 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_lpuart10_tx: IOMUXC_GPIO_AD_15_LPUART10_TX { + pinmux = <0x400e8148 1 0x400e8628 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_spdif_in: IOMUXC_GPIO_AD_15_SPDIF_IN { + pinmux = <0x400e8148 0 0x400e86b4 1 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc1_ch5a: IOMUXC_GPIO_AD_16_ADC1_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc2_ch5a: IOMUXC_GPIO_AD_16_ADC2_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_1g_mdc: IOMUXC_GPIO_AD_16_ENET_1G_MDC { + pinmux = <0x400e814c 9 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_rdata03: IOMUXC_GPIO_AD_16_ENET_RDATA03 { + pinmux = <0x400e814c 6 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexio2_flexio16: IOMUXC_GPIO_AD_16_FLEXIO2_FLEXIO16 { + pinmux = <0x400e814c 8 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexpwm3_pwm2_x: IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X { + pinmux = <0x400e814c 11 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexspi1_b_sclk: IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK { + pinmux = <0x400e814c 3 0x400e8578 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio9_io15: IOMUXC_GPIO_AD_16_GPIO9_IO15 { + pinmux = <0x400e814c 10 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15_cm7: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15_CM7 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpt1_compare3: IOMUXC_GPIO_AD_16_GPT1_COMPARE3 { + pinmux = <0x400e814c 2 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_lpuart10_rx: IOMUXC_GPIO_AD_16_LPUART10_RX { + pinmux = <0x400e814c 1 0x400e8624 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_spdif_out: IOMUXC_GPIO_AD_16_SPDIF_OUT { + pinmux = <0x400e814c 0 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_acmp1_cmpo: IOMUXC_GPIO_AD_17_ACMP1_CMPO { + pinmux = <0x400e8150 1 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc1_ch5b: IOMUXC_GPIO_AD_17_ADC1_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc2_ch5b: IOMUXC_GPIO_AD_17_ADC2_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_1g_mdio: IOMUXC_GPIO_AD_17_ENET_1G_MDIO { + pinmux = <0x400e8150 9 0x400e84c8 2 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_rdata02: IOMUXC_GPIO_AD_17_ENET_RDATA02 { + pinmux = <0x400e8150 6 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexio2_flexio17: IOMUXC_GPIO_AD_17_FLEXIO2_FLEXIO17 { + pinmux = <0x400e8150 8 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexpwm3_pwm3_x: IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X { + pinmux = <0x400e8150 11 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexspi1_a_dqs: IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS { + pinmux = <0x400e8150 3 0x400e8550 1 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio9_io16: IOMUXC_GPIO_AD_17_GPIO9_IO16 { + pinmux = <0x400e8150 10 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16_cm7: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16_CM7 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpt1_clk: IOMUXC_GPIO_AD_17_GPT1_CLK { + pinmux = <0x400e8150 2 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_sai1_mclk: IOMUXC_GPIO_AD_17_SAI1_MCLK { + pinmux = <0x400e8150 0 0x400e866c 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_acmp2_cmpo: IOMUXC_GPIO_AD_18_ACMP2_CMPO { + pinmux = <0x400e8154 1 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_adc2_ch0a: IOMUXC_GPIO_AD_18_ADC2_CH0A { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_enet_crs: IOMUXC_GPIO_AD_18_ENET_CRS { + pinmux = <0x400e8154 6 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexio2_flexio18: IOMUXC_GPIO_AD_18_FLEXIO2_FLEXIO18 { + pinmux = <0x400e8154 8 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexpwm4_pwm0_x: IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X { + pinmux = <0x400e8154 11 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexspi1_a_ss0_b: IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B { + pinmux = <0x400e8154 3 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio9_io17: IOMUXC_GPIO_AD_18_GPIO9_IO17 { + pinmux = <0x400e8154 10 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17_cm7: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17_CM7 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpi2c2_scl: IOMUXC_GPIO_AD_18_LPI2C2_SCL { + pinmux = <0x400e8154 9 0x400e85b4 1 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpspi1_pcs1: IOMUXC_GPIO_AD_18_LPSPI1_PCS1 { + pinmux = <0x400e8154 2 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_sai1_rx_sync: IOMUXC_GPIO_AD_18_SAI1_RX_SYNC { + pinmux = <0x400e8154 0 0x400e8678 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_acmp3_cmpo: IOMUXC_GPIO_AD_19_ACMP3_CMPO { + pinmux = <0x400e8158 1 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_adc2_ch0b: IOMUXC_GPIO_AD_19_ADC2_CH0B { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_enet_col: IOMUXC_GPIO_AD_19_ENET_COL { + pinmux = <0x400e8158 6 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexio2_flexio19: IOMUXC_GPIO_AD_19_FLEXIO2_FLEXIO19 { + pinmux = <0x400e8158 8 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexpwm4_pwm1_x: IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X { + pinmux = <0x400e8158 11 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexspi1_a_sclk: IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK { + pinmux = <0x400e8158 3 0x400e8574 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio9_io18: IOMUXC_GPIO_AD_19_GPIO9_IO18 { + pinmux = <0x400e8158 10 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18_cm7: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18_CM7 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpi2c2_sda: IOMUXC_GPIO_AD_19_LPI2C2_SDA { + pinmux = <0x400e8158 9 0x400e85b8 1 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpspi1_pcs2: IOMUXC_GPIO_AD_19_LPSPI1_PCS2 { + pinmux = <0x400e8158 2 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_sai1_rx_bclk: IOMUXC_GPIO_AD_19_SAI1_RX_BCLK { + pinmux = <0x400e8158 0 0x400e8670 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_acmp4_cmpo: IOMUXC_GPIO_AD_20_ACMP4_CMPO { + pinmux = <0x400e815c 1 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_adc2_ch1a: IOMUXC_GPIO_AD_20_ADC2_CH1A { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexio2_flexio20: IOMUXC_GPIO_AD_20_FLEXIO2_FLEXIO20 { + pinmux = <0x400e815c 8 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexpwm4_pwm2_x: IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X { + pinmux = <0x400e815c 11 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexspi1_a_data00: IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 { + pinmux = <0x400e815c 3 0x400e8554 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio9_io19: IOMUXC_GPIO_AD_20_GPIO9_IO19 { + pinmux = <0x400e815c 10 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19_cm7: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19_CM7 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_kpp_row07: IOMUXC_GPIO_AD_20_KPP_ROW07 { + pinmux = <0x400e815c 6 0x400e85a8 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_lpspi1_pcs3: IOMUXC_GPIO_AD_20_LPSPI1_PCS3 { + pinmux = <0x400e815c 2 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_sai1_rx_data00: IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 { + pinmux = <0x400e815c 0 0x400e8674 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_adc2_ch1b: IOMUXC_GPIO_AD_21_ADC2_CH1B { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexio2_flexio21: IOMUXC_GPIO_AD_21_FLEXIO2_FLEXIO21 { + pinmux = <0x400e8160 8 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexpwm4_pwm3_x: IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X { + pinmux = <0x400e8160 11 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexspi1_a_data01: IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 { + pinmux = <0x400e8160 3 0x400e8558 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio9_io20: IOMUXC_GPIO_AD_21_GPIO9_IO20 { + pinmux = <0x400e8160 10 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20_cm7: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20_CM7 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_kpp_col07: IOMUXC_GPIO_AD_21_KPP_COL07 { + pinmux = <0x400e8160 6 0x400e85a0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_lpspi2_pcs1: IOMUXC_GPIO_AD_21_LPSPI2_PCS1 { + pinmux = <0x400e8160 2 0x400e85e0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_sai1_tx_data00: IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 { + pinmux = <0x400e8160 0 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_adc2_ch2a: IOMUXC_GPIO_AD_22_ADC2_CH2A { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexio2_flexio22: IOMUXC_GPIO_AD_22_FLEXIO2_FLEXIO22 { + pinmux = <0x400e8164 8 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexspi1_a_data02: IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 { + pinmux = <0x400e8164 3 0x400e855c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio9_io21: IOMUXC_GPIO_AD_22_GPIO9_IO21 { + pinmux = <0x400e8164 10 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21_cm7: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21_CM7 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_kpp_row06: IOMUXC_GPIO_AD_22_KPP_ROW06 { + pinmux = <0x400e8164 6 0x400e85a4 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_lpspi2_pcs2: IOMUXC_GPIO_AD_22_LPSPI2_PCS2 { + pinmux = <0x400e8164 2 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_sai1_tx_bclk: IOMUXC_GPIO_AD_22_SAI1_TX_BCLK { + pinmux = <0x400e8164 0 0x400e867c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_adc2_ch2b: IOMUXC_GPIO_AD_23_ADC2_CH2B { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexio2_flexio23: IOMUXC_GPIO_AD_23_FLEXIO2_FLEXIO23 { + pinmux = <0x400e8168 8 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexspi1_a_data03: IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 { + pinmux = <0x400e8168 3 0x400e8560 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio9_io22: IOMUXC_GPIO_AD_23_GPIO9_IO22 { + pinmux = <0x400e8168 10 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22_cm7: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22_CM7 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_kpp_col06: IOMUXC_GPIO_AD_23_KPP_COL06 { + pinmux = <0x400e8168 6 0x400e859c 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_lpspi2_pcs3: IOMUXC_GPIO_AD_23_LPSPI2_PCS3 { + pinmux = <0x400e8168 2 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_sai1_tx_sync: IOMUXC_GPIO_AD_23_SAI1_TX_SYNC { + pinmux = <0x400e8168 0 0x400e8680 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_adc2_ch6a: IOMUXC_GPIO_AD_24_ADC2_CH6A { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_enet_rx_en: IOMUXC_GPIO_AD_24_ENET_RX_EN { + pinmux = <0x400e816c 3 0x400e84b8 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexio2_flexio24: IOMUXC_GPIO_AD_24_FLEXIO2_FLEXIO24 { + pinmux = <0x400e816c 8 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexpwm2_pwm0_a: IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A { + pinmux = <0x400e816c 4 0x400e8518 1 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio9_io23: IOMUXC_GPIO_AD_24_GPIO9_IO23 { + pinmux = <0x400e816c 10 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23_cm7: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23_CM7 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_kpp_row05: IOMUXC_GPIO_AD_24_KPP_ROW05 { + pinmux = <0x400e816c 6 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpi2c4_scl: IOMUXC_GPIO_AD_24_LPI2C4_SCL { + pinmux = <0x400e816c 9 0x400e85c4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpspi2_sck: IOMUXC_GPIO_AD_24_LPSPI2_SCK { + pinmux = <0x400e816c 1 0x400e85e4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpuart1_tx: IOMUXC_GPIO_AD_24_LPUART1_TX { + pinmux = <0x400e816c 0 0x400e8620 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_adc2_ch6b: IOMUXC_GPIO_AD_25_ADC2_CH6B { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_enet_rx_er: IOMUXC_GPIO_AD_25_ENET_RX_ER { + pinmux = <0x400e8170 3 0x400e84bc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexio2_flexio25: IOMUXC_GPIO_AD_25_FLEXIO2_FLEXIO25 { + pinmux = <0x400e8170 8 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexpwm2_pwm0_b: IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B { + pinmux = <0x400e8170 4 0x400e8524 1 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio9_io24: IOMUXC_GPIO_AD_25_GPIO9_IO24 { + pinmux = <0x400e8170 10 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24_cm7: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24_CM7 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_kpp_col05: IOMUXC_GPIO_AD_25_KPP_COL05 { + pinmux = <0x400e8170 6 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpi2c4_sda: IOMUXC_GPIO_AD_25_LPI2C4_SDA { + pinmux = <0x400e8170 9 0x400e85c8 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpspi2_pcs0: IOMUXC_GPIO_AD_25_LPSPI2_PCS0 { + pinmux = <0x400e8170 1 0x400e85dc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpuart1_rx: IOMUXC_GPIO_AD_25_LPUART1_RX { + pinmux = <0x400e8170 0 0x400e861c 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_acmp2_in3: IOMUXC_GPIO_AD_26_ACMP2_IN3 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_enet_rdata00: IOMUXC_GPIO_AD_26_ENET_RDATA00 { + pinmux = <0x400e8174 3 0x400e84b0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexio2_flexio26: IOMUXC_GPIO_AD_26_FLEXIO2_FLEXIO26 { + pinmux = <0x400e8174 8 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexpwm2_pwm1_a: IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A { + pinmux = <0x400e8174 4 0x400e851c 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio9_io25: IOMUXC_GPIO_AD_26_GPIO9_IO25 { + pinmux = <0x400e8174 10 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25_cm7: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25_CM7 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_kpp_row04: IOMUXC_GPIO_AD_26_KPP_ROW04 { + pinmux = <0x400e8174 6 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpspi2_sdo: IOMUXC_GPIO_AD_26_LPSPI2_SDO { + pinmux = <0x400e8174 1 0x400e85ec 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpuart1_cts_b: IOMUXC_GPIO_AD_26_LPUART1_CTS_B { + pinmux = <0x400e8174 0 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_semc_csx01: IOMUXC_GPIO_AD_26_SEMC_CSX01 { + pinmux = <0x400e8174 2 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_usdhc2_cd_b: IOMUXC_GPIO_AD_26_USDHC2_CD_B { + pinmux = <0x400e8174 11 0x400e86d0 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_acmp2_in4: IOMUXC_GPIO_AD_27_ACMP2_IN4 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_enet_rdata01: IOMUXC_GPIO_AD_27_ENET_RDATA01 { + pinmux = <0x400e8178 3 0x400e84b4 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexio2_flexio27: IOMUXC_GPIO_AD_27_FLEXIO2_FLEXIO27 { + pinmux = <0x400e8178 8 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexpwm2_pwm1_b: IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B { + pinmux = <0x400e8178 4 0x400e8528 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio9_io26: IOMUXC_GPIO_AD_27_GPIO9_IO26 { + pinmux = <0x400e8178 10 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26_cm7: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26_CM7 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_kpp_col04: IOMUXC_GPIO_AD_27_KPP_COL04 { + pinmux = <0x400e8178 6 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpspi2_sdi: IOMUXC_GPIO_AD_27_LPSPI2_SDI { + pinmux = <0x400e8178 1 0x400e85e8 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpuart1_rts_b: IOMUXC_GPIO_AD_27_LPUART1_RTS_B { + pinmux = <0x400e8178 0 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_semc_csx02: IOMUXC_GPIO_AD_27_SEMC_CSX02 { + pinmux = <0x400e8178 2 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_usdhc2_wp: IOMUXC_GPIO_AD_27_USDHC2_WP { + pinmux = <0x400e8178 11 0x400e86d4 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_acmp3_in1: IOMUXC_GPIO_AD_28_ACMP3_IN1 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_enet_tx_en: IOMUXC_GPIO_AD_28_ENET_TX_EN { + pinmux = <0x400e817c 3 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexio2_flexio28: IOMUXC_GPIO_AD_28_FLEXIO2_FLEXIO28 { + pinmux = <0x400e817c 8 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexpwm2_pwm2_a: IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A { + pinmux = <0x400e817c 4 0x400e8520 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio9_io27: IOMUXC_GPIO_AD_28_GPIO9_IO27 { + pinmux = <0x400e817c 10 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27_cm7: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27_CM7 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_kpp_row03: IOMUXC_GPIO_AD_28_KPP_ROW03 { + pinmux = <0x400e817c 6 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpspi1_sck: IOMUXC_GPIO_AD_28_LPSPI1_SCK { + pinmux = <0x400e817c 0 0x400e85d0 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpuart5_tx: IOMUXC_GPIO_AD_28_LPUART5_TX { + pinmux = <0x400e817c 1 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_semc_csx03: IOMUXC_GPIO_AD_28_SEMC_CSX03 { + pinmux = <0x400e817c 2 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_usdhc2_vselect: IOMUXC_GPIO_AD_28_USDHC2_VSELECT { + pinmux = <0x400e817c 11 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_video_mux_ext_dcic1: IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e817c 9 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_acmp3_in2: IOMUXC_GPIO_AD_29_ACMP3_IN2 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_ref_clk: IOMUXC_GPIO_AD_29_ENET_REF_CLK { + pinmux = <0x400e8180 2 0x400e84a8 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_tx_clk: IOMUXC_GPIO_AD_29_ENET_TX_CLK { + pinmux = <0x400e8180 3 0x400e84c0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexio2_flexio29: IOMUXC_GPIO_AD_29_FLEXIO2_FLEXIO29 { + pinmux = <0x400e8180 8 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexpwm2_pwm2_b: IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B { + pinmux = <0x400e8180 4 0x400e852c 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio9_io28: IOMUXC_GPIO_AD_29_GPIO9_IO28 { + pinmux = <0x400e8180 10 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28_cm7: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28_CM7 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_kpp_col03: IOMUXC_GPIO_AD_29_KPP_COL03 { + pinmux = <0x400e8180 6 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpspi1_pcs0: IOMUXC_GPIO_AD_29_LPSPI1_PCS0 { + pinmux = <0x400e8180 0 0x400e85cc 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpuart5_rx: IOMUXC_GPIO_AD_29_LPUART5_RX { + pinmux = <0x400e8180 1 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_usdhc2_reset_b: IOMUXC_GPIO_AD_29_USDHC2_RESET_B { + pinmux = <0x400e8180 11 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_video_mux_ext_dcic2: IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8180 9 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_acmp3_in3: IOMUXC_GPIO_AD_30_ACMP3_IN3 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_can2_tx: IOMUXC_GPIO_AD_30_CAN2_TX { + pinmux = <0x400e8184 2 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_enet_tdata00: IOMUXC_GPIO_AD_30_ENET_TDATA00 { + pinmux = <0x400e8184 3 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_flexio2_flexio30: IOMUXC_GPIO_AD_30_FLEXIO2_FLEXIO30 { + pinmux = <0x400e8184 8 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio9_io29: IOMUXC_GPIO_AD_30_GPIO9_IO29 { + pinmux = <0x400e8184 10 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29_cm7: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29_CM7 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_kpp_row02: IOMUXC_GPIO_AD_30_KPP_ROW02 { + pinmux = <0x400e8184 6 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpspi1_sdo: IOMUXC_GPIO_AD_30_LPSPI1_SDO { + pinmux = <0x400e8184 0 0x400e85d8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpuart3_tx: IOMUXC_GPIO_AD_30_LPUART3_TX { + pinmux = <0x400e8184 4 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_usb_otg2_oc: IOMUXC_GPIO_AD_30_USB_OTG2_OC { + pinmux = <0x400e8184 1 0x400e86b8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_AD_30_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e8184 9 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_acmp3_in4: IOMUXC_GPIO_AD_31_ACMP3_IN4 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_can2_rx: IOMUXC_GPIO_AD_31_CAN2_RX { + pinmux = <0x400e8188 2 0x400e849c 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_enet_tdata01: IOMUXC_GPIO_AD_31_ENET_TDATA01 { + pinmux = <0x400e8188 3 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_flexio2_flexio31: IOMUXC_GPIO_AD_31_FLEXIO2_FLEXIO31 { + pinmux = <0x400e8188 8 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio9_io30: IOMUXC_GPIO_AD_31_GPIO9_IO30 { + pinmux = <0x400e8188 10 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30_cm7: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30_CM7 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_kpp_col02: IOMUXC_GPIO_AD_31_KPP_COL02 { + pinmux = <0x400e8188 6 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpspi1_sdi: IOMUXC_GPIO_AD_31_LPSPI1_SDI { + pinmux = <0x400e8188 0 0x400e85d4 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpuart3_rx: IOMUXC_GPIO_AD_31_LPUART3_RX { + pinmux = <0x400e8188 4 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_usb_otg2_pwr: IOMUXC_GPIO_AD_31_USB_OTG2_PWR { + pinmux = <0x400e8188 1 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_AD_31_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8188 9 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_acmp4_in1: IOMUXC_GPIO_AD_32_ACMP4_IN1 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_1g_mdc: IOMUXC_GPIO_AD_32_ENET_1G_MDC { + pinmux = <0x400e818c 9 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_mdc: IOMUXC_GPIO_AD_32_ENET_MDC { + pinmux = <0x400e818c 3 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio9_io31: IOMUXC_GPIO_AD_32_GPIO9_IO31 { + pinmux = <0x400e818c 10 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31_cm7: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31_CM7 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_kpp_row01: IOMUXC_GPIO_AD_32_KPP_ROW01 { + pinmux = <0x400e818c 6 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpi2c1_scl: IOMUXC_GPIO_AD_32_LPI2C1_SCL { + pinmux = <0x400e818c 0 0x400e85ac 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpuart10_tx: IOMUXC_GPIO_AD_32_LPUART10_TX { + pinmux = <0x400e818c 8 0x400e8628 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_pgmc_pmic_ready: IOMUXC_GPIO_AD_32_PGMC_PMIC_READY { + pinmux = <0x400e818c 2 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usbphy2_otg_id: IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID { + pinmux = <0x400e818c 1 0x400e86c4 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usdhc1_cd_b: IOMUXC_GPIO_AD_32_USDHC1_CD_B { + pinmux = <0x400e818c 4 0x400e86c8 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_acmp4_in2: IOMUXC_GPIO_AD_33_ACMP4_IN2 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_1g_mdio: IOMUXC_GPIO_AD_33_ENET_1G_MDIO { + pinmux = <0x400e8190 9 0x400e84c8 3 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_mdio: IOMUXC_GPIO_AD_33_ENET_MDIO { + pinmux = <0x400e8190 3 0x400e84ac 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio10_io00: IOMUXC_GPIO_AD_33_GPIO10_IO00 { + pinmux = <0x400e8190 10 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio_mux4_io00: IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_kpp_col01: IOMUXC_GPIO_AD_33_KPP_COL01 { + pinmux = <0x400e8190 6 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpi2c1_sda: IOMUXC_GPIO_AD_33_LPI2C1_SDA { + pinmux = <0x400e8190 0 0x400e85b0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpuart10_rx: IOMUXC_GPIO_AD_33_LPUART10_RX { + pinmux = <0x400e8190 8 0x400e8624 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usbphy1_otg_id: IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID { + pinmux = <0x400e8190 1 0x400e86c0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usdhc1_wp: IOMUXC_GPIO_AD_33_USDHC1_WP { + pinmux = <0x400e8190 4 0x400e86cc 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_in17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_IN17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_inout17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_acmp4_in3: IOMUXC_GPIO_AD_34_ACMP4_IN3 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN { + pinmux = <0x400e8194 3 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1g_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN { + pinmux = <0x400e8194 0 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio10_io01: IOMUXC_GPIO_AD_34_GPIO10_IO01 { + pinmux = <0x400e8194 10 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio_mux4_io01: IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_kpp_row00: IOMUXC_GPIO_AD_34_KPP_ROW00 { + pinmux = <0x400e8194 6 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_lpuart10_cts_b: IOMUXC_GPIO_AD_34_LPUART10_CTS_B { + pinmux = <0x400e8194 8 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usb_otg1_pwr: IOMUXC_GPIO_AD_34_USB_OTG1_PWR { + pinmux = <0x400e8194 1 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usdhc1_vselect: IOMUXC_GPIO_AD_34_USDHC1_VSELECT { + pinmux = <0x400e8194 4 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_wdog1_wdog_any: IOMUXC_GPIO_AD_34_WDOG1_WDOG_ANY { + pinmux = <0x400e8194 9 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_in18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_IN18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_inout18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_acmp4_in4: IOMUXC_GPIO_AD_35_ACMP4_IN4 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT { + pinmux = <0x400e8198 3 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1g_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT { + pinmux = <0x400e8198 0 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_flexspi1_b_ss1_b: IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B { + pinmux = <0x400e8198 9 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio10_io02: IOMUXC_GPIO_AD_35_GPIO10_IO02 { + pinmux = <0x400e8198 10 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio_mux4_io02: IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_kpp_col00: IOMUXC_GPIO_AD_35_KPP_COL00 { + pinmux = <0x400e8198 6 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_lpuart10_rts_b: IOMUXC_GPIO_AD_35_LPUART10_RTS_B { + pinmux = <0x400e8198 8 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usb_otg1_oc: IOMUXC_GPIO_AD_35_USB_OTG1_OC { + pinmux = <0x400e8198 1 0x400e86bc 1 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usdhc1_reset_b: IOMUXC_GPIO_AD_35_USDHC1_RESET_B { + pinmux = <0x400e8198 4 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_in19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_IN19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_inout19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_INOUT19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_enet_1g_rx_en: IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN { + pinmux = <0x400e81e4 1 0x400e84e0 2 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio10_io21: IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 { + pinmux = <0x400e81e4 10 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio_mux4_io21: IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 { + pinmux = <0x400e81e4 5 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_qtimer1_timer0: IOMUXC_GPIO_DISP_B1_00_QTIMER1_TIMER0 { + pinmux = <0x400e81e4 3 0x400e863c 2 0x400e8428>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_in26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_IN26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_inout26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_clk: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK { + pinmux = <0x400e81e8 1 0x400e84cc 2 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_er: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER { + pinmux = <0x400e81e8 2 0x400e84e4 1 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio10_io22: IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 { + pinmux = <0x400e81e8 10 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio_mux4_io22: IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 { + pinmux = <0x400e81e8 5 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_qtimer1_timer1: IOMUXC_GPIO_DISP_B1_01_QTIMER1_TIMER1 { + pinmux = <0x400e81e8 3 0x400e8640 2 0x400e842c>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_in27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_IN27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_inout27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_enet_1g_rdata00: IOMUXC_GPIO_DISP_B1_02_ENET_1G_RDATA00 { + pinmux = <0x400e81ec 1 0x400e84d0 2 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio10_io23: IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 { + pinmux = <0x400e81ec 10 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio_mux4_io23: IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 { + pinmux = <0x400e81ec 5 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpi2c3_scl: IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL { + pinmux = <0x400e81ec 2 0x400e85bc 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpuart1_tx: IOMUXC_GPIO_DISP_B1_02_LPUART1_TX { + pinmux = <0x400e81ec 9 0x400e8620 1 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_qtimer1_timer2: IOMUXC_GPIO_DISP_B1_02_QTIMER1_TIMER2 { + pinmux = <0x400e81ec 3 0x400e8644 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_in28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_IN28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_inout28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_enet_1g_rdata01: IOMUXC_GPIO_DISP_B1_03_ENET_1G_RDATA01 { + pinmux = <0x400e81f0 1 0x400e84d4 2 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio10_io24: IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 { + pinmux = <0x400e81f0 10 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio_mux4_io24: IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 { + pinmux = <0x400e81f0 5 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpi2c3_sda: IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA { + pinmux = <0x400e81f0 2 0x400e85c0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpuart1_rx: IOMUXC_GPIO_DISP_B1_03_LPUART1_RX { + pinmux = <0x400e81f0 9 0x400e861c 1 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_qtimer2_timer0: IOMUXC_GPIO_DISP_B1_03_QTIMER2_TIMER0 { + pinmux = <0x400e81f0 3 0x400e8648 2 0x400e8434>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_in29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_IN29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_inout29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_enet_1g_rdata02: IOMUXC_GPIO_DISP_B1_04_ENET_1G_RDATA02 { + pinmux = <0x400e81f4 1 0x400e84d8 2 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio10_io25: IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 { + pinmux = <0x400e81f4 10 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio_mux4_io25: IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 { + pinmux = <0x400e81f4 5 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpspi3_sck: IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK { + pinmux = <0x400e81f4 9 0x400e8600 1 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpuart4_rx: IOMUXC_GPIO_DISP_B1_04_LPUART4_RX { + pinmux = <0x400e81f4 2 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_qtimer2_timer1: IOMUXC_GPIO_DISP_B1_04_QTIMER2_TIMER1 { + pinmux = <0x400e81f4 3 0x400e864c 2 0x400e8438>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_in30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_IN30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_inout30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_enet_1g_rdata03: IOMUXC_GPIO_DISP_B1_05_ENET_1G_RDATA03 { + pinmux = <0x400e81f8 1 0x400e84dc 2 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio10_io26: IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 { + pinmux = <0x400e81f8 10 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio_mux4_io26: IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 { + pinmux = <0x400e81f8 5 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpspi3_sdi: IOMUXC_GPIO_DISP_B1_05_LPSPI3_SDI { + pinmux = <0x400e81f8 9 0x400e8604 1 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpuart4_cts_b: IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B { + pinmux = <0x400e81f8 2 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_qtimer2_timer2: IOMUXC_GPIO_DISP_B1_05_QTIMER2_TIMER2 { + pinmux = <0x400e81f8 3 0x400e8650 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_in31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_IN31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_inout31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_enet_1g_tdata03: IOMUXC_GPIO_DISP_B1_06_ENET_1G_TDATA03 { + pinmux = <0x400e81fc 1 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio10_io27: IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 { + pinmux = <0x400e81fc 10 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio_mux4_io27: IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 { + pinmux = <0x400e81fc 5 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpspi3_sdo: IOMUXC_GPIO_DISP_B1_06_LPSPI3_SDO { + pinmux = <0x400e81fc 9 0x400e8608 1 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpuart4_tx: IOMUXC_GPIO_DISP_B1_06_LPUART4_TX { + pinmux = <0x400e81fc 2 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_qtimer3_timer0: IOMUXC_GPIO_DISP_B1_06_QTIMER3_TIMER0 { + pinmux = <0x400e81fc 3 0x400e8654 2 0x400e8440>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_src_bt_cfg00: IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 { + pinmux = <0x400e81fc 6 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_in32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_IN32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_inout32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_enet_1g_tdata02: IOMUXC_GPIO_DISP_B1_07_ENET_1G_TDATA02 { + pinmux = <0x400e8200 1 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio10_io28: IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 { + pinmux = <0x400e8200 10 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio_mux4_io28: IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 { + pinmux = <0x400e8200 5 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpspi3_pcs0: IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 { + pinmux = <0x400e8200 9 0x400e85f0 1 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpuart4_rts_b: IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B { + pinmux = <0x400e8200 2 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_qtimer3_timer1: IOMUXC_GPIO_DISP_B1_07_QTIMER3_TIMER1 { + pinmux = <0x400e8200 3 0x400e8658 2 0x400e8444>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_src_bt_cfg01: IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 { + pinmux = <0x400e8200 6 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_in33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_IN33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_inout33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_enet_1g_tdata01: IOMUXC_GPIO_DISP_B1_08_ENET_1G_TDATA01 { + pinmux = <0x400e8204 1 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio10_io29: IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 { + pinmux = <0x400e8204 10 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio_mux4_io29: IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 { + pinmux = <0x400e8204 5 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_lpspi3_pcs1: IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 { + pinmux = <0x400e8204 9 0x400e85f4 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_qtimer3_timer2: IOMUXC_GPIO_DISP_B1_08_QTIMER3_TIMER2 { + pinmux = <0x400e8204 3 0x400e865c 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_src_bt_cfg02: IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 { + pinmux = <0x400e8204 6 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_usdhc1_cd_b: IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B { + pinmux = <0x400e8204 2 0x400e86c8 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_in34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_IN34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_inout34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_enet_1g_tdata00: IOMUXC_GPIO_DISP_B1_09_ENET_1G_TDATA00 { + pinmux = <0x400e8208 1 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio10_io30: IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 { + pinmux = <0x400e8208 10 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio_mux4_io30: IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 { + pinmux = <0x400e8208 5 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_lpspi3_pcs2: IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 { + pinmux = <0x400e8208 9 0x400e85f8 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_qtimer4_timer0: IOMUXC_GPIO_DISP_B1_09_QTIMER4_TIMER0 { + pinmux = <0x400e8208 3 0x400e8660 2 0x400e844c>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_src_bt_cfg03: IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 { + pinmux = <0x400e8208 6 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_usdhc1_wp: IOMUXC_GPIO_DISP_B1_09_USDHC1_WP { + pinmux = <0x400e8208 2 0x400e86cc 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_in35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_IN35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_inout35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_enet_1g_tx_en: IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN { + pinmux = <0x400e820c 1 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio10_io31: IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 { + pinmux = <0x400e820c 10 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio_mux4_io31: IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 { + pinmux = <0x400e820c 5 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_lpspi3_pcs3: IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 { + pinmux = <0x400e820c 9 0x400e85fc 1 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_qtimer4_timer1: IOMUXC_GPIO_DISP_B1_10_QTIMER4_TIMER1 { + pinmux = <0x400e820c 3 0x400e8664 2 0x400e8450>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_src_bt_cfg04: IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 { + pinmux = <0x400e820c 6 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_usdhc1_reset_b: IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B { + pinmux = <0x400e820c 2 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_in36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_IN36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_inout36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_INOUT36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e8210 2 0x400e84c4 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_tx_clk_io: IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e8210 1 0x400e84e8 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio11_io00: IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 { + pinmux = <0x400e8210 10 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio_mux5_io00: IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 { + pinmux = <0x400e8210 5 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_qtimer4_timer2: IOMUXC_GPIO_DISP_B1_11_QTIMER4_TIMER2 { + pinmux = <0x400e8210 3 0x400e8668 1 0x400e8454>; + pin-pdrv; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_src_bt_cfg05: IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 { + pinmux = <0x400e8210 6 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_in37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_IN37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_inout37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_INOUT37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_enet_1g_tx_er: IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER { + pinmux = <0x400e8214 3 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio11_io01: IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 { + pinmux = <0x400e8214 10 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio_mux5_io01: IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 { + pinmux = <0x400e8214 5 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_mqs_right: IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT { + pinmux = <0x400e8214 2 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_rx_data01: IOMUXC_GPIO_DISP_B2_00_SAI1_RX_DATA01 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_tx_data03: IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_src_bt_cfg06: IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 { + pinmux = <0x400e8214 6 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_00_WDOG1_WDOG_B { + pinmux = <0x400e8214 1 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ccm_enet_ref_clk_25m: IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8218 9 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ewm_ewm_out_b: IOMUXC_GPIO_DISP_B2_01_EWM_EWM_OUT_B { + pinmux = <0x400e8218 8 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio11_io02: IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 { + pinmux = <0x400e8218 10 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio_mux5_io02: IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 { + pinmux = <0x400e8218 5 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_mqs_left: IOMUXC_GPIO_DISP_B2_01_MQS_LEFT { + pinmux = <0x400e8218 2 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_rx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_RX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_tx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_src_bt_cfg07: IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 { + pinmux = <0x400e8218 6 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_usdhc1_vselect: IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT { + pinmux = <0x400e8218 1 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_01_WDOG2_WDOG_B { + pinmux = <0x400e8218 3 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_arm_trace00: IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 { + pinmux = <0x400e821c 3 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_enet_tdata00: IOMUXC_GPIO_DISP_B2_02_ENET_TDATA00 { + pinmux = <0x400e821c 1 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio11_io03: IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 { + pinmux = <0x400e821c 10 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio_mux5_io03: IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 { + pinmux = <0x400e821c 5 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_pit1_trigger03: IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER03 { + pinmux = <0x400e821c 2 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_rx_data03: IOMUXC_GPIO_DISP_B2_02_SAI1_RX_DATA03 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_tx_data01: IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_src_bt_cfg08: IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 { + pinmux = <0x400e821c 6 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_arm_trace01: IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 { + pinmux = <0x400e8220 3 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_enet_tdata01: IOMUXC_GPIO_DISP_B2_03_ENET_TDATA01 { + pinmux = <0x400e8220 1 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio11_io04: IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 { + pinmux = <0x400e8220 10 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio_mux5_io04: IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 { + pinmux = <0x400e8220 5 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_pit1_trigger02: IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER02 { + pinmux = <0x400e8220 2 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_sai1_mclk: IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK { + pinmux = <0x400e8220 4 0x400e866c 1 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_src_bt_cfg09: IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 { + pinmux = <0x400e8220 6 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_arm_trace02: IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 { + pinmux = <0x400e8224 3 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_enet_tx_en: IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN { + pinmux = <0x400e8224 1 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio11_io05: IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 { + pinmux = <0x400e8224 10 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio_mux5_io05: IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 { + pinmux = <0x400e8224 5 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_pit1_trigger01: IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER01 { + pinmux = <0x400e8224 2 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_sai1_rx_sync: IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC { + pinmux = <0x400e8224 4 0x400e8678 1 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_src_bt_cfg10: IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 { + pinmux = <0x400e8224 6 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_arm_trace03: IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 { + pinmux = <0x400e8228 3 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_ref_clk: IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK { + pinmux = <0x400e8228 2 0x400e84a8 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_tx_clk: IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK { + pinmux = <0x400e8228 1 0x400e84c0 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio11_io06: IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 { + pinmux = <0x400e8228 10 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio_mux5_io06: IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 { + pinmux = <0x400e8228 5 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_sai1_rx_bclk: IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK { + pinmux = <0x400e8228 4 0x400e8670 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_src_bt_cfg11: IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 { + pinmux = <0x400e8228 6 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_arm_trace_clk: IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK { + pinmux = <0x400e822c 3 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_enet_rdata00: IOMUXC_GPIO_DISP_B2_06_ENET_RDATA00 { + pinmux = <0x400e822c 1 0x400e84b0 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio11_io07: IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 { + pinmux = <0x400e822c 10 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio_mux5_io07: IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 { + pinmux = <0x400e822c 5 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_lpuart7_tx: IOMUXC_GPIO_DISP_B2_06_LPUART7_TX { + pinmux = <0x400e822c 2 0x400e8630 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_sai1_rx_data00: IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 { + pinmux = <0x400e822c 4 0x400e8674 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_arm_trace_swo: IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO { + pinmux = <0x400e8230 3 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_enet_rdata01: IOMUXC_GPIO_DISP_B2_07_ENET_RDATA01 { + pinmux = <0x400e8230 1 0x400e84b4 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio11_io08: IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 { + pinmux = <0x400e8230 10 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio_mux5_io08: IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 { + pinmux = <0x400e8230 5 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_lpuart7_rx: IOMUXC_GPIO_DISP_B2_07_LPUART7_RX { + pinmux = <0x400e8230 2 0x400e862c 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_sai1_tx_data00: IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 { + pinmux = <0x400e8230 4 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_cm7_imxrt_txev: IOMUXC_GPIO_DISP_B2_08_CM7_IMXRT_TXEV { + pinmux = <0x400e8234 3 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_enet_rx_en: IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN { + pinmux = <0x400e8234 1 0x400e84b8 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio11_io09: IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 { + pinmux = <0x400e8234 10 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio_mux5_io09: IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 { + pinmux = <0x400e8234 5 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart1_tx: IOMUXC_GPIO_DISP_B2_08_LPUART1_TX { + pinmux = <0x400e8234 9 0x400e8620 2 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart8_tx: IOMUXC_GPIO_DISP_B2_08_LPUART8_TX { + pinmux = <0x400e8234 2 0x400e8638 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_sai1_tx_bclk: IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK { + pinmux = <0x400e8234 4 0x400e867c 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_cm7_imxrt_rxev: IOMUXC_GPIO_DISP_B2_09_CM7_IMXRT_RXEV { + pinmux = <0x400e8238 3 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_enet_rx_er: IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER { + pinmux = <0x400e8238 1 0x400e84bc 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio11_io10: IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 { + pinmux = <0x400e8238 10 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio_mux5_io10: IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 { + pinmux = <0x400e8238 5 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart1_rx: IOMUXC_GPIO_DISP_B2_09_LPUART1_RX { + pinmux = <0x400e8238 9 0x400e861c 2 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart8_rx: IOMUXC_GPIO_DISP_B2_09_LPUART8_RX { + pinmux = <0x400e8238 2 0x400e8634 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_sai1_tx_sync: IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC { + pinmux = <0x400e8238 4 0x400e8680 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio11_io11: IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 { + pinmux = <0x400e823c 10 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio_mux5_io11: IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 { + pinmux = <0x400e823c 5 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpi2c3_scl: IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL { + pinmux = <0x400e823c 6 0x400e85bc 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpuart2_tx: IOMUXC_GPIO_DISP_B2_10_LPUART2_TX { + pinmux = <0x400e823c 2 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_sim2_trxd: IOMUXC_GPIO_DISP_B2_10_SIM2_TRXD { + pinmux = <0x400e823c 1 0x400e86a8 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_spdif_in: IOMUXC_GPIO_DISP_B2_10_SPDIF_IN { + pinmux = <0x400e823c 9 0x400e86b4 2 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_10_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e823c 3 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_in38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_IN38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_inout38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_INOUT38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio11_io12: IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 { + pinmux = <0x400e8240 10 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio_mux5_io12: IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 { + pinmux = <0x400e8240 5 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpi2c3_sda: IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA { + pinmux = <0x400e8240 6 0x400e85c0 1 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpuart2_rx: IOMUXC_GPIO_DISP_B2_11_LPUART2_RX { + pinmux = <0x400e8240 2 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_sim2_clk: IOMUXC_GPIO_DISP_B2_11_SIM2_CLK { + pinmux = <0x400e8240 1 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_spdif_out: IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT { + pinmux = <0x400e8240 9 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_11_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8240 3 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_in39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_IN39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_inout39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_INOUT39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_can1_tx: IOMUXC_GPIO_DISP_B2_12_CAN1_TX { + pinmux = <0x400e8244 2 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio11_io13: IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 { + pinmux = <0x400e8244 10 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio_mux5_io13: IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 { + pinmux = <0x400e8244 5 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpi2c4_scl: IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL { + pinmux = <0x400e8244 6 0x400e85c4 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpspi4_sck: IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK { + pinmux = <0x400e8244 9 0x400e8610 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpuart2_cts_b: IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B { + pinmux = <0x400e8244 3 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_sim2_rst_b: IOMUXC_GPIO_DISP_B2_12_SIM2_RST_B { + pinmux = <0x400e8244 1 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_in40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_IN40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_inout40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_INOUT40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_can1_rx: IOMUXC_GPIO_DISP_B2_13_CAN1_RX { + pinmux = <0x400e8248 2 0x400e8498 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_enet_ref_clk: IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK { + pinmux = <0x400e8248 4 0x400e84a8 2 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio11_io14: IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 { + pinmux = <0x400e8248 10 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio_mux5_io14: IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 { + pinmux = <0x400e8248 5 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpi2c4_sda: IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA { + pinmux = <0x400e8248 6 0x400e85c8 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpspi4_sdi: IOMUXC_GPIO_DISP_B2_13_LPSPI4_SDI { + pinmux = <0x400e8248 9 0x400e8614 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpuart2_rts_b: IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B { + pinmux = <0x400e8248 3 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_sim2_sven: IOMUXC_GPIO_DISP_B2_13_SIM2_SVEN { + pinmux = <0x400e8248 1 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_can1_tx: IOMUXC_GPIO_DISP_B2_14_CAN1_TX { + pinmux = <0x400e824c 6 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK1 { + pinmux = <0x400e824c 4 0x400e84c4 3 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio11_io15: IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 { + pinmux = <0x400e824c 10 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio_mux5_io15: IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 { + pinmux = <0x400e824c 5 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_lpspi4_sdo: IOMUXC_GPIO_DISP_B2_14_LPSPI4_SDO { + pinmux = <0x400e824c 9 0x400e8618 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_sim2_pd: IOMUXC_GPIO_DISP_B2_14_SIM2_PD { + pinmux = <0x400e824c 1 0x400e86ac 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_ext_dcic1: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e824c 3 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_14_WDOG2_WDOG_B { + pinmux = <0x400e824c 2 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_can1_rx: IOMUXC_GPIO_DISP_B2_15_CAN1_RX { + pinmux = <0x400e8250 6 0x400e8498 2 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio11_io16: IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 { + pinmux = <0x400e8250 10 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio_mux5_io16: IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 { + pinmux = <0x400e8250 5 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_lpspi4_pcs0: IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 { + pinmux = <0x400e8250 9 0x400e860c 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_pit1_trigger00: IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER00 { + pinmux = <0x400e8250 4 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_sim2_power_fail: IOMUXC_GPIO_DISP_B2_15_SIM2_POWER_FAIL { + pinmux = <0x400e8250 1 0x400e86b0 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_ext_dcic2: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8250 3 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_15_WDOG1_WDOG_B { + pinmux = <0x400e8250 2 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexio1_flexio00: IOMUXC_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00 { + pinmux = <0x400e8010 8 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexpwm4_pwm0_a: IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A { + pinmux = <0x400e8010 1 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio7_io00: IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 { + pinmux = <0x400e8010 10 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio_mux1_io00: IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 { + pinmux = <0x400e8010 5 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_semc_data00: IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 { + pinmux = <0x400e8010 0 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexio1_flexio01: IOMUXC_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01 { + pinmux = <0x400e8014 8 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexpwm4_pwm0_b: IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B { + pinmux = <0x400e8014 1 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio7_io01: IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 { + pinmux = <0x400e8014 10 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio_mux1_io01: IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 { + pinmux = <0x400e8014 5 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_semc_data01: IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 { + pinmux = <0x400e8014 0 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexio1_flexio02: IOMUXC_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02 { + pinmux = <0x400e8018 8 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexpwm4_pwm1_a: IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A { + pinmux = <0x400e8018 1 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio7_io02: IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 { + pinmux = <0x400e8018 10 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio_mux1_io02: IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 { + pinmux = <0x400e8018 5 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_semc_data02: IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 { + pinmux = <0x400e8018 0 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexio1_flexio03: IOMUXC_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03 { + pinmux = <0x400e801c 8 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexpwm4_pwm1_b: IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B { + pinmux = <0x400e801c 1 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio7_io03: IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 { + pinmux = <0x400e801c 10 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio_mux1_io03: IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 { + pinmux = <0x400e801c 5 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_semc_data03: IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 { + pinmux = <0x400e801c 0 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexio1_flexio04: IOMUXC_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04 { + pinmux = <0x400e8020 8 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexpwm4_pwm2_a: IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A { + pinmux = <0x400e8020 1 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio7_io04: IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 { + pinmux = <0x400e8020 10 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio_mux1_io04: IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 { + pinmux = <0x400e8020 5 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_semc_data04: IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 { + pinmux = <0x400e8020 0 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexio1_flexio05: IOMUXC_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05 { + pinmux = <0x400e8024 8 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexpwm4_pwm2_b: IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B { + pinmux = <0x400e8024 1 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio7_io05: IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 { + pinmux = <0x400e8024 10 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio_mux1_io05: IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 { + pinmux = <0x400e8024 5 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_semc_data05: IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 { + pinmux = <0x400e8024 0 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexio1_flexio06: IOMUXC_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06 { + pinmux = <0x400e8028 8 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexpwm2_pwm0_a: IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A { + pinmux = <0x400e8028 1 0x400e8518 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio7_io06: IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 { + pinmux = <0x400e8028 10 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio_mux1_io06: IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 { + pinmux = <0x400e8028 5 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_semc_data06: IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 { + pinmux = <0x400e8028 0 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexio1_flexio07: IOMUXC_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07 { + pinmux = <0x400e802c 8 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexpwm2_pwm0_b: IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B { + pinmux = <0x400e802c 1 0x400e8524 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio7_io07: IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 { + pinmux = <0x400e802c 10 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio_mux1_io07: IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 { + pinmux = <0x400e802c 5 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_semc_data07: IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 { + pinmux = <0x400e802c 0 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexio1_flexio08: IOMUXC_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08 { + pinmux = <0x400e8030 8 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexpwm2_pwm1_a: IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A { + pinmux = <0x400e8030 1 0x400e851c 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio7_io08: IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 { + pinmux = <0x400e8030 10 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio_mux1_io08: IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 { + pinmux = <0x400e8030 5 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_semc_dm00: IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 { + pinmux = <0x400e8030 0 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexio1_flexio09: IOMUXC_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09 { + pinmux = <0x400e8034 8 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexpwm2_pwm1_b: IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B { + pinmux = <0x400e8034 1 0x400e8528 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio7_io09: IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 { + pinmux = <0x400e8034 10 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio_mux1_io09: IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 { + pinmux = <0x400e8034 5 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpt5_capture1: IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 { + pinmux = <0x400e8034 2 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_semc_addr00: IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 { + pinmux = <0x400e8034 0 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexio1_flexio10: IOMUXC_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10 { + pinmux = <0x400e8038 8 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexpwm2_pwm2_a: IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A { + pinmux = <0x400e8038 1 0x400e8520 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio7_io10: IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 { + pinmux = <0x400e8038 10 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio_mux1_io10: IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 { + pinmux = <0x400e8038 5 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpt5_capture2: IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 { + pinmux = <0x400e8038 2 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_semc_addr01: IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 { + pinmux = <0x400e8038 0 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexio1_flexio11: IOMUXC_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11 { + pinmux = <0x400e803c 8 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexpwm2_pwm2_b: IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B { + pinmux = <0x400e803c 1 0x400e852c 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio7_io11: IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 { + pinmux = <0x400e803c 10 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio_mux1_io11: IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 { + pinmux = <0x400e803c 5 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpt5_compare1: IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 { + pinmux = <0x400e803c 2 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_semc_addr02: IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 { + pinmux = <0x400e803c 0 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_flexio1_flexio12: IOMUXC_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12 { + pinmux = <0x400e8040 8 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio7_io12: IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 { + pinmux = <0x400e8040 10 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio_mux1_io12: IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 { + pinmux = <0x400e8040 5 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpt5_compare2: IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 { + pinmux = <0x400e8040 2 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_semc_addr03: IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 { + pinmux = <0x400e8040 0 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_in04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_IN04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_INOUT04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_flexio1_flexio13: IOMUXC_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13 { + pinmux = <0x400e8044 8 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio7_io13: IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 { + pinmux = <0x400e8044 10 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio_mux1_io13: IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 { + pinmux = <0x400e8044 5 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpt5_compare3: IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 { + pinmux = <0x400e8044 2 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_semc_addr04: IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 { + pinmux = <0x400e8044 0 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_in05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_IN05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_INOUT05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_flexio1_flexio14: IOMUXC_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14 { + pinmux = <0x400e8048 8 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio7_io14: IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 { + pinmux = <0x400e8048 10 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio_mux1_io14: IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 { + pinmux = <0x400e8048 5 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpt5_clk: IOMUXC_GPIO_EMC_B1_14_GPT5_CLK { + pinmux = <0x400e8048 2 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_semc_addr05: IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 { + pinmux = <0x400e8048 0 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_in06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_IN06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_INOUT06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_flexio1_flexio15: IOMUXC_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15 { + pinmux = <0x400e804c 8 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio7_io15: IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 { + pinmux = <0x400e804c 10 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio_mux1_io15: IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 { + pinmux = <0x400e804c 5 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_semc_addr06: IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 { + pinmux = <0x400e804c 0 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_in07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_IN07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_INOUT07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_flexio1_flexio16: IOMUXC_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16 { + pinmux = <0x400e8050 8 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio7_io16: IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 { + pinmux = <0x400e8050 10 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio_mux1_io16: IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 { + pinmux = <0x400e8050 5 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_semc_addr07: IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 { + pinmux = <0x400e8050 0 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_in08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_IN08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_INOUT08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexio1_flexio17: IOMUXC_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17 { + pinmux = <0x400e8054 8 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexpwm4_pwm3_a: IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A { + pinmux = <0x400e8054 1 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio7_io17: IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 { + pinmux = <0x400e8054 10 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio_mux1_io17: IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 { + pinmux = <0x400e8054 5 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_qtimer1_timer0: IOMUXC_GPIO_EMC_B1_17_QTIMER1_TIMER0 { + pinmux = <0x400e8054 2 0x400e863c 0 0x400e8298>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_semc_addr08: IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 { + pinmux = <0x400e8054 0 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexio1_flexio18: IOMUXC_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18 { + pinmux = <0x400e8058 8 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexpwm4_pwm3_b: IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B { + pinmux = <0x400e8058 1 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio7_io18: IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 { + pinmux = <0x400e8058 10 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio_mux1_io18: IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 { + pinmux = <0x400e8058 5 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_qtimer2_timer0: IOMUXC_GPIO_EMC_B1_18_QTIMER2_TIMER0 { + pinmux = <0x400e8058 2 0x400e8648 0 0x400e829c>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_semc_addr09: IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 { + pinmux = <0x400e8058 0 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexio1_flexio19: IOMUXC_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19 { + pinmux = <0x400e805c 8 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexpwm2_pwm3_a: IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A { + pinmux = <0x400e805c 1 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio7_io19: IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 { + pinmux = <0x400e805c 10 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio_mux1_io19: IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 { + pinmux = <0x400e805c 5 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_qtimer3_timer0: IOMUXC_GPIO_EMC_B1_19_QTIMER3_TIMER0 { + pinmux = <0x400e805c 2 0x400e8654 0 0x400e82a0>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_semc_addr11: IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 { + pinmux = <0x400e805c 0 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexio1_flexio20: IOMUXC_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20 { + pinmux = <0x400e8060 8 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexpwm2_pwm3_b: IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B { + pinmux = <0x400e8060 1 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio7_io20: IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 { + pinmux = <0x400e8060 10 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio_mux1_io20: IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 { + pinmux = <0x400e8060 5 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_qtimer4_timer0: IOMUXC_GPIO_EMC_B1_20_QTIMER4_TIMER0 { + pinmux = <0x400e8060 2 0x400e8660 0 0x400e82a4>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_semc_addr12: IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 { + pinmux = <0x400e8060 0 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexio1_flexio21: IOMUXC_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21 { + pinmux = <0x400e8064 8 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A { + pinmux = <0x400e8064 1 0x400e853c 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio7_io21: IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 { + pinmux = <0x400e8064 10 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio_mux1_io21: IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 { + pinmux = <0x400e8064 5 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_semc_ba0: IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 { + pinmux = <0x400e8064 0 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexio1_flexio22: IOMUXC_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22 { + pinmux = <0x400e8068 8 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B { + pinmux = <0x400e8068 1 0x400e854c 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio7_io22: IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 { + pinmux = <0x400e8068 10 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio_mux1_io22: IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 { + pinmux = <0x400e8068 5 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_semc_ba1: IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 { + pinmux = <0x400e8068 0 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexio1_flexio23: IOMUXC_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23 { + pinmux = <0x400e806c 8 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexpwm1_pwm0_a: IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A { + pinmux = <0x400e806c 1 0x400e8500 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio7_io23: IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 { + pinmux = <0x400e806c 10 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio_mux1_io23: IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 { + pinmux = <0x400e806c 5 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_semc_addr10: IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 { + pinmux = <0x400e806c 0 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexio1_flexio24: IOMUXC_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24 { + pinmux = <0x400e8070 8 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexpwm1_pwm0_b: IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B { + pinmux = <0x400e8070 1 0x400e850c 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio7_io24: IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 { + pinmux = <0x400e8070 10 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio_mux1_io24: IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 { + pinmux = <0x400e8070 5 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_semc_cas: IOMUXC_GPIO_EMC_B1_24_SEMC_CAS { + pinmux = <0x400e8070 0 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexio1_flexio25: IOMUXC_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25 { + pinmux = <0x400e8074 8 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexpwm1_pwm1_a: IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A { + pinmux = <0x400e8074 1 0x400e8504 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio7_io25: IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 { + pinmux = <0x400e8074 10 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio_mux1_io25: IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 { + pinmux = <0x400e8074 5 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_semc_ras: IOMUXC_GPIO_EMC_B1_25_SEMC_RAS { + pinmux = <0x400e8074 0 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexio1_flexio26: IOMUXC_GPIO_EMC_B1_26_FLEXIO1_FLEXIO26 { + pinmux = <0x400e8078 8 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexpwm1_pwm1_b: IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B { + pinmux = <0x400e8078 1 0x400e8510 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio7_io26: IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 { + pinmux = <0x400e8078 10 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio_mux1_io26: IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 { + pinmux = <0x400e8078 5 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_semc_clk: IOMUXC_GPIO_EMC_B1_26_SEMC_CLK { + pinmux = <0x400e8078 0 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexio1_flexio27: IOMUXC_GPIO_EMC_B1_27_FLEXIO1_FLEXIO27 { + pinmux = <0x400e807c 8 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexpwm1_pwm2_a: IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A { + pinmux = <0x400e807c 1 0x400e8508 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio7_io27: IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 { + pinmux = <0x400e807c 10 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio_mux1_io27: IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 { + pinmux = <0x400e807c 5 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_semc_cke: IOMUXC_GPIO_EMC_B1_27_SEMC_CKE { + pinmux = <0x400e807c 0 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexio1_flexio28: IOMUXC_GPIO_EMC_B1_28_FLEXIO1_FLEXIO28 { + pinmux = <0x400e8080 8 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexpwm1_pwm2_b: IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B { + pinmux = <0x400e8080 1 0x400e8514 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio7_io28: IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 { + pinmux = <0x400e8080 10 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio_mux1_io28: IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 { + pinmux = <0x400e8080 5 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_semc_we: IOMUXC_GPIO_EMC_B1_28_SEMC_WE { + pinmux = <0x400e8080 0 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexio1_flexio29: IOMUXC_GPIO_EMC_B1_29_FLEXIO1_FLEXIO29 { + pinmux = <0x400e8084 8 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A { + pinmux = <0x400e8084 1 0x400e8530 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio7_io29: IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 { + pinmux = <0x400e8084 10 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio_mux1_io29: IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 { + pinmux = <0x400e8084 5 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_semc_cs0: IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 { + pinmux = <0x400e8084 0 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexio1_flexio30: IOMUXC_GPIO_EMC_B1_30_FLEXIO1_FLEXIO30 { + pinmux = <0x400e8088 8 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B { + pinmux = <0x400e8088 1 0x400e8540 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio7_io30: IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 { + pinmux = <0x400e8088 10 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio_mux1_io30: IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 { + pinmux = <0x400e8088 5 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_semc_data08: IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 { + pinmux = <0x400e8088 0 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexio1_flexio31: IOMUXC_GPIO_EMC_B1_31_FLEXIO1_FLEXIO31 { + pinmux = <0x400e808c 8 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A { + pinmux = <0x400e808c 1 0x400e8534 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio7_io31: IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 { + pinmux = <0x400e808c 10 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio_mux1_io31: IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 { + pinmux = <0x400e808c 5 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_semc_data09: IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 { + pinmux = <0x400e808c 0 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B { + pinmux = <0x400e8090 1 0x400e8544 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio8_io00: IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 { + pinmux = <0x400e8090 10 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00_cm7: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00_CM7 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_semc_data10: IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 { + pinmux = <0x400e8090 0 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A { + pinmux = <0x400e8094 1 0x400e8538 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio8_io01: IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 { + pinmux = <0x400e8094 10 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01_cm7: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01_CM7 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_semc_data11: IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 { + pinmux = <0x400e8094 0 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B { + pinmux = <0x400e8098 1 0x400e8548 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio8_io02: IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 { + pinmux = <0x400e8098 10 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02_cm7: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02_CM7 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_semc_data12: IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 { + pinmux = <0x400e8098 0 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio8_io03: IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 { + pinmux = <0x400e809c 10 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03_cm7: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03_CM7 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_semc_data13: IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 { + pinmux = <0x400e809c 0 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_in09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_IN09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_INOUT09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio8_io04: IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 { + pinmux = <0x400e80a0 10 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04_cm7: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04_CM7 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_semc_data14: IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 { + pinmux = <0x400e80a0 0 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_in10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_IN10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_INOUT10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio8_io05: IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 { + pinmux = <0x400e80a4 10 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05_cm7: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05_CM7 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_semc_data15: IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 { + pinmux = <0x400e80a4 0 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_in11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_IN11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_INOUT11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_flexpwm1_pwm3_a: IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A { + pinmux = <0x400e80a8 1 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio8_io06: IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 { + pinmux = <0x400e80a8 10 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06_cm7: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06_CM7 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_qtimer1_timer1: IOMUXC_GPIO_EMC_B1_38_QTIMER1_TIMER1 { + pinmux = <0x400e80a8 2 0x400e8640 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_semc_dm01: IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 { + pinmux = <0x400e80a8 0 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_flexpwm1_pwm3_b: IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B { + pinmux = <0x400e80ac 1 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio8_io07: IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 { + pinmux = <0x400e80ac 10 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07_cm7: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07_CM7 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_qtimer2_timer1: IOMUXC_GPIO_EMC_B1_39_QTIMER2_TIMER1 { + pinmux = <0x400e80ac 2 0x400e864c 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_semc_dqs: IOMUXC_GPIO_EMC_B1_39_SEMC_DQS { + pinmux = <0x400e80ac 0 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_ccm_clko1: IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 { + pinmux = <0x400e80b0 9 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_enet_1g_mdc: IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC { + pinmux = <0x400e80b0 7 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio8_io08: IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 { + pinmux = <0x400e80b0 10 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08_cm7: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08_CM7 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_lpuart6_tx: IOMUXC_GPIO_EMC_B1_40_LPUART6_TX { + pinmux = <0x400e80b0 3 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_mqs_right: IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT { + pinmux = <0x400e80b0 2 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_semc_rdy: IOMUXC_GPIO_EMC_B1_40_SEMC_RDY { + pinmux = <0x400e80b0 0 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_in12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_IN12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_INOUT12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_ccm_clko2: IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 { + pinmux = <0x400e80b4 9 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_enet_1g_mdio: IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO { + pinmux = <0x400e80b4 7 0x400e84c8 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_flexspi2_b_data07: IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 { + pinmux = <0x400e80b4 4 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio8_io09: IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 { + pinmux = <0x400e80b4 10 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09_cm7: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09_CM7 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_lpuart6_rx: IOMUXC_GPIO_EMC_B1_41_LPUART6_RX { + pinmux = <0x400e80b4 3 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_mqs_left: IOMUXC_GPIO_EMC_B1_41_MQS_LEFT { + pinmux = <0x400e80b4 2 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_semc_csx00: IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 { + pinmux = <0x400e80b4 0 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_in13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_IN13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_INOUT13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_ccm_enet_ref_clk_25m: IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e80b8 1 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A { + pinmux = <0x400e80b8 11 0x400e8530 1 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexspi2_b_data06: IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 { + pinmux = <0x400e80b8 4 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio8_io10: IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 { + pinmux = <0x400e80b8 10 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10_cm7: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10_CM7 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpi2c2_scl: IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL { + pinmux = <0x400e80b8 9 0x400e85b4 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpspi1_sck: IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK { + pinmux = <0x400e80b8 8 0x400e85d0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpuart6_cts_b: IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B { + pinmux = <0x400e80b8 3 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_00_QTIMER3_TIMER1 { + pinmux = <0x400e80b8 2 0x400e8658 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_semc_data16: IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 { + pinmux = <0x400e80b8 0 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_in20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_inout20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B { + pinmux = <0x400e80bc 11 0x400e8540 1 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexspi2_b_data05: IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 { + pinmux = <0x400e80bc 4 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio8_io11: IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 { + pinmux = <0x400e80bc 10 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11_cm7: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11_CM7 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpi2c2_sda: IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA { + pinmux = <0x400e80bc 9 0x400e85b8 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpspi1_pcs0: IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 { + pinmux = <0x400e80bc 8 0x400e85cc 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpuart6_rts_b: IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B { + pinmux = <0x400e80bc 3 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_qtimer4_timer1: IOMUXC_GPIO_EMC_B2_01_QTIMER4_TIMER1 { + pinmux = <0x400e80bc 2 0x400e8664 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_semc_data17: IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 { + pinmux = <0x400e80bc 0 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_usdhc2_cd_b: IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B { + pinmux = <0x400e80bc 1 0x400e86d0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_in21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_inout21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A { + pinmux = <0x400e80c0 11 0x400e8534 1 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexspi2_b_data04: IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 { + pinmux = <0x400e80c0 4 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio8_io12: IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 { + pinmux = <0x400e80c0 10 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12_cm7: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12_CM7 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_lpspi1_sdo: IOMUXC_GPIO_EMC_B2_02_LPSPI1_SDO { + pinmux = <0x400e80c0 8 0x400e85d8 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_semc_data18: IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 { + pinmux = <0x400e80c0 0 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_usdhc2_wp: IOMUXC_GPIO_EMC_B2_02_USDHC2_WP { + pinmux = <0x400e80c0 1 0x400e86d4 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_in22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_inout22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_enet_1g_tdata03: IOMUXC_GPIO_EMC_B2_03_ENET_1G_TDATA03 { + pinmux = <0x400e80c4 7 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B { + pinmux = <0x400e80c4 11 0x400e8544 1 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexspi2_b_data03: IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 { + pinmux = <0x400e80c4 4 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio8_io13: IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 { + pinmux = <0x400e80c4 10 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13_cm7: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13_CM7 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_lpspi1_sdi: IOMUXC_GPIO_EMC_B2_03_LPSPI1_SDI { + pinmux = <0x400e80c4 8 0x400e85d4 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_semc_data19: IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 { + pinmux = <0x400e80c4 0 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_usdhc2_vselect: IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT { + pinmux = <0x400e80c4 1 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_in23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_inout23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_enet_1g_tdata02: IOMUXC_GPIO_EMC_B2_04_ENET_1G_TDATA02 { + pinmux = <0x400e80c8 7 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A { + pinmux = <0x400e80c8 11 0x400e8538 1 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexspi2_b_data02: IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 { + pinmux = <0x400e80c8 4 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio8_io14: IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 { + pinmux = <0x400e80c8 10 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14_cm7: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14_CM7 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_lpspi3_sck: IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK { + pinmux = <0x400e80c8 8 0x400e8600 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_sai2_mclk: IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK { + pinmux = <0x400e80c8 2 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_semc_data20: IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 { + pinmux = <0x400e80c8 0 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_usdhc2_reset_b: IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B { + pinmux = <0x400e80c8 1 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_in24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_inout24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_enet_1g_rx_clk: IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK { + pinmux = <0x400e80cc 7 0x400e84cc 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B { + pinmux = <0x400e80cc 11 0x400e8548 1 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexspi2_b_data01: IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 { + pinmux = <0x400e80cc 4 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio8_io15: IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 { + pinmux = <0x400e80cc 10 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15_cm7: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15_CM7 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpt3_clk: IOMUXC_GPIO_EMC_B2_05_GPT3_CLK { + pinmux = <0x400e80cc 1 0x400e8598 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_lpspi3_pcs0: IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 { + pinmux = <0x400e80cc 8 0x400e85f0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_pit1_trigger00: IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER00 { + pinmux = <0x400e80cc 9 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_sai2_rx_sync: IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC { + pinmux = <0x400e80cc 2 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_semc_data21: IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 { + pinmux = <0x400e80cc 0 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_in25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_inout25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_enet_1g_tx_er: IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER { + pinmux = <0x400e80d0 7 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A { + pinmux = <0x400e80d0 11 0x400e853c 1 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexspi2_b_data00: IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 { + pinmux = <0x400e80d0 4 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio8_io16: IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 { + pinmux = <0x400e80d0 10 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16_cm7: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16_CM7 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpt3_capture1: IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 { + pinmux = <0x400e80d0 1 0x400e8590 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_lpspi3_sdo: IOMUXC_GPIO_EMC_B2_06_LPSPI3_SDO { + pinmux = <0x400e80d0 8 0x400e8608 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_pit1_trigger01: IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER01 { + pinmux = <0x400e80d0 9 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_sai2_rx_bclk: IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK { + pinmux = <0x400e80d0 2 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_semc_data22: IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 { + pinmux = <0x400e80d0 0 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_in26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_IN26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_inout26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_enet_1g_rdata03: IOMUXC_GPIO_EMC_B2_07_ENET_1G_RDATA03 { + pinmux = <0x400e80d4 7 0x400e84dc 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B { + pinmux = <0x400e80d4 11 0x400e854c 1 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexspi2_b_dqs: IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS { + pinmux = <0x400e80d4 4 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio8_io17: IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 { + pinmux = <0x400e80d4 10 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17_cm7: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17_CM7 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpt3_capture2: IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 { + pinmux = <0x400e80d4 1 0x400e8594 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_lpspi3_sdi: IOMUXC_GPIO_EMC_B2_07_LPSPI3_SDI { + pinmux = <0x400e80d4 8 0x400e8604 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_pit1_trigger02: IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER02 { + pinmux = <0x400e80d4 9 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_sai2_rx_data: IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA { + pinmux = <0x400e80d4 2 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_semc_data23: IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 { + pinmux = <0x400e80d4 0 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_in27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_IN27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_inout27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_enet_1g_rdata02: IOMUXC_GPIO_EMC_B2_08_ENET_1G_RDATA02 { + pinmux = <0x400e80d8 7 0x400e84d8 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B { + pinmux = <0x400e80d8 4 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio8_io18: IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 { + pinmux = <0x400e80d8 10 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18_cm7: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18_CM7 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpt3_compare1: IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 { + pinmux = <0x400e80d8 1 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_lpspi3_pcs1: IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 { + pinmux = <0x400e80d8 8 0x400e85f4 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_pit1_trigger03: IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER03 { + pinmux = <0x400e80d8 9 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_sai2_tx_data: IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA { + pinmux = <0x400e80d8 2 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_semc_dm02: IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 { + pinmux = <0x400e80d8 0 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_in28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_IN28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_inout28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_enet_1g_crs: IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS { + pinmux = <0x400e80dc 7 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_flexspi2_b_sclk: IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK { + pinmux = <0x400e80dc 4 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio8_io19: IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 { + pinmux = <0x400e80dc 10 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19_cm7: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19_CM7 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpt3_compare2: IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 { + pinmux = <0x400e80dc 1 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_lpspi3_pcs2: IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 { + pinmux = <0x400e80dc 8 0x400e85f8 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_qtimer1_timer0: IOMUXC_GPIO_EMC_B2_09_QTIMER1_TIMER0 { + pinmux = <0x400e80dc 9 0x400e863c 1 0x400e8320>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_sai2_tx_bclk: IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK { + pinmux = <0x400e80dc 2 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_semc_data24: IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 { + pinmux = <0x400e80dc 0 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_in29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_IN29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_inout29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_enet_1g_col: IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL { + pinmux = <0x400e80e0 7 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_flexspi2_a_sclk: IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK { + pinmux = <0x400e80e0 4 0x400e858c 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio8_io20: IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 { + pinmux = <0x400e80e0 10 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20_cm7: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20_CM7 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpt3_compare3: IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 { + pinmux = <0x400e80e0 1 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_lpspi3_pcs3: IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 { + pinmux = <0x400e80e0 8 0x400e85fc 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_qtimer1_timer1: IOMUXC_GPIO_EMC_B2_10_QTIMER1_TIMER1 { + pinmux = <0x400e80e0 9 0x400e8640 1 0x400e8324>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_sai2_tx_sync: IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC { + pinmux = <0x400e80e0 2 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_semc_data25: IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 { + pinmux = <0x400e80e0 0 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_in30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_IN30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_inout30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_enet_1g_tdata00: IOMUXC_GPIO_EMC_B2_11_ENET_1G_TDATA00 { + pinmux = <0x400e80e4 2 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B { + pinmux = <0x400e80e4 4 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio8_io21: IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 { + pinmux = <0x400e80e4 10 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21_cm7: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21_CM7 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_qtimer1_timer2: IOMUXC_GPIO_EMC_B2_11_QTIMER1_TIMER2 { + pinmux = <0x400e80e4 9 0x400e8644 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sai3_rx_sync: IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC { + pinmux = <0x400e80e4 3 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_semc_data26: IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 { + pinmux = <0x400e80e4 0 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sim1_trxd: IOMUXC_GPIO_EMC_B2_11_SIM1_TRXD { + pinmux = <0x400e80e4 8 0x400e869c 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_spdif_in: IOMUXC_GPIO_EMC_B2_11_SPDIF_IN { + pinmux = <0x400e80e4 1 0x400e86b4 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_in31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_IN31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_inout31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_enet_1g_tdata01: IOMUXC_GPIO_EMC_B2_12_ENET_1G_TDATA01 { + pinmux = <0x400e80e8 2 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_flexspi2_a_dqs: IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS { + pinmux = <0x400e80e8 4 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio8_io22: IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 { + pinmux = <0x400e80e8 10 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22_cm7: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22_CM7 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_qtimer1_timer3: IOMUXC_GPIO_EMC_B2_12_QTIMER1_TIMER3 { + pinmux = <0x400e80e8 9 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4030 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sai3_rx_bclk: IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK { + pinmux = <0x400e80e8 3 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_semc_data27: IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 { + pinmux = <0x400e80e8 0 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sim1_clk: IOMUXC_GPIO_EMC_B2_12_SIM1_CLK { + pinmux = <0x400e80e8 8 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_spdif_out: IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT { + pinmux = <0x400e80e8 1 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_in32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_IN32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_inout32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_enet_1g_tx_en: IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN { + pinmux = <0x400e80ec 2 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_flexspi2_a_data00: IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 { + pinmux = <0x400e80ec 4 0x400e857c 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio8_io23: IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 { + pinmux = <0x400e80ec 10 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23_cm7: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23_CM7 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_qtimer2_timer0: IOMUXC_GPIO_EMC_B2_13_QTIMER2_TIMER0 { + pinmux = <0x400e80ec 9 0x400e8648 1 0x400e8330>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sai3_rx_data: IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA { + pinmux = <0x400e80ec 3 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_semc_data28: IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 { + pinmux = <0x400e80ec 0 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sim1_rst_b: IOMUXC_GPIO_EMC_B2_13_SIM1_RST_B { + pinmux = <0x400e80ec 8 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_in33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_IN33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_inout33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_enet_1g_tx_clk_io: IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO { + pinmux = <0x400e80f0 2 0x400e84e8 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_flexspi2_a_data01: IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 { + pinmux = <0x400e80f0 4 0x400e8580 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio8_io24: IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 { + pinmux = <0x400e80f0 10 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24_cm7: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24_CM7 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_qtimer2_timer1: IOMUXC_GPIO_EMC_B2_14_QTIMER2_TIMER1 { + pinmux = <0x400e80f0 9 0x400e864c 1 0x400e8334>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sai3_tx_data: IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA { + pinmux = <0x400e80f0 3 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_semc_data29: IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 { + pinmux = <0x400e80f0 0 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sim1_sven: IOMUXC_GPIO_EMC_B2_14_SIM1_SVEN { + pinmux = <0x400e80f0 8 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_in34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_IN34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_inout34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_enet_1g_rdata00: IOMUXC_GPIO_EMC_B2_15_ENET_1G_RDATA00 { + pinmux = <0x400e80f4 2 0x400e84d0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_flexspi2_a_data02: IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 { + pinmux = <0x400e80f4 4 0x400e8584 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio8_io25: IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 { + pinmux = <0x400e80f4 10 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25_cm7: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25_CM7 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_qtimer2_timer2: IOMUXC_GPIO_EMC_B2_15_QTIMER2_TIMER2 { + pinmux = <0x400e80f4 9 0x400e8650 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sai3_tx_bclk: IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK { + pinmux = <0x400e80f4 3 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_semc_data30: IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 { + pinmux = <0x400e80f4 0 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sim1_pd: IOMUXC_GPIO_EMC_B2_15_SIM1_PD { + pinmux = <0x400e80f4 8 0x400e86a0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_in35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_IN35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_inout35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_enet_1g_rdata01: IOMUXC_GPIO_EMC_B2_16_ENET_1G_RDATA01 { + pinmux = <0x400e80f8 2 0x400e84d4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_flexspi2_a_data03: IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 { + pinmux = <0x400e80f8 4 0x400e8588 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio8_io26: IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 { + pinmux = <0x400e80f8 10 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26_cm7: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26_CM7 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_qtimer2_timer3: IOMUXC_GPIO_EMC_B2_16_QTIMER2_TIMER3 { + pinmux = <0x400e80f8 9 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4034 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sai3_tx_sync: IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC { + pinmux = <0x400e80f8 3 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_semc_data31: IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 { + pinmux = <0x400e80f8 0 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sim1_power_fail: IOMUXC_GPIO_EMC_B2_16_SIM1_POWER_FAIL { + pinmux = <0x400e80f8 8 0x400e86a4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_in14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_IN14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_enet_1g_rx_en: IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN { + pinmux = <0x400e80fc 2 0x400e84e0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_flexspi2_a_data04: IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 { + pinmux = <0x400e80fc 4 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio8_io27: IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 { + pinmux = <0x400e80fc 10 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27_cm7: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27_CM7 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_qtimer3_timer0: IOMUXC_GPIO_EMC_B2_17_QTIMER3_TIMER0 { + pinmux = <0x400e80fc 9 0x400e8654 1 0x400e8340>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_sai3_mclk: IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK { + pinmux = <0x400e80fc 3 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_semc_dm03: IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 { + pinmux = <0x400e80fc 0 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_wdog1_wdog_any: IOMUXC_GPIO_EMC_B2_17_WDOG1_WDOG_ANY { + pinmux = <0x400e80fc 8 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_in15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_IN15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_enet_1g_rx_er: IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER { + pinmux = <0x400e8100 2 0x400e84e4 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_ewm_ewm_out_b: IOMUXC_GPIO_EMC_B2_18_EWM_EWM_OUT_B { + pinmux = <0x400e8100 3 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi1_a_dqs: IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS { + pinmux = <0x400e8100 6 0x400e8550 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi2_a_data05: IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 { + pinmux = <0x400e8100 4 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio8_io28: IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 { + pinmux = <0x400e8100 10 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28_cm7: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28_CM7 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_18_QTIMER3_TIMER1 { + pinmux = <0x400e8100 9 0x400e8658 1 0x400e8344>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_semc_dqs4: IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 { + pinmux = <0x400e8100 0 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_wdog1_wdog_b: IOMUXC_GPIO_EMC_B2_18_WDOG1_WDOG_B { + pinmux = <0x400e8100 8 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_IN16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC { + pinmux = <0x400e8104 2 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_ref_clk1: IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK1 { + pinmux = <0x400e8104 3 0x400e84c4 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_MDC { + pinmux = <0x400e8104 1 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_flexspi2_a_data06: IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 { + pinmux = <0x400e8104 4 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio8_io29: IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 { + pinmux = <0x400e8104 10 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29_cm7: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29_CM7 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_qtimer3_timer2: IOMUXC_GPIO_EMC_B2_19_QTIMER3_TIMER2 { + pinmux = <0x400e8104 9 0x400e865c 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_semc_clkx00: IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 { + pinmux = <0x400e8104 0 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_1g_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO { + pinmux = <0x400e8108 2 0x400e84c8 1 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_MDIO { + pinmux = <0x400e8108 1 0x400e84ac 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_flexspi2_a_data07: IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 { + pinmux = <0x400e8108 4 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio8_io30: IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 { + pinmux = <0x400e8108 10 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30_cm7: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30_CM7 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_qtimer3_timer3: IOMUXC_GPIO_EMC_B2_20_QTIMER3_TIMER3 { + pinmux = <0x400e8108 9 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e4038 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_semc_clkx01: IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 { + pinmux = <0x400e8108 0 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_can3_tx: IOMUXC_LPSR_GPIO_LPSR_00_CAN3_TX { + pinmux = <0x40c08000 0 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_cm4_imxrt_txev: IOMUXC_LPSR_GPIO_LPSR_00_CM4_IMXRT_TXEV { + pinmux = <0x40c08000 3 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio12_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO12_IO00 { + pinmux = <0x40c08000 10 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio_mux6_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO_MUX6_IO00 { + pinmux = <0x40c08000 5 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_00_LPUART12_TX { + pinmux = <0x40c08000 6 0x40c080b0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mic_clk: IOMUXC_LPSR_GPIO_LPSR_00_MIC_CLK { + pinmux = <0x40c08000 1 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mqs_right: IOMUXC_LPSR_GPIO_LPSR_00_MQS_RIGHT { + pinmux = <0x40c08000 2 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_00_SAI4_MCLK { + pinmux = <0x40c08000 7 0x40c080c8 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_can3_rx: IOMUXC_LPSR_GPIO_LPSR_01_CAN3_RX { + pinmux = <0x40c08004 0 0x40c08080 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_cm4_imxrt_rxev: IOMUXC_LPSR_GPIO_LPSR_01_CM4_IMXRT_RXEV { + pinmux = <0x40c08004 3 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio12_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO12_IO01 { + pinmux = <0x40c08004 10 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO_MUX6_IO01 { + pinmux = <0x40c08004 5 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_01_LPUART12_RX { + pinmux = <0x40c08004 6 0x40c080ac 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_01_MIC_BITSTREAM00 { + pinmux = <0x40c08004 1 0x40c080b4 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mqs_left: IOMUXC_LPSR_GPIO_LPSR_01_MQS_LEFT { + pinmux = <0x40c08004 2 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio12_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO12_IO02 { + pinmux = <0x40c08008 10 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO_MUX6_IO02 { + pinmux = <0x40c08008 5 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_02_LPSPI5_SCK { + pinmux = <0x40c08008 1 0x40c08098 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_mqs_right: IOMUXC_LPSR_GPIO_LPSR_02_MQS_RIGHT { + pinmux = <0x40c08008 3 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_02_SAI4_TX_DATA { + pinmux = <0x40c08008 2 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_src_boot_mode00: IOMUXC_LPSR_GPIO_LPSR_02_SRC_BOOT_MODE00 { + pinmux = <0x40c08008 0 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio12_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO12_IO03 { + pinmux = <0x40c0800c 10 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO_MUX6_IO03 { + pinmux = <0x40c0800c 5 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_03_LPSPI5_PCS0 { + pinmux = <0x40c0800c 1 0x40c08094 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_mqs_left: IOMUXC_LPSR_GPIO_LPSR_03_MQS_LEFT { + pinmux = <0x40c0800c 3 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_03_SAI4_TX_SYNC { + pinmux = <0x40c0800c 2 0x40c080dc 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_src_boot_mode01: IOMUXC_LPSR_GPIO_LPSR_03_SRC_BOOT_MODE01 { + pinmux = <0x40c0800c 0 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio12_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO12_IO04 { + pinmux = <0x40c08010 10 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO_MUX6_IO04 { + pinmux = <0x40c08010 5 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_04_LPI2C5_SDA { + pinmux = <0x40c08010 0 0x40c08088 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_04_LPSPI5_SDO { + pinmux = <0x40c08010 1 0x40c080a0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_04_LPUART11_TX { + pinmux = <0x40c08010 6 0x40c080a8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart12_rts_b: IOMUXC_LPSR_GPIO_LPSR_04_LPUART12_RTS_B { + pinmux = <0x40c08010 3 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_04_SAI4_TX_BCLK { + pinmux = <0x40c08010 2 0x40c080d8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio12_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO12_IO05 { + pinmux = <0x40c08014 10 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO_MUX6_IO05 { + pinmux = <0x40c08014 5 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_05_LPI2C5_SCL { + pinmux = <0x40c08014 0 0x40c08084 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_05_LPSPI5_SDI { + pinmux = <0x40c08014 1 0x40c0809c 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_05_LPUART11_RX { + pinmux = <0x40c08014 6 0x40c080a4 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart12_cts_b: IOMUXC_LPSR_GPIO_LPSR_05_LPUART12_CTS_B { + pinmux = <0x40c08014 3 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_05_SAI4_MCLK { + pinmux = <0x40c08014 2 0x40c080c8 1 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_can3_tx: IOMUXC_LPSR_GPIO_LPSR_06_CAN3_TX { + pinmux = <0x40c08018 6 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio12_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO12_IO06 { + pinmux = <0x40c08018 10 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO_MUX6_IO06 { + pinmux = <0x40c08018 5 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_06_LPI2C6_SDA { + pinmux = <0x40c08018 0 0x40c08090 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi5_pcs1: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI5_PCS1 { + pinmux = <0x40c08018 8 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi6_pcs3: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI6_PCS3 { + pinmux = <0x40c08018 4 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_06_LPUART12_TX { + pinmux = <0x40c08018 3 0x40c080b0 1 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_06_PIT2_TRIGGER03 { + pinmux = <0x40c08018 7 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_06_SAI4_RX_DATA { + pinmux = <0x40c08018 2 0x40c080d0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_can3_rx: IOMUXC_LPSR_GPIO_LPSR_07_CAN3_RX { + pinmux = <0x40c0801c 6 0x40c08080 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio12_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO12_IO07 { + pinmux = <0x40c0801c 10 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO_MUX6_IO07 { + pinmux = <0x40c0801c 5 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_07_LPI2C6_SCL { + pinmux = <0x40c0801c 0 0x40c0808c 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi5_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI5_PCS2 { + pinmux = <0x40c0801c 8 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi6_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI6_PCS2 { + pinmux = <0x40c0801c 4 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_07_LPUART12_RX { + pinmux = <0x40c0801c 3 0x40c080ac 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_07_PIT2_TRIGGER02 { + pinmux = <0x40c0801c 7 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_07_SAI4_RX_BCLK { + pinmux = <0x40c0801c 2 0x40c080cc 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_can3_tx: IOMUXC_LPSR_GPIO_LPSR_08_CAN3_TX { + pinmux = <0x40c08020 1 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio12_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO12_IO08 { + pinmux = <0x40c08020 10 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO_MUX6_IO08 { + pinmux = <0x40c08020 5 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_08_LPI2C5_SDA { + pinmux = <0x40c08020 6 0x40c08088 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi5_pcs3: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI5_PCS3 { + pinmux = <0x40c08020 8 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi6_pcs1: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI6_PCS1 { + pinmux = <0x40c08020 4 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_08_LPUART11_TX { + pinmux = <0x40c08020 0 0x40c080a8 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_mic_clk: IOMUXC_LPSR_GPIO_LPSR_08_MIC_CLK { + pinmux = <0x40c08020 3 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_08_PIT2_TRIGGER01 { + pinmux = <0x40c08020 7 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_08_SAI4_RX_SYNC { + pinmux = <0x40c08020 2 0x40c080d4 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_can3_rx: IOMUXC_LPSR_GPIO_LPSR_09_CAN3_RX { + pinmux = <0x40c08024 1 0x40c08080 2 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio12_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO12_IO09 { + pinmux = <0x40c08024 10 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO_MUX6_IO09 { + pinmux = <0x40c08024 5 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_09_LPI2C5_SCL { + pinmux = <0x40c08024 6 0x40c08084 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpspi6_pcs0: IOMUXC_LPSR_GPIO_LPSR_09_LPSPI6_PCS0 { + pinmux = <0x40c08024 4 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_09_LPUART11_RX { + pinmux = <0x40c08024 0 0x40c080a4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_09_MIC_BITSTREAM00 { + pinmux = <0x40c08024 3 0x40c080b4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_09_PIT2_TRIGGER00 { + pinmux = <0x40c08024 2 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_09_SAI4_TX_DATA { + pinmux = <0x40c08024 7 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio12_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO12_IO10 { + pinmux = <0x40c08028 10 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO_MUX6_IO10 { + pinmux = <0x40c08028 5 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_jtag_mux_trstb: IOMUXC_LPSR_GPIO_LPSR_10_JTAG_MUX_TRSTB { + pinmux = <0x40c08028 0 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c5_scls: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C5_SCLS { + pinmux = <0x40c08028 6 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C6_SDA { + pinmux = <0x40c08028 2 0x40c08090 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpspi6_sck: IOMUXC_LPSR_GPIO_LPSR_10_LPSPI6_SCK { + pinmux = <0x40c08028 4 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart11_cts_b: IOMUXC_LPSR_GPIO_LPSR_10_LPUART11_CTS_B { + pinmux = <0x40c08028 1 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_10_LPUART12_TX { + pinmux = <0x40c08028 8 0x40c080b0 2 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_10_MIC_BITSTREAM01 { + pinmux = <0x40c08028 3 0x40c080b8 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_10_SAI4_TX_SYNC { + pinmux = <0x40c08028 7 0x40c080dc 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_arm_trace_swo: IOMUXC_LPSR_GPIO_LPSR_11_ARM_TRACE_SWO { + pinmux = <0x40c0802c 7 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio12_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO12_IO11 { + pinmux = <0x40c0802c 10 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO_MUX6_IO11 { + pinmux = <0x40c0802c 5 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_jtag_mux_tdo: IOMUXC_LPSR_GPIO_LPSR_11_JTAG_MUX_TDO { + pinmux = <0x40c0802c 0 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c5_sdas: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C5_SDAS { + pinmux = <0x40c0802c 6 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C6_SCL { + pinmux = <0x40c0802c 2 0x40c0808c 1 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpspi6_sdo: IOMUXC_LPSR_GPIO_LPSR_11_LPSPI6_SDO { + pinmux = <0x40c0802c 4 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart11_rts_b: IOMUXC_LPSR_GPIO_LPSR_11_LPUART11_RTS_B { + pinmux = <0x40c0802c 1 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_11_LPUART12_RX { + pinmux = <0x40c0802c 8 0x40c080ac 2 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_11_MIC_BITSTREAM02 { + pinmux = <0x40c0802c 3 0x40c080bc 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio12_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO12_IO12 { + pinmux = <0x40c08030 10 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO_MUX6_IO12 { + pinmux = <0x40c08030 5 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_jtag_mux_tdi: IOMUXC_LPSR_GPIO_LPSR_12_JTAG_MUX_TDI { + pinmux = <0x40c08030 0 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpi2c5_hreq: IOMUXC_LPSR_GPIO_LPSR_12_LPI2C5_HREQ { + pinmux = <0x40c08030 6 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI5_SCK { + pinmux = <0x40c08030 8 0x40c08098 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi6_sdi: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI6_SDI { + pinmux = <0x40c08030 4 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_12_MIC_BITSTREAM03 { + pinmux = <0x40c08030 3 0x40c080c0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_12_PIT2_TRIGGER00 { + pinmux = <0x40c08030 1 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_12_SAI4_TX_BCLK { + pinmux = <0x40c08030 7 0x40c080d8 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio12_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO12_IO13 { + pinmux = <0x40c08034 10 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO_MUX6_IO13 { + pinmux = <0x40c08034 5 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_jtag_mux_mod: IOMUXC_LPSR_GPIO_LPSR_13_JTAG_MUX_MOD { + pinmux = <0x40c08034 0 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_13_LPSPI5_PCS0 { + pinmux = <0x40c08034 8 0x40c08094 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_13_MIC_BITSTREAM01 { + pinmux = <0x40c08034 1 0x40c080b8 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_13_PIT2_TRIGGER01 { + pinmux = <0x40c08034 2 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_13_SAI4_RX_DATA { + pinmux = <0x40c08034 7 0x40c080d0 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio12_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO12_IO14 { + pinmux = <0x40c08038 10 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO_MUX6_IO14 { + pinmux = <0x40c08038 5 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_jtag_mux_tck: IOMUXC_LPSR_GPIO_LPSR_14_JTAG_MUX_TCK { + pinmux = <0x40c08038 0 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_14_LPSPI5_SDO { + pinmux = <0x40c08038 8 0x40c080a0 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_14_MIC_BITSTREAM02 { + pinmux = <0x40c08038 1 0x40c080bc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_14_PIT2_TRIGGER02 { + pinmux = <0x40c08038 2 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_14_SAI4_RX_BCLK { + pinmux = <0x40c08038 7 0x40c080cc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio12_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO12_IO15 { + pinmux = <0x40c0803c 10 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO_MUX6_IO15 { + pinmux = <0x40c0803c 5 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_jtag_mux_tms: IOMUXC_LPSR_GPIO_LPSR_15_JTAG_MUX_TMS { + pinmux = <0x40c0803c 0 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_15_LPSPI5_SDI { + pinmux = <0x40c0803c 8 0x40c0809c 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_15_MIC_BITSTREAM03 { + pinmux = <0x40c0803c 1 0x40c080c0 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_15_PIT2_TRIGGER03 { + pinmux = <0x40c0803c 2 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_15_SAI4_RX_SYNC { + pinmux = <0x40c0803c 7 0x40c080d4 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi2_a_ss0_b: IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B { + pinmux = <0x400e819c 6 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio10_io03: IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 { + pinmux = <0x400e819c 10 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio_mux4_io03: IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 { + pinmux = <0x400e819c 5 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpt4_capture1: IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 { + pinmux = <0x400e819c 3 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_kpp_row07: IOMUXC_GPIO_SD_B1_00_KPP_ROW07 { + pinmux = <0x400e819c 8 0x400e85a8 1 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc1_cmd: IOMUXC_GPIO_SD_B1_00_USDHC1_CMD { + pinmux = <0x400e819c 0 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi2_a_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK { + pinmux = <0x400e81a0 6 0x400e858c 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio10_io04: IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 { + pinmux = <0x400e81a0 10 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio_mux4_io04: IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 { + pinmux = <0x400e81a0 5 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpt4_capture2: IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 { + pinmux = <0x400e81a0 3 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_kpp_col07: IOMUXC_GPIO_SD_B1_01_KPP_COL07 { + pinmux = <0x400e81a0 8 0x400e85a0 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc1_clk: IOMUXC_GPIO_SD_B1_01_USDHC1_CLK { + pinmux = <0x400e81a0 0 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_in21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_inout21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81a4 9 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi2_a_data00: IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 { + pinmux = <0x400e81a4 6 0x400e857c 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio10_io05: IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 { + pinmux = <0x400e81a4 10 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio_mux4_io05: IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 { + pinmux = <0x400e81a4 5 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpt4_compare1: IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 { + pinmux = <0x400e81a4 3 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_kpp_row06: IOMUXC_GPIO_SD_B1_02_KPP_ROW06 { + pinmux = <0x400e81a4 8 0x400e85a4 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc1_data0: IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 { + pinmux = <0x400e81a4 0 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_in22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_inout22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi1_b_ss1_b: IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B { + pinmux = <0x400e81a8 9 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi2_a_data01: IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 { + pinmux = <0x400e81a8 6 0x400e8580 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio10_io06: IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 { + pinmux = <0x400e81a8 10 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio_mux4_io06: IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 { + pinmux = <0x400e81a8 5 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpt4_compare2: IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 { + pinmux = <0x400e81a8 3 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_kpp_col06: IOMUXC_GPIO_SD_B1_03_KPP_COL06 { + pinmux = <0x400e81a8 8 0x400e859c 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc1_data1: IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 { + pinmux = <0x400e81a8 0 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_in23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_inout23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81ac 8 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi2_a_data02: IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 { + pinmux = <0x400e81ac 6 0x400e8584 1 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio10_io07: IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 { + pinmux = <0x400e81ac 10 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio_mux4_io07: IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 { + pinmux = <0x400e81ac 5 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpt4_compare3: IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 { + pinmux = <0x400e81ac 3 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc1_data2: IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 { + pinmux = <0x400e81ac 0 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_in24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_inout24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi1_b_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS { + pinmux = <0x400e81b0 8 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi2_a_data03: IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 { + pinmux = <0x400e81b0 6 0x400e8588 1 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio10_io08: IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 { + pinmux = <0x400e81b0 10 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio_mux4_io08: IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 { + pinmux = <0x400e81b0 5 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpt4_clk: IOMUXC_GPIO_SD_B1_05_GPT4_CLK { + pinmux = <0x400e81b0 3 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc1_data3: IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 { + pinmux = <0x400e81b0 0 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_in25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_inout25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_enet_1g_rx_en: IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN { + pinmux = <0x400e81b4 2 0x400e84e0 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_flexspi1_b_data03: IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 { + pinmux = <0x400e81b4 1 0x400e8570 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio10_io09: IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 { + pinmux = <0x400e81b4 10 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio_mux4_io09: IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 { + pinmux = <0x400e81b4 5 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpspi4_sck: IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK { + pinmux = <0x400e81b4 4 0x400e8610 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpuart9_tx: IOMUXC_GPIO_SD_B2_00_LPUART9_TX { + pinmux = <0x400e81b4 3 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_usdhc2_data3: IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 { + pinmux = <0x400e81b4 0 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_enet_1g_rx_clk: IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK { + pinmux = <0x400e81b8 2 0x400e84cc 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_flexspi1_b_data02: IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 { + pinmux = <0x400e81b8 1 0x400e856c 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio10_io10: IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 { + pinmux = <0x400e81b8 10 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio_mux4_io10: IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 { + pinmux = <0x400e81b8 5 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpspi4_pcs0: IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 { + pinmux = <0x400e81b8 4 0x400e860c 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpuart9_rx: IOMUXC_GPIO_SD_B2_01_LPUART9_RX { + pinmux = <0x400e81b8 3 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_usdhc2_data2: IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 { + pinmux = <0x400e81b8 0 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_enet_1g_rdata00: IOMUXC_GPIO_SD_B2_02_ENET_1G_RDATA00 { + pinmux = <0x400e81bc 2 0x400e84d0 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_flexspi1_b_data01: IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 { + pinmux = <0x400e81bc 1 0x400e8568 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio10_io11: IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 { + pinmux = <0x400e81bc 10 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio_mux4_io11: IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 { + pinmux = <0x400e81bc 5 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpspi4_sdo: IOMUXC_GPIO_SD_B2_02_LPSPI4_SDO { + pinmux = <0x400e81bc 4 0x400e8618 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpuart9_cts_b: IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B { + pinmux = <0x400e81bc 3 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_usdhc2_data1: IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 { + pinmux = <0x400e81bc 0 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_enet_1g_rdata01: IOMUXC_GPIO_SD_B2_03_ENET_1G_RDATA01 { + pinmux = <0x400e81c0 2 0x400e84d4 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_flexspi1_b_data00: IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 { + pinmux = <0x400e81c0 1 0x400e8564 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio10_io12: IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 { + pinmux = <0x400e81c0 10 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio_mux4_io12: IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 { + pinmux = <0x400e81c0 5 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpspi4_sdi: IOMUXC_GPIO_SD_B2_03_LPSPI4_SDI { + pinmux = <0x400e81c0 4 0x400e8614 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpuart9_rts_b: IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B { + pinmux = <0x400e81c0 3 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_usdhc2_data0: IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 { + pinmux = <0x400e81c0 0 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_enet_1g_rdata02: IOMUXC_GPIO_SD_B2_04_ENET_1G_RDATA02 { + pinmux = <0x400e81c4 2 0x400e84d8 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81c4 3 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_b_sclk: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK { + pinmux = <0x400e81c4 1 0x400e8578 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio10_io13: IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 { + pinmux = <0x400e81c4 10 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio_mux4_io13: IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 { + pinmux = <0x400e81c4 5 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_lpspi4_pcs1: IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 { + pinmux = <0x400e81c4 4 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_usdhc2_clk: IOMUXC_GPIO_SD_B2_04_USDHC2_CLK { + pinmux = <0x400e81c4 0 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_enet_1g_rdata03: IOMUXC_GPIO_SD_B2_05_ENET_1G_RDATA03 { + pinmux = <0x400e81c8 2 0x400e84dc 1 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_a_dqs: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS { + pinmux = <0x400e81c8 1 0x400e8550 2 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81c8 3 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio10_io14: IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 { + pinmux = <0x400e81c8 10 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio_mux4_io14: IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 { + pinmux = <0x400e81c8 5 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_lpspi4_pcs2: IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 { + pinmux = <0x400e81c8 4 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_usdhc2_cmd: IOMUXC_GPIO_SD_B2_05_USDHC2_CMD { + pinmux = <0x400e81c8 0 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_enet_1g_tdata03: IOMUXC_GPIO_SD_B2_06_ENET_1G_TDATA03 { + pinmux = <0x400e81cc 2 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_flexspi1_a_ss0_b: IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B { + pinmux = <0x400e81cc 1 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio10_io15: IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 { + pinmux = <0x400e81cc 10 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio_mux4_io15: IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 { + pinmux = <0x400e81cc 5 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpt6_capture1: IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 { + pinmux = <0x400e81cc 4 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_lpspi4_pcs3: IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 { + pinmux = <0x400e81cc 3 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B { + pinmux = <0x400e81cc 0 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_1g_tdata02: IOMUXC_GPIO_SD_B2_07_ENET_1G_TDATA02 { + pinmux = <0x400e81d0 2 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_tx_er: IOMUXC_GPIO_SD_B2_07_ENET_TX_ER { + pinmux = <0x400e81d0 8 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_flexspi1_a_sclk: IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK { + pinmux = <0x400e81d0 1 0x400e8574 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio10_io16: IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 { + pinmux = <0x400e81d0 10 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio_mux4_io16: IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 { + pinmux = <0x400e81d0 5 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpt6_capture2: IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 { + pinmux = <0x400e81d0 4 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpspi2_sck: IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK { + pinmux = <0x400e81d0 6 0x400e85e4 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpuart3_cts_b: IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B { + pinmux = <0x400e81d0 3 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_usdhc2_strobe: IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE { + pinmux = <0x400e81d0 0 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_enet_1g_tdata01: IOMUXC_GPIO_SD_B2_08_ENET_1G_TDATA01 { + pinmux = <0x400e81d4 2 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_flexspi1_a_data00: IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 { + pinmux = <0x400e81d4 1 0x400e8554 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio10_io17: IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 { + pinmux = <0x400e81d4 10 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio_mux4_io17: IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 { + pinmux = <0x400e81d4 5 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpt6_compare1: IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 { + pinmux = <0x400e81d4 4 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpspi2_pcs0: IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 { + pinmux = <0x400e81d4 6 0x400e85dc 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpuart3_rts_b: IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B { + pinmux = <0x400e81d4 3 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_usdhc2_data4: IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 { + pinmux = <0x400e81d4 0 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_enet_1g_tdata00: IOMUXC_GPIO_SD_B2_09_ENET_1G_TDATA00 { + pinmux = <0x400e81d8 2 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_flexspi1_a_data01: IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 { + pinmux = <0x400e81d8 1 0x400e8558 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio10_io18: IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 { + pinmux = <0x400e81d8 10 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio_mux4_io18: IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 { + pinmux = <0x400e81d8 5 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpt6_compare2: IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 { + pinmux = <0x400e81d8 4 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpspi2_sdo: IOMUXC_GPIO_SD_B2_09_LPSPI2_SDO { + pinmux = <0x400e81d8 6 0x400e85ec 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpuart5_cts_b: IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B { + pinmux = <0x400e81d8 3 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_usdhc2_data5: IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 { + pinmux = <0x400e81d8 0 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_enet_1g_tx_en: IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN { + pinmux = <0x400e81dc 2 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_flexspi1_a_data02: IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 { + pinmux = <0x400e81dc 1 0x400e855c 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio10_io19: IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 { + pinmux = <0x400e81dc 10 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio_mux4_io19: IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 { + pinmux = <0x400e81dc 5 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpt6_compare3: IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 { + pinmux = <0x400e81dc 4 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpspi2_sdi: IOMUXC_GPIO_SD_B2_10_LPSPI2_SDI { + pinmux = <0x400e81dc 6 0x400e85e8 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpuart5_rts_b: IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B { + pinmux = <0x400e81dc 3 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_usdhc2_data6: IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 { + pinmux = <0x400e81dc 0 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_ref_clk1: IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e81e0 3 0x400e84c4 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_tx_clk_io: IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e81e0 2 0x400e84e8 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_flexspi1_a_data03: IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 { + pinmux = <0x400e81e0 1 0x400e8560 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio10_io20: IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 { + pinmux = <0x400e81e0 10 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio_mux4_io20: IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 { + pinmux = <0x400e81e0 5 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpt6_clk: IOMUXC_GPIO_SD_B2_11_GPT6_CLK { + pinmux = <0x400e81e0 4 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_lpspi2_pcs1: IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 { + pinmux = <0x400e81e0 6 0x400e85e0 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_usdhc2_data7: IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 { + pinmux = <0x400e81e0 0 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03: IOMUXC_SNVS_GPIO_SNVS_00_DIG_GPIO13_IO03 { + pinmux = <0x40c9400c 5 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_snvs_lp_tamper00: IOMUXC_SNVS_GPIO_SNVS_00_DIG_SNVS_LP_TAMPER00 { + pinmux = <0x40c9400c 0 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04: IOMUXC_SNVS_GPIO_SNVS_01_DIG_GPIO13_IO04 { + pinmux = <0x40c94010 5 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_snvs_lp_tamper01: IOMUXC_SNVS_GPIO_SNVS_01_DIG_SNVS_LP_TAMPER01 { + pinmux = <0x40c94010 0 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05: IOMUXC_SNVS_GPIO_SNVS_02_DIG_GPIO13_IO05 { + pinmux = <0x40c94014 5 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_snvs_lp_tamper02: IOMUXC_SNVS_GPIO_SNVS_02_DIG_SNVS_LP_TAMPER02 { + pinmux = <0x40c94014 0 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06: IOMUXC_SNVS_GPIO_SNVS_03_DIG_GPIO13_IO06 { + pinmux = <0x40c94018 5 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_snvs_lp_tamper03: IOMUXC_SNVS_GPIO_SNVS_03_DIG_SNVS_LP_TAMPER03 { + pinmux = <0x40c94018 0 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07: IOMUXC_SNVS_GPIO_SNVS_04_DIG_GPIO13_IO07 { + pinmux = <0x40c9401c 5 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_snvs_lp_tamper04: IOMUXC_SNVS_GPIO_SNVS_04_DIG_SNVS_LP_TAMPER04 { + pinmux = <0x40c9401c 0 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08: IOMUXC_SNVS_GPIO_SNVS_05_DIG_GPIO13_IO08 { + pinmux = <0x40c94020 5 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_snvs_lp_tamper05: IOMUXC_SNVS_GPIO_SNVS_05_DIG_SNVS_LP_TAMPER05 { + pinmux = <0x40c94020 0 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09: IOMUXC_SNVS_GPIO_SNVS_06_DIG_GPIO13_IO09 { + pinmux = <0x40c94024 5 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_snvs_lp_tamper06: IOMUXC_SNVS_GPIO_SNVS_06_DIG_SNVS_LP_TAMPER06 { + pinmux = <0x40c94024 0 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10: IOMUXC_SNVS_GPIO_SNVS_07_DIG_GPIO13_IO10 { + pinmux = <0x40c94028 5 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_snvs_lp_tamper07: IOMUXC_SNVS_GPIO_SNVS_07_DIG_SNVS_LP_TAMPER07 { + pinmux = <0x40c94028 0 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11: IOMUXC_SNVS_GPIO_SNVS_08_DIG_GPIO13_IO11 { + pinmux = <0x40c9402c 5 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_snvs_lp_tamper08: IOMUXC_SNVS_GPIO_SNVS_08_DIG_SNVS_LP_TAMPER08 { + pinmux = <0x40c9402c 0 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12: IOMUXC_SNVS_GPIO_SNVS_09_DIG_GPIO13_IO12 { + pinmux = <0x40c94030 5 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_snvs_lp_tamper09: IOMUXC_SNVS_GPIO_SNVS_09_DIG_SNVS_LP_TAMPER09 { + pinmux = <0x40c94030 0 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_dig_src_reset_b: IOMUXC_SNVS_ONOFF_DIG_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x40c9403c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_gpio13_io01: IOMUXC_SNVS_PMIC_ON_REQ_DIG_GPIO13_IO01 { + pinmux = <0x40c94004 5 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_snvs_lp_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ { + pinmux = <0x40c94004 0 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_gpio13_io02: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_GPIO13_IO02 { + pinmux = <0x40c94008 5 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_pgmc_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_PGMC_PMIC_VSTBY_REQ { + pinmux = <0x40c94008 0 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_dig_src_por_b: IOMUXC_SNVS_POR_B_DIG_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x40c94038>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_dig_test_mode: IOMUXC_SNVS_TEST_MODE_DIG_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x40c94034>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_dig_gpio13_io00: IOMUXC_SNVS_WAKEUP_DIG_GPIO13_IO00 { + pinmux = <0x40c94000 5 0x0 0 0x40c94040>; + pin-snvs; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1165dvm6a-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1165dvm6a-pinctrl.dtsi new file mode 100644 index 000000000..1cdae917f --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1165dvm6a-pinctrl.dtsi @@ -0,0 +1,5984 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1165DVM6A + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_00_acmp1_in1: IOMUXC_GPIO_AD_00_ACMP1_IN1 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_can2_tx: IOMUXC_GPIO_AD_00_CAN2_TX { + pinmux = <0x400e810c 1 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_enet_1g_1588_event1_in: IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN { + pinmux = <0x400e810c 2 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexio2_flexio00: IOMUXC_GPIO_AD_00_FLEXIO2_FLEXIO00 { + pinmux = <0x400e810c 8 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexpwm1_pwm0_a: IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A { + pinmux = <0x400e810c 4 0x400e8500 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexspi2_b_ss1_b: IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B { + pinmux = <0x400e810c 9 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio8_io31: IOMUXC_GPIO_AD_00_GPIO8_IO31 { + pinmux = <0x400e810c 10 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31_cm7: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31_CM7 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpt2_capture1: IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 { + pinmux = <0x400e810c 3 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_lpuart7_tx: IOMUXC_GPIO_AD_00_LPUART7_TX { + pinmux = <0x400e810c 6 0x400e8630 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_sim1_trxd: IOMUXC_GPIO_AD_00_SIM1_TRXD { + pinmux = <0x400e810c 0 0x400e869c 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_acmp1_in2: IOMUXC_GPIO_AD_01_ACMP1_IN2 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_can2_rx: IOMUXC_GPIO_AD_01_CAN2_RX { + pinmux = <0x400e8110 1 0x400e849c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_enet_1g_1588_event1_out: IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT { + pinmux = <0x400e8110 2 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexio2_flexio01: IOMUXC_GPIO_AD_01_FLEXIO2_FLEXIO01 { + pinmux = <0x400e8110 8 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexpwm1_pwm0_b: IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B { + pinmux = <0x400e8110 4 0x400e850c 1 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexspi2_a_ss1_b: IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B { + pinmux = <0x400e8110 9 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio9_io00: IOMUXC_GPIO_AD_01_GPIO9_IO00 { + pinmux = <0x400e8110 10 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00_cm7: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00_CM7 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpt2_capture2: IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 { + pinmux = <0x400e8110 3 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_lpuart7_rx: IOMUXC_GPIO_AD_01_LPUART7_RX { + pinmux = <0x400e8110 6 0x400e862c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_sim1_clk: IOMUXC_GPIO_AD_01_SIM1_CLK { + pinmux = <0x400e8110 0 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_acmp1_in3: IOMUXC_GPIO_AD_02_ACMP1_IN3 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_enet_1g_1588_event2_in: IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN { + pinmux = <0x400e8114 2 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexio2_flexio02: IOMUXC_GPIO_AD_02_FLEXIO2_FLEXIO02 { + pinmux = <0x400e8114 8 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexpwm1_pwm1_a: IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A { + pinmux = <0x400e8114 4 0x400e8504 1 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio9_io01: IOMUXC_GPIO_AD_02_GPIO9_IO01 { + pinmux = <0x400e8114 10 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01_cm7: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01_CM7 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpt2_compare1: IOMUXC_GPIO_AD_02_GPT2_COMPARE1 { + pinmux = <0x400e8114 3 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart7_cts_b: IOMUXC_GPIO_AD_02_LPUART7_CTS_B { + pinmux = <0x400e8114 1 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart8_tx: IOMUXC_GPIO_AD_02_LPUART8_TX { + pinmux = <0x400e8114 6 0x400e8638 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_sim1_rst_b: IOMUXC_GPIO_AD_02_SIM1_RST_B { + pinmux = <0x400e8114 0 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_video_mux_ext_dcic1: IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e8114 9 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_acmp1_in4: IOMUXC_GPIO_AD_03_ACMP1_IN4 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_enet_1g_1588_event2_out: IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT { + pinmux = <0x400e8118 2 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexio2_flexio03: IOMUXC_GPIO_AD_03_FLEXIO2_FLEXIO03 { + pinmux = <0x400e8118 8 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexpwm1_pwm1_b: IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B { + pinmux = <0x400e8118 4 0x400e8510 1 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio9_io02: IOMUXC_GPIO_AD_03_GPIO9_IO02 { + pinmux = <0x400e8118 10 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02_cm7: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02_CM7 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpt2_compare2: IOMUXC_GPIO_AD_03_GPT2_COMPARE2 { + pinmux = <0x400e8118 3 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart7_rts_b: IOMUXC_GPIO_AD_03_LPUART7_RTS_B { + pinmux = <0x400e8118 1 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart8_rx: IOMUXC_GPIO_AD_03_LPUART8_RX { + pinmux = <0x400e8118 6 0x400e8634 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_sim1_sven: IOMUXC_GPIO_AD_03_SIM1_SVEN { + pinmux = <0x400e8118 0 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_video_mux_ext_dcic2: IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8118 9 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_acmp2_in1: IOMUXC_GPIO_AD_04_ACMP2_IN1 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_enet_1g_1588_event3_in: IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN { + pinmux = <0x400e811c 2 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexio2_flexio04: IOMUXC_GPIO_AD_04_FLEXIO2_FLEXIO04 { + pinmux = <0x400e811c 8 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexpwm1_pwm2_a: IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A { + pinmux = <0x400e811c 4 0x400e8508 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio9_io03: IOMUXC_GPIO_AD_04_GPIO9_IO03 { + pinmux = <0x400e811c 10 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03_cm7: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03_CM7 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpt2_compare3: IOMUXC_GPIO_AD_04_GPT2_COMPARE3 { + pinmux = <0x400e811c 3 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_lpuart8_cts_b: IOMUXC_GPIO_AD_04_LPUART8_CTS_B { + pinmux = <0x400e811c 1 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_qtimer4_timer0: IOMUXC_GPIO_AD_04_QTIMER4_TIMER0 { + pinmux = <0x400e811c 9 0x400e8660 1 0x400e8360>; + pin-pue; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_sim1_pd: IOMUXC_GPIO_AD_04_SIM1_PD { + pinmux = <0x400e811c 0 0x400e86a0 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_wdog1_wdog_b: IOMUXC_GPIO_AD_04_WDOG1_WDOG_B { + pinmux = <0x400e811c 6 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_acmp2_in2: IOMUXC_GPIO_AD_05_ACMP2_IN2 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_enet_1g_1588_event3_out: IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT { + pinmux = <0x400e8120 2 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexio2_flexio05: IOMUXC_GPIO_AD_05_FLEXIO2_FLEXIO05 { + pinmux = <0x400e8120 8 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexpwm1_pwm2_b: IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B { + pinmux = <0x400e8120 4 0x400e8514 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio9_io04: IOMUXC_GPIO_AD_05_GPIO9_IO04 { + pinmux = <0x400e8120 10 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04_cm7: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04_CM7 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpt2_clk: IOMUXC_GPIO_AD_05_GPT2_CLK { + pinmux = <0x400e8120 3 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_lpuart8_rts_b: IOMUXC_GPIO_AD_05_LPUART8_RTS_B { + pinmux = <0x400e8120 1 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_qtimer4_timer1: IOMUXC_GPIO_AD_05_QTIMER4_TIMER1 { + pinmux = <0x400e8120 9 0x400e8664 1 0x400e8364>; + pin-pue; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_sim1_power_fail: IOMUXC_GPIO_AD_05_SIM1_POWER_FAIL { + pinmux = <0x400e8120 0 0x400e86a4 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_wdog2_wdog_b: IOMUXC_GPIO_AD_05_WDOG2_WDOG_B { + pinmux = <0x400e8120 6 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_adc1_ch0a: IOMUXC_GPIO_AD_06_ADC1_CH0A { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_can1_tx: IOMUXC_GPIO_AD_06_CAN1_TX { + pinmux = <0x400e8124 1 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_enet_1588_event1_in: IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN { + pinmux = <0x400e8124 6 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexio2_flexio06: IOMUXC_GPIO_AD_06_FLEXIO2_FLEXIO06 { + pinmux = <0x400e8124 8 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexpwm1_pwm0_x: IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X { + pinmux = <0x400e8124 11 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio9_io05: IOMUXC_GPIO_AD_06_GPIO9_IO05 { + pinmux = <0x400e8124 10 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05_cm7: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05_CM7 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpt3_capture1: IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 { + pinmux = <0x400e8124 3 0x400e8590 1 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_qtimer4_timer2: IOMUXC_GPIO_AD_06_QTIMER4_TIMER2 { + pinmux = <0x400e8124 9 0x400e8668 0 0x400e8368>; + pin-pue; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_sim2_trxd: IOMUXC_GPIO_AD_06_SIM2_TRXD { + pinmux = <0x400e8124 2 0x400e86a8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_usb_otg2_oc: IOMUXC_GPIO_AD_06_USB_OTG2_OC { + pinmux = <0x400e8124 0 0x400e86b8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_adc1_ch0b: IOMUXC_GPIO_AD_07_ADC1_CH0B { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_can1_rx: IOMUXC_GPIO_AD_07_CAN1_RX { + pinmux = <0x400e8128 1 0x400e8498 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_enet_1588_event1_out: IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT { + pinmux = <0x400e8128 6 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexio2_flexio07: IOMUXC_GPIO_AD_07_FLEXIO2_FLEXIO07 { + pinmux = <0x400e8128 8 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexpwm1_pwm1_x: IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X { + pinmux = <0x400e8128 11 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio9_io06: IOMUXC_GPIO_AD_07_GPIO9_IO06 { + pinmux = <0x400e8128 10 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06_cm7: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06_CM7 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpt3_capture2: IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 { + pinmux = <0x400e8128 3 0x400e8594 1 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_qtimer4_timer3: IOMUXC_GPIO_AD_07_QTIMER4_TIMER3 { + pinmux = <0x400e8128 9 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e403c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_sim2_clk: IOMUXC_GPIO_AD_07_SIM2_CLK { + pinmux = <0x400e8128 2 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_usb_otg2_pwr: IOMUXC_GPIO_AD_07_USB_OTG2_PWR { + pinmux = <0x400e8128 0 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_adc1_ch1a: IOMUXC_GPIO_AD_08_ADC1_CH1A { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_enet_1588_event2_in: IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN { + pinmux = <0x400e812c 6 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexio2_flexio08: IOMUXC_GPIO_AD_08_FLEXIO2_FLEXIO08 { + pinmux = <0x400e812c 8 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexpwm1_pwm2_x: IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X { + pinmux = <0x400e812c 11 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio9_io07: IOMUXC_GPIO_AD_08_GPIO9_IO07 { + pinmux = <0x400e812c 10 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07_cm7: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07_CM7 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpt3_compare1: IOMUXC_GPIO_AD_08_GPT3_COMPARE1 { + pinmux = <0x400e812c 3 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_lpi2c1_scl: IOMUXC_GPIO_AD_08_LPI2C1_SCL { + pinmux = <0x400e812c 1 0x400e85ac 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_sim2_rst_b: IOMUXC_GPIO_AD_08_SIM2_RST_B { + pinmux = <0x400e812c 2 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_usbphy2_otg_id: IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID { + pinmux = <0x400e812c 0 0x400e86c4 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_adc1_ch1b: IOMUXC_GPIO_AD_09_ADC1_CH1B { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_enet_1588_event2_out: IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT { + pinmux = <0x400e8130 6 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexio2_flexio09: IOMUXC_GPIO_AD_09_FLEXIO2_FLEXIO09 { + pinmux = <0x400e8130 8 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexpwm1_pwm3_x: IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X { + pinmux = <0x400e8130 11 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio9_io08: IOMUXC_GPIO_AD_09_GPIO9_IO08 { + pinmux = <0x400e8130 10 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08_cm7: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08_CM7 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpt3_compare2: IOMUXC_GPIO_AD_09_GPT3_COMPARE2 { + pinmux = <0x400e8130 3 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_lpi2c1_sda: IOMUXC_GPIO_AD_09_LPI2C1_SDA { + pinmux = <0x400e8130 1 0x400e85b0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_sim2_sven: IOMUXC_GPIO_AD_09_SIM2_SVEN { + pinmux = <0x400e8130 2 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_usbphy1_otg_id: IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID { + pinmux = <0x400e8130 0 0x400e86c0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_adc1_ch2a: IOMUXC_GPIO_AD_10_ADC1_CH2A { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_enet_1588_event3_in: IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN { + pinmux = <0x400e8134 6 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexio2_flexio10: IOMUXC_GPIO_AD_10_FLEXIO2_FLEXIO10 { + pinmux = <0x400e8134 8 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexpwm2_pwm0_x: IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X { + pinmux = <0x400e8134 11 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio9_io09: IOMUXC_GPIO_AD_10_GPIO9_IO09 { + pinmux = <0x400e8134 10 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09_cm7: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09_CM7 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpt3_compare3: IOMUXC_GPIO_AD_10_GPT3_COMPARE3 { + pinmux = <0x400e8134 3 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_lpi2c1_scls: IOMUXC_GPIO_AD_10_LPI2C1_SCLS { + pinmux = <0x400e8134 1 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_sim2_pd: IOMUXC_GPIO_AD_10_SIM2_PD { + pinmux = <0x400e8134 2 0x400e86ac 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_usb_otg1_pwr: IOMUXC_GPIO_AD_10_USB_OTG1_PWR { + pinmux = <0x400e8134 0 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_adc1_ch2b: IOMUXC_GPIO_AD_11_ADC1_CH2B { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_enet_1588_event3_out: IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT { + pinmux = <0x400e8138 6 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexio2_flexio11: IOMUXC_GPIO_AD_11_FLEXIO2_FLEXIO11 { + pinmux = <0x400e8138 8 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexpwm2_pwm1_x: IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X { + pinmux = <0x400e8138 11 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio9_io10: IOMUXC_GPIO_AD_11_GPIO9_IO10 { + pinmux = <0x400e8138 10 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10_cm7: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10_CM7 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpt3_clk: IOMUXC_GPIO_AD_11_GPT3_CLK { + pinmux = <0x400e8138 3 0x400e8598 1 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_lpi2c1_sdas: IOMUXC_GPIO_AD_11_LPI2C1_SDAS { + pinmux = <0x400e8138 1 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_sim2_power_fail: IOMUXC_GPIO_AD_11_SIM2_POWER_FAIL { + pinmux = <0x400e8138 2 0x400e86b0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_usb_otg1_oc: IOMUXC_GPIO_AD_11_USB_OTG1_OC { + pinmux = <0x400e8138 0 0x400e86bc 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc1_ch3a: IOMUXC_GPIO_AD_12_ADC1_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc2_ch3a: IOMUXC_GPIO_AD_12_ADC2_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_enet_tdata03: IOMUXC_GPIO_AD_12_ENET_TDATA03 { + pinmux = <0x400e813c 6 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_ewm_ewm_out_b: IOMUXC_GPIO_AD_12_EWM_EWM_OUT_B { + pinmux = <0x400e813c 9 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexio2_flexio12: IOMUXC_GPIO_AD_12_FLEXIO2_FLEXIO12 { + pinmux = <0x400e813c 8 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexpwm2_pwm2_x: IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X { + pinmux = <0x400e813c 11 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexspi1_b_data03: IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 { + pinmux = <0x400e813c 3 0x400e8570 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio9_io11: IOMUXC_GPIO_AD_12_GPIO9_IO11 { + pinmux = <0x400e813c 10 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11_cm7: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11_CM7 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpt1_capture1: IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 { + pinmux = <0x400e813c 2 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_lpi2c1_hreq: IOMUXC_GPIO_AD_12_LPI2C1_HREQ { + pinmux = <0x400e813c 1 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_spdif_lock: IOMUXC_GPIO_AD_12_SPDIF_LOCK { + pinmux = <0x400e813c 0 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc1_ch3b: IOMUXC_GPIO_AD_13_ADC1_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc2_ch3b: IOMUXC_GPIO_AD_13_ADC2_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_enet_tdata02: IOMUXC_GPIO_AD_13_ENET_TDATA02 { + pinmux = <0x400e8140 6 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexio2_flexio13: IOMUXC_GPIO_AD_13_FLEXIO2_FLEXIO13 { + pinmux = <0x400e8140 8 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexpwm2_pwm3_x: IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X { + pinmux = <0x400e8140 11 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexspi1_b_data02: IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 { + pinmux = <0x400e8140 3 0x400e856c 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio9_io12: IOMUXC_GPIO_AD_13_GPIO9_IO12 { + pinmux = <0x400e8140 10 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12_cm7: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12_CM7 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpt1_capture2: IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 { + pinmux = <0x400e8140 2 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_pit1_trigger00: IOMUXC_GPIO_AD_13_PIT1_TRIGGER00 { + pinmux = <0x400e8140 1 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_spdif_sr_clk: IOMUXC_GPIO_AD_13_SPDIF_SR_CLK { + pinmux = <0x400e8140 0 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc1_ch4a: IOMUXC_GPIO_AD_14_ADC1_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc2_ch4a: IOMUXC_GPIO_AD_14_ADC2_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_ccm_enet_ref_clk_25m: IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8144 9 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_enet_rx_clk: IOMUXC_GPIO_AD_14_ENET_RX_CLK { + pinmux = <0x400e8144 6 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexio2_flexio14: IOMUXC_GPIO_AD_14_FLEXIO2_FLEXIO14 { + pinmux = <0x400e8144 8 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexpwm3_pwm0_x: IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X { + pinmux = <0x400e8144 11 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexspi1_b_data01: IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 { + pinmux = <0x400e8144 3 0x400e8568 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio9_io13: IOMUXC_GPIO_AD_14_GPIO9_IO13 { + pinmux = <0x400e8144 10 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13_cm7: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13_CM7 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpt1_compare1: IOMUXC_GPIO_AD_14_GPT1_COMPARE1 { + pinmux = <0x400e8144 2 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_spdif_ext_clk: IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK { + pinmux = <0x400e8144 0 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc1_ch4b: IOMUXC_GPIO_AD_15_ADC1_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc2_ch4b: IOMUXC_GPIO_AD_15_ADC2_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_enet_tx_er: IOMUXC_GPIO_AD_15_ENET_TX_ER { + pinmux = <0x400e8148 6 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexio2_flexio15: IOMUXC_GPIO_AD_15_FLEXIO2_FLEXIO15 { + pinmux = <0x400e8148 8 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexpwm3_pwm1_x: IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X { + pinmux = <0x400e8148 11 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexspi1_b_data00: IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 { + pinmux = <0x400e8148 3 0x400e8564 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio9_io14: IOMUXC_GPIO_AD_15_GPIO9_IO14 { + pinmux = <0x400e8148 10 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14_cm7: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14_CM7 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpt1_compare2: IOMUXC_GPIO_AD_15_GPT1_COMPARE2 { + pinmux = <0x400e8148 2 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_lpuart10_tx: IOMUXC_GPIO_AD_15_LPUART10_TX { + pinmux = <0x400e8148 1 0x400e8628 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_spdif_in: IOMUXC_GPIO_AD_15_SPDIF_IN { + pinmux = <0x400e8148 0 0x400e86b4 1 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc1_ch5a: IOMUXC_GPIO_AD_16_ADC1_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc2_ch5a: IOMUXC_GPIO_AD_16_ADC2_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_1g_mdc: IOMUXC_GPIO_AD_16_ENET_1G_MDC { + pinmux = <0x400e814c 9 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_rdata03: IOMUXC_GPIO_AD_16_ENET_RDATA03 { + pinmux = <0x400e814c 6 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexio2_flexio16: IOMUXC_GPIO_AD_16_FLEXIO2_FLEXIO16 { + pinmux = <0x400e814c 8 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexpwm3_pwm2_x: IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X { + pinmux = <0x400e814c 11 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexspi1_b_sclk: IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK { + pinmux = <0x400e814c 3 0x400e8578 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio9_io15: IOMUXC_GPIO_AD_16_GPIO9_IO15 { + pinmux = <0x400e814c 10 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15_cm7: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15_CM7 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpt1_compare3: IOMUXC_GPIO_AD_16_GPT1_COMPARE3 { + pinmux = <0x400e814c 2 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_lpuart10_rx: IOMUXC_GPIO_AD_16_LPUART10_RX { + pinmux = <0x400e814c 1 0x400e8624 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_spdif_out: IOMUXC_GPIO_AD_16_SPDIF_OUT { + pinmux = <0x400e814c 0 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_acmp1_cmpo: IOMUXC_GPIO_AD_17_ACMP1_CMPO { + pinmux = <0x400e8150 1 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc1_ch5b: IOMUXC_GPIO_AD_17_ADC1_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc2_ch5b: IOMUXC_GPIO_AD_17_ADC2_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_1g_mdio: IOMUXC_GPIO_AD_17_ENET_1G_MDIO { + pinmux = <0x400e8150 9 0x400e84c8 2 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_rdata02: IOMUXC_GPIO_AD_17_ENET_RDATA02 { + pinmux = <0x400e8150 6 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexio2_flexio17: IOMUXC_GPIO_AD_17_FLEXIO2_FLEXIO17 { + pinmux = <0x400e8150 8 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexpwm3_pwm3_x: IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X { + pinmux = <0x400e8150 11 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexspi1_a_dqs: IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS { + pinmux = <0x400e8150 3 0x400e8550 1 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio9_io16: IOMUXC_GPIO_AD_17_GPIO9_IO16 { + pinmux = <0x400e8150 10 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16_cm7: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16_CM7 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpt1_clk: IOMUXC_GPIO_AD_17_GPT1_CLK { + pinmux = <0x400e8150 2 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_sai1_mclk: IOMUXC_GPIO_AD_17_SAI1_MCLK { + pinmux = <0x400e8150 0 0x400e866c 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_acmp2_cmpo: IOMUXC_GPIO_AD_18_ACMP2_CMPO { + pinmux = <0x400e8154 1 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_adc2_ch0a: IOMUXC_GPIO_AD_18_ADC2_CH0A { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_enet_crs: IOMUXC_GPIO_AD_18_ENET_CRS { + pinmux = <0x400e8154 6 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexio2_flexio18: IOMUXC_GPIO_AD_18_FLEXIO2_FLEXIO18 { + pinmux = <0x400e8154 8 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexpwm4_pwm0_x: IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X { + pinmux = <0x400e8154 11 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexspi1_a_ss0_b: IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B { + pinmux = <0x400e8154 3 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio9_io17: IOMUXC_GPIO_AD_18_GPIO9_IO17 { + pinmux = <0x400e8154 10 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17_cm7: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17_CM7 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpi2c2_scl: IOMUXC_GPIO_AD_18_LPI2C2_SCL { + pinmux = <0x400e8154 9 0x400e85b4 1 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpspi1_pcs1: IOMUXC_GPIO_AD_18_LPSPI1_PCS1 { + pinmux = <0x400e8154 2 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_sai1_rx_sync: IOMUXC_GPIO_AD_18_SAI1_RX_SYNC { + pinmux = <0x400e8154 0 0x400e8678 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_acmp3_cmpo: IOMUXC_GPIO_AD_19_ACMP3_CMPO { + pinmux = <0x400e8158 1 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_adc2_ch0b: IOMUXC_GPIO_AD_19_ADC2_CH0B { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_enet_col: IOMUXC_GPIO_AD_19_ENET_COL { + pinmux = <0x400e8158 6 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexio2_flexio19: IOMUXC_GPIO_AD_19_FLEXIO2_FLEXIO19 { + pinmux = <0x400e8158 8 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexpwm4_pwm1_x: IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X { + pinmux = <0x400e8158 11 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexspi1_a_sclk: IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK { + pinmux = <0x400e8158 3 0x400e8574 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio9_io18: IOMUXC_GPIO_AD_19_GPIO9_IO18 { + pinmux = <0x400e8158 10 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18_cm7: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18_CM7 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpi2c2_sda: IOMUXC_GPIO_AD_19_LPI2C2_SDA { + pinmux = <0x400e8158 9 0x400e85b8 1 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpspi1_pcs2: IOMUXC_GPIO_AD_19_LPSPI1_PCS2 { + pinmux = <0x400e8158 2 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_sai1_rx_bclk: IOMUXC_GPIO_AD_19_SAI1_RX_BCLK { + pinmux = <0x400e8158 0 0x400e8670 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_acmp4_cmpo: IOMUXC_GPIO_AD_20_ACMP4_CMPO { + pinmux = <0x400e815c 1 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_adc2_ch1a: IOMUXC_GPIO_AD_20_ADC2_CH1A { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexio2_flexio20: IOMUXC_GPIO_AD_20_FLEXIO2_FLEXIO20 { + pinmux = <0x400e815c 8 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexpwm4_pwm2_x: IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X { + pinmux = <0x400e815c 11 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexspi1_a_data00: IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 { + pinmux = <0x400e815c 3 0x400e8554 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio9_io19: IOMUXC_GPIO_AD_20_GPIO9_IO19 { + pinmux = <0x400e815c 10 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19_cm7: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19_CM7 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_kpp_row07: IOMUXC_GPIO_AD_20_KPP_ROW07 { + pinmux = <0x400e815c 6 0x400e85a8 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_lpspi1_pcs3: IOMUXC_GPIO_AD_20_LPSPI1_PCS3 { + pinmux = <0x400e815c 2 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_sai1_rx_data00: IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 { + pinmux = <0x400e815c 0 0x400e8674 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_adc2_ch1b: IOMUXC_GPIO_AD_21_ADC2_CH1B { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexio2_flexio21: IOMUXC_GPIO_AD_21_FLEXIO2_FLEXIO21 { + pinmux = <0x400e8160 8 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexpwm4_pwm3_x: IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X { + pinmux = <0x400e8160 11 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexspi1_a_data01: IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 { + pinmux = <0x400e8160 3 0x400e8558 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio9_io20: IOMUXC_GPIO_AD_21_GPIO9_IO20 { + pinmux = <0x400e8160 10 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20_cm7: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20_CM7 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_kpp_col07: IOMUXC_GPIO_AD_21_KPP_COL07 { + pinmux = <0x400e8160 6 0x400e85a0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_lpspi2_pcs1: IOMUXC_GPIO_AD_21_LPSPI2_PCS1 { + pinmux = <0x400e8160 2 0x400e85e0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_sai1_tx_data00: IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 { + pinmux = <0x400e8160 0 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_adc2_ch2a: IOMUXC_GPIO_AD_22_ADC2_CH2A { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexio2_flexio22: IOMUXC_GPIO_AD_22_FLEXIO2_FLEXIO22 { + pinmux = <0x400e8164 8 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexspi1_a_data02: IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 { + pinmux = <0x400e8164 3 0x400e855c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio9_io21: IOMUXC_GPIO_AD_22_GPIO9_IO21 { + pinmux = <0x400e8164 10 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21_cm7: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21_CM7 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_kpp_row06: IOMUXC_GPIO_AD_22_KPP_ROW06 { + pinmux = <0x400e8164 6 0x400e85a4 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_lpspi2_pcs2: IOMUXC_GPIO_AD_22_LPSPI2_PCS2 { + pinmux = <0x400e8164 2 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_sai1_tx_bclk: IOMUXC_GPIO_AD_22_SAI1_TX_BCLK { + pinmux = <0x400e8164 0 0x400e867c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_adc2_ch2b: IOMUXC_GPIO_AD_23_ADC2_CH2B { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexio2_flexio23: IOMUXC_GPIO_AD_23_FLEXIO2_FLEXIO23 { + pinmux = <0x400e8168 8 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexspi1_a_data03: IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 { + pinmux = <0x400e8168 3 0x400e8560 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio9_io22: IOMUXC_GPIO_AD_23_GPIO9_IO22 { + pinmux = <0x400e8168 10 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22_cm7: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22_CM7 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_kpp_col06: IOMUXC_GPIO_AD_23_KPP_COL06 { + pinmux = <0x400e8168 6 0x400e859c 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_lpspi2_pcs3: IOMUXC_GPIO_AD_23_LPSPI2_PCS3 { + pinmux = <0x400e8168 2 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_sai1_tx_sync: IOMUXC_GPIO_AD_23_SAI1_TX_SYNC { + pinmux = <0x400e8168 0 0x400e8680 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_adc2_ch6a: IOMUXC_GPIO_AD_24_ADC2_CH6A { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_enet_rx_en: IOMUXC_GPIO_AD_24_ENET_RX_EN { + pinmux = <0x400e816c 3 0x400e84b8 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexio2_flexio24: IOMUXC_GPIO_AD_24_FLEXIO2_FLEXIO24 { + pinmux = <0x400e816c 8 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexpwm2_pwm0_a: IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A { + pinmux = <0x400e816c 4 0x400e8518 1 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio9_io23: IOMUXC_GPIO_AD_24_GPIO9_IO23 { + pinmux = <0x400e816c 10 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23_cm7: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23_CM7 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_kpp_row05: IOMUXC_GPIO_AD_24_KPP_ROW05 { + pinmux = <0x400e816c 6 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpi2c4_scl: IOMUXC_GPIO_AD_24_LPI2C4_SCL { + pinmux = <0x400e816c 9 0x400e85c4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpspi2_sck: IOMUXC_GPIO_AD_24_LPSPI2_SCK { + pinmux = <0x400e816c 1 0x400e85e4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpuart1_tx: IOMUXC_GPIO_AD_24_LPUART1_TX { + pinmux = <0x400e816c 0 0x400e8620 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_adc2_ch6b: IOMUXC_GPIO_AD_25_ADC2_CH6B { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_enet_rx_er: IOMUXC_GPIO_AD_25_ENET_RX_ER { + pinmux = <0x400e8170 3 0x400e84bc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexio2_flexio25: IOMUXC_GPIO_AD_25_FLEXIO2_FLEXIO25 { + pinmux = <0x400e8170 8 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexpwm2_pwm0_b: IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B { + pinmux = <0x400e8170 4 0x400e8524 1 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio9_io24: IOMUXC_GPIO_AD_25_GPIO9_IO24 { + pinmux = <0x400e8170 10 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24_cm7: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24_CM7 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_kpp_col05: IOMUXC_GPIO_AD_25_KPP_COL05 { + pinmux = <0x400e8170 6 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpi2c4_sda: IOMUXC_GPIO_AD_25_LPI2C4_SDA { + pinmux = <0x400e8170 9 0x400e85c8 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpspi2_pcs0: IOMUXC_GPIO_AD_25_LPSPI2_PCS0 { + pinmux = <0x400e8170 1 0x400e85dc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpuart1_rx: IOMUXC_GPIO_AD_25_LPUART1_RX { + pinmux = <0x400e8170 0 0x400e861c 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_acmp2_in3: IOMUXC_GPIO_AD_26_ACMP2_IN3 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_enet_rdata00: IOMUXC_GPIO_AD_26_ENET_RDATA00 { + pinmux = <0x400e8174 3 0x400e84b0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexio2_flexio26: IOMUXC_GPIO_AD_26_FLEXIO2_FLEXIO26 { + pinmux = <0x400e8174 8 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexpwm2_pwm1_a: IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A { + pinmux = <0x400e8174 4 0x400e851c 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio9_io25: IOMUXC_GPIO_AD_26_GPIO9_IO25 { + pinmux = <0x400e8174 10 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25_cm7: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25_CM7 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_kpp_row04: IOMUXC_GPIO_AD_26_KPP_ROW04 { + pinmux = <0x400e8174 6 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpspi2_sdo: IOMUXC_GPIO_AD_26_LPSPI2_SDO { + pinmux = <0x400e8174 1 0x400e85ec 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpuart1_cts_b: IOMUXC_GPIO_AD_26_LPUART1_CTS_B { + pinmux = <0x400e8174 0 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_semc_csx01: IOMUXC_GPIO_AD_26_SEMC_CSX01 { + pinmux = <0x400e8174 2 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_usdhc2_cd_b: IOMUXC_GPIO_AD_26_USDHC2_CD_B { + pinmux = <0x400e8174 11 0x400e86d0 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_acmp2_in4: IOMUXC_GPIO_AD_27_ACMP2_IN4 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_enet_rdata01: IOMUXC_GPIO_AD_27_ENET_RDATA01 { + pinmux = <0x400e8178 3 0x400e84b4 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexio2_flexio27: IOMUXC_GPIO_AD_27_FLEXIO2_FLEXIO27 { + pinmux = <0x400e8178 8 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexpwm2_pwm1_b: IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B { + pinmux = <0x400e8178 4 0x400e8528 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio9_io26: IOMUXC_GPIO_AD_27_GPIO9_IO26 { + pinmux = <0x400e8178 10 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26_cm7: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26_CM7 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_kpp_col04: IOMUXC_GPIO_AD_27_KPP_COL04 { + pinmux = <0x400e8178 6 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpspi2_sdi: IOMUXC_GPIO_AD_27_LPSPI2_SDI { + pinmux = <0x400e8178 1 0x400e85e8 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpuart1_rts_b: IOMUXC_GPIO_AD_27_LPUART1_RTS_B { + pinmux = <0x400e8178 0 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_semc_csx02: IOMUXC_GPIO_AD_27_SEMC_CSX02 { + pinmux = <0x400e8178 2 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_usdhc2_wp: IOMUXC_GPIO_AD_27_USDHC2_WP { + pinmux = <0x400e8178 11 0x400e86d4 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_acmp3_in1: IOMUXC_GPIO_AD_28_ACMP3_IN1 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_enet_tx_en: IOMUXC_GPIO_AD_28_ENET_TX_EN { + pinmux = <0x400e817c 3 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexio2_flexio28: IOMUXC_GPIO_AD_28_FLEXIO2_FLEXIO28 { + pinmux = <0x400e817c 8 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexpwm2_pwm2_a: IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A { + pinmux = <0x400e817c 4 0x400e8520 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio9_io27: IOMUXC_GPIO_AD_28_GPIO9_IO27 { + pinmux = <0x400e817c 10 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27_cm7: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27_CM7 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_kpp_row03: IOMUXC_GPIO_AD_28_KPP_ROW03 { + pinmux = <0x400e817c 6 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpspi1_sck: IOMUXC_GPIO_AD_28_LPSPI1_SCK { + pinmux = <0x400e817c 0 0x400e85d0 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpuart5_tx: IOMUXC_GPIO_AD_28_LPUART5_TX { + pinmux = <0x400e817c 1 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_semc_csx03: IOMUXC_GPIO_AD_28_SEMC_CSX03 { + pinmux = <0x400e817c 2 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_usdhc2_vselect: IOMUXC_GPIO_AD_28_USDHC2_VSELECT { + pinmux = <0x400e817c 11 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_video_mux_ext_dcic1: IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e817c 9 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_acmp3_in2: IOMUXC_GPIO_AD_29_ACMP3_IN2 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_ref_clk: IOMUXC_GPIO_AD_29_ENET_REF_CLK { + pinmux = <0x400e8180 2 0x400e84a8 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_tx_clk: IOMUXC_GPIO_AD_29_ENET_TX_CLK { + pinmux = <0x400e8180 3 0x400e84c0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexio2_flexio29: IOMUXC_GPIO_AD_29_FLEXIO2_FLEXIO29 { + pinmux = <0x400e8180 8 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexpwm2_pwm2_b: IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B { + pinmux = <0x400e8180 4 0x400e852c 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio9_io28: IOMUXC_GPIO_AD_29_GPIO9_IO28 { + pinmux = <0x400e8180 10 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28_cm7: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28_CM7 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_kpp_col03: IOMUXC_GPIO_AD_29_KPP_COL03 { + pinmux = <0x400e8180 6 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpspi1_pcs0: IOMUXC_GPIO_AD_29_LPSPI1_PCS0 { + pinmux = <0x400e8180 0 0x400e85cc 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpuart5_rx: IOMUXC_GPIO_AD_29_LPUART5_RX { + pinmux = <0x400e8180 1 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_usdhc2_reset_b: IOMUXC_GPIO_AD_29_USDHC2_RESET_B { + pinmux = <0x400e8180 11 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_video_mux_ext_dcic2: IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8180 9 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_acmp3_in3: IOMUXC_GPIO_AD_30_ACMP3_IN3 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_can2_tx: IOMUXC_GPIO_AD_30_CAN2_TX { + pinmux = <0x400e8184 2 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_enet_tdata00: IOMUXC_GPIO_AD_30_ENET_TDATA00 { + pinmux = <0x400e8184 3 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_flexio2_flexio30: IOMUXC_GPIO_AD_30_FLEXIO2_FLEXIO30 { + pinmux = <0x400e8184 8 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio9_io29: IOMUXC_GPIO_AD_30_GPIO9_IO29 { + pinmux = <0x400e8184 10 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29_cm7: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29_CM7 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_kpp_row02: IOMUXC_GPIO_AD_30_KPP_ROW02 { + pinmux = <0x400e8184 6 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpspi1_sdo: IOMUXC_GPIO_AD_30_LPSPI1_SDO { + pinmux = <0x400e8184 0 0x400e85d8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpuart3_tx: IOMUXC_GPIO_AD_30_LPUART3_TX { + pinmux = <0x400e8184 4 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_usb_otg2_oc: IOMUXC_GPIO_AD_30_USB_OTG2_OC { + pinmux = <0x400e8184 1 0x400e86b8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_AD_30_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e8184 9 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_acmp3_in4: IOMUXC_GPIO_AD_31_ACMP3_IN4 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_can2_rx: IOMUXC_GPIO_AD_31_CAN2_RX { + pinmux = <0x400e8188 2 0x400e849c 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_enet_tdata01: IOMUXC_GPIO_AD_31_ENET_TDATA01 { + pinmux = <0x400e8188 3 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_flexio2_flexio31: IOMUXC_GPIO_AD_31_FLEXIO2_FLEXIO31 { + pinmux = <0x400e8188 8 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio9_io30: IOMUXC_GPIO_AD_31_GPIO9_IO30 { + pinmux = <0x400e8188 10 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30_cm7: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30_CM7 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_kpp_col02: IOMUXC_GPIO_AD_31_KPP_COL02 { + pinmux = <0x400e8188 6 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpspi1_sdi: IOMUXC_GPIO_AD_31_LPSPI1_SDI { + pinmux = <0x400e8188 0 0x400e85d4 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpuart3_rx: IOMUXC_GPIO_AD_31_LPUART3_RX { + pinmux = <0x400e8188 4 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_usb_otg2_pwr: IOMUXC_GPIO_AD_31_USB_OTG2_PWR { + pinmux = <0x400e8188 1 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_AD_31_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8188 9 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_acmp4_in1: IOMUXC_GPIO_AD_32_ACMP4_IN1 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_1g_mdc: IOMUXC_GPIO_AD_32_ENET_1G_MDC { + pinmux = <0x400e818c 9 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_mdc: IOMUXC_GPIO_AD_32_ENET_MDC { + pinmux = <0x400e818c 3 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio9_io31: IOMUXC_GPIO_AD_32_GPIO9_IO31 { + pinmux = <0x400e818c 10 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31_cm7: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31_CM7 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_kpp_row01: IOMUXC_GPIO_AD_32_KPP_ROW01 { + pinmux = <0x400e818c 6 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpi2c1_scl: IOMUXC_GPIO_AD_32_LPI2C1_SCL { + pinmux = <0x400e818c 0 0x400e85ac 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpuart10_tx: IOMUXC_GPIO_AD_32_LPUART10_TX { + pinmux = <0x400e818c 8 0x400e8628 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_pgmc_pmic_ready: IOMUXC_GPIO_AD_32_PGMC_PMIC_READY { + pinmux = <0x400e818c 2 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usbphy2_otg_id: IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID { + pinmux = <0x400e818c 1 0x400e86c4 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usdhc1_cd_b: IOMUXC_GPIO_AD_32_USDHC1_CD_B { + pinmux = <0x400e818c 4 0x400e86c8 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_acmp4_in2: IOMUXC_GPIO_AD_33_ACMP4_IN2 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_1g_mdio: IOMUXC_GPIO_AD_33_ENET_1G_MDIO { + pinmux = <0x400e8190 9 0x400e84c8 3 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_mdio: IOMUXC_GPIO_AD_33_ENET_MDIO { + pinmux = <0x400e8190 3 0x400e84ac 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio10_io00: IOMUXC_GPIO_AD_33_GPIO10_IO00 { + pinmux = <0x400e8190 10 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio_mux4_io00: IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_kpp_col01: IOMUXC_GPIO_AD_33_KPP_COL01 { + pinmux = <0x400e8190 6 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpi2c1_sda: IOMUXC_GPIO_AD_33_LPI2C1_SDA { + pinmux = <0x400e8190 0 0x400e85b0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpuart10_rx: IOMUXC_GPIO_AD_33_LPUART10_RX { + pinmux = <0x400e8190 8 0x400e8624 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usbphy1_otg_id: IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID { + pinmux = <0x400e8190 1 0x400e86c0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usdhc1_wp: IOMUXC_GPIO_AD_33_USDHC1_WP { + pinmux = <0x400e8190 4 0x400e86cc 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_in17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_IN17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_inout17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_acmp4_in3: IOMUXC_GPIO_AD_34_ACMP4_IN3 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN { + pinmux = <0x400e8194 3 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1g_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN { + pinmux = <0x400e8194 0 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio10_io01: IOMUXC_GPIO_AD_34_GPIO10_IO01 { + pinmux = <0x400e8194 10 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio_mux4_io01: IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_kpp_row00: IOMUXC_GPIO_AD_34_KPP_ROW00 { + pinmux = <0x400e8194 6 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_lpuart10_cts_b: IOMUXC_GPIO_AD_34_LPUART10_CTS_B { + pinmux = <0x400e8194 8 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usb_otg1_pwr: IOMUXC_GPIO_AD_34_USB_OTG1_PWR { + pinmux = <0x400e8194 1 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usdhc1_vselect: IOMUXC_GPIO_AD_34_USDHC1_VSELECT { + pinmux = <0x400e8194 4 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_wdog1_wdog_any: IOMUXC_GPIO_AD_34_WDOG1_WDOG_ANY { + pinmux = <0x400e8194 9 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_in18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_IN18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_inout18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_acmp4_in4: IOMUXC_GPIO_AD_35_ACMP4_IN4 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT { + pinmux = <0x400e8198 3 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1g_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT { + pinmux = <0x400e8198 0 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_flexspi1_b_ss1_b: IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B { + pinmux = <0x400e8198 9 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio10_io02: IOMUXC_GPIO_AD_35_GPIO10_IO02 { + pinmux = <0x400e8198 10 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio_mux4_io02: IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_kpp_col00: IOMUXC_GPIO_AD_35_KPP_COL00 { + pinmux = <0x400e8198 6 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_lpuart10_rts_b: IOMUXC_GPIO_AD_35_LPUART10_RTS_B { + pinmux = <0x400e8198 8 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usb_otg1_oc: IOMUXC_GPIO_AD_35_USB_OTG1_OC { + pinmux = <0x400e8198 1 0x400e86bc 1 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usdhc1_reset_b: IOMUXC_GPIO_AD_35_USDHC1_RESET_B { + pinmux = <0x400e8198 4 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_in19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_IN19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_inout19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_INOUT19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_enet_1g_rx_en: IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN { + pinmux = <0x400e81e4 1 0x400e84e0 2 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio10_io21: IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 { + pinmux = <0x400e81e4 10 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio_mux4_io21: IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 { + pinmux = <0x400e81e4 5 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_qtimer1_timer0: IOMUXC_GPIO_DISP_B1_00_QTIMER1_TIMER0 { + pinmux = <0x400e81e4 3 0x400e863c 2 0x400e8428>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_in26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_IN26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_inout26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_clk: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK { + pinmux = <0x400e81e8 1 0x400e84cc 2 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_er: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER { + pinmux = <0x400e81e8 2 0x400e84e4 1 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio10_io22: IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 { + pinmux = <0x400e81e8 10 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio_mux4_io22: IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 { + pinmux = <0x400e81e8 5 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_qtimer1_timer1: IOMUXC_GPIO_DISP_B1_01_QTIMER1_TIMER1 { + pinmux = <0x400e81e8 3 0x400e8640 2 0x400e842c>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_in27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_IN27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_inout27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_enet_1g_rdata00: IOMUXC_GPIO_DISP_B1_02_ENET_1G_RDATA00 { + pinmux = <0x400e81ec 1 0x400e84d0 2 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio10_io23: IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 { + pinmux = <0x400e81ec 10 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio_mux4_io23: IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 { + pinmux = <0x400e81ec 5 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpi2c3_scl: IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL { + pinmux = <0x400e81ec 2 0x400e85bc 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpuart1_tx: IOMUXC_GPIO_DISP_B1_02_LPUART1_TX { + pinmux = <0x400e81ec 9 0x400e8620 1 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_qtimer1_timer2: IOMUXC_GPIO_DISP_B1_02_QTIMER1_TIMER2 { + pinmux = <0x400e81ec 3 0x400e8644 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_in28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_IN28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_inout28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_enet_1g_rdata01: IOMUXC_GPIO_DISP_B1_03_ENET_1G_RDATA01 { + pinmux = <0x400e81f0 1 0x400e84d4 2 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio10_io24: IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 { + pinmux = <0x400e81f0 10 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio_mux4_io24: IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 { + pinmux = <0x400e81f0 5 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpi2c3_sda: IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA { + pinmux = <0x400e81f0 2 0x400e85c0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpuart1_rx: IOMUXC_GPIO_DISP_B1_03_LPUART1_RX { + pinmux = <0x400e81f0 9 0x400e861c 1 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_qtimer2_timer0: IOMUXC_GPIO_DISP_B1_03_QTIMER2_TIMER0 { + pinmux = <0x400e81f0 3 0x400e8648 2 0x400e8434>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_in29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_IN29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_inout29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_enet_1g_rdata02: IOMUXC_GPIO_DISP_B1_04_ENET_1G_RDATA02 { + pinmux = <0x400e81f4 1 0x400e84d8 2 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio10_io25: IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 { + pinmux = <0x400e81f4 10 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio_mux4_io25: IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 { + pinmux = <0x400e81f4 5 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpspi3_sck: IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK { + pinmux = <0x400e81f4 9 0x400e8600 1 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpuart4_rx: IOMUXC_GPIO_DISP_B1_04_LPUART4_RX { + pinmux = <0x400e81f4 2 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_qtimer2_timer1: IOMUXC_GPIO_DISP_B1_04_QTIMER2_TIMER1 { + pinmux = <0x400e81f4 3 0x400e864c 2 0x400e8438>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_in30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_IN30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_inout30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_enet_1g_rdata03: IOMUXC_GPIO_DISP_B1_05_ENET_1G_RDATA03 { + pinmux = <0x400e81f8 1 0x400e84dc 2 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio10_io26: IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 { + pinmux = <0x400e81f8 10 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio_mux4_io26: IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 { + pinmux = <0x400e81f8 5 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpspi3_sdi: IOMUXC_GPIO_DISP_B1_05_LPSPI3_SDI { + pinmux = <0x400e81f8 9 0x400e8604 1 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpuart4_cts_b: IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B { + pinmux = <0x400e81f8 2 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_qtimer2_timer2: IOMUXC_GPIO_DISP_B1_05_QTIMER2_TIMER2 { + pinmux = <0x400e81f8 3 0x400e8650 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_in31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_IN31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_inout31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_enet_1g_tdata03: IOMUXC_GPIO_DISP_B1_06_ENET_1G_TDATA03 { + pinmux = <0x400e81fc 1 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio10_io27: IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 { + pinmux = <0x400e81fc 10 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio_mux4_io27: IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 { + pinmux = <0x400e81fc 5 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpspi3_sdo: IOMUXC_GPIO_DISP_B1_06_LPSPI3_SDO { + pinmux = <0x400e81fc 9 0x400e8608 1 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpuart4_tx: IOMUXC_GPIO_DISP_B1_06_LPUART4_TX { + pinmux = <0x400e81fc 2 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_qtimer3_timer0: IOMUXC_GPIO_DISP_B1_06_QTIMER3_TIMER0 { + pinmux = <0x400e81fc 3 0x400e8654 2 0x400e8440>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_src_bt_cfg00: IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 { + pinmux = <0x400e81fc 6 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_in32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_IN32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_inout32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_enet_1g_tdata02: IOMUXC_GPIO_DISP_B1_07_ENET_1G_TDATA02 { + pinmux = <0x400e8200 1 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio10_io28: IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 { + pinmux = <0x400e8200 10 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio_mux4_io28: IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 { + pinmux = <0x400e8200 5 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpspi3_pcs0: IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 { + pinmux = <0x400e8200 9 0x400e85f0 1 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpuart4_rts_b: IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B { + pinmux = <0x400e8200 2 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_qtimer3_timer1: IOMUXC_GPIO_DISP_B1_07_QTIMER3_TIMER1 { + pinmux = <0x400e8200 3 0x400e8658 2 0x400e8444>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_src_bt_cfg01: IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 { + pinmux = <0x400e8200 6 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_in33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_IN33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_inout33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_enet_1g_tdata01: IOMUXC_GPIO_DISP_B1_08_ENET_1G_TDATA01 { + pinmux = <0x400e8204 1 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio10_io29: IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 { + pinmux = <0x400e8204 10 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio_mux4_io29: IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 { + pinmux = <0x400e8204 5 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_lpspi3_pcs1: IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 { + pinmux = <0x400e8204 9 0x400e85f4 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_qtimer3_timer2: IOMUXC_GPIO_DISP_B1_08_QTIMER3_TIMER2 { + pinmux = <0x400e8204 3 0x400e865c 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_src_bt_cfg02: IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 { + pinmux = <0x400e8204 6 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_usdhc1_cd_b: IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B { + pinmux = <0x400e8204 2 0x400e86c8 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_in34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_IN34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_inout34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_enet_1g_tdata00: IOMUXC_GPIO_DISP_B1_09_ENET_1G_TDATA00 { + pinmux = <0x400e8208 1 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio10_io30: IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 { + pinmux = <0x400e8208 10 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio_mux4_io30: IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 { + pinmux = <0x400e8208 5 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_lpspi3_pcs2: IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 { + pinmux = <0x400e8208 9 0x400e85f8 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_qtimer4_timer0: IOMUXC_GPIO_DISP_B1_09_QTIMER4_TIMER0 { + pinmux = <0x400e8208 3 0x400e8660 2 0x400e844c>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_src_bt_cfg03: IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 { + pinmux = <0x400e8208 6 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_usdhc1_wp: IOMUXC_GPIO_DISP_B1_09_USDHC1_WP { + pinmux = <0x400e8208 2 0x400e86cc 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_in35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_IN35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_inout35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_enet_1g_tx_en: IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN { + pinmux = <0x400e820c 1 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio10_io31: IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 { + pinmux = <0x400e820c 10 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio_mux4_io31: IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 { + pinmux = <0x400e820c 5 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_lpspi3_pcs3: IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 { + pinmux = <0x400e820c 9 0x400e85fc 1 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_qtimer4_timer1: IOMUXC_GPIO_DISP_B1_10_QTIMER4_TIMER1 { + pinmux = <0x400e820c 3 0x400e8664 2 0x400e8450>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_src_bt_cfg04: IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 { + pinmux = <0x400e820c 6 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_usdhc1_reset_b: IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B { + pinmux = <0x400e820c 2 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_in36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_IN36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_inout36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_INOUT36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e8210 2 0x400e84c4 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_tx_clk_io: IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e8210 1 0x400e84e8 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio11_io00: IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 { + pinmux = <0x400e8210 10 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio_mux5_io00: IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 { + pinmux = <0x400e8210 5 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_qtimer4_timer2: IOMUXC_GPIO_DISP_B1_11_QTIMER4_TIMER2 { + pinmux = <0x400e8210 3 0x400e8668 1 0x400e8454>; + pin-pdrv; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_src_bt_cfg05: IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 { + pinmux = <0x400e8210 6 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_in37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_IN37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_inout37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_INOUT37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_enet_1g_tx_er: IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER { + pinmux = <0x400e8214 3 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio11_io01: IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 { + pinmux = <0x400e8214 10 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio_mux5_io01: IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 { + pinmux = <0x400e8214 5 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_mqs_right: IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT { + pinmux = <0x400e8214 2 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_rx_data01: IOMUXC_GPIO_DISP_B2_00_SAI1_RX_DATA01 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_tx_data03: IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_src_bt_cfg06: IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 { + pinmux = <0x400e8214 6 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_00_WDOG1_WDOG_B { + pinmux = <0x400e8214 1 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ccm_enet_ref_clk_25m: IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8218 9 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ewm_ewm_out_b: IOMUXC_GPIO_DISP_B2_01_EWM_EWM_OUT_B { + pinmux = <0x400e8218 8 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio11_io02: IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 { + pinmux = <0x400e8218 10 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio_mux5_io02: IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 { + pinmux = <0x400e8218 5 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_mqs_left: IOMUXC_GPIO_DISP_B2_01_MQS_LEFT { + pinmux = <0x400e8218 2 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_rx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_RX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_tx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_src_bt_cfg07: IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 { + pinmux = <0x400e8218 6 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_usdhc1_vselect: IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT { + pinmux = <0x400e8218 1 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_01_WDOG2_WDOG_B { + pinmux = <0x400e8218 3 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_arm_trace00: IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 { + pinmux = <0x400e821c 3 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_enet_tdata00: IOMUXC_GPIO_DISP_B2_02_ENET_TDATA00 { + pinmux = <0x400e821c 1 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio11_io03: IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 { + pinmux = <0x400e821c 10 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio_mux5_io03: IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 { + pinmux = <0x400e821c 5 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_pit1_trigger03: IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER03 { + pinmux = <0x400e821c 2 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_rx_data03: IOMUXC_GPIO_DISP_B2_02_SAI1_RX_DATA03 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_tx_data01: IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_src_bt_cfg08: IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 { + pinmux = <0x400e821c 6 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_arm_trace01: IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 { + pinmux = <0x400e8220 3 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_enet_tdata01: IOMUXC_GPIO_DISP_B2_03_ENET_TDATA01 { + pinmux = <0x400e8220 1 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio11_io04: IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 { + pinmux = <0x400e8220 10 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio_mux5_io04: IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 { + pinmux = <0x400e8220 5 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_pit1_trigger02: IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER02 { + pinmux = <0x400e8220 2 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_sai1_mclk: IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK { + pinmux = <0x400e8220 4 0x400e866c 1 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_src_bt_cfg09: IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 { + pinmux = <0x400e8220 6 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_arm_trace02: IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 { + pinmux = <0x400e8224 3 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_enet_tx_en: IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN { + pinmux = <0x400e8224 1 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio11_io05: IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 { + pinmux = <0x400e8224 10 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio_mux5_io05: IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 { + pinmux = <0x400e8224 5 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_pit1_trigger01: IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER01 { + pinmux = <0x400e8224 2 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_sai1_rx_sync: IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC { + pinmux = <0x400e8224 4 0x400e8678 1 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_src_bt_cfg10: IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 { + pinmux = <0x400e8224 6 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_arm_trace03: IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 { + pinmux = <0x400e8228 3 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_ref_clk: IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK { + pinmux = <0x400e8228 2 0x400e84a8 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_tx_clk: IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK { + pinmux = <0x400e8228 1 0x400e84c0 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio11_io06: IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 { + pinmux = <0x400e8228 10 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio_mux5_io06: IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 { + pinmux = <0x400e8228 5 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_sai1_rx_bclk: IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK { + pinmux = <0x400e8228 4 0x400e8670 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_src_bt_cfg11: IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 { + pinmux = <0x400e8228 6 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_arm_trace_clk: IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK { + pinmux = <0x400e822c 3 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_enet_rdata00: IOMUXC_GPIO_DISP_B2_06_ENET_RDATA00 { + pinmux = <0x400e822c 1 0x400e84b0 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio11_io07: IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 { + pinmux = <0x400e822c 10 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio_mux5_io07: IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 { + pinmux = <0x400e822c 5 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_lpuart7_tx: IOMUXC_GPIO_DISP_B2_06_LPUART7_TX { + pinmux = <0x400e822c 2 0x400e8630 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_sai1_rx_data00: IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 { + pinmux = <0x400e822c 4 0x400e8674 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_arm_trace_swo: IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO { + pinmux = <0x400e8230 3 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_enet_rdata01: IOMUXC_GPIO_DISP_B2_07_ENET_RDATA01 { + pinmux = <0x400e8230 1 0x400e84b4 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio11_io08: IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 { + pinmux = <0x400e8230 10 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio_mux5_io08: IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 { + pinmux = <0x400e8230 5 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_lpuart7_rx: IOMUXC_GPIO_DISP_B2_07_LPUART7_RX { + pinmux = <0x400e8230 2 0x400e862c 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_sai1_tx_data00: IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 { + pinmux = <0x400e8230 4 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_cm7_imxrt_txev: IOMUXC_GPIO_DISP_B2_08_CM7_IMXRT_TXEV { + pinmux = <0x400e8234 3 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_enet_rx_en: IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN { + pinmux = <0x400e8234 1 0x400e84b8 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio11_io09: IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 { + pinmux = <0x400e8234 10 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio_mux5_io09: IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 { + pinmux = <0x400e8234 5 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart1_tx: IOMUXC_GPIO_DISP_B2_08_LPUART1_TX { + pinmux = <0x400e8234 9 0x400e8620 2 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart8_tx: IOMUXC_GPIO_DISP_B2_08_LPUART8_TX { + pinmux = <0x400e8234 2 0x400e8638 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_sai1_tx_bclk: IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK { + pinmux = <0x400e8234 4 0x400e867c 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_cm7_imxrt_rxev: IOMUXC_GPIO_DISP_B2_09_CM7_IMXRT_RXEV { + pinmux = <0x400e8238 3 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_enet_rx_er: IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER { + pinmux = <0x400e8238 1 0x400e84bc 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio11_io10: IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 { + pinmux = <0x400e8238 10 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio_mux5_io10: IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 { + pinmux = <0x400e8238 5 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart1_rx: IOMUXC_GPIO_DISP_B2_09_LPUART1_RX { + pinmux = <0x400e8238 9 0x400e861c 2 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart8_rx: IOMUXC_GPIO_DISP_B2_09_LPUART8_RX { + pinmux = <0x400e8238 2 0x400e8634 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_sai1_tx_sync: IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC { + pinmux = <0x400e8238 4 0x400e8680 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio11_io11: IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 { + pinmux = <0x400e823c 10 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio_mux5_io11: IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 { + pinmux = <0x400e823c 5 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpi2c3_scl: IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL { + pinmux = <0x400e823c 6 0x400e85bc 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpuart2_tx: IOMUXC_GPIO_DISP_B2_10_LPUART2_TX { + pinmux = <0x400e823c 2 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_sim2_trxd: IOMUXC_GPIO_DISP_B2_10_SIM2_TRXD { + pinmux = <0x400e823c 1 0x400e86a8 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_spdif_in: IOMUXC_GPIO_DISP_B2_10_SPDIF_IN { + pinmux = <0x400e823c 9 0x400e86b4 2 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_10_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e823c 3 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_in38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_IN38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_inout38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_INOUT38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio11_io12: IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 { + pinmux = <0x400e8240 10 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio_mux5_io12: IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 { + pinmux = <0x400e8240 5 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpi2c3_sda: IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA { + pinmux = <0x400e8240 6 0x400e85c0 1 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpuart2_rx: IOMUXC_GPIO_DISP_B2_11_LPUART2_RX { + pinmux = <0x400e8240 2 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_sim2_clk: IOMUXC_GPIO_DISP_B2_11_SIM2_CLK { + pinmux = <0x400e8240 1 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_spdif_out: IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT { + pinmux = <0x400e8240 9 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_11_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8240 3 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_in39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_IN39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_inout39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_INOUT39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_can1_tx: IOMUXC_GPIO_DISP_B2_12_CAN1_TX { + pinmux = <0x400e8244 2 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio11_io13: IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 { + pinmux = <0x400e8244 10 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio_mux5_io13: IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 { + pinmux = <0x400e8244 5 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpi2c4_scl: IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL { + pinmux = <0x400e8244 6 0x400e85c4 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpspi4_sck: IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK { + pinmux = <0x400e8244 9 0x400e8610 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpuart2_cts_b: IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B { + pinmux = <0x400e8244 3 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_sim2_rst_b: IOMUXC_GPIO_DISP_B2_12_SIM2_RST_B { + pinmux = <0x400e8244 1 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_in40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_IN40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_inout40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_INOUT40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_can1_rx: IOMUXC_GPIO_DISP_B2_13_CAN1_RX { + pinmux = <0x400e8248 2 0x400e8498 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_enet_ref_clk: IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK { + pinmux = <0x400e8248 4 0x400e84a8 2 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio11_io14: IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 { + pinmux = <0x400e8248 10 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio_mux5_io14: IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 { + pinmux = <0x400e8248 5 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpi2c4_sda: IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA { + pinmux = <0x400e8248 6 0x400e85c8 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpspi4_sdi: IOMUXC_GPIO_DISP_B2_13_LPSPI4_SDI { + pinmux = <0x400e8248 9 0x400e8614 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpuart2_rts_b: IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B { + pinmux = <0x400e8248 3 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_sim2_sven: IOMUXC_GPIO_DISP_B2_13_SIM2_SVEN { + pinmux = <0x400e8248 1 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_can1_tx: IOMUXC_GPIO_DISP_B2_14_CAN1_TX { + pinmux = <0x400e824c 6 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK1 { + pinmux = <0x400e824c 4 0x400e84c4 3 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio11_io15: IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 { + pinmux = <0x400e824c 10 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio_mux5_io15: IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 { + pinmux = <0x400e824c 5 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_lpspi4_sdo: IOMUXC_GPIO_DISP_B2_14_LPSPI4_SDO { + pinmux = <0x400e824c 9 0x400e8618 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_sim2_pd: IOMUXC_GPIO_DISP_B2_14_SIM2_PD { + pinmux = <0x400e824c 1 0x400e86ac 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_ext_dcic1: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e824c 3 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_14_WDOG2_WDOG_B { + pinmux = <0x400e824c 2 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_can1_rx: IOMUXC_GPIO_DISP_B2_15_CAN1_RX { + pinmux = <0x400e8250 6 0x400e8498 2 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio11_io16: IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 { + pinmux = <0x400e8250 10 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio_mux5_io16: IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 { + pinmux = <0x400e8250 5 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_lpspi4_pcs0: IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 { + pinmux = <0x400e8250 9 0x400e860c 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_pit1_trigger00: IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER00 { + pinmux = <0x400e8250 4 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_sim2_power_fail: IOMUXC_GPIO_DISP_B2_15_SIM2_POWER_FAIL { + pinmux = <0x400e8250 1 0x400e86b0 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_ext_dcic2: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8250 3 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_15_WDOG1_WDOG_B { + pinmux = <0x400e8250 2 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexio1_flexio00: IOMUXC_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00 { + pinmux = <0x400e8010 8 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexpwm4_pwm0_a: IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A { + pinmux = <0x400e8010 1 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio7_io00: IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 { + pinmux = <0x400e8010 10 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio_mux1_io00: IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 { + pinmux = <0x400e8010 5 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_semc_data00: IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 { + pinmux = <0x400e8010 0 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexio1_flexio01: IOMUXC_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01 { + pinmux = <0x400e8014 8 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexpwm4_pwm0_b: IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B { + pinmux = <0x400e8014 1 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio7_io01: IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 { + pinmux = <0x400e8014 10 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio_mux1_io01: IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 { + pinmux = <0x400e8014 5 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_semc_data01: IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 { + pinmux = <0x400e8014 0 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexio1_flexio02: IOMUXC_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02 { + pinmux = <0x400e8018 8 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexpwm4_pwm1_a: IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A { + pinmux = <0x400e8018 1 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio7_io02: IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 { + pinmux = <0x400e8018 10 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio_mux1_io02: IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 { + pinmux = <0x400e8018 5 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_semc_data02: IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 { + pinmux = <0x400e8018 0 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexio1_flexio03: IOMUXC_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03 { + pinmux = <0x400e801c 8 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexpwm4_pwm1_b: IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B { + pinmux = <0x400e801c 1 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio7_io03: IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 { + pinmux = <0x400e801c 10 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio_mux1_io03: IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 { + pinmux = <0x400e801c 5 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_semc_data03: IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 { + pinmux = <0x400e801c 0 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexio1_flexio04: IOMUXC_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04 { + pinmux = <0x400e8020 8 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexpwm4_pwm2_a: IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A { + pinmux = <0x400e8020 1 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio7_io04: IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 { + pinmux = <0x400e8020 10 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio_mux1_io04: IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 { + pinmux = <0x400e8020 5 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_semc_data04: IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 { + pinmux = <0x400e8020 0 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexio1_flexio05: IOMUXC_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05 { + pinmux = <0x400e8024 8 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexpwm4_pwm2_b: IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B { + pinmux = <0x400e8024 1 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio7_io05: IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 { + pinmux = <0x400e8024 10 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio_mux1_io05: IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 { + pinmux = <0x400e8024 5 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_semc_data05: IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 { + pinmux = <0x400e8024 0 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexio1_flexio06: IOMUXC_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06 { + pinmux = <0x400e8028 8 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexpwm2_pwm0_a: IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A { + pinmux = <0x400e8028 1 0x400e8518 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio7_io06: IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 { + pinmux = <0x400e8028 10 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio_mux1_io06: IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 { + pinmux = <0x400e8028 5 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_semc_data06: IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 { + pinmux = <0x400e8028 0 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexio1_flexio07: IOMUXC_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07 { + pinmux = <0x400e802c 8 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexpwm2_pwm0_b: IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B { + pinmux = <0x400e802c 1 0x400e8524 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio7_io07: IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 { + pinmux = <0x400e802c 10 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio_mux1_io07: IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 { + pinmux = <0x400e802c 5 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_semc_data07: IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 { + pinmux = <0x400e802c 0 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexio1_flexio08: IOMUXC_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08 { + pinmux = <0x400e8030 8 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexpwm2_pwm1_a: IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A { + pinmux = <0x400e8030 1 0x400e851c 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio7_io08: IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 { + pinmux = <0x400e8030 10 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio_mux1_io08: IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 { + pinmux = <0x400e8030 5 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_semc_dm00: IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 { + pinmux = <0x400e8030 0 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexio1_flexio09: IOMUXC_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09 { + pinmux = <0x400e8034 8 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexpwm2_pwm1_b: IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B { + pinmux = <0x400e8034 1 0x400e8528 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio7_io09: IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 { + pinmux = <0x400e8034 10 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio_mux1_io09: IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 { + pinmux = <0x400e8034 5 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpt5_capture1: IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 { + pinmux = <0x400e8034 2 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_semc_addr00: IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 { + pinmux = <0x400e8034 0 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexio1_flexio10: IOMUXC_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10 { + pinmux = <0x400e8038 8 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexpwm2_pwm2_a: IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A { + pinmux = <0x400e8038 1 0x400e8520 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio7_io10: IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 { + pinmux = <0x400e8038 10 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio_mux1_io10: IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 { + pinmux = <0x400e8038 5 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpt5_capture2: IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 { + pinmux = <0x400e8038 2 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_semc_addr01: IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 { + pinmux = <0x400e8038 0 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexio1_flexio11: IOMUXC_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11 { + pinmux = <0x400e803c 8 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexpwm2_pwm2_b: IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B { + pinmux = <0x400e803c 1 0x400e852c 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio7_io11: IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 { + pinmux = <0x400e803c 10 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio_mux1_io11: IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 { + pinmux = <0x400e803c 5 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpt5_compare1: IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 { + pinmux = <0x400e803c 2 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_semc_addr02: IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 { + pinmux = <0x400e803c 0 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_flexio1_flexio12: IOMUXC_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12 { + pinmux = <0x400e8040 8 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio7_io12: IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 { + pinmux = <0x400e8040 10 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio_mux1_io12: IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 { + pinmux = <0x400e8040 5 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpt5_compare2: IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 { + pinmux = <0x400e8040 2 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_semc_addr03: IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 { + pinmux = <0x400e8040 0 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_in04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_IN04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_INOUT04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_flexio1_flexio13: IOMUXC_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13 { + pinmux = <0x400e8044 8 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio7_io13: IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 { + pinmux = <0x400e8044 10 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio_mux1_io13: IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 { + pinmux = <0x400e8044 5 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpt5_compare3: IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 { + pinmux = <0x400e8044 2 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_semc_addr04: IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 { + pinmux = <0x400e8044 0 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_in05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_IN05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_INOUT05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_flexio1_flexio14: IOMUXC_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14 { + pinmux = <0x400e8048 8 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio7_io14: IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 { + pinmux = <0x400e8048 10 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio_mux1_io14: IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 { + pinmux = <0x400e8048 5 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpt5_clk: IOMUXC_GPIO_EMC_B1_14_GPT5_CLK { + pinmux = <0x400e8048 2 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_semc_addr05: IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 { + pinmux = <0x400e8048 0 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_in06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_IN06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_INOUT06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_flexio1_flexio15: IOMUXC_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15 { + pinmux = <0x400e804c 8 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio7_io15: IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 { + pinmux = <0x400e804c 10 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio_mux1_io15: IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 { + pinmux = <0x400e804c 5 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_semc_addr06: IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 { + pinmux = <0x400e804c 0 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_in07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_IN07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_INOUT07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_flexio1_flexio16: IOMUXC_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16 { + pinmux = <0x400e8050 8 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio7_io16: IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 { + pinmux = <0x400e8050 10 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio_mux1_io16: IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 { + pinmux = <0x400e8050 5 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_semc_addr07: IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 { + pinmux = <0x400e8050 0 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_in08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_IN08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_INOUT08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexio1_flexio17: IOMUXC_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17 { + pinmux = <0x400e8054 8 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexpwm4_pwm3_a: IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A { + pinmux = <0x400e8054 1 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio7_io17: IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 { + pinmux = <0x400e8054 10 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio_mux1_io17: IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 { + pinmux = <0x400e8054 5 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_qtimer1_timer0: IOMUXC_GPIO_EMC_B1_17_QTIMER1_TIMER0 { + pinmux = <0x400e8054 2 0x400e863c 0 0x400e8298>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_semc_addr08: IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 { + pinmux = <0x400e8054 0 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexio1_flexio18: IOMUXC_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18 { + pinmux = <0x400e8058 8 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexpwm4_pwm3_b: IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B { + pinmux = <0x400e8058 1 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio7_io18: IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 { + pinmux = <0x400e8058 10 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio_mux1_io18: IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 { + pinmux = <0x400e8058 5 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_qtimer2_timer0: IOMUXC_GPIO_EMC_B1_18_QTIMER2_TIMER0 { + pinmux = <0x400e8058 2 0x400e8648 0 0x400e829c>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_semc_addr09: IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 { + pinmux = <0x400e8058 0 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexio1_flexio19: IOMUXC_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19 { + pinmux = <0x400e805c 8 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexpwm2_pwm3_a: IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A { + pinmux = <0x400e805c 1 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio7_io19: IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 { + pinmux = <0x400e805c 10 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio_mux1_io19: IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 { + pinmux = <0x400e805c 5 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_qtimer3_timer0: IOMUXC_GPIO_EMC_B1_19_QTIMER3_TIMER0 { + pinmux = <0x400e805c 2 0x400e8654 0 0x400e82a0>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_semc_addr11: IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 { + pinmux = <0x400e805c 0 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexio1_flexio20: IOMUXC_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20 { + pinmux = <0x400e8060 8 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexpwm2_pwm3_b: IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B { + pinmux = <0x400e8060 1 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio7_io20: IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 { + pinmux = <0x400e8060 10 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio_mux1_io20: IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 { + pinmux = <0x400e8060 5 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_qtimer4_timer0: IOMUXC_GPIO_EMC_B1_20_QTIMER4_TIMER0 { + pinmux = <0x400e8060 2 0x400e8660 0 0x400e82a4>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_semc_addr12: IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 { + pinmux = <0x400e8060 0 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexio1_flexio21: IOMUXC_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21 { + pinmux = <0x400e8064 8 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A { + pinmux = <0x400e8064 1 0x400e853c 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio7_io21: IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 { + pinmux = <0x400e8064 10 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio_mux1_io21: IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 { + pinmux = <0x400e8064 5 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_semc_ba0: IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 { + pinmux = <0x400e8064 0 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexio1_flexio22: IOMUXC_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22 { + pinmux = <0x400e8068 8 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B { + pinmux = <0x400e8068 1 0x400e854c 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio7_io22: IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 { + pinmux = <0x400e8068 10 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio_mux1_io22: IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 { + pinmux = <0x400e8068 5 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_semc_ba1: IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 { + pinmux = <0x400e8068 0 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexio1_flexio23: IOMUXC_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23 { + pinmux = <0x400e806c 8 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexpwm1_pwm0_a: IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A { + pinmux = <0x400e806c 1 0x400e8500 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio7_io23: IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 { + pinmux = <0x400e806c 10 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio_mux1_io23: IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 { + pinmux = <0x400e806c 5 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_semc_addr10: IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 { + pinmux = <0x400e806c 0 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexio1_flexio24: IOMUXC_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24 { + pinmux = <0x400e8070 8 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexpwm1_pwm0_b: IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B { + pinmux = <0x400e8070 1 0x400e850c 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio7_io24: IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 { + pinmux = <0x400e8070 10 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio_mux1_io24: IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 { + pinmux = <0x400e8070 5 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_semc_cas: IOMUXC_GPIO_EMC_B1_24_SEMC_CAS { + pinmux = <0x400e8070 0 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexio1_flexio25: IOMUXC_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25 { + pinmux = <0x400e8074 8 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexpwm1_pwm1_a: IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A { + pinmux = <0x400e8074 1 0x400e8504 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio7_io25: IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 { + pinmux = <0x400e8074 10 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio_mux1_io25: IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 { + pinmux = <0x400e8074 5 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_semc_ras: IOMUXC_GPIO_EMC_B1_25_SEMC_RAS { + pinmux = <0x400e8074 0 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexio1_flexio26: IOMUXC_GPIO_EMC_B1_26_FLEXIO1_FLEXIO26 { + pinmux = <0x400e8078 8 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexpwm1_pwm1_b: IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B { + pinmux = <0x400e8078 1 0x400e8510 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio7_io26: IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 { + pinmux = <0x400e8078 10 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio_mux1_io26: IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 { + pinmux = <0x400e8078 5 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_semc_clk: IOMUXC_GPIO_EMC_B1_26_SEMC_CLK { + pinmux = <0x400e8078 0 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexio1_flexio27: IOMUXC_GPIO_EMC_B1_27_FLEXIO1_FLEXIO27 { + pinmux = <0x400e807c 8 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexpwm1_pwm2_a: IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A { + pinmux = <0x400e807c 1 0x400e8508 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio7_io27: IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 { + pinmux = <0x400e807c 10 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio_mux1_io27: IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 { + pinmux = <0x400e807c 5 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_semc_cke: IOMUXC_GPIO_EMC_B1_27_SEMC_CKE { + pinmux = <0x400e807c 0 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexio1_flexio28: IOMUXC_GPIO_EMC_B1_28_FLEXIO1_FLEXIO28 { + pinmux = <0x400e8080 8 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexpwm1_pwm2_b: IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B { + pinmux = <0x400e8080 1 0x400e8514 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio7_io28: IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 { + pinmux = <0x400e8080 10 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio_mux1_io28: IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 { + pinmux = <0x400e8080 5 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_semc_we: IOMUXC_GPIO_EMC_B1_28_SEMC_WE { + pinmux = <0x400e8080 0 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexio1_flexio29: IOMUXC_GPIO_EMC_B1_29_FLEXIO1_FLEXIO29 { + pinmux = <0x400e8084 8 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A { + pinmux = <0x400e8084 1 0x400e8530 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio7_io29: IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 { + pinmux = <0x400e8084 10 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio_mux1_io29: IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 { + pinmux = <0x400e8084 5 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_semc_cs0: IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 { + pinmux = <0x400e8084 0 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexio1_flexio30: IOMUXC_GPIO_EMC_B1_30_FLEXIO1_FLEXIO30 { + pinmux = <0x400e8088 8 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B { + pinmux = <0x400e8088 1 0x400e8540 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio7_io30: IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 { + pinmux = <0x400e8088 10 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio_mux1_io30: IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 { + pinmux = <0x400e8088 5 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_semc_data08: IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 { + pinmux = <0x400e8088 0 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexio1_flexio31: IOMUXC_GPIO_EMC_B1_31_FLEXIO1_FLEXIO31 { + pinmux = <0x400e808c 8 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A { + pinmux = <0x400e808c 1 0x400e8534 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio7_io31: IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 { + pinmux = <0x400e808c 10 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio_mux1_io31: IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 { + pinmux = <0x400e808c 5 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_semc_data09: IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 { + pinmux = <0x400e808c 0 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B { + pinmux = <0x400e8090 1 0x400e8544 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio8_io00: IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 { + pinmux = <0x400e8090 10 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00_cm7: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00_CM7 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_semc_data10: IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 { + pinmux = <0x400e8090 0 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A { + pinmux = <0x400e8094 1 0x400e8538 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio8_io01: IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 { + pinmux = <0x400e8094 10 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01_cm7: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01_CM7 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_semc_data11: IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 { + pinmux = <0x400e8094 0 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B { + pinmux = <0x400e8098 1 0x400e8548 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio8_io02: IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 { + pinmux = <0x400e8098 10 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02_cm7: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02_CM7 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_semc_data12: IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 { + pinmux = <0x400e8098 0 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio8_io03: IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 { + pinmux = <0x400e809c 10 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03_cm7: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03_CM7 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_semc_data13: IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 { + pinmux = <0x400e809c 0 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_in09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_IN09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_INOUT09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio8_io04: IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 { + pinmux = <0x400e80a0 10 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04_cm7: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04_CM7 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_semc_data14: IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 { + pinmux = <0x400e80a0 0 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_in10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_IN10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_INOUT10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio8_io05: IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 { + pinmux = <0x400e80a4 10 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05_cm7: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05_CM7 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_semc_data15: IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 { + pinmux = <0x400e80a4 0 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_in11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_IN11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_INOUT11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_flexpwm1_pwm3_a: IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A { + pinmux = <0x400e80a8 1 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio8_io06: IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 { + pinmux = <0x400e80a8 10 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06_cm7: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06_CM7 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_qtimer1_timer1: IOMUXC_GPIO_EMC_B1_38_QTIMER1_TIMER1 { + pinmux = <0x400e80a8 2 0x400e8640 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_semc_dm01: IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 { + pinmux = <0x400e80a8 0 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_flexpwm1_pwm3_b: IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B { + pinmux = <0x400e80ac 1 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio8_io07: IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 { + pinmux = <0x400e80ac 10 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07_cm7: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07_CM7 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_qtimer2_timer1: IOMUXC_GPIO_EMC_B1_39_QTIMER2_TIMER1 { + pinmux = <0x400e80ac 2 0x400e864c 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_semc_dqs: IOMUXC_GPIO_EMC_B1_39_SEMC_DQS { + pinmux = <0x400e80ac 0 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_ccm_clko1: IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 { + pinmux = <0x400e80b0 9 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_enet_1g_mdc: IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC { + pinmux = <0x400e80b0 7 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio8_io08: IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 { + pinmux = <0x400e80b0 10 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08_cm7: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08_CM7 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_lpuart6_tx: IOMUXC_GPIO_EMC_B1_40_LPUART6_TX { + pinmux = <0x400e80b0 3 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_mqs_right: IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT { + pinmux = <0x400e80b0 2 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_semc_rdy: IOMUXC_GPIO_EMC_B1_40_SEMC_RDY { + pinmux = <0x400e80b0 0 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_in12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_IN12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_INOUT12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_ccm_clko2: IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 { + pinmux = <0x400e80b4 9 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_enet_1g_mdio: IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO { + pinmux = <0x400e80b4 7 0x400e84c8 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_flexspi2_b_data07: IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 { + pinmux = <0x400e80b4 4 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio8_io09: IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 { + pinmux = <0x400e80b4 10 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09_cm7: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09_CM7 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_lpuart6_rx: IOMUXC_GPIO_EMC_B1_41_LPUART6_RX { + pinmux = <0x400e80b4 3 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_mqs_left: IOMUXC_GPIO_EMC_B1_41_MQS_LEFT { + pinmux = <0x400e80b4 2 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_semc_csx00: IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 { + pinmux = <0x400e80b4 0 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_in13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_IN13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_INOUT13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_ccm_enet_ref_clk_25m: IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e80b8 1 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A { + pinmux = <0x400e80b8 11 0x400e8530 1 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexspi2_b_data06: IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 { + pinmux = <0x400e80b8 4 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio8_io10: IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 { + pinmux = <0x400e80b8 10 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10_cm7: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10_CM7 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpi2c2_scl: IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL { + pinmux = <0x400e80b8 9 0x400e85b4 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpspi1_sck: IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK { + pinmux = <0x400e80b8 8 0x400e85d0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpuart6_cts_b: IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B { + pinmux = <0x400e80b8 3 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_00_QTIMER3_TIMER1 { + pinmux = <0x400e80b8 2 0x400e8658 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_semc_data16: IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 { + pinmux = <0x400e80b8 0 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_in20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_inout20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B { + pinmux = <0x400e80bc 11 0x400e8540 1 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexspi2_b_data05: IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 { + pinmux = <0x400e80bc 4 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio8_io11: IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 { + pinmux = <0x400e80bc 10 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11_cm7: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11_CM7 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpi2c2_sda: IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA { + pinmux = <0x400e80bc 9 0x400e85b8 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpspi1_pcs0: IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 { + pinmux = <0x400e80bc 8 0x400e85cc 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpuart6_rts_b: IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B { + pinmux = <0x400e80bc 3 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_qtimer4_timer1: IOMUXC_GPIO_EMC_B2_01_QTIMER4_TIMER1 { + pinmux = <0x400e80bc 2 0x400e8664 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_semc_data17: IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 { + pinmux = <0x400e80bc 0 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_usdhc2_cd_b: IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B { + pinmux = <0x400e80bc 1 0x400e86d0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_in21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_inout21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A { + pinmux = <0x400e80c0 11 0x400e8534 1 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexspi2_b_data04: IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 { + pinmux = <0x400e80c0 4 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio8_io12: IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 { + pinmux = <0x400e80c0 10 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12_cm7: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12_CM7 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_lpspi1_sdo: IOMUXC_GPIO_EMC_B2_02_LPSPI1_SDO { + pinmux = <0x400e80c0 8 0x400e85d8 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_semc_data18: IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 { + pinmux = <0x400e80c0 0 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_usdhc2_wp: IOMUXC_GPIO_EMC_B2_02_USDHC2_WP { + pinmux = <0x400e80c0 1 0x400e86d4 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_in22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_inout22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_enet_1g_tdata03: IOMUXC_GPIO_EMC_B2_03_ENET_1G_TDATA03 { + pinmux = <0x400e80c4 7 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B { + pinmux = <0x400e80c4 11 0x400e8544 1 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexspi2_b_data03: IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 { + pinmux = <0x400e80c4 4 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio8_io13: IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 { + pinmux = <0x400e80c4 10 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13_cm7: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13_CM7 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_lpspi1_sdi: IOMUXC_GPIO_EMC_B2_03_LPSPI1_SDI { + pinmux = <0x400e80c4 8 0x400e85d4 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_semc_data19: IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 { + pinmux = <0x400e80c4 0 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_usdhc2_vselect: IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT { + pinmux = <0x400e80c4 1 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_in23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_inout23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_enet_1g_tdata02: IOMUXC_GPIO_EMC_B2_04_ENET_1G_TDATA02 { + pinmux = <0x400e80c8 7 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A { + pinmux = <0x400e80c8 11 0x400e8538 1 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexspi2_b_data02: IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 { + pinmux = <0x400e80c8 4 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio8_io14: IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 { + pinmux = <0x400e80c8 10 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14_cm7: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14_CM7 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_lpspi3_sck: IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK { + pinmux = <0x400e80c8 8 0x400e8600 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_sai2_mclk: IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK { + pinmux = <0x400e80c8 2 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_semc_data20: IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 { + pinmux = <0x400e80c8 0 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_usdhc2_reset_b: IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B { + pinmux = <0x400e80c8 1 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_in24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_inout24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_enet_1g_rx_clk: IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK { + pinmux = <0x400e80cc 7 0x400e84cc 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B { + pinmux = <0x400e80cc 11 0x400e8548 1 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexspi2_b_data01: IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 { + pinmux = <0x400e80cc 4 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio8_io15: IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 { + pinmux = <0x400e80cc 10 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15_cm7: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15_CM7 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpt3_clk: IOMUXC_GPIO_EMC_B2_05_GPT3_CLK { + pinmux = <0x400e80cc 1 0x400e8598 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_lpspi3_pcs0: IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 { + pinmux = <0x400e80cc 8 0x400e85f0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_pit1_trigger00: IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER00 { + pinmux = <0x400e80cc 9 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_sai2_rx_sync: IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC { + pinmux = <0x400e80cc 2 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_semc_data21: IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 { + pinmux = <0x400e80cc 0 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_in25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_inout25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_enet_1g_tx_er: IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER { + pinmux = <0x400e80d0 7 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A { + pinmux = <0x400e80d0 11 0x400e853c 1 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexspi2_b_data00: IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 { + pinmux = <0x400e80d0 4 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio8_io16: IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 { + pinmux = <0x400e80d0 10 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16_cm7: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16_CM7 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpt3_capture1: IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 { + pinmux = <0x400e80d0 1 0x400e8590 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_lpspi3_sdo: IOMUXC_GPIO_EMC_B2_06_LPSPI3_SDO { + pinmux = <0x400e80d0 8 0x400e8608 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_pit1_trigger01: IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER01 { + pinmux = <0x400e80d0 9 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_sai2_rx_bclk: IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK { + pinmux = <0x400e80d0 2 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_semc_data22: IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 { + pinmux = <0x400e80d0 0 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_in26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_IN26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_inout26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_enet_1g_rdata03: IOMUXC_GPIO_EMC_B2_07_ENET_1G_RDATA03 { + pinmux = <0x400e80d4 7 0x400e84dc 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B { + pinmux = <0x400e80d4 11 0x400e854c 1 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexspi2_b_dqs: IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS { + pinmux = <0x400e80d4 4 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio8_io17: IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 { + pinmux = <0x400e80d4 10 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17_cm7: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17_CM7 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpt3_capture2: IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 { + pinmux = <0x400e80d4 1 0x400e8594 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_lpspi3_sdi: IOMUXC_GPIO_EMC_B2_07_LPSPI3_SDI { + pinmux = <0x400e80d4 8 0x400e8604 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_pit1_trigger02: IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER02 { + pinmux = <0x400e80d4 9 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_sai2_rx_data: IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA { + pinmux = <0x400e80d4 2 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_semc_data23: IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 { + pinmux = <0x400e80d4 0 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_in27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_IN27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_inout27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_enet_1g_rdata02: IOMUXC_GPIO_EMC_B2_08_ENET_1G_RDATA02 { + pinmux = <0x400e80d8 7 0x400e84d8 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B { + pinmux = <0x400e80d8 4 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio8_io18: IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 { + pinmux = <0x400e80d8 10 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18_cm7: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18_CM7 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpt3_compare1: IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 { + pinmux = <0x400e80d8 1 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_lpspi3_pcs1: IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 { + pinmux = <0x400e80d8 8 0x400e85f4 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_pit1_trigger03: IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER03 { + pinmux = <0x400e80d8 9 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_sai2_tx_data: IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA { + pinmux = <0x400e80d8 2 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_semc_dm02: IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 { + pinmux = <0x400e80d8 0 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_in28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_IN28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_inout28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_enet_1g_crs: IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS { + pinmux = <0x400e80dc 7 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_flexspi2_b_sclk: IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK { + pinmux = <0x400e80dc 4 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio8_io19: IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 { + pinmux = <0x400e80dc 10 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19_cm7: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19_CM7 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpt3_compare2: IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 { + pinmux = <0x400e80dc 1 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_lpspi3_pcs2: IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 { + pinmux = <0x400e80dc 8 0x400e85f8 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_qtimer1_timer0: IOMUXC_GPIO_EMC_B2_09_QTIMER1_TIMER0 { + pinmux = <0x400e80dc 9 0x400e863c 1 0x400e8320>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_sai2_tx_bclk: IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK { + pinmux = <0x400e80dc 2 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_semc_data24: IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 { + pinmux = <0x400e80dc 0 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_in29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_IN29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_inout29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_enet_1g_col: IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL { + pinmux = <0x400e80e0 7 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_flexspi2_a_sclk: IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK { + pinmux = <0x400e80e0 4 0x400e858c 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio8_io20: IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 { + pinmux = <0x400e80e0 10 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20_cm7: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20_CM7 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpt3_compare3: IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 { + pinmux = <0x400e80e0 1 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_lpspi3_pcs3: IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 { + pinmux = <0x400e80e0 8 0x400e85fc 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_qtimer1_timer1: IOMUXC_GPIO_EMC_B2_10_QTIMER1_TIMER1 { + pinmux = <0x400e80e0 9 0x400e8640 1 0x400e8324>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_sai2_tx_sync: IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC { + pinmux = <0x400e80e0 2 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_semc_data25: IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 { + pinmux = <0x400e80e0 0 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_in30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_IN30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_inout30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_enet_1g_tdata00: IOMUXC_GPIO_EMC_B2_11_ENET_1G_TDATA00 { + pinmux = <0x400e80e4 2 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B { + pinmux = <0x400e80e4 4 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio8_io21: IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 { + pinmux = <0x400e80e4 10 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21_cm7: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21_CM7 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_qtimer1_timer2: IOMUXC_GPIO_EMC_B2_11_QTIMER1_TIMER2 { + pinmux = <0x400e80e4 9 0x400e8644 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sai3_rx_sync: IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC { + pinmux = <0x400e80e4 3 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_semc_data26: IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 { + pinmux = <0x400e80e4 0 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sim1_trxd: IOMUXC_GPIO_EMC_B2_11_SIM1_TRXD { + pinmux = <0x400e80e4 8 0x400e869c 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_spdif_in: IOMUXC_GPIO_EMC_B2_11_SPDIF_IN { + pinmux = <0x400e80e4 1 0x400e86b4 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_in31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_IN31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_inout31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_enet_1g_tdata01: IOMUXC_GPIO_EMC_B2_12_ENET_1G_TDATA01 { + pinmux = <0x400e80e8 2 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_flexspi2_a_dqs: IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS { + pinmux = <0x400e80e8 4 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio8_io22: IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 { + pinmux = <0x400e80e8 10 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22_cm7: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22_CM7 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_qtimer1_timer3: IOMUXC_GPIO_EMC_B2_12_QTIMER1_TIMER3 { + pinmux = <0x400e80e8 9 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4030 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sai3_rx_bclk: IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK { + pinmux = <0x400e80e8 3 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_semc_data27: IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 { + pinmux = <0x400e80e8 0 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sim1_clk: IOMUXC_GPIO_EMC_B2_12_SIM1_CLK { + pinmux = <0x400e80e8 8 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_spdif_out: IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT { + pinmux = <0x400e80e8 1 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_in32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_IN32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_inout32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_enet_1g_tx_en: IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN { + pinmux = <0x400e80ec 2 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_flexspi2_a_data00: IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 { + pinmux = <0x400e80ec 4 0x400e857c 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio8_io23: IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 { + pinmux = <0x400e80ec 10 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23_cm7: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23_CM7 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_qtimer2_timer0: IOMUXC_GPIO_EMC_B2_13_QTIMER2_TIMER0 { + pinmux = <0x400e80ec 9 0x400e8648 1 0x400e8330>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sai3_rx_data: IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA { + pinmux = <0x400e80ec 3 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_semc_data28: IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 { + pinmux = <0x400e80ec 0 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sim1_rst_b: IOMUXC_GPIO_EMC_B2_13_SIM1_RST_B { + pinmux = <0x400e80ec 8 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_in33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_IN33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_inout33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_enet_1g_tx_clk_io: IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO { + pinmux = <0x400e80f0 2 0x400e84e8 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_flexspi2_a_data01: IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 { + pinmux = <0x400e80f0 4 0x400e8580 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio8_io24: IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 { + pinmux = <0x400e80f0 10 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24_cm7: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24_CM7 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_qtimer2_timer1: IOMUXC_GPIO_EMC_B2_14_QTIMER2_TIMER1 { + pinmux = <0x400e80f0 9 0x400e864c 1 0x400e8334>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sai3_tx_data: IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA { + pinmux = <0x400e80f0 3 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_semc_data29: IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 { + pinmux = <0x400e80f0 0 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sim1_sven: IOMUXC_GPIO_EMC_B2_14_SIM1_SVEN { + pinmux = <0x400e80f0 8 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_in34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_IN34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_inout34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_enet_1g_rdata00: IOMUXC_GPIO_EMC_B2_15_ENET_1G_RDATA00 { + pinmux = <0x400e80f4 2 0x400e84d0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_flexspi2_a_data02: IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 { + pinmux = <0x400e80f4 4 0x400e8584 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio8_io25: IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 { + pinmux = <0x400e80f4 10 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25_cm7: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25_CM7 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_qtimer2_timer2: IOMUXC_GPIO_EMC_B2_15_QTIMER2_TIMER2 { + pinmux = <0x400e80f4 9 0x400e8650 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sai3_tx_bclk: IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK { + pinmux = <0x400e80f4 3 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_semc_data30: IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 { + pinmux = <0x400e80f4 0 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sim1_pd: IOMUXC_GPIO_EMC_B2_15_SIM1_PD { + pinmux = <0x400e80f4 8 0x400e86a0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_in35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_IN35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_inout35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_enet_1g_rdata01: IOMUXC_GPIO_EMC_B2_16_ENET_1G_RDATA01 { + pinmux = <0x400e80f8 2 0x400e84d4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_flexspi2_a_data03: IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 { + pinmux = <0x400e80f8 4 0x400e8588 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio8_io26: IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 { + pinmux = <0x400e80f8 10 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26_cm7: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26_CM7 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_qtimer2_timer3: IOMUXC_GPIO_EMC_B2_16_QTIMER2_TIMER3 { + pinmux = <0x400e80f8 9 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4034 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sai3_tx_sync: IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC { + pinmux = <0x400e80f8 3 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_semc_data31: IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 { + pinmux = <0x400e80f8 0 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sim1_power_fail: IOMUXC_GPIO_EMC_B2_16_SIM1_POWER_FAIL { + pinmux = <0x400e80f8 8 0x400e86a4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_in14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_IN14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_enet_1g_rx_en: IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN { + pinmux = <0x400e80fc 2 0x400e84e0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_flexspi2_a_data04: IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 { + pinmux = <0x400e80fc 4 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio8_io27: IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 { + pinmux = <0x400e80fc 10 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27_cm7: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27_CM7 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_qtimer3_timer0: IOMUXC_GPIO_EMC_B2_17_QTIMER3_TIMER0 { + pinmux = <0x400e80fc 9 0x400e8654 1 0x400e8340>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_sai3_mclk: IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK { + pinmux = <0x400e80fc 3 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_semc_dm03: IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 { + pinmux = <0x400e80fc 0 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_wdog1_wdog_any: IOMUXC_GPIO_EMC_B2_17_WDOG1_WDOG_ANY { + pinmux = <0x400e80fc 8 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_in15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_IN15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_enet_1g_rx_er: IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER { + pinmux = <0x400e8100 2 0x400e84e4 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_ewm_ewm_out_b: IOMUXC_GPIO_EMC_B2_18_EWM_EWM_OUT_B { + pinmux = <0x400e8100 3 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi1_a_dqs: IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS { + pinmux = <0x400e8100 6 0x400e8550 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi2_a_data05: IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 { + pinmux = <0x400e8100 4 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio8_io28: IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 { + pinmux = <0x400e8100 10 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28_cm7: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28_CM7 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_18_QTIMER3_TIMER1 { + pinmux = <0x400e8100 9 0x400e8658 1 0x400e8344>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_semc_dqs4: IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 { + pinmux = <0x400e8100 0 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_wdog1_wdog_b: IOMUXC_GPIO_EMC_B2_18_WDOG1_WDOG_B { + pinmux = <0x400e8100 8 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_IN16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC { + pinmux = <0x400e8104 2 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_ref_clk1: IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK1 { + pinmux = <0x400e8104 3 0x400e84c4 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_MDC { + pinmux = <0x400e8104 1 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_flexspi2_a_data06: IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 { + pinmux = <0x400e8104 4 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio8_io29: IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 { + pinmux = <0x400e8104 10 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29_cm7: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29_CM7 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_qtimer3_timer2: IOMUXC_GPIO_EMC_B2_19_QTIMER3_TIMER2 { + pinmux = <0x400e8104 9 0x400e865c 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_semc_clkx00: IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 { + pinmux = <0x400e8104 0 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_1g_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO { + pinmux = <0x400e8108 2 0x400e84c8 1 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_MDIO { + pinmux = <0x400e8108 1 0x400e84ac 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_flexspi2_a_data07: IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 { + pinmux = <0x400e8108 4 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio8_io30: IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 { + pinmux = <0x400e8108 10 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30_cm7: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30_CM7 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_qtimer3_timer3: IOMUXC_GPIO_EMC_B2_20_QTIMER3_TIMER3 { + pinmux = <0x400e8108 9 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e4038 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_semc_clkx01: IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 { + pinmux = <0x400e8108 0 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_can3_tx: IOMUXC_LPSR_GPIO_LPSR_00_CAN3_TX { + pinmux = <0x40c08000 0 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_cm4_imxrt_txev: IOMUXC_LPSR_GPIO_LPSR_00_CM4_IMXRT_TXEV { + pinmux = <0x40c08000 3 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio12_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO12_IO00 { + pinmux = <0x40c08000 10 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio_mux6_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO_MUX6_IO00 { + pinmux = <0x40c08000 5 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_00_LPUART12_TX { + pinmux = <0x40c08000 6 0x40c080b0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mic_clk: IOMUXC_LPSR_GPIO_LPSR_00_MIC_CLK { + pinmux = <0x40c08000 1 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mqs_right: IOMUXC_LPSR_GPIO_LPSR_00_MQS_RIGHT { + pinmux = <0x40c08000 2 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_00_SAI4_MCLK { + pinmux = <0x40c08000 7 0x40c080c8 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_can3_rx: IOMUXC_LPSR_GPIO_LPSR_01_CAN3_RX { + pinmux = <0x40c08004 0 0x40c08080 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_cm4_imxrt_rxev: IOMUXC_LPSR_GPIO_LPSR_01_CM4_IMXRT_RXEV { + pinmux = <0x40c08004 3 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio12_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO12_IO01 { + pinmux = <0x40c08004 10 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO_MUX6_IO01 { + pinmux = <0x40c08004 5 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_01_LPUART12_RX { + pinmux = <0x40c08004 6 0x40c080ac 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_01_MIC_BITSTREAM00 { + pinmux = <0x40c08004 1 0x40c080b4 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mqs_left: IOMUXC_LPSR_GPIO_LPSR_01_MQS_LEFT { + pinmux = <0x40c08004 2 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio12_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO12_IO02 { + pinmux = <0x40c08008 10 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO_MUX6_IO02 { + pinmux = <0x40c08008 5 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_02_LPSPI5_SCK { + pinmux = <0x40c08008 1 0x40c08098 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_mqs_right: IOMUXC_LPSR_GPIO_LPSR_02_MQS_RIGHT { + pinmux = <0x40c08008 3 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_02_SAI4_TX_DATA { + pinmux = <0x40c08008 2 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_src_boot_mode00: IOMUXC_LPSR_GPIO_LPSR_02_SRC_BOOT_MODE00 { + pinmux = <0x40c08008 0 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio12_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO12_IO03 { + pinmux = <0x40c0800c 10 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO_MUX6_IO03 { + pinmux = <0x40c0800c 5 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_03_LPSPI5_PCS0 { + pinmux = <0x40c0800c 1 0x40c08094 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_mqs_left: IOMUXC_LPSR_GPIO_LPSR_03_MQS_LEFT { + pinmux = <0x40c0800c 3 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_03_SAI4_TX_SYNC { + pinmux = <0x40c0800c 2 0x40c080dc 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_src_boot_mode01: IOMUXC_LPSR_GPIO_LPSR_03_SRC_BOOT_MODE01 { + pinmux = <0x40c0800c 0 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio12_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO12_IO04 { + pinmux = <0x40c08010 10 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO_MUX6_IO04 { + pinmux = <0x40c08010 5 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_04_LPI2C5_SDA { + pinmux = <0x40c08010 0 0x40c08088 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_04_LPSPI5_SDO { + pinmux = <0x40c08010 1 0x40c080a0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_04_LPUART11_TX { + pinmux = <0x40c08010 6 0x40c080a8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart12_rts_b: IOMUXC_LPSR_GPIO_LPSR_04_LPUART12_RTS_B { + pinmux = <0x40c08010 3 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_04_SAI4_TX_BCLK { + pinmux = <0x40c08010 2 0x40c080d8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio12_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO12_IO05 { + pinmux = <0x40c08014 10 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO_MUX6_IO05 { + pinmux = <0x40c08014 5 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_05_LPI2C5_SCL { + pinmux = <0x40c08014 0 0x40c08084 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_05_LPSPI5_SDI { + pinmux = <0x40c08014 1 0x40c0809c 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_05_LPUART11_RX { + pinmux = <0x40c08014 6 0x40c080a4 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart12_cts_b: IOMUXC_LPSR_GPIO_LPSR_05_LPUART12_CTS_B { + pinmux = <0x40c08014 3 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_05_SAI4_MCLK { + pinmux = <0x40c08014 2 0x40c080c8 1 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_can3_tx: IOMUXC_LPSR_GPIO_LPSR_06_CAN3_TX { + pinmux = <0x40c08018 6 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio12_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO12_IO06 { + pinmux = <0x40c08018 10 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO_MUX6_IO06 { + pinmux = <0x40c08018 5 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_06_LPI2C6_SDA { + pinmux = <0x40c08018 0 0x40c08090 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi5_pcs1: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI5_PCS1 { + pinmux = <0x40c08018 8 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi6_pcs3: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI6_PCS3 { + pinmux = <0x40c08018 4 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_06_LPUART12_TX { + pinmux = <0x40c08018 3 0x40c080b0 1 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_06_PIT2_TRIGGER03 { + pinmux = <0x40c08018 7 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_06_SAI4_RX_DATA { + pinmux = <0x40c08018 2 0x40c080d0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_can3_rx: IOMUXC_LPSR_GPIO_LPSR_07_CAN3_RX { + pinmux = <0x40c0801c 6 0x40c08080 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio12_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO12_IO07 { + pinmux = <0x40c0801c 10 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO_MUX6_IO07 { + pinmux = <0x40c0801c 5 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_07_LPI2C6_SCL { + pinmux = <0x40c0801c 0 0x40c0808c 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi5_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI5_PCS2 { + pinmux = <0x40c0801c 8 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi6_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI6_PCS2 { + pinmux = <0x40c0801c 4 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_07_LPUART12_RX { + pinmux = <0x40c0801c 3 0x40c080ac 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_07_PIT2_TRIGGER02 { + pinmux = <0x40c0801c 7 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_07_SAI4_RX_BCLK { + pinmux = <0x40c0801c 2 0x40c080cc 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_can3_tx: IOMUXC_LPSR_GPIO_LPSR_08_CAN3_TX { + pinmux = <0x40c08020 1 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio12_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO12_IO08 { + pinmux = <0x40c08020 10 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO_MUX6_IO08 { + pinmux = <0x40c08020 5 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_08_LPI2C5_SDA { + pinmux = <0x40c08020 6 0x40c08088 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi5_pcs3: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI5_PCS3 { + pinmux = <0x40c08020 8 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi6_pcs1: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI6_PCS1 { + pinmux = <0x40c08020 4 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_08_LPUART11_TX { + pinmux = <0x40c08020 0 0x40c080a8 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_mic_clk: IOMUXC_LPSR_GPIO_LPSR_08_MIC_CLK { + pinmux = <0x40c08020 3 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_08_PIT2_TRIGGER01 { + pinmux = <0x40c08020 7 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_08_SAI4_RX_SYNC { + pinmux = <0x40c08020 2 0x40c080d4 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_can3_rx: IOMUXC_LPSR_GPIO_LPSR_09_CAN3_RX { + pinmux = <0x40c08024 1 0x40c08080 2 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio12_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO12_IO09 { + pinmux = <0x40c08024 10 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO_MUX6_IO09 { + pinmux = <0x40c08024 5 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_09_LPI2C5_SCL { + pinmux = <0x40c08024 6 0x40c08084 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpspi6_pcs0: IOMUXC_LPSR_GPIO_LPSR_09_LPSPI6_PCS0 { + pinmux = <0x40c08024 4 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_09_LPUART11_RX { + pinmux = <0x40c08024 0 0x40c080a4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_09_MIC_BITSTREAM00 { + pinmux = <0x40c08024 3 0x40c080b4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_09_PIT2_TRIGGER00 { + pinmux = <0x40c08024 2 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_09_SAI4_TX_DATA { + pinmux = <0x40c08024 7 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio12_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO12_IO10 { + pinmux = <0x40c08028 10 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO_MUX6_IO10 { + pinmux = <0x40c08028 5 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_jtag_mux_trstb: IOMUXC_LPSR_GPIO_LPSR_10_JTAG_MUX_TRSTB { + pinmux = <0x40c08028 0 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c5_scls: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C5_SCLS { + pinmux = <0x40c08028 6 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C6_SDA { + pinmux = <0x40c08028 2 0x40c08090 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpspi6_sck: IOMUXC_LPSR_GPIO_LPSR_10_LPSPI6_SCK { + pinmux = <0x40c08028 4 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart11_cts_b: IOMUXC_LPSR_GPIO_LPSR_10_LPUART11_CTS_B { + pinmux = <0x40c08028 1 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_10_LPUART12_TX { + pinmux = <0x40c08028 8 0x40c080b0 2 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_10_MIC_BITSTREAM01 { + pinmux = <0x40c08028 3 0x40c080b8 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_10_SAI4_TX_SYNC { + pinmux = <0x40c08028 7 0x40c080dc 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_arm_trace_swo: IOMUXC_LPSR_GPIO_LPSR_11_ARM_TRACE_SWO { + pinmux = <0x40c0802c 7 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio12_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO12_IO11 { + pinmux = <0x40c0802c 10 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO_MUX6_IO11 { + pinmux = <0x40c0802c 5 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_jtag_mux_tdo: IOMUXC_LPSR_GPIO_LPSR_11_JTAG_MUX_TDO { + pinmux = <0x40c0802c 0 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c5_sdas: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C5_SDAS { + pinmux = <0x40c0802c 6 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C6_SCL { + pinmux = <0x40c0802c 2 0x40c0808c 1 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpspi6_sdo: IOMUXC_LPSR_GPIO_LPSR_11_LPSPI6_SDO { + pinmux = <0x40c0802c 4 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart11_rts_b: IOMUXC_LPSR_GPIO_LPSR_11_LPUART11_RTS_B { + pinmux = <0x40c0802c 1 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_11_LPUART12_RX { + pinmux = <0x40c0802c 8 0x40c080ac 2 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_11_MIC_BITSTREAM02 { + pinmux = <0x40c0802c 3 0x40c080bc 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio12_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO12_IO12 { + pinmux = <0x40c08030 10 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO_MUX6_IO12 { + pinmux = <0x40c08030 5 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_jtag_mux_tdi: IOMUXC_LPSR_GPIO_LPSR_12_JTAG_MUX_TDI { + pinmux = <0x40c08030 0 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpi2c5_hreq: IOMUXC_LPSR_GPIO_LPSR_12_LPI2C5_HREQ { + pinmux = <0x40c08030 6 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI5_SCK { + pinmux = <0x40c08030 8 0x40c08098 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi6_sdi: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI6_SDI { + pinmux = <0x40c08030 4 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_12_MIC_BITSTREAM03 { + pinmux = <0x40c08030 3 0x40c080c0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_12_PIT2_TRIGGER00 { + pinmux = <0x40c08030 1 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_12_SAI4_TX_BCLK { + pinmux = <0x40c08030 7 0x40c080d8 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio12_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO12_IO13 { + pinmux = <0x40c08034 10 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO_MUX6_IO13 { + pinmux = <0x40c08034 5 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_jtag_mux_mod: IOMUXC_LPSR_GPIO_LPSR_13_JTAG_MUX_MOD { + pinmux = <0x40c08034 0 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_13_LPSPI5_PCS0 { + pinmux = <0x40c08034 8 0x40c08094 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_13_MIC_BITSTREAM01 { + pinmux = <0x40c08034 1 0x40c080b8 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_13_PIT2_TRIGGER01 { + pinmux = <0x40c08034 2 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_13_SAI4_RX_DATA { + pinmux = <0x40c08034 7 0x40c080d0 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio12_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO12_IO14 { + pinmux = <0x40c08038 10 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO_MUX6_IO14 { + pinmux = <0x40c08038 5 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_jtag_mux_tck: IOMUXC_LPSR_GPIO_LPSR_14_JTAG_MUX_TCK { + pinmux = <0x40c08038 0 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_14_LPSPI5_SDO { + pinmux = <0x40c08038 8 0x40c080a0 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_14_MIC_BITSTREAM02 { + pinmux = <0x40c08038 1 0x40c080bc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_14_PIT2_TRIGGER02 { + pinmux = <0x40c08038 2 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_14_SAI4_RX_BCLK { + pinmux = <0x40c08038 7 0x40c080cc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio12_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO12_IO15 { + pinmux = <0x40c0803c 10 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO_MUX6_IO15 { + pinmux = <0x40c0803c 5 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_jtag_mux_tms: IOMUXC_LPSR_GPIO_LPSR_15_JTAG_MUX_TMS { + pinmux = <0x40c0803c 0 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_15_LPSPI5_SDI { + pinmux = <0x40c0803c 8 0x40c0809c 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_15_MIC_BITSTREAM03 { + pinmux = <0x40c0803c 1 0x40c080c0 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_15_PIT2_TRIGGER03 { + pinmux = <0x40c0803c 2 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_15_SAI4_RX_SYNC { + pinmux = <0x40c0803c 7 0x40c080d4 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi2_a_ss0_b: IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B { + pinmux = <0x400e819c 6 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio10_io03: IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 { + pinmux = <0x400e819c 10 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio_mux4_io03: IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 { + pinmux = <0x400e819c 5 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpt4_capture1: IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 { + pinmux = <0x400e819c 3 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_kpp_row07: IOMUXC_GPIO_SD_B1_00_KPP_ROW07 { + pinmux = <0x400e819c 8 0x400e85a8 1 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc1_cmd: IOMUXC_GPIO_SD_B1_00_USDHC1_CMD { + pinmux = <0x400e819c 0 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi2_a_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK { + pinmux = <0x400e81a0 6 0x400e858c 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio10_io04: IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 { + pinmux = <0x400e81a0 10 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio_mux4_io04: IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 { + pinmux = <0x400e81a0 5 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpt4_capture2: IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 { + pinmux = <0x400e81a0 3 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_kpp_col07: IOMUXC_GPIO_SD_B1_01_KPP_COL07 { + pinmux = <0x400e81a0 8 0x400e85a0 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc1_clk: IOMUXC_GPIO_SD_B1_01_USDHC1_CLK { + pinmux = <0x400e81a0 0 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_in21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_inout21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81a4 9 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi2_a_data00: IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 { + pinmux = <0x400e81a4 6 0x400e857c 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio10_io05: IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 { + pinmux = <0x400e81a4 10 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio_mux4_io05: IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 { + pinmux = <0x400e81a4 5 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpt4_compare1: IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 { + pinmux = <0x400e81a4 3 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_kpp_row06: IOMUXC_GPIO_SD_B1_02_KPP_ROW06 { + pinmux = <0x400e81a4 8 0x400e85a4 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc1_data0: IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 { + pinmux = <0x400e81a4 0 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_in22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_inout22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi1_b_ss1_b: IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B { + pinmux = <0x400e81a8 9 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi2_a_data01: IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 { + pinmux = <0x400e81a8 6 0x400e8580 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio10_io06: IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 { + pinmux = <0x400e81a8 10 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio_mux4_io06: IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 { + pinmux = <0x400e81a8 5 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpt4_compare2: IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 { + pinmux = <0x400e81a8 3 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_kpp_col06: IOMUXC_GPIO_SD_B1_03_KPP_COL06 { + pinmux = <0x400e81a8 8 0x400e859c 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc1_data1: IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 { + pinmux = <0x400e81a8 0 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_in23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_inout23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81ac 8 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi2_a_data02: IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 { + pinmux = <0x400e81ac 6 0x400e8584 1 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio10_io07: IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 { + pinmux = <0x400e81ac 10 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio_mux4_io07: IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 { + pinmux = <0x400e81ac 5 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpt4_compare3: IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 { + pinmux = <0x400e81ac 3 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc1_data2: IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 { + pinmux = <0x400e81ac 0 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_in24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_inout24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi1_b_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS { + pinmux = <0x400e81b0 8 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi2_a_data03: IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 { + pinmux = <0x400e81b0 6 0x400e8588 1 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio10_io08: IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 { + pinmux = <0x400e81b0 10 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio_mux4_io08: IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 { + pinmux = <0x400e81b0 5 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpt4_clk: IOMUXC_GPIO_SD_B1_05_GPT4_CLK { + pinmux = <0x400e81b0 3 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc1_data3: IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 { + pinmux = <0x400e81b0 0 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_in25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_inout25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_enet_1g_rx_en: IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN { + pinmux = <0x400e81b4 2 0x400e84e0 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_flexspi1_b_data03: IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 { + pinmux = <0x400e81b4 1 0x400e8570 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio10_io09: IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 { + pinmux = <0x400e81b4 10 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio_mux4_io09: IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 { + pinmux = <0x400e81b4 5 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpspi4_sck: IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK { + pinmux = <0x400e81b4 4 0x400e8610 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpuart9_tx: IOMUXC_GPIO_SD_B2_00_LPUART9_TX { + pinmux = <0x400e81b4 3 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_usdhc2_data3: IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 { + pinmux = <0x400e81b4 0 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_enet_1g_rx_clk: IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK { + pinmux = <0x400e81b8 2 0x400e84cc 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_flexspi1_b_data02: IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 { + pinmux = <0x400e81b8 1 0x400e856c 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio10_io10: IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 { + pinmux = <0x400e81b8 10 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio_mux4_io10: IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 { + pinmux = <0x400e81b8 5 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpspi4_pcs0: IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 { + pinmux = <0x400e81b8 4 0x400e860c 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpuart9_rx: IOMUXC_GPIO_SD_B2_01_LPUART9_RX { + pinmux = <0x400e81b8 3 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_usdhc2_data2: IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 { + pinmux = <0x400e81b8 0 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_enet_1g_rdata00: IOMUXC_GPIO_SD_B2_02_ENET_1G_RDATA00 { + pinmux = <0x400e81bc 2 0x400e84d0 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_flexspi1_b_data01: IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 { + pinmux = <0x400e81bc 1 0x400e8568 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio10_io11: IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 { + pinmux = <0x400e81bc 10 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio_mux4_io11: IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 { + pinmux = <0x400e81bc 5 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpspi4_sdo: IOMUXC_GPIO_SD_B2_02_LPSPI4_SDO { + pinmux = <0x400e81bc 4 0x400e8618 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpuart9_cts_b: IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B { + pinmux = <0x400e81bc 3 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_usdhc2_data1: IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 { + pinmux = <0x400e81bc 0 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_enet_1g_rdata01: IOMUXC_GPIO_SD_B2_03_ENET_1G_RDATA01 { + pinmux = <0x400e81c0 2 0x400e84d4 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_flexspi1_b_data00: IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 { + pinmux = <0x400e81c0 1 0x400e8564 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio10_io12: IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 { + pinmux = <0x400e81c0 10 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio_mux4_io12: IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 { + pinmux = <0x400e81c0 5 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpspi4_sdi: IOMUXC_GPIO_SD_B2_03_LPSPI4_SDI { + pinmux = <0x400e81c0 4 0x400e8614 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpuart9_rts_b: IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B { + pinmux = <0x400e81c0 3 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_usdhc2_data0: IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 { + pinmux = <0x400e81c0 0 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_enet_1g_rdata02: IOMUXC_GPIO_SD_B2_04_ENET_1G_RDATA02 { + pinmux = <0x400e81c4 2 0x400e84d8 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81c4 3 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_b_sclk: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK { + pinmux = <0x400e81c4 1 0x400e8578 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio10_io13: IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 { + pinmux = <0x400e81c4 10 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio_mux4_io13: IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 { + pinmux = <0x400e81c4 5 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_lpspi4_pcs1: IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 { + pinmux = <0x400e81c4 4 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_usdhc2_clk: IOMUXC_GPIO_SD_B2_04_USDHC2_CLK { + pinmux = <0x400e81c4 0 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_enet_1g_rdata03: IOMUXC_GPIO_SD_B2_05_ENET_1G_RDATA03 { + pinmux = <0x400e81c8 2 0x400e84dc 1 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_a_dqs: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS { + pinmux = <0x400e81c8 1 0x400e8550 2 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81c8 3 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio10_io14: IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 { + pinmux = <0x400e81c8 10 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio_mux4_io14: IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 { + pinmux = <0x400e81c8 5 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_lpspi4_pcs2: IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 { + pinmux = <0x400e81c8 4 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_usdhc2_cmd: IOMUXC_GPIO_SD_B2_05_USDHC2_CMD { + pinmux = <0x400e81c8 0 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_enet_1g_tdata03: IOMUXC_GPIO_SD_B2_06_ENET_1G_TDATA03 { + pinmux = <0x400e81cc 2 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_flexspi1_a_ss0_b: IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B { + pinmux = <0x400e81cc 1 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio10_io15: IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 { + pinmux = <0x400e81cc 10 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio_mux4_io15: IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 { + pinmux = <0x400e81cc 5 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpt6_capture1: IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 { + pinmux = <0x400e81cc 4 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_lpspi4_pcs3: IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 { + pinmux = <0x400e81cc 3 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B { + pinmux = <0x400e81cc 0 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_1g_tdata02: IOMUXC_GPIO_SD_B2_07_ENET_1G_TDATA02 { + pinmux = <0x400e81d0 2 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_tx_er: IOMUXC_GPIO_SD_B2_07_ENET_TX_ER { + pinmux = <0x400e81d0 8 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_flexspi1_a_sclk: IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK { + pinmux = <0x400e81d0 1 0x400e8574 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio10_io16: IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 { + pinmux = <0x400e81d0 10 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio_mux4_io16: IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 { + pinmux = <0x400e81d0 5 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpt6_capture2: IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 { + pinmux = <0x400e81d0 4 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpspi2_sck: IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK { + pinmux = <0x400e81d0 6 0x400e85e4 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpuart3_cts_b: IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B { + pinmux = <0x400e81d0 3 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_usdhc2_strobe: IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE { + pinmux = <0x400e81d0 0 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_enet_1g_tdata01: IOMUXC_GPIO_SD_B2_08_ENET_1G_TDATA01 { + pinmux = <0x400e81d4 2 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_flexspi1_a_data00: IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 { + pinmux = <0x400e81d4 1 0x400e8554 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio10_io17: IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 { + pinmux = <0x400e81d4 10 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio_mux4_io17: IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 { + pinmux = <0x400e81d4 5 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpt6_compare1: IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 { + pinmux = <0x400e81d4 4 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpspi2_pcs0: IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 { + pinmux = <0x400e81d4 6 0x400e85dc 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpuart3_rts_b: IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B { + pinmux = <0x400e81d4 3 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_usdhc2_data4: IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 { + pinmux = <0x400e81d4 0 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_enet_1g_tdata00: IOMUXC_GPIO_SD_B2_09_ENET_1G_TDATA00 { + pinmux = <0x400e81d8 2 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_flexspi1_a_data01: IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 { + pinmux = <0x400e81d8 1 0x400e8558 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio10_io18: IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 { + pinmux = <0x400e81d8 10 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio_mux4_io18: IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 { + pinmux = <0x400e81d8 5 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpt6_compare2: IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 { + pinmux = <0x400e81d8 4 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpspi2_sdo: IOMUXC_GPIO_SD_B2_09_LPSPI2_SDO { + pinmux = <0x400e81d8 6 0x400e85ec 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpuart5_cts_b: IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B { + pinmux = <0x400e81d8 3 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_usdhc2_data5: IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 { + pinmux = <0x400e81d8 0 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_enet_1g_tx_en: IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN { + pinmux = <0x400e81dc 2 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_flexspi1_a_data02: IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 { + pinmux = <0x400e81dc 1 0x400e855c 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio10_io19: IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 { + pinmux = <0x400e81dc 10 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio_mux4_io19: IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 { + pinmux = <0x400e81dc 5 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpt6_compare3: IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 { + pinmux = <0x400e81dc 4 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpspi2_sdi: IOMUXC_GPIO_SD_B2_10_LPSPI2_SDI { + pinmux = <0x400e81dc 6 0x400e85e8 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpuart5_rts_b: IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B { + pinmux = <0x400e81dc 3 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_usdhc2_data6: IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 { + pinmux = <0x400e81dc 0 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_ref_clk1: IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e81e0 3 0x400e84c4 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_tx_clk_io: IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e81e0 2 0x400e84e8 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_flexspi1_a_data03: IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 { + pinmux = <0x400e81e0 1 0x400e8560 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio10_io20: IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 { + pinmux = <0x400e81e0 10 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio_mux4_io20: IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 { + pinmux = <0x400e81e0 5 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpt6_clk: IOMUXC_GPIO_SD_B2_11_GPT6_CLK { + pinmux = <0x400e81e0 4 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_lpspi2_pcs1: IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 { + pinmux = <0x400e81e0 6 0x400e85e0 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_usdhc2_data7: IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 { + pinmux = <0x400e81e0 0 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03: IOMUXC_SNVS_GPIO_SNVS_00_DIG_GPIO13_IO03 { + pinmux = <0x40c9400c 5 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_snvs_lp_tamper00: IOMUXC_SNVS_GPIO_SNVS_00_DIG_SNVS_LP_TAMPER00 { + pinmux = <0x40c9400c 0 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04: IOMUXC_SNVS_GPIO_SNVS_01_DIG_GPIO13_IO04 { + pinmux = <0x40c94010 5 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_snvs_lp_tamper01: IOMUXC_SNVS_GPIO_SNVS_01_DIG_SNVS_LP_TAMPER01 { + pinmux = <0x40c94010 0 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05: IOMUXC_SNVS_GPIO_SNVS_02_DIG_GPIO13_IO05 { + pinmux = <0x40c94014 5 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_snvs_lp_tamper02: IOMUXC_SNVS_GPIO_SNVS_02_DIG_SNVS_LP_TAMPER02 { + pinmux = <0x40c94014 0 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06: IOMUXC_SNVS_GPIO_SNVS_03_DIG_GPIO13_IO06 { + pinmux = <0x40c94018 5 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_snvs_lp_tamper03: IOMUXC_SNVS_GPIO_SNVS_03_DIG_SNVS_LP_TAMPER03 { + pinmux = <0x40c94018 0 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07: IOMUXC_SNVS_GPIO_SNVS_04_DIG_GPIO13_IO07 { + pinmux = <0x40c9401c 5 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_snvs_lp_tamper04: IOMUXC_SNVS_GPIO_SNVS_04_DIG_SNVS_LP_TAMPER04 { + pinmux = <0x40c9401c 0 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08: IOMUXC_SNVS_GPIO_SNVS_05_DIG_GPIO13_IO08 { + pinmux = <0x40c94020 5 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_snvs_lp_tamper05: IOMUXC_SNVS_GPIO_SNVS_05_DIG_SNVS_LP_TAMPER05 { + pinmux = <0x40c94020 0 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09: IOMUXC_SNVS_GPIO_SNVS_06_DIG_GPIO13_IO09 { + pinmux = <0x40c94024 5 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_snvs_lp_tamper06: IOMUXC_SNVS_GPIO_SNVS_06_DIG_SNVS_LP_TAMPER06 { + pinmux = <0x40c94024 0 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10: IOMUXC_SNVS_GPIO_SNVS_07_DIG_GPIO13_IO10 { + pinmux = <0x40c94028 5 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_snvs_lp_tamper07: IOMUXC_SNVS_GPIO_SNVS_07_DIG_SNVS_LP_TAMPER07 { + pinmux = <0x40c94028 0 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11: IOMUXC_SNVS_GPIO_SNVS_08_DIG_GPIO13_IO11 { + pinmux = <0x40c9402c 5 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_snvs_lp_tamper08: IOMUXC_SNVS_GPIO_SNVS_08_DIG_SNVS_LP_TAMPER08 { + pinmux = <0x40c9402c 0 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12: IOMUXC_SNVS_GPIO_SNVS_09_DIG_GPIO13_IO12 { + pinmux = <0x40c94030 5 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_snvs_lp_tamper09: IOMUXC_SNVS_GPIO_SNVS_09_DIG_SNVS_LP_TAMPER09 { + pinmux = <0x40c94030 0 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_dig_src_reset_b: IOMUXC_SNVS_ONOFF_DIG_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x40c9403c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_gpio13_io01: IOMUXC_SNVS_PMIC_ON_REQ_DIG_GPIO13_IO01 { + pinmux = <0x40c94004 5 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_snvs_lp_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ { + pinmux = <0x40c94004 0 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_gpio13_io02: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_GPIO13_IO02 { + pinmux = <0x40c94008 5 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_pgmc_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_PGMC_PMIC_VSTBY_REQ { + pinmux = <0x40c94008 0 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_dig_src_por_b: IOMUXC_SNVS_POR_B_DIG_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x40c94038>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_dig_test_mode: IOMUXC_SNVS_TEST_MODE_DIG_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x40c94034>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_dig_gpio13_io00: IOMUXC_SNVS_WAKEUP_DIG_GPIO13_IO00 { + pinmux = <0x40c94000 5 0x0 0 0x40c94040>; + pin-snvs; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1165xvm5a-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1165xvm5a-pinctrl.dtsi new file mode 100644 index 000000000..5d537a61b --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1165xvm5a-pinctrl.dtsi @@ -0,0 +1,5984 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1165XVM5A + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_00_acmp1_in1: IOMUXC_GPIO_AD_00_ACMP1_IN1 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_can2_tx: IOMUXC_GPIO_AD_00_CAN2_TX { + pinmux = <0x400e810c 1 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_enet_1g_1588_event1_in: IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN { + pinmux = <0x400e810c 2 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexio2_flexio00: IOMUXC_GPIO_AD_00_FLEXIO2_FLEXIO00 { + pinmux = <0x400e810c 8 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexpwm1_pwm0_a: IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A { + pinmux = <0x400e810c 4 0x400e8500 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexspi2_b_ss1_b: IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B { + pinmux = <0x400e810c 9 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio8_io31: IOMUXC_GPIO_AD_00_GPIO8_IO31 { + pinmux = <0x400e810c 10 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31_cm7: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31_CM7 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpt2_capture1: IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 { + pinmux = <0x400e810c 3 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_lpuart7_tx: IOMUXC_GPIO_AD_00_LPUART7_TX { + pinmux = <0x400e810c 6 0x400e8630 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_sim1_trxd: IOMUXC_GPIO_AD_00_SIM1_TRXD { + pinmux = <0x400e810c 0 0x400e869c 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_acmp1_in2: IOMUXC_GPIO_AD_01_ACMP1_IN2 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_can2_rx: IOMUXC_GPIO_AD_01_CAN2_RX { + pinmux = <0x400e8110 1 0x400e849c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_enet_1g_1588_event1_out: IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT { + pinmux = <0x400e8110 2 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexio2_flexio01: IOMUXC_GPIO_AD_01_FLEXIO2_FLEXIO01 { + pinmux = <0x400e8110 8 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexpwm1_pwm0_b: IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B { + pinmux = <0x400e8110 4 0x400e850c 1 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexspi2_a_ss1_b: IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B { + pinmux = <0x400e8110 9 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio9_io00: IOMUXC_GPIO_AD_01_GPIO9_IO00 { + pinmux = <0x400e8110 10 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00_cm7: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00_CM7 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpt2_capture2: IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 { + pinmux = <0x400e8110 3 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_lpuart7_rx: IOMUXC_GPIO_AD_01_LPUART7_RX { + pinmux = <0x400e8110 6 0x400e862c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_sim1_clk: IOMUXC_GPIO_AD_01_SIM1_CLK { + pinmux = <0x400e8110 0 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_acmp1_in3: IOMUXC_GPIO_AD_02_ACMP1_IN3 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_enet_1g_1588_event2_in: IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN { + pinmux = <0x400e8114 2 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexio2_flexio02: IOMUXC_GPIO_AD_02_FLEXIO2_FLEXIO02 { + pinmux = <0x400e8114 8 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexpwm1_pwm1_a: IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A { + pinmux = <0x400e8114 4 0x400e8504 1 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio9_io01: IOMUXC_GPIO_AD_02_GPIO9_IO01 { + pinmux = <0x400e8114 10 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01_cm7: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01_CM7 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpt2_compare1: IOMUXC_GPIO_AD_02_GPT2_COMPARE1 { + pinmux = <0x400e8114 3 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart7_cts_b: IOMUXC_GPIO_AD_02_LPUART7_CTS_B { + pinmux = <0x400e8114 1 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart8_tx: IOMUXC_GPIO_AD_02_LPUART8_TX { + pinmux = <0x400e8114 6 0x400e8638 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_sim1_rst_b: IOMUXC_GPIO_AD_02_SIM1_RST_B { + pinmux = <0x400e8114 0 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_video_mux_ext_dcic1: IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e8114 9 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_acmp1_in4: IOMUXC_GPIO_AD_03_ACMP1_IN4 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_enet_1g_1588_event2_out: IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT { + pinmux = <0x400e8118 2 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexio2_flexio03: IOMUXC_GPIO_AD_03_FLEXIO2_FLEXIO03 { + pinmux = <0x400e8118 8 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexpwm1_pwm1_b: IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B { + pinmux = <0x400e8118 4 0x400e8510 1 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio9_io02: IOMUXC_GPIO_AD_03_GPIO9_IO02 { + pinmux = <0x400e8118 10 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02_cm7: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02_CM7 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpt2_compare2: IOMUXC_GPIO_AD_03_GPT2_COMPARE2 { + pinmux = <0x400e8118 3 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart7_rts_b: IOMUXC_GPIO_AD_03_LPUART7_RTS_B { + pinmux = <0x400e8118 1 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart8_rx: IOMUXC_GPIO_AD_03_LPUART8_RX { + pinmux = <0x400e8118 6 0x400e8634 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_sim1_sven: IOMUXC_GPIO_AD_03_SIM1_SVEN { + pinmux = <0x400e8118 0 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_video_mux_ext_dcic2: IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8118 9 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_acmp2_in1: IOMUXC_GPIO_AD_04_ACMP2_IN1 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_enet_1g_1588_event3_in: IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN { + pinmux = <0x400e811c 2 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexio2_flexio04: IOMUXC_GPIO_AD_04_FLEXIO2_FLEXIO04 { + pinmux = <0x400e811c 8 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexpwm1_pwm2_a: IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A { + pinmux = <0x400e811c 4 0x400e8508 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio9_io03: IOMUXC_GPIO_AD_04_GPIO9_IO03 { + pinmux = <0x400e811c 10 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03_cm7: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03_CM7 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpt2_compare3: IOMUXC_GPIO_AD_04_GPT2_COMPARE3 { + pinmux = <0x400e811c 3 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_lpuart8_cts_b: IOMUXC_GPIO_AD_04_LPUART8_CTS_B { + pinmux = <0x400e811c 1 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_qtimer4_timer0: IOMUXC_GPIO_AD_04_QTIMER4_TIMER0 { + pinmux = <0x400e811c 9 0x400e8660 1 0x400e8360>; + pin-pue; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_sim1_pd: IOMUXC_GPIO_AD_04_SIM1_PD { + pinmux = <0x400e811c 0 0x400e86a0 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_wdog1_wdog_b: IOMUXC_GPIO_AD_04_WDOG1_WDOG_B { + pinmux = <0x400e811c 6 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_acmp2_in2: IOMUXC_GPIO_AD_05_ACMP2_IN2 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_enet_1g_1588_event3_out: IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT { + pinmux = <0x400e8120 2 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexio2_flexio05: IOMUXC_GPIO_AD_05_FLEXIO2_FLEXIO05 { + pinmux = <0x400e8120 8 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexpwm1_pwm2_b: IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B { + pinmux = <0x400e8120 4 0x400e8514 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio9_io04: IOMUXC_GPIO_AD_05_GPIO9_IO04 { + pinmux = <0x400e8120 10 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04_cm7: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04_CM7 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpt2_clk: IOMUXC_GPIO_AD_05_GPT2_CLK { + pinmux = <0x400e8120 3 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_lpuart8_rts_b: IOMUXC_GPIO_AD_05_LPUART8_RTS_B { + pinmux = <0x400e8120 1 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_qtimer4_timer1: IOMUXC_GPIO_AD_05_QTIMER4_TIMER1 { + pinmux = <0x400e8120 9 0x400e8664 1 0x400e8364>; + pin-pue; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_sim1_power_fail: IOMUXC_GPIO_AD_05_SIM1_POWER_FAIL { + pinmux = <0x400e8120 0 0x400e86a4 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_wdog2_wdog_b: IOMUXC_GPIO_AD_05_WDOG2_WDOG_B { + pinmux = <0x400e8120 6 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_adc1_ch0a: IOMUXC_GPIO_AD_06_ADC1_CH0A { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_can1_tx: IOMUXC_GPIO_AD_06_CAN1_TX { + pinmux = <0x400e8124 1 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_enet_1588_event1_in: IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN { + pinmux = <0x400e8124 6 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexio2_flexio06: IOMUXC_GPIO_AD_06_FLEXIO2_FLEXIO06 { + pinmux = <0x400e8124 8 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexpwm1_pwm0_x: IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X { + pinmux = <0x400e8124 11 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio9_io05: IOMUXC_GPIO_AD_06_GPIO9_IO05 { + pinmux = <0x400e8124 10 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05_cm7: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05_CM7 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpt3_capture1: IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 { + pinmux = <0x400e8124 3 0x400e8590 1 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_qtimer4_timer2: IOMUXC_GPIO_AD_06_QTIMER4_TIMER2 { + pinmux = <0x400e8124 9 0x400e8668 0 0x400e8368>; + pin-pue; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_sim2_trxd: IOMUXC_GPIO_AD_06_SIM2_TRXD { + pinmux = <0x400e8124 2 0x400e86a8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_usb_otg2_oc: IOMUXC_GPIO_AD_06_USB_OTG2_OC { + pinmux = <0x400e8124 0 0x400e86b8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_adc1_ch0b: IOMUXC_GPIO_AD_07_ADC1_CH0B { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_can1_rx: IOMUXC_GPIO_AD_07_CAN1_RX { + pinmux = <0x400e8128 1 0x400e8498 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_enet_1588_event1_out: IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT { + pinmux = <0x400e8128 6 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexio2_flexio07: IOMUXC_GPIO_AD_07_FLEXIO2_FLEXIO07 { + pinmux = <0x400e8128 8 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexpwm1_pwm1_x: IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X { + pinmux = <0x400e8128 11 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio9_io06: IOMUXC_GPIO_AD_07_GPIO9_IO06 { + pinmux = <0x400e8128 10 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06_cm7: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06_CM7 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpt3_capture2: IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 { + pinmux = <0x400e8128 3 0x400e8594 1 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_qtimer4_timer3: IOMUXC_GPIO_AD_07_QTIMER4_TIMER3 { + pinmux = <0x400e8128 9 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e403c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_sim2_clk: IOMUXC_GPIO_AD_07_SIM2_CLK { + pinmux = <0x400e8128 2 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_usb_otg2_pwr: IOMUXC_GPIO_AD_07_USB_OTG2_PWR { + pinmux = <0x400e8128 0 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_adc1_ch1a: IOMUXC_GPIO_AD_08_ADC1_CH1A { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_enet_1588_event2_in: IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN { + pinmux = <0x400e812c 6 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexio2_flexio08: IOMUXC_GPIO_AD_08_FLEXIO2_FLEXIO08 { + pinmux = <0x400e812c 8 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexpwm1_pwm2_x: IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X { + pinmux = <0x400e812c 11 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio9_io07: IOMUXC_GPIO_AD_08_GPIO9_IO07 { + pinmux = <0x400e812c 10 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07_cm7: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07_CM7 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpt3_compare1: IOMUXC_GPIO_AD_08_GPT3_COMPARE1 { + pinmux = <0x400e812c 3 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_lpi2c1_scl: IOMUXC_GPIO_AD_08_LPI2C1_SCL { + pinmux = <0x400e812c 1 0x400e85ac 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_sim2_rst_b: IOMUXC_GPIO_AD_08_SIM2_RST_B { + pinmux = <0x400e812c 2 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_usbphy2_otg_id: IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID { + pinmux = <0x400e812c 0 0x400e86c4 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_adc1_ch1b: IOMUXC_GPIO_AD_09_ADC1_CH1B { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_enet_1588_event2_out: IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT { + pinmux = <0x400e8130 6 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexio2_flexio09: IOMUXC_GPIO_AD_09_FLEXIO2_FLEXIO09 { + pinmux = <0x400e8130 8 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexpwm1_pwm3_x: IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X { + pinmux = <0x400e8130 11 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio9_io08: IOMUXC_GPIO_AD_09_GPIO9_IO08 { + pinmux = <0x400e8130 10 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08_cm7: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08_CM7 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpt3_compare2: IOMUXC_GPIO_AD_09_GPT3_COMPARE2 { + pinmux = <0x400e8130 3 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_lpi2c1_sda: IOMUXC_GPIO_AD_09_LPI2C1_SDA { + pinmux = <0x400e8130 1 0x400e85b0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_sim2_sven: IOMUXC_GPIO_AD_09_SIM2_SVEN { + pinmux = <0x400e8130 2 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_usbphy1_otg_id: IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID { + pinmux = <0x400e8130 0 0x400e86c0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_adc1_ch2a: IOMUXC_GPIO_AD_10_ADC1_CH2A { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_enet_1588_event3_in: IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN { + pinmux = <0x400e8134 6 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexio2_flexio10: IOMUXC_GPIO_AD_10_FLEXIO2_FLEXIO10 { + pinmux = <0x400e8134 8 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexpwm2_pwm0_x: IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X { + pinmux = <0x400e8134 11 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio9_io09: IOMUXC_GPIO_AD_10_GPIO9_IO09 { + pinmux = <0x400e8134 10 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09_cm7: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09_CM7 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpt3_compare3: IOMUXC_GPIO_AD_10_GPT3_COMPARE3 { + pinmux = <0x400e8134 3 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_lpi2c1_scls: IOMUXC_GPIO_AD_10_LPI2C1_SCLS { + pinmux = <0x400e8134 1 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_sim2_pd: IOMUXC_GPIO_AD_10_SIM2_PD { + pinmux = <0x400e8134 2 0x400e86ac 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_usb_otg1_pwr: IOMUXC_GPIO_AD_10_USB_OTG1_PWR { + pinmux = <0x400e8134 0 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_adc1_ch2b: IOMUXC_GPIO_AD_11_ADC1_CH2B { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_enet_1588_event3_out: IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT { + pinmux = <0x400e8138 6 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexio2_flexio11: IOMUXC_GPIO_AD_11_FLEXIO2_FLEXIO11 { + pinmux = <0x400e8138 8 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexpwm2_pwm1_x: IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X { + pinmux = <0x400e8138 11 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio9_io10: IOMUXC_GPIO_AD_11_GPIO9_IO10 { + pinmux = <0x400e8138 10 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10_cm7: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10_CM7 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpt3_clk: IOMUXC_GPIO_AD_11_GPT3_CLK { + pinmux = <0x400e8138 3 0x400e8598 1 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_lpi2c1_sdas: IOMUXC_GPIO_AD_11_LPI2C1_SDAS { + pinmux = <0x400e8138 1 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_sim2_power_fail: IOMUXC_GPIO_AD_11_SIM2_POWER_FAIL { + pinmux = <0x400e8138 2 0x400e86b0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_usb_otg1_oc: IOMUXC_GPIO_AD_11_USB_OTG1_OC { + pinmux = <0x400e8138 0 0x400e86bc 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc1_ch3a: IOMUXC_GPIO_AD_12_ADC1_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc2_ch3a: IOMUXC_GPIO_AD_12_ADC2_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_enet_tdata03: IOMUXC_GPIO_AD_12_ENET_TDATA03 { + pinmux = <0x400e813c 6 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_ewm_ewm_out_b: IOMUXC_GPIO_AD_12_EWM_EWM_OUT_B { + pinmux = <0x400e813c 9 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexio2_flexio12: IOMUXC_GPIO_AD_12_FLEXIO2_FLEXIO12 { + pinmux = <0x400e813c 8 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexpwm2_pwm2_x: IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X { + pinmux = <0x400e813c 11 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexspi1_b_data03: IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 { + pinmux = <0x400e813c 3 0x400e8570 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio9_io11: IOMUXC_GPIO_AD_12_GPIO9_IO11 { + pinmux = <0x400e813c 10 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11_cm7: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11_CM7 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpt1_capture1: IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 { + pinmux = <0x400e813c 2 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_lpi2c1_hreq: IOMUXC_GPIO_AD_12_LPI2C1_HREQ { + pinmux = <0x400e813c 1 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_spdif_lock: IOMUXC_GPIO_AD_12_SPDIF_LOCK { + pinmux = <0x400e813c 0 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc1_ch3b: IOMUXC_GPIO_AD_13_ADC1_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc2_ch3b: IOMUXC_GPIO_AD_13_ADC2_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_enet_tdata02: IOMUXC_GPIO_AD_13_ENET_TDATA02 { + pinmux = <0x400e8140 6 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexio2_flexio13: IOMUXC_GPIO_AD_13_FLEXIO2_FLEXIO13 { + pinmux = <0x400e8140 8 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexpwm2_pwm3_x: IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X { + pinmux = <0x400e8140 11 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexspi1_b_data02: IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 { + pinmux = <0x400e8140 3 0x400e856c 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio9_io12: IOMUXC_GPIO_AD_13_GPIO9_IO12 { + pinmux = <0x400e8140 10 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12_cm7: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12_CM7 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpt1_capture2: IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 { + pinmux = <0x400e8140 2 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_pit1_trigger00: IOMUXC_GPIO_AD_13_PIT1_TRIGGER00 { + pinmux = <0x400e8140 1 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_spdif_sr_clk: IOMUXC_GPIO_AD_13_SPDIF_SR_CLK { + pinmux = <0x400e8140 0 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc1_ch4a: IOMUXC_GPIO_AD_14_ADC1_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc2_ch4a: IOMUXC_GPIO_AD_14_ADC2_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_ccm_enet_ref_clk_25m: IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8144 9 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_enet_rx_clk: IOMUXC_GPIO_AD_14_ENET_RX_CLK { + pinmux = <0x400e8144 6 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexio2_flexio14: IOMUXC_GPIO_AD_14_FLEXIO2_FLEXIO14 { + pinmux = <0x400e8144 8 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexpwm3_pwm0_x: IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X { + pinmux = <0x400e8144 11 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexspi1_b_data01: IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 { + pinmux = <0x400e8144 3 0x400e8568 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio9_io13: IOMUXC_GPIO_AD_14_GPIO9_IO13 { + pinmux = <0x400e8144 10 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13_cm7: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13_CM7 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpt1_compare1: IOMUXC_GPIO_AD_14_GPT1_COMPARE1 { + pinmux = <0x400e8144 2 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_spdif_ext_clk: IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK { + pinmux = <0x400e8144 0 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc1_ch4b: IOMUXC_GPIO_AD_15_ADC1_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc2_ch4b: IOMUXC_GPIO_AD_15_ADC2_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_enet_tx_er: IOMUXC_GPIO_AD_15_ENET_TX_ER { + pinmux = <0x400e8148 6 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexio2_flexio15: IOMUXC_GPIO_AD_15_FLEXIO2_FLEXIO15 { + pinmux = <0x400e8148 8 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexpwm3_pwm1_x: IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X { + pinmux = <0x400e8148 11 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexspi1_b_data00: IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 { + pinmux = <0x400e8148 3 0x400e8564 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio9_io14: IOMUXC_GPIO_AD_15_GPIO9_IO14 { + pinmux = <0x400e8148 10 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14_cm7: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14_CM7 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpt1_compare2: IOMUXC_GPIO_AD_15_GPT1_COMPARE2 { + pinmux = <0x400e8148 2 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_lpuart10_tx: IOMUXC_GPIO_AD_15_LPUART10_TX { + pinmux = <0x400e8148 1 0x400e8628 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_spdif_in: IOMUXC_GPIO_AD_15_SPDIF_IN { + pinmux = <0x400e8148 0 0x400e86b4 1 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc1_ch5a: IOMUXC_GPIO_AD_16_ADC1_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc2_ch5a: IOMUXC_GPIO_AD_16_ADC2_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_1g_mdc: IOMUXC_GPIO_AD_16_ENET_1G_MDC { + pinmux = <0x400e814c 9 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_rdata03: IOMUXC_GPIO_AD_16_ENET_RDATA03 { + pinmux = <0x400e814c 6 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexio2_flexio16: IOMUXC_GPIO_AD_16_FLEXIO2_FLEXIO16 { + pinmux = <0x400e814c 8 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexpwm3_pwm2_x: IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X { + pinmux = <0x400e814c 11 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexspi1_b_sclk: IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK { + pinmux = <0x400e814c 3 0x400e8578 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio9_io15: IOMUXC_GPIO_AD_16_GPIO9_IO15 { + pinmux = <0x400e814c 10 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15_cm7: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15_CM7 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpt1_compare3: IOMUXC_GPIO_AD_16_GPT1_COMPARE3 { + pinmux = <0x400e814c 2 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_lpuart10_rx: IOMUXC_GPIO_AD_16_LPUART10_RX { + pinmux = <0x400e814c 1 0x400e8624 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_spdif_out: IOMUXC_GPIO_AD_16_SPDIF_OUT { + pinmux = <0x400e814c 0 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_acmp1_cmpo: IOMUXC_GPIO_AD_17_ACMP1_CMPO { + pinmux = <0x400e8150 1 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc1_ch5b: IOMUXC_GPIO_AD_17_ADC1_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc2_ch5b: IOMUXC_GPIO_AD_17_ADC2_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_1g_mdio: IOMUXC_GPIO_AD_17_ENET_1G_MDIO { + pinmux = <0x400e8150 9 0x400e84c8 2 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_rdata02: IOMUXC_GPIO_AD_17_ENET_RDATA02 { + pinmux = <0x400e8150 6 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexio2_flexio17: IOMUXC_GPIO_AD_17_FLEXIO2_FLEXIO17 { + pinmux = <0x400e8150 8 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexpwm3_pwm3_x: IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X { + pinmux = <0x400e8150 11 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexspi1_a_dqs: IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS { + pinmux = <0x400e8150 3 0x400e8550 1 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio9_io16: IOMUXC_GPIO_AD_17_GPIO9_IO16 { + pinmux = <0x400e8150 10 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16_cm7: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16_CM7 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpt1_clk: IOMUXC_GPIO_AD_17_GPT1_CLK { + pinmux = <0x400e8150 2 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_sai1_mclk: IOMUXC_GPIO_AD_17_SAI1_MCLK { + pinmux = <0x400e8150 0 0x400e866c 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_acmp2_cmpo: IOMUXC_GPIO_AD_18_ACMP2_CMPO { + pinmux = <0x400e8154 1 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_adc2_ch0a: IOMUXC_GPIO_AD_18_ADC2_CH0A { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_enet_crs: IOMUXC_GPIO_AD_18_ENET_CRS { + pinmux = <0x400e8154 6 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexio2_flexio18: IOMUXC_GPIO_AD_18_FLEXIO2_FLEXIO18 { + pinmux = <0x400e8154 8 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexpwm4_pwm0_x: IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X { + pinmux = <0x400e8154 11 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexspi1_a_ss0_b: IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B { + pinmux = <0x400e8154 3 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio9_io17: IOMUXC_GPIO_AD_18_GPIO9_IO17 { + pinmux = <0x400e8154 10 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17_cm7: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17_CM7 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpi2c2_scl: IOMUXC_GPIO_AD_18_LPI2C2_SCL { + pinmux = <0x400e8154 9 0x400e85b4 1 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpspi1_pcs1: IOMUXC_GPIO_AD_18_LPSPI1_PCS1 { + pinmux = <0x400e8154 2 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_sai1_rx_sync: IOMUXC_GPIO_AD_18_SAI1_RX_SYNC { + pinmux = <0x400e8154 0 0x400e8678 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_acmp3_cmpo: IOMUXC_GPIO_AD_19_ACMP3_CMPO { + pinmux = <0x400e8158 1 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_adc2_ch0b: IOMUXC_GPIO_AD_19_ADC2_CH0B { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_enet_col: IOMUXC_GPIO_AD_19_ENET_COL { + pinmux = <0x400e8158 6 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexio2_flexio19: IOMUXC_GPIO_AD_19_FLEXIO2_FLEXIO19 { + pinmux = <0x400e8158 8 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexpwm4_pwm1_x: IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X { + pinmux = <0x400e8158 11 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexspi1_a_sclk: IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK { + pinmux = <0x400e8158 3 0x400e8574 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio9_io18: IOMUXC_GPIO_AD_19_GPIO9_IO18 { + pinmux = <0x400e8158 10 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18_cm7: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18_CM7 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpi2c2_sda: IOMUXC_GPIO_AD_19_LPI2C2_SDA { + pinmux = <0x400e8158 9 0x400e85b8 1 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpspi1_pcs2: IOMUXC_GPIO_AD_19_LPSPI1_PCS2 { + pinmux = <0x400e8158 2 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_sai1_rx_bclk: IOMUXC_GPIO_AD_19_SAI1_RX_BCLK { + pinmux = <0x400e8158 0 0x400e8670 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_acmp4_cmpo: IOMUXC_GPIO_AD_20_ACMP4_CMPO { + pinmux = <0x400e815c 1 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_adc2_ch1a: IOMUXC_GPIO_AD_20_ADC2_CH1A { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexio2_flexio20: IOMUXC_GPIO_AD_20_FLEXIO2_FLEXIO20 { + pinmux = <0x400e815c 8 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexpwm4_pwm2_x: IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X { + pinmux = <0x400e815c 11 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexspi1_a_data00: IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 { + pinmux = <0x400e815c 3 0x400e8554 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio9_io19: IOMUXC_GPIO_AD_20_GPIO9_IO19 { + pinmux = <0x400e815c 10 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19_cm7: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19_CM7 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_kpp_row07: IOMUXC_GPIO_AD_20_KPP_ROW07 { + pinmux = <0x400e815c 6 0x400e85a8 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_lpspi1_pcs3: IOMUXC_GPIO_AD_20_LPSPI1_PCS3 { + pinmux = <0x400e815c 2 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_sai1_rx_data00: IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 { + pinmux = <0x400e815c 0 0x400e8674 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_adc2_ch1b: IOMUXC_GPIO_AD_21_ADC2_CH1B { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexio2_flexio21: IOMUXC_GPIO_AD_21_FLEXIO2_FLEXIO21 { + pinmux = <0x400e8160 8 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexpwm4_pwm3_x: IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X { + pinmux = <0x400e8160 11 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexspi1_a_data01: IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 { + pinmux = <0x400e8160 3 0x400e8558 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio9_io20: IOMUXC_GPIO_AD_21_GPIO9_IO20 { + pinmux = <0x400e8160 10 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20_cm7: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20_CM7 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_kpp_col07: IOMUXC_GPIO_AD_21_KPP_COL07 { + pinmux = <0x400e8160 6 0x400e85a0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_lpspi2_pcs1: IOMUXC_GPIO_AD_21_LPSPI2_PCS1 { + pinmux = <0x400e8160 2 0x400e85e0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_sai1_tx_data00: IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 { + pinmux = <0x400e8160 0 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_adc2_ch2a: IOMUXC_GPIO_AD_22_ADC2_CH2A { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexio2_flexio22: IOMUXC_GPIO_AD_22_FLEXIO2_FLEXIO22 { + pinmux = <0x400e8164 8 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexspi1_a_data02: IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 { + pinmux = <0x400e8164 3 0x400e855c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio9_io21: IOMUXC_GPIO_AD_22_GPIO9_IO21 { + pinmux = <0x400e8164 10 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21_cm7: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21_CM7 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_kpp_row06: IOMUXC_GPIO_AD_22_KPP_ROW06 { + pinmux = <0x400e8164 6 0x400e85a4 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_lpspi2_pcs2: IOMUXC_GPIO_AD_22_LPSPI2_PCS2 { + pinmux = <0x400e8164 2 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_sai1_tx_bclk: IOMUXC_GPIO_AD_22_SAI1_TX_BCLK { + pinmux = <0x400e8164 0 0x400e867c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_adc2_ch2b: IOMUXC_GPIO_AD_23_ADC2_CH2B { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexio2_flexio23: IOMUXC_GPIO_AD_23_FLEXIO2_FLEXIO23 { + pinmux = <0x400e8168 8 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexspi1_a_data03: IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 { + pinmux = <0x400e8168 3 0x400e8560 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio9_io22: IOMUXC_GPIO_AD_23_GPIO9_IO22 { + pinmux = <0x400e8168 10 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22_cm7: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22_CM7 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_kpp_col06: IOMUXC_GPIO_AD_23_KPP_COL06 { + pinmux = <0x400e8168 6 0x400e859c 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_lpspi2_pcs3: IOMUXC_GPIO_AD_23_LPSPI2_PCS3 { + pinmux = <0x400e8168 2 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_sai1_tx_sync: IOMUXC_GPIO_AD_23_SAI1_TX_SYNC { + pinmux = <0x400e8168 0 0x400e8680 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_adc2_ch6a: IOMUXC_GPIO_AD_24_ADC2_CH6A { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_enet_rx_en: IOMUXC_GPIO_AD_24_ENET_RX_EN { + pinmux = <0x400e816c 3 0x400e84b8 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexio2_flexio24: IOMUXC_GPIO_AD_24_FLEXIO2_FLEXIO24 { + pinmux = <0x400e816c 8 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexpwm2_pwm0_a: IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A { + pinmux = <0x400e816c 4 0x400e8518 1 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio9_io23: IOMUXC_GPIO_AD_24_GPIO9_IO23 { + pinmux = <0x400e816c 10 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23_cm7: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23_CM7 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_kpp_row05: IOMUXC_GPIO_AD_24_KPP_ROW05 { + pinmux = <0x400e816c 6 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpi2c4_scl: IOMUXC_GPIO_AD_24_LPI2C4_SCL { + pinmux = <0x400e816c 9 0x400e85c4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpspi2_sck: IOMUXC_GPIO_AD_24_LPSPI2_SCK { + pinmux = <0x400e816c 1 0x400e85e4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpuart1_tx: IOMUXC_GPIO_AD_24_LPUART1_TX { + pinmux = <0x400e816c 0 0x400e8620 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_adc2_ch6b: IOMUXC_GPIO_AD_25_ADC2_CH6B { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_enet_rx_er: IOMUXC_GPIO_AD_25_ENET_RX_ER { + pinmux = <0x400e8170 3 0x400e84bc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexio2_flexio25: IOMUXC_GPIO_AD_25_FLEXIO2_FLEXIO25 { + pinmux = <0x400e8170 8 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexpwm2_pwm0_b: IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B { + pinmux = <0x400e8170 4 0x400e8524 1 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio9_io24: IOMUXC_GPIO_AD_25_GPIO9_IO24 { + pinmux = <0x400e8170 10 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24_cm7: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24_CM7 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_kpp_col05: IOMUXC_GPIO_AD_25_KPP_COL05 { + pinmux = <0x400e8170 6 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpi2c4_sda: IOMUXC_GPIO_AD_25_LPI2C4_SDA { + pinmux = <0x400e8170 9 0x400e85c8 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpspi2_pcs0: IOMUXC_GPIO_AD_25_LPSPI2_PCS0 { + pinmux = <0x400e8170 1 0x400e85dc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpuart1_rx: IOMUXC_GPIO_AD_25_LPUART1_RX { + pinmux = <0x400e8170 0 0x400e861c 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_acmp2_in3: IOMUXC_GPIO_AD_26_ACMP2_IN3 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_enet_rdata00: IOMUXC_GPIO_AD_26_ENET_RDATA00 { + pinmux = <0x400e8174 3 0x400e84b0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexio2_flexio26: IOMUXC_GPIO_AD_26_FLEXIO2_FLEXIO26 { + pinmux = <0x400e8174 8 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexpwm2_pwm1_a: IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A { + pinmux = <0x400e8174 4 0x400e851c 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio9_io25: IOMUXC_GPIO_AD_26_GPIO9_IO25 { + pinmux = <0x400e8174 10 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25_cm7: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25_CM7 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_kpp_row04: IOMUXC_GPIO_AD_26_KPP_ROW04 { + pinmux = <0x400e8174 6 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpspi2_sdo: IOMUXC_GPIO_AD_26_LPSPI2_SDO { + pinmux = <0x400e8174 1 0x400e85ec 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpuart1_cts_b: IOMUXC_GPIO_AD_26_LPUART1_CTS_B { + pinmux = <0x400e8174 0 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_semc_csx01: IOMUXC_GPIO_AD_26_SEMC_CSX01 { + pinmux = <0x400e8174 2 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_usdhc2_cd_b: IOMUXC_GPIO_AD_26_USDHC2_CD_B { + pinmux = <0x400e8174 11 0x400e86d0 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_acmp2_in4: IOMUXC_GPIO_AD_27_ACMP2_IN4 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_enet_rdata01: IOMUXC_GPIO_AD_27_ENET_RDATA01 { + pinmux = <0x400e8178 3 0x400e84b4 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexio2_flexio27: IOMUXC_GPIO_AD_27_FLEXIO2_FLEXIO27 { + pinmux = <0x400e8178 8 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexpwm2_pwm1_b: IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B { + pinmux = <0x400e8178 4 0x400e8528 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio9_io26: IOMUXC_GPIO_AD_27_GPIO9_IO26 { + pinmux = <0x400e8178 10 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26_cm7: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26_CM7 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_kpp_col04: IOMUXC_GPIO_AD_27_KPP_COL04 { + pinmux = <0x400e8178 6 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpspi2_sdi: IOMUXC_GPIO_AD_27_LPSPI2_SDI { + pinmux = <0x400e8178 1 0x400e85e8 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpuart1_rts_b: IOMUXC_GPIO_AD_27_LPUART1_RTS_B { + pinmux = <0x400e8178 0 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_semc_csx02: IOMUXC_GPIO_AD_27_SEMC_CSX02 { + pinmux = <0x400e8178 2 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_usdhc2_wp: IOMUXC_GPIO_AD_27_USDHC2_WP { + pinmux = <0x400e8178 11 0x400e86d4 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_acmp3_in1: IOMUXC_GPIO_AD_28_ACMP3_IN1 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_enet_tx_en: IOMUXC_GPIO_AD_28_ENET_TX_EN { + pinmux = <0x400e817c 3 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexio2_flexio28: IOMUXC_GPIO_AD_28_FLEXIO2_FLEXIO28 { + pinmux = <0x400e817c 8 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexpwm2_pwm2_a: IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A { + pinmux = <0x400e817c 4 0x400e8520 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio9_io27: IOMUXC_GPIO_AD_28_GPIO9_IO27 { + pinmux = <0x400e817c 10 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27_cm7: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27_CM7 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_kpp_row03: IOMUXC_GPIO_AD_28_KPP_ROW03 { + pinmux = <0x400e817c 6 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpspi1_sck: IOMUXC_GPIO_AD_28_LPSPI1_SCK { + pinmux = <0x400e817c 0 0x400e85d0 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpuart5_tx: IOMUXC_GPIO_AD_28_LPUART5_TX { + pinmux = <0x400e817c 1 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_semc_csx03: IOMUXC_GPIO_AD_28_SEMC_CSX03 { + pinmux = <0x400e817c 2 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_usdhc2_vselect: IOMUXC_GPIO_AD_28_USDHC2_VSELECT { + pinmux = <0x400e817c 11 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_video_mux_ext_dcic1: IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e817c 9 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_acmp3_in2: IOMUXC_GPIO_AD_29_ACMP3_IN2 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_ref_clk: IOMUXC_GPIO_AD_29_ENET_REF_CLK { + pinmux = <0x400e8180 2 0x400e84a8 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_tx_clk: IOMUXC_GPIO_AD_29_ENET_TX_CLK { + pinmux = <0x400e8180 3 0x400e84c0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexio2_flexio29: IOMUXC_GPIO_AD_29_FLEXIO2_FLEXIO29 { + pinmux = <0x400e8180 8 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexpwm2_pwm2_b: IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B { + pinmux = <0x400e8180 4 0x400e852c 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio9_io28: IOMUXC_GPIO_AD_29_GPIO9_IO28 { + pinmux = <0x400e8180 10 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28_cm7: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28_CM7 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_kpp_col03: IOMUXC_GPIO_AD_29_KPP_COL03 { + pinmux = <0x400e8180 6 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpspi1_pcs0: IOMUXC_GPIO_AD_29_LPSPI1_PCS0 { + pinmux = <0x400e8180 0 0x400e85cc 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpuart5_rx: IOMUXC_GPIO_AD_29_LPUART5_RX { + pinmux = <0x400e8180 1 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_usdhc2_reset_b: IOMUXC_GPIO_AD_29_USDHC2_RESET_B { + pinmux = <0x400e8180 11 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_video_mux_ext_dcic2: IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8180 9 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_acmp3_in3: IOMUXC_GPIO_AD_30_ACMP3_IN3 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_can2_tx: IOMUXC_GPIO_AD_30_CAN2_TX { + pinmux = <0x400e8184 2 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_enet_tdata00: IOMUXC_GPIO_AD_30_ENET_TDATA00 { + pinmux = <0x400e8184 3 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_flexio2_flexio30: IOMUXC_GPIO_AD_30_FLEXIO2_FLEXIO30 { + pinmux = <0x400e8184 8 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio9_io29: IOMUXC_GPIO_AD_30_GPIO9_IO29 { + pinmux = <0x400e8184 10 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29_cm7: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29_CM7 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_kpp_row02: IOMUXC_GPIO_AD_30_KPP_ROW02 { + pinmux = <0x400e8184 6 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpspi1_sdo: IOMUXC_GPIO_AD_30_LPSPI1_SDO { + pinmux = <0x400e8184 0 0x400e85d8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpuart3_tx: IOMUXC_GPIO_AD_30_LPUART3_TX { + pinmux = <0x400e8184 4 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_usb_otg2_oc: IOMUXC_GPIO_AD_30_USB_OTG2_OC { + pinmux = <0x400e8184 1 0x400e86b8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_AD_30_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e8184 9 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_acmp3_in4: IOMUXC_GPIO_AD_31_ACMP3_IN4 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_can2_rx: IOMUXC_GPIO_AD_31_CAN2_RX { + pinmux = <0x400e8188 2 0x400e849c 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_enet_tdata01: IOMUXC_GPIO_AD_31_ENET_TDATA01 { + pinmux = <0x400e8188 3 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_flexio2_flexio31: IOMUXC_GPIO_AD_31_FLEXIO2_FLEXIO31 { + pinmux = <0x400e8188 8 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio9_io30: IOMUXC_GPIO_AD_31_GPIO9_IO30 { + pinmux = <0x400e8188 10 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30_cm7: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30_CM7 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_kpp_col02: IOMUXC_GPIO_AD_31_KPP_COL02 { + pinmux = <0x400e8188 6 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpspi1_sdi: IOMUXC_GPIO_AD_31_LPSPI1_SDI { + pinmux = <0x400e8188 0 0x400e85d4 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpuart3_rx: IOMUXC_GPIO_AD_31_LPUART3_RX { + pinmux = <0x400e8188 4 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_usb_otg2_pwr: IOMUXC_GPIO_AD_31_USB_OTG2_PWR { + pinmux = <0x400e8188 1 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_AD_31_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8188 9 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_acmp4_in1: IOMUXC_GPIO_AD_32_ACMP4_IN1 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_1g_mdc: IOMUXC_GPIO_AD_32_ENET_1G_MDC { + pinmux = <0x400e818c 9 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_mdc: IOMUXC_GPIO_AD_32_ENET_MDC { + pinmux = <0x400e818c 3 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio9_io31: IOMUXC_GPIO_AD_32_GPIO9_IO31 { + pinmux = <0x400e818c 10 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31_cm7: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31_CM7 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_kpp_row01: IOMUXC_GPIO_AD_32_KPP_ROW01 { + pinmux = <0x400e818c 6 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpi2c1_scl: IOMUXC_GPIO_AD_32_LPI2C1_SCL { + pinmux = <0x400e818c 0 0x400e85ac 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpuart10_tx: IOMUXC_GPIO_AD_32_LPUART10_TX { + pinmux = <0x400e818c 8 0x400e8628 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_pgmc_pmic_ready: IOMUXC_GPIO_AD_32_PGMC_PMIC_READY { + pinmux = <0x400e818c 2 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usbphy2_otg_id: IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID { + pinmux = <0x400e818c 1 0x400e86c4 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usdhc1_cd_b: IOMUXC_GPIO_AD_32_USDHC1_CD_B { + pinmux = <0x400e818c 4 0x400e86c8 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_acmp4_in2: IOMUXC_GPIO_AD_33_ACMP4_IN2 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_1g_mdio: IOMUXC_GPIO_AD_33_ENET_1G_MDIO { + pinmux = <0x400e8190 9 0x400e84c8 3 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_mdio: IOMUXC_GPIO_AD_33_ENET_MDIO { + pinmux = <0x400e8190 3 0x400e84ac 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio10_io00: IOMUXC_GPIO_AD_33_GPIO10_IO00 { + pinmux = <0x400e8190 10 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio_mux4_io00: IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_kpp_col01: IOMUXC_GPIO_AD_33_KPP_COL01 { + pinmux = <0x400e8190 6 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpi2c1_sda: IOMUXC_GPIO_AD_33_LPI2C1_SDA { + pinmux = <0x400e8190 0 0x400e85b0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpuart10_rx: IOMUXC_GPIO_AD_33_LPUART10_RX { + pinmux = <0x400e8190 8 0x400e8624 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usbphy1_otg_id: IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID { + pinmux = <0x400e8190 1 0x400e86c0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usdhc1_wp: IOMUXC_GPIO_AD_33_USDHC1_WP { + pinmux = <0x400e8190 4 0x400e86cc 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_in17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_IN17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_inout17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_acmp4_in3: IOMUXC_GPIO_AD_34_ACMP4_IN3 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN { + pinmux = <0x400e8194 3 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1g_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN { + pinmux = <0x400e8194 0 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio10_io01: IOMUXC_GPIO_AD_34_GPIO10_IO01 { + pinmux = <0x400e8194 10 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio_mux4_io01: IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_kpp_row00: IOMUXC_GPIO_AD_34_KPP_ROW00 { + pinmux = <0x400e8194 6 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_lpuart10_cts_b: IOMUXC_GPIO_AD_34_LPUART10_CTS_B { + pinmux = <0x400e8194 8 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usb_otg1_pwr: IOMUXC_GPIO_AD_34_USB_OTG1_PWR { + pinmux = <0x400e8194 1 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usdhc1_vselect: IOMUXC_GPIO_AD_34_USDHC1_VSELECT { + pinmux = <0x400e8194 4 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_wdog1_wdog_any: IOMUXC_GPIO_AD_34_WDOG1_WDOG_ANY { + pinmux = <0x400e8194 9 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_in18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_IN18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_inout18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_acmp4_in4: IOMUXC_GPIO_AD_35_ACMP4_IN4 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT { + pinmux = <0x400e8198 3 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1g_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT { + pinmux = <0x400e8198 0 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_flexspi1_b_ss1_b: IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B { + pinmux = <0x400e8198 9 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio10_io02: IOMUXC_GPIO_AD_35_GPIO10_IO02 { + pinmux = <0x400e8198 10 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio_mux4_io02: IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_kpp_col00: IOMUXC_GPIO_AD_35_KPP_COL00 { + pinmux = <0x400e8198 6 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_lpuart10_rts_b: IOMUXC_GPIO_AD_35_LPUART10_RTS_B { + pinmux = <0x400e8198 8 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usb_otg1_oc: IOMUXC_GPIO_AD_35_USB_OTG1_OC { + pinmux = <0x400e8198 1 0x400e86bc 1 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usdhc1_reset_b: IOMUXC_GPIO_AD_35_USDHC1_RESET_B { + pinmux = <0x400e8198 4 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_in19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_IN19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_inout19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_INOUT19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_enet_1g_rx_en: IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN { + pinmux = <0x400e81e4 1 0x400e84e0 2 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio10_io21: IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 { + pinmux = <0x400e81e4 10 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio_mux4_io21: IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 { + pinmux = <0x400e81e4 5 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_qtimer1_timer0: IOMUXC_GPIO_DISP_B1_00_QTIMER1_TIMER0 { + pinmux = <0x400e81e4 3 0x400e863c 2 0x400e8428>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_in26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_IN26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_inout26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_clk: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK { + pinmux = <0x400e81e8 1 0x400e84cc 2 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_er: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER { + pinmux = <0x400e81e8 2 0x400e84e4 1 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio10_io22: IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 { + pinmux = <0x400e81e8 10 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio_mux4_io22: IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 { + pinmux = <0x400e81e8 5 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_qtimer1_timer1: IOMUXC_GPIO_DISP_B1_01_QTIMER1_TIMER1 { + pinmux = <0x400e81e8 3 0x400e8640 2 0x400e842c>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_in27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_IN27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_inout27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_enet_1g_rdata00: IOMUXC_GPIO_DISP_B1_02_ENET_1G_RDATA00 { + pinmux = <0x400e81ec 1 0x400e84d0 2 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio10_io23: IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 { + pinmux = <0x400e81ec 10 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio_mux4_io23: IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 { + pinmux = <0x400e81ec 5 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpi2c3_scl: IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL { + pinmux = <0x400e81ec 2 0x400e85bc 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpuart1_tx: IOMUXC_GPIO_DISP_B1_02_LPUART1_TX { + pinmux = <0x400e81ec 9 0x400e8620 1 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_qtimer1_timer2: IOMUXC_GPIO_DISP_B1_02_QTIMER1_TIMER2 { + pinmux = <0x400e81ec 3 0x400e8644 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_in28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_IN28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_inout28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_enet_1g_rdata01: IOMUXC_GPIO_DISP_B1_03_ENET_1G_RDATA01 { + pinmux = <0x400e81f0 1 0x400e84d4 2 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio10_io24: IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 { + pinmux = <0x400e81f0 10 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio_mux4_io24: IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 { + pinmux = <0x400e81f0 5 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpi2c3_sda: IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA { + pinmux = <0x400e81f0 2 0x400e85c0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpuart1_rx: IOMUXC_GPIO_DISP_B1_03_LPUART1_RX { + pinmux = <0x400e81f0 9 0x400e861c 1 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_qtimer2_timer0: IOMUXC_GPIO_DISP_B1_03_QTIMER2_TIMER0 { + pinmux = <0x400e81f0 3 0x400e8648 2 0x400e8434>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_in29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_IN29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_inout29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_enet_1g_rdata02: IOMUXC_GPIO_DISP_B1_04_ENET_1G_RDATA02 { + pinmux = <0x400e81f4 1 0x400e84d8 2 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio10_io25: IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 { + pinmux = <0x400e81f4 10 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio_mux4_io25: IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 { + pinmux = <0x400e81f4 5 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpspi3_sck: IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK { + pinmux = <0x400e81f4 9 0x400e8600 1 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpuart4_rx: IOMUXC_GPIO_DISP_B1_04_LPUART4_RX { + pinmux = <0x400e81f4 2 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_qtimer2_timer1: IOMUXC_GPIO_DISP_B1_04_QTIMER2_TIMER1 { + pinmux = <0x400e81f4 3 0x400e864c 2 0x400e8438>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_in30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_IN30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_inout30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_enet_1g_rdata03: IOMUXC_GPIO_DISP_B1_05_ENET_1G_RDATA03 { + pinmux = <0x400e81f8 1 0x400e84dc 2 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio10_io26: IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 { + pinmux = <0x400e81f8 10 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio_mux4_io26: IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 { + pinmux = <0x400e81f8 5 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpspi3_sdi: IOMUXC_GPIO_DISP_B1_05_LPSPI3_SDI { + pinmux = <0x400e81f8 9 0x400e8604 1 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpuart4_cts_b: IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B { + pinmux = <0x400e81f8 2 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_qtimer2_timer2: IOMUXC_GPIO_DISP_B1_05_QTIMER2_TIMER2 { + pinmux = <0x400e81f8 3 0x400e8650 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_in31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_IN31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_inout31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_enet_1g_tdata03: IOMUXC_GPIO_DISP_B1_06_ENET_1G_TDATA03 { + pinmux = <0x400e81fc 1 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio10_io27: IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 { + pinmux = <0x400e81fc 10 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio_mux4_io27: IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 { + pinmux = <0x400e81fc 5 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpspi3_sdo: IOMUXC_GPIO_DISP_B1_06_LPSPI3_SDO { + pinmux = <0x400e81fc 9 0x400e8608 1 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpuart4_tx: IOMUXC_GPIO_DISP_B1_06_LPUART4_TX { + pinmux = <0x400e81fc 2 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_qtimer3_timer0: IOMUXC_GPIO_DISP_B1_06_QTIMER3_TIMER0 { + pinmux = <0x400e81fc 3 0x400e8654 2 0x400e8440>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_src_bt_cfg00: IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 { + pinmux = <0x400e81fc 6 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_in32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_IN32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_inout32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_enet_1g_tdata02: IOMUXC_GPIO_DISP_B1_07_ENET_1G_TDATA02 { + pinmux = <0x400e8200 1 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio10_io28: IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 { + pinmux = <0x400e8200 10 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio_mux4_io28: IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 { + pinmux = <0x400e8200 5 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpspi3_pcs0: IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 { + pinmux = <0x400e8200 9 0x400e85f0 1 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpuart4_rts_b: IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B { + pinmux = <0x400e8200 2 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_qtimer3_timer1: IOMUXC_GPIO_DISP_B1_07_QTIMER3_TIMER1 { + pinmux = <0x400e8200 3 0x400e8658 2 0x400e8444>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_src_bt_cfg01: IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 { + pinmux = <0x400e8200 6 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_in33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_IN33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_inout33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_enet_1g_tdata01: IOMUXC_GPIO_DISP_B1_08_ENET_1G_TDATA01 { + pinmux = <0x400e8204 1 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio10_io29: IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 { + pinmux = <0x400e8204 10 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio_mux4_io29: IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 { + pinmux = <0x400e8204 5 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_lpspi3_pcs1: IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 { + pinmux = <0x400e8204 9 0x400e85f4 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_qtimer3_timer2: IOMUXC_GPIO_DISP_B1_08_QTIMER3_TIMER2 { + pinmux = <0x400e8204 3 0x400e865c 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_src_bt_cfg02: IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 { + pinmux = <0x400e8204 6 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_usdhc1_cd_b: IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B { + pinmux = <0x400e8204 2 0x400e86c8 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_in34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_IN34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_inout34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_enet_1g_tdata00: IOMUXC_GPIO_DISP_B1_09_ENET_1G_TDATA00 { + pinmux = <0x400e8208 1 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio10_io30: IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 { + pinmux = <0x400e8208 10 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio_mux4_io30: IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 { + pinmux = <0x400e8208 5 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_lpspi3_pcs2: IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 { + pinmux = <0x400e8208 9 0x400e85f8 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_qtimer4_timer0: IOMUXC_GPIO_DISP_B1_09_QTIMER4_TIMER0 { + pinmux = <0x400e8208 3 0x400e8660 2 0x400e844c>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_src_bt_cfg03: IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 { + pinmux = <0x400e8208 6 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_usdhc1_wp: IOMUXC_GPIO_DISP_B1_09_USDHC1_WP { + pinmux = <0x400e8208 2 0x400e86cc 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_in35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_IN35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_inout35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_enet_1g_tx_en: IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN { + pinmux = <0x400e820c 1 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio10_io31: IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 { + pinmux = <0x400e820c 10 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio_mux4_io31: IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 { + pinmux = <0x400e820c 5 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_lpspi3_pcs3: IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 { + pinmux = <0x400e820c 9 0x400e85fc 1 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_qtimer4_timer1: IOMUXC_GPIO_DISP_B1_10_QTIMER4_TIMER1 { + pinmux = <0x400e820c 3 0x400e8664 2 0x400e8450>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_src_bt_cfg04: IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 { + pinmux = <0x400e820c 6 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_usdhc1_reset_b: IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B { + pinmux = <0x400e820c 2 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_in36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_IN36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_inout36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_INOUT36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e8210 2 0x400e84c4 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_tx_clk_io: IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e8210 1 0x400e84e8 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio11_io00: IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 { + pinmux = <0x400e8210 10 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio_mux5_io00: IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 { + pinmux = <0x400e8210 5 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_qtimer4_timer2: IOMUXC_GPIO_DISP_B1_11_QTIMER4_TIMER2 { + pinmux = <0x400e8210 3 0x400e8668 1 0x400e8454>; + pin-pdrv; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_src_bt_cfg05: IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 { + pinmux = <0x400e8210 6 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_in37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_IN37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_inout37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_INOUT37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_enet_1g_tx_er: IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER { + pinmux = <0x400e8214 3 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio11_io01: IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 { + pinmux = <0x400e8214 10 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio_mux5_io01: IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 { + pinmux = <0x400e8214 5 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_mqs_right: IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT { + pinmux = <0x400e8214 2 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_rx_data01: IOMUXC_GPIO_DISP_B2_00_SAI1_RX_DATA01 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_tx_data03: IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_src_bt_cfg06: IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 { + pinmux = <0x400e8214 6 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_00_WDOG1_WDOG_B { + pinmux = <0x400e8214 1 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ccm_enet_ref_clk_25m: IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8218 9 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ewm_ewm_out_b: IOMUXC_GPIO_DISP_B2_01_EWM_EWM_OUT_B { + pinmux = <0x400e8218 8 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio11_io02: IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 { + pinmux = <0x400e8218 10 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio_mux5_io02: IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 { + pinmux = <0x400e8218 5 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_mqs_left: IOMUXC_GPIO_DISP_B2_01_MQS_LEFT { + pinmux = <0x400e8218 2 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_rx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_RX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_tx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_src_bt_cfg07: IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 { + pinmux = <0x400e8218 6 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_usdhc1_vselect: IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT { + pinmux = <0x400e8218 1 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_01_WDOG2_WDOG_B { + pinmux = <0x400e8218 3 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_arm_trace00: IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 { + pinmux = <0x400e821c 3 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_enet_tdata00: IOMUXC_GPIO_DISP_B2_02_ENET_TDATA00 { + pinmux = <0x400e821c 1 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio11_io03: IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 { + pinmux = <0x400e821c 10 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio_mux5_io03: IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 { + pinmux = <0x400e821c 5 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_pit1_trigger03: IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER03 { + pinmux = <0x400e821c 2 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_rx_data03: IOMUXC_GPIO_DISP_B2_02_SAI1_RX_DATA03 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_tx_data01: IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_src_bt_cfg08: IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 { + pinmux = <0x400e821c 6 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_arm_trace01: IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 { + pinmux = <0x400e8220 3 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_enet_tdata01: IOMUXC_GPIO_DISP_B2_03_ENET_TDATA01 { + pinmux = <0x400e8220 1 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio11_io04: IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 { + pinmux = <0x400e8220 10 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio_mux5_io04: IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 { + pinmux = <0x400e8220 5 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_pit1_trigger02: IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER02 { + pinmux = <0x400e8220 2 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_sai1_mclk: IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK { + pinmux = <0x400e8220 4 0x400e866c 1 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_src_bt_cfg09: IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 { + pinmux = <0x400e8220 6 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_arm_trace02: IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 { + pinmux = <0x400e8224 3 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_enet_tx_en: IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN { + pinmux = <0x400e8224 1 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio11_io05: IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 { + pinmux = <0x400e8224 10 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio_mux5_io05: IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 { + pinmux = <0x400e8224 5 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_pit1_trigger01: IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER01 { + pinmux = <0x400e8224 2 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_sai1_rx_sync: IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC { + pinmux = <0x400e8224 4 0x400e8678 1 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_src_bt_cfg10: IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 { + pinmux = <0x400e8224 6 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_arm_trace03: IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 { + pinmux = <0x400e8228 3 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_ref_clk: IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK { + pinmux = <0x400e8228 2 0x400e84a8 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_tx_clk: IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK { + pinmux = <0x400e8228 1 0x400e84c0 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio11_io06: IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 { + pinmux = <0x400e8228 10 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio_mux5_io06: IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 { + pinmux = <0x400e8228 5 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_sai1_rx_bclk: IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK { + pinmux = <0x400e8228 4 0x400e8670 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_src_bt_cfg11: IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 { + pinmux = <0x400e8228 6 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_arm_trace_clk: IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK { + pinmux = <0x400e822c 3 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_enet_rdata00: IOMUXC_GPIO_DISP_B2_06_ENET_RDATA00 { + pinmux = <0x400e822c 1 0x400e84b0 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio11_io07: IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 { + pinmux = <0x400e822c 10 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio_mux5_io07: IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 { + pinmux = <0x400e822c 5 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_lpuart7_tx: IOMUXC_GPIO_DISP_B2_06_LPUART7_TX { + pinmux = <0x400e822c 2 0x400e8630 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_sai1_rx_data00: IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 { + pinmux = <0x400e822c 4 0x400e8674 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_arm_trace_swo: IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO { + pinmux = <0x400e8230 3 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_enet_rdata01: IOMUXC_GPIO_DISP_B2_07_ENET_RDATA01 { + pinmux = <0x400e8230 1 0x400e84b4 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio11_io08: IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 { + pinmux = <0x400e8230 10 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio_mux5_io08: IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 { + pinmux = <0x400e8230 5 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_lpuart7_rx: IOMUXC_GPIO_DISP_B2_07_LPUART7_RX { + pinmux = <0x400e8230 2 0x400e862c 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_sai1_tx_data00: IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 { + pinmux = <0x400e8230 4 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_cm7_imxrt_txev: IOMUXC_GPIO_DISP_B2_08_CM7_IMXRT_TXEV { + pinmux = <0x400e8234 3 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_enet_rx_en: IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN { + pinmux = <0x400e8234 1 0x400e84b8 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio11_io09: IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 { + pinmux = <0x400e8234 10 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio_mux5_io09: IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 { + pinmux = <0x400e8234 5 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart1_tx: IOMUXC_GPIO_DISP_B2_08_LPUART1_TX { + pinmux = <0x400e8234 9 0x400e8620 2 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart8_tx: IOMUXC_GPIO_DISP_B2_08_LPUART8_TX { + pinmux = <0x400e8234 2 0x400e8638 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_sai1_tx_bclk: IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK { + pinmux = <0x400e8234 4 0x400e867c 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_cm7_imxrt_rxev: IOMUXC_GPIO_DISP_B2_09_CM7_IMXRT_RXEV { + pinmux = <0x400e8238 3 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_enet_rx_er: IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER { + pinmux = <0x400e8238 1 0x400e84bc 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio11_io10: IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 { + pinmux = <0x400e8238 10 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio_mux5_io10: IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 { + pinmux = <0x400e8238 5 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart1_rx: IOMUXC_GPIO_DISP_B2_09_LPUART1_RX { + pinmux = <0x400e8238 9 0x400e861c 2 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart8_rx: IOMUXC_GPIO_DISP_B2_09_LPUART8_RX { + pinmux = <0x400e8238 2 0x400e8634 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_sai1_tx_sync: IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC { + pinmux = <0x400e8238 4 0x400e8680 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio11_io11: IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 { + pinmux = <0x400e823c 10 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio_mux5_io11: IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 { + pinmux = <0x400e823c 5 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpi2c3_scl: IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL { + pinmux = <0x400e823c 6 0x400e85bc 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpuart2_tx: IOMUXC_GPIO_DISP_B2_10_LPUART2_TX { + pinmux = <0x400e823c 2 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_sim2_trxd: IOMUXC_GPIO_DISP_B2_10_SIM2_TRXD { + pinmux = <0x400e823c 1 0x400e86a8 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_spdif_in: IOMUXC_GPIO_DISP_B2_10_SPDIF_IN { + pinmux = <0x400e823c 9 0x400e86b4 2 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_10_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e823c 3 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_in38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_IN38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_inout38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_INOUT38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio11_io12: IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 { + pinmux = <0x400e8240 10 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio_mux5_io12: IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 { + pinmux = <0x400e8240 5 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpi2c3_sda: IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA { + pinmux = <0x400e8240 6 0x400e85c0 1 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpuart2_rx: IOMUXC_GPIO_DISP_B2_11_LPUART2_RX { + pinmux = <0x400e8240 2 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_sim2_clk: IOMUXC_GPIO_DISP_B2_11_SIM2_CLK { + pinmux = <0x400e8240 1 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_spdif_out: IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT { + pinmux = <0x400e8240 9 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_11_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8240 3 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_in39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_IN39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_inout39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_INOUT39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_can1_tx: IOMUXC_GPIO_DISP_B2_12_CAN1_TX { + pinmux = <0x400e8244 2 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio11_io13: IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 { + pinmux = <0x400e8244 10 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio_mux5_io13: IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 { + pinmux = <0x400e8244 5 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpi2c4_scl: IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL { + pinmux = <0x400e8244 6 0x400e85c4 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpspi4_sck: IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK { + pinmux = <0x400e8244 9 0x400e8610 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpuart2_cts_b: IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B { + pinmux = <0x400e8244 3 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_sim2_rst_b: IOMUXC_GPIO_DISP_B2_12_SIM2_RST_B { + pinmux = <0x400e8244 1 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_in40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_IN40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_inout40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_INOUT40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_can1_rx: IOMUXC_GPIO_DISP_B2_13_CAN1_RX { + pinmux = <0x400e8248 2 0x400e8498 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_enet_ref_clk: IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK { + pinmux = <0x400e8248 4 0x400e84a8 2 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio11_io14: IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 { + pinmux = <0x400e8248 10 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio_mux5_io14: IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 { + pinmux = <0x400e8248 5 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpi2c4_sda: IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA { + pinmux = <0x400e8248 6 0x400e85c8 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpspi4_sdi: IOMUXC_GPIO_DISP_B2_13_LPSPI4_SDI { + pinmux = <0x400e8248 9 0x400e8614 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpuart2_rts_b: IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B { + pinmux = <0x400e8248 3 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_sim2_sven: IOMUXC_GPIO_DISP_B2_13_SIM2_SVEN { + pinmux = <0x400e8248 1 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_can1_tx: IOMUXC_GPIO_DISP_B2_14_CAN1_TX { + pinmux = <0x400e824c 6 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK1 { + pinmux = <0x400e824c 4 0x400e84c4 3 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio11_io15: IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 { + pinmux = <0x400e824c 10 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio_mux5_io15: IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 { + pinmux = <0x400e824c 5 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_lpspi4_sdo: IOMUXC_GPIO_DISP_B2_14_LPSPI4_SDO { + pinmux = <0x400e824c 9 0x400e8618 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_sim2_pd: IOMUXC_GPIO_DISP_B2_14_SIM2_PD { + pinmux = <0x400e824c 1 0x400e86ac 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_ext_dcic1: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e824c 3 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_14_WDOG2_WDOG_B { + pinmux = <0x400e824c 2 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_can1_rx: IOMUXC_GPIO_DISP_B2_15_CAN1_RX { + pinmux = <0x400e8250 6 0x400e8498 2 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio11_io16: IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 { + pinmux = <0x400e8250 10 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio_mux5_io16: IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 { + pinmux = <0x400e8250 5 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_lpspi4_pcs0: IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 { + pinmux = <0x400e8250 9 0x400e860c 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_pit1_trigger00: IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER00 { + pinmux = <0x400e8250 4 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_sim2_power_fail: IOMUXC_GPIO_DISP_B2_15_SIM2_POWER_FAIL { + pinmux = <0x400e8250 1 0x400e86b0 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_ext_dcic2: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8250 3 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_15_WDOG1_WDOG_B { + pinmux = <0x400e8250 2 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexio1_flexio00: IOMUXC_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00 { + pinmux = <0x400e8010 8 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexpwm4_pwm0_a: IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A { + pinmux = <0x400e8010 1 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio7_io00: IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 { + pinmux = <0x400e8010 10 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio_mux1_io00: IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 { + pinmux = <0x400e8010 5 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_semc_data00: IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 { + pinmux = <0x400e8010 0 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexio1_flexio01: IOMUXC_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01 { + pinmux = <0x400e8014 8 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexpwm4_pwm0_b: IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B { + pinmux = <0x400e8014 1 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio7_io01: IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 { + pinmux = <0x400e8014 10 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio_mux1_io01: IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 { + pinmux = <0x400e8014 5 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_semc_data01: IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 { + pinmux = <0x400e8014 0 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexio1_flexio02: IOMUXC_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02 { + pinmux = <0x400e8018 8 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexpwm4_pwm1_a: IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A { + pinmux = <0x400e8018 1 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio7_io02: IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 { + pinmux = <0x400e8018 10 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio_mux1_io02: IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 { + pinmux = <0x400e8018 5 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_semc_data02: IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 { + pinmux = <0x400e8018 0 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexio1_flexio03: IOMUXC_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03 { + pinmux = <0x400e801c 8 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexpwm4_pwm1_b: IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B { + pinmux = <0x400e801c 1 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio7_io03: IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 { + pinmux = <0x400e801c 10 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio_mux1_io03: IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 { + pinmux = <0x400e801c 5 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_semc_data03: IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 { + pinmux = <0x400e801c 0 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexio1_flexio04: IOMUXC_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04 { + pinmux = <0x400e8020 8 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexpwm4_pwm2_a: IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A { + pinmux = <0x400e8020 1 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio7_io04: IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 { + pinmux = <0x400e8020 10 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio_mux1_io04: IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 { + pinmux = <0x400e8020 5 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_semc_data04: IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 { + pinmux = <0x400e8020 0 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexio1_flexio05: IOMUXC_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05 { + pinmux = <0x400e8024 8 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexpwm4_pwm2_b: IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B { + pinmux = <0x400e8024 1 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio7_io05: IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 { + pinmux = <0x400e8024 10 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio_mux1_io05: IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 { + pinmux = <0x400e8024 5 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_semc_data05: IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 { + pinmux = <0x400e8024 0 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexio1_flexio06: IOMUXC_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06 { + pinmux = <0x400e8028 8 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexpwm2_pwm0_a: IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A { + pinmux = <0x400e8028 1 0x400e8518 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio7_io06: IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 { + pinmux = <0x400e8028 10 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio_mux1_io06: IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 { + pinmux = <0x400e8028 5 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_semc_data06: IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 { + pinmux = <0x400e8028 0 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexio1_flexio07: IOMUXC_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07 { + pinmux = <0x400e802c 8 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexpwm2_pwm0_b: IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B { + pinmux = <0x400e802c 1 0x400e8524 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio7_io07: IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 { + pinmux = <0x400e802c 10 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio_mux1_io07: IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 { + pinmux = <0x400e802c 5 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_semc_data07: IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 { + pinmux = <0x400e802c 0 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexio1_flexio08: IOMUXC_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08 { + pinmux = <0x400e8030 8 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexpwm2_pwm1_a: IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A { + pinmux = <0x400e8030 1 0x400e851c 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio7_io08: IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 { + pinmux = <0x400e8030 10 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio_mux1_io08: IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 { + pinmux = <0x400e8030 5 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_semc_dm00: IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 { + pinmux = <0x400e8030 0 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexio1_flexio09: IOMUXC_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09 { + pinmux = <0x400e8034 8 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexpwm2_pwm1_b: IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B { + pinmux = <0x400e8034 1 0x400e8528 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio7_io09: IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 { + pinmux = <0x400e8034 10 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio_mux1_io09: IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 { + pinmux = <0x400e8034 5 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpt5_capture1: IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 { + pinmux = <0x400e8034 2 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_semc_addr00: IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 { + pinmux = <0x400e8034 0 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexio1_flexio10: IOMUXC_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10 { + pinmux = <0x400e8038 8 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexpwm2_pwm2_a: IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A { + pinmux = <0x400e8038 1 0x400e8520 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio7_io10: IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 { + pinmux = <0x400e8038 10 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio_mux1_io10: IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 { + pinmux = <0x400e8038 5 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpt5_capture2: IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 { + pinmux = <0x400e8038 2 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_semc_addr01: IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 { + pinmux = <0x400e8038 0 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexio1_flexio11: IOMUXC_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11 { + pinmux = <0x400e803c 8 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexpwm2_pwm2_b: IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B { + pinmux = <0x400e803c 1 0x400e852c 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio7_io11: IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 { + pinmux = <0x400e803c 10 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio_mux1_io11: IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 { + pinmux = <0x400e803c 5 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpt5_compare1: IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 { + pinmux = <0x400e803c 2 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_semc_addr02: IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 { + pinmux = <0x400e803c 0 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_flexio1_flexio12: IOMUXC_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12 { + pinmux = <0x400e8040 8 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio7_io12: IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 { + pinmux = <0x400e8040 10 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio_mux1_io12: IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 { + pinmux = <0x400e8040 5 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpt5_compare2: IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 { + pinmux = <0x400e8040 2 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_semc_addr03: IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 { + pinmux = <0x400e8040 0 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_in04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_IN04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_INOUT04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_flexio1_flexio13: IOMUXC_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13 { + pinmux = <0x400e8044 8 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio7_io13: IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 { + pinmux = <0x400e8044 10 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio_mux1_io13: IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 { + pinmux = <0x400e8044 5 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpt5_compare3: IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 { + pinmux = <0x400e8044 2 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_semc_addr04: IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 { + pinmux = <0x400e8044 0 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_in05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_IN05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_INOUT05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_flexio1_flexio14: IOMUXC_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14 { + pinmux = <0x400e8048 8 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio7_io14: IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 { + pinmux = <0x400e8048 10 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio_mux1_io14: IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 { + pinmux = <0x400e8048 5 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpt5_clk: IOMUXC_GPIO_EMC_B1_14_GPT5_CLK { + pinmux = <0x400e8048 2 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_semc_addr05: IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 { + pinmux = <0x400e8048 0 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_in06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_IN06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_INOUT06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_flexio1_flexio15: IOMUXC_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15 { + pinmux = <0x400e804c 8 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio7_io15: IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 { + pinmux = <0x400e804c 10 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio_mux1_io15: IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 { + pinmux = <0x400e804c 5 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_semc_addr06: IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 { + pinmux = <0x400e804c 0 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_in07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_IN07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_INOUT07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_flexio1_flexio16: IOMUXC_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16 { + pinmux = <0x400e8050 8 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio7_io16: IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 { + pinmux = <0x400e8050 10 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio_mux1_io16: IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 { + pinmux = <0x400e8050 5 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_semc_addr07: IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 { + pinmux = <0x400e8050 0 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_in08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_IN08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_INOUT08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexio1_flexio17: IOMUXC_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17 { + pinmux = <0x400e8054 8 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexpwm4_pwm3_a: IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A { + pinmux = <0x400e8054 1 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio7_io17: IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 { + pinmux = <0x400e8054 10 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio_mux1_io17: IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 { + pinmux = <0x400e8054 5 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_qtimer1_timer0: IOMUXC_GPIO_EMC_B1_17_QTIMER1_TIMER0 { + pinmux = <0x400e8054 2 0x400e863c 0 0x400e8298>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_semc_addr08: IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 { + pinmux = <0x400e8054 0 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexio1_flexio18: IOMUXC_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18 { + pinmux = <0x400e8058 8 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexpwm4_pwm3_b: IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B { + pinmux = <0x400e8058 1 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio7_io18: IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 { + pinmux = <0x400e8058 10 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio_mux1_io18: IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 { + pinmux = <0x400e8058 5 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_qtimer2_timer0: IOMUXC_GPIO_EMC_B1_18_QTIMER2_TIMER0 { + pinmux = <0x400e8058 2 0x400e8648 0 0x400e829c>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_semc_addr09: IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 { + pinmux = <0x400e8058 0 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexio1_flexio19: IOMUXC_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19 { + pinmux = <0x400e805c 8 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexpwm2_pwm3_a: IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A { + pinmux = <0x400e805c 1 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio7_io19: IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 { + pinmux = <0x400e805c 10 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio_mux1_io19: IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 { + pinmux = <0x400e805c 5 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_qtimer3_timer0: IOMUXC_GPIO_EMC_B1_19_QTIMER3_TIMER0 { + pinmux = <0x400e805c 2 0x400e8654 0 0x400e82a0>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_semc_addr11: IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 { + pinmux = <0x400e805c 0 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexio1_flexio20: IOMUXC_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20 { + pinmux = <0x400e8060 8 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexpwm2_pwm3_b: IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B { + pinmux = <0x400e8060 1 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio7_io20: IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 { + pinmux = <0x400e8060 10 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio_mux1_io20: IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 { + pinmux = <0x400e8060 5 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_qtimer4_timer0: IOMUXC_GPIO_EMC_B1_20_QTIMER4_TIMER0 { + pinmux = <0x400e8060 2 0x400e8660 0 0x400e82a4>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_semc_addr12: IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 { + pinmux = <0x400e8060 0 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexio1_flexio21: IOMUXC_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21 { + pinmux = <0x400e8064 8 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A { + pinmux = <0x400e8064 1 0x400e853c 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio7_io21: IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 { + pinmux = <0x400e8064 10 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio_mux1_io21: IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 { + pinmux = <0x400e8064 5 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_semc_ba0: IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 { + pinmux = <0x400e8064 0 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexio1_flexio22: IOMUXC_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22 { + pinmux = <0x400e8068 8 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B { + pinmux = <0x400e8068 1 0x400e854c 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio7_io22: IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 { + pinmux = <0x400e8068 10 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio_mux1_io22: IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 { + pinmux = <0x400e8068 5 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_semc_ba1: IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 { + pinmux = <0x400e8068 0 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexio1_flexio23: IOMUXC_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23 { + pinmux = <0x400e806c 8 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexpwm1_pwm0_a: IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A { + pinmux = <0x400e806c 1 0x400e8500 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio7_io23: IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 { + pinmux = <0x400e806c 10 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio_mux1_io23: IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 { + pinmux = <0x400e806c 5 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_semc_addr10: IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 { + pinmux = <0x400e806c 0 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexio1_flexio24: IOMUXC_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24 { + pinmux = <0x400e8070 8 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexpwm1_pwm0_b: IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B { + pinmux = <0x400e8070 1 0x400e850c 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio7_io24: IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 { + pinmux = <0x400e8070 10 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio_mux1_io24: IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 { + pinmux = <0x400e8070 5 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_semc_cas: IOMUXC_GPIO_EMC_B1_24_SEMC_CAS { + pinmux = <0x400e8070 0 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexio1_flexio25: IOMUXC_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25 { + pinmux = <0x400e8074 8 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexpwm1_pwm1_a: IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A { + pinmux = <0x400e8074 1 0x400e8504 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio7_io25: IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 { + pinmux = <0x400e8074 10 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio_mux1_io25: IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 { + pinmux = <0x400e8074 5 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_semc_ras: IOMUXC_GPIO_EMC_B1_25_SEMC_RAS { + pinmux = <0x400e8074 0 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexio1_flexio26: IOMUXC_GPIO_EMC_B1_26_FLEXIO1_FLEXIO26 { + pinmux = <0x400e8078 8 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexpwm1_pwm1_b: IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B { + pinmux = <0x400e8078 1 0x400e8510 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio7_io26: IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 { + pinmux = <0x400e8078 10 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio_mux1_io26: IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 { + pinmux = <0x400e8078 5 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_semc_clk: IOMUXC_GPIO_EMC_B1_26_SEMC_CLK { + pinmux = <0x400e8078 0 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexio1_flexio27: IOMUXC_GPIO_EMC_B1_27_FLEXIO1_FLEXIO27 { + pinmux = <0x400e807c 8 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexpwm1_pwm2_a: IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A { + pinmux = <0x400e807c 1 0x400e8508 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio7_io27: IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 { + pinmux = <0x400e807c 10 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio_mux1_io27: IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 { + pinmux = <0x400e807c 5 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_semc_cke: IOMUXC_GPIO_EMC_B1_27_SEMC_CKE { + pinmux = <0x400e807c 0 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexio1_flexio28: IOMUXC_GPIO_EMC_B1_28_FLEXIO1_FLEXIO28 { + pinmux = <0x400e8080 8 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexpwm1_pwm2_b: IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B { + pinmux = <0x400e8080 1 0x400e8514 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio7_io28: IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 { + pinmux = <0x400e8080 10 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio_mux1_io28: IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 { + pinmux = <0x400e8080 5 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_semc_we: IOMUXC_GPIO_EMC_B1_28_SEMC_WE { + pinmux = <0x400e8080 0 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexio1_flexio29: IOMUXC_GPIO_EMC_B1_29_FLEXIO1_FLEXIO29 { + pinmux = <0x400e8084 8 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A { + pinmux = <0x400e8084 1 0x400e8530 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio7_io29: IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 { + pinmux = <0x400e8084 10 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio_mux1_io29: IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 { + pinmux = <0x400e8084 5 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_semc_cs0: IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 { + pinmux = <0x400e8084 0 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexio1_flexio30: IOMUXC_GPIO_EMC_B1_30_FLEXIO1_FLEXIO30 { + pinmux = <0x400e8088 8 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B { + pinmux = <0x400e8088 1 0x400e8540 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio7_io30: IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 { + pinmux = <0x400e8088 10 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio_mux1_io30: IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 { + pinmux = <0x400e8088 5 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_semc_data08: IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 { + pinmux = <0x400e8088 0 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexio1_flexio31: IOMUXC_GPIO_EMC_B1_31_FLEXIO1_FLEXIO31 { + pinmux = <0x400e808c 8 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A { + pinmux = <0x400e808c 1 0x400e8534 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio7_io31: IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 { + pinmux = <0x400e808c 10 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio_mux1_io31: IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 { + pinmux = <0x400e808c 5 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_semc_data09: IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 { + pinmux = <0x400e808c 0 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B { + pinmux = <0x400e8090 1 0x400e8544 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio8_io00: IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 { + pinmux = <0x400e8090 10 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00_cm7: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00_CM7 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_semc_data10: IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 { + pinmux = <0x400e8090 0 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A { + pinmux = <0x400e8094 1 0x400e8538 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio8_io01: IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 { + pinmux = <0x400e8094 10 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01_cm7: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01_CM7 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_semc_data11: IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 { + pinmux = <0x400e8094 0 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B { + pinmux = <0x400e8098 1 0x400e8548 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio8_io02: IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 { + pinmux = <0x400e8098 10 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02_cm7: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02_CM7 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_semc_data12: IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 { + pinmux = <0x400e8098 0 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio8_io03: IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 { + pinmux = <0x400e809c 10 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03_cm7: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03_CM7 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_semc_data13: IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 { + pinmux = <0x400e809c 0 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_in09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_IN09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_INOUT09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio8_io04: IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 { + pinmux = <0x400e80a0 10 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04_cm7: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04_CM7 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_semc_data14: IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 { + pinmux = <0x400e80a0 0 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_in10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_IN10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_INOUT10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio8_io05: IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 { + pinmux = <0x400e80a4 10 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05_cm7: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05_CM7 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_semc_data15: IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 { + pinmux = <0x400e80a4 0 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_in11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_IN11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_INOUT11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_flexpwm1_pwm3_a: IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A { + pinmux = <0x400e80a8 1 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio8_io06: IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 { + pinmux = <0x400e80a8 10 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06_cm7: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06_CM7 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_qtimer1_timer1: IOMUXC_GPIO_EMC_B1_38_QTIMER1_TIMER1 { + pinmux = <0x400e80a8 2 0x400e8640 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_semc_dm01: IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 { + pinmux = <0x400e80a8 0 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_flexpwm1_pwm3_b: IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B { + pinmux = <0x400e80ac 1 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio8_io07: IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 { + pinmux = <0x400e80ac 10 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07_cm7: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07_CM7 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_qtimer2_timer1: IOMUXC_GPIO_EMC_B1_39_QTIMER2_TIMER1 { + pinmux = <0x400e80ac 2 0x400e864c 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_semc_dqs: IOMUXC_GPIO_EMC_B1_39_SEMC_DQS { + pinmux = <0x400e80ac 0 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_ccm_clko1: IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 { + pinmux = <0x400e80b0 9 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_enet_1g_mdc: IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC { + pinmux = <0x400e80b0 7 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio8_io08: IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 { + pinmux = <0x400e80b0 10 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08_cm7: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08_CM7 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_lpuart6_tx: IOMUXC_GPIO_EMC_B1_40_LPUART6_TX { + pinmux = <0x400e80b0 3 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_mqs_right: IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT { + pinmux = <0x400e80b0 2 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_semc_rdy: IOMUXC_GPIO_EMC_B1_40_SEMC_RDY { + pinmux = <0x400e80b0 0 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_in12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_IN12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_INOUT12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_ccm_clko2: IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 { + pinmux = <0x400e80b4 9 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_enet_1g_mdio: IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO { + pinmux = <0x400e80b4 7 0x400e84c8 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_flexspi2_b_data07: IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 { + pinmux = <0x400e80b4 4 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio8_io09: IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 { + pinmux = <0x400e80b4 10 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09_cm7: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09_CM7 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_lpuart6_rx: IOMUXC_GPIO_EMC_B1_41_LPUART6_RX { + pinmux = <0x400e80b4 3 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_mqs_left: IOMUXC_GPIO_EMC_B1_41_MQS_LEFT { + pinmux = <0x400e80b4 2 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_semc_csx00: IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 { + pinmux = <0x400e80b4 0 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_in13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_IN13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_INOUT13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_ccm_enet_ref_clk_25m: IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e80b8 1 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A { + pinmux = <0x400e80b8 11 0x400e8530 1 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexspi2_b_data06: IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 { + pinmux = <0x400e80b8 4 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio8_io10: IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 { + pinmux = <0x400e80b8 10 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10_cm7: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10_CM7 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpi2c2_scl: IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL { + pinmux = <0x400e80b8 9 0x400e85b4 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpspi1_sck: IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK { + pinmux = <0x400e80b8 8 0x400e85d0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpuart6_cts_b: IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B { + pinmux = <0x400e80b8 3 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_00_QTIMER3_TIMER1 { + pinmux = <0x400e80b8 2 0x400e8658 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_semc_data16: IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 { + pinmux = <0x400e80b8 0 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_in20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_inout20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B { + pinmux = <0x400e80bc 11 0x400e8540 1 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexspi2_b_data05: IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 { + pinmux = <0x400e80bc 4 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio8_io11: IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 { + pinmux = <0x400e80bc 10 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11_cm7: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11_CM7 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpi2c2_sda: IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA { + pinmux = <0x400e80bc 9 0x400e85b8 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpspi1_pcs0: IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 { + pinmux = <0x400e80bc 8 0x400e85cc 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpuart6_rts_b: IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B { + pinmux = <0x400e80bc 3 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_qtimer4_timer1: IOMUXC_GPIO_EMC_B2_01_QTIMER4_TIMER1 { + pinmux = <0x400e80bc 2 0x400e8664 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_semc_data17: IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 { + pinmux = <0x400e80bc 0 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_usdhc2_cd_b: IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B { + pinmux = <0x400e80bc 1 0x400e86d0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_in21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_inout21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A { + pinmux = <0x400e80c0 11 0x400e8534 1 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexspi2_b_data04: IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 { + pinmux = <0x400e80c0 4 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio8_io12: IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 { + pinmux = <0x400e80c0 10 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12_cm7: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12_CM7 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_lpspi1_sdo: IOMUXC_GPIO_EMC_B2_02_LPSPI1_SDO { + pinmux = <0x400e80c0 8 0x400e85d8 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_semc_data18: IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 { + pinmux = <0x400e80c0 0 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_usdhc2_wp: IOMUXC_GPIO_EMC_B2_02_USDHC2_WP { + pinmux = <0x400e80c0 1 0x400e86d4 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_in22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_inout22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_enet_1g_tdata03: IOMUXC_GPIO_EMC_B2_03_ENET_1G_TDATA03 { + pinmux = <0x400e80c4 7 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B { + pinmux = <0x400e80c4 11 0x400e8544 1 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexspi2_b_data03: IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 { + pinmux = <0x400e80c4 4 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio8_io13: IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 { + pinmux = <0x400e80c4 10 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13_cm7: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13_CM7 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_lpspi1_sdi: IOMUXC_GPIO_EMC_B2_03_LPSPI1_SDI { + pinmux = <0x400e80c4 8 0x400e85d4 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_semc_data19: IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 { + pinmux = <0x400e80c4 0 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_usdhc2_vselect: IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT { + pinmux = <0x400e80c4 1 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_in23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_inout23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_enet_1g_tdata02: IOMUXC_GPIO_EMC_B2_04_ENET_1G_TDATA02 { + pinmux = <0x400e80c8 7 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A { + pinmux = <0x400e80c8 11 0x400e8538 1 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexspi2_b_data02: IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 { + pinmux = <0x400e80c8 4 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio8_io14: IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 { + pinmux = <0x400e80c8 10 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14_cm7: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14_CM7 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_lpspi3_sck: IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK { + pinmux = <0x400e80c8 8 0x400e8600 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_sai2_mclk: IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK { + pinmux = <0x400e80c8 2 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_semc_data20: IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 { + pinmux = <0x400e80c8 0 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_usdhc2_reset_b: IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B { + pinmux = <0x400e80c8 1 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_in24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_inout24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_enet_1g_rx_clk: IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK { + pinmux = <0x400e80cc 7 0x400e84cc 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B { + pinmux = <0x400e80cc 11 0x400e8548 1 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexspi2_b_data01: IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 { + pinmux = <0x400e80cc 4 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio8_io15: IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 { + pinmux = <0x400e80cc 10 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15_cm7: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15_CM7 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpt3_clk: IOMUXC_GPIO_EMC_B2_05_GPT3_CLK { + pinmux = <0x400e80cc 1 0x400e8598 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_lpspi3_pcs0: IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 { + pinmux = <0x400e80cc 8 0x400e85f0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_pit1_trigger00: IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER00 { + pinmux = <0x400e80cc 9 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_sai2_rx_sync: IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC { + pinmux = <0x400e80cc 2 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_semc_data21: IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 { + pinmux = <0x400e80cc 0 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_in25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_inout25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_enet_1g_tx_er: IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER { + pinmux = <0x400e80d0 7 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A { + pinmux = <0x400e80d0 11 0x400e853c 1 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexspi2_b_data00: IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 { + pinmux = <0x400e80d0 4 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio8_io16: IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 { + pinmux = <0x400e80d0 10 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16_cm7: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16_CM7 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpt3_capture1: IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 { + pinmux = <0x400e80d0 1 0x400e8590 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_lpspi3_sdo: IOMUXC_GPIO_EMC_B2_06_LPSPI3_SDO { + pinmux = <0x400e80d0 8 0x400e8608 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_pit1_trigger01: IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER01 { + pinmux = <0x400e80d0 9 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_sai2_rx_bclk: IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK { + pinmux = <0x400e80d0 2 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_semc_data22: IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 { + pinmux = <0x400e80d0 0 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_in26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_IN26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_inout26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_enet_1g_rdata03: IOMUXC_GPIO_EMC_B2_07_ENET_1G_RDATA03 { + pinmux = <0x400e80d4 7 0x400e84dc 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B { + pinmux = <0x400e80d4 11 0x400e854c 1 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexspi2_b_dqs: IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS { + pinmux = <0x400e80d4 4 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio8_io17: IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 { + pinmux = <0x400e80d4 10 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17_cm7: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17_CM7 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpt3_capture2: IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 { + pinmux = <0x400e80d4 1 0x400e8594 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_lpspi3_sdi: IOMUXC_GPIO_EMC_B2_07_LPSPI3_SDI { + pinmux = <0x400e80d4 8 0x400e8604 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_pit1_trigger02: IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER02 { + pinmux = <0x400e80d4 9 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_sai2_rx_data: IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA { + pinmux = <0x400e80d4 2 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_semc_data23: IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 { + pinmux = <0x400e80d4 0 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_in27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_IN27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_inout27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_enet_1g_rdata02: IOMUXC_GPIO_EMC_B2_08_ENET_1G_RDATA02 { + pinmux = <0x400e80d8 7 0x400e84d8 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B { + pinmux = <0x400e80d8 4 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio8_io18: IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 { + pinmux = <0x400e80d8 10 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18_cm7: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18_CM7 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpt3_compare1: IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 { + pinmux = <0x400e80d8 1 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_lpspi3_pcs1: IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 { + pinmux = <0x400e80d8 8 0x400e85f4 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_pit1_trigger03: IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER03 { + pinmux = <0x400e80d8 9 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_sai2_tx_data: IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA { + pinmux = <0x400e80d8 2 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_semc_dm02: IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 { + pinmux = <0x400e80d8 0 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_in28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_IN28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_inout28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_enet_1g_crs: IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS { + pinmux = <0x400e80dc 7 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_flexspi2_b_sclk: IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK { + pinmux = <0x400e80dc 4 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio8_io19: IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 { + pinmux = <0x400e80dc 10 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19_cm7: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19_CM7 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpt3_compare2: IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 { + pinmux = <0x400e80dc 1 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_lpspi3_pcs2: IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 { + pinmux = <0x400e80dc 8 0x400e85f8 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_qtimer1_timer0: IOMUXC_GPIO_EMC_B2_09_QTIMER1_TIMER0 { + pinmux = <0x400e80dc 9 0x400e863c 1 0x400e8320>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_sai2_tx_bclk: IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK { + pinmux = <0x400e80dc 2 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_semc_data24: IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 { + pinmux = <0x400e80dc 0 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_in29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_IN29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_inout29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_enet_1g_col: IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL { + pinmux = <0x400e80e0 7 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_flexspi2_a_sclk: IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK { + pinmux = <0x400e80e0 4 0x400e858c 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio8_io20: IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 { + pinmux = <0x400e80e0 10 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20_cm7: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20_CM7 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpt3_compare3: IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 { + pinmux = <0x400e80e0 1 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_lpspi3_pcs3: IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 { + pinmux = <0x400e80e0 8 0x400e85fc 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_qtimer1_timer1: IOMUXC_GPIO_EMC_B2_10_QTIMER1_TIMER1 { + pinmux = <0x400e80e0 9 0x400e8640 1 0x400e8324>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_sai2_tx_sync: IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC { + pinmux = <0x400e80e0 2 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_semc_data25: IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 { + pinmux = <0x400e80e0 0 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_in30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_IN30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_inout30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_enet_1g_tdata00: IOMUXC_GPIO_EMC_B2_11_ENET_1G_TDATA00 { + pinmux = <0x400e80e4 2 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B { + pinmux = <0x400e80e4 4 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio8_io21: IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 { + pinmux = <0x400e80e4 10 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21_cm7: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21_CM7 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_qtimer1_timer2: IOMUXC_GPIO_EMC_B2_11_QTIMER1_TIMER2 { + pinmux = <0x400e80e4 9 0x400e8644 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sai3_rx_sync: IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC { + pinmux = <0x400e80e4 3 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_semc_data26: IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 { + pinmux = <0x400e80e4 0 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sim1_trxd: IOMUXC_GPIO_EMC_B2_11_SIM1_TRXD { + pinmux = <0x400e80e4 8 0x400e869c 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_spdif_in: IOMUXC_GPIO_EMC_B2_11_SPDIF_IN { + pinmux = <0x400e80e4 1 0x400e86b4 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_in31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_IN31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_inout31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_enet_1g_tdata01: IOMUXC_GPIO_EMC_B2_12_ENET_1G_TDATA01 { + pinmux = <0x400e80e8 2 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_flexspi2_a_dqs: IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS { + pinmux = <0x400e80e8 4 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio8_io22: IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 { + pinmux = <0x400e80e8 10 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22_cm7: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22_CM7 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_qtimer1_timer3: IOMUXC_GPIO_EMC_B2_12_QTIMER1_TIMER3 { + pinmux = <0x400e80e8 9 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4030 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sai3_rx_bclk: IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK { + pinmux = <0x400e80e8 3 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_semc_data27: IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 { + pinmux = <0x400e80e8 0 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sim1_clk: IOMUXC_GPIO_EMC_B2_12_SIM1_CLK { + pinmux = <0x400e80e8 8 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_spdif_out: IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT { + pinmux = <0x400e80e8 1 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_in32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_IN32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_inout32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_enet_1g_tx_en: IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN { + pinmux = <0x400e80ec 2 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_flexspi2_a_data00: IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 { + pinmux = <0x400e80ec 4 0x400e857c 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio8_io23: IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 { + pinmux = <0x400e80ec 10 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23_cm7: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23_CM7 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_qtimer2_timer0: IOMUXC_GPIO_EMC_B2_13_QTIMER2_TIMER0 { + pinmux = <0x400e80ec 9 0x400e8648 1 0x400e8330>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sai3_rx_data: IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA { + pinmux = <0x400e80ec 3 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_semc_data28: IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 { + pinmux = <0x400e80ec 0 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sim1_rst_b: IOMUXC_GPIO_EMC_B2_13_SIM1_RST_B { + pinmux = <0x400e80ec 8 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_in33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_IN33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_inout33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_enet_1g_tx_clk_io: IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO { + pinmux = <0x400e80f0 2 0x400e84e8 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_flexspi2_a_data01: IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 { + pinmux = <0x400e80f0 4 0x400e8580 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio8_io24: IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 { + pinmux = <0x400e80f0 10 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24_cm7: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24_CM7 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_qtimer2_timer1: IOMUXC_GPIO_EMC_B2_14_QTIMER2_TIMER1 { + pinmux = <0x400e80f0 9 0x400e864c 1 0x400e8334>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sai3_tx_data: IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA { + pinmux = <0x400e80f0 3 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_semc_data29: IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 { + pinmux = <0x400e80f0 0 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sim1_sven: IOMUXC_GPIO_EMC_B2_14_SIM1_SVEN { + pinmux = <0x400e80f0 8 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_in34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_IN34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_inout34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_enet_1g_rdata00: IOMUXC_GPIO_EMC_B2_15_ENET_1G_RDATA00 { + pinmux = <0x400e80f4 2 0x400e84d0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_flexspi2_a_data02: IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 { + pinmux = <0x400e80f4 4 0x400e8584 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio8_io25: IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 { + pinmux = <0x400e80f4 10 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25_cm7: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25_CM7 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_qtimer2_timer2: IOMUXC_GPIO_EMC_B2_15_QTIMER2_TIMER2 { + pinmux = <0x400e80f4 9 0x400e8650 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sai3_tx_bclk: IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK { + pinmux = <0x400e80f4 3 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_semc_data30: IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 { + pinmux = <0x400e80f4 0 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sim1_pd: IOMUXC_GPIO_EMC_B2_15_SIM1_PD { + pinmux = <0x400e80f4 8 0x400e86a0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_in35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_IN35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_inout35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_enet_1g_rdata01: IOMUXC_GPIO_EMC_B2_16_ENET_1G_RDATA01 { + pinmux = <0x400e80f8 2 0x400e84d4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_flexspi2_a_data03: IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 { + pinmux = <0x400e80f8 4 0x400e8588 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio8_io26: IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 { + pinmux = <0x400e80f8 10 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26_cm7: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26_CM7 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_qtimer2_timer3: IOMUXC_GPIO_EMC_B2_16_QTIMER2_TIMER3 { + pinmux = <0x400e80f8 9 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4034 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sai3_tx_sync: IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC { + pinmux = <0x400e80f8 3 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_semc_data31: IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 { + pinmux = <0x400e80f8 0 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sim1_power_fail: IOMUXC_GPIO_EMC_B2_16_SIM1_POWER_FAIL { + pinmux = <0x400e80f8 8 0x400e86a4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_in14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_IN14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_enet_1g_rx_en: IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN { + pinmux = <0x400e80fc 2 0x400e84e0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_flexspi2_a_data04: IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 { + pinmux = <0x400e80fc 4 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio8_io27: IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 { + pinmux = <0x400e80fc 10 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27_cm7: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27_CM7 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_qtimer3_timer0: IOMUXC_GPIO_EMC_B2_17_QTIMER3_TIMER0 { + pinmux = <0x400e80fc 9 0x400e8654 1 0x400e8340>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_sai3_mclk: IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK { + pinmux = <0x400e80fc 3 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_semc_dm03: IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 { + pinmux = <0x400e80fc 0 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_wdog1_wdog_any: IOMUXC_GPIO_EMC_B2_17_WDOG1_WDOG_ANY { + pinmux = <0x400e80fc 8 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_in15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_IN15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_enet_1g_rx_er: IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER { + pinmux = <0x400e8100 2 0x400e84e4 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_ewm_ewm_out_b: IOMUXC_GPIO_EMC_B2_18_EWM_EWM_OUT_B { + pinmux = <0x400e8100 3 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi1_a_dqs: IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS { + pinmux = <0x400e8100 6 0x400e8550 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi2_a_data05: IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 { + pinmux = <0x400e8100 4 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio8_io28: IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 { + pinmux = <0x400e8100 10 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28_cm7: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28_CM7 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_18_QTIMER3_TIMER1 { + pinmux = <0x400e8100 9 0x400e8658 1 0x400e8344>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_semc_dqs4: IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 { + pinmux = <0x400e8100 0 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_wdog1_wdog_b: IOMUXC_GPIO_EMC_B2_18_WDOG1_WDOG_B { + pinmux = <0x400e8100 8 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_IN16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC { + pinmux = <0x400e8104 2 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_ref_clk1: IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK1 { + pinmux = <0x400e8104 3 0x400e84c4 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_MDC { + pinmux = <0x400e8104 1 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_flexspi2_a_data06: IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 { + pinmux = <0x400e8104 4 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio8_io29: IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 { + pinmux = <0x400e8104 10 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29_cm7: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29_CM7 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_qtimer3_timer2: IOMUXC_GPIO_EMC_B2_19_QTIMER3_TIMER2 { + pinmux = <0x400e8104 9 0x400e865c 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_semc_clkx00: IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 { + pinmux = <0x400e8104 0 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_1g_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO { + pinmux = <0x400e8108 2 0x400e84c8 1 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_MDIO { + pinmux = <0x400e8108 1 0x400e84ac 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_flexspi2_a_data07: IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 { + pinmux = <0x400e8108 4 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio8_io30: IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 { + pinmux = <0x400e8108 10 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30_cm7: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30_CM7 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_qtimer3_timer3: IOMUXC_GPIO_EMC_B2_20_QTIMER3_TIMER3 { + pinmux = <0x400e8108 9 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e4038 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_semc_clkx01: IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 { + pinmux = <0x400e8108 0 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_can3_tx: IOMUXC_LPSR_GPIO_LPSR_00_CAN3_TX { + pinmux = <0x40c08000 0 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_cm4_imxrt_txev: IOMUXC_LPSR_GPIO_LPSR_00_CM4_IMXRT_TXEV { + pinmux = <0x40c08000 3 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio12_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO12_IO00 { + pinmux = <0x40c08000 10 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio_mux6_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO_MUX6_IO00 { + pinmux = <0x40c08000 5 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_00_LPUART12_TX { + pinmux = <0x40c08000 6 0x40c080b0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mic_clk: IOMUXC_LPSR_GPIO_LPSR_00_MIC_CLK { + pinmux = <0x40c08000 1 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mqs_right: IOMUXC_LPSR_GPIO_LPSR_00_MQS_RIGHT { + pinmux = <0x40c08000 2 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_00_SAI4_MCLK { + pinmux = <0x40c08000 7 0x40c080c8 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_can3_rx: IOMUXC_LPSR_GPIO_LPSR_01_CAN3_RX { + pinmux = <0x40c08004 0 0x40c08080 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_cm4_imxrt_rxev: IOMUXC_LPSR_GPIO_LPSR_01_CM4_IMXRT_RXEV { + pinmux = <0x40c08004 3 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio12_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO12_IO01 { + pinmux = <0x40c08004 10 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO_MUX6_IO01 { + pinmux = <0x40c08004 5 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_01_LPUART12_RX { + pinmux = <0x40c08004 6 0x40c080ac 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_01_MIC_BITSTREAM00 { + pinmux = <0x40c08004 1 0x40c080b4 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mqs_left: IOMUXC_LPSR_GPIO_LPSR_01_MQS_LEFT { + pinmux = <0x40c08004 2 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio12_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO12_IO02 { + pinmux = <0x40c08008 10 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO_MUX6_IO02 { + pinmux = <0x40c08008 5 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_02_LPSPI5_SCK { + pinmux = <0x40c08008 1 0x40c08098 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_mqs_right: IOMUXC_LPSR_GPIO_LPSR_02_MQS_RIGHT { + pinmux = <0x40c08008 3 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_02_SAI4_TX_DATA { + pinmux = <0x40c08008 2 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_src_boot_mode00: IOMUXC_LPSR_GPIO_LPSR_02_SRC_BOOT_MODE00 { + pinmux = <0x40c08008 0 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio12_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO12_IO03 { + pinmux = <0x40c0800c 10 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO_MUX6_IO03 { + pinmux = <0x40c0800c 5 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_03_LPSPI5_PCS0 { + pinmux = <0x40c0800c 1 0x40c08094 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_mqs_left: IOMUXC_LPSR_GPIO_LPSR_03_MQS_LEFT { + pinmux = <0x40c0800c 3 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_03_SAI4_TX_SYNC { + pinmux = <0x40c0800c 2 0x40c080dc 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_src_boot_mode01: IOMUXC_LPSR_GPIO_LPSR_03_SRC_BOOT_MODE01 { + pinmux = <0x40c0800c 0 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio12_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO12_IO04 { + pinmux = <0x40c08010 10 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO_MUX6_IO04 { + pinmux = <0x40c08010 5 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_04_LPI2C5_SDA { + pinmux = <0x40c08010 0 0x40c08088 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_04_LPSPI5_SDO { + pinmux = <0x40c08010 1 0x40c080a0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_04_LPUART11_TX { + pinmux = <0x40c08010 6 0x40c080a8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart12_rts_b: IOMUXC_LPSR_GPIO_LPSR_04_LPUART12_RTS_B { + pinmux = <0x40c08010 3 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_04_SAI4_TX_BCLK { + pinmux = <0x40c08010 2 0x40c080d8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio12_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO12_IO05 { + pinmux = <0x40c08014 10 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO_MUX6_IO05 { + pinmux = <0x40c08014 5 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_05_LPI2C5_SCL { + pinmux = <0x40c08014 0 0x40c08084 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_05_LPSPI5_SDI { + pinmux = <0x40c08014 1 0x40c0809c 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_05_LPUART11_RX { + pinmux = <0x40c08014 6 0x40c080a4 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart12_cts_b: IOMUXC_LPSR_GPIO_LPSR_05_LPUART12_CTS_B { + pinmux = <0x40c08014 3 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_05_SAI4_MCLK { + pinmux = <0x40c08014 2 0x40c080c8 1 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_can3_tx: IOMUXC_LPSR_GPIO_LPSR_06_CAN3_TX { + pinmux = <0x40c08018 6 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio12_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO12_IO06 { + pinmux = <0x40c08018 10 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO_MUX6_IO06 { + pinmux = <0x40c08018 5 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_06_LPI2C6_SDA { + pinmux = <0x40c08018 0 0x40c08090 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi5_pcs1: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI5_PCS1 { + pinmux = <0x40c08018 8 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi6_pcs3: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI6_PCS3 { + pinmux = <0x40c08018 4 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_06_LPUART12_TX { + pinmux = <0x40c08018 3 0x40c080b0 1 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_06_PIT2_TRIGGER03 { + pinmux = <0x40c08018 7 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_06_SAI4_RX_DATA { + pinmux = <0x40c08018 2 0x40c080d0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_can3_rx: IOMUXC_LPSR_GPIO_LPSR_07_CAN3_RX { + pinmux = <0x40c0801c 6 0x40c08080 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio12_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO12_IO07 { + pinmux = <0x40c0801c 10 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO_MUX6_IO07 { + pinmux = <0x40c0801c 5 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_07_LPI2C6_SCL { + pinmux = <0x40c0801c 0 0x40c0808c 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi5_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI5_PCS2 { + pinmux = <0x40c0801c 8 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi6_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI6_PCS2 { + pinmux = <0x40c0801c 4 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_07_LPUART12_RX { + pinmux = <0x40c0801c 3 0x40c080ac 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_07_PIT2_TRIGGER02 { + pinmux = <0x40c0801c 7 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_07_SAI4_RX_BCLK { + pinmux = <0x40c0801c 2 0x40c080cc 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_can3_tx: IOMUXC_LPSR_GPIO_LPSR_08_CAN3_TX { + pinmux = <0x40c08020 1 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio12_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO12_IO08 { + pinmux = <0x40c08020 10 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO_MUX6_IO08 { + pinmux = <0x40c08020 5 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_08_LPI2C5_SDA { + pinmux = <0x40c08020 6 0x40c08088 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi5_pcs3: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI5_PCS3 { + pinmux = <0x40c08020 8 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi6_pcs1: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI6_PCS1 { + pinmux = <0x40c08020 4 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_08_LPUART11_TX { + pinmux = <0x40c08020 0 0x40c080a8 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_mic_clk: IOMUXC_LPSR_GPIO_LPSR_08_MIC_CLK { + pinmux = <0x40c08020 3 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_08_PIT2_TRIGGER01 { + pinmux = <0x40c08020 7 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_08_SAI4_RX_SYNC { + pinmux = <0x40c08020 2 0x40c080d4 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_can3_rx: IOMUXC_LPSR_GPIO_LPSR_09_CAN3_RX { + pinmux = <0x40c08024 1 0x40c08080 2 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio12_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO12_IO09 { + pinmux = <0x40c08024 10 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO_MUX6_IO09 { + pinmux = <0x40c08024 5 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_09_LPI2C5_SCL { + pinmux = <0x40c08024 6 0x40c08084 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpspi6_pcs0: IOMUXC_LPSR_GPIO_LPSR_09_LPSPI6_PCS0 { + pinmux = <0x40c08024 4 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_09_LPUART11_RX { + pinmux = <0x40c08024 0 0x40c080a4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_09_MIC_BITSTREAM00 { + pinmux = <0x40c08024 3 0x40c080b4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_09_PIT2_TRIGGER00 { + pinmux = <0x40c08024 2 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_09_SAI4_TX_DATA { + pinmux = <0x40c08024 7 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio12_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO12_IO10 { + pinmux = <0x40c08028 10 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO_MUX6_IO10 { + pinmux = <0x40c08028 5 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_jtag_mux_trstb: IOMUXC_LPSR_GPIO_LPSR_10_JTAG_MUX_TRSTB { + pinmux = <0x40c08028 0 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c5_scls: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C5_SCLS { + pinmux = <0x40c08028 6 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C6_SDA { + pinmux = <0x40c08028 2 0x40c08090 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpspi6_sck: IOMUXC_LPSR_GPIO_LPSR_10_LPSPI6_SCK { + pinmux = <0x40c08028 4 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart11_cts_b: IOMUXC_LPSR_GPIO_LPSR_10_LPUART11_CTS_B { + pinmux = <0x40c08028 1 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_10_LPUART12_TX { + pinmux = <0x40c08028 8 0x40c080b0 2 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_10_MIC_BITSTREAM01 { + pinmux = <0x40c08028 3 0x40c080b8 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_10_SAI4_TX_SYNC { + pinmux = <0x40c08028 7 0x40c080dc 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_arm_trace_swo: IOMUXC_LPSR_GPIO_LPSR_11_ARM_TRACE_SWO { + pinmux = <0x40c0802c 7 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio12_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO12_IO11 { + pinmux = <0x40c0802c 10 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO_MUX6_IO11 { + pinmux = <0x40c0802c 5 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_jtag_mux_tdo: IOMUXC_LPSR_GPIO_LPSR_11_JTAG_MUX_TDO { + pinmux = <0x40c0802c 0 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c5_sdas: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C5_SDAS { + pinmux = <0x40c0802c 6 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C6_SCL { + pinmux = <0x40c0802c 2 0x40c0808c 1 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpspi6_sdo: IOMUXC_LPSR_GPIO_LPSR_11_LPSPI6_SDO { + pinmux = <0x40c0802c 4 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart11_rts_b: IOMUXC_LPSR_GPIO_LPSR_11_LPUART11_RTS_B { + pinmux = <0x40c0802c 1 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_11_LPUART12_RX { + pinmux = <0x40c0802c 8 0x40c080ac 2 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_11_MIC_BITSTREAM02 { + pinmux = <0x40c0802c 3 0x40c080bc 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio12_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO12_IO12 { + pinmux = <0x40c08030 10 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO_MUX6_IO12 { + pinmux = <0x40c08030 5 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_jtag_mux_tdi: IOMUXC_LPSR_GPIO_LPSR_12_JTAG_MUX_TDI { + pinmux = <0x40c08030 0 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpi2c5_hreq: IOMUXC_LPSR_GPIO_LPSR_12_LPI2C5_HREQ { + pinmux = <0x40c08030 6 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI5_SCK { + pinmux = <0x40c08030 8 0x40c08098 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi6_sdi: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI6_SDI { + pinmux = <0x40c08030 4 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_12_MIC_BITSTREAM03 { + pinmux = <0x40c08030 3 0x40c080c0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_12_PIT2_TRIGGER00 { + pinmux = <0x40c08030 1 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_12_SAI4_TX_BCLK { + pinmux = <0x40c08030 7 0x40c080d8 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio12_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO12_IO13 { + pinmux = <0x40c08034 10 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO_MUX6_IO13 { + pinmux = <0x40c08034 5 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_jtag_mux_mod: IOMUXC_LPSR_GPIO_LPSR_13_JTAG_MUX_MOD { + pinmux = <0x40c08034 0 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_13_LPSPI5_PCS0 { + pinmux = <0x40c08034 8 0x40c08094 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_13_MIC_BITSTREAM01 { + pinmux = <0x40c08034 1 0x40c080b8 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_13_PIT2_TRIGGER01 { + pinmux = <0x40c08034 2 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_13_SAI4_RX_DATA { + pinmux = <0x40c08034 7 0x40c080d0 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio12_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO12_IO14 { + pinmux = <0x40c08038 10 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO_MUX6_IO14 { + pinmux = <0x40c08038 5 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_jtag_mux_tck: IOMUXC_LPSR_GPIO_LPSR_14_JTAG_MUX_TCK { + pinmux = <0x40c08038 0 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_14_LPSPI5_SDO { + pinmux = <0x40c08038 8 0x40c080a0 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_14_MIC_BITSTREAM02 { + pinmux = <0x40c08038 1 0x40c080bc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_14_PIT2_TRIGGER02 { + pinmux = <0x40c08038 2 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_14_SAI4_RX_BCLK { + pinmux = <0x40c08038 7 0x40c080cc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio12_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO12_IO15 { + pinmux = <0x40c0803c 10 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO_MUX6_IO15 { + pinmux = <0x40c0803c 5 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_jtag_mux_tms: IOMUXC_LPSR_GPIO_LPSR_15_JTAG_MUX_TMS { + pinmux = <0x40c0803c 0 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_15_LPSPI5_SDI { + pinmux = <0x40c0803c 8 0x40c0809c 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_15_MIC_BITSTREAM03 { + pinmux = <0x40c0803c 1 0x40c080c0 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_15_PIT2_TRIGGER03 { + pinmux = <0x40c0803c 2 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_15_SAI4_RX_SYNC { + pinmux = <0x40c0803c 7 0x40c080d4 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi2_a_ss0_b: IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B { + pinmux = <0x400e819c 6 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio10_io03: IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 { + pinmux = <0x400e819c 10 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio_mux4_io03: IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 { + pinmux = <0x400e819c 5 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpt4_capture1: IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 { + pinmux = <0x400e819c 3 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_kpp_row07: IOMUXC_GPIO_SD_B1_00_KPP_ROW07 { + pinmux = <0x400e819c 8 0x400e85a8 1 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc1_cmd: IOMUXC_GPIO_SD_B1_00_USDHC1_CMD { + pinmux = <0x400e819c 0 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi2_a_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK { + pinmux = <0x400e81a0 6 0x400e858c 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio10_io04: IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 { + pinmux = <0x400e81a0 10 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio_mux4_io04: IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 { + pinmux = <0x400e81a0 5 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpt4_capture2: IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 { + pinmux = <0x400e81a0 3 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_kpp_col07: IOMUXC_GPIO_SD_B1_01_KPP_COL07 { + pinmux = <0x400e81a0 8 0x400e85a0 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc1_clk: IOMUXC_GPIO_SD_B1_01_USDHC1_CLK { + pinmux = <0x400e81a0 0 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_in21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_inout21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81a4 9 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi2_a_data00: IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 { + pinmux = <0x400e81a4 6 0x400e857c 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio10_io05: IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 { + pinmux = <0x400e81a4 10 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio_mux4_io05: IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 { + pinmux = <0x400e81a4 5 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpt4_compare1: IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 { + pinmux = <0x400e81a4 3 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_kpp_row06: IOMUXC_GPIO_SD_B1_02_KPP_ROW06 { + pinmux = <0x400e81a4 8 0x400e85a4 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc1_data0: IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 { + pinmux = <0x400e81a4 0 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_in22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_inout22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi1_b_ss1_b: IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B { + pinmux = <0x400e81a8 9 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi2_a_data01: IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 { + pinmux = <0x400e81a8 6 0x400e8580 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio10_io06: IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 { + pinmux = <0x400e81a8 10 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio_mux4_io06: IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 { + pinmux = <0x400e81a8 5 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpt4_compare2: IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 { + pinmux = <0x400e81a8 3 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_kpp_col06: IOMUXC_GPIO_SD_B1_03_KPP_COL06 { + pinmux = <0x400e81a8 8 0x400e859c 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc1_data1: IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 { + pinmux = <0x400e81a8 0 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_in23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_inout23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81ac 8 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi2_a_data02: IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 { + pinmux = <0x400e81ac 6 0x400e8584 1 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio10_io07: IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 { + pinmux = <0x400e81ac 10 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio_mux4_io07: IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 { + pinmux = <0x400e81ac 5 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpt4_compare3: IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 { + pinmux = <0x400e81ac 3 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc1_data2: IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 { + pinmux = <0x400e81ac 0 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_in24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_inout24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi1_b_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS { + pinmux = <0x400e81b0 8 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi2_a_data03: IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 { + pinmux = <0x400e81b0 6 0x400e8588 1 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio10_io08: IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 { + pinmux = <0x400e81b0 10 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio_mux4_io08: IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 { + pinmux = <0x400e81b0 5 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpt4_clk: IOMUXC_GPIO_SD_B1_05_GPT4_CLK { + pinmux = <0x400e81b0 3 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc1_data3: IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 { + pinmux = <0x400e81b0 0 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_in25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_inout25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_enet_1g_rx_en: IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN { + pinmux = <0x400e81b4 2 0x400e84e0 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_flexspi1_b_data03: IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 { + pinmux = <0x400e81b4 1 0x400e8570 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio10_io09: IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 { + pinmux = <0x400e81b4 10 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio_mux4_io09: IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 { + pinmux = <0x400e81b4 5 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpspi4_sck: IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK { + pinmux = <0x400e81b4 4 0x400e8610 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpuart9_tx: IOMUXC_GPIO_SD_B2_00_LPUART9_TX { + pinmux = <0x400e81b4 3 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_usdhc2_data3: IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 { + pinmux = <0x400e81b4 0 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_enet_1g_rx_clk: IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK { + pinmux = <0x400e81b8 2 0x400e84cc 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_flexspi1_b_data02: IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 { + pinmux = <0x400e81b8 1 0x400e856c 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio10_io10: IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 { + pinmux = <0x400e81b8 10 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio_mux4_io10: IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 { + pinmux = <0x400e81b8 5 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpspi4_pcs0: IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 { + pinmux = <0x400e81b8 4 0x400e860c 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpuart9_rx: IOMUXC_GPIO_SD_B2_01_LPUART9_RX { + pinmux = <0x400e81b8 3 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_usdhc2_data2: IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 { + pinmux = <0x400e81b8 0 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_enet_1g_rdata00: IOMUXC_GPIO_SD_B2_02_ENET_1G_RDATA00 { + pinmux = <0x400e81bc 2 0x400e84d0 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_flexspi1_b_data01: IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 { + pinmux = <0x400e81bc 1 0x400e8568 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio10_io11: IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 { + pinmux = <0x400e81bc 10 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio_mux4_io11: IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 { + pinmux = <0x400e81bc 5 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpspi4_sdo: IOMUXC_GPIO_SD_B2_02_LPSPI4_SDO { + pinmux = <0x400e81bc 4 0x400e8618 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpuart9_cts_b: IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B { + pinmux = <0x400e81bc 3 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_usdhc2_data1: IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 { + pinmux = <0x400e81bc 0 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_enet_1g_rdata01: IOMUXC_GPIO_SD_B2_03_ENET_1G_RDATA01 { + pinmux = <0x400e81c0 2 0x400e84d4 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_flexspi1_b_data00: IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 { + pinmux = <0x400e81c0 1 0x400e8564 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio10_io12: IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 { + pinmux = <0x400e81c0 10 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio_mux4_io12: IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 { + pinmux = <0x400e81c0 5 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpspi4_sdi: IOMUXC_GPIO_SD_B2_03_LPSPI4_SDI { + pinmux = <0x400e81c0 4 0x400e8614 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpuart9_rts_b: IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B { + pinmux = <0x400e81c0 3 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_usdhc2_data0: IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 { + pinmux = <0x400e81c0 0 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_enet_1g_rdata02: IOMUXC_GPIO_SD_B2_04_ENET_1G_RDATA02 { + pinmux = <0x400e81c4 2 0x400e84d8 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81c4 3 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_b_sclk: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK { + pinmux = <0x400e81c4 1 0x400e8578 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio10_io13: IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 { + pinmux = <0x400e81c4 10 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio_mux4_io13: IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 { + pinmux = <0x400e81c4 5 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_lpspi4_pcs1: IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 { + pinmux = <0x400e81c4 4 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_usdhc2_clk: IOMUXC_GPIO_SD_B2_04_USDHC2_CLK { + pinmux = <0x400e81c4 0 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_enet_1g_rdata03: IOMUXC_GPIO_SD_B2_05_ENET_1G_RDATA03 { + pinmux = <0x400e81c8 2 0x400e84dc 1 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_a_dqs: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS { + pinmux = <0x400e81c8 1 0x400e8550 2 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81c8 3 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio10_io14: IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 { + pinmux = <0x400e81c8 10 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio_mux4_io14: IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 { + pinmux = <0x400e81c8 5 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_lpspi4_pcs2: IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 { + pinmux = <0x400e81c8 4 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_usdhc2_cmd: IOMUXC_GPIO_SD_B2_05_USDHC2_CMD { + pinmux = <0x400e81c8 0 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_enet_1g_tdata03: IOMUXC_GPIO_SD_B2_06_ENET_1G_TDATA03 { + pinmux = <0x400e81cc 2 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_flexspi1_a_ss0_b: IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B { + pinmux = <0x400e81cc 1 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio10_io15: IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 { + pinmux = <0x400e81cc 10 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio_mux4_io15: IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 { + pinmux = <0x400e81cc 5 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpt6_capture1: IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 { + pinmux = <0x400e81cc 4 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_lpspi4_pcs3: IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 { + pinmux = <0x400e81cc 3 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B { + pinmux = <0x400e81cc 0 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_1g_tdata02: IOMUXC_GPIO_SD_B2_07_ENET_1G_TDATA02 { + pinmux = <0x400e81d0 2 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_tx_er: IOMUXC_GPIO_SD_B2_07_ENET_TX_ER { + pinmux = <0x400e81d0 8 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_flexspi1_a_sclk: IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK { + pinmux = <0x400e81d0 1 0x400e8574 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio10_io16: IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 { + pinmux = <0x400e81d0 10 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio_mux4_io16: IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 { + pinmux = <0x400e81d0 5 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpt6_capture2: IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 { + pinmux = <0x400e81d0 4 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpspi2_sck: IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK { + pinmux = <0x400e81d0 6 0x400e85e4 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpuart3_cts_b: IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B { + pinmux = <0x400e81d0 3 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_usdhc2_strobe: IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE { + pinmux = <0x400e81d0 0 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_enet_1g_tdata01: IOMUXC_GPIO_SD_B2_08_ENET_1G_TDATA01 { + pinmux = <0x400e81d4 2 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_flexspi1_a_data00: IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 { + pinmux = <0x400e81d4 1 0x400e8554 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio10_io17: IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 { + pinmux = <0x400e81d4 10 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio_mux4_io17: IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 { + pinmux = <0x400e81d4 5 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpt6_compare1: IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 { + pinmux = <0x400e81d4 4 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpspi2_pcs0: IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 { + pinmux = <0x400e81d4 6 0x400e85dc 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpuart3_rts_b: IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B { + pinmux = <0x400e81d4 3 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_usdhc2_data4: IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 { + pinmux = <0x400e81d4 0 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_enet_1g_tdata00: IOMUXC_GPIO_SD_B2_09_ENET_1G_TDATA00 { + pinmux = <0x400e81d8 2 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_flexspi1_a_data01: IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 { + pinmux = <0x400e81d8 1 0x400e8558 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio10_io18: IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 { + pinmux = <0x400e81d8 10 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio_mux4_io18: IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 { + pinmux = <0x400e81d8 5 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpt6_compare2: IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 { + pinmux = <0x400e81d8 4 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpspi2_sdo: IOMUXC_GPIO_SD_B2_09_LPSPI2_SDO { + pinmux = <0x400e81d8 6 0x400e85ec 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpuart5_cts_b: IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B { + pinmux = <0x400e81d8 3 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_usdhc2_data5: IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 { + pinmux = <0x400e81d8 0 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_enet_1g_tx_en: IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN { + pinmux = <0x400e81dc 2 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_flexspi1_a_data02: IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 { + pinmux = <0x400e81dc 1 0x400e855c 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio10_io19: IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 { + pinmux = <0x400e81dc 10 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio_mux4_io19: IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 { + pinmux = <0x400e81dc 5 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpt6_compare3: IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 { + pinmux = <0x400e81dc 4 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpspi2_sdi: IOMUXC_GPIO_SD_B2_10_LPSPI2_SDI { + pinmux = <0x400e81dc 6 0x400e85e8 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpuart5_rts_b: IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B { + pinmux = <0x400e81dc 3 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_usdhc2_data6: IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 { + pinmux = <0x400e81dc 0 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_ref_clk1: IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e81e0 3 0x400e84c4 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_tx_clk_io: IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e81e0 2 0x400e84e8 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_flexspi1_a_data03: IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 { + pinmux = <0x400e81e0 1 0x400e8560 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio10_io20: IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 { + pinmux = <0x400e81e0 10 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio_mux4_io20: IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 { + pinmux = <0x400e81e0 5 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpt6_clk: IOMUXC_GPIO_SD_B2_11_GPT6_CLK { + pinmux = <0x400e81e0 4 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_lpspi2_pcs1: IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 { + pinmux = <0x400e81e0 6 0x400e85e0 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_usdhc2_data7: IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 { + pinmux = <0x400e81e0 0 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03: IOMUXC_SNVS_GPIO_SNVS_00_DIG_GPIO13_IO03 { + pinmux = <0x40c9400c 5 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_snvs_lp_tamper00: IOMUXC_SNVS_GPIO_SNVS_00_DIG_SNVS_LP_TAMPER00 { + pinmux = <0x40c9400c 0 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04: IOMUXC_SNVS_GPIO_SNVS_01_DIG_GPIO13_IO04 { + pinmux = <0x40c94010 5 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_snvs_lp_tamper01: IOMUXC_SNVS_GPIO_SNVS_01_DIG_SNVS_LP_TAMPER01 { + pinmux = <0x40c94010 0 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05: IOMUXC_SNVS_GPIO_SNVS_02_DIG_GPIO13_IO05 { + pinmux = <0x40c94014 5 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_snvs_lp_tamper02: IOMUXC_SNVS_GPIO_SNVS_02_DIG_SNVS_LP_TAMPER02 { + pinmux = <0x40c94014 0 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06: IOMUXC_SNVS_GPIO_SNVS_03_DIG_GPIO13_IO06 { + pinmux = <0x40c94018 5 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_snvs_lp_tamper03: IOMUXC_SNVS_GPIO_SNVS_03_DIG_SNVS_LP_TAMPER03 { + pinmux = <0x40c94018 0 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07: IOMUXC_SNVS_GPIO_SNVS_04_DIG_GPIO13_IO07 { + pinmux = <0x40c9401c 5 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_snvs_lp_tamper04: IOMUXC_SNVS_GPIO_SNVS_04_DIG_SNVS_LP_TAMPER04 { + pinmux = <0x40c9401c 0 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08: IOMUXC_SNVS_GPIO_SNVS_05_DIG_GPIO13_IO08 { + pinmux = <0x40c94020 5 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_snvs_lp_tamper05: IOMUXC_SNVS_GPIO_SNVS_05_DIG_SNVS_LP_TAMPER05 { + pinmux = <0x40c94020 0 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09: IOMUXC_SNVS_GPIO_SNVS_06_DIG_GPIO13_IO09 { + pinmux = <0x40c94024 5 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_snvs_lp_tamper06: IOMUXC_SNVS_GPIO_SNVS_06_DIG_SNVS_LP_TAMPER06 { + pinmux = <0x40c94024 0 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10: IOMUXC_SNVS_GPIO_SNVS_07_DIG_GPIO13_IO10 { + pinmux = <0x40c94028 5 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_snvs_lp_tamper07: IOMUXC_SNVS_GPIO_SNVS_07_DIG_SNVS_LP_TAMPER07 { + pinmux = <0x40c94028 0 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11: IOMUXC_SNVS_GPIO_SNVS_08_DIG_GPIO13_IO11 { + pinmux = <0x40c9402c 5 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_snvs_lp_tamper08: IOMUXC_SNVS_GPIO_SNVS_08_DIG_SNVS_LP_TAMPER08 { + pinmux = <0x40c9402c 0 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12: IOMUXC_SNVS_GPIO_SNVS_09_DIG_GPIO13_IO12 { + pinmux = <0x40c94030 5 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_snvs_lp_tamper09: IOMUXC_SNVS_GPIO_SNVS_09_DIG_SNVS_LP_TAMPER09 { + pinmux = <0x40c94030 0 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_dig_src_reset_b: IOMUXC_SNVS_ONOFF_DIG_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x40c9403c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_gpio13_io01: IOMUXC_SNVS_PMIC_ON_REQ_DIG_GPIO13_IO01 { + pinmux = <0x40c94004 5 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_snvs_lp_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ { + pinmux = <0x40c94004 0 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_gpio13_io02: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_GPIO13_IO02 { + pinmux = <0x40c94008 5 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_pgmc_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_PGMC_PMIC_VSTBY_REQ { + pinmux = <0x40c94008 0 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_dig_src_por_b: IOMUXC_SNVS_POR_B_DIG_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x40c94038>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_dig_test_mode: IOMUXC_SNVS_TEST_MODE_DIG_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x40c94034>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_dig_gpio13_io00: IOMUXC_SNVS_WAKEUP_DIG_GPIO13_IO00 { + pinmux = <0x40c94000 5 0x0 0 0x40c94040>; + pin-snvs; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1172avm8a-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1172avm8a-pinctrl.dtsi new file mode 100644 index 000000000..4efb845d0 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1172avm8a-pinctrl.dtsi @@ -0,0 +1,6212 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1172AVM8A + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_00_acmp1_in1: IOMUXC_GPIO_AD_00_ACMP1_IN1 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_can2_tx: IOMUXC_GPIO_AD_00_CAN2_TX { + pinmux = <0x400e810c 1 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_enet_1g_1588_event1_in: IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN { + pinmux = <0x400e810c 2 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexio2_flexio00: IOMUXC_GPIO_AD_00_FLEXIO2_FLEXIO00 { + pinmux = <0x400e810c 8 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexpwm1_pwm0_a: IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A { + pinmux = <0x400e810c 4 0x400e8500 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexspi2_b_ss1_b: IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B { + pinmux = <0x400e810c 9 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio8_io31: IOMUXC_GPIO_AD_00_GPIO8_IO31 { + pinmux = <0x400e810c 10 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31_cm7: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31_CM7 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpt2_capture1: IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 { + pinmux = <0x400e810c 3 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_lpuart7_tx: IOMUXC_GPIO_AD_00_LPUART7_TX { + pinmux = <0x400e810c 6 0x400e8630 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_sim1_trxd: IOMUXC_GPIO_AD_00_SIM1_TRXD { + pinmux = <0x400e810c 0 0x400e869c 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_acmp1_in2: IOMUXC_GPIO_AD_01_ACMP1_IN2 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_can2_rx: IOMUXC_GPIO_AD_01_CAN2_RX { + pinmux = <0x400e8110 1 0x400e849c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_enet_1g_1588_event1_out: IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT { + pinmux = <0x400e8110 2 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexio2_flexio01: IOMUXC_GPIO_AD_01_FLEXIO2_FLEXIO01 { + pinmux = <0x400e8110 8 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexpwm1_pwm0_b: IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B { + pinmux = <0x400e8110 4 0x400e850c 1 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexspi2_a_ss1_b: IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B { + pinmux = <0x400e8110 9 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio9_io00: IOMUXC_GPIO_AD_01_GPIO9_IO00 { + pinmux = <0x400e8110 10 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00_cm7: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00_CM7 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpt2_capture2: IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 { + pinmux = <0x400e8110 3 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_lpuart7_rx: IOMUXC_GPIO_AD_01_LPUART7_RX { + pinmux = <0x400e8110 6 0x400e862c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_sim1_clk: IOMUXC_GPIO_AD_01_SIM1_CLK { + pinmux = <0x400e8110 0 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_acmp1_in3: IOMUXC_GPIO_AD_02_ACMP1_IN3 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_enet_1g_1588_event2_in: IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN { + pinmux = <0x400e8114 2 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexio2_flexio02: IOMUXC_GPIO_AD_02_FLEXIO2_FLEXIO02 { + pinmux = <0x400e8114 8 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexpwm1_pwm1_a: IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A { + pinmux = <0x400e8114 4 0x400e8504 1 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio9_io01: IOMUXC_GPIO_AD_02_GPIO9_IO01 { + pinmux = <0x400e8114 10 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01_cm7: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01_CM7 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpt2_compare1: IOMUXC_GPIO_AD_02_GPT2_COMPARE1 { + pinmux = <0x400e8114 3 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart7_cts_b: IOMUXC_GPIO_AD_02_LPUART7_CTS_B { + pinmux = <0x400e8114 1 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart8_tx: IOMUXC_GPIO_AD_02_LPUART8_TX { + pinmux = <0x400e8114 6 0x400e8638 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_sim1_rst_b: IOMUXC_GPIO_AD_02_SIM1_RST_B { + pinmux = <0x400e8114 0 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_video_mux_ext_dcic1: IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e8114 9 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_acmp1_in4: IOMUXC_GPIO_AD_03_ACMP1_IN4 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_enet_1g_1588_event2_out: IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT { + pinmux = <0x400e8118 2 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexio2_flexio03: IOMUXC_GPIO_AD_03_FLEXIO2_FLEXIO03 { + pinmux = <0x400e8118 8 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexpwm1_pwm1_b: IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B { + pinmux = <0x400e8118 4 0x400e8510 1 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio9_io02: IOMUXC_GPIO_AD_03_GPIO9_IO02 { + pinmux = <0x400e8118 10 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02_cm7: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02_CM7 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpt2_compare2: IOMUXC_GPIO_AD_03_GPT2_COMPARE2 { + pinmux = <0x400e8118 3 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart7_rts_b: IOMUXC_GPIO_AD_03_LPUART7_RTS_B { + pinmux = <0x400e8118 1 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart8_rx: IOMUXC_GPIO_AD_03_LPUART8_RX { + pinmux = <0x400e8118 6 0x400e8634 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_sim1_sven: IOMUXC_GPIO_AD_03_SIM1_SVEN { + pinmux = <0x400e8118 0 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_video_mux_ext_dcic2: IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8118 9 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_acmp2_in1: IOMUXC_GPIO_AD_04_ACMP2_IN1 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_enet_1g_1588_event3_in: IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN { + pinmux = <0x400e811c 2 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexio2_flexio04: IOMUXC_GPIO_AD_04_FLEXIO2_FLEXIO04 { + pinmux = <0x400e811c 8 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexpwm1_pwm2_a: IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A { + pinmux = <0x400e811c 4 0x400e8508 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio9_io03: IOMUXC_GPIO_AD_04_GPIO9_IO03 { + pinmux = <0x400e811c 10 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03_cm7: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03_CM7 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpt2_compare3: IOMUXC_GPIO_AD_04_GPT2_COMPARE3 { + pinmux = <0x400e811c 3 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_lpuart8_cts_b: IOMUXC_GPIO_AD_04_LPUART8_CTS_B { + pinmux = <0x400e811c 1 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_qtimer4_timer0: IOMUXC_GPIO_AD_04_QTIMER4_TIMER0 { + pinmux = <0x400e811c 9 0x400e8660 1 0x400e8360>; + pin-pue; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_sim1_pd: IOMUXC_GPIO_AD_04_SIM1_PD { + pinmux = <0x400e811c 0 0x400e86a0 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_wdog1_wdog_b: IOMUXC_GPIO_AD_04_WDOG1_WDOG_B { + pinmux = <0x400e811c 6 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_acmp2_in2: IOMUXC_GPIO_AD_05_ACMP2_IN2 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_enet_1g_1588_event3_out: IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT { + pinmux = <0x400e8120 2 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexio2_flexio05: IOMUXC_GPIO_AD_05_FLEXIO2_FLEXIO05 { + pinmux = <0x400e8120 8 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexpwm1_pwm2_b: IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B { + pinmux = <0x400e8120 4 0x400e8514 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio9_io04: IOMUXC_GPIO_AD_05_GPIO9_IO04 { + pinmux = <0x400e8120 10 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04_cm7: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04_CM7 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpt2_clk: IOMUXC_GPIO_AD_05_GPT2_CLK { + pinmux = <0x400e8120 3 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_lpuart8_rts_b: IOMUXC_GPIO_AD_05_LPUART8_RTS_B { + pinmux = <0x400e8120 1 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_qtimer4_timer1: IOMUXC_GPIO_AD_05_QTIMER4_TIMER1 { + pinmux = <0x400e8120 9 0x400e8664 1 0x400e8364>; + pin-pue; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_sim1_power_fail: IOMUXC_GPIO_AD_05_SIM1_POWER_FAIL { + pinmux = <0x400e8120 0 0x400e86a4 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_wdog2_wdog_b: IOMUXC_GPIO_AD_05_WDOG2_WDOG_B { + pinmux = <0x400e8120 6 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_adc1_ch0a: IOMUXC_GPIO_AD_06_ADC1_CH0A { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_can1_tx: IOMUXC_GPIO_AD_06_CAN1_TX { + pinmux = <0x400e8124 1 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_enet_1588_event1_in: IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN { + pinmux = <0x400e8124 6 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexio2_flexio06: IOMUXC_GPIO_AD_06_FLEXIO2_FLEXIO06 { + pinmux = <0x400e8124 8 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexpwm1_pwm0_x: IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X { + pinmux = <0x400e8124 11 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio9_io05: IOMUXC_GPIO_AD_06_GPIO9_IO05 { + pinmux = <0x400e8124 10 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05_cm7: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05_CM7 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpt3_capture1: IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 { + pinmux = <0x400e8124 3 0x400e8590 1 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_qtimer4_timer2: IOMUXC_GPIO_AD_06_QTIMER4_TIMER2 { + pinmux = <0x400e8124 9 0x400e8668 0 0x400e8368>; + pin-pue; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_sim2_trxd: IOMUXC_GPIO_AD_06_SIM2_TRXD { + pinmux = <0x400e8124 2 0x400e86a8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_usb_otg2_oc: IOMUXC_GPIO_AD_06_USB_OTG2_OC { + pinmux = <0x400e8124 0 0x400e86b8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_video_mux_csi_data15: IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 { + pinmux = <0x400e8124 4 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_adc1_ch0b: IOMUXC_GPIO_AD_07_ADC1_CH0B { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_can1_rx: IOMUXC_GPIO_AD_07_CAN1_RX { + pinmux = <0x400e8128 1 0x400e8498 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_enet_1588_event1_out: IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT { + pinmux = <0x400e8128 6 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexio2_flexio07: IOMUXC_GPIO_AD_07_FLEXIO2_FLEXIO07 { + pinmux = <0x400e8128 8 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexpwm1_pwm1_x: IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X { + pinmux = <0x400e8128 11 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio9_io06: IOMUXC_GPIO_AD_07_GPIO9_IO06 { + pinmux = <0x400e8128 10 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06_cm7: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06_CM7 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpt3_capture2: IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 { + pinmux = <0x400e8128 3 0x400e8594 1 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_qtimer4_timer3: IOMUXC_GPIO_AD_07_QTIMER4_TIMER3 { + pinmux = <0x400e8128 9 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e403c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_sim2_clk: IOMUXC_GPIO_AD_07_SIM2_CLK { + pinmux = <0x400e8128 2 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_usb_otg2_pwr: IOMUXC_GPIO_AD_07_USB_OTG2_PWR { + pinmux = <0x400e8128 0 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_video_mux_csi_data14: IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 { + pinmux = <0x400e8128 4 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_adc1_ch1a: IOMUXC_GPIO_AD_08_ADC1_CH1A { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_enet_1588_event2_in: IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN { + pinmux = <0x400e812c 6 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexio2_flexio08: IOMUXC_GPIO_AD_08_FLEXIO2_FLEXIO08 { + pinmux = <0x400e812c 8 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexpwm1_pwm2_x: IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X { + pinmux = <0x400e812c 11 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio9_io07: IOMUXC_GPIO_AD_08_GPIO9_IO07 { + pinmux = <0x400e812c 10 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07_cm7: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07_CM7 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpt3_compare1: IOMUXC_GPIO_AD_08_GPT3_COMPARE1 { + pinmux = <0x400e812c 3 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_lpi2c1_scl: IOMUXC_GPIO_AD_08_LPI2C1_SCL { + pinmux = <0x400e812c 1 0x400e85ac 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_sim2_rst_b: IOMUXC_GPIO_AD_08_SIM2_RST_B { + pinmux = <0x400e812c 2 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_usbphy2_otg_id: IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID { + pinmux = <0x400e812c 0 0x400e86c4 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_video_mux_csi_data13: IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 { + pinmux = <0x400e812c 4 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_adc1_ch1b: IOMUXC_GPIO_AD_09_ADC1_CH1B { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_enet_1588_event2_out: IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT { + pinmux = <0x400e8130 6 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexio2_flexio09: IOMUXC_GPIO_AD_09_FLEXIO2_FLEXIO09 { + pinmux = <0x400e8130 8 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexpwm1_pwm3_x: IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X { + pinmux = <0x400e8130 11 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio9_io08: IOMUXC_GPIO_AD_09_GPIO9_IO08 { + pinmux = <0x400e8130 10 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08_cm7: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08_CM7 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpt3_compare2: IOMUXC_GPIO_AD_09_GPT3_COMPARE2 { + pinmux = <0x400e8130 3 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_lpi2c1_sda: IOMUXC_GPIO_AD_09_LPI2C1_SDA { + pinmux = <0x400e8130 1 0x400e85b0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_sim2_sven: IOMUXC_GPIO_AD_09_SIM2_SVEN { + pinmux = <0x400e8130 2 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_usbphy1_otg_id: IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID { + pinmux = <0x400e8130 0 0x400e86c0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_video_mux_csi_data12: IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 { + pinmux = <0x400e8130 4 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_adc1_ch2a: IOMUXC_GPIO_AD_10_ADC1_CH2A { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_enet_1588_event3_in: IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN { + pinmux = <0x400e8134 6 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexio2_flexio10: IOMUXC_GPIO_AD_10_FLEXIO2_FLEXIO10 { + pinmux = <0x400e8134 8 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexpwm2_pwm0_x: IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X { + pinmux = <0x400e8134 11 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio9_io09: IOMUXC_GPIO_AD_10_GPIO9_IO09 { + pinmux = <0x400e8134 10 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09_cm7: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09_CM7 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpt3_compare3: IOMUXC_GPIO_AD_10_GPT3_COMPARE3 { + pinmux = <0x400e8134 3 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_lpi2c1_scls: IOMUXC_GPIO_AD_10_LPI2C1_SCLS { + pinmux = <0x400e8134 1 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_sim2_pd: IOMUXC_GPIO_AD_10_SIM2_PD { + pinmux = <0x400e8134 2 0x400e86ac 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_usb_otg1_pwr: IOMUXC_GPIO_AD_10_USB_OTG1_PWR { + pinmux = <0x400e8134 0 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_video_mux_csi_data11: IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 { + pinmux = <0x400e8134 4 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_adc1_ch2b: IOMUXC_GPIO_AD_11_ADC1_CH2B { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_enet_1588_event3_out: IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT { + pinmux = <0x400e8138 6 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexio2_flexio11: IOMUXC_GPIO_AD_11_FLEXIO2_FLEXIO11 { + pinmux = <0x400e8138 8 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexpwm2_pwm1_x: IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X { + pinmux = <0x400e8138 11 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio9_io10: IOMUXC_GPIO_AD_11_GPIO9_IO10 { + pinmux = <0x400e8138 10 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10_cm7: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10_CM7 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpt3_clk: IOMUXC_GPIO_AD_11_GPT3_CLK { + pinmux = <0x400e8138 3 0x400e8598 1 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_lpi2c1_sdas: IOMUXC_GPIO_AD_11_LPI2C1_SDAS { + pinmux = <0x400e8138 1 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_sim2_power_fail: IOMUXC_GPIO_AD_11_SIM2_POWER_FAIL { + pinmux = <0x400e8138 2 0x400e86b0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_usb_otg1_oc: IOMUXC_GPIO_AD_11_USB_OTG1_OC { + pinmux = <0x400e8138 0 0x400e86bc 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_video_mux_csi_data10: IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 { + pinmux = <0x400e8138 4 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc1_ch3a: IOMUXC_GPIO_AD_12_ADC1_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc2_ch3a: IOMUXC_GPIO_AD_12_ADC2_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_enet_tdata03: IOMUXC_GPIO_AD_12_ENET_TDATA03 { + pinmux = <0x400e813c 6 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_ewm_ewm_out_b: IOMUXC_GPIO_AD_12_EWM_EWM_OUT_B { + pinmux = <0x400e813c 9 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexio2_flexio12: IOMUXC_GPIO_AD_12_FLEXIO2_FLEXIO12 { + pinmux = <0x400e813c 8 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexpwm2_pwm2_x: IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X { + pinmux = <0x400e813c 11 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexspi1_b_data03: IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 { + pinmux = <0x400e813c 3 0x400e8570 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio9_io11: IOMUXC_GPIO_AD_12_GPIO9_IO11 { + pinmux = <0x400e813c 10 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11_cm7: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11_CM7 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpt1_capture1: IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 { + pinmux = <0x400e813c 2 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_lpi2c1_hreq: IOMUXC_GPIO_AD_12_LPI2C1_HREQ { + pinmux = <0x400e813c 1 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_spdif_lock: IOMUXC_GPIO_AD_12_SPDIF_LOCK { + pinmux = <0x400e813c 0 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_video_mux_csi_pixclk: IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK { + pinmux = <0x400e813c 4 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc1_ch3b: IOMUXC_GPIO_AD_13_ADC1_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc2_ch3b: IOMUXC_GPIO_AD_13_ADC2_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_enet_tdata02: IOMUXC_GPIO_AD_13_ENET_TDATA02 { + pinmux = <0x400e8140 6 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexio2_flexio13: IOMUXC_GPIO_AD_13_FLEXIO2_FLEXIO13 { + pinmux = <0x400e8140 8 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexpwm2_pwm3_x: IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X { + pinmux = <0x400e8140 11 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexspi1_b_data02: IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 { + pinmux = <0x400e8140 3 0x400e856c 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio9_io12: IOMUXC_GPIO_AD_13_GPIO9_IO12 { + pinmux = <0x400e8140 10 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12_cm7: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12_CM7 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpt1_capture2: IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 { + pinmux = <0x400e8140 2 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_pit1_trigger00: IOMUXC_GPIO_AD_13_PIT1_TRIGGER00 { + pinmux = <0x400e8140 1 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_spdif_sr_clk: IOMUXC_GPIO_AD_13_SPDIF_SR_CLK { + pinmux = <0x400e8140 0 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_video_mux_csi_mclk: IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK { + pinmux = <0x400e8140 4 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc1_ch4a: IOMUXC_GPIO_AD_14_ADC1_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc2_ch4a: IOMUXC_GPIO_AD_14_ADC2_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_ccm_enet_ref_clk_25m: IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8144 9 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_enet_rx_clk: IOMUXC_GPIO_AD_14_ENET_RX_CLK { + pinmux = <0x400e8144 6 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexio2_flexio14: IOMUXC_GPIO_AD_14_FLEXIO2_FLEXIO14 { + pinmux = <0x400e8144 8 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexpwm3_pwm0_x: IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X { + pinmux = <0x400e8144 11 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexspi1_b_data01: IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 { + pinmux = <0x400e8144 3 0x400e8568 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio9_io13: IOMUXC_GPIO_AD_14_GPIO9_IO13 { + pinmux = <0x400e8144 10 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13_cm7: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13_CM7 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpt1_compare1: IOMUXC_GPIO_AD_14_GPT1_COMPARE1 { + pinmux = <0x400e8144 2 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_spdif_ext_clk: IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK { + pinmux = <0x400e8144 0 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_video_mux_csi_vsync: IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC { + pinmux = <0x400e8144 4 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc1_ch4b: IOMUXC_GPIO_AD_15_ADC1_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc2_ch4b: IOMUXC_GPIO_AD_15_ADC2_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_enet_tx_er: IOMUXC_GPIO_AD_15_ENET_TX_ER { + pinmux = <0x400e8148 6 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexio2_flexio15: IOMUXC_GPIO_AD_15_FLEXIO2_FLEXIO15 { + pinmux = <0x400e8148 8 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexpwm3_pwm1_x: IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X { + pinmux = <0x400e8148 11 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexspi1_b_data00: IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 { + pinmux = <0x400e8148 3 0x400e8564 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio9_io14: IOMUXC_GPIO_AD_15_GPIO9_IO14 { + pinmux = <0x400e8148 10 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14_cm7: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14_CM7 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpt1_compare2: IOMUXC_GPIO_AD_15_GPT1_COMPARE2 { + pinmux = <0x400e8148 2 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_lpuart10_tx: IOMUXC_GPIO_AD_15_LPUART10_TX { + pinmux = <0x400e8148 1 0x400e8628 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_spdif_in: IOMUXC_GPIO_AD_15_SPDIF_IN { + pinmux = <0x400e8148 0 0x400e86b4 1 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_video_mux_csi_hsync: IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC { + pinmux = <0x400e8148 4 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc1_ch5a: IOMUXC_GPIO_AD_16_ADC1_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc2_ch5a: IOMUXC_GPIO_AD_16_ADC2_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_1g_mdc: IOMUXC_GPIO_AD_16_ENET_1G_MDC { + pinmux = <0x400e814c 9 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_rdata03: IOMUXC_GPIO_AD_16_ENET_RDATA03 { + pinmux = <0x400e814c 6 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexio2_flexio16: IOMUXC_GPIO_AD_16_FLEXIO2_FLEXIO16 { + pinmux = <0x400e814c 8 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexpwm3_pwm2_x: IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X { + pinmux = <0x400e814c 11 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexspi1_b_sclk: IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK { + pinmux = <0x400e814c 3 0x400e8578 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio9_io15: IOMUXC_GPIO_AD_16_GPIO9_IO15 { + pinmux = <0x400e814c 10 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15_cm7: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15_CM7 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpt1_compare3: IOMUXC_GPIO_AD_16_GPT1_COMPARE3 { + pinmux = <0x400e814c 2 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_lpuart10_rx: IOMUXC_GPIO_AD_16_LPUART10_RX { + pinmux = <0x400e814c 1 0x400e8624 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_spdif_out: IOMUXC_GPIO_AD_16_SPDIF_OUT { + pinmux = <0x400e814c 0 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_video_mux_csi_data09: IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 { + pinmux = <0x400e814c 4 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_acmp1_cmpo: IOMUXC_GPIO_AD_17_ACMP1_CMPO { + pinmux = <0x400e8150 1 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc1_ch5b: IOMUXC_GPIO_AD_17_ADC1_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc2_ch5b: IOMUXC_GPIO_AD_17_ADC2_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_1g_mdio: IOMUXC_GPIO_AD_17_ENET_1G_MDIO { + pinmux = <0x400e8150 9 0x400e84c8 2 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_rdata02: IOMUXC_GPIO_AD_17_ENET_RDATA02 { + pinmux = <0x400e8150 6 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexio2_flexio17: IOMUXC_GPIO_AD_17_FLEXIO2_FLEXIO17 { + pinmux = <0x400e8150 8 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexpwm3_pwm3_x: IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X { + pinmux = <0x400e8150 11 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexspi1_a_dqs: IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS { + pinmux = <0x400e8150 3 0x400e8550 1 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio9_io16: IOMUXC_GPIO_AD_17_GPIO9_IO16 { + pinmux = <0x400e8150 10 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16_cm7: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16_CM7 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpt1_clk: IOMUXC_GPIO_AD_17_GPT1_CLK { + pinmux = <0x400e8150 2 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_sai1_mclk: IOMUXC_GPIO_AD_17_SAI1_MCLK { + pinmux = <0x400e8150 0 0x400e866c 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_video_mux_csi_data08: IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 { + pinmux = <0x400e8150 4 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_acmp2_cmpo: IOMUXC_GPIO_AD_18_ACMP2_CMPO { + pinmux = <0x400e8154 1 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_adc2_ch0a: IOMUXC_GPIO_AD_18_ADC2_CH0A { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_enet_crs: IOMUXC_GPIO_AD_18_ENET_CRS { + pinmux = <0x400e8154 6 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexio2_flexio18: IOMUXC_GPIO_AD_18_FLEXIO2_FLEXIO18 { + pinmux = <0x400e8154 8 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexpwm4_pwm0_x: IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X { + pinmux = <0x400e8154 11 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexspi1_a_ss0_b: IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B { + pinmux = <0x400e8154 3 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio9_io17: IOMUXC_GPIO_AD_18_GPIO9_IO17 { + pinmux = <0x400e8154 10 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17_cm7: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17_CM7 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpi2c2_scl: IOMUXC_GPIO_AD_18_LPI2C2_SCL { + pinmux = <0x400e8154 9 0x400e85b4 1 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpspi1_pcs1: IOMUXC_GPIO_AD_18_LPSPI1_PCS1 { + pinmux = <0x400e8154 2 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_sai1_rx_sync: IOMUXC_GPIO_AD_18_SAI1_RX_SYNC { + pinmux = <0x400e8154 0 0x400e8678 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_video_mux_csi_data07: IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 { + pinmux = <0x400e8154 4 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_acmp3_cmpo: IOMUXC_GPIO_AD_19_ACMP3_CMPO { + pinmux = <0x400e8158 1 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_adc2_ch0b: IOMUXC_GPIO_AD_19_ADC2_CH0B { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_enet_col: IOMUXC_GPIO_AD_19_ENET_COL { + pinmux = <0x400e8158 6 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexio2_flexio19: IOMUXC_GPIO_AD_19_FLEXIO2_FLEXIO19 { + pinmux = <0x400e8158 8 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexpwm4_pwm1_x: IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X { + pinmux = <0x400e8158 11 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexspi1_a_sclk: IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK { + pinmux = <0x400e8158 3 0x400e8574 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio9_io18: IOMUXC_GPIO_AD_19_GPIO9_IO18 { + pinmux = <0x400e8158 10 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18_cm7: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18_CM7 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpi2c2_sda: IOMUXC_GPIO_AD_19_LPI2C2_SDA { + pinmux = <0x400e8158 9 0x400e85b8 1 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpspi1_pcs2: IOMUXC_GPIO_AD_19_LPSPI1_PCS2 { + pinmux = <0x400e8158 2 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_sai1_rx_bclk: IOMUXC_GPIO_AD_19_SAI1_RX_BCLK { + pinmux = <0x400e8158 0 0x400e8670 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_video_mux_csi_data06: IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 { + pinmux = <0x400e8158 4 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_acmp4_cmpo: IOMUXC_GPIO_AD_20_ACMP4_CMPO { + pinmux = <0x400e815c 1 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_adc2_ch1a: IOMUXC_GPIO_AD_20_ADC2_CH1A { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexio2_flexio20: IOMUXC_GPIO_AD_20_FLEXIO2_FLEXIO20 { + pinmux = <0x400e815c 8 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexpwm4_pwm2_x: IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X { + pinmux = <0x400e815c 11 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexspi1_a_data00: IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 { + pinmux = <0x400e815c 3 0x400e8554 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio9_io19: IOMUXC_GPIO_AD_20_GPIO9_IO19 { + pinmux = <0x400e815c 10 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19_cm7: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19_CM7 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_kpp_row07: IOMUXC_GPIO_AD_20_KPP_ROW07 { + pinmux = <0x400e815c 6 0x400e85a8 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_lpspi1_pcs3: IOMUXC_GPIO_AD_20_LPSPI1_PCS3 { + pinmux = <0x400e815c 2 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_sai1_rx_data00: IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 { + pinmux = <0x400e815c 0 0x400e8674 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_video_mux_csi_data05: IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 { + pinmux = <0x400e815c 4 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_adc2_ch1b: IOMUXC_GPIO_AD_21_ADC2_CH1B { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexio2_flexio21: IOMUXC_GPIO_AD_21_FLEXIO2_FLEXIO21 { + pinmux = <0x400e8160 8 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexpwm4_pwm3_x: IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X { + pinmux = <0x400e8160 11 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexspi1_a_data01: IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 { + pinmux = <0x400e8160 3 0x400e8558 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio9_io20: IOMUXC_GPIO_AD_21_GPIO9_IO20 { + pinmux = <0x400e8160 10 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20_cm7: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20_CM7 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_kpp_col07: IOMUXC_GPIO_AD_21_KPP_COL07 { + pinmux = <0x400e8160 6 0x400e85a0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_lpspi2_pcs1: IOMUXC_GPIO_AD_21_LPSPI2_PCS1 { + pinmux = <0x400e8160 2 0x400e85e0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_sai1_tx_data00: IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 { + pinmux = <0x400e8160 0 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_video_mux_csi_data04: IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 { + pinmux = <0x400e8160 4 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_adc2_ch2a: IOMUXC_GPIO_AD_22_ADC2_CH2A { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexio2_flexio22: IOMUXC_GPIO_AD_22_FLEXIO2_FLEXIO22 { + pinmux = <0x400e8164 8 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexspi1_a_data02: IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 { + pinmux = <0x400e8164 3 0x400e855c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio9_io21: IOMUXC_GPIO_AD_22_GPIO9_IO21 { + pinmux = <0x400e8164 10 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21_cm7: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21_CM7 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_kpp_row06: IOMUXC_GPIO_AD_22_KPP_ROW06 { + pinmux = <0x400e8164 6 0x400e85a4 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_lpspi2_pcs2: IOMUXC_GPIO_AD_22_LPSPI2_PCS2 { + pinmux = <0x400e8164 2 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_sai1_tx_bclk: IOMUXC_GPIO_AD_22_SAI1_TX_BCLK { + pinmux = <0x400e8164 0 0x400e867c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_video_mux_csi_data03: IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 { + pinmux = <0x400e8164 4 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_adc2_ch2b: IOMUXC_GPIO_AD_23_ADC2_CH2B { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexio2_flexio23: IOMUXC_GPIO_AD_23_FLEXIO2_FLEXIO23 { + pinmux = <0x400e8168 8 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexspi1_a_data03: IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 { + pinmux = <0x400e8168 3 0x400e8560 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio9_io22: IOMUXC_GPIO_AD_23_GPIO9_IO22 { + pinmux = <0x400e8168 10 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22_cm7: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22_CM7 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_kpp_col06: IOMUXC_GPIO_AD_23_KPP_COL06 { + pinmux = <0x400e8168 6 0x400e859c 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_lpspi2_pcs3: IOMUXC_GPIO_AD_23_LPSPI2_PCS3 { + pinmux = <0x400e8168 2 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_sai1_tx_sync: IOMUXC_GPIO_AD_23_SAI1_TX_SYNC { + pinmux = <0x400e8168 0 0x400e8680 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_video_mux_csi_data02: IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 { + pinmux = <0x400e8168 4 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_adc2_ch6a: IOMUXC_GPIO_AD_24_ADC2_CH6A { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_enet_rx_en: IOMUXC_GPIO_AD_24_ENET_RX_EN { + pinmux = <0x400e816c 3 0x400e84b8 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexio2_flexio24: IOMUXC_GPIO_AD_24_FLEXIO2_FLEXIO24 { + pinmux = <0x400e816c 8 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexpwm2_pwm0_a: IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A { + pinmux = <0x400e816c 4 0x400e8518 1 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio9_io23: IOMUXC_GPIO_AD_24_GPIO9_IO23 { + pinmux = <0x400e816c 10 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23_cm7: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23_CM7 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_kpp_row05: IOMUXC_GPIO_AD_24_KPP_ROW05 { + pinmux = <0x400e816c 6 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpi2c4_scl: IOMUXC_GPIO_AD_24_LPI2C4_SCL { + pinmux = <0x400e816c 9 0x400e85c4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpspi2_sck: IOMUXC_GPIO_AD_24_LPSPI2_SCK { + pinmux = <0x400e816c 1 0x400e85e4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpuart1_tx: IOMUXC_GPIO_AD_24_LPUART1_TX { + pinmux = <0x400e816c 0 0x400e8620 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_video_mux_csi_data00: IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 { + pinmux = <0x400e816c 2 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_adc2_ch6b: IOMUXC_GPIO_AD_25_ADC2_CH6B { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_enet_rx_er: IOMUXC_GPIO_AD_25_ENET_RX_ER { + pinmux = <0x400e8170 3 0x400e84bc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexio2_flexio25: IOMUXC_GPIO_AD_25_FLEXIO2_FLEXIO25 { + pinmux = <0x400e8170 8 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexpwm2_pwm0_b: IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B { + pinmux = <0x400e8170 4 0x400e8524 1 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio9_io24: IOMUXC_GPIO_AD_25_GPIO9_IO24 { + pinmux = <0x400e8170 10 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24_cm7: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24_CM7 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_kpp_col05: IOMUXC_GPIO_AD_25_KPP_COL05 { + pinmux = <0x400e8170 6 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpi2c4_sda: IOMUXC_GPIO_AD_25_LPI2C4_SDA { + pinmux = <0x400e8170 9 0x400e85c8 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpspi2_pcs0: IOMUXC_GPIO_AD_25_LPSPI2_PCS0 { + pinmux = <0x400e8170 1 0x400e85dc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpuart1_rx: IOMUXC_GPIO_AD_25_LPUART1_RX { + pinmux = <0x400e8170 0 0x400e861c 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_video_mux_csi_data01: IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 { + pinmux = <0x400e8170 2 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_acmp2_in3: IOMUXC_GPIO_AD_26_ACMP2_IN3 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_enet_rdata00: IOMUXC_GPIO_AD_26_ENET_RDATA00 { + pinmux = <0x400e8174 3 0x400e84b0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexio2_flexio26: IOMUXC_GPIO_AD_26_FLEXIO2_FLEXIO26 { + pinmux = <0x400e8174 8 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexpwm2_pwm1_a: IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A { + pinmux = <0x400e8174 4 0x400e851c 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio9_io25: IOMUXC_GPIO_AD_26_GPIO9_IO25 { + pinmux = <0x400e8174 10 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25_cm7: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25_CM7 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_kpp_row04: IOMUXC_GPIO_AD_26_KPP_ROW04 { + pinmux = <0x400e8174 6 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpspi2_sdo: IOMUXC_GPIO_AD_26_LPSPI2_SDO { + pinmux = <0x400e8174 1 0x400e85ec 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpuart1_cts_b: IOMUXC_GPIO_AD_26_LPUART1_CTS_B { + pinmux = <0x400e8174 0 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_semc_csx01: IOMUXC_GPIO_AD_26_SEMC_CSX01 { + pinmux = <0x400e8174 2 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_usdhc2_cd_b: IOMUXC_GPIO_AD_26_USDHC2_CD_B { + pinmux = <0x400e8174 11 0x400e86d0 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_acmp2_in4: IOMUXC_GPIO_AD_27_ACMP2_IN4 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_enet_rdata01: IOMUXC_GPIO_AD_27_ENET_RDATA01 { + pinmux = <0x400e8178 3 0x400e84b4 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexio2_flexio27: IOMUXC_GPIO_AD_27_FLEXIO2_FLEXIO27 { + pinmux = <0x400e8178 8 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexpwm2_pwm1_b: IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B { + pinmux = <0x400e8178 4 0x400e8528 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio9_io26: IOMUXC_GPIO_AD_27_GPIO9_IO26 { + pinmux = <0x400e8178 10 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26_cm7: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26_CM7 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_kpp_col04: IOMUXC_GPIO_AD_27_KPP_COL04 { + pinmux = <0x400e8178 6 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpspi2_sdi: IOMUXC_GPIO_AD_27_LPSPI2_SDI { + pinmux = <0x400e8178 1 0x400e85e8 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpuart1_rts_b: IOMUXC_GPIO_AD_27_LPUART1_RTS_B { + pinmux = <0x400e8178 0 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_semc_csx02: IOMUXC_GPIO_AD_27_SEMC_CSX02 { + pinmux = <0x400e8178 2 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_usdhc2_wp: IOMUXC_GPIO_AD_27_USDHC2_WP { + pinmux = <0x400e8178 11 0x400e86d4 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_acmp3_in1: IOMUXC_GPIO_AD_28_ACMP3_IN1 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_enet_tx_en: IOMUXC_GPIO_AD_28_ENET_TX_EN { + pinmux = <0x400e817c 3 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexio2_flexio28: IOMUXC_GPIO_AD_28_FLEXIO2_FLEXIO28 { + pinmux = <0x400e817c 8 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexpwm2_pwm2_a: IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A { + pinmux = <0x400e817c 4 0x400e8520 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio9_io27: IOMUXC_GPIO_AD_28_GPIO9_IO27 { + pinmux = <0x400e817c 10 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27_cm7: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27_CM7 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_kpp_row03: IOMUXC_GPIO_AD_28_KPP_ROW03 { + pinmux = <0x400e817c 6 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpspi1_sck: IOMUXC_GPIO_AD_28_LPSPI1_SCK { + pinmux = <0x400e817c 0 0x400e85d0 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpuart5_tx: IOMUXC_GPIO_AD_28_LPUART5_TX { + pinmux = <0x400e817c 1 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_semc_csx03: IOMUXC_GPIO_AD_28_SEMC_CSX03 { + pinmux = <0x400e817c 2 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_usdhc2_vselect: IOMUXC_GPIO_AD_28_USDHC2_VSELECT { + pinmux = <0x400e817c 11 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_video_mux_ext_dcic1: IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e817c 9 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_acmp3_in2: IOMUXC_GPIO_AD_29_ACMP3_IN2 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_ref_clk: IOMUXC_GPIO_AD_29_ENET_REF_CLK { + pinmux = <0x400e8180 2 0x400e84a8 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_tx_clk: IOMUXC_GPIO_AD_29_ENET_TX_CLK { + pinmux = <0x400e8180 3 0x400e84c0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexio2_flexio29: IOMUXC_GPIO_AD_29_FLEXIO2_FLEXIO29 { + pinmux = <0x400e8180 8 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexpwm2_pwm2_b: IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B { + pinmux = <0x400e8180 4 0x400e852c 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio9_io28: IOMUXC_GPIO_AD_29_GPIO9_IO28 { + pinmux = <0x400e8180 10 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28_cm7: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28_CM7 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_kpp_col03: IOMUXC_GPIO_AD_29_KPP_COL03 { + pinmux = <0x400e8180 6 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpspi1_pcs0: IOMUXC_GPIO_AD_29_LPSPI1_PCS0 { + pinmux = <0x400e8180 0 0x400e85cc 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpuart5_rx: IOMUXC_GPIO_AD_29_LPUART5_RX { + pinmux = <0x400e8180 1 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_usdhc2_reset_b: IOMUXC_GPIO_AD_29_USDHC2_RESET_B { + pinmux = <0x400e8180 11 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_video_mux_ext_dcic2: IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8180 9 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_acmp3_in3: IOMUXC_GPIO_AD_30_ACMP3_IN3 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_can2_tx: IOMUXC_GPIO_AD_30_CAN2_TX { + pinmux = <0x400e8184 2 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_enet_tdata00: IOMUXC_GPIO_AD_30_ENET_TDATA00 { + pinmux = <0x400e8184 3 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_flexio2_flexio30: IOMUXC_GPIO_AD_30_FLEXIO2_FLEXIO30 { + pinmux = <0x400e8184 8 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio9_io29: IOMUXC_GPIO_AD_30_GPIO9_IO29 { + pinmux = <0x400e8184 10 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29_cm7: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29_CM7 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_kpp_row02: IOMUXC_GPIO_AD_30_KPP_ROW02 { + pinmux = <0x400e8184 6 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpspi1_sdo: IOMUXC_GPIO_AD_30_LPSPI1_SDO { + pinmux = <0x400e8184 0 0x400e85d8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpuart3_tx: IOMUXC_GPIO_AD_30_LPUART3_TX { + pinmux = <0x400e8184 4 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_usb_otg2_oc: IOMUXC_GPIO_AD_30_USB_OTG2_OC { + pinmux = <0x400e8184 1 0x400e86b8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_AD_30_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e8184 9 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_acmp3_in4: IOMUXC_GPIO_AD_31_ACMP3_IN4 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_can2_rx: IOMUXC_GPIO_AD_31_CAN2_RX { + pinmux = <0x400e8188 2 0x400e849c 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_enet_tdata01: IOMUXC_GPIO_AD_31_ENET_TDATA01 { + pinmux = <0x400e8188 3 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_flexio2_flexio31: IOMUXC_GPIO_AD_31_FLEXIO2_FLEXIO31 { + pinmux = <0x400e8188 8 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio9_io30: IOMUXC_GPIO_AD_31_GPIO9_IO30 { + pinmux = <0x400e8188 10 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30_cm7: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30_CM7 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_kpp_col02: IOMUXC_GPIO_AD_31_KPP_COL02 { + pinmux = <0x400e8188 6 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpspi1_sdi: IOMUXC_GPIO_AD_31_LPSPI1_SDI { + pinmux = <0x400e8188 0 0x400e85d4 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpuart3_rx: IOMUXC_GPIO_AD_31_LPUART3_RX { + pinmux = <0x400e8188 4 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_usb_otg2_pwr: IOMUXC_GPIO_AD_31_USB_OTG2_PWR { + pinmux = <0x400e8188 1 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_AD_31_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8188 9 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_acmp4_in1: IOMUXC_GPIO_AD_32_ACMP4_IN1 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_1g_mdc: IOMUXC_GPIO_AD_32_ENET_1G_MDC { + pinmux = <0x400e818c 9 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_mdc: IOMUXC_GPIO_AD_32_ENET_MDC { + pinmux = <0x400e818c 3 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio9_io31: IOMUXC_GPIO_AD_32_GPIO9_IO31 { + pinmux = <0x400e818c 10 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31_cm7: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31_CM7 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_kpp_row01: IOMUXC_GPIO_AD_32_KPP_ROW01 { + pinmux = <0x400e818c 6 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpi2c1_scl: IOMUXC_GPIO_AD_32_LPI2C1_SCL { + pinmux = <0x400e818c 0 0x400e85ac 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpuart10_tx: IOMUXC_GPIO_AD_32_LPUART10_TX { + pinmux = <0x400e818c 8 0x400e8628 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_pgmc_pmic_ready: IOMUXC_GPIO_AD_32_PGMC_PMIC_READY { + pinmux = <0x400e818c 2 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usbphy2_otg_id: IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID { + pinmux = <0x400e818c 1 0x400e86c4 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usdhc1_cd_b: IOMUXC_GPIO_AD_32_USDHC1_CD_B { + pinmux = <0x400e818c 4 0x400e86c8 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_acmp4_in2: IOMUXC_GPIO_AD_33_ACMP4_IN2 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_1g_mdio: IOMUXC_GPIO_AD_33_ENET_1G_MDIO { + pinmux = <0x400e8190 9 0x400e84c8 3 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_mdio: IOMUXC_GPIO_AD_33_ENET_MDIO { + pinmux = <0x400e8190 3 0x400e84ac 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio10_io00: IOMUXC_GPIO_AD_33_GPIO10_IO00 { + pinmux = <0x400e8190 10 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio_mux4_io00: IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_kpp_col01: IOMUXC_GPIO_AD_33_KPP_COL01 { + pinmux = <0x400e8190 6 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpi2c1_sda: IOMUXC_GPIO_AD_33_LPI2C1_SDA { + pinmux = <0x400e8190 0 0x400e85b0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpuart10_rx: IOMUXC_GPIO_AD_33_LPUART10_RX { + pinmux = <0x400e8190 8 0x400e8624 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usbphy1_otg_id: IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID { + pinmux = <0x400e8190 1 0x400e86c0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usdhc1_wp: IOMUXC_GPIO_AD_33_USDHC1_WP { + pinmux = <0x400e8190 4 0x400e86cc 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_in17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_IN17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_inout17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_acmp4_in3: IOMUXC_GPIO_AD_34_ACMP4_IN3 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN { + pinmux = <0x400e8194 3 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1g_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN { + pinmux = <0x400e8194 0 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio10_io01: IOMUXC_GPIO_AD_34_GPIO10_IO01 { + pinmux = <0x400e8194 10 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio_mux4_io01: IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_kpp_row00: IOMUXC_GPIO_AD_34_KPP_ROW00 { + pinmux = <0x400e8194 6 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_lpuart10_cts_b: IOMUXC_GPIO_AD_34_LPUART10_CTS_B { + pinmux = <0x400e8194 8 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usb_otg1_pwr: IOMUXC_GPIO_AD_34_USB_OTG1_PWR { + pinmux = <0x400e8194 1 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usdhc1_vselect: IOMUXC_GPIO_AD_34_USDHC1_VSELECT { + pinmux = <0x400e8194 4 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_wdog1_wdog_any: IOMUXC_GPIO_AD_34_WDOG1_WDOG_ANY { + pinmux = <0x400e8194 9 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_in18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_IN18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_inout18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_acmp4_in4: IOMUXC_GPIO_AD_35_ACMP4_IN4 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT { + pinmux = <0x400e8198 3 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1g_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT { + pinmux = <0x400e8198 0 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_flexspi1_b_ss1_b: IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B { + pinmux = <0x400e8198 9 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio10_io02: IOMUXC_GPIO_AD_35_GPIO10_IO02 { + pinmux = <0x400e8198 10 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio_mux4_io02: IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_kpp_col00: IOMUXC_GPIO_AD_35_KPP_COL00 { + pinmux = <0x400e8198 6 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_lpuart10_rts_b: IOMUXC_GPIO_AD_35_LPUART10_RTS_B { + pinmux = <0x400e8198 8 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usb_otg1_oc: IOMUXC_GPIO_AD_35_USB_OTG1_OC { + pinmux = <0x400e8198 1 0x400e86bc 1 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usdhc1_reset_b: IOMUXC_GPIO_AD_35_USDHC1_RESET_B { + pinmux = <0x400e8198 4 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_in19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_IN19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_inout19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_INOUT19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_enet_1g_rx_en: IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN { + pinmux = <0x400e81e4 1 0x400e84e0 2 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio10_io21: IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 { + pinmux = <0x400e81e4 10 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio_mux4_io21: IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 { + pinmux = <0x400e81e4 5 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_qtimer1_timer0: IOMUXC_GPIO_DISP_B1_00_QTIMER1_TIMER0 { + pinmux = <0x400e81e4 3 0x400e863c 2 0x400e8428>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_video_mux_lcdif_clk: IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK { + pinmux = <0x400e81e4 0 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_in26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_IN26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_inout26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_clk: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK { + pinmux = <0x400e81e8 1 0x400e84cc 2 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_er: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER { + pinmux = <0x400e81e8 2 0x400e84e4 1 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio10_io22: IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 { + pinmux = <0x400e81e8 10 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio_mux4_io22: IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 { + pinmux = <0x400e81e8 5 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_qtimer1_timer1: IOMUXC_GPIO_DISP_B1_01_QTIMER1_TIMER1 { + pinmux = <0x400e81e8 3 0x400e8640 2 0x400e842c>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_video_mux_lcdif_enable: IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE { + pinmux = <0x400e81e8 0 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_in27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_IN27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_inout27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_enet_1g_rdata00: IOMUXC_GPIO_DISP_B1_02_ENET_1G_RDATA00 { + pinmux = <0x400e81ec 1 0x400e84d0 2 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio10_io23: IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 { + pinmux = <0x400e81ec 10 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio_mux4_io23: IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 { + pinmux = <0x400e81ec 5 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpi2c3_scl: IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL { + pinmux = <0x400e81ec 2 0x400e85bc 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpuart1_tx: IOMUXC_GPIO_DISP_B1_02_LPUART1_TX { + pinmux = <0x400e81ec 9 0x400e8620 1 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_qtimer1_timer2: IOMUXC_GPIO_DISP_B1_02_QTIMER1_TIMER2 { + pinmux = <0x400e81ec 3 0x400e8644 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_video_mux_lcdif_hsync: IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC { + pinmux = <0x400e81ec 0 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_in28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_IN28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_inout28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_enet_1g_rdata01: IOMUXC_GPIO_DISP_B1_03_ENET_1G_RDATA01 { + pinmux = <0x400e81f0 1 0x400e84d4 2 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio10_io24: IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 { + pinmux = <0x400e81f0 10 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio_mux4_io24: IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 { + pinmux = <0x400e81f0 5 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpi2c3_sda: IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA { + pinmux = <0x400e81f0 2 0x400e85c0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpuart1_rx: IOMUXC_GPIO_DISP_B1_03_LPUART1_RX { + pinmux = <0x400e81f0 9 0x400e861c 1 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_qtimer2_timer0: IOMUXC_GPIO_DISP_B1_03_QTIMER2_TIMER0 { + pinmux = <0x400e81f0 3 0x400e8648 2 0x400e8434>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_video_mux_lcdif_vsync: IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC { + pinmux = <0x400e81f0 0 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_in29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_IN29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_inout29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_enet_1g_rdata02: IOMUXC_GPIO_DISP_B1_04_ENET_1G_RDATA02 { + pinmux = <0x400e81f4 1 0x400e84d8 2 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio10_io25: IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 { + pinmux = <0x400e81f4 10 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio_mux4_io25: IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 { + pinmux = <0x400e81f4 5 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpspi3_sck: IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK { + pinmux = <0x400e81f4 9 0x400e8600 1 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpuart4_rx: IOMUXC_GPIO_DISP_B1_04_LPUART4_RX { + pinmux = <0x400e81f4 2 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_qtimer2_timer1: IOMUXC_GPIO_DISP_B1_04_QTIMER2_TIMER1 { + pinmux = <0x400e81f4 3 0x400e864c 2 0x400e8438>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_video_mux_lcdif_data00: IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 { + pinmux = <0x400e81f4 0 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_in30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_IN30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_inout30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_enet_1g_rdata03: IOMUXC_GPIO_DISP_B1_05_ENET_1G_RDATA03 { + pinmux = <0x400e81f8 1 0x400e84dc 2 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio10_io26: IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 { + pinmux = <0x400e81f8 10 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio_mux4_io26: IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 { + pinmux = <0x400e81f8 5 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpspi3_sdi: IOMUXC_GPIO_DISP_B1_05_LPSPI3_SDI { + pinmux = <0x400e81f8 9 0x400e8604 1 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpuart4_cts_b: IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B { + pinmux = <0x400e81f8 2 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_qtimer2_timer2: IOMUXC_GPIO_DISP_B1_05_QTIMER2_TIMER2 { + pinmux = <0x400e81f8 3 0x400e8650 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_video_mux_lcdif_data01: IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 { + pinmux = <0x400e81f8 0 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_in31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_IN31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_inout31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_enet_1g_tdata03: IOMUXC_GPIO_DISP_B1_06_ENET_1G_TDATA03 { + pinmux = <0x400e81fc 1 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio10_io27: IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 { + pinmux = <0x400e81fc 10 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio_mux4_io27: IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 { + pinmux = <0x400e81fc 5 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpspi3_sdo: IOMUXC_GPIO_DISP_B1_06_LPSPI3_SDO { + pinmux = <0x400e81fc 9 0x400e8608 1 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpuart4_tx: IOMUXC_GPIO_DISP_B1_06_LPUART4_TX { + pinmux = <0x400e81fc 2 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_qtimer3_timer0: IOMUXC_GPIO_DISP_B1_06_QTIMER3_TIMER0 { + pinmux = <0x400e81fc 3 0x400e8654 2 0x400e8440>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_src_bt_cfg00: IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 { + pinmux = <0x400e81fc 6 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_video_mux_lcdif_data02: IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 { + pinmux = <0x400e81fc 0 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_in32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_IN32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_inout32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_enet_1g_tdata02: IOMUXC_GPIO_DISP_B1_07_ENET_1G_TDATA02 { + pinmux = <0x400e8200 1 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio10_io28: IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 { + pinmux = <0x400e8200 10 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio_mux4_io28: IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 { + pinmux = <0x400e8200 5 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpspi3_pcs0: IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 { + pinmux = <0x400e8200 9 0x400e85f0 1 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpuart4_rts_b: IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B { + pinmux = <0x400e8200 2 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_qtimer3_timer1: IOMUXC_GPIO_DISP_B1_07_QTIMER3_TIMER1 { + pinmux = <0x400e8200 3 0x400e8658 2 0x400e8444>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_src_bt_cfg01: IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 { + pinmux = <0x400e8200 6 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_video_mux_lcdif_data03: IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 { + pinmux = <0x400e8200 0 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_in33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_IN33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_inout33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_enet_1g_tdata01: IOMUXC_GPIO_DISP_B1_08_ENET_1G_TDATA01 { + pinmux = <0x400e8204 1 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio10_io29: IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 { + pinmux = <0x400e8204 10 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio_mux4_io29: IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 { + pinmux = <0x400e8204 5 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_lpspi3_pcs1: IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 { + pinmux = <0x400e8204 9 0x400e85f4 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_qtimer3_timer2: IOMUXC_GPIO_DISP_B1_08_QTIMER3_TIMER2 { + pinmux = <0x400e8204 3 0x400e865c 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_src_bt_cfg02: IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 { + pinmux = <0x400e8204 6 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_usdhc1_cd_b: IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B { + pinmux = <0x400e8204 2 0x400e86c8 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_video_mux_lcdif_data04: IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 { + pinmux = <0x400e8204 0 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_in34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_IN34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_inout34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_enet_1g_tdata00: IOMUXC_GPIO_DISP_B1_09_ENET_1G_TDATA00 { + pinmux = <0x400e8208 1 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio10_io30: IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 { + pinmux = <0x400e8208 10 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio_mux4_io30: IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 { + pinmux = <0x400e8208 5 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_lpspi3_pcs2: IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 { + pinmux = <0x400e8208 9 0x400e85f8 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_qtimer4_timer0: IOMUXC_GPIO_DISP_B1_09_QTIMER4_TIMER0 { + pinmux = <0x400e8208 3 0x400e8660 2 0x400e844c>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_src_bt_cfg03: IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 { + pinmux = <0x400e8208 6 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_usdhc1_wp: IOMUXC_GPIO_DISP_B1_09_USDHC1_WP { + pinmux = <0x400e8208 2 0x400e86cc 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_video_mux_lcdif_data05: IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 { + pinmux = <0x400e8208 0 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_in35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_IN35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_inout35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_enet_1g_tx_en: IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN { + pinmux = <0x400e820c 1 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio10_io31: IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 { + pinmux = <0x400e820c 10 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio_mux4_io31: IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 { + pinmux = <0x400e820c 5 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_lpspi3_pcs3: IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 { + pinmux = <0x400e820c 9 0x400e85fc 1 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_qtimer4_timer1: IOMUXC_GPIO_DISP_B1_10_QTIMER4_TIMER1 { + pinmux = <0x400e820c 3 0x400e8664 2 0x400e8450>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_src_bt_cfg04: IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 { + pinmux = <0x400e820c 6 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_usdhc1_reset_b: IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B { + pinmux = <0x400e820c 2 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_video_mux_lcdif_data06: IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 { + pinmux = <0x400e820c 0 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_in36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_IN36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_inout36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_INOUT36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e8210 2 0x400e84c4 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_tx_clk_io: IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e8210 1 0x400e84e8 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio11_io00: IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 { + pinmux = <0x400e8210 10 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio_mux5_io00: IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 { + pinmux = <0x400e8210 5 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_qtimer4_timer2: IOMUXC_GPIO_DISP_B1_11_QTIMER4_TIMER2 { + pinmux = <0x400e8210 3 0x400e8668 1 0x400e8454>; + pin-pdrv; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_src_bt_cfg05: IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 { + pinmux = <0x400e8210 6 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_video_mux_lcdif_data07: IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 { + pinmux = <0x400e8210 0 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_in37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_IN37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_inout37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_INOUT37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_enet_1g_tx_er: IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER { + pinmux = <0x400e8214 3 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio11_io01: IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 { + pinmux = <0x400e8214 10 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio_mux5_io01: IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 { + pinmux = <0x400e8214 5 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_mqs_right: IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT { + pinmux = <0x400e8214 2 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_rx_data01: IOMUXC_GPIO_DISP_B2_00_SAI1_RX_DATA01 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_tx_data03: IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_src_bt_cfg06: IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 { + pinmux = <0x400e8214 6 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_video_mux_lcdif_data08: IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 { + pinmux = <0x400e8214 0 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_00_WDOG1_WDOG_B { + pinmux = <0x400e8214 1 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ccm_enet_ref_clk_25m: IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8218 9 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ewm_ewm_out_b: IOMUXC_GPIO_DISP_B2_01_EWM_EWM_OUT_B { + pinmux = <0x400e8218 8 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio11_io02: IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 { + pinmux = <0x400e8218 10 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio_mux5_io02: IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 { + pinmux = <0x400e8218 5 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_mqs_left: IOMUXC_GPIO_DISP_B2_01_MQS_LEFT { + pinmux = <0x400e8218 2 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_rx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_RX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_tx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_src_bt_cfg07: IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 { + pinmux = <0x400e8218 6 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_usdhc1_vselect: IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT { + pinmux = <0x400e8218 1 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_video_mux_lcdif_data09: IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 { + pinmux = <0x400e8218 0 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_01_WDOG2_WDOG_B { + pinmux = <0x400e8218 3 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_arm_trace00: IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 { + pinmux = <0x400e821c 3 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_enet_tdata00: IOMUXC_GPIO_DISP_B2_02_ENET_TDATA00 { + pinmux = <0x400e821c 1 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio11_io03: IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 { + pinmux = <0x400e821c 10 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio_mux5_io03: IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 { + pinmux = <0x400e821c 5 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_pit1_trigger03: IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER03 { + pinmux = <0x400e821c 2 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_rx_data03: IOMUXC_GPIO_DISP_B2_02_SAI1_RX_DATA03 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_tx_data01: IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_src_bt_cfg08: IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 { + pinmux = <0x400e821c 6 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_video_mux_lcdif_data10: IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 { + pinmux = <0x400e821c 0 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_arm_trace01: IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 { + pinmux = <0x400e8220 3 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_enet_tdata01: IOMUXC_GPIO_DISP_B2_03_ENET_TDATA01 { + pinmux = <0x400e8220 1 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio11_io04: IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 { + pinmux = <0x400e8220 10 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio_mux5_io04: IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 { + pinmux = <0x400e8220 5 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_pit1_trigger02: IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER02 { + pinmux = <0x400e8220 2 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_sai1_mclk: IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK { + pinmux = <0x400e8220 4 0x400e866c 1 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_src_bt_cfg09: IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 { + pinmux = <0x400e8220 6 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_video_mux_lcdif_data11: IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 { + pinmux = <0x400e8220 0 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_arm_trace02: IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 { + pinmux = <0x400e8224 3 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_enet_tx_en: IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN { + pinmux = <0x400e8224 1 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio11_io05: IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 { + pinmux = <0x400e8224 10 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio_mux5_io05: IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 { + pinmux = <0x400e8224 5 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_pit1_trigger01: IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER01 { + pinmux = <0x400e8224 2 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_sai1_rx_sync: IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC { + pinmux = <0x400e8224 4 0x400e8678 1 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_src_bt_cfg10: IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 { + pinmux = <0x400e8224 6 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_video_mux_lcdif_data12: IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 { + pinmux = <0x400e8224 0 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_arm_trace03: IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 { + pinmux = <0x400e8228 3 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_ref_clk: IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK { + pinmux = <0x400e8228 2 0x400e84a8 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_tx_clk: IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK { + pinmux = <0x400e8228 1 0x400e84c0 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio11_io06: IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 { + pinmux = <0x400e8228 10 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio_mux5_io06: IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 { + pinmux = <0x400e8228 5 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_sai1_rx_bclk: IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK { + pinmux = <0x400e8228 4 0x400e8670 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_src_bt_cfg11: IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 { + pinmux = <0x400e8228 6 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_video_mux_lcdif_data13: IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 { + pinmux = <0x400e8228 0 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_arm_trace_clk: IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK { + pinmux = <0x400e822c 3 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_enet_rdata00: IOMUXC_GPIO_DISP_B2_06_ENET_RDATA00 { + pinmux = <0x400e822c 1 0x400e84b0 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio11_io07: IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 { + pinmux = <0x400e822c 10 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio_mux5_io07: IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 { + pinmux = <0x400e822c 5 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_lpuart7_tx: IOMUXC_GPIO_DISP_B2_06_LPUART7_TX { + pinmux = <0x400e822c 2 0x400e8630 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_sai1_rx_data00: IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 { + pinmux = <0x400e822c 4 0x400e8674 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_video_mux_lcdif_data14: IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 { + pinmux = <0x400e822c 0 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_arm_trace_swo: IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO { + pinmux = <0x400e8230 3 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_enet_rdata01: IOMUXC_GPIO_DISP_B2_07_ENET_RDATA01 { + pinmux = <0x400e8230 1 0x400e84b4 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio11_io08: IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 { + pinmux = <0x400e8230 10 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio_mux5_io08: IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 { + pinmux = <0x400e8230 5 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_lpuart7_rx: IOMUXC_GPIO_DISP_B2_07_LPUART7_RX { + pinmux = <0x400e8230 2 0x400e862c 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_sai1_tx_data00: IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 { + pinmux = <0x400e8230 4 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_video_mux_lcdif_data15: IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 { + pinmux = <0x400e8230 0 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_cm7_imxrt_txev: IOMUXC_GPIO_DISP_B2_08_CM7_IMXRT_TXEV { + pinmux = <0x400e8234 3 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_enet_rx_en: IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN { + pinmux = <0x400e8234 1 0x400e84b8 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio11_io09: IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 { + pinmux = <0x400e8234 10 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio_mux5_io09: IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 { + pinmux = <0x400e8234 5 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart1_tx: IOMUXC_GPIO_DISP_B2_08_LPUART1_TX { + pinmux = <0x400e8234 9 0x400e8620 2 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart8_tx: IOMUXC_GPIO_DISP_B2_08_LPUART8_TX { + pinmux = <0x400e8234 2 0x400e8638 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_sai1_tx_bclk: IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK { + pinmux = <0x400e8234 4 0x400e867c 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_video_mux_lcdif_data16: IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 { + pinmux = <0x400e8234 0 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_cm7_imxrt_rxev: IOMUXC_GPIO_DISP_B2_09_CM7_IMXRT_RXEV { + pinmux = <0x400e8238 3 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_enet_rx_er: IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER { + pinmux = <0x400e8238 1 0x400e84bc 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio11_io10: IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 { + pinmux = <0x400e8238 10 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio_mux5_io10: IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 { + pinmux = <0x400e8238 5 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart1_rx: IOMUXC_GPIO_DISP_B2_09_LPUART1_RX { + pinmux = <0x400e8238 9 0x400e861c 2 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart8_rx: IOMUXC_GPIO_DISP_B2_09_LPUART8_RX { + pinmux = <0x400e8238 2 0x400e8634 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_sai1_tx_sync: IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC { + pinmux = <0x400e8238 4 0x400e8680 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_video_mux_lcdif_data17: IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 { + pinmux = <0x400e8238 0 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio11_io11: IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 { + pinmux = <0x400e823c 10 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio_mux5_io11: IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 { + pinmux = <0x400e823c 5 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpi2c3_scl: IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL { + pinmux = <0x400e823c 6 0x400e85bc 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpuart2_tx: IOMUXC_GPIO_DISP_B2_10_LPUART2_TX { + pinmux = <0x400e823c 2 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_sim2_trxd: IOMUXC_GPIO_DISP_B2_10_SIM2_TRXD { + pinmux = <0x400e823c 1 0x400e86a8 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_spdif_in: IOMUXC_GPIO_DISP_B2_10_SPDIF_IN { + pinmux = <0x400e823c 9 0x400e86b4 2 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_video_mux_lcdif_data18: IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 { + pinmux = <0x400e823c 0 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_10_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e823c 3 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_in38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_IN38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_inout38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_INOUT38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio11_io12: IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 { + pinmux = <0x400e8240 10 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio_mux5_io12: IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 { + pinmux = <0x400e8240 5 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpi2c3_sda: IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA { + pinmux = <0x400e8240 6 0x400e85c0 1 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpuart2_rx: IOMUXC_GPIO_DISP_B2_11_LPUART2_RX { + pinmux = <0x400e8240 2 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_sim2_clk: IOMUXC_GPIO_DISP_B2_11_SIM2_CLK { + pinmux = <0x400e8240 1 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_spdif_out: IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT { + pinmux = <0x400e8240 9 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_video_mux_lcdif_data19: IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 { + pinmux = <0x400e8240 0 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_11_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8240 3 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_in39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_IN39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_inout39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_INOUT39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_can1_tx: IOMUXC_GPIO_DISP_B2_12_CAN1_TX { + pinmux = <0x400e8244 2 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio11_io13: IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 { + pinmux = <0x400e8244 10 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio_mux5_io13: IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 { + pinmux = <0x400e8244 5 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpi2c4_scl: IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL { + pinmux = <0x400e8244 6 0x400e85c4 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpspi4_sck: IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK { + pinmux = <0x400e8244 9 0x400e8610 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpuart2_cts_b: IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B { + pinmux = <0x400e8244 3 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_sim2_rst_b: IOMUXC_GPIO_DISP_B2_12_SIM2_RST_B { + pinmux = <0x400e8244 1 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_video_mux_lcdif_data20: IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 { + pinmux = <0x400e8244 0 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_in40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_IN40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_inout40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_INOUT40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_can1_rx: IOMUXC_GPIO_DISP_B2_13_CAN1_RX { + pinmux = <0x400e8248 2 0x400e8498 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_enet_ref_clk: IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK { + pinmux = <0x400e8248 4 0x400e84a8 2 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio11_io14: IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 { + pinmux = <0x400e8248 10 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio_mux5_io14: IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 { + pinmux = <0x400e8248 5 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpi2c4_sda: IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA { + pinmux = <0x400e8248 6 0x400e85c8 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpspi4_sdi: IOMUXC_GPIO_DISP_B2_13_LPSPI4_SDI { + pinmux = <0x400e8248 9 0x400e8614 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpuart2_rts_b: IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B { + pinmux = <0x400e8248 3 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_sim2_sven: IOMUXC_GPIO_DISP_B2_13_SIM2_SVEN { + pinmux = <0x400e8248 1 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_video_mux_lcdif_data21: IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 { + pinmux = <0x400e8248 0 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_can1_tx: IOMUXC_GPIO_DISP_B2_14_CAN1_TX { + pinmux = <0x400e824c 6 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK1 { + pinmux = <0x400e824c 4 0x400e84c4 3 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio11_io15: IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 { + pinmux = <0x400e824c 10 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio_mux5_io15: IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 { + pinmux = <0x400e824c 5 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_lpspi4_sdo: IOMUXC_GPIO_DISP_B2_14_LPSPI4_SDO { + pinmux = <0x400e824c 9 0x400e8618 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_sim2_pd: IOMUXC_GPIO_DISP_B2_14_SIM2_PD { + pinmux = <0x400e824c 1 0x400e86ac 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_ext_dcic1: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e824c 3 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_lcdif_data22: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 { + pinmux = <0x400e824c 0 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_14_WDOG2_WDOG_B { + pinmux = <0x400e824c 2 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_can1_rx: IOMUXC_GPIO_DISP_B2_15_CAN1_RX { + pinmux = <0x400e8250 6 0x400e8498 2 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio11_io16: IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 { + pinmux = <0x400e8250 10 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio_mux5_io16: IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 { + pinmux = <0x400e8250 5 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_lpspi4_pcs0: IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 { + pinmux = <0x400e8250 9 0x400e860c 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_pit1_trigger00: IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER00 { + pinmux = <0x400e8250 4 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_sim2_power_fail: IOMUXC_GPIO_DISP_B2_15_SIM2_POWER_FAIL { + pinmux = <0x400e8250 1 0x400e86b0 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_ext_dcic2: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8250 3 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_lcdif_data23: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 { + pinmux = <0x400e8250 0 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_15_WDOG1_WDOG_B { + pinmux = <0x400e8250 2 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexio1_flexio00: IOMUXC_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00 { + pinmux = <0x400e8010 8 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexpwm4_pwm0_a: IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A { + pinmux = <0x400e8010 1 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio7_io00: IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 { + pinmux = <0x400e8010 10 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio_mux1_io00: IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 { + pinmux = <0x400e8010 5 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_semc_data00: IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 { + pinmux = <0x400e8010 0 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexio1_flexio01: IOMUXC_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01 { + pinmux = <0x400e8014 8 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexpwm4_pwm0_b: IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B { + pinmux = <0x400e8014 1 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio7_io01: IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 { + pinmux = <0x400e8014 10 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio_mux1_io01: IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 { + pinmux = <0x400e8014 5 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_semc_data01: IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 { + pinmux = <0x400e8014 0 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexio1_flexio02: IOMUXC_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02 { + pinmux = <0x400e8018 8 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexpwm4_pwm1_a: IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A { + pinmux = <0x400e8018 1 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio7_io02: IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 { + pinmux = <0x400e8018 10 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio_mux1_io02: IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 { + pinmux = <0x400e8018 5 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_semc_data02: IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 { + pinmux = <0x400e8018 0 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexio1_flexio03: IOMUXC_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03 { + pinmux = <0x400e801c 8 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexpwm4_pwm1_b: IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B { + pinmux = <0x400e801c 1 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio7_io03: IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 { + pinmux = <0x400e801c 10 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio_mux1_io03: IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 { + pinmux = <0x400e801c 5 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_semc_data03: IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 { + pinmux = <0x400e801c 0 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexio1_flexio04: IOMUXC_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04 { + pinmux = <0x400e8020 8 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexpwm4_pwm2_a: IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A { + pinmux = <0x400e8020 1 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio7_io04: IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 { + pinmux = <0x400e8020 10 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio_mux1_io04: IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 { + pinmux = <0x400e8020 5 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_semc_data04: IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 { + pinmux = <0x400e8020 0 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexio1_flexio05: IOMUXC_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05 { + pinmux = <0x400e8024 8 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexpwm4_pwm2_b: IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B { + pinmux = <0x400e8024 1 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio7_io05: IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 { + pinmux = <0x400e8024 10 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio_mux1_io05: IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 { + pinmux = <0x400e8024 5 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_semc_data05: IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 { + pinmux = <0x400e8024 0 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexio1_flexio06: IOMUXC_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06 { + pinmux = <0x400e8028 8 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexpwm2_pwm0_a: IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A { + pinmux = <0x400e8028 1 0x400e8518 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio7_io06: IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 { + pinmux = <0x400e8028 10 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio_mux1_io06: IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 { + pinmux = <0x400e8028 5 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_semc_data06: IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 { + pinmux = <0x400e8028 0 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexio1_flexio07: IOMUXC_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07 { + pinmux = <0x400e802c 8 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexpwm2_pwm0_b: IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B { + pinmux = <0x400e802c 1 0x400e8524 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio7_io07: IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 { + pinmux = <0x400e802c 10 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio_mux1_io07: IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 { + pinmux = <0x400e802c 5 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_semc_data07: IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 { + pinmux = <0x400e802c 0 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexio1_flexio08: IOMUXC_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08 { + pinmux = <0x400e8030 8 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexpwm2_pwm1_a: IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A { + pinmux = <0x400e8030 1 0x400e851c 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio7_io08: IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 { + pinmux = <0x400e8030 10 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio_mux1_io08: IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 { + pinmux = <0x400e8030 5 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_semc_dm00: IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 { + pinmux = <0x400e8030 0 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexio1_flexio09: IOMUXC_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09 { + pinmux = <0x400e8034 8 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexpwm2_pwm1_b: IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B { + pinmux = <0x400e8034 1 0x400e8528 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio7_io09: IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 { + pinmux = <0x400e8034 10 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio_mux1_io09: IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 { + pinmux = <0x400e8034 5 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpt5_capture1: IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 { + pinmux = <0x400e8034 2 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_semc_addr00: IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 { + pinmux = <0x400e8034 0 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexio1_flexio10: IOMUXC_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10 { + pinmux = <0x400e8038 8 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexpwm2_pwm2_a: IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A { + pinmux = <0x400e8038 1 0x400e8520 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio7_io10: IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 { + pinmux = <0x400e8038 10 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio_mux1_io10: IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 { + pinmux = <0x400e8038 5 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpt5_capture2: IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 { + pinmux = <0x400e8038 2 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_semc_addr01: IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 { + pinmux = <0x400e8038 0 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexio1_flexio11: IOMUXC_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11 { + pinmux = <0x400e803c 8 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexpwm2_pwm2_b: IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B { + pinmux = <0x400e803c 1 0x400e852c 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio7_io11: IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 { + pinmux = <0x400e803c 10 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio_mux1_io11: IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 { + pinmux = <0x400e803c 5 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpt5_compare1: IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 { + pinmux = <0x400e803c 2 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_semc_addr02: IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 { + pinmux = <0x400e803c 0 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_flexio1_flexio12: IOMUXC_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12 { + pinmux = <0x400e8040 8 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio7_io12: IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 { + pinmux = <0x400e8040 10 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio_mux1_io12: IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 { + pinmux = <0x400e8040 5 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpt5_compare2: IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 { + pinmux = <0x400e8040 2 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_semc_addr03: IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 { + pinmux = <0x400e8040 0 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_in04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_IN04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_INOUT04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_flexio1_flexio13: IOMUXC_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13 { + pinmux = <0x400e8044 8 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio7_io13: IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 { + pinmux = <0x400e8044 10 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio_mux1_io13: IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 { + pinmux = <0x400e8044 5 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpt5_compare3: IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 { + pinmux = <0x400e8044 2 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_semc_addr04: IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 { + pinmux = <0x400e8044 0 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_in05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_IN05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_INOUT05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_flexio1_flexio14: IOMUXC_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14 { + pinmux = <0x400e8048 8 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio7_io14: IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 { + pinmux = <0x400e8048 10 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio_mux1_io14: IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 { + pinmux = <0x400e8048 5 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpt5_clk: IOMUXC_GPIO_EMC_B1_14_GPT5_CLK { + pinmux = <0x400e8048 2 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_semc_addr05: IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 { + pinmux = <0x400e8048 0 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_in06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_IN06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_INOUT06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_flexio1_flexio15: IOMUXC_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15 { + pinmux = <0x400e804c 8 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio7_io15: IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 { + pinmux = <0x400e804c 10 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio_mux1_io15: IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 { + pinmux = <0x400e804c 5 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_semc_addr06: IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 { + pinmux = <0x400e804c 0 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_in07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_IN07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_INOUT07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_flexio1_flexio16: IOMUXC_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16 { + pinmux = <0x400e8050 8 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio7_io16: IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 { + pinmux = <0x400e8050 10 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio_mux1_io16: IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 { + pinmux = <0x400e8050 5 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_semc_addr07: IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 { + pinmux = <0x400e8050 0 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_in08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_IN08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_INOUT08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexio1_flexio17: IOMUXC_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17 { + pinmux = <0x400e8054 8 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexpwm4_pwm3_a: IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A { + pinmux = <0x400e8054 1 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio7_io17: IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 { + pinmux = <0x400e8054 10 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio_mux1_io17: IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 { + pinmux = <0x400e8054 5 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_qtimer1_timer0: IOMUXC_GPIO_EMC_B1_17_QTIMER1_TIMER0 { + pinmux = <0x400e8054 2 0x400e863c 0 0x400e8298>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_semc_addr08: IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 { + pinmux = <0x400e8054 0 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexio1_flexio18: IOMUXC_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18 { + pinmux = <0x400e8058 8 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexpwm4_pwm3_b: IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B { + pinmux = <0x400e8058 1 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio7_io18: IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 { + pinmux = <0x400e8058 10 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio_mux1_io18: IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 { + pinmux = <0x400e8058 5 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_qtimer2_timer0: IOMUXC_GPIO_EMC_B1_18_QTIMER2_TIMER0 { + pinmux = <0x400e8058 2 0x400e8648 0 0x400e829c>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_semc_addr09: IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 { + pinmux = <0x400e8058 0 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexio1_flexio19: IOMUXC_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19 { + pinmux = <0x400e805c 8 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexpwm2_pwm3_a: IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A { + pinmux = <0x400e805c 1 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio7_io19: IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 { + pinmux = <0x400e805c 10 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio_mux1_io19: IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 { + pinmux = <0x400e805c 5 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_qtimer3_timer0: IOMUXC_GPIO_EMC_B1_19_QTIMER3_TIMER0 { + pinmux = <0x400e805c 2 0x400e8654 0 0x400e82a0>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_semc_addr11: IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 { + pinmux = <0x400e805c 0 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexio1_flexio20: IOMUXC_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20 { + pinmux = <0x400e8060 8 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexpwm2_pwm3_b: IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B { + pinmux = <0x400e8060 1 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio7_io20: IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 { + pinmux = <0x400e8060 10 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio_mux1_io20: IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 { + pinmux = <0x400e8060 5 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_qtimer4_timer0: IOMUXC_GPIO_EMC_B1_20_QTIMER4_TIMER0 { + pinmux = <0x400e8060 2 0x400e8660 0 0x400e82a4>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_semc_addr12: IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 { + pinmux = <0x400e8060 0 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexio1_flexio21: IOMUXC_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21 { + pinmux = <0x400e8064 8 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A { + pinmux = <0x400e8064 1 0x400e853c 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio7_io21: IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 { + pinmux = <0x400e8064 10 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio_mux1_io21: IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 { + pinmux = <0x400e8064 5 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_semc_ba0: IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 { + pinmux = <0x400e8064 0 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexio1_flexio22: IOMUXC_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22 { + pinmux = <0x400e8068 8 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B { + pinmux = <0x400e8068 1 0x400e854c 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio7_io22: IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 { + pinmux = <0x400e8068 10 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio_mux1_io22: IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 { + pinmux = <0x400e8068 5 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_semc_ba1: IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 { + pinmux = <0x400e8068 0 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexio1_flexio23: IOMUXC_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23 { + pinmux = <0x400e806c 8 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexpwm1_pwm0_a: IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A { + pinmux = <0x400e806c 1 0x400e8500 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio7_io23: IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 { + pinmux = <0x400e806c 10 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio_mux1_io23: IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 { + pinmux = <0x400e806c 5 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_semc_addr10: IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 { + pinmux = <0x400e806c 0 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexio1_flexio24: IOMUXC_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24 { + pinmux = <0x400e8070 8 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexpwm1_pwm0_b: IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B { + pinmux = <0x400e8070 1 0x400e850c 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio7_io24: IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 { + pinmux = <0x400e8070 10 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio_mux1_io24: IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 { + pinmux = <0x400e8070 5 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_semc_cas: IOMUXC_GPIO_EMC_B1_24_SEMC_CAS { + pinmux = <0x400e8070 0 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexio1_flexio25: IOMUXC_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25 { + pinmux = <0x400e8074 8 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexpwm1_pwm1_a: IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A { + pinmux = <0x400e8074 1 0x400e8504 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio7_io25: IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 { + pinmux = <0x400e8074 10 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio_mux1_io25: IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 { + pinmux = <0x400e8074 5 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_semc_ras: IOMUXC_GPIO_EMC_B1_25_SEMC_RAS { + pinmux = <0x400e8074 0 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexio1_flexio26: IOMUXC_GPIO_EMC_B1_26_FLEXIO1_FLEXIO26 { + pinmux = <0x400e8078 8 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexpwm1_pwm1_b: IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B { + pinmux = <0x400e8078 1 0x400e8510 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio7_io26: IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 { + pinmux = <0x400e8078 10 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio_mux1_io26: IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 { + pinmux = <0x400e8078 5 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_semc_clk: IOMUXC_GPIO_EMC_B1_26_SEMC_CLK { + pinmux = <0x400e8078 0 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexio1_flexio27: IOMUXC_GPIO_EMC_B1_27_FLEXIO1_FLEXIO27 { + pinmux = <0x400e807c 8 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexpwm1_pwm2_a: IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A { + pinmux = <0x400e807c 1 0x400e8508 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio7_io27: IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 { + pinmux = <0x400e807c 10 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio_mux1_io27: IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 { + pinmux = <0x400e807c 5 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_semc_cke: IOMUXC_GPIO_EMC_B1_27_SEMC_CKE { + pinmux = <0x400e807c 0 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexio1_flexio28: IOMUXC_GPIO_EMC_B1_28_FLEXIO1_FLEXIO28 { + pinmux = <0x400e8080 8 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexpwm1_pwm2_b: IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B { + pinmux = <0x400e8080 1 0x400e8514 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio7_io28: IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 { + pinmux = <0x400e8080 10 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio_mux1_io28: IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 { + pinmux = <0x400e8080 5 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_semc_we: IOMUXC_GPIO_EMC_B1_28_SEMC_WE { + pinmux = <0x400e8080 0 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexio1_flexio29: IOMUXC_GPIO_EMC_B1_29_FLEXIO1_FLEXIO29 { + pinmux = <0x400e8084 8 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A { + pinmux = <0x400e8084 1 0x400e8530 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio7_io29: IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 { + pinmux = <0x400e8084 10 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio_mux1_io29: IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 { + pinmux = <0x400e8084 5 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_semc_cs0: IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 { + pinmux = <0x400e8084 0 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexio1_flexio30: IOMUXC_GPIO_EMC_B1_30_FLEXIO1_FLEXIO30 { + pinmux = <0x400e8088 8 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B { + pinmux = <0x400e8088 1 0x400e8540 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio7_io30: IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 { + pinmux = <0x400e8088 10 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio_mux1_io30: IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 { + pinmux = <0x400e8088 5 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_semc_data08: IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 { + pinmux = <0x400e8088 0 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexio1_flexio31: IOMUXC_GPIO_EMC_B1_31_FLEXIO1_FLEXIO31 { + pinmux = <0x400e808c 8 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A { + pinmux = <0x400e808c 1 0x400e8534 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio7_io31: IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 { + pinmux = <0x400e808c 10 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio_mux1_io31: IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 { + pinmux = <0x400e808c 5 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_semc_data09: IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 { + pinmux = <0x400e808c 0 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B { + pinmux = <0x400e8090 1 0x400e8544 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio8_io00: IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 { + pinmux = <0x400e8090 10 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00_cm7: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00_CM7 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_semc_data10: IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 { + pinmux = <0x400e8090 0 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A { + pinmux = <0x400e8094 1 0x400e8538 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio8_io01: IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 { + pinmux = <0x400e8094 10 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01_cm7: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01_CM7 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_semc_data11: IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 { + pinmux = <0x400e8094 0 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B { + pinmux = <0x400e8098 1 0x400e8548 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio8_io02: IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 { + pinmux = <0x400e8098 10 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02_cm7: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02_CM7 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_semc_data12: IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 { + pinmux = <0x400e8098 0 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio8_io03: IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 { + pinmux = <0x400e809c 10 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03_cm7: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03_CM7 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_semc_data13: IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 { + pinmux = <0x400e809c 0 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_in09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_IN09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_INOUT09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio8_io04: IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 { + pinmux = <0x400e80a0 10 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04_cm7: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04_CM7 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_semc_data14: IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 { + pinmux = <0x400e80a0 0 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_in10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_IN10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_INOUT10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio8_io05: IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 { + pinmux = <0x400e80a4 10 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05_cm7: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05_CM7 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_semc_data15: IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 { + pinmux = <0x400e80a4 0 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_in11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_IN11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_INOUT11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_flexpwm1_pwm3_a: IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A { + pinmux = <0x400e80a8 1 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio8_io06: IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 { + pinmux = <0x400e80a8 10 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06_cm7: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06_CM7 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_qtimer1_timer1: IOMUXC_GPIO_EMC_B1_38_QTIMER1_TIMER1 { + pinmux = <0x400e80a8 2 0x400e8640 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_semc_dm01: IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 { + pinmux = <0x400e80a8 0 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_flexpwm1_pwm3_b: IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B { + pinmux = <0x400e80ac 1 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio8_io07: IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 { + pinmux = <0x400e80ac 10 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07_cm7: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07_CM7 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_qtimer2_timer1: IOMUXC_GPIO_EMC_B1_39_QTIMER2_TIMER1 { + pinmux = <0x400e80ac 2 0x400e864c 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_semc_dqs: IOMUXC_GPIO_EMC_B1_39_SEMC_DQS { + pinmux = <0x400e80ac 0 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_ccm_clko1: IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 { + pinmux = <0x400e80b0 9 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_enet_1g_mdc: IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC { + pinmux = <0x400e80b0 7 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio8_io08: IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 { + pinmux = <0x400e80b0 10 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08_cm7: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08_CM7 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_lpuart6_tx: IOMUXC_GPIO_EMC_B1_40_LPUART6_TX { + pinmux = <0x400e80b0 3 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_mqs_right: IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT { + pinmux = <0x400e80b0 2 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_semc_rdy: IOMUXC_GPIO_EMC_B1_40_SEMC_RDY { + pinmux = <0x400e80b0 0 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_in12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_IN12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_INOUT12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_ccm_clko2: IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 { + pinmux = <0x400e80b4 9 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_enet_1g_mdio: IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO { + pinmux = <0x400e80b4 7 0x400e84c8 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_flexspi2_b_data07: IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 { + pinmux = <0x400e80b4 4 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio8_io09: IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 { + pinmux = <0x400e80b4 10 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09_cm7: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09_CM7 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_lpuart6_rx: IOMUXC_GPIO_EMC_B1_41_LPUART6_RX { + pinmux = <0x400e80b4 3 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_mqs_left: IOMUXC_GPIO_EMC_B1_41_MQS_LEFT { + pinmux = <0x400e80b4 2 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_semc_csx00: IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 { + pinmux = <0x400e80b4 0 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_in13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_IN13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_INOUT13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_ccm_enet_ref_clk_25m: IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e80b8 1 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A { + pinmux = <0x400e80b8 11 0x400e8530 1 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexspi2_b_data06: IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 { + pinmux = <0x400e80b8 4 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio8_io10: IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 { + pinmux = <0x400e80b8 10 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10_cm7: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10_CM7 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpi2c2_scl: IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL { + pinmux = <0x400e80b8 9 0x400e85b4 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpspi1_sck: IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK { + pinmux = <0x400e80b8 8 0x400e85d0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpuart6_cts_b: IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B { + pinmux = <0x400e80b8 3 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_00_QTIMER3_TIMER1 { + pinmux = <0x400e80b8 2 0x400e8658 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_semc_data16: IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 { + pinmux = <0x400e80b8 0 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_in20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_inout20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B { + pinmux = <0x400e80bc 11 0x400e8540 1 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexspi2_b_data05: IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 { + pinmux = <0x400e80bc 4 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio8_io11: IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 { + pinmux = <0x400e80bc 10 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11_cm7: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11_CM7 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpi2c2_sda: IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA { + pinmux = <0x400e80bc 9 0x400e85b8 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpspi1_pcs0: IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 { + pinmux = <0x400e80bc 8 0x400e85cc 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpuart6_rts_b: IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B { + pinmux = <0x400e80bc 3 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_qtimer4_timer1: IOMUXC_GPIO_EMC_B2_01_QTIMER4_TIMER1 { + pinmux = <0x400e80bc 2 0x400e8664 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_semc_data17: IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 { + pinmux = <0x400e80bc 0 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_usdhc2_cd_b: IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B { + pinmux = <0x400e80bc 1 0x400e86d0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_in21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_inout21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A { + pinmux = <0x400e80c0 11 0x400e8534 1 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexspi2_b_data04: IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 { + pinmux = <0x400e80c0 4 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio8_io12: IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 { + pinmux = <0x400e80c0 10 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12_cm7: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12_CM7 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_lpspi1_sdo: IOMUXC_GPIO_EMC_B2_02_LPSPI1_SDO { + pinmux = <0x400e80c0 8 0x400e85d8 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_semc_data18: IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 { + pinmux = <0x400e80c0 0 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_usdhc2_wp: IOMUXC_GPIO_EMC_B2_02_USDHC2_WP { + pinmux = <0x400e80c0 1 0x400e86d4 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_video_mux_csi_data23: IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 { + pinmux = <0x400e80c0 3 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_in22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_inout22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_enet_1g_tdata03: IOMUXC_GPIO_EMC_B2_03_ENET_1G_TDATA03 { + pinmux = <0x400e80c4 7 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B { + pinmux = <0x400e80c4 11 0x400e8544 1 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexspi2_b_data03: IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 { + pinmux = <0x400e80c4 4 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio8_io13: IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 { + pinmux = <0x400e80c4 10 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13_cm7: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13_CM7 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_lpspi1_sdi: IOMUXC_GPIO_EMC_B2_03_LPSPI1_SDI { + pinmux = <0x400e80c4 8 0x400e85d4 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_semc_data19: IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 { + pinmux = <0x400e80c4 0 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_usdhc2_vselect: IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT { + pinmux = <0x400e80c4 1 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_video_mux_csi_data22: IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 { + pinmux = <0x400e80c4 3 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_in23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_inout23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_enet_1g_tdata02: IOMUXC_GPIO_EMC_B2_04_ENET_1G_TDATA02 { + pinmux = <0x400e80c8 7 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A { + pinmux = <0x400e80c8 11 0x400e8538 1 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexspi2_b_data02: IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 { + pinmux = <0x400e80c8 4 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio8_io14: IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 { + pinmux = <0x400e80c8 10 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14_cm7: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14_CM7 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_lpspi3_sck: IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK { + pinmux = <0x400e80c8 8 0x400e8600 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_sai2_mclk: IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK { + pinmux = <0x400e80c8 2 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_semc_data20: IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 { + pinmux = <0x400e80c8 0 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_usdhc2_reset_b: IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B { + pinmux = <0x400e80c8 1 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_video_mux_csi_data21: IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 { + pinmux = <0x400e80c8 3 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_in24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_inout24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_enet_1g_rx_clk: IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK { + pinmux = <0x400e80cc 7 0x400e84cc 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B { + pinmux = <0x400e80cc 11 0x400e8548 1 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexspi2_b_data01: IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 { + pinmux = <0x400e80cc 4 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio8_io15: IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 { + pinmux = <0x400e80cc 10 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15_cm7: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15_CM7 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpt3_clk: IOMUXC_GPIO_EMC_B2_05_GPT3_CLK { + pinmux = <0x400e80cc 1 0x400e8598 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_lpspi3_pcs0: IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 { + pinmux = <0x400e80cc 8 0x400e85f0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_pit1_trigger00: IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER00 { + pinmux = <0x400e80cc 9 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_sai2_rx_sync: IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC { + pinmux = <0x400e80cc 2 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_semc_data21: IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 { + pinmux = <0x400e80cc 0 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_video_mux_csi_data20: IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 { + pinmux = <0x400e80cc 3 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_in25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_inout25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_enet_1g_tx_er: IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER { + pinmux = <0x400e80d0 7 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A { + pinmux = <0x400e80d0 11 0x400e853c 1 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexspi2_b_data00: IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 { + pinmux = <0x400e80d0 4 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio8_io16: IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 { + pinmux = <0x400e80d0 10 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16_cm7: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16_CM7 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpt3_capture1: IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 { + pinmux = <0x400e80d0 1 0x400e8590 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_lpspi3_sdo: IOMUXC_GPIO_EMC_B2_06_LPSPI3_SDO { + pinmux = <0x400e80d0 8 0x400e8608 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_pit1_trigger01: IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER01 { + pinmux = <0x400e80d0 9 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_sai2_rx_bclk: IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK { + pinmux = <0x400e80d0 2 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_semc_data22: IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 { + pinmux = <0x400e80d0 0 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_video_mux_csi_data19: IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 { + pinmux = <0x400e80d0 3 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_in26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_IN26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_inout26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_enet_1g_rdata03: IOMUXC_GPIO_EMC_B2_07_ENET_1G_RDATA03 { + pinmux = <0x400e80d4 7 0x400e84dc 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B { + pinmux = <0x400e80d4 11 0x400e854c 1 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexspi2_b_dqs: IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS { + pinmux = <0x400e80d4 4 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio8_io17: IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 { + pinmux = <0x400e80d4 10 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17_cm7: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17_CM7 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpt3_capture2: IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 { + pinmux = <0x400e80d4 1 0x400e8594 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_lpspi3_sdi: IOMUXC_GPIO_EMC_B2_07_LPSPI3_SDI { + pinmux = <0x400e80d4 8 0x400e8604 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_pit1_trigger02: IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER02 { + pinmux = <0x400e80d4 9 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_sai2_rx_data: IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA { + pinmux = <0x400e80d4 2 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_semc_data23: IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 { + pinmux = <0x400e80d4 0 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_video_mux_csi_data18: IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 { + pinmux = <0x400e80d4 3 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_in27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_IN27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_inout27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_enet_1g_rdata02: IOMUXC_GPIO_EMC_B2_08_ENET_1G_RDATA02 { + pinmux = <0x400e80d8 7 0x400e84d8 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B { + pinmux = <0x400e80d8 4 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio8_io18: IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 { + pinmux = <0x400e80d8 10 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18_cm7: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18_CM7 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpt3_compare1: IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 { + pinmux = <0x400e80d8 1 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_lpspi3_pcs1: IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 { + pinmux = <0x400e80d8 8 0x400e85f4 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_pit1_trigger03: IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER03 { + pinmux = <0x400e80d8 9 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_sai2_tx_data: IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA { + pinmux = <0x400e80d8 2 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_semc_dm02: IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 { + pinmux = <0x400e80d8 0 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_video_mux_csi_data17: IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 { + pinmux = <0x400e80d8 3 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_in28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_IN28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_inout28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_enet_1g_crs: IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS { + pinmux = <0x400e80dc 7 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_flexspi2_b_sclk: IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK { + pinmux = <0x400e80dc 4 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio8_io19: IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 { + pinmux = <0x400e80dc 10 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19_cm7: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19_CM7 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpt3_compare2: IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 { + pinmux = <0x400e80dc 1 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_lpspi3_pcs2: IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 { + pinmux = <0x400e80dc 8 0x400e85f8 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_qtimer1_timer0: IOMUXC_GPIO_EMC_B2_09_QTIMER1_TIMER0 { + pinmux = <0x400e80dc 9 0x400e863c 1 0x400e8320>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_sai2_tx_bclk: IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK { + pinmux = <0x400e80dc 2 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_semc_data24: IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 { + pinmux = <0x400e80dc 0 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_video_mux_csi_data16: IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 { + pinmux = <0x400e80dc 3 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_in29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_IN29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_inout29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_enet_1g_col: IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL { + pinmux = <0x400e80e0 7 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_flexspi2_a_sclk: IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK { + pinmux = <0x400e80e0 4 0x400e858c 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio8_io20: IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 { + pinmux = <0x400e80e0 10 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20_cm7: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20_CM7 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpt3_compare3: IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 { + pinmux = <0x400e80e0 1 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_lpspi3_pcs3: IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 { + pinmux = <0x400e80e0 8 0x400e85fc 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_qtimer1_timer1: IOMUXC_GPIO_EMC_B2_10_QTIMER1_TIMER1 { + pinmux = <0x400e80e0 9 0x400e8640 1 0x400e8324>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_sai2_tx_sync: IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC { + pinmux = <0x400e80e0 2 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_semc_data25: IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 { + pinmux = <0x400e80e0 0 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_video_mux_csi_field: IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD { + pinmux = <0x400e80e0 3 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_in30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_IN30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_inout30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_enet_1g_tdata00: IOMUXC_GPIO_EMC_B2_11_ENET_1G_TDATA00 { + pinmux = <0x400e80e4 2 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B { + pinmux = <0x400e80e4 4 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio8_io21: IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 { + pinmux = <0x400e80e4 10 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21_cm7: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21_CM7 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_qtimer1_timer2: IOMUXC_GPIO_EMC_B2_11_QTIMER1_TIMER2 { + pinmux = <0x400e80e4 9 0x400e8644 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sai3_rx_sync: IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC { + pinmux = <0x400e80e4 3 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_semc_data26: IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 { + pinmux = <0x400e80e4 0 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sim1_trxd: IOMUXC_GPIO_EMC_B2_11_SIM1_TRXD { + pinmux = <0x400e80e4 8 0x400e869c 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_spdif_in: IOMUXC_GPIO_EMC_B2_11_SPDIF_IN { + pinmux = <0x400e80e4 1 0x400e86b4 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_in31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_IN31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_inout31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_enet_1g_tdata01: IOMUXC_GPIO_EMC_B2_12_ENET_1G_TDATA01 { + pinmux = <0x400e80e8 2 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_flexspi2_a_dqs: IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS { + pinmux = <0x400e80e8 4 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio8_io22: IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 { + pinmux = <0x400e80e8 10 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22_cm7: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22_CM7 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_qtimer1_timer3: IOMUXC_GPIO_EMC_B2_12_QTIMER1_TIMER3 { + pinmux = <0x400e80e8 9 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4030 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sai3_rx_bclk: IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK { + pinmux = <0x400e80e8 3 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_semc_data27: IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 { + pinmux = <0x400e80e8 0 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sim1_clk: IOMUXC_GPIO_EMC_B2_12_SIM1_CLK { + pinmux = <0x400e80e8 8 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_spdif_out: IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT { + pinmux = <0x400e80e8 1 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_in32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_IN32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_inout32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_enet_1g_tx_en: IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN { + pinmux = <0x400e80ec 2 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_flexspi2_a_data00: IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 { + pinmux = <0x400e80ec 4 0x400e857c 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio8_io23: IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 { + pinmux = <0x400e80ec 10 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23_cm7: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23_CM7 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_qtimer2_timer0: IOMUXC_GPIO_EMC_B2_13_QTIMER2_TIMER0 { + pinmux = <0x400e80ec 9 0x400e8648 1 0x400e8330>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sai3_rx_data: IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA { + pinmux = <0x400e80ec 3 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_semc_data28: IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 { + pinmux = <0x400e80ec 0 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sim1_rst_b: IOMUXC_GPIO_EMC_B2_13_SIM1_RST_B { + pinmux = <0x400e80ec 8 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_in33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_IN33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_inout33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_enet_1g_tx_clk_io: IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO { + pinmux = <0x400e80f0 2 0x400e84e8 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_flexspi2_a_data01: IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 { + pinmux = <0x400e80f0 4 0x400e8580 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio8_io24: IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 { + pinmux = <0x400e80f0 10 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24_cm7: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24_CM7 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_qtimer2_timer1: IOMUXC_GPIO_EMC_B2_14_QTIMER2_TIMER1 { + pinmux = <0x400e80f0 9 0x400e864c 1 0x400e8334>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sai3_tx_data: IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA { + pinmux = <0x400e80f0 3 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_semc_data29: IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 { + pinmux = <0x400e80f0 0 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sim1_sven: IOMUXC_GPIO_EMC_B2_14_SIM1_SVEN { + pinmux = <0x400e80f0 8 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_in34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_IN34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_inout34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_enet_1g_rdata00: IOMUXC_GPIO_EMC_B2_15_ENET_1G_RDATA00 { + pinmux = <0x400e80f4 2 0x400e84d0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_flexspi2_a_data02: IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 { + pinmux = <0x400e80f4 4 0x400e8584 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio8_io25: IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 { + pinmux = <0x400e80f4 10 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25_cm7: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25_CM7 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_qtimer2_timer2: IOMUXC_GPIO_EMC_B2_15_QTIMER2_TIMER2 { + pinmux = <0x400e80f4 9 0x400e8650 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sai3_tx_bclk: IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK { + pinmux = <0x400e80f4 3 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_semc_data30: IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 { + pinmux = <0x400e80f4 0 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sim1_pd: IOMUXC_GPIO_EMC_B2_15_SIM1_PD { + pinmux = <0x400e80f4 8 0x400e86a0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_in35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_IN35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_inout35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_enet_1g_rdata01: IOMUXC_GPIO_EMC_B2_16_ENET_1G_RDATA01 { + pinmux = <0x400e80f8 2 0x400e84d4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_flexspi2_a_data03: IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 { + pinmux = <0x400e80f8 4 0x400e8588 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio8_io26: IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 { + pinmux = <0x400e80f8 10 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26_cm7: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26_CM7 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_qtimer2_timer3: IOMUXC_GPIO_EMC_B2_16_QTIMER2_TIMER3 { + pinmux = <0x400e80f8 9 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4034 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sai3_tx_sync: IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC { + pinmux = <0x400e80f8 3 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_semc_data31: IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 { + pinmux = <0x400e80f8 0 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sim1_power_fail: IOMUXC_GPIO_EMC_B2_16_SIM1_POWER_FAIL { + pinmux = <0x400e80f8 8 0x400e86a4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_in14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_IN14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_enet_1g_rx_en: IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN { + pinmux = <0x400e80fc 2 0x400e84e0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_flexspi2_a_data04: IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 { + pinmux = <0x400e80fc 4 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio8_io27: IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 { + pinmux = <0x400e80fc 10 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27_cm7: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27_CM7 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_qtimer3_timer0: IOMUXC_GPIO_EMC_B2_17_QTIMER3_TIMER0 { + pinmux = <0x400e80fc 9 0x400e8654 1 0x400e8340>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_sai3_mclk: IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK { + pinmux = <0x400e80fc 3 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_semc_dm03: IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 { + pinmux = <0x400e80fc 0 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_wdog1_wdog_any: IOMUXC_GPIO_EMC_B2_17_WDOG1_WDOG_ANY { + pinmux = <0x400e80fc 8 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_in15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_IN15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_enet_1g_rx_er: IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER { + pinmux = <0x400e8100 2 0x400e84e4 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_ewm_ewm_out_b: IOMUXC_GPIO_EMC_B2_18_EWM_EWM_OUT_B { + pinmux = <0x400e8100 3 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi1_a_dqs: IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS { + pinmux = <0x400e8100 6 0x400e8550 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi2_a_data05: IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 { + pinmux = <0x400e8100 4 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio8_io28: IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 { + pinmux = <0x400e8100 10 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28_cm7: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28_CM7 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_18_QTIMER3_TIMER1 { + pinmux = <0x400e8100 9 0x400e8658 1 0x400e8344>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_semc_dqs4: IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 { + pinmux = <0x400e8100 0 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_wdog1_wdog_b: IOMUXC_GPIO_EMC_B2_18_WDOG1_WDOG_B { + pinmux = <0x400e8100 8 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_IN16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC { + pinmux = <0x400e8104 2 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_ref_clk1: IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK1 { + pinmux = <0x400e8104 3 0x400e84c4 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_MDC { + pinmux = <0x400e8104 1 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_flexspi2_a_data06: IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 { + pinmux = <0x400e8104 4 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio8_io29: IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 { + pinmux = <0x400e8104 10 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29_cm7: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29_CM7 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_qtimer3_timer2: IOMUXC_GPIO_EMC_B2_19_QTIMER3_TIMER2 { + pinmux = <0x400e8104 9 0x400e865c 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_semc_clkx00: IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 { + pinmux = <0x400e8104 0 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_1g_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO { + pinmux = <0x400e8108 2 0x400e84c8 1 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_MDIO { + pinmux = <0x400e8108 1 0x400e84ac 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_flexspi2_a_data07: IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 { + pinmux = <0x400e8108 4 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio8_io30: IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 { + pinmux = <0x400e8108 10 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30_cm7: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30_CM7 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_qtimer3_timer3: IOMUXC_GPIO_EMC_B2_20_QTIMER3_TIMER3 { + pinmux = <0x400e8108 9 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e4038 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_semc_clkx01: IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 { + pinmux = <0x400e8108 0 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_can3_tx: IOMUXC_LPSR_GPIO_LPSR_00_CAN3_TX { + pinmux = <0x40c08000 0 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_cm4_imxrt_txev: IOMUXC_LPSR_GPIO_LPSR_00_CM4_IMXRT_TXEV { + pinmux = <0x40c08000 3 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio12_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO12_IO00 { + pinmux = <0x40c08000 10 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio_mux6_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO_MUX6_IO00 { + pinmux = <0x40c08000 5 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_00_LPUART12_TX { + pinmux = <0x40c08000 6 0x40c080b0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mic_clk: IOMUXC_LPSR_GPIO_LPSR_00_MIC_CLK { + pinmux = <0x40c08000 1 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mqs_right: IOMUXC_LPSR_GPIO_LPSR_00_MQS_RIGHT { + pinmux = <0x40c08000 2 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_00_SAI4_MCLK { + pinmux = <0x40c08000 7 0x40c080c8 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_can3_rx: IOMUXC_LPSR_GPIO_LPSR_01_CAN3_RX { + pinmux = <0x40c08004 0 0x40c08080 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_cm4_imxrt_rxev: IOMUXC_LPSR_GPIO_LPSR_01_CM4_IMXRT_RXEV { + pinmux = <0x40c08004 3 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio12_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO12_IO01 { + pinmux = <0x40c08004 10 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO_MUX6_IO01 { + pinmux = <0x40c08004 5 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_01_LPUART12_RX { + pinmux = <0x40c08004 6 0x40c080ac 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_01_MIC_BITSTREAM00 { + pinmux = <0x40c08004 1 0x40c080b4 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mqs_left: IOMUXC_LPSR_GPIO_LPSR_01_MQS_LEFT { + pinmux = <0x40c08004 2 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio12_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO12_IO02 { + pinmux = <0x40c08008 10 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO_MUX6_IO02 { + pinmux = <0x40c08008 5 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_02_LPSPI5_SCK { + pinmux = <0x40c08008 1 0x40c08098 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_mqs_right: IOMUXC_LPSR_GPIO_LPSR_02_MQS_RIGHT { + pinmux = <0x40c08008 3 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_02_SAI4_TX_DATA { + pinmux = <0x40c08008 2 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_src_boot_mode00: IOMUXC_LPSR_GPIO_LPSR_02_SRC_BOOT_MODE00 { + pinmux = <0x40c08008 0 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio12_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO12_IO03 { + pinmux = <0x40c0800c 10 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO_MUX6_IO03 { + pinmux = <0x40c0800c 5 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_03_LPSPI5_PCS0 { + pinmux = <0x40c0800c 1 0x40c08094 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_mqs_left: IOMUXC_LPSR_GPIO_LPSR_03_MQS_LEFT { + pinmux = <0x40c0800c 3 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_03_SAI4_TX_SYNC { + pinmux = <0x40c0800c 2 0x40c080dc 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_src_boot_mode01: IOMUXC_LPSR_GPIO_LPSR_03_SRC_BOOT_MODE01 { + pinmux = <0x40c0800c 0 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio12_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO12_IO04 { + pinmux = <0x40c08010 10 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO_MUX6_IO04 { + pinmux = <0x40c08010 5 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_04_LPI2C5_SDA { + pinmux = <0x40c08010 0 0x40c08088 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_04_LPSPI5_SDO { + pinmux = <0x40c08010 1 0x40c080a0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_04_LPUART11_TX { + pinmux = <0x40c08010 6 0x40c080a8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart12_rts_b: IOMUXC_LPSR_GPIO_LPSR_04_LPUART12_RTS_B { + pinmux = <0x40c08010 3 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_04_SAI4_TX_BCLK { + pinmux = <0x40c08010 2 0x40c080d8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio12_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO12_IO05 { + pinmux = <0x40c08014 10 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO_MUX6_IO05 { + pinmux = <0x40c08014 5 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_05_LPI2C5_SCL { + pinmux = <0x40c08014 0 0x40c08084 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_05_LPSPI5_SDI { + pinmux = <0x40c08014 1 0x40c0809c 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_05_LPUART11_RX { + pinmux = <0x40c08014 6 0x40c080a4 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart12_cts_b: IOMUXC_LPSR_GPIO_LPSR_05_LPUART12_CTS_B { + pinmux = <0x40c08014 3 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_05_SAI4_MCLK { + pinmux = <0x40c08014 2 0x40c080c8 1 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_can3_tx: IOMUXC_LPSR_GPIO_LPSR_06_CAN3_TX { + pinmux = <0x40c08018 6 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio12_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO12_IO06 { + pinmux = <0x40c08018 10 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO_MUX6_IO06 { + pinmux = <0x40c08018 5 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_06_LPI2C6_SDA { + pinmux = <0x40c08018 0 0x40c08090 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi5_pcs1: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI5_PCS1 { + pinmux = <0x40c08018 8 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi6_pcs3: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI6_PCS3 { + pinmux = <0x40c08018 4 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_06_LPUART12_TX { + pinmux = <0x40c08018 3 0x40c080b0 1 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_06_PIT2_TRIGGER03 { + pinmux = <0x40c08018 7 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_06_SAI4_RX_DATA { + pinmux = <0x40c08018 2 0x40c080d0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_can3_rx: IOMUXC_LPSR_GPIO_LPSR_07_CAN3_RX { + pinmux = <0x40c0801c 6 0x40c08080 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio12_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO12_IO07 { + pinmux = <0x40c0801c 10 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO_MUX6_IO07 { + pinmux = <0x40c0801c 5 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_07_LPI2C6_SCL { + pinmux = <0x40c0801c 0 0x40c0808c 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi5_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI5_PCS2 { + pinmux = <0x40c0801c 8 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi6_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI6_PCS2 { + pinmux = <0x40c0801c 4 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_07_LPUART12_RX { + pinmux = <0x40c0801c 3 0x40c080ac 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_07_PIT2_TRIGGER02 { + pinmux = <0x40c0801c 7 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_07_SAI4_RX_BCLK { + pinmux = <0x40c0801c 2 0x40c080cc 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_can3_tx: IOMUXC_LPSR_GPIO_LPSR_08_CAN3_TX { + pinmux = <0x40c08020 1 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio12_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO12_IO08 { + pinmux = <0x40c08020 10 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO_MUX6_IO08 { + pinmux = <0x40c08020 5 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_08_LPI2C5_SDA { + pinmux = <0x40c08020 6 0x40c08088 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi5_pcs3: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI5_PCS3 { + pinmux = <0x40c08020 8 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi6_pcs1: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI6_PCS1 { + pinmux = <0x40c08020 4 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_08_LPUART11_TX { + pinmux = <0x40c08020 0 0x40c080a8 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_mic_clk: IOMUXC_LPSR_GPIO_LPSR_08_MIC_CLK { + pinmux = <0x40c08020 3 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_08_PIT2_TRIGGER01 { + pinmux = <0x40c08020 7 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_08_SAI4_RX_SYNC { + pinmux = <0x40c08020 2 0x40c080d4 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_can3_rx: IOMUXC_LPSR_GPIO_LPSR_09_CAN3_RX { + pinmux = <0x40c08024 1 0x40c08080 2 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio12_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO12_IO09 { + pinmux = <0x40c08024 10 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO_MUX6_IO09 { + pinmux = <0x40c08024 5 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_09_LPI2C5_SCL { + pinmux = <0x40c08024 6 0x40c08084 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpspi6_pcs0: IOMUXC_LPSR_GPIO_LPSR_09_LPSPI6_PCS0 { + pinmux = <0x40c08024 4 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_09_LPUART11_RX { + pinmux = <0x40c08024 0 0x40c080a4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_09_MIC_BITSTREAM00 { + pinmux = <0x40c08024 3 0x40c080b4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_09_PIT2_TRIGGER00 { + pinmux = <0x40c08024 2 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_09_SAI4_TX_DATA { + pinmux = <0x40c08024 7 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio12_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO12_IO10 { + pinmux = <0x40c08028 10 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO_MUX6_IO10 { + pinmux = <0x40c08028 5 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_jtag_mux_trstb: IOMUXC_LPSR_GPIO_LPSR_10_JTAG_MUX_TRSTB { + pinmux = <0x40c08028 0 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c5_scls: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C5_SCLS { + pinmux = <0x40c08028 6 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C6_SDA { + pinmux = <0x40c08028 2 0x40c08090 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpspi6_sck: IOMUXC_LPSR_GPIO_LPSR_10_LPSPI6_SCK { + pinmux = <0x40c08028 4 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart11_cts_b: IOMUXC_LPSR_GPIO_LPSR_10_LPUART11_CTS_B { + pinmux = <0x40c08028 1 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_10_LPUART12_TX { + pinmux = <0x40c08028 8 0x40c080b0 2 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_10_MIC_BITSTREAM01 { + pinmux = <0x40c08028 3 0x40c080b8 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_10_SAI4_TX_SYNC { + pinmux = <0x40c08028 7 0x40c080dc 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_arm_trace_swo: IOMUXC_LPSR_GPIO_LPSR_11_ARM_TRACE_SWO { + pinmux = <0x40c0802c 7 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio12_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO12_IO11 { + pinmux = <0x40c0802c 10 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO_MUX6_IO11 { + pinmux = <0x40c0802c 5 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_jtag_mux_tdo: IOMUXC_LPSR_GPIO_LPSR_11_JTAG_MUX_TDO { + pinmux = <0x40c0802c 0 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c5_sdas: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C5_SDAS { + pinmux = <0x40c0802c 6 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C6_SCL { + pinmux = <0x40c0802c 2 0x40c0808c 1 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpspi6_sdo: IOMUXC_LPSR_GPIO_LPSR_11_LPSPI6_SDO { + pinmux = <0x40c0802c 4 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart11_rts_b: IOMUXC_LPSR_GPIO_LPSR_11_LPUART11_RTS_B { + pinmux = <0x40c0802c 1 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_11_LPUART12_RX { + pinmux = <0x40c0802c 8 0x40c080ac 2 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_11_MIC_BITSTREAM02 { + pinmux = <0x40c0802c 3 0x40c080bc 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio12_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO12_IO12 { + pinmux = <0x40c08030 10 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO_MUX6_IO12 { + pinmux = <0x40c08030 5 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_jtag_mux_tdi: IOMUXC_LPSR_GPIO_LPSR_12_JTAG_MUX_TDI { + pinmux = <0x40c08030 0 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpi2c5_hreq: IOMUXC_LPSR_GPIO_LPSR_12_LPI2C5_HREQ { + pinmux = <0x40c08030 6 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI5_SCK { + pinmux = <0x40c08030 8 0x40c08098 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi6_sdi: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI6_SDI { + pinmux = <0x40c08030 4 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_12_MIC_BITSTREAM03 { + pinmux = <0x40c08030 3 0x40c080c0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_12_PIT2_TRIGGER00 { + pinmux = <0x40c08030 1 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_12_SAI4_TX_BCLK { + pinmux = <0x40c08030 7 0x40c080d8 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio12_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO12_IO13 { + pinmux = <0x40c08034 10 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO_MUX6_IO13 { + pinmux = <0x40c08034 5 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_jtag_mux_mod: IOMUXC_LPSR_GPIO_LPSR_13_JTAG_MUX_MOD { + pinmux = <0x40c08034 0 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_13_LPSPI5_PCS0 { + pinmux = <0x40c08034 8 0x40c08094 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_13_MIC_BITSTREAM01 { + pinmux = <0x40c08034 1 0x40c080b8 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_13_PIT2_TRIGGER01 { + pinmux = <0x40c08034 2 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_13_SAI4_RX_DATA { + pinmux = <0x40c08034 7 0x40c080d0 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio12_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO12_IO14 { + pinmux = <0x40c08038 10 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO_MUX6_IO14 { + pinmux = <0x40c08038 5 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_jtag_mux_tck: IOMUXC_LPSR_GPIO_LPSR_14_JTAG_MUX_TCK { + pinmux = <0x40c08038 0 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_14_LPSPI5_SDO { + pinmux = <0x40c08038 8 0x40c080a0 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_14_MIC_BITSTREAM02 { + pinmux = <0x40c08038 1 0x40c080bc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_14_PIT2_TRIGGER02 { + pinmux = <0x40c08038 2 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_14_SAI4_RX_BCLK { + pinmux = <0x40c08038 7 0x40c080cc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio12_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO12_IO15 { + pinmux = <0x40c0803c 10 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO_MUX6_IO15 { + pinmux = <0x40c0803c 5 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_jtag_mux_tms: IOMUXC_LPSR_GPIO_LPSR_15_JTAG_MUX_TMS { + pinmux = <0x40c0803c 0 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_15_LPSPI5_SDI { + pinmux = <0x40c0803c 8 0x40c0809c 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_15_MIC_BITSTREAM03 { + pinmux = <0x40c0803c 1 0x40c080c0 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_15_PIT2_TRIGGER03 { + pinmux = <0x40c0803c 2 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_15_SAI4_RX_SYNC { + pinmux = <0x40c0803c 7 0x40c080d4 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi2_a_ss0_b: IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B { + pinmux = <0x400e819c 6 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio10_io03: IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 { + pinmux = <0x400e819c 10 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio_mux4_io03: IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 { + pinmux = <0x400e819c 5 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpt4_capture1: IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 { + pinmux = <0x400e819c 3 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_kpp_row07: IOMUXC_GPIO_SD_B1_00_KPP_ROW07 { + pinmux = <0x400e819c 8 0x400e85a8 1 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc1_cmd: IOMUXC_GPIO_SD_B1_00_USDHC1_CMD { + pinmux = <0x400e819c 0 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi2_a_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK { + pinmux = <0x400e81a0 6 0x400e858c 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio10_io04: IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 { + pinmux = <0x400e81a0 10 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio_mux4_io04: IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 { + pinmux = <0x400e81a0 5 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpt4_capture2: IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 { + pinmux = <0x400e81a0 3 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_kpp_col07: IOMUXC_GPIO_SD_B1_01_KPP_COL07 { + pinmux = <0x400e81a0 8 0x400e85a0 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc1_clk: IOMUXC_GPIO_SD_B1_01_USDHC1_CLK { + pinmux = <0x400e81a0 0 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_in21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_inout21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81a4 9 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi2_a_data00: IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 { + pinmux = <0x400e81a4 6 0x400e857c 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio10_io05: IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 { + pinmux = <0x400e81a4 10 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio_mux4_io05: IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 { + pinmux = <0x400e81a4 5 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpt4_compare1: IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 { + pinmux = <0x400e81a4 3 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_kpp_row06: IOMUXC_GPIO_SD_B1_02_KPP_ROW06 { + pinmux = <0x400e81a4 8 0x400e85a4 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc1_data0: IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 { + pinmux = <0x400e81a4 0 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_in22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_inout22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi1_b_ss1_b: IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B { + pinmux = <0x400e81a8 9 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi2_a_data01: IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 { + pinmux = <0x400e81a8 6 0x400e8580 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio10_io06: IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 { + pinmux = <0x400e81a8 10 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio_mux4_io06: IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 { + pinmux = <0x400e81a8 5 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpt4_compare2: IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 { + pinmux = <0x400e81a8 3 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_kpp_col06: IOMUXC_GPIO_SD_B1_03_KPP_COL06 { + pinmux = <0x400e81a8 8 0x400e859c 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc1_data1: IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 { + pinmux = <0x400e81a8 0 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_in23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_inout23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81ac 8 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi2_a_data02: IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 { + pinmux = <0x400e81ac 6 0x400e8584 1 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio10_io07: IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 { + pinmux = <0x400e81ac 10 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio_mux4_io07: IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 { + pinmux = <0x400e81ac 5 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpt4_compare3: IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 { + pinmux = <0x400e81ac 3 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc1_data2: IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 { + pinmux = <0x400e81ac 0 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_in24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_inout24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi1_b_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS { + pinmux = <0x400e81b0 8 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi2_a_data03: IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 { + pinmux = <0x400e81b0 6 0x400e8588 1 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio10_io08: IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 { + pinmux = <0x400e81b0 10 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio_mux4_io08: IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 { + pinmux = <0x400e81b0 5 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpt4_clk: IOMUXC_GPIO_SD_B1_05_GPT4_CLK { + pinmux = <0x400e81b0 3 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc1_data3: IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 { + pinmux = <0x400e81b0 0 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_in25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_inout25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_enet_1g_rx_en: IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN { + pinmux = <0x400e81b4 2 0x400e84e0 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_flexspi1_b_data03: IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 { + pinmux = <0x400e81b4 1 0x400e8570 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio10_io09: IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 { + pinmux = <0x400e81b4 10 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio_mux4_io09: IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 { + pinmux = <0x400e81b4 5 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpspi4_sck: IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK { + pinmux = <0x400e81b4 4 0x400e8610 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpuart9_tx: IOMUXC_GPIO_SD_B2_00_LPUART9_TX { + pinmux = <0x400e81b4 3 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_usdhc2_data3: IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 { + pinmux = <0x400e81b4 0 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_enet_1g_rx_clk: IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK { + pinmux = <0x400e81b8 2 0x400e84cc 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_flexspi1_b_data02: IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 { + pinmux = <0x400e81b8 1 0x400e856c 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio10_io10: IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 { + pinmux = <0x400e81b8 10 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio_mux4_io10: IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 { + pinmux = <0x400e81b8 5 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpspi4_pcs0: IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 { + pinmux = <0x400e81b8 4 0x400e860c 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpuart9_rx: IOMUXC_GPIO_SD_B2_01_LPUART9_RX { + pinmux = <0x400e81b8 3 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_usdhc2_data2: IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 { + pinmux = <0x400e81b8 0 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_enet_1g_rdata00: IOMUXC_GPIO_SD_B2_02_ENET_1G_RDATA00 { + pinmux = <0x400e81bc 2 0x400e84d0 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_flexspi1_b_data01: IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 { + pinmux = <0x400e81bc 1 0x400e8568 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio10_io11: IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 { + pinmux = <0x400e81bc 10 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio_mux4_io11: IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 { + pinmux = <0x400e81bc 5 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpspi4_sdo: IOMUXC_GPIO_SD_B2_02_LPSPI4_SDO { + pinmux = <0x400e81bc 4 0x400e8618 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpuart9_cts_b: IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B { + pinmux = <0x400e81bc 3 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_usdhc2_data1: IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 { + pinmux = <0x400e81bc 0 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_enet_1g_rdata01: IOMUXC_GPIO_SD_B2_03_ENET_1G_RDATA01 { + pinmux = <0x400e81c0 2 0x400e84d4 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_flexspi1_b_data00: IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 { + pinmux = <0x400e81c0 1 0x400e8564 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio10_io12: IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 { + pinmux = <0x400e81c0 10 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio_mux4_io12: IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 { + pinmux = <0x400e81c0 5 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpspi4_sdi: IOMUXC_GPIO_SD_B2_03_LPSPI4_SDI { + pinmux = <0x400e81c0 4 0x400e8614 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpuart9_rts_b: IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B { + pinmux = <0x400e81c0 3 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_usdhc2_data0: IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 { + pinmux = <0x400e81c0 0 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_enet_1g_rdata02: IOMUXC_GPIO_SD_B2_04_ENET_1G_RDATA02 { + pinmux = <0x400e81c4 2 0x400e84d8 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81c4 3 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_b_sclk: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK { + pinmux = <0x400e81c4 1 0x400e8578 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio10_io13: IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 { + pinmux = <0x400e81c4 10 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio_mux4_io13: IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 { + pinmux = <0x400e81c4 5 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_lpspi4_pcs1: IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 { + pinmux = <0x400e81c4 4 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_usdhc2_clk: IOMUXC_GPIO_SD_B2_04_USDHC2_CLK { + pinmux = <0x400e81c4 0 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_enet_1g_rdata03: IOMUXC_GPIO_SD_B2_05_ENET_1G_RDATA03 { + pinmux = <0x400e81c8 2 0x400e84dc 1 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_a_dqs: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS { + pinmux = <0x400e81c8 1 0x400e8550 2 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81c8 3 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio10_io14: IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 { + pinmux = <0x400e81c8 10 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio_mux4_io14: IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 { + pinmux = <0x400e81c8 5 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_lpspi4_pcs2: IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 { + pinmux = <0x400e81c8 4 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_usdhc2_cmd: IOMUXC_GPIO_SD_B2_05_USDHC2_CMD { + pinmux = <0x400e81c8 0 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_enet_1g_tdata03: IOMUXC_GPIO_SD_B2_06_ENET_1G_TDATA03 { + pinmux = <0x400e81cc 2 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_flexspi1_a_ss0_b: IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B { + pinmux = <0x400e81cc 1 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio10_io15: IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 { + pinmux = <0x400e81cc 10 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio_mux4_io15: IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 { + pinmux = <0x400e81cc 5 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpt6_capture1: IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 { + pinmux = <0x400e81cc 4 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_lpspi4_pcs3: IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 { + pinmux = <0x400e81cc 3 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B { + pinmux = <0x400e81cc 0 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_1g_tdata02: IOMUXC_GPIO_SD_B2_07_ENET_1G_TDATA02 { + pinmux = <0x400e81d0 2 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_tx_er: IOMUXC_GPIO_SD_B2_07_ENET_TX_ER { + pinmux = <0x400e81d0 8 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_flexspi1_a_sclk: IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK { + pinmux = <0x400e81d0 1 0x400e8574 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio10_io16: IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 { + pinmux = <0x400e81d0 10 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio_mux4_io16: IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 { + pinmux = <0x400e81d0 5 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpt6_capture2: IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 { + pinmux = <0x400e81d0 4 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpspi2_sck: IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK { + pinmux = <0x400e81d0 6 0x400e85e4 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpuart3_cts_b: IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B { + pinmux = <0x400e81d0 3 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_usdhc2_strobe: IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE { + pinmux = <0x400e81d0 0 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_enet_1g_tdata01: IOMUXC_GPIO_SD_B2_08_ENET_1G_TDATA01 { + pinmux = <0x400e81d4 2 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_flexspi1_a_data00: IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 { + pinmux = <0x400e81d4 1 0x400e8554 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio10_io17: IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 { + pinmux = <0x400e81d4 10 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio_mux4_io17: IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 { + pinmux = <0x400e81d4 5 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpt6_compare1: IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 { + pinmux = <0x400e81d4 4 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpspi2_pcs0: IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 { + pinmux = <0x400e81d4 6 0x400e85dc 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpuart3_rts_b: IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B { + pinmux = <0x400e81d4 3 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_usdhc2_data4: IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 { + pinmux = <0x400e81d4 0 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_enet_1g_tdata00: IOMUXC_GPIO_SD_B2_09_ENET_1G_TDATA00 { + pinmux = <0x400e81d8 2 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_flexspi1_a_data01: IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 { + pinmux = <0x400e81d8 1 0x400e8558 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio10_io18: IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 { + pinmux = <0x400e81d8 10 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio_mux4_io18: IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 { + pinmux = <0x400e81d8 5 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpt6_compare2: IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 { + pinmux = <0x400e81d8 4 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpspi2_sdo: IOMUXC_GPIO_SD_B2_09_LPSPI2_SDO { + pinmux = <0x400e81d8 6 0x400e85ec 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpuart5_cts_b: IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B { + pinmux = <0x400e81d8 3 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_usdhc2_data5: IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 { + pinmux = <0x400e81d8 0 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_enet_1g_tx_en: IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN { + pinmux = <0x400e81dc 2 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_flexspi1_a_data02: IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 { + pinmux = <0x400e81dc 1 0x400e855c 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio10_io19: IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 { + pinmux = <0x400e81dc 10 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio_mux4_io19: IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 { + pinmux = <0x400e81dc 5 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpt6_compare3: IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 { + pinmux = <0x400e81dc 4 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpspi2_sdi: IOMUXC_GPIO_SD_B2_10_LPSPI2_SDI { + pinmux = <0x400e81dc 6 0x400e85e8 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpuart5_rts_b: IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B { + pinmux = <0x400e81dc 3 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_usdhc2_data6: IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 { + pinmux = <0x400e81dc 0 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_ref_clk1: IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e81e0 3 0x400e84c4 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_tx_clk_io: IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e81e0 2 0x400e84e8 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_flexspi1_a_data03: IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 { + pinmux = <0x400e81e0 1 0x400e8560 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio10_io20: IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 { + pinmux = <0x400e81e0 10 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio_mux4_io20: IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 { + pinmux = <0x400e81e0 5 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpt6_clk: IOMUXC_GPIO_SD_B2_11_GPT6_CLK { + pinmux = <0x400e81e0 4 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_lpspi2_pcs1: IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 { + pinmux = <0x400e81e0 6 0x400e85e0 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_usdhc2_data7: IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 { + pinmux = <0x400e81e0 0 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03: IOMUXC_SNVS_GPIO_SNVS_00_DIG_GPIO13_IO03 { + pinmux = <0x40c9400c 5 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_snvs_lp_tamper00: IOMUXC_SNVS_GPIO_SNVS_00_DIG_SNVS_LP_TAMPER00 { + pinmux = <0x40c9400c 0 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04: IOMUXC_SNVS_GPIO_SNVS_01_DIG_GPIO13_IO04 { + pinmux = <0x40c94010 5 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_snvs_lp_tamper01: IOMUXC_SNVS_GPIO_SNVS_01_DIG_SNVS_LP_TAMPER01 { + pinmux = <0x40c94010 0 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05: IOMUXC_SNVS_GPIO_SNVS_02_DIG_GPIO13_IO05 { + pinmux = <0x40c94014 5 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_snvs_lp_tamper02: IOMUXC_SNVS_GPIO_SNVS_02_DIG_SNVS_LP_TAMPER02 { + pinmux = <0x40c94014 0 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06: IOMUXC_SNVS_GPIO_SNVS_03_DIG_GPIO13_IO06 { + pinmux = <0x40c94018 5 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_snvs_lp_tamper03: IOMUXC_SNVS_GPIO_SNVS_03_DIG_SNVS_LP_TAMPER03 { + pinmux = <0x40c94018 0 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07: IOMUXC_SNVS_GPIO_SNVS_04_DIG_GPIO13_IO07 { + pinmux = <0x40c9401c 5 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_snvs_lp_tamper04: IOMUXC_SNVS_GPIO_SNVS_04_DIG_SNVS_LP_TAMPER04 { + pinmux = <0x40c9401c 0 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08: IOMUXC_SNVS_GPIO_SNVS_05_DIG_GPIO13_IO08 { + pinmux = <0x40c94020 5 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_snvs_lp_tamper05: IOMUXC_SNVS_GPIO_SNVS_05_DIG_SNVS_LP_TAMPER05 { + pinmux = <0x40c94020 0 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09: IOMUXC_SNVS_GPIO_SNVS_06_DIG_GPIO13_IO09 { + pinmux = <0x40c94024 5 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_snvs_lp_tamper06: IOMUXC_SNVS_GPIO_SNVS_06_DIG_SNVS_LP_TAMPER06 { + pinmux = <0x40c94024 0 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10: IOMUXC_SNVS_GPIO_SNVS_07_DIG_GPIO13_IO10 { + pinmux = <0x40c94028 5 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_snvs_lp_tamper07: IOMUXC_SNVS_GPIO_SNVS_07_DIG_SNVS_LP_TAMPER07 { + pinmux = <0x40c94028 0 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11: IOMUXC_SNVS_GPIO_SNVS_08_DIG_GPIO13_IO11 { + pinmux = <0x40c9402c 5 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_snvs_lp_tamper08: IOMUXC_SNVS_GPIO_SNVS_08_DIG_SNVS_LP_TAMPER08 { + pinmux = <0x40c9402c 0 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12: IOMUXC_SNVS_GPIO_SNVS_09_DIG_GPIO13_IO12 { + pinmux = <0x40c94030 5 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_snvs_lp_tamper09: IOMUXC_SNVS_GPIO_SNVS_09_DIG_SNVS_LP_TAMPER09 { + pinmux = <0x40c94030 0 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_dig_src_reset_b: IOMUXC_SNVS_ONOFF_DIG_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x40c9403c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_gpio13_io01: IOMUXC_SNVS_PMIC_ON_REQ_DIG_GPIO13_IO01 { + pinmux = <0x40c94004 5 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_snvs_lp_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ { + pinmux = <0x40c94004 0 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_gpio13_io02: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_GPIO13_IO02 { + pinmux = <0x40c94008 5 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_pgmc_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_PGMC_PMIC_VSTBY_REQ { + pinmux = <0x40c94008 0 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_dig_src_por_b: IOMUXC_SNVS_POR_B_DIG_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x40c94038>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_dig_test_mode: IOMUXC_SNVS_TEST_MODE_DIG_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x40c94034>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_dig_gpio13_io00: IOMUXC_SNVS_WAKEUP_DIG_GPIO13_IO00 { + pinmux = <0x40c94000 5 0x0 0 0x40c94040>; + pin-snvs; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1172cvm8a-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1172cvm8a-pinctrl.dtsi new file mode 100644 index 000000000..81a219c49 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1172cvm8a-pinctrl.dtsi @@ -0,0 +1,6212 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1172CVM8A + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_00_acmp1_in1: IOMUXC_GPIO_AD_00_ACMP1_IN1 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_can2_tx: IOMUXC_GPIO_AD_00_CAN2_TX { + pinmux = <0x400e810c 1 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_enet_1g_1588_event1_in: IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN { + pinmux = <0x400e810c 2 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexio2_flexio00: IOMUXC_GPIO_AD_00_FLEXIO2_FLEXIO00 { + pinmux = <0x400e810c 8 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexpwm1_pwm0_a: IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A { + pinmux = <0x400e810c 4 0x400e8500 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexspi2_b_ss1_b: IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B { + pinmux = <0x400e810c 9 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio8_io31: IOMUXC_GPIO_AD_00_GPIO8_IO31 { + pinmux = <0x400e810c 10 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31_cm7: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31_CM7 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpt2_capture1: IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 { + pinmux = <0x400e810c 3 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_lpuart7_tx: IOMUXC_GPIO_AD_00_LPUART7_TX { + pinmux = <0x400e810c 6 0x400e8630 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_sim1_trxd: IOMUXC_GPIO_AD_00_SIM1_TRXD { + pinmux = <0x400e810c 0 0x400e869c 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_acmp1_in2: IOMUXC_GPIO_AD_01_ACMP1_IN2 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_can2_rx: IOMUXC_GPIO_AD_01_CAN2_RX { + pinmux = <0x400e8110 1 0x400e849c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_enet_1g_1588_event1_out: IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT { + pinmux = <0x400e8110 2 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexio2_flexio01: IOMUXC_GPIO_AD_01_FLEXIO2_FLEXIO01 { + pinmux = <0x400e8110 8 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexpwm1_pwm0_b: IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B { + pinmux = <0x400e8110 4 0x400e850c 1 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexspi2_a_ss1_b: IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B { + pinmux = <0x400e8110 9 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio9_io00: IOMUXC_GPIO_AD_01_GPIO9_IO00 { + pinmux = <0x400e8110 10 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00_cm7: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00_CM7 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpt2_capture2: IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 { + pinmux = <0x400e8110 3 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_lpuart7_rx: IOMUXC_GPIO_AD_01_LPUART7_RX { + pinmux = <0x400e8110 6 0x400e862c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_sim1_clk: IOMUXC_GPIO_AD_01_SIM1_CLK { + pinmux = <0x400e8110 0 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_acmp1_in3: IOMUXC_GPIO_AD_02_ACMP1_IN3 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_enet_1g_1588_event2_in: IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN { + pinmux = <0x400e8114 2 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexio2_flexio02: IOMUXC_GPIO_AD_02_FLEXIO2_FLEXIO02 { + pinmux = <0x400e8114 8 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexpwm1_pwm1_a: IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A { + pinmux = <0x400e8114 4 0x400e8504 1 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio9_io01: IOMUXC_GPIO_AD_02_GPIO9_IO01 { + pinmux = <0x400e8114 10 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01_cm7: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01_CM7 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpt2_compare1: IOMUXC_GPIO_AD_02_GPT2_COMPARE1 { + pinmux = <0x400e8114 3 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart7_cts_b: IOMUXC_GPIO_AD_02_LPUART7_CTS_B { + pinmux = <0x400e8114 1 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart8_tx: IOMUXC_GPIO_AD_02_LPUART8_TX { + pinmux = <0x400e8114 6 0x400e8638 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_sim1_rst_b: IOMUXC_GPIO_AD_02_SIM1_RST_B { + pinmux = <0x400e8114 0 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_video_mux_ext_dcic1: IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e8114 9 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_acmp1_in4: IOMUXC_GPIO_AD_03_ACMP1_IN4 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_enet_1g_1588_event2_out: IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT { + pinmux = <0x400e8118 2 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexio2_flexio03: IOMUXC_GPIO_AD_03_FLEXIO2_FLEXIO03 { + pinmux = <0x400e8118 8 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexpwm1_pwm1_b: IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B { + pinmux = <0x400e8118 4 0x400e8510 1 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio9_io02: IOMUXC_GPIO_AD_03_GPIO9_IO02 { + pinmux = <0x400e8118 10 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02_cm7: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02_CM7 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpt2_compare2: IOMUXC_GPIO_AD_03_GPT2_COMPARE2 { + pinmux = <0x400e8118 3 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart7_rts_b: IOMUXC_GPIO_AD_03_LPUART7_RTS_B { + pinmux = <0x400e8118 1 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart8_rx: IOMUXC_GPIO_AD_03_LPUART8_RX { + pinmux = <0x400e8118 6 0x400e8634 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_sim1_sven: IOMUXC_GPIO_AD_03_SIM1_SVEN { + pinmux = <0x400e8118 0 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_video_mux_ext_dcic2: IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8118 9 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_acmp2_in1: IOMUXC_GPIO_AD_04_ACMP2_IN1 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_enet_1g_1588_event3_in: IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN { + pinmux = <0x400e811c 2 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexio2_flexio04: IOMUXC_GPIO_AD_04_FLEXIO2_FLEXIO04 { + pinmux = <0x400e811c 8 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexpwm1_pwm2_a: IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A { + pinmux = <0x400e811c 4 0x400e8508 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio9_io03: IOMUXC_GPIO_AD_04_GPIO9_IO03 { + pinmux = <0x400e811c 10 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03_cm7: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03_CM7 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpt2_compare3: IOMUXC_GPIO_AD_04_GPT2_COMPARE3 { + pinmux = <0x400e811c 3 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_lpuart8_cts_b: IOMUXC_GPIO_AD_04_LPUART8_CTS_B { + pinmux = <0x400e811c 1 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_qtimer4_timer0: IOMUXC_GPIO_AD_04_QTIMER4_TIMER0 { + pinmux = <0x400e811c 9 0x400e8660 1 0x400e8360>; + pin-pue; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_sim1_pd: IOMUXC_GPIO_AD_04_SIM1_PD { + pinmux = <0x400e811c 0 0x400e86a0 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_wdog1_wdog_b: IOMUXC_GPIO_AD_04_WDOG1_WDOG_B { + pinmux = <0x400e811c 6 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_acmp2_in2: IOMUXC_GPIO_AD_05_ACMP2_IN2 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_enet_1g_1588_event3_out: IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT { + pinmux = <0x400e8120 2 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexio2_flexio05: IOMUXC_GPIO_AD_05_FLEXIO2_FLEXIO05 { + pinmux = <0x400e8120 8 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexpwm1_pwm2_b: IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B { + pinmux = <0x400e8120 4 0x400e8514 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio9_io04: IOMUXC_GPIO_AD_05_GPIO9_IO04 { + pinmux = <0x400e8120 10 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04_cm7: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04_CM7 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpt2_clk: IOMUXC_GPIO_AD_05_GPT2_CLK { + pinmux = <0x400e8120 3 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_lpuart8_rts_b: IOMUXC_GPIO_AD_05_LPUART8_RTS_B { + pinmux = <0x400e8120 1 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_qtimer4_timer1: IOMUXC_GPIO_AD_05_QTIMER4_TIMER1 { + pinmux = <0x400e8120 9 0x400e8664 1 0x400e8364>; + pin-pue; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_sim1_power_fail: IOMUXC_GPIO_AD_05_SIM1_POWER_FAIL { + pinmux = <0x400e8120 0 0x400e86a4 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_wdog2_wdog_b: IOMUXC_GPIO_AD_05_WDOG2_WDOG_B { + pinmux = <0x400e8120 6 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_adc1_ch0a: IOMUXC_GPIO_AD_06_ADC1_CH0A { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_can1_tx: IOMUXC_GPIO_AD_06_CAN1_TX { + pinmux = <0x400e8124 1 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_enet_1588_event1_in: IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN { + pinmux = <0x400e8124 6 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexio2_flexio06: IOMUXC_GPIO_AD_06_FLEXIO2_FLEXIO06 { + pinmux = <0x400e8124 8 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexpwm1_pwm0_x: IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X { + pinmux = <0x400e8124 11 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio9_io05: IOMUXC_GPIO_AD_06_GPIO9_IO05 { + pinmux = <0x400e8124 10 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05_cm7: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05_CM7 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpt3_capture1: IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 { + pinmux = <0x400e8124 3 0x400e8590 1 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_qtimer4_timer2: IOMUXC_GPIO_AD_06_QTIMER4_TIMER2 { + pinmux = <0x400e8124 9 0x400e8668 0 0x400e8368>; + pin-pue; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_sim2_trxd: IOMUXC_GPIO_AD_06_SIM2_TRXD { + pinmux = <0x400e8124 2 0x400e86a8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_usb_otg2_oc: IOMUXC_GPIO_AD_06_USB_OTG2_OC { + pinmux = <0x400e8124 0 0x400e86b8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_video_mux_csi_data15: IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 { + pinmux = <0x400e8124 4 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_adc1_ch0b: IOMUXC_GPIO_AD_07_ADC1_CH0B { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_can1_rx: IOMUXC_GPIO_AD_07_CAN1_RX { + pinmux = <0x400e8128 1 0x400e8498 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_enet_1588_event1_out: IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT { + pinmux = <0x400e8128 6 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexio2_flexio07: IOMUXC_GPIO_AD_07_FLEXIO2_FLEXIO07 { + pinmux = <0x400e8128 8 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexpwm1_pwm1_x: IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X { + pinmux = <0x400e8128 11 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio9_io06: IOMUXC_GPIO_AD_07_GPIO9_IO06 { + pinmux = <0x400e8128 10 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06_cm7: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06_CM7 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpt3_capture2: IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 { + pinmux = <0x400e8128 3 0x400e8594 1 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_qtimer4_timer3: IOMUXC_GPIO_AD_07_QTIMER4_TIMER3 { + pinmux = <0x400e8128 9 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e403c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_sim2_clk: IOMUXC_GPIO_AD_07_SIM2_CLK { + pinmux = <0x400e8128 2 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_usb_otg2_pwr: IOMUXC_GPIO_AD_07_USB_OTG2_PWR { + pinmux = <0x400e8128 0 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_video_mux_csi_data14: IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 { + pinmux = <0x400e8128 4 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_adc1_ch1a: IOMUXC_GPIO_AD_08_ADC1_CH1A { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_enet_1588_event2_in: IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN { + pinmux = <0x400e812c 6 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexio2_flexio08: IOMUXC_GPIO_AD_08_FLEXIO2_FLEXIO08 { + pinmux = <0x400e812c 8 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexpwm1_pwm2_x: IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X { + pinmux = <0x400e812c 11 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio9_io07: IOMUXC_GPIO_AD_08_GPIO9_IO07 { + pinmux = <0x400e812c 10 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07_cm7: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07_CM7 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpt3_compare1: IOMUXC_GPIO_AD_08_GPT3_COMPARE1 { + pinmux = <0x400e812c 3 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_lpi2c1_scl: IOMUXC_GPIO_AD_08_LPI2C1_SCL { + pinmux = <0x400e812c 1 0x400e85ac 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_sim2_rst_b: IOMUXC_GPIO_AD_08_SIM2_RST_B { + pinmux = <0x400e812c 2 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_usbphy2_otg_id: IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID { + pinmux = <0x400e812c 0 0x400e86c4 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_video_mux_csi_data13: IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 { + pinmux = <0x400e812c 4 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_adc1_ch1b: IOMUXC_GPIO_AD_09_ADC1_CH1B { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_enet_1588_event2_out: IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT { + pinmux = <0x400e8130 6 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexio2_flexio09: IOMUXC_GPIO_AD_09_FLEXIO2_FLEXIO09 { + pinmux = <0x400e8130 8 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexpwm1_pwm3_x: IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X { + pinmux = <0x400e8130 11 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio9_io08: IOMUXC_GPIO_AD_09_GPIO9_IO08 { + pinmux = <0x400e8130 10 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08_cm7: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08_CM7 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpt3_compare2: IOMUXC_GPIO_AD_09_GPT3_COMPARE2 { + pinmux = <0x400e8130 3 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_lpi2c1_sda: IOMUXC_GPIO_AD_09_LPI2C1_SDA { + pinmux = <0x400e8130 1 0x400e85b0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_sim2_sven: IOMUXC_GPIO_AD_09_SIM2_SVEN { + pinmux = <0x400e8130 2 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_usbphy1_otg_id: IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID { + pinmux = <0x400e8130 0 0x400e86c0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_video_mux_csi_data12: IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 { + pinmux = <0x400e8130 4 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_adc1_ch2a: IOMUXC_GPIO_AD_10_ADC1_CH2A { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_enet_1588_event3_in: IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN { + pinmux = <0x400e8134 6 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexio2_flexio10: IOMUXC_GPIO_AD_10_FLEXIO2_FLEXIO10 { + pinmux = <0x400e8134 8 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexpwm2_pwm0_x: IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X { + pinmux = <0x400e8134 11 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio9_io09: IOMUXC_GPIO_AD_10_GPIO9_IO09 { + pinmux = <0x400e8134 10 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09_cm7: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09_CM7 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpt3_compare3: IOMUXC_GPIO_AD_10_GPT3_COMPARE3 { + pinmux = <0x400e8134 3 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_lpi2c1_scls: IOMUXC_GPIO_AD_10_LPI2C1_SCLS { + pinmux = <0x400e8134 1 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_sim2_pd: IOMUXC_GPIO_AD_10_SIM2_PD { + pinmux = <0x400e8134 2 0x400e86ac 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_usb_otg1_pwr: IOMUXC_GPIO_AD_10_USB_OTG1_PWR { + pinmux = <0x400e8134 0 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_video_mux_csi_data11: IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 { + pinmux = <0x400e8134 4 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_adc1_ch2b: IOMUXC_GPIO_AD_11_ADC1_CH2B { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_enet_1588_event3_out: IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT { + pinmux = <0x400e8138 6 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexio2_flexio11: IOMUXC_GPIO_AD_11_FLEXIO2_FLEXIO11 { + pinmux = <0x400e8138 8 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexpwm2_pwm1_x: IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X { + pinmux = <0x400e8138 11 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio9_io10: IOMUXC_GPIO_AD_11_GPIO9_IO10 { + pinmux = <0x400e8138 10 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10_cm7: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10_CM7 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpt3_clk: IOMUXC_GPIO_AD_11_GPT3_CLK { + pinmux = <0x400e8138 3 0x400e8598 1 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_lpi2c1_sdas: IOMUXC_GPIO_AD_11_LPI2C1_SDAS { + pinmux = <0x400e8138 1 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_sim2_power_fail: IOMUXC_GPIO_AD_11_SIM2_POWER_FAIL { + pinmux = <0x400e8138 2 0x400e86b0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_usb_otg1_oc: IOMUXC_GPIO_AD_11_USB_OTG1_OC { + pinmux = <0x400e8138 0 0x400e86bc 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_video_mux_csi_data10: IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 { + pinmux = <0x400e8138 4 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc1_ch3a: IOMUXC_GPIO_AD_12_ADC1_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc2_ch3a: IOMUXC_GPIO_AD_12_ADC2_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_enet_tdata03: IOMUXC_GPIO_AD_12_ENET_TDATA03 { + pinmux = <0x400e813c 6 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_ewm_ewm_out_b: IOMUXC_GPIO_AD_12_EWM_EWM_OUT_B { + pinmux = <0x400e813c 9 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexio2_flexio12: IOMUXC_GPIO_AD_12_FLEXIO2_FLEXIO12 { + pinmux = <0x400e813c 8 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexpwm2_pwm2_x: IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X { + pinmux = <0x400e813c 11 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexspi1_b_data03: IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 { + pinmux = <0x400e813c 3 0x400e8570 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio9_io11: IOMUXC_GPIO_AD_12_GPIO9_IO11 { + pinmux = <0x400e813c 10 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11_cm7: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11_CM7 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpt1_capture1: IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 { + pinmux = <0x400e813c 2 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_lpi2c1_hreq: IOMUXC_GPIO_AD_12_LPI2C1_HREQ { + pinmux = <0x400e813c 1 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_spdif_lock: IOMUXC_GPIO_AD_12_SPDIF_LOCK { + pinmux = <0x400e813c 0 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_video_mux_csi_pixclk: IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK { + pinmux = <0x400e813c 4 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc1_ch3b: IOMUXC_GPIO_AD_13_ADC1_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc2_ch3b: IOMUXC_GPIO_AD_13_ADC2_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_enet_tdata02: IOMUXC_GPIO_AD_13_ENET_TDATA02 { + pinmux = <0x400e8140 6 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexio2_flexio13: IOMUXC_GPIO_AD_13_FLEXIO2_FLEXIO13 { + pinmux = <0x400e8140 8 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexpwm2_pwm3_x: IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X { + pinmux = <0x400e8140 11 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexspi1_b_data02: IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 { + pinmux = <0x400e8140 3 0x400e856c 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio9_io12: IOMUXC_GPIO_AD_13_GPIO9_IO12 { + pinmux = <0x400e8140 10 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12_cm7: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12_CM7 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpt1_capture2: IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 { + pinmux = <0x400e8140 2 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_pit1_trigger00: IOMUXC_GPIO_AD_13_PIT1_TRIGGER00 { + pinmux = <0x400e8140 1 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_spdif_sr_clk: IOMUXC_GPIO_AD_13_SPDIF_SR_CLK { + pinmux = <0x400e8140 0 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_video_mux_csi_mclk: IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK { + pinmux = <0x400e8140 4 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc1_ch4a: IOMUXC_GPIO_AD_14_ADC1_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc2_ch4a: IOMUXC_GPIO_AD_14_ADC2_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_ccm_enet_ref_clk_25m: IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8144 9 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_enet_rx_clk: IOMUXC_GPIO_AD_14_ENET_RX_CLK { + pinmux = <0x400e8144 6 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexio2_flexio14: IOMUXC_GPIO_AD_14_FLEXIO2_FLEXIO14 { + pinmux = <0x400e8144 8 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexpwm3_pwm0_x: IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X { + pinmux = <0x400e8144 11 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexspi1_b_data01: IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 { + pinmux = <0x400e8144 3 0x400e8568 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio9_io13: IOMUXC_GPIO_AD_14_GPIO9_IO13 { + pinmux = <0x400e8144 10 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13_cm7: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13_CM7 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpt1_compare1: IOMUXC_GPIO_AD_14_GPT1_COMPARE1 { + pinmux = <0x400e8144 2 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_spdif_ext_clk: IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK { + pinmux = <0x400e8144 0 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_video_mux_csi_vsync: IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC { + pinmux = <0x400e8144 4 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc1_ch4b: IOMUXC_GPIO_AD_15_ADC1_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc2_ch4b: IOMUXC_GPIO_AD_15_ADC2_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_enet_tx_er: IOMUXC_GPIO_AD_15_ENET_TX_ER { + pinmux = <0x400e8148 6 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexio2_flexio15: IOMUXC_GPIO_AD_15_FLEXIO2_FLEXIO15 { + pinmux = <0x400e8148 8 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexpwm3_pwm1_x: IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X { + pinmux = <0x400e8148 11 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexspi1_b_data00: IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 { + pinmux = <0x400e8148 3 0x400e8564 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio9_io14: IOMUXC_GPIO_AD_15_GPIO9_IO14 { + pinmux = <0x400e8148 10 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14_cm7: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14_CM7 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpt1_compare2: IOMUXC_GPIO_AD_15_GPT1_COMPARE2 { + pinmux = <0x400e8148 2 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_lpuart10_tx: IOMUXC_GPIO_AD_15_LPUART10_TX { + pinmux = <0x400e8148 1 0x400e8628 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_spdif_in: IOMUXC_GPIO_AD_15_SPDIF_IN { + pinmux = <0x400e8148 0 0x400e86b4 1 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_video_mux_csi_hsync: IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC { + pinmux = <0x400e8148 4 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc1_ch5a: IOMUXC_GPIO_AD_16_ADC1_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc2_ch5a: IOMUXC_GPIO_AD_16_ADC2_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_1g_mdc: IOMUXC_GPIO_AD_16_ENET_1G_MDC { + pinmux = <0x400e814c 9 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_rdata03: IOMUXC_GPIO_AD_16_ENET_RDATA03 { + pinmux = <0x400e814c 6 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexio2_flexio16: IOMUXC_GPIO_AD_16_FLEXIO2_FLEXIO16 { + pinmux = <0x400e814c 8 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexpwm3_pwm2_x: IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X { + pinmux = <0x400e814c 11 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexspi1_b_sclk: IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK { + pinmux = <0x400e814c 3 0x400e8578 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio9_io15: IOMUXC_GPIO_AD_16_GPIO9_IO15 { + pinmux = <0x400e814c 10 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15_cm7: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15_CM7 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpt1_compare3: IOMUXC_GPIO_AD_16_GPT1_COMPARE3 { + pinmux = <0x400e814c 2 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_lpuart10_rx: IOMUXC_GPIO_AD_16_LPUART10_RX { + pinmux = <0x400e814c 1 0x400e8624 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_spdif_out: IOMUXC_GPIO_AD_16_SPDIF_OUT { + pinmux = <0x400e814c 0 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_video_mux_csi_data09: IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 { + pinmux = <0x400e814c 4 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_acmp1_cmpo: IOMUXC_GPIO_AD_17_ACMP1_CMPO { + pinmux = <0x400e8150 1 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc1_ch5b: IOMUXC_GPIO_AD_17_ADC1_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc2_ch5b: IOMUXC_GPIO_AD_17_ADC2_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_1g_mdio: IOMUXC_GPIO_AD_17_ENET_1G_MDIO { + pinmux = <0x400e8150 9 0x400e84c8 2 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_rdata02: IOMUXC_GPIO_AD_17_ENET_RDATA02 { + pinmux = <0x400e8150 6 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexio2_flexio17: IOMUXC_GPIO_AD_17_FLEXIO2_FLEXIO17 { + pinmux = <0x400e8150 8 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexpwm3_pwm3_x: IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X { + pinmux = <0x400e8150 11 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexspi1_a_dqs: IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS { + pinmux = <0x400e8150 3 0x400e8550 1 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio9_io16: IOMUXC_GPIO_AD_17_GPIO9_IO16 { + pinmux = <0x400e8150 10 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16_cm7: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16_CM7 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpt1_clk: IOMUXC_GPIO_AD_17_GPT1_CLK { + pinmux = <0x400e8150 2 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_sai1_mclk: IOMUXC_GPIO_AD_17_SAI1_MCLK { + pinmux = <0x400e8150 0 0x400e866c 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_video_mux_csi_data08: IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 { + pinmux = <0x400e8150 4 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_acmp2_cmpo: IOMUXC_GPIO_AD_18_ACMP2_CMPO { + pinmux = <0x400e8154 1 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_adc2_ch0a: IOMUXC_GPIO_AD_18_ADC2_CH0A { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_enet_crs: IOMUXC_GPIO_AD_18_ENET_CRS { + pinmux = <0x400e8154 6 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexio2_flexio18: IOMUXC_GPIO_AD_18_FLEXIO2_FLEXIO18 { + pinmux = <0x400e8154 8 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexpwm4_pwm0_x: IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X { + pinmux = <0x400e8154 11 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexspi1_a_ss0_b: IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B { + pinmux = <0x400e8154 3 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio9_io17: IOMUXC_GPIO_AD_18_GPIO9_IO17 { + pinmux = <0x400e8154 10 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17_cm7: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17_CM7 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpi2c2_scl: IOMUXC_GPIO_AD_18_LPI2C2_SCL { + pinmux = <0x400e8154 9 0x400e85b4 1 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpspi1_pcs1: IOMUXC_GPIO_AD_18_LPSPI1_PCS1 { + pinmux = <0x400e8154 2 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_sai1_rx_sync: IOMUXC_GPIO_AD_18_SAI1_RX_SYNC { + pinmux = <0x400e8154 0 0x400e8678 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_video_mux_csi_data07: IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 { + pinmux = <0x400e8154 4 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_acmp3_cmpo: IOMUXC_GPIO_AD_19_ACMP3_CMPO { + pinmux = <0x400e8158 1 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_adc2_ch0b: IOMUXC_GPIO_AD_19_ADC2_CH0B { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_enet_col: IOMUXC_GPIO_AD_19_ENET_COL { + pinmux = <0x400e8158 6 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexio2_flexio19: IOMUXC_GPIO_AD_19_FLEXIO2_FLEXIO19 { + pinmux = <0x400e8158 8 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexpwm4_pwm1_x: IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X { + pinmux = <0x400e8158 11 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexspi1_a_sclk: IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK { + pinmux = <0x400e8158 3 0x400e8574 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio9_io18: IOMUXC_GPIO_AD_19_GPIO9_IO18 { + pinmux = <0x400e8158 10 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18_cm7: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18_CM7 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpi2c2_sda: IOMUXC_GPIO_AD_19_LPI2C2_SDA { + pinmux = <0x400e8158 9 0x400e85b8 1 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpspi1_pcs2: IOMUXC_GPIO_AD_19_LPSPI1_PCS2 { + pinmux = <0x400e8158 2 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_sai1_rx_bclk: IOMUXC_GPIO_AD_19_SAI1_RX_BCLK { + pinmux = <0x400e8158 0 0x400e8670 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_video_mux_csi_data06: IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 { + pinmux = <0x400e8158 4 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_acmp4_cmpo: IOMUXC_GPIO_AD_20_ACMP4_CMPO { + pinmux = <0x400e815c 1 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_adc2_ch1a: IOMUXC_GPIO_AD_20_ADC2_CH1A { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexio2_flexio20: IOMUXC_GPIO_AD_20_FLEXIO2_FLEXIO20 { + pinmux = <0x400e815c 8 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexpwm4_pwm2_x: IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X { + pinmux = <0x400e815c 11 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexspi1_a_data00: IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 { + pinmux = <0x400e815c 3 0x400e8554 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio9_io19: IOMUXC_GPIO_AD_20_GPIO9_IO19 { + pinmux = <0x400e815c 10 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19_cm7: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19_CM7 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_kpp_row07: IOMUXC_GPIO_AD_20_KPP_ROW07 { + pinmux = <0x400e815c 6 0x400e85a8 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_lpspi1_pcs3: IOMUXC_GPIO_AD_20_LPSPI1_PCS3 { + pinmux = <0x400e815c 2 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_sai1_rx_data00: IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 { + pinmux = <0x400e815c 0 0x400e8674 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_video_mux_csi_data05: IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 { + pinmux = <0x400e815c 4 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_adc2_ch1b: IOMUXC_GPIO_AD_21_ADC2_CH1B { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexio2_flexio21: IOMUXC_GPIO_AD_21_FLEXIO2_FLEXIO21 { + pinmux = <0x400e8160 8 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexpwm4_pwm3_x: IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X { + pinmux = <0x400e8160 11 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexspi1_a_data01: IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 { + pinmux = <0x400e8160 3 0x400e8558 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio9_io20: IOMUXC_GPIO_AD_21_GPIO9_IO20 { + pinmux = <0x400e8160 10 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20_cm7: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20_CM7 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_kpp_col07: IOMUXC_GPIO_AD_21_KPP_COL07 { + pinmux = <0x400e8160 6 0x400e85a0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_lpspi2_pcs1: IOMUXC_GPIO_AD_21_LPSPI2_PCS1 { + pinmux = <0x400e8160 2 0x400e85e0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_sai1_tx_data00: IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 { + pinmux = <0x400e8160 0 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_video_mux_csi_data04: IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 { + pinmux = <0x400e8160 4 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_adc2_ch2a: IOMUXC_GPIO_AD_22_ADC2_CH2A { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexio2_flexio22: IOMUXC_GPIO_AD_22_FLEXIO2_FLEXIO22 { + pinmux = <0x400e8164 8 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexspi1_a_data02: IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 { + pinmux = <0x400e8164 3 0x400e855c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio9_io21: IOMUXC_GPIO_AD_22_GPIO9_IO21 { + pinmux = <0x400e8164 10 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21_cm7: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21_CM7 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_kpp_row06: IOMUXC_GPIO_AD_22_KPP_ROW06 { + pinmux = <0x400e8164 6 0x400e85a4 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_lpspi2_pcs2: IOMUXC_GPIO_AD_22_LPSPI2_PCS2 { + pinmux = <0x400e8164 2 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_sai1_tx_bclk: IOMUXC_GPIO_AD_22_SAI1_TX_BCLK { + pinmux = <0x400e8164 0 0x400e867c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_video_mux_csi_data03: IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 { + pinmux = <0x400e8164 4 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_adc2_ch2b: IOMUXC_GPIO_AD_23_ADC2_CH2B { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexio2_flexio23: IOMUXC_GPIO_AD_23_FLEXIO2_FLEXIO23 { + pinmux = <0x400e8168 8 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexspi1_a_data03: IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 { + pinmux = <0x400e8168 3 0x400e8560 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio9_io22: IOMUXC_GPIO_AD_23_GPIO9_IO22 { + pinmux = <0x400e8168 10 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22_cm7: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22_CM7 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_kpp_col06: IOMUXC_GPIO_AD_23_KPP_COL06 { + pinmux = <0x400e8168 6 0x400e859c 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_lpspi2_pcs3: IOMUXC_GPIO_AD_23_LPSPI2_PCS3 { + pinmux = <0x400e8168 2 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_sai1_tx_sync: IOMUXC_GPIO_AD_23_SAI1_TX_SYNC { + pinmux = <0x400e8168 0 0x400e8680 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_video_mux_csi_data02: IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 { + pinmux = <0x400e8168 4 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_adc2_ch6a: IOMUXC_GPIO_AD_24_ADC2_CH6A { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_enet_rx_en: IOMUXC_GPIO_AD_24_ENET_RX_EN { + pinmux = <0x400e816c 3 0x400e84b8 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexio2_flexio24: IOMUXC_GPIO_AD_24_FLEXIO2_FLEXIO24 { + pinmux = <0x400e816c 8 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexpwm2_pwm0_a: IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A { + pinmux = <0x400e816c 4 0x400e8518 1 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio9_io23: IOMUXC_GPIO_AD_24_GPIO9_IO23 { + pinmux = <0x400e816c 10 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23_cm7: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23_CM7 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_kpp_row05: IOMUXC_GPIO_AD_24_KPP_ROW05 { + pinmux = <0x400e816c 6 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpi2c4_scl: IOMUXC_GPIO_AD_24_LPI2C4_SCL { + pinmux = <0x400e816c 9 0x400e85c4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpspi2_sck: IOMUXC_GPIO_AD_24_LPSPI2_SCK { + pinmux = <0x400e816c 1 0x400e85e4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpuart1_tx: IOMUXC_GPIO_AD_24_LPUART1_TX { + pinmux = <0x400e816c 0 0x400e8620 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_video_mux_csi_data00: IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 { + pinmux = <0x400e816c 2 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_adc2_ch6b: IOMUXC_GPIO_AD_25_ADC2_CH6B { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_enet_rx_er: IOMUXC_GPIO_AD_25_ENET_RX_ER { + pinmux = <0x400e8170 3 0x400e84bc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexio2_flexio25: IOMUXC_GPIO_AD_25_FLEXIO2_FLEXIO25 { + pinmux = <0x400e8170 8 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexpwm2_pwm0_b: IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B { + pinmux = <0x400e8170 4 0x400e8524 1 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio9_io24: IOMUXC_GPIO_AD_25_GPIO9_IO24 { + pinmux = <0x400e8170 10 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24_cm7: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24_CM7 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_kpp_col05: IOMUXC_GPIO_AD_25_KPP_COL05 { + pinmux = <0x400e8170 6 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpi2c4_sda: IOMUXC_GPIO_AD_25_LPI2C4_SDA { + pinmux = <0x400e8170 9 0x400e85c8 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpspi2_pcs0: IOMUXC_GPIO_AD_25_LPSPI2_PCS0 { + pinmux = <0x400e8170 1 0x400e85dc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpuart1_rx: IOMUXC_GPIO_AD_25_LPUART1_RX { + pinmux = <0x400e8170 0 0x400e861c 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_video_mux_csi_data01: IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 { + pinmux = <0x400e8170 2 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_acmp2_in3: IOMUXC_GPIO_AD_26_ACMP2_IN3 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_enet_rdata00: IOMUXC_GPIO_AD_26_ENET_RDATA00 { + pinmux = <0x400e8174 3 0x400e84b0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexio2_flexio26: IOMUXC_GPIO_AD_26_FLEXIO2_FLEXIO26 { + pinmux = <0x400e8174 8 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexpwm2_pwm1_a: IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A { + pinmux = <0x400e8174 4 0x400e851c 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio9_io25: IOMUXC_GPIO_AD_26_GPIO9_IO25 { + pinmux = <0x400e8174 10 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25_cm7: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25_CM7 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_kpp_row04: IOMUXC_GPIO_AD_26_KPP_ROW04 { + pinmux = <0x400e8174 6 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpspi2_sdo: IOMUXC_GPIO_AD_26_LPSPI2_SDO { + pinmux = <0x400e8174 1 0x400e85ec 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpuart1_cts_b: IOMUXC_GPIO_AD_26_LPUART1_CTS_B { + pinmux = <0x400e8174 0 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_semc_csx01: IOMUXC_GPIO_AD_26_SEMC_CSX01 { + pinmux = <0x400e8174 2 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_usdhc2_cd_b: IOMUXC_GPIO_AD_26_USDHC2_CD_B { + pinmux = <0x400e8174 11 0x400e86d0 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_acmp2_in4: IOMUXC_GPIO_AD_27_ACMP2_IN4 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_enet_rdata01: IOMUXC_GPIO_AD_27_ENET_RDATA01 { + pinmux = <0x400e8178 3 0x400e84b4 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexio2_flexio27: IOMUXC_GPIO_AD_27_FLEXIO2_FLEXIO27 { + pinmux = <0x400e8178 8 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexpwm2_pwm1_b: IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B { + pinmux = <0x400e8178 4 0x400e8528 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio9_io26: IOMUXC_GPIO_AD_27_GPIO9_IO26 { + pinmux = <0x400e8178 10 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26_cm7: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26_CM7 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_kpp_col04: IOMUXC_GPIO_AD_27_KPP_COL04 { + pinmux = <0x400e8178 6 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpspi2_sdi: IOMUXC_GPIO_AD_27_LPSPI2_SDI { + pinmux = <0x400e8178 1 0x400e85e8 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpuart1_rts_b: IOMUXC_GPIO_AD_27_LPUART1_RTS_B { + pinmux = <0x400e8178 0 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_semc_csx02: IOMUXC_GPIO_AD_27_SEMC_CSX02 { + pinmux = <0x400e8178 2 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_usdhc2_wp: IOMUXC_GPIO_AD_27_USDHC2_WP { + pinmux = <0x400e8178 11 0x400e86d4 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_acmp3_in1: IOMUXC_GPIO_AD_28_ACMP3_IN1 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_enet_tx_en: IOMUXC_GPIO_AD_28_ENET_TX_EN { + pinmux = <0x400e817c 3 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexio2_flexio28: IOMUXC_GPIO_AD_28_FLEXIO2_FLEXIO28 { + pinmux = <0x400e817c 8 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexpwm2_pwm2_a: IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A { + pinmux = <0x400e817c 4 0x400e8520 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio9_io27: IOMUXC_GPIO_AD_28_GPIO9_IO27 { + pinmux = <0x400e817c 10 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27_cm7: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27_CM7 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_kpp_row03: IOMUXC_GPIO_AD_28_KPP_ROW03 { + pinmux = <0x400e817c 6 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpspi1_sck: IOMUXC_GPIO_AD_28_LPSPI1_SCK { + pinmux = <0x400e817c 0 0x400e85d0 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpuart5_tx: IOMUXC_GPIO_AD_28_LPUART5_TX { + pinmux = <0x400e817c 1 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_semc_csx03: IOMUXC_GPIO_AD_28_SEMC_CSX03 { + pinmux = <0x400e817c 2 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_usdhc2_vselect: IOMUXC_GPIO_AD_28_USDHC2_VSELECT { + pinmux = <0x400e817c 11 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_video_mux_ext_dcic1: IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e817c 9 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_acmp3_in2: IOMUXC_GPIO_AD_29_ACMP3_IN2 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_ref_clk: IOMUXC_GPIO_AD_29_ENET_REF_CLK { + pinmux = <0x400e8180 2 0x400e84a8 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_tx_clk: IOMUXC_GPIO_AD_29_ENET_TX_CLK { + pinmux = <0x400e8180 3 0x400e84c0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexio2_flexio29: IOMUXC_GPIO_AD_29_FLEXIO2_FLEXIO29 { + pinmux = <0x400e8180 8 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexpwm2_pwm2_b: IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B { + pinmux = <0x400e8180 4 0x400e852c 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio9_io28: IOMUXC_GPIO_AD_29_GPIO9_IO28 { + pinmux = <0x400e8180 10 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28_cm7: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28_CM7 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_kpp_col03: IOMUXC_GPIO_AD_29_KPP_COL03 { + pinmux = <0x400e8180 6 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpspi1_pcs0: IOMUXC_GPIO_AD_29_LPSPI1_PCS0 { + pinmux = <0x400e8180 0 0x400e85cc 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpuart5_rx: IOMUXC_GPIO_AD_29_LPUART5_RX { + pinmux = <0x400e8180 1 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_usdhc2_reset_b: IOMUXC_GPIO_AD_29_USDHC2_RESET_B { + pinmux = <0x400e8180 11 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_video_mux_ext_dcic2: IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8180 9 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_acmp3_in3: IOMUXC_GPIO_AD_30_ACMP3_IN3 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_can2_tx: IOMUXC_GPIO_AD_30_CAN2_TX { + pinmux = <0x400e8184 2 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_enet_tdata00: IOMUXC_GPIO_AD_30_ENET_TDATA00 { + pinmux = <0x400e8184 3 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_flexio2_flexio30: IOMUXC_GPIO_AD_30_FLEXIO2_FLEXIO30 { + pinmux = <0x400e8184 8 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio9_io29: IOMUXC_GPIO_AD_30_GPIO9_IO29 { + pinmux = <0x400e8184 10 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29_cm7: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29_CM7 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_kpp_row02: IOMUXC_GPIO_AD_30_KPP_ROW02 { + pinmux = <0x400e8184 6 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpspi1_sdo: IOMUXC_GPIO_AD_30_LPSPI1_SDO { + pinmux = <0x400e8184 0 0x400e85d8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpuart3_tx: IOMUXC_GPIO_AD_30_LPUART3_TX { + pinmux = <0x400e8184 4 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_usb_otg2_oc: IOMUXC_GPIO_AD_30_USB_OTG2_OC { + pinmux = <0x400e8184 1 0x400e86b8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_AD_30_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e8184 9 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_acmp3_in4: IOMUXC_GPIO_AD_31_ACMP3_IN4 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_can2_rx: IOMUXC_GPIO_AD_31_CAN2_RX { + pinmux = <0x400e8188 2 0x400e849c 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_enet_tdata01: IOMUXC_GPIO_AD_31_ENET_TDATA01 { + pinmux = <0x400e8188 3 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_flexio2_flexio31: IOMUXC_GPIO_AD_31_FLEXIO2_FLEXIO31 { + pinmux = <0x400e8188 8 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio9_io30: IOMUXC_GPIO_AD_31_GPIO9_IO30 { + pinmux = <0x400e8188 10 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30_cm7: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30_CM7 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_kpp_col02: IOMUXC_GPIO_AD_31_KPP_COL02 { + pinmux = <0x400e8188 6 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpspi1_sdi: IOMUXC_GPIO_AD_31_LPSPI1_SDI { + pinmux = <0x400e8188 0 0x400e85d4 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpuart3_rx: IOMUXC_GPIO_AD_31_LPUART3_RX { + pinmux = <0x400e8188 4 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_usb_otg2_pwr: IOMUXC_GPIO_AD_31_USB_OTG2_PWR { + pinmux = <0x400e8188 1 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_AD_31_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8188 9 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_acmp4_in1: IOMUXC_GPIO_AD_32_ACMP4_IN1 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_1g_mdc: IOMUXC_GPIO_AD_32_ENET_1G_MDC { + pinmux = <0x400e818c 9 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_mdc: IOMUXC_GPIO_AD_32_ENET_MDC { + pinmux = <0x400e818c 3 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio9_io31: IOMUXC_GPIO_AD_32_GPIO9_IO31 { + pinmux = <0x400e818c 10 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31_cm7: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31_CM7 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_kpp_row01: IOMUXC_GPIO_AD_32_KPP_ROW01 { + pinmux = <0x400e818c 6 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpi2c1_scl: IOMUXC_GPIO_AD_32_LPI2C1_SCL { + pinmux = <0x400e818c 0 0x400e85ac 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpuart10_tx: IOMUXC_GPIO_AD_32_LPUART10_TX { + pinmux = <0x400e818c 8 0x400e8628 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_pgmc_pmic_ready: IOMUXC_GPIO_AD_32_PGMC_PMIC_READY { + pinmux = <0x400e818c 2 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usbphy2_otg_id: IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID { + pinmux = <0x400e818c 1 0x400e86c4 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usdhc1_cd_b: IOMUXC_GPIO_AD_32_USDHC1_CD_B { + pinmux = <0x400e818c 4 0x400e86c8 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_acmp4_in2: IOMUXC_GPIO_AD_33_ACMP4_IN2 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_1g_mdio: IOMUXC_GPIO_AD_33_ENET_1G_MDIO { + pinmux = <0x400e8190 9 0x400e84c8 3 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_mdio: IOMUXC_GPIO_AD_33_ENET_MDIO { + pinmux = <0x400e8190 3 0x400e84ac 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio10_io00: IOMUXC_GPIO_AD_33_GPIO10_IO00 { + pinmux = <0x400e8190 10 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio_mux4_io00: IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_kpp_col01: IOMUXC_GPIO_AD_33_KPP_COL01 { + pinmux = <0x400e8190 6 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpi2c1_sda: IOMUXC_GPIO_AD_33_LPI2C1_SDA { + pinmux = <0x400e8190 0 0x400e85b0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpuart10_rx: IOMUXC_GPIO_AD_33_LPUART10_RX { + pinmux = <0x400e8190 8 0x400e8624 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usbphy1_otg_id: IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID { + pinmux = <0x400e8190 1 0x400e86c0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usdhc1_wp: IOMUXC_GPIO_AD_33_USDHC1_WP { + pinmux = <0x400e8190 4 0x400e86cc 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_in17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_IN17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_inout17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_acmp4_in3: IOMUXC_GPIO_AD_34_ACMP4_IN3 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN { + pinmux = <0x400e8194 3 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1g_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN { + pinmux = <0x400e8194 0 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio10_io01: IOMUXC_GPIO_AD_34_GPIO10_IO01 { + pinmux = <0x400e8194 10 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio_mux4_io01: IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_kpp_row00: IOMUXC_GPIO_AD_34_KPP_ROW00 { + pinmux = <0x400e8194 6 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_lpuart10_cts_b: IOMUXC_GPIO_AD_34_LPUART10_CTS_B { + pinmux = <0x400e8194 8 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usb_otg1_pwr: IOMUXC_GPIO_AD_34_USB_OTG1_PWR { + pinmux = <0x400e8194 1 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usdhc1_vselect: IOMUXC_GPIO_AD_34_USDHC1_VSELECT { + pinmux = <0x400e8194 4 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_wdog1_wdog_any: IOMUXC_GPIO_AD_34_WDOG1_WDOG_ANY { + pinmux = <0x400e8194 9 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_in18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_IN18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_inout18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_acmp4_in4: IOMUXC_GPIO_AD_35_ACMP4_IN4 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT { + pinmux = <0x400e8198 3 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1g_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT { + pinmux = <0x400e8198 0 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_flexspi1_b_ss1_b: IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B { + pinmux = <0x400e8198 9 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio10_io02: IOMUXC_GPIO_AD_35_GPIO10_IO02 { + pinmux = <0x400e8198 10 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio_mux4_io02: IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_kpp_col00: IOMUXC_GPIO_AD_35_KPP_COL00 { + pinmux = <0x400e8198 6 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_lpuart10_rts_b: IOMUXC_GPIO_AD_35_LPUART10_RTS_B { + pinmux = <0x400e8198 8 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usb_otg1_oc: IOMUXC_GPIO_AD_35_USB_OTG1_OC { + pinmux = <0x400e8198 1 0x400e86bc 1 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usdhc1_reset_b: IOMUXC_GPIO_AD_35_USDHC1_RESET_B { + pinmux = <0x400e8198 4 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_in19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_IN19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_inout19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_INOUT19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_enet_1g_rx_en: IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN { + pinmux = <0x400e81e4 1 0x400e84e0 2 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio10_io21: IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 { + pinmux = <0x400e81e4 10 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio_mux4_io21: IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 { + pinmux = <0x400e81e4 5 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_qtimer1_timer0: IOMUXC_GPIO_DISP_B1_00_QTIMER1_TIMER0 { + pinmux = <0x400e81e4 3 0x400e863c 2 0x400e8428>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_video_mux_lcdif_clk: IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK { + pinmux = <0x400e81e4 0 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_in26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_IN26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_inout26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_clk: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK { + pinmux = <0x400e81e8 1 0x400e84cc 2 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_er: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER { + pinmux = <0x400e81e8 2 0x400e84e4 1 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio10_io22: IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 { + pinmux = <0x400e81e8 10 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio_mux4_io22: IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 { + pinmux = <0x400e81e8 5 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_qtimer1_timer1: IOMUXC_GPIO_DISP_B1_01_QTIMER1_TIMER1 { + pinmux = <0x400e81e8 3 0x400e8640 2 0x400e842c>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_video_mux_lcdif_enable: IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE { + pinmux = <0x400e81e8 0 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_in27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_IN27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_inout27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_enet_1g_rdata00: IOMUXC_GPIO_DISP_B1_02_ENET_1G_RDATA00 { + pinmux = <0x400e81ec 1 0x400e84d0 2 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio10_io23: IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 { + pinmux = <0x400e81ec 10 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio_mux4_io23: IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 { + pinmux = <0x400e81ec 5 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpi2c3_scl: IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL { + pinmux = <0x400e81ec 2 0x400e85bc 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpuart1_tx: IOMUXC_GPIO_DISP_B1_02_LPUART1_TX { + pinmux = <0x400e81ec 9 0x400e8620 1 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_qtimer1_timer2: IOMUXC_GPIO_DISP_B1_02_QTIMER1_TIMER2 { + pinmux = <0x400e81ec 3 0x400e8644 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_video_mux_lcdif_hsync: IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC { + pinmux = <0x400e81ec 0 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_in28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_IN28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_inout28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_enet_1g_rdata01: IOMUXC_GPIO_DISP_B1_03_ENET_1G_RDATA01 { + pinmux = <0x400e81f0 1 0x400e84d4 2 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio10_io24: IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 { + pinmux = <0x400e81f0 10 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio_mux4_io24: IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 { + pinmux = <0x400e81f0 5 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpi2c3_sda: IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA { + pinmux = <0x400e81f0 2 0x400e85c0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpuart1_rx: IOMUXC_GPIO_DISP_B1_03_LPUART1_RX { + pinmux = <0x400e81f0 9 0x400e861c 1 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_qtimer2_timer0: IOMUXC_GPIO_DISP_B1_03_QTIMER2_TIMER0 { + pinmux = <0x400e81f0 3 0x400e8648 2 0x400e8434>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_video_mux_lcdif_vsync: IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC { + pinmux = <0x400e81f0 0 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_in29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_IN29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_inout29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_enet_1g_rdata02: IOMUXC_GPIO_DISP_B1_04_ENET_1G_RDATA02 { + pinmux = <0x400e81f4 1 0x400e84d8 2 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio10_io25: IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 { + pinmux = <0x400e81f4 10 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio_mux4_io25: IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 { + pinmux = <0x400e81f4 5 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpspi3_sck: IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK { + pinmux = <0x400e81f4 9 0x400e8600 1 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpuart4_rx: IOMUXC_GPIO_DISP_B1_04_LPUART4_RX { + pinmux = <0x400e81f4 2 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_qtimer2_timer1: IOMUXC_GPIO_DISP_B1_04_QTIMER2_TIMER1 { + pinmux = <0x400e81f4 3 0x400e864c 2 0x400e8438>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_video_mux_lcdif_data00: IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 { + pinmux = <0x400e81f4 0 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_in30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_IN30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_inout30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_enet_1g_rdata03: IOMUXC_GPIO_DISP_B1_05_ENET_1G_RDATA03 { + pinmux = <0x400e81f8 1 0x400e84dc 2 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio10_io26: IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 { + pinmux = <0x400e81f8 10 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio_mux4_io26: IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 { + pinmux = <0x400e81f8 5 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpspi3_sdi: IOMUXC_GPIO_DISP_B1_05_LPSPI3_SDI { + pinmux = <0x400e81f8 9 0x400e8604 1 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpuart4_cts_b: IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B { + pinmux = <0x400e81f8 2 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_qtimer2_timer2: IOMUXC_GPIO_DISP_B1_05_QTIMER2_TIMER2 { + pinmux = <0x400e81f8 3 0x400e8650 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_video_mux_lcdif_data01: IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 { + pinmux = <0x400e81f8 0 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_in31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_IN31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_inout31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_enet_1g_tdata03: IOMUXC_GPIO_DISP_B1_06_ENET_1G_TDATA03 { + pinmux = <0x400e81fc 1 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio10_io27: IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 { + pinmux = <0x400e81fc 10 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio_mux4_io27: IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 { + pinmux = <0x400e81fc 5 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpspi3_sdo: IOMUXC_GPIO_DISP_B1_06_LPSPI3_SDO { + pinmux = <0x400e81fc 9 0x400e8608 1 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpuart4_tx: IOMUXC_GPIO_DISP_B1_06_LPUART4_TX { + pinmux = <0x400e81fc 2 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_qtimer3_timer0: IOMUXC_GPIO_DISP_B1_06_QTIMER3_TIMER0 { + pinmux = <0x400e81fc 3 0x400e8654 2 0x400e8440>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_src_bt_cfg00: IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 { + pinmux = <0x400e81fc 6 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_video_mux_lcdif_data02: IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 { + pinmux = <0x400e81fc 0 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_in32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_IN32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_inout32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_enet_1g_tdata02: IOMUXC_GPIO_DISP_B1_07_ENET_1G_TDATA02 { + pinmux = <0x400e8200 1 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio10_io28: IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 { + pinmux = <0x400e8200 10 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio_mux4_io28: IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 { + pinmux = <0x400e8200 5 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpspi3_pcs0: IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 { + pinmux = <0x400e8200 9 0x400e85f0 1 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpuart4_rts_b: IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B { + pinmux = <0x400e8200 2 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_qtimer3_timer1: IOMUXC_GPIO_DISP_B1_07_QTIMER3_TIMER1 { + pinmux = <0x400e8200 3 0x400e8658 2 0x400e8444>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_src_bt_cfg01: IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 { + pinmux = <0x400e8200 6 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_video_mux_lcdif_data03: IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 { + pinmux = <0x400e8200 0 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_in33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_IN33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_inout33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_enet_1g_tdata01: IOMUXC_GPIO_DISP_B1_08_ENET_1G_TDATA01 { + pinmux = <0x400e8204 1 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio10_io29: IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 { + pinmux = <0x400e8204 10 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio_mux4_io29: IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 { + pinmux = <0x400e8204 5 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_lpspi3_pcs1: IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 { + pinmux = <0x400e8204 9 0x400e85f4 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_qtimer3_timer2: IOMUXC_GPIO_DISP_B1_08_QTIMER3_TIMER2 { + pinmux = <0x400e8204 3 0x400e865c 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_src_bt_cfg02: IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 { + pinmux = <0x400e8204 6 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_usdhc1_cd_b: IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B { + pinmux = <0x400e8204 2 0x400e86c8 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_video_mux_lcdif_data04: IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 { + pinmux = <0x400e8204 0 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_in34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_IN34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_inout34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_enet_1g_tdata00: IOMUXC_GPIO_DISP_B1_09_ENET_1G_TDATA00 { + pinmux = <0x400e8208 1 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio10_io30: IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 { + pinmux = <0x400e8208 10 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio_mux4_io30: IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 { + pinmux = <0x400e8208 5 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_lpspi3_pcs2: IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 { + pinmux = <0x400e8208 9 0x400e85f8 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_qtimer4_timer0: IOMUXC_GPIO_DISP_B1_09_QTIMER4_TIMER0 { + pinmux = <0x400e8208 3 0x400e8660 2 0x400e844c>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_src_bt_cfg03: IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 { + pinmux = <0x400e8208 6 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_usdhc1_wp: IOMUXC_GPIO_DISP_B1_09_USDHC1_WP { + pinmux = <0x400e8208 2 0x400e86cc 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_video_mux_lcdif_data05: IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 { + pinmux = <0x400e8208 0 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_in35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_IN35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_inout35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_enet_1g_tx_en: IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN { + pinmux = <0x400e820c 1 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio10_io31: IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 { + pinmux = <0x400e820c 10 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio_mux4_io31: IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 { + pinmux = <0x400e820c 5 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_lpspi3_pcs3: IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 { + pinmux = <0x400e820c 9 0x400e85fc 1 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_qtimer4_timer1: IOMUXC_GPIO_DISP_B1_10_QTIMER4_TIMER1 { + pinmux = <0x400e820c 3 0x400e8664 2 0x400e8450>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_src_bt_cfg04: IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 { + pinmux = <0x400e820c 6 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_usdhc1_reset_b: IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B { + pinmux = <0x400e820c 2 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_video_mux_lcdif_data06: IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 { + pinmux = <0x400e820c 0 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_in36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_IN36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_inout36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_INOUT36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e8210 2 0x400e84c4 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_tx_clk_io: IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e8210 1 0x400e84e8 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio11_io00: IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 { + pinmux = <0x400e8210 10 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio_mux5_io00: IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 { + pinmux = <0x400e8210 5 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_qtimer4_timer2: IOMUXC_GPIO_DISP_B1_11_QTIMER4_TIMER2 { + pinmux = <0x400e8210 3 0x400e8668 1 0x400e8454>; + pin-pdrv; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_src_bt_cfg05: IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 { + pinmux = <0x400e8210 6 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_video_mux_lcdif_data07: IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 { + pinmux = <0x400e8210 0 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_in37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_IN37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_inout37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_INOUT37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_enet_1g_tx_er: IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER { + pinmux = <0x400e8214 3 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio11_io01: IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 { + pinmux = <0x400e8214 10 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio_mux5_io01: IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 { + pinmux = <0x400e8214 5 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_mqs_right: IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT { + pinmux = <0x400e8214 2 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_rx_data01: IOMUXC_GPIO_DISP_B2_00_SAI1_RX_DATA01 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_tx_data03: IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_src_bt_cfg06: IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 { + pinmux = <0x400e8214 6 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_video_mux_lcdif_data08: IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 { + pinmux = <0x400e8214 0 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_00_WDOG1_WDOG_B { + pinmux = <0x400e8214 1 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ccm_enet_ref_clk_25m: IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8218 9 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ewm_ewm_out_b: IOMUXC_GPIO_DISP_B2_01_EWM_EWM_OUT_B { + pinmux = <0x400e8218 8 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio11_io02: IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 { + pinmux = <0x400e8218 10 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio_mux5_io02: IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 { + pinmux = <0x400e8218 5 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_mqs_left: IOMUXC_GPIO_DISP_B2_01_MQS_LEFT { + pinmux = <0x400e8218 2 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_rx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_RX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_tx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_src_bt_cfg07: IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 { + pinmux = <0x400e8218 6 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_usdhc1_vselect: IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT { + pinmux = <0x400e8218 1 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_video_mux_lcdif_data09: IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 { + pinmux = <0x400e8218 0 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_01_WDOG2_WDOG_B { + pinmux = <0x400e8218 3 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_arm_trace00: IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 { + pinmux = <0x400e821c 3 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_enet_tdata00: IOMUXC_GPIO_DISP_B2_02_ENET_TDATA00 { + pinmux = <0x400e821c 1 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio11_io03: IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 { + pinmux = <0x400e821c 10 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio_mux5_io03: IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 { + pinmux = <0x400e821c 5 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_pit1_trigger03: IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER03 { + pinmux = <0x400e821c 2 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_rx_data03: IOMUXC_GPIO_DISP_B2_02_SAI1_RX_DATA03 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_tx_data01: IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_src_bt_cfg08: IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 { + pinmux = <0x400e821c 6 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_video_mux_lcdif_data10: IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 { + pinmux = <0x400e821c 0 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_arm_trace01: IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 { + pinmux = <0x400e8220 3 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_enet_tdata01: IOMUXC_GPIO_DISP_B2_03_ENET_TDATA01 { + pinmux = <0x400e8220 1 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio11_io04: IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 { + pinmux = <0x400e8220 10 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio_mux5_io04: IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 { + pinmux = <0x400e8220 5 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_pit1_trigger02: IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER02 { + pinmux = <0x400e8220 2 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_sai1_mclk: IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK { + pinmux = <0x400e8220 4 0x400e866c 1 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_src_bt_cfg09: IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 { + pinmux = <0x400e8220 6 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_video_mux_lcdif_data11: IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 { + pinmux = <0x400e8220 0 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_arm_trace02: IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 { + pinmux = <0x400e8224 3 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_enet_tx_en: IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN { + pinmux = <0x400e8224 1 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio11_io05: IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 { + pinmux = <0x400e8224 10 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio_mux5_io05: IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 { + pinmux = <0x400e8224 5 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_pit1_trigger01: IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER01 { + pinmux = <0x400e8224 2 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_sai1_rx_sync: IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC { + pinmux = <0x400e8224 4 0x400e8678 1 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_src_bt_cfg10: IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 { + pinmux = <0x400e8224 6 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_video_mux_lcdif_data12: IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 { + pinmux = <0x400e8224 0 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_arm_trace03: IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 { + pinmux = <0x400e8228 3 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_ref_clk: IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK { + pinmux = <0x400e8228 2 0x400e84a8 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_tx_clk: IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK { + pinmux = <0x400e8228 1 0x400e84c0 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio11_io06: IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 { + pinmux = <0x400e8228 10 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio_mux5_io06: IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 { + pinmux = <0x400e8228 5 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_sai1_rx_bclk: IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK { + pinmux = <0x400e8228 4 0x400e8670 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_src_bt_cfg11: IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 { + pinmux = <0x400e8228 6 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_video_mux_lcdif_data13: IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 { + pinmux = <0x400e8228 0 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_arm_trace_clk: IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK { + pinmux = <0x400e822c 3 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_enet_rdata00: IOMUXC_GPIO_DISP_B2_06_ENET_RDATA00 { + pinmux = <0x400e822c 1 0x400e84b0 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio11_io07: IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 { + pinmux = <0x400e822c 10 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio_mux5_io07: IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 { + pinmux = <0x400e822c 5 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_lpuart7_tx: IOMUXC_GPIO_DISP_B2_06_LPUART7_TX { + pinmux = <0x400e822c 2 0x400e8630 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_sai1_rx_data00: IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 { + pinmux = <0x400e822c 4 0x400e8674 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_video_mux_lcdif_data14: IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 { + pinmux = <0x400e822c 0 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_arm_trace_swo: IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO { + pinmux = <0x400e8230 3 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_enet_rdata01: IOMUXC_GPIO_DISP_B2_07_ENET_RDATA01 { + pinmux = <0x400e8230 1 0x400e84b4 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio11_io08: IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 { + pinmux = <0x400e8230 10 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio_mux5_io08: IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 { + pinmux = <0x400e8230 5 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_lpuart7_rx: IOMUXC_GPIO_DISP_B2_07_LPUART7_RX { + pinmux = <0x400e8230 2 0x400e862c 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_sai1_tx_data00: IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 { + pinmux = <0x400e8230 4 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_video_mux_lcdif_data15: IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 { + pinmux = <0x400e8230 0 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_cm7_imxrt_txev: IOMUXC_GPIO_DISP_B2_08_CM7_IMXRT_TXEV { + pinmux = <0x400e8234 3 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_enet_rx_en: IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN { + pinmux = <0x400e8234 1 0x400e84b8 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio11_io09: IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 { + pinmux = <0x400e8234 10 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio_mux5_io09: IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 { + pinmux = <0x400e8234 5 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart1_tx: IOMUXC_GPIO_DISP_B2_08_LPUART1_TX { + pinmux = <0x400e8234 9 0x400e8620 2 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart8_tx: IOMUXC_GPIO_DISP_B2_08_LPUART8_TX { + pinmux = <0x400e8234 2 0x400e8638 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_sai1_tx_bclk: IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK { + pinmux = <0x400e8234 4 0x400e867c 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_video_mux_lcdif_data16: IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 { + pinmux = <0x400e8234 0 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_cm7_imxrt_rxev: IOMUXC_GPIO_DISP_B2_09_CM7_IMXRT_RXEV { + pinmux = <0x400e8238 3 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_enet_rx_er: IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER { + pinmux = <0x400e8238 1 0x400e84bc 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio11_io10: IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 { + pinmux = <0x400e8238 10 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio_mux5_io10: IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 { + pinmux = <0x400e8238 5 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart1_rx: IOMUXC_GPIO_DISP_B2_09_LPUART1_RX { + pinmux = <0x400e8238 9 0x400e861c 2 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart8_rx: IOMUXC_GPIO_DISP_B2_09_LPUART8_RX { + pinmux = <0x400e8238 2 0x400e8634 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_sai1_tx_sync: IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC { + pinmux = <0x400e8238 4 0x400e8680 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_video_mux_lcdif_data17: IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 { + pinmux = <0x400e8238 0 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio11_io11: IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 { + pinmux = <0x400e823c 10 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio_mux5_io11: IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 { + pinmux = <0x400e823c 5 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpi2c3_scl: IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL { + pinmux = <0x400e823c 6 0x400e85bc 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpuart2_tx: IOMUXC_GPIO_DISP_B2_10_LPUART2_TX { + pinmux = <0x400e823c 2 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_sim2_trxd: IOMUXC_GPIO_DISP_B2_10_SIM2_TRXD { + pinmux = <0x400e823c 1 0x400e86a8 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_spdif_in: IOMUXC_GPIO_DISP_B2_10_SPDIF_IN { + pinmux = <0x400e823c 9 0x400e86b4 2 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_video_mux_lcdif_data18: IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 { + pinmux = <0x400e823c 0 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_10_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e823c 3 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_in38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_IN38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_inout38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_INOUT38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio11_io12: IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 { + pinmux = <0x400e8240 10 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio_mux5_io12: IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 { + pinmux = <0x400e8240 5 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpi2c3_sda: IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA { + pinmux = <0x400e8240 6 0x400e85c0 1 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpuart2_rx: IOMUXC_GPIO_DISP_B2_11_LPUART2_RX { + pinmux = <0x400e8240 2 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_sim2_clk: IOMUXC_GPIO_DISP_B2_11_SIM2_CLK { + pinmux = <0x400e8240 1 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_spdif_out: IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT { + pinmux = <0x400e8240 9 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_video_mux_lcdif_data19: IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 { + pinmux = <0x400e8240 0 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_11_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8240 3 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_in39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_IN39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_inout39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_INOUT39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_can1_tx: IOMUXC_GPIO_DISP_B2_12_CAN1_TX { + pinmux = <0x400e8244 2 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio11_io13: IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 { + pinmux = <0x400e8244 10 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio_mux5_io13: IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 { + pinmux = <0x400e8244 5 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpi2c4_scl: IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL { + pinmux = <0x400e8244 6 0x400e85c4 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpspi4_sck: IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK { + pinmux = <0x400e8244 9 0x400e8610 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpuart2_cts_b: IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B { + pinmux = <0x400e8244 3 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_sim2_rst_b: IOMUXC_GPIO_DISP_B2_12_SIM2_RST_B { + pinmux = <0x400e8244 1 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_video_mux_lcdif_data20: IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 { + pinmux = <0x400e8244 0 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_in40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_IN40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_inout40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_INOUT40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_can1_rx: IOMUXC_GPIO_DISP_B2_13_CAN1_RX { + pinmux = <0x400e8248 2 0x400e8498 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_enet_ref_clk: IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK { + pinmux = <0x400e8248 4 0x400e84a8 2 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio11_io14: IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 { + pinmux = <0x400e8248 10 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio_mux5_io14: IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 { + pinmux = <0x400e8248 5 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpi2c4_sda: IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA { + pinmux = <0x400e8248 6 0x400e85c8 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpspi4_sdi: IOMUXC_GPIO_DISP_B2_13_LPSPI4_SDI { + pinmux = <0x400e8248 9 0x400e8614 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpuart2_rts_b: IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B { + pinmux = <0x400e8248 3 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_sim2_sven: IOMUXC_GPIO_DISP_B2_13_SIM2_SVEN { + pinmux = <0x400e8248 1 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_video_mux_lcdif_data21: IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 { + pinmux = <0x400e8248 0 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_can1_tx: IOMUXC_GPIO_DISP_B2_14_CAN1_TX { + pinmux = <0x400e824c 6 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK1 { + pinmux = <0x400e824c 4 0x400e84c4 3 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio11_io15: IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 { + pinmux = <0x400e824c 10 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio_mux5_io15: IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 { + pinmux = <0x400e824c 5 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_lpspi4_sdo: IOMUXC_GPIO_DISP_B2_14_LPSPI4_SDO { + pinmux = <0x400e824c 9 0x400e8618 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_sim2_pd: IOMUXC_GPIO_DISP_B2_14_SIM2_PD { + pinmux = <0x400e824c 1 0x400e86ac 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_ext_dcic1: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e824c 3 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_lcdif_data22: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 { + pinmux = <0x400e824c 0 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_14_WDOG2_WDOG_B { + pinmux = <0x400e824c 2 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_can1_rx: IOMUXC_GPIO_DISP_B2_15_CAN1_RX { + pinmux = <0x400e8250 6 0x400e8498 2 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio11_io16: IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 { + pinmux = <0x400e8250 10 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio_mux5_io16: IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 { + pinmux = <0x400e8250 5 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_lpspi4_pcs0: IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 { + pinmux = <0x400e8250 9 0x400e860c 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_pit1_trigger00: IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER00 { + pinmux = <0x400e8250 4 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_sim2_power_fail: IOMUXC_GPIO_DISP_B2_15_SIM2_POWER_FAIL { + pinmux = <0x400e8250 1 0x400e86b0 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_ext_dcic2: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8250 3 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_lcdif_data23: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 { + pinmux = <0x400e8250 0 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_15_WDOG1_WDOG_B { + pinmux = <0x400e8250 2 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexio1_flexio00: IOMUXC_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00 { + pinmux = <0x400e8010 8 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexpwm4_pwm0_a: IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A { + pinmux = <0x400e8010 1 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio7_io00: IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 { + pinmux = <0x400e8010 10 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio_mux1_io00: IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 { + pinmux = <0x400e8010 5 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_semc_data00: IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 { + pinmux = <0x400e8010 0 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexio1_flexio01: IOMUXC_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01 { + pinmux = <0x400e8014 8 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexpwm4_pwm0_b: IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B { + pinmux = <0x400e8014 1 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio7_io01: IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 { + pinmux = <0x400e8014 10 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio_mux1_io01: IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 { + pinmux = <0x400e8014 5 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_semc_data01: IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 { + pinmux = <0x400e8014 0 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexio1_flexio02: IOMUXC_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02 { + pinmux = <0x400e8018 8 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexpwm4_pwm1_a: IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A { + pinmux = <0x400e8018 1 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio7_io02: IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 { + pinmux = <0x400e8018 10 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio_mux1_io02: IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 { + pinmux = <0x400e8018 5 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_semc_data02: IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 { + pinmux = <0x400e8018 0 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexio1_flexio03: IOMUXC_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03 { + pinmux = <0x400e801c 8 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexpwm4_pwm1_b: IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B { + pinmux = <0x400e801c 1 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio7_io03: IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 { + pinmux = <0x400e801c 10 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio_mux1_io03: IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 { + pinmux = <0x400e801c 5 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_semc_data03: IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 { + pinmux = <0x400e801c 0 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexio1_flexio04: IOMUXC_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04 { + pinmux = <0x400e8020 8 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexpwm4_pwm2_a: IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A { + pinmux = <0x400e8020 1 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio7_io04: IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 { + pinmux = <0x400e8020 10 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio_mux1_io04: IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 { + pinmux = <0x400e8020 5 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_semc_data04: IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 { + pinmux = <0x400e8020 0 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexio1_flexio05: IOMUXC_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05 { + pinmux = <0x400e8024 8 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexpwm4_pwm2_b: IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B { + pinmux = <0x400e8024 1 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio7_io05: IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 { + pinmux = <0x400e8024 10 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio_mux1_io05: IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 { + pinmux = <0x400e8024 5 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_semc_data05: IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 { + pinmux = <0x400e8024 0 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexio1_flexio06: IOMUXC_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06 { + pinmux = <0x400e8028 8 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexpwm2_pwm0_a: IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A { + pinmux = <0x400e8028 1 0x400e8518 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio7_io06: IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 { + pinmux = <0x400e8028 10 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio_mux1_io06: IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 { + pinmux = <0x400e8028 5 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_semc_data06: IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 { + pinmux = <0x400e8028 0 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexio1_flexio07: IOMUXC_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07 { + pinmux = <0x400e802c 8 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexpwm2_pwm0_b: IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B { + pinmux = <0x400e802c 1 0x400e8524 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio7_io07: IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 { + pinmux = <0x400e802c 10 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio_mux1_io07: IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 { + pinmux = <0x400e802c 5 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_semc_data07: IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 { + pinmux = <0x400e802c 0 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexio1_flexio08: IOMUXC_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08 { + pinmux = <0x400e8030 8 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexpwm2_pwm1_a: IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A { + pinmux = <0x400e8030 1 0x400e851c 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio7_io08: IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 { + pinmux = <0x400e8030 10 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio_mux1_io08: IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 { + pinmux = <0x400e8030 5 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_semc_dm00: IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 { + pinmux = <0x400e8030 0 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexio1_flexio09: IOMUXC_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09 { + pinmux = <0x400e8034 8 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexpwm2_pwm1_b: IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B { + pinmux = <0x400e8034 1 0x400e8528 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio7_io09: IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 { + pinmux = <0x400e8034 10 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio_mux1_io09: IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 { + pinmux = <0x400e8034 5 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpt5_capture1: IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 { + pinmux = <0x400e8034 2 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_semc_addr00: IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 { + pinmux = <0x400e8034 0 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexio1_flexio10: IOMUXC_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10 { + pinmux = <0x400e8038 8 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexpwm2_pwm2_a: IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A { + pinmux = <0x400e8038 1 0x400e8520 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio7_io10: IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 { + pinmux = <0x400e8038 10 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio_mux1_io10: IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 { + pinmux = <0x400e8038 5 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpt5_capture2: IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 { + pinmux = <0x400e8038 2 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_semc_addr01: IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 { + pinmux = <0x400e8038 0 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexio1_flexio11: IOMUXC_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11 { + pinmux = <0x400e803c 8 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexpwm2_pwm2_b: IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B { + pinmux = <0x400e803c 1 0x400e852c 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio7_io11: IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 { + pinmux = <0x400e803c 10 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio_mux1_io11: IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 { + pinmux = <0x400e803c 5 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpt5_compare1: IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 { + pinmux = <0x400e803c 2 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_semc_addr02: IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 { + pinmux = <0x400e803c 0 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_flexio1_flexio12: IOMUXC_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12 { + pinmux = <0x400e8040 8 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio7_io12: IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 { + pinmux = <0x400e8040 10 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio_mux1_io12: IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 { + pinmux = <0x400e8040 5 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpt5_compare2: IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 { + pinmux = <0x400e8040 2 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_semc_addr03: IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 { + pinmux = <0x400e8040 0 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_in04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_IN04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_INOUT04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_flexio1_flexio13: IOMUXC_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13 { + pinmux = <0x400e8044 8 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio7_io13: IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 { + pinmux = <0x400e8044 10 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio_mux1_io13: IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 { + pinmux = <0x400e8044 5 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpt5_compare3: IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 { + pinmux = <0x400e8044 2 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_semc_addr04: IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 { + pinmux = <0x400e8044 0 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_in05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_IN05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_INOUT05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_flexio1_flexio14: IOMUXC_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14 { + pinmux = <0x400e8048 8 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio7_io14: IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 { + pinmux = <0x400e8048 10 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio_mux1_io14: IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 { + pinmux = <0x400e8048 5 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpt5_clk: IOMUXC_GPIO_EMC_B1_14_GPT5_CLK { + pinmux = <0x400e8048 2 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_semc_addr05: IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 { + pinmux = <0x400e8048 0 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_in06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_IN06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_INOUT06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_flexio1_flexio15: IOMUXC_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15 { + pinmux = <0x400e804c 8 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio7_io15: IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 { + pinmux = <0x400e804c 10 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio_mux1_io15: IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 { + pinmux = <0x400e804c 5 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_semc_addr06: IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 { + pinmux = <0x400e804c 0 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_in07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_IN07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_INOUT07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_flexio1_flexio16: IOMUXC_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16 { + pinmux = <0x400e8050 8 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio7_io16: IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 { + pinmux = <0x400e8050 10 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio_mux1_io16: IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 { + pinmux = <0x400e8050 5 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_semc_addr07: IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 { + pinmux = <0x400e8050 0 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_in08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_IN08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_INOUT08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexio1_flexio17: IOMUXC_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17 { + pinmux = <0x400e8054 8 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexpwm4_pwm3_a: IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A { + pinmux = <0x400e8054 1 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio7_io17: IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 { + pinmux = <0x400e8054 10 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio_mux1_io17: IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 { + pinmux = <0x400e8054 5 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_qtimer1_timer0: IOMUXC_GPIO_EMC_B1_17_QTIMER1_TIMER0 { + pinmux = <0x400e8054 2 0x400e863c 0 0x400e8298>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_semc_addr08: IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 { + pinmux = <0x400e8054 0 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexio1_flexio18: IOMUXC_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18 { + pinmux = <0x400e8058 8 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexpwm4_pwm3_b: IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B { + pinmux = <0x400e8058 1 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio7_io18: IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 { + pinmux = <0x400e8058 10 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio_mux1_io18: IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 { + pinmux = <0x400e8058 5 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_qtimer2_timer0: IOMUXC_GPIO_EMC_B1_18_QTIMER2_TIMER0 { + pinmux = <0x400e8058 2 0x400e8648 0 0x400e829c>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_semc_addr09: IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 { + pinmux = <0x400e8058 0 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexio1_flexio19: IOMUXC_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19 { + pinmux = <0x400e805c 8 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexpwm2_pwm3_a: IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A { + pinmux = <0x400e805c 1 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio7_io19: IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 { + pinmux = <0x400e805c 10 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio_mux1_io19: IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 { + pinmux = <0x400e805c 5 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_qtimer3_timer0: IOMUXC_GPIO_EMC_B1_19_QTIMER3_TIMER0 { + pinmux = <0x400e805c 2 0x400e8654 0 0x400e82a0>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_semc_addr11: IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 { + pinmux = <0x400e805c 0 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexio1_flexio20: IOMUXC_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20 { + pinmux = <0x400e8060 8 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexpwm2_pwm3_b: IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B { + pinmux = <0x400e8060 1 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio7_io20: IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 { + pinmux = <0x400e8060 10 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio_mux1_io20: IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 { + pinmux = <0x400e8060 5 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_qtimer4_timer0: IOMUXC_GPIO_EMC_B1_20_QTIMER4_TIMER0 { + pinmux = <0x400e8060 2 0x400e8660 0 0x400e82a4>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_semc_addr12: IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 { + pinmux = <0x400e8060 0 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexio1_flexio21: IOMUXC_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21 { + pinmux = <0x400e8064 8 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A { + pinmux = <0x400e8064 1 0x400e853c 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio7_io21: IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 { + pinmux = <0x400e8064 10 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio_mux1_io21: IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 { + pinmux = <0x400e8064 5 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_semc_ba0: IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 { + pinmux = <0x400e8064 0 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexio1_flexio22: IOMUXC_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22 { + pinmux = <0x400e8068 8 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B { + pinmux = <0x400e8068 1 0x400e854c 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio7_io22: IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 { + pinmux = <0x400e8068 10 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio_mux1_io22: IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 { + pinmux = <0x400e8068 5 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_semc_ba1: IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 { + pinmux = <0x400e8068 0 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexio1_flexio23: IOMUXC_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23 { + pinmux = <0x400e806c 8 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexpwm1_pwm0_a: IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A { + pinmux = <0x400e806c 1 0x400e8500 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio7_io23: IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 { + pinmux = <0x400e806c 10 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio_mux1_io23: IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 { + pinmux = <0x400e806c 5 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_semc_addr10: IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 { + pinmux = <0x400e806c 0 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexio1_flexio24: IOMUXC_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24 { + pinmux = <0x400e8070 8 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexpwm1_pwm0_b: IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B { + pinmux = <0x400e8070 1 0x400e850c 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio7_io24: IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 { + pinmux = <0x400e8070 10 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio_mux1_io24: IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 { + pinmux = <0x400e8070 5 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_semc_cas: IOMUXC_GPIO_EMC_B1_24_SEMC_CAS { + pinmux = <0x400e8070 0 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexio1_flexio25: IOMUXC_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25 { + pinmux = <0x400e8074 8 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexpwm1_pwm1_a: IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A { + pinmux = <0x400e8074 1 0x400e8504 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio7_io25: IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 { + pinmux = <0x400e8074 10 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio_mux1_io25: IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 { + pinmux = <0x400e8074 5 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_semc_ras: IOMUXC_GPIO_EMC_B1_25_SEMC_RAS { + pinmux = <0x400e8074 0 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexio1_flexio26: IOMUXC_GPIO_EMC_B1_26_FLEXIO1_FLEXIO26 { + pinmux = <0x400e8078 8 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexpwm1_pwm1_b: IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B { + pinmux = <0x400e8078 1 0x400e8510 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio7_io26: IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 { + pinmux = <0x400e8078 10 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio_mux1_io26: IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 { + pinmux = <0x400e8078 5 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_semc_clk: IOMUXC_GPIO_EMC_B1_26_SEMC_CLK { + pinmux = <0x400e8078 0 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexio1_flexio27: IOMUXC_GPIO_EMC_B1_27_FLEXIO1_FLEXIO27 { + pinmux = <0x400e807c 8 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexpwm1_pwm2_a: IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A { + pinmux = <0x400e807c 1 0x400e8508 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio7_io27: IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 { + pinmux = <0x400e807c 10 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio_mux1_io27: IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 { + pinmux = <0x400e807c 5 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_semc_cke: IOMUXC_GPIO_EMC_B1_27_SEMC_CKE { + pinmux = <0x400e807c 0 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexio1_flexio28: IOMUXC_GPIO_EMC_B1_28_FLEXIO1_FLEXIO28 { + pinmux = <0x400e8080 8 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexpwm1_pwm2_b: IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B { + pinmux = <0x400e8080 1 0x400e8514 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio7_io28: IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 { + pinmux = <0x400e8080 10 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio_mux1_io28: IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 { + pinmux = <0x400e8080 5 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_semc_we: IOMUXC_GPIO_EMC_B1_28_SEMC_WE { + pinmux = <0x400e8080 0 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexio1_flexio29: IOMUXC_GPIO_EMC_B1_29_FLEXIO1_FLEXIO29 { + pinmux = <0x400e8084 8 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A { + pinmux = <0x400e8084 1 0x400e8530 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio7_io29: IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 { + pinmux = <0x400e8084 10 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio_mux1_io29: IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 { + pinmux = <0x400e8084 5 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_semc_cs0: IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 { + pinmux = <0x400e8084 0 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexio1_flexio30: IOMUXC_GPIO_EMC_B1_30_FLEXIO1_FLEXIO30 { + pinmux = <0x400e8088 8 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B { + pinmux = <0x400e8088 1 0x400e8540 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio7_io30: IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 { + pinmux = <0x400e8088 10 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio_mux1_io30: IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 { + pinmux = <0x400e8088 5 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_semc_data08: IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 { + pinmux = <0x400e8088 0 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexio1_flexio31: IOMUXC_GPIO_EMC_B1_31_FLEXIO1_FLEXIO31 { + pinmux = <0x400e808c 8 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A { + pinmux = <0x400e808c 1 0x400e8534 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio7_io31: IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 { + pinmux = <0x400e808c 10 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio_mux1_io31: IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 { + pinmux = <0x400e808c 5 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_semc_data09: IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 { + pinmux = <0x400e808c 0 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B { + pinmux = <0x400e8090 1 0x400e8544 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio8_io00: IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 { + pinmux = <0x400e8090 10 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00_cm7: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00_CM7 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_semc_data10: IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 { + pinmux = <0x400e8090 0 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A { + pinmux = <0x400e8094 1 0x400e8538 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio8_io01: IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 { + pinmux = <0x400e8094 10 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01_cm7: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01_CM7 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_semc_data11: IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 { + pinmux = <0x400e8094 0 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B { + pinmux = <0x400e8098 1 0x400e8548 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio8_io02: IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 { + pinmux = <0x400e8098 10 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02_cm7: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02_CM7 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_semc_data12: IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 { + pinmux = <0x400e8098 0 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio8_io03: IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 { + pinmux = <0x400e809c 10 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03_cm7: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03_CM7 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_semc_data13: IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 { + pinmux = <0x400e809c 0 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_in09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_IN09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_INOUT09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio8_io04: IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 { + pinmux = <0x400e80a0 10 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04_cm7: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04_CM7 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_semc_data14: IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 { + pinmux = <0x400e80a0 0 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_in10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_IN10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_INOUT10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio8_io05: IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 { + pinmux = <0x400e80a4 10 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05_cm7: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05_CM7 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_semc_data15: IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 { + pinmux = <0x400e80a4 0 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_in11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_IN11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_INOUT11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_flexpwm1_pwm3_a: IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A { + pinmux = <0x400e80a8 1 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio8_io06: IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 { + pinmux = <0x400e80a8 10 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06_cm7: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06_CM7 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_qtimer1_timer1: IOMUXC_GPIO_EMC_B1_38_QTIMER1_TIMER1 { + pinmux = <0x400e80a8 2 0x400e8640 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_semc_dm01: IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 { + pinmux = <0x400e80a8 0 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_flexpwm1_pwm3_b: IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B { + pinmux = <0x400e80ac 1 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio8_io07: IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 { + pinmux = <0x400e80ac 10 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07_cm7: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07_CM7 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_qtimer2_timer1: IOMUXC_GPIO_EMC_B1_39_QTIMER2_TIMER1 { + pinmux = <0x400e80ac 2 0x400e864c 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_semc_dqs: IOMUXC_GPIO_EMC_B1_39_SEMC_DQS { + pinmux = <0x400e80ac 0 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_ccm_clko1: IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 { + pinmux = <0x400e80b0 9 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_enet_1g_mdc: IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC { + pinmux = <0x400e80b0 7 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio8_io08: IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 { + pinmux = <0x400e80b0 10 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08_cm7: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08_CM7 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_lpuart6_tx: IOMUXC_GPIO_EMC_B1_40_LPUART6_TX { + pinmux = <0x400e80b0 3 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_mqs_right: IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT { + pinmux = <0x400e80b0 2 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_semc_rdy: IOMUXC_GPIO_EMC_B1_40_SEMC_RDY { + pinmux = <0x400e80b0 0 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_in12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_IN12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_INOUT12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_ccm_clko2: IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 { + pinmux = <0x400e80b4 9 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_enet_1g_mdio: IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO { + pinmux = <0x400e80b4 7 0x400e84c8 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_flexspi2_b_data07: IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 { + pinmux = <0x400e80b4 4 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio8_io09: IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 { + pinmux = <0x400e80b4 10 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09_cm7: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09_CM7 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_lpuart6_rx: IOMUXC_GPIO_EMC_B1_41_LPUART6_RX { + pinmux = <0x400e80b4 3 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_mqs_left: IOMUXC_GPIO_EMC_B1_41_MQS_LEFT { + pinmux = <0x400e80b4 2 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_semc_csx00: IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 { + pinmux = <0x400e80b4 0 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_in13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_IN13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_INOUT13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_ccm_enet_ref_clk_25m: IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e80b8 1 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A { + pinmux = <0x400e80b8 11 0x400e8530 1 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexspi2_b_data06: IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 { + pinmux = <0x400e80b8 4 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio8_io10: IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 { + pinmux = <0x400e80b8 10 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10_cm7: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10_CM7 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpi2c2_scl: IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL { + pinmux = <0x400e80b8 9 0x400e85b4 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpspi1_sck: IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK { + pinmux = <0x400e80b8 8 0x400e85d0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpuart6_cts_b: IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B { + pinmux = <0x400e80b8 3 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_00_QTIMER3_TIMER1 { + pinmux = <0x400e80b8 2 0x400e8658 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_semc_data16: IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 { + pinmux = <0x400e80b8 0 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_in20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_inout20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B { + pinmux = <0x400e80bc 11 0x400e8540 1 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexspi2_b_data05: IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 { + pinmux = <0x400e80bc 4 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio8_io11: IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 { + pinmux = <0x400e80bc 10 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11_cm7: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11_CM7 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpi2c2_sda: IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA { + pinmux = <0x400e80bc 9 0x400e85b8 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpspi1_pcs0: IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 { + pinmux = <0x400e80bc 8 0x400e85cc 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpuart6_rts_b: IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B { + pinmux = <0x400e80bc 3 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_qtimer4_timer1: IOMUXC_GPIO_EMC_B2_01_QTIMER4_TIMER1 { + pinmux = <0x400e80bc 2 0x400e8664 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_semc_data17: IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 { + pinmux = <0x400e80bc 0 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_usdhc2_cd_b: IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B { + pinmux = <0x400e80bc 1 0x400e86d0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_in21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_inout21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A { + pinmux = <0x400e80c0 11 0x400e8534 1 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexspi2_b_data04: IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 { + pinmux = <0x400e80c0 4 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio8_io12: IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 { + pinmux = <0x400e80c0 10 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12_cm7: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12_CM7 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_lpspi1_sdo: IOMUXC_GPIO_EMC_B2_02_LPSPI1_SDO { + pinmux = <0x400e80c0 8 0x400e85d8 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_semc_data18: IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 { + pinmux = <0x400e80c0 0 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_usdhc2_wp: IOMUXC_GPIO_EMC_B2_02_USDHC2_WP { + pinmux = <0x400e80c0 1 0x400e86d4 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_video_mux_csi_data23: IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 { + pinmux = <0x400e80c0 3 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_in22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_inout22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_enet_1g_tdata03: IOMUXC_GPIO_EMC_B2_03_ENET_1G_TDATA03 { + pinmux = <0x400e80c4 7 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B { + pinmux = <0x400e80c4 11 0x400e8544 1 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexspi2_b_data03: IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 { + pinmux = <0x400e80c4 4 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio8_io13: IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 { + pinmux = <0x400e80c4 10 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13_cm7: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13_CM7 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_lpspi1_sdi: IOMUXC_GPIO_EMC_B2_03_LPSPI1_SDI { + pinmux = <0x400e80c4 8 0x400e85d4 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_semc_data19: IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 { + pinmux = <0x400e80c4 0 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_usdhc2_vselect: IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT { + pinmux = <0x400e80c4 1 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_video_mux_csi_data22: IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 { + pinmux = <0x400e80c4 3 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_in23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_inout23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_enet_1g_tdata02: IOMUXC_GPIO_EMC_B2_04_ENET_1G_TDATA02 { + pinmux = <0x400e80c8 7 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A { + pinmux = <0x400e80c8 11 0x400e8538 1 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexspi2_b_data02: IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 { + pinmux = <0x400e80c8 4 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio8_io14: IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 { + pinmux = <0x400e80c8 10 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14_cm7: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14_CM7 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_lpspi3_sck: IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK { + pinmux = <0x400e80c8 8 0x400e8600 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_sai2_mclk: IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK { + pinmux = <0x400e80c8 2 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_semc_data20: IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 { + pinmux = <0x400e80c8 0 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_usdhc2_reset_b: IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B { + pinmux = <0x400e80c8 1 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_video_mux_csi_data21: IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 { + pinmux = <0x400e80c8 3 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_in24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_inout24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_enet_1g_rx_clk: IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK { + pinmux = <0x400e80cc 7 0x400e84cc 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B { + pinmux = <0x400e80cc 11 0x400e8548 1 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexspi2_b_data01: IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 { + pinmux = <0x400e80cc 4 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio8_io15: IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 { + pinmux = <0x400e80cc 10 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15_cm7: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15_CM7 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpt3_clk: IOMUXC_GPIO_EMC_B2_05_GPT3_CLK { + pinmux = <0x400e80cc 1 0x400e8598 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_lpspi3_pcs0: IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 { + pinmux = <0x400e80cc 8 0x400e85f0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_pit1_trigger00: IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER00 { + pinmux = <0x400e80cc 9 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_sai2_rx_sync: IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC { + pinmux = <0x400e80cc 2 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_semc_data21: IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 { + pinmux = <0x400e80cc 0 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_video_mux_csi_data20: IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 { + pinmux = <0x400e80cc 3 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_in25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_inout25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_enet_1g_tx_er: IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER { + pinmux = <0x400e80d0 7 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A { + pinmux = <0x400e80d0 11 0x400e853c 1 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexspi2_b_data00: IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 { + pinmux = <0x400e80d0 4 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio8_io16: IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 { + pinmux = <0x400e80d0 10 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16_cm7: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16_CM7 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpt3_capture1: IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 { + pinmux = <0x400e80d0 1 0x400e8590 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_lpspi3_sdo: IOMUXC_GPIO_EMC_B2_06_LPSPI3_SDO { + pinmux = <0x400e80d0 8 0x400e8608 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_pit1_trigger01: IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER01 { + pinmux = <0x400e80d0 9 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_sai2_rx_bclk: IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK { + pinmux = <0x400e80d0 2 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_semc_data22: IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 { + pinmux = <0x400e80d0 0 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_video_mux_csi_data19: IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 { + pinmux = <0x400e80d0 3 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_in26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_IN26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_inout26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_enet_1g_rdata03: IOMUXC_GPIO_EMC_B2_07_ENET_1G_RDATA03 { + pinmux = <0x400e80d4 7 0x400e84dc 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B { + pinmux = <0x400e80d4 11 0x400e854c 1 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexspi2_b_dqs: IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS { + pinmux = <0x400e80d4 4 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio8_io17: IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 { + pinmux = <0x400e80d4 10 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17_cm7: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17_CM7 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpt3_capture2: IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 { + pinmux = <0x400e80d4 1 0x400e8594 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_lpspi3_sdi: IOMUXC_GPIO_EMC_B2_07_LPSPI3_SDI { + pinmux = <0x400e80d4 8 0x400e8604 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_pit1_trigger02: IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER02 { + pinmux = <0x400e80d4 9 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_sai2_rx_data: IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA { + pinmux = <0x400e80d4 2 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_semc_data23: IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 { + pinmux = <0x400e80d4 0 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_video_mux_csi_data18: IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 { + pinmux = <0x400e80d4 3 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_in27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_IN27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_inout27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_enet_1g_rdata02: IOMUXC_GPIO_EMC_B2_08_ENET_1G_RDATA02 { + pinmux = <0x400e80d8 7 0x400e84d8 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B { + pinmux = <0x400e80d8 4 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio8_io18: IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 { + pinmux = <0x400e80d8 10 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18_cm7: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18_CM7 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpt3_compare1: IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 { + pinmux = <0x400e80d8 1 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_lpspi3_pcs1: IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 { + pinmux = <0x400e80d8 8 0x400e85f4 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_pit1_trigger03: IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER03 { + pinmux = <0x400e80d8 9 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_sai2_tx_data: IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA { + pinmux = <0x400e80d8 2 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_semc_dm02: IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 { + pinmux = <0x400e80d8 0 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_video_mux_csi_data17: IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 { + pinmux = <0x400e80d8 3 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_in28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_IN28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_inout28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_enet_1g_crs: IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS { + pinmux = <0x400e80dc 7 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_flexspi2_b_sclk: IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK { + pinmux = <0x400e80dc 4 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio8_io19: IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 { + pinmux = <0x400e80dc 10 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19_cm7: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19_CM7 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpt3_compare2: IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 { + pinmux = <0x400e80dc 1 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_lpspi3_pcs2: IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 { + pinmux = <0x400e80dc 8 0x400e85f8 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_qtimer1_timer0: IOMUXC_GPIO_EMC_B2_09_QTIMER1_TIMER0 { + pinmux = <0x400e80dc 9 0x400e863c 1 0x400e8320>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_sai2_tx_bclk: IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK { + pinmux = <0x400e80dc 2 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_semc_data24: IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 { + pinmux = <0x400e80dc 0 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_video_mux_csi_data16: IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 { + pinmux = <0x400e80dc 3 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_in29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_IN29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_inout29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_enet_1g_col: IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL { + pinmux = <0x400e80e0 7 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_flexspi2_a_sclk: IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK { + pinmux = <0x400e80e0 4 0x400e858c 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio8_io20: IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 { + pinmux = <0x400e80e0 10 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20_cm7: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20_CM7 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpt3_compare3: IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 { + pinmux = <0x400e80e0 1 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_lpspi3_pcs3: IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 { + pinmux = <0x400e80e0 8 0x400e85fc 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_qtimer1_timer1: IOMUXC_GPIO_EMC_B2_10_QTIMER1_TIMER1 { + pinmux = <0x400e80e0 9 0x400e8640 1 0x400e8324>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_sai2_tx_sync: IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC { + pinmux = <0x400e80e0 2 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_semc_data25: IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 { + pinmux = <0x400e80e0 0 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_video_mux_csi_field: IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD { + pinmux = <0x400e80e0 3 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_in30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_IN30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_inout30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_enet_1g_tdata00: IOMUXC_GPIO_EMC_B2_11_ENET_1G_TDATA00 { + pinmux = <0x400e80e4 2 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B { + pinmux = <0x400e80e4 4 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio8_io21: IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 { + pinmux = <0x400e80e4 10 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21_cm7: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21_CM7 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_qtimer1_timer2: IOMUXC_GPIO_EMC_B2_11_QTIMER1_TIMER2 { + pinmux = <0x400e80e4 9 0x400e8644 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sai3_rx_sync: IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC { + pinmux = <0x400e80e4 3 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_semc_data26: IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 { + pinmux = <0x400e80e4 0 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sim1_trxd: IOMUXC_GPIO_EMC_B2_11_SIM1_TRXD { + pinmux = <0x400e80e4 8 0x400e869c 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_spdif_in: IOMUXC_GPIO_EMC_B2_11_SPDIF_IN { + pinmux = <0x400e80e4 1 0x400e86b4 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_in31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_IN31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_inout31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_enet_1g_tdata01: IOMUXC_GPIO_EMC_B2_12_ENET_1G_TDATA01 { + pinmux = <0x400e80e8 2 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_flexspi2_a_dqs: IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS { + pinmux = <0x400e80e8 4 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio8_io22: IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 { + pinmux = <0x400e80e8 10 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22_cm7: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22_CM7 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_qtimer1_timer3: IOMUXC_GPIO_EMC_B2_12_QTIMER1_TIMER3 { + pinmux = <0x400e80e8 9 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4030 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sai3_rx_bclk: IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK { + pinmux = <0x400e80e8 3 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_semc_data27: IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 { + pinmux = <0x400e80e8 0 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sim1_clk: IOMUXC_GPIO_EMC_B2_12_SIM1_CLK { + pinmux = <0x400e80e8 8 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_spdif_out: IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT { + pinmux = <0x400e80e8 1 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_in32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_IN32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_inout32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_enet_1g_tx_en: IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN { + pinmux = <0x400e80ec 2 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_flexspi2_a_data00: IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 { + pinmux = <0x400e80ec 4 0x400e857c 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio8_io23: IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 { + pinmux = <0x400e80ec 10 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23_cm7: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23_CM7 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_qtimer2_timer0: IOMUXC_GPIO_EMC_B2_13_QTIMER2_TIMER0 { + pinmux = <0x400e80ec 9 0x400e8648 1 0x400e8330>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sai3_rx_data: IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA { + pinmux = <0x400e80ec 3 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_semc_data28: IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 { + pinmux = <0x400e80ec 0 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sim1_rst_b: IOMUXC_GPIO_EMC_B2_13_SIM1_RST_B { + pinmux = <0x400e80ec 8 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_in33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_IN33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_inout33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_enet_1g_tx_clk_io: IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO { + pinmux = <0x400e80f0 2 0x400e84e8 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_flexspi2_a_data01: IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 { + pinmux = <0x400e80f0 4 0x400e8580 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio8_io24: IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 { + pinmux = <0x400e80f0 10 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24_cm7: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24_CM7 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_qtimer2_timer1: IOMUXC_GPIO_EMC_B2_14_QTIMER2_TIMER1 { + pinmux = <0x400e80f0 9 0x400e864c 1 0x400e8334>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sai3_tx_data: IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA { + pinmux = <0x400e80f0 3 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_semc_data29: IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 { + pinmux = <0x400e80f0 0 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sim1_sven: IOMUXC_GPIO_EMC_B2_14_SIM1_SVEN { + pinmux = <0x400e80f0 8 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_in34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_IN34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_inout34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_enet_1g_rdata00: IOMUXC_GPIO_EMC_B2_15_ENET_1G_RDATA00 { + pinmux = <0x400e80f4 2 0x400e84d0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_flexspi2_a_data02: IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 { + pinmux = <0x400e80f4 4 0x400e8584 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio8_io25: IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 { + pinmux = <0x400e80f4 10 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25_cm7: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25_CM7 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_qtimer2_timer2: IOMUXC_GPIO_EMC_B2_15_QTIMER2_TIMER2 { + pinmux = <0x400e80f4 9 0x400e8650 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sai3_tx_bclk: IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK { + pinmux = <0x400e80f4 3 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_semc_data30: IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 { + pinmux = <0x400e80f4 0 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sim1_pd: IOMUXC_GPIO_EMC_B2_15_SIM1_PD { + pinmux = <0x400e80f4 8 0x400e86a0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_in35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_IN35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_inout35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_enet_1g_rdata01: IOMUXC_GPIO_EMC_B2_16_ENET_1G_RDATA01 { + pinmux = <0x400e80f8 2 0x400e84d4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_flexspi2_a_data03: IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 { + pinmux = <0x400e80f8 4 0x400e8588 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio8_io26: IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 { + pinmux = <0x400e80f8 10 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26_cm7: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26_CM7 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_qtimer2_timer3: IOMUXC_GPIO_EMC_B2_16_QTIMER2_TIMER3 { + pinmux = <0x400e80f8 9 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4034 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sai3_tx_sync: IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC { + pinmux = <0x400e80f8 3 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_semc_data31: IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 { + pinmux = <0x400e80f8 0 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sim1_power_fail: IOMUXC_GPIO_EMC_B2_16_SIM1_POWER_FAIL { + pinmux = <0x400e80f8 8 0x400e86a4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_in14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_IN14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_enet_1g_rx_en: IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN { + pinmux = <0x400e80fc 2 0x400e84e0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_flexspi2_a_data04: IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 { + pinmux = <0x400e80fc 4 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio8_io27: IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 { + pinmux = <0x400e80fc 10 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27_cm7: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27_CM7 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_qtimer3_timer0: IOMUXC_GPIO_EMC_B2_17_QTIMER3_TIMER0 { + pinmux = <0x400e80fc 9 0x400e8654 1 0x400e8340>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_sai3_mclk: IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK { + pinmux = <0x400e80fc 3 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_semc_dm03: IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 { + pinmux = <0x400e80fc 0 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_wdog1_wdog_any: IOMUXC_GPIO_EMC_B2_17_WDOG1_WDOG_ANY { + pinmux = <0x400e80fc 8 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_in15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_IN15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_enet_1g_rx_er: IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER { + pinmux = <0x400e8100 2 0x400e84e4 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_ewm_ewm_out_b: IOMUXC_GPIO_EMC_B2_18_EWM_EWM_OUT_B { + pinmux = <0x400e8100 3 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi1_a_dqs: IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS { + pinmux = <0x400e8100 6 0x400e8550 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi2_a_data05: IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 { + pinmux = <0x400e8100 4 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio8_io28: IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 { + pinmux = <0x400e8100 10 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28_cm7: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28_CM7 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_18_QTIMER3_TIMER1 { + pinmux = <0x400e8100 9 0x400e8658 1 0x400e8344>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_semc_dqs4: IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 { + pinmux = <0x400e8100 0 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_wdog1_wdog_b: IOMUXC_GPIO_EMC_B2_18_WDOG1_WDOG_B { + pinmux = <0x400e8100 8 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_IN16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC { + pinmux = <0x400e8104 2 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_ref_clk1: IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK1 { + pinmux = <0x400e8104 3 0x400e84c4 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_MDC { + pinmux = <0x400e8104 1 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_flexspi2_a_data06: IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 { + pinmux = <0x400e8104 4 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio8_io29: IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 { + pinmux = <0x400e8104 10 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29_cm7: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29_CM7 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_qtimer3_timer2: IOMUXC_GPIO_EMC_B2_19_QTIMER3_TIMER2 { + pinmux = <0x400e8104 9 0x400e865c 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_semc_clkx00: IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 { + pinmux = <0x400e8104 0 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_1g_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO { + pinmux = <0x400e8108 2 0x400e84c8 1 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_MDIO { + pinmux = <0x400e8108 1 0x400e84ac 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_flexspi2_a_data07: IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 { + pinmux = <0x400e8108 4 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio8_io30: IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 { + pinmux = <0x400e8108 10 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30_cm7: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30_CM7 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_qtimer3_timer3: IOMUXC_GPIO_EMC_B2_20_QTIMER3_TIMER3 { + pinmux = <0x400e8108 9 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e4038 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_semc_clkx01: IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 { + pinmux = <0x400e8108 0 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_can3_tx: IOMUXC_LPSR_GPIO_LPSR_00_CAN3_TX { + pinmux = <0x40c08000 0 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_cm4_imxrt_txev: IOMUXC_LPSR_GPIO_LPSR_00_CM4_IMXRT_TXEV { + pinmux = <0x40c08000 3 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio12_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO12_IO00 { + pinmux = <0x40c08000 10 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio_mux6_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO_MUX6_IO00 { + pinmux = <0x40c08000 5 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_00_LPUART12_TX { + pinmux = <0x40c08000 6 0x40c080b0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mic_clk: IOMUXC_LPSR_GPIO_LPSR_00_MIC_CLK { + pinmux = <0x40c08000 1 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mqs_right: IOMUXC_LPSR_GPIO_LPSR_00_MQS_RIGHT { + pinmux = <0x40c08000 2 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_00_SAI4_MCLK { + pinmux = <0x40c08000 7 0x40c080c8 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_can3_rx: IOMUXC_LPSR_GPIO_LPSR_01_CAN3_RX { + pinmux = <0x40c08004 0 0x40c08080 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_cm4_imxrt_rxev: IOMUXC_LPSR_GPIO_LPSR_01_CM4_IMXRT_RXEV { + pinmux = <0x40c08004 3 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio12_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO12_IO01 { + pinmux = <0x40c08004 10 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO_MUX6_IO01 { + pinmux = <0x40c08004 5 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_01_LPUART12_RX { + pinmux = <0x40c08004 6 0x40c080ac 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_01_MIC_BITSTREAM00 { + pinmux = <0x40c08004 1 0x40c080b4 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mqs_left: IOMUXC_LPSR_GPIO_LPSR_01_MQS_LEFT { + pinmux = <0x40c08004 2 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio12_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO12_IO02 { + pinmux = <0x40c08008 10 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO_MUX6_IO02 { + pinmux = <0x40c08008 5 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_02_LPSPI5_SCK { + pinmux = <0x40c08008 1 0x40c08098 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_mqs_right: IOMUXC_LPSR_GPIO_LPSR_02_MQS_RIGHT { + pinmux = <0x40c08008 3 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_02_SAI4_TX_DATA { + pinmux = <0x40c08008 2 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_src_boot_mode00: IOMUXC_LPSR_GPIO_LPSR_02_SRC_BOOT_MODE00 { + pinmux = <0x40c08008 0 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio12_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO12_IO03 { + pinmux = <0x40c0800c 10 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO_MUX6_IO03 { + pinmux = <0x40c0800c 5 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_03_LPSPI5_PCS0 { + pinmux = <0x40c0800c 1 0x40c08094 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_mqs_left: IOMUXC_LPSR_GPIO_LPSR_03_MQS_LEFT { + pinmux = <0x40c0800c 3 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_03_SAI4_TX_SYNC { + pinmux = <0x40c0800c 2 0x40c080dc 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_src_boot_mode01: IOMUXC_LPSR_GPIO_LPSR_03_SRC_BOOT_MODE01 { + pinmux = <0x40c0800c 0 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio12_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO12_IO04 { + pinmux = <0x40c08010 10 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO_MUX6_IO04 { + pinmux = <0x40c08010 5 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_04_LPI2C5_SDA { + pinmux = <0x40c08010 0 0x40c08088 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_04_LPSPI5_SDO { + pinmux = <0x40c08010 1 0x40c080a0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_04_LPUART11_TX { + pinmux = <0x40c08010 6 0x40c080a8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart12_rts_b: IOMUXC_LPSR_GPIO_LPSR_04_LPUART12_RTS_B { + pinmux = <0x40c08010 3 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_04_SAI4_TX_BCLK { + pinmux = <0x40c08010 2 0x40c080d8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio12_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO12_IO05 { + pinmux = <0x40c08014 10 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO_MUX6_IO05 { + pinmux = <0x40c08014 5 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_05_LPI2C5_SCL { + pinmux = <0x40c08014 0 0x40c08084 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_05_LPSPI5_SDI { + pinmux = <0x40c08014 1 0x40c0809c 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_05_LPUART11_RX { + pinmux = <0x40c08014 6 0x40c080a4 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart12_cts_b: IOMUXC_LPSR_GPIO_LPSR_05_LPUART12_CTS_B { + pinmux = <0x40c08014 3 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_05_SAI4_MCLK { + pinmux = <0x40c08014 2 0x40c080c8 1 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_can3_tx: IOMUXC_LPSR_GPIO_LPSR_06_CAN3_TX { + pinmux = <0x40c08018 6 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio12_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO12_IO06 { + pinmux = <0x40c08018 10 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO_MUX6_IO06 { + pinmux = <0x40c08018 5 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_06_LPI2C6_SDA { + pinmux = <0x40c08018 0 0x40c08090 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi5_pcs1: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI5_PCS1 { + pinmux = <0x40c08018 8 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi6_pcs3: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI6_PCS3 { + pinmux = <0x40c08018 4 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_06_LPUART12_TX { + pinmux = <0x40c08018 3 0x40c080b0 1 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_06_PIT2_TRIGGER03 { + pinmux = <0x40c08018 7 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_06_SAI4_RX_DATA { + pinmux = <0x40c08018 2 0x40c080d0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_can3_rx: IOMUXC_LPSR_GPIO_LPSR_07_CAN3_RX { + pinmux = <0x40c0801c 6 0x40c08080 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio12_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO12_IO07 { + pinmux = <0x40c0801c 10 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO_MUX6_IO07 { + pinmux = <0x40c0801c 5 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_07_LPI2C6_SCL { + pinmux = <0x40c0801c 0 0x40c0808c 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi5_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI5_PCS2 { + pinmux = <0x40c0801c 8 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi6_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI6_PCS2 { + pinmux = <0x40c0801c 4 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_07_LPUART12_RX { + pinmux = <0x40c0801c 3 0x40c080ac 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_07_PIT2_TRIGGER02 { + pinmux = <0x40c0801c 7 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_07_SAI4_RX_BCLK { + pinmux = <0x40c0801c 2 0x40c080cc 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_can3_tx: IOMUXC_LPSR_GPIO_LPSR_08_CAN3_TX { + pinmux = <0x40c08020 1 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio12_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO12_IO08 { + pinmux = <0x40c08020 10 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO_MUX6_IO08 { + pinmux = <0x40c08020 5 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_08_LPI2C5_SDA { + pinmux = <0x40c08020 6 0x40c08088 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi5_pcs3: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI5_PCS3 { + pinmux = <0x40c08020 8 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi6_pcs1: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI6_PCS1 { + pinmux = <0x40c08020 4 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_08_LPUART11_TX { + pinmux = <0x40c08020 0 0x40c080a8 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_mic_clk: IOMUXC_LPSR_GPIO_LPSR_08_MIC_CLK { + pinmux = <0x40c08020 3 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_08_PIT2_TRIGGER01 { + pinmux = <0x40c08020 7 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_08_SAI4_RX_SYNC { + pinmux = <0x40c08020 2 0x40c080d4 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_can3_rx: IOMUXC_LPSR_GPIO_LPSR_09_CAN3_RX { + pinmux = <0x40c08024 1 0x40c08080 2 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio12_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO12_IO09 { + pinmux = <0x40c08024 10 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO_MUX6_IO09 { + pinmux = <0x40c08024 5 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_09_LPI2C5_SCL { + pinmux = <0x40c08024 6 0x40c08084 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpspi6_pcs0: IOMUXC_LPSR_GPIO_LPSR_09_LPSPI6_PCS0 { + pinmux = <0x40c08024 4 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_09_LPUART11_RX { + pinmux = <0x40c08024 0 0x40c080a4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_09_MIC_BITSTREAM00 { + pinmux = <0x40c08024 3 0x40c080b4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_09_PIT2_TRIGGER00 { + pinmux = <0x40c08024 2 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_09_SAI4_TX_DATA { + pinmux = <0x40c08024 7 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio12_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO12_IO10 { + pinmux = <0x40c08028 10 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO_MUX6_IO10 { + pinmux = <0x40c08028 5 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_jtag_mux_trstb: IOMUXC_LPSR_GPIO_LPSR_10_JTAG_MUX_TRSTB { + pinmux = <0x40c08028 0 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c5_scls: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C5_SCLS { + pinmux = <0x40c08028 6 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C6_SDA { + pinmux = <0x40c08028 2 0x40c08090 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpspi6_sck: IOMUXC_LPSR_GPIO_LPSR_10_LPSPI6_SCK { + pinmux = <0x40c08028 4 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart11_cts_b: IOMUXC_LPSR_GPIO_LPSR_10_LPUART11_CTS_B { + pinmux = <0x40c08028 1 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_10_LPUART12_TX { + pinmux = <0x40c08028 8 0x40c080b0 2 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_10_MIC_BITSTREAM01 { + pinmux = <0x40c08028 3 0x40c080b8 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_10_SAI4_TX_SYNC { + pinmux = <0x40c08028 7 0x40c080dc 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_arm_trace_swo: IOMUXC_LPSR_GPIO_LPSR_11_ARM_TRACE_SWO { + pinmux = <0x40c0802c 7 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio12_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO12_IO11 { + pinmux = <0x40c0802c 10 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO_MUX6_IO11 { + pinmux = <0x40c0802c 5 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_jtag_mux_tdo: IOMUXC_LPSR_GPIO_LPSR_11_JTAG_MUX_TDO { + pinmux = <0x40c0802c 0 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c5_sdas: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C5_SDAS { + pinmux = <0x40c0802c 6 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C6_SCL { + pinmux = <0x40c0802c 2 0x40c0808c 1 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpspi6_sdo: IOMUXC_LPSR_GPIO_LPSR_11_LPSPI6_SDO { + pinmux = <0x40c0802c 4 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart11_rts_b: IOMUXC_LPSR_GPIO_LPSR_11_LPUART11_RTS_B { + pinmux = <0x40c0802c 1 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_11_LPUART12_RX { + pinmux = <0x40c0802c 8 0x40c080ac 2 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_11_MIC_BITSTREAM02 { + pinmux = <0x40c0802c 3 0x40c080bc 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio12_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO12_IO12 { + pinmux = <0x40c08030 10 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO_MUX6_IO12 { + pinmux = <0x40c08030 5 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_jtag_mux_tdi: IOMUXC_LPSR_GPIO_LPSR_12_JTAG_MUX_TDI { + pinmux = <0x40c08030 0 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpi2c5_hreq: IOMUXC_LPSR_GPIO_LPSR_12_LPI2C5_HREQ { + pinmux = <0x40c08030 6 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI5_SCK { + pinmux = <0x40c08030 8 0x40c08098 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi6_sdi: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI6_SDI { + pinmux = <0x40c08030 4 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_12_MIC_BITSTREAM03 { + pinmux = <0x40c08030 3 0x40c080c0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_12_PIT2_TRIGGER00 { + pinmux = <0x40c08030 1 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_12_SAI4_TX_BCLK { + pinmux = <0x40c08030 7 0x40c080d8 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio12_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO12_IO13 { + pinmux = <0x40c08034 10 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO_MUX6_IO13 { + pinmux = <0x40c08034 5 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_jtag_mux_mod: IOMUXC_LPSR_GPIO_LPSR_13_JTAG_MUX_MOD { + pinmux = <0x40c08034 0 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_13_LPSPI5_PCS0 { + pinmux = <0x40c08034 8 0x40c08094 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_13_MIC_BITSTREAM01 { + pinmux = <0x40c08034 1 0x40c080b8 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_13_PIT2_TRIGGER01 { + pinmux = <0x40c08034 2 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_13_SAI4_RX_DATA { + pinmux = <0x40c08034 7 0x40c080d0 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio12_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO12_IO14 { + pinmux = <0x40c08038 10 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO_MUX6_IO14 { + pinmux = <0x40c08038 5 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_jtag_mux_tck: IOMUXC_LPSR_GPIO_LPSR_14_JTAG_MUX_TCK { + pinmux = <0x40c08038 0 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_14_LPSPI5_SDO { + pinmux = <0x40c08038 8 0x40c080a0 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_14_MIC_BITSTREAM02 { + pinmux = <0x40c08038 1 0x40c080bc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_14_PIT2_TRIGGER02 { + pinmux = <0x40c08038 2 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_14_SAI4_RX_BCLK { + pinmux = <0x40c08038 7 0x40c080cc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio12_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO12_IO15 { + pinmux = <0x40c0803c 10 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO_MUX6_IO15 { + pinmux = <0x40c0803c 5 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_jtag_mux_tms: IOMUXC_LPSR_GPIO_LPSR_15_JTAG_MUX_TMS { + pinmux = <0x40c0803c 0 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_15_LPSPI5_SDI { + pinmux = <0x40c0803c 8 0x40c0809c 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_15_MIC_BITSTREAM03 { + pinmux = <0x40c0803c 1 0x40c080c0 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_15_PIT2_TRIGGER03 { + pinmux = <0x40c0803c 2 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_15_SAI4_RX_SYNC { + pinmux = <0x40c0803c 7 0x40c080d4 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi2_a_ss0_b: IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B { + pinmux = <0x400e819c 6 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio10_io03: IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 { + pinmux = <0x400e819c 10 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio_mux4_io03: IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 { + pinmux = <0x400e819c 5 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpt4_capture1: IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 { + pinmux = <0x400e819c 3 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_kpp_row07: IOMUXC_GPIO_SD_B1_00_KPP_ROW07 { + pinmux = <0x400e819c 8 0x400e85a8 1 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc1_cmd: IOMUXC_GPIO_SD_B1_00_USDHC1_CMD { + pinmux = <0x400e819c 0 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi2_a_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK { + pinmux = <0x400e81a0 6 0x400e858c 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio10_io04: IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 { + pinmux = <0x400e81a0 10 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio_mux4_io04: IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 { + pinmux = <0x400e81a0 5 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpt4_capture2: IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 { + pinmux = <0x400e81a0 3 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_kpp_col07: IOMUXC_GPIO_SD_B1_01_KPP_COL07 { + pinmux = <0x400e81a0 8 0x400e85a0 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc1_clk: IOMUXC_GPIO_SD_B1_01_USDHC1_CLK { + pinmux = <0x400e81a0 0 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_in21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_inout21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81a4 9 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi2_a_data00: IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 { + pinmux = <0x400e81a4 6 0x400e857c 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio10_io05: IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 { + pinmux = <0x400e81a4 10 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio_mux4_io05: IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 { + pinmux = <0x400e81a4 5 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpt4_compare1: IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 { + pinmux = <0x400e81a4 3 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_kpp_row06: IOMUXC_GPIO_SD_B1_02_KPP_ROW06 { + pinmux = <0x400e81a4 8 0x400e85a4 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc1_data0: IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 { + pinmux = <0x400e81a4 0 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_in22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_inout22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi1_b_ss1_b: IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B { + pinmux = <0x400e81a8 9 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi2_a_data01: IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 { + pinmux = <0x400e81a8 6 0x400e8580 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio10_io06: IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 { + pinmux = <0x400e81a8 10 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio_mux4_io06: IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 { + pinmux = <0x400e81a8 5 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpt4_compare2: IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 { + pinmux = <0x400e81a8 3 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_kpp_col06: IOMUXC_GPIO_SD_B1_03_KPP_COL06 { + pinmux = <0x400e81a8 8 0x400e859c 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc1_data1: IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 { + pinmux = <0x400e81a8 0 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_in23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_inout23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81ac 8 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi2_a_data02: IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 { + pinmux = <0x400e81ac 6 0x400e8584 1 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio10_io07: IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 { + pinmux = <0x400e81ac 10 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio_mux4_io07: IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 { + pinmux = <0x400e81ac 5 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpt4_compare3: IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 { + pinmux = <0x400e81ac 3 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc1_data2: IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 { + pinmux = <0x400e81ac 0 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_in24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_inout24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi1_b_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS { + pinmux = <0x400e81b0 8 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi2_a_data03: IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 { + pinmux = <0x400e81b0 6 0x400e8588 1 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio10_io08: IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 { + pinmux = <0x400e81b0 10 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio_mux4_io08: IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 { + pinmux = <0x400e81b0 5 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpt4_clk: IOMUXC_GPIO_SD_B1_05_GPT4_CLK { + pinmux = <0x400e81b0 3 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc1_data3: IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 { + pinmux = <0x400e81b0 0 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_in25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_inout25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_enet_1g_rx_en: IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN { + pinmux = <0x400e81b4 2 0x400e84e0 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_flexspi1_b_data03: IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 { + pinmux = <0x400e81b4 1 0x400e8570 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio10_io09: IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 { + pinmux = <0x400e81b4 10 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio_mux4_io09: IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 { + pinmux = <0x400e81b4 5 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpspi4_sck: IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK { + pinmux = <0x400e81b4 4 0x400e8610 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpuart9_tx: IOMUXC_GPIO_SD_B2_00_LPUART9_TX { + pinmux = <0x400e81b4 3 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_usdhc2_data3: IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 { + pinmux = <0x400e81b4 0 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_enet_1g_rx_clk: IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK { + pinmux = <0x400e81b8 2 0x400e84cc 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_flexspi1_b_data02: IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 { + pinmux = <0x400e81b8 1 0x400e856c 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio10_io10: IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 { + pinmux = <0x400e81b8 10 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio_mux4_io10: IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 { + pinmux = <0x400e81b8 5 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpspi4_pcs0: IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 { + pinmux = <0x400e81b8 4 0x400e860c 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpuart9_rx: IOMUXC_GPIO_SD_B2_01_LPUART9_RX { + pinmux = <0x400e81b8 3 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_usdhc2_data2: IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 { + pinmux = <0x400e81b8 0 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_enet_1g_rdata00: IOMUXC_GPIO_SD_B2_02_ENET_1G_RDATA00 { + pinmux = <0x400e81bc 2 0x400e84d0 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_flexspi1_b_data01: IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 { + pinmux = <0x400e81bc 1 0x400e8568 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio10_io11: IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 { + pinmux = <0x400e81bc 10 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio_mux4_io11: IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 { + pinmux = <0x400e81bc 5 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpspi4_sdo: IOMUXC_GPIO_SD_B2_02_LPSPI4_SDO { + pinmux = <0x400e81bc 4 0x400e8618 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpuart9_cts_b: IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B { + pinmux = <0x400e81bc 3 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_usdhc2_data1: IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 { + pinmux = <0x400e81bc 0 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_enet_1g_rdata01: IOMUXC_GPIO_SD_B2_03_ENET_1G_RDATA01 { + pinmux = <0x400e81c0 2 0x400e84d4 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_flexspi1_b_data00: IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 { + pinmux = <0x400e81c0 1 0x400e8564 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio10_io12: IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 { + pinmux = <0x400e81c0 10 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio_mux4_io12: IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 { + pinmux = <0x400e81c0 5 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpspi4_sdi: IOMUXC_GPIO_SD_B2_03_LPSPI4_SDI { + pinmux = <0x400e81c0 4 0x400e8614 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpuart9_rts_b: IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B { + pinmux = <0x400e81c0 3 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_usdhc2_data0: IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 { + pinmux = <0x400e81c0 0 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_enet_1g_rdata02: IOMUXC_GPIO_SD_B2_04_ENET_1G_RDATA02 { + pinmux = <0x400e81c4 2 0x400e84d8 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81c4 3 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_b_sclk: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK { + pinmux = <0x400e81c4 1 0x400e8578 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio10_io13: IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 { + pinmux = <0x400e81c4 10 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio_mux4_io13: IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 { + pinmux = <0x400e81c4 5 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_lpspi4_pcs1: IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 { + pinmux = <0x400e81c4 4 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_usdhc2_clk: IOMUXC_GPIO_SD_B2_04_USDHC2_CLK { + pinmux = <0x400e81c4 0 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_enet_1g_rdata03: IOMUXC_GPIO_SD_B2_05_ENET_1G_RDATA03 { + pinmux = <0x400e81c8 2 0x400e84dc 1 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_a_dqs: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS { + pinmux = <0x400e81c8 1 0x400e8550 2 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81c8 3 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio10_io14: IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 { + pinmux = <0x400e81c8 10 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio_mux4_io14: IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 { + pinmux = <0x400e81c8 5 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_lpspi4_pcs2: IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 { + pinmux = <0x400e81c8 4 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_usdhc2_cmd: IOMUXC_GPIO_SD_B2_05_USDHC2_CMD { + pinmux = <0x400e81c8 0 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_enet_1g_tdata03: IOMUXC_GPIO_SD_B2_06_ENET_1G_TDATA03 { + pinmux = <0x400e81cc 2 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_flexspi1_a_ss0_b: IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B { + pinmux = <0x400e81cc 1 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio10_io15: IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 { + pinmux = <0x400e81cc 10 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio_mux4_io15: IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 { + pinmux = <0x400e81cc 5 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpt6_capture1: IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 { + pinmux = <0x400e81cc 4 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_lpspi4_pcs3: IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 { + pinmux = <0x400e81cc 3 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B { + pinmux = <0x400e81cc 0 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_1g_tdata02: IOMUXC_GPIO_SD_B2_07_ENET_1G_TDATA02 { + pinmux = <0x400e81d0 2 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_tx_er: IOMUXC_GPIO_SD_B2_07_ENET_TX_ER { + pinmux = <0x400e81d0 8 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_flexspi1_a_sclk: IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK { + pinmux = <0x400e81d0 1 0x400e8574 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio10_io16: IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 { + pinmux = <0x400e81d0 10 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio_mux4_io16: IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 { + pinmux = <0x400e81d0 5 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpt6_capture2: IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 { + pinmux = <0x400e81d0 4 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpspi2_sck: IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK { + pinmux = <0x400e81d0 6 0x400e85e4 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpuart3_cts_b: IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B { + pinmux = <0x400e81d0 3 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_usdhc2_strobe: IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE { + pinmux = <0x400e81d0 0 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_enet_1g_tdata01: IOMUXC_GPIO_SD_B2_08_ENET_1G_TDATA01 { + pinmux = <0x400e81d4 2 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_flexspi1_a_data00: IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 { + pinmux = <0x400e81d4 1 0x400e8554 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio10_io17: IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 { + pinmux = <0x400e81d4 10 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio_mux4_io17: IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 { + pinmux = <0x400e81d4 5 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpt6_compare1: IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 { + pinmux = <0x400e81d4 4 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpspi2_pcs0: IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 { + pinmux = <0x400e81d4 6 0x400e85dc 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpuart3_rts_b: IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B { + pinmux = <0x400e81d4 3 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_usdhc2_data4: IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 { + pinmux = <0x400e81d4 0 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_enet_1g_tdata00: IOMUXC_GPIO_SD_B2_09_ENET_1G_TDATA00 { + pinmux = <0x400e81d8 2 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_flexspi1_a_data01: IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 { + pinmux = <0x400e81d8 1 0x400e8558 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio10_io18: IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 { + pinmux = <0x400e81d8 10 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio_mux4_io18: IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 { + pinmux = <0x400e81d8 5 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpt6_compare2: IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 { + pinmux = <0x400e81d8 4 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpspi2_sdo: IOMUXC_GPIO_SD_B2_09_LPSPI2_SDO { + pinmux = <0x400e81d8 6 0x400e85ec 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpuart5_cts_b: IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B { + pinmux = <0x400e81d8 3 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_usdhc2_data5: IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 { + pinmux = <0x400e81d8 0 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_enet_1g_tx_en: IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN { + pinmux = <0x400e81dc 2 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_flexspi1_a_data02: IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 { + pinmux = <0x400e81dc 1 0x400e855c 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio10_io19: IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 { + pinmux = <0x400e81dc 10 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio_mux4_io19: IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 { + pinmux = <0x400e81dc 5 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpt6_compare3: IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 { + pinmux = <0x400e81dc 4 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpspi2_sdi: IOMUXC_GPIO_SD_B2_10_LPSPI2_SDI { + pinmux = <0x400e81dc 6 0x400e85e8 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpuart5_rts_b: IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B { + pinmux = <0x400e81dc 3 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_usdhc2_data6: IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 { + pinmux = <0x400e81dc 0 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_ref_clk1: IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e81e0 3 0x400e84c4 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_tx_clk_io: IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e81e0 2 0x400e84e8 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_flexspi1_a_data03: IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 { + pinmux = <0x400e81e0 1 0x400e8560 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio10_io20: IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 { + pinmux = <0x400e81e0 10 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio_mux4_io20: IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 { + pinmux = <0x400e81e0 5 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpt6_clk: IOMUXC_GPIO_SD_B2_11_GPT6_CLK { + pinmux = <0x400e81e0 4 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_lpspi2_pcs1: IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 { + pinmux = <0x400e81e0 6 0x400e85e0 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_usdhc2_data7: IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 { + pinmux = <0x400e81e0 0 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03: IOMUXC_SNVS_GPIO_SNVS_00_DIG_GPIO13_IO03 { + pinmux = <0x40c9400c 5 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_snvs_lp_tamper00: IOMUXC_SNVS_GPIO_SNVS_00_DIG_SNVS_LP_TAMPER00 { + pinmux = <0x40c9400c 0 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04: IOMUXC_SNVS_GPIO_SNVS_01_DIG_GPIO13_IO04 { + pinmux = <0x40c94010 5 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_snvs_lp_tamper01: IOMUXC_SNVS_GPIO_SNVS_01_DIG_SNVS_LP_TAMPER01 { + pinmux = <0x40c94010 0 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05: IOMUXC_SNVS_GPIO_SNVS_02_DIG_GPIO13_IO05 { + pinmux = <0x40c94014 5 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_snvs_lp_tamper02: IOMUXC_SNVS_GPIO_SNVS_02_DIG_SNVS_LP_TAMPER02 { + pinmux = <0x40c94014 0 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06: IOMUXC_SNVS_GPIO_SNVS_03_DIG_GPIO13_IO06 { + pinmux = <0x40c94018 5 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_snvs_lp_tamper03: IOMUXC_SNVS_GPIO_SNVS_03_DIG_SNVS_LP_TAMPER03 { + pinmux = <0x40c94018 0 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07: IOMUXC_SNVS_GPIO_SNVS_04_DIG_GPIO13_IO07 { + pinmux = <0x40c9401c 5 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_snvs_lp_tamper04: IOMUXC_SNVS_GPIO_SNVS_04_DIG_SNVS_LP_TAMPER04 { + pinmux = <0x40c9401c 0 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08: IOMUXC_SNVS_GPIO_SNVS_05_DIG_GPIO13_IO08 { + pinmux = <0x40c94020 5 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_snvs_lp_tamper05: IOMUXC_SNVS_GPIO_SNVS_05_DIG_SNVS_LP_TAMPER05 { + pinmux = <0x40c94020 0 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09: IOMUXC_SNVS_GPIO_SNVS_06_DIG_GPIO13_IO09 { + pinmux = <0x40c94024 5 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_snvs_lp_tamper06: IOMUXC_SNVS_GPIO_SNVS_06_DIG_SNVS_LP_TAMPER06 { + pinmux = <0x40c94024 0 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10: IOMUXC_SNVS_GPIO_SNVS_07_DIG_GPIO13_IO10 { + pinmux = <0x40c94028 5 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_snvs_lp_tamper07: IOMUXC_SNVS_GPIO_SNVS_07_DIG_SNVS_LP_TAMPER07 { + pinmux = <0x40c94028 0 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11: IOMUXC_SNVS_GPIO_SNVS_08_DIG_GPIO13_IO11 { + pinmux = <0x40c9402c 5 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_snvs_lp_tamper08: IOMUXC_SNVS_GPIO_SNVS_08_DIG_SNVS_LP_TAMPER08 { + pinmux = <0x40c9402c 0 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12: IOMUXC_SNVS_GPIO_SNVS_09_DIG_GPIO13_IO12 { + pinmux = <0x40c94030 5 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_snvs_lp_tamper09: IOMUXC_SNVS_GPIO_SNVS_09_DIG_SNVS_LP_TAMPER09 { + pinmux = <0x40c94030 0 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_dig_src_reset_b: IOMUXC_SNVS_ONOFF_DIG_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x40c9403c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_gpio13_io01: IOMUXC_SNVS_PMIC_ON_REQ_DIG_GPIO13_IO01 { + pinmux = <0x40c94004 5 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_snvs_lp_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ { + pinmux = <0x40c94004 0 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_gpio13_io02: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_GPIO13_IO02 { + pinmux = <0x40c94008 5 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_pgmc_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_PGMC_PMIC_VSTBY_REQ { + pinmux = <0x40c94008 0 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_dig_src_por_b: IOMUXC_SNVS_POR_B_DIG_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x40c94038>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_dig_test_mode: IOMUXC_SNVS_TEST_MODE_DIG_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x40c94034>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_dig_gpio13_io00: IOMUXC_SNVS_WAKEUP_DIG_GPIO13_IO00 { + pinmux = <0x40c94000 5 0x0 0 0x40c94040>; + pin-snvs; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1172dvmaa-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1172dvmaa-pinctrl.dtsi new file mode 100644 index 000000000..761ffec50 --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1172dvmaa-pinctrl.dtsi @@ -0,0 +1,6212 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1172DVMAA + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_00_acmp1_in1: IOMUXC_GPIO_AD_00_ACMP1_IN1 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_can2_tx: IOMUXC_GPIO_AD_00_CAN2_TX { + pinmux = <0x400e810c 1 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_enet_1g_1588_event1_in: IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN { + pinmux = <0x400e810c 2 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexio2_flexio00: IOMUXC_GPIO_AD_00_FLEXIO2_FLEXIO00 { + pinmux = <0x400e810c 8 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexpwm1_pwm0_a: IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A { + pinmux = <0x400e810c 4 0x400e8500 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexspi2_b_ss1_b: IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B { + pinmux = <0x400e810c 9 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio8_io31: IOMUXC_GPIO_AD_00_GPIO8_IO31 { + pinmux = <0x400e810c 10 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31_cm7: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31_CM7 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpt2_capture1: IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 { + pinmux = <0x400e810c 3 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_lpuart7_tx: IOMUXC_GPIO_AD_00_LPUART7_TX { + pinmux = <0x400e810c 6 0x400e8630 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_sim1_trxd: IOMUXC_GPIO_AD_00_SIM1_TRXD { + pinmux = <0x400e810c 0 0x400e869c 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_acmp1_in2: IOMUXC_GPIO_AD_01_ACMP1_IN2 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_can2_rx: IOMUXC_GPIO_AD_01_CAN2_RX { + pinmux = <0x400e8110 1 0x400e849c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_enet_1g_1588_event1_out: IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT { + pinmux = <0x400e8110 2 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexio2_flexio01: IOMUXC_GPIO_AD_01_FLEXIO2_FLEXIO01 { + pinmux = <0x400e8110 8 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexpwm1_pwm0_b: IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B { + pinmux = <0x400e8110 4 0x400e850c 1 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexspi2_a_ss1_b: IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B { + pinmux = <0x400e8110 9 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio9_io00: IOMUXC_GPIO_AD_01_GPIO9_IO00 { + pinmux = <0x400e8110 10 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00_cm7: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00_CM7 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpt2_capture2: IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 { + pinmux = <0x400e8110 3 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_lpuart7_rx: IOMUXC_GPIO_AD_01_LPUART7_RX { + pinmux = <0x400e8110 6 0x400e862c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_sim1_clk: IOMUXC_GPIO_AD_01_SIM1_CLK { + pinmux = <0x400e8110 0 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_acmp1_in3: IOMUXC_GPIO_AD_02_ACMP1_IN3 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_enet_1g_1588_event2_in: IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN { + pinmux = <0x400e8114 2 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexio2_flexio02: IOMUXC_GPIO_AD_02_FLEXIO2_FLEXIO02 { + pinmux = <0x400e8114 8 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexpwm1_pwm1_a: IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A { + pinmux = <0x400e8114 4 0x400e8504 1 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio9_io01: IOMUXC_GPIO_AD_02_GPIO9_IO01 { + pinmux = <0x400e8114 10 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01_cm7: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01_CM7 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpt2_compare1: IOMUXC_GPIO_AD_02_GPT2_COMPARE1 { + pinmux = <0x400e8114 3 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart7_cts_b: IOMUXC_GPIO_AD_02_LPUART7_CTS_B { + pinmux = <0x400e8114 1 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart8_tx: IOMUXC_GPIO_AD_02_LPUART8_TX { + pinmux = <0x400e8114 6 0x400e8638 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_sim1_rst_b: IOMUXC_GPIO_AD_02_SIM1_RST_B { + pinmux = <0x400e8114 0 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_video_mux_ext_dcic1: IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e8114 9 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_acmp1_in4: IOMUXC_GPIO_AD_03_ACMP1_IN4 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_enet_1g_1588_event2_out: IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT { + pinmux = <0x400e8118 2 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexio2_flexio03: IOMUXC_GPIO_AD_03_FLEXIO2_FLEXIO03 { + pinmux = <0x400e8118 8 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexpwm1_pwm1_b: IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B { + pinmux = <0x400e8118 4 0x400e8510 1 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio9_io02: IOMUXC_GPIO_AD_03_GPIO9_IO02 { + pinmux = <0x400e8118 10 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02_cm7: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02_CM7 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpt2_compare2: IOMUXC_GPIO_AD_03_GPT2_COMPARE2 { + pinmux = <0x400e8118 3 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart7_rts_b: IOMUXC_GPIO_AD_03_LPUART7_RTS_B { + pinmux = <0x400e8118 1 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart8_rx: IOMUXC_GPIO_AD_03_LPUART8_RX { + pinmux = <0x400e8118 6 0x400e8634 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_sim1_sven: IOMUXC_GPIO_AD_03_SIM1_SVEN { + pinmux = <0x400e8118 0 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_video_mux_ext_dcic2: IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8118 9 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_acmp2_in1: IOMUXC_GPIO_AD_04_ACMP2_IN1 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_enet_1g_1588_event3_in: IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN { + pinmux = <0x400e811c 2 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexio2_flexio04: IOMUXC_GPIO_AD_04_FLEXIO2_FLEXIO04 { + pinmux = <0x400e811c 8 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexpwm1_pwm2_a: IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A { + pinmux = <0x400e811c 4 0x400e8508 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio9_io03: IOMUXC_GPIO_AD_04_GPIO9_IO03 { + pinmux = <0x400e811c 10 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03_cm7: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03_CM7 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpt2_compare3: IOMUXC_GPIO_AD_04_GPT2_COMPARE3 { + pinmux = <0x400e811c 3 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_lpuart8_cts_b: IOMUXC_GPIO_AD_04_LPUART8_CTS_B { + pinmux = <0x400e811c 1 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_qtimer4_timer0: IOMUXC_GPIO_AD_04_QTIMER4_TIMER0 { + pinmux = <0x400e811c 9 0x400e8660 1 0x400e8360>; + pin-pue; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_sim1_pd: IOMUXC_GPIO_AD_04_SIM1_PD { + pinmux = <0x400e811c 0 0x400e86a0 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_wdog1_wdog_b: IOMUXC_GPIO_AD_04_WDOG1_WDOG_B { + pinmux = <0x400e811c 6 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_acmp2_in2: IOMUXC_GPIO_AD_05_ACMP2_IN2 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_enet_1g_1588_event3_out: IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT { + pinmux = <0x400e8120 2 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexio2_flexio05: IOMUXC_GPIO_AD_05_FLEXIO2_FLEXIO05 { + pinmux = <0x400e8120 8 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexpwm1_pwm2_b: IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B { + pinmux = <0x400e8120 4 0x400e8514 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio9_io04: IOMUXC_GPIO_AD_05_GPIO9_IO04 { + pinmux = <0x400e8120 10 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04_cm7: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04_CM7 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpt2_clk: IOMUXC_GPIO_AD_05_GPT2_CLK { + pinmux = <0x400e8120 3 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_lpuart8_rts_b: IOMUXC_GPIO_AD_05_LPUART8_RTS_B { + pinmux = <0x400e8120 1 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_qtimer4_timer1: IOMUXC_GPIO_AD_05_QTIMER4_TIMER1 { + pinmux = <0x400e8120 9 0x400e8664 1 0x400e8364>; + pin-pue; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_sim1_power_fail: IOMUXC_GPIO_AD_05_SIM1_POWER_FAIL { + pinmux = <0x400e8120 0 0x400e86a4 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_wdog2_wdog_b: IOMUXC_GPIO_AD_05_WDOG2_WDOG_B { + pinmux = <0x400e8120 6 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_adc1_ch0a: IOMUXC_GPIO_AD_06_ADC1_CH0A { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_can1_tx: IOMUXC_GPIO_AD_06_CAN1_TX { + pinmux = <0x400e8124 1 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_enet_1588_event1_in: IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN { + pinmux = <0x400e8124 6 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexio2_flexio06: IOMUXC_GPIO_AD_06_FLEXIO2_FLEXIO06 { + pinmux = <0x400e8124 8 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexpwm1_pwm0_x: IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X { + pinmux = <0x400e8124 11 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio9_io05: IOMUXC_GPIO_AD_06_GPIO9_IO05 { + pinmux = <0x400e8124 10 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05_cm7: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05_CM7 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpt3_capture1: IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 { + pinmux = <0x400e8124 3 0x400e8590 1 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_qtimer4_timer2: IOMUXC_GPIO_AD_06_QTIMER4_TIMER2 { + pinmux = <0x400e8124 9 0x400e8668 0 0x400e8368>; + pin-pue; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_sim2_trxd: IOMUXC_GPIO_AD_06_SIM2_TRXD { + pinmux = <0x400e8124 2 0x400e86a8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_usb_otg2_oc: IOMUXC_GPIO_AD_06_USB_OTG2_OC { + pinmux = <0x400e8124 0 0x400e86b8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_video_mux_csi_data15: IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 { + pinmux = <0x400e8124 4 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_adc1_ch0b: IOMUXC_GPIO_AD_07_ADC1_CH0B { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_can1_rx: IOMUXC_GPIO_AD_07_CAN1_RX { + pinmux = <0x400e8128 1 0x400e8498 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_enet_1588_event1_out: IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT { + pinmux = <0x400e8128 6 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexio2_flexio07: IOMUXC_GPIO_AD_07_FLEXIO2_FLEXIO07 { + pinmux = <0x400e8128 8 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexpwm1_pwm1_x: IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X { + pinmux = <0x400e8128 11 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio9_io06: IOMUXC_GPIO_AD_07_GPIO9_IO06 { + pinmux = <0x400e8128 10 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06_cm7: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06_CM7 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpt3_capture2: IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 { + pinmux = <0x400e8128 3 0x400e8594 1 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_qtimer4_timer3: IOMUXC_GPIO_AD_07_QTIMER4_TIMER3 { + pinmux = <0x400e8128 9 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e403c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_sim2_clk: IOMUXC_GPIO_AD_07_SIM2_CLK { + pinmux = <0x400e8128 2 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_usb_otg2_pwr: IOMUXC_GPIO_AD_07_USB_OTG2_PWR { + pinmux = <0x400e8128 0 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_video_mux_csi_data14: IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 { + pinmux = <0x400e8128 4 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_adc1_ch1a: IOMUXC_GPIO_AD_08_ADC1_CH1A { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_enet_1588_event2_in: IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN { + pinmux = <0x400e812c 6 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexio2_flexio08: IOMUXC_GPIO_AD_08_FLEXIO2_FLEXIO08 { + pinmux = <0x400e812c 8 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexpwm1_pwm2_x: IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X { + pinmux = <0x400e812c 11 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio9_io07: IOMUXC_GPIO_AD_08_GPIO9_IO07 { + pinmux = <0x400e812c 10 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07_cm7: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07_CM7 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpt3_compare1: IOMUXC_GPIO_AD_08_GPT3_COMPARE1 { + pinmux = <0x400e812c 3 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_lpi2c1_scl: IOMUXC_GPIO_AD_08_LPI2C1_SCL { + pinmux = <0x400e812c 1 0x400e85ac 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_sim2_rst_b: IOMUXC_GPIO_AD_08_SIM2_RST_B { + pinmux = <0x400e812c 2 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_usbphy2_otg_id: IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID { + pinmux = <0x400e812c 0 0x400e86c4 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_video_mux_csi_data13: IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 { + pinmux = <0x400e812c 4 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_adc1_ch1b: IOMUXC_GPIO_AD_09_ADC1_CH1B { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_enet_1588_event2_out: IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT { + pinmux = <0x400e8130 6 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexio2_flexio09: IOMUXC_GPIO_AD_09_FLEXIO2_FLEXIO09 { + pinmux = <0x400e8130 8 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexpwm1_pwm3_x: IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X { + pinmux = <0x400e8130 11 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio9_io08: IOMUXC_GPIO_AD_09_GPIO9_IO08 { + pinmux = <0x400e8130 10 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08_cm7: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08_CM7 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpt3_compare2: IOMUXC_GPIO_AD_09_GPT3_COMPARE2 { + pinmux = <0x400e8130 3 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_lpi2c1_sda: IOMUXC_GPIO_AD_09_LPI2C1_SDA { + pinmux = <0x400e8130 1 0x400e85b0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_sim2_sven: IOMUXC_GPIO_AD_09_SIM2_SVEN { + pinmux = <0x400e8130 2 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_usbphy1_otg_id: IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID { + pinmux = <0x400e8130 0 0x400e86c0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_video_mux_csi_data12: IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 { + pinmux = <0x400e8130 4 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_adc1_ch2a: IOMUXC_GPIO_AD_10_ADC1_CH2A { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_enet_1588_event3_in: IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN { + pinmux = <0x400e8134 6 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexio2_flexio10: IOMUXC_GPIO_AD_10_FLEXIO2_FLEXIO10 { + pinmux = <0x400e8134 8 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexpwm2_pwm0_x: IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X { + pinmux = <0x400e8134 11 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio9_io09: IOMUXC_GPIO_AD_10_GPIO9_IO09 { + pinmux = <0x400e8134 10 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09_cm7: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09_CM7 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpt3_compare3: IOMUXC_GPIO_AD_10_GPT3_COMPARE3 { + pinmux = <0x400e8134 3 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_lpi2c1_scls: IOMUXC_GPIO_AD_10_LPI2C1_SCLS { + pinmux = <0x400e8134 1 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_sim2_pd: IOMUXC_GPIO_AD_10_SIM2_PD { + pinmux = <0x400e8134 2 0x400e86ac 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_usb_otg1_pwr: IOMUXC_GPIO_AD_10_USB_OTG1_PWR { + pinmux = <0x400e8134 0 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_video_mux_csi_data11: IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 { + pinmux = <0x400e8134 4 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_adc1_ch2b: IOMUXC_GPIO_AD_11_ADC1_CH2B { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_enet_1588_event3_out: IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT { + pinmux = <0x400e8138 6 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexio2_flexio11: IOMUXC_GPIO_AD_11_FLEXIO2_FLEXIO11 { + pinmux = <0x400e8138 8 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexpwm2_pwm1_x: IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X { + pinmux = <0x400e8138 11 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio9_io10: IOMUXC_GPIO_AD_11_GPIO9_IO10 { + pinmux = <0x400e8138 10 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10_cm7: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10_CM7 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpt3_clk: IOMUXC_GPIO_AD_11_GPT3_CLK { + pinmux = <0x400e8138 3 0x400e8598 1 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_lpi2c1_sdas: IOMUXC_GPIO_AD_11_LPI2C1_SDAS { + pinmux = <0x400e8138 1 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_sim2_power_fail: IOMUXC_GPIO_AD_11_SIM2_POWER_FAIL { + pinmux = <0x400e8138 2 0x400e86b0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_usb_otg1_oc: IOMUXC_GPIO_AD_11_USB_OTG1_OC { + pinmux = <0x400e8138 0 0x400e86bc 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_video_mux_csi_data10: IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 { + pinmux = <0x400e8138 4 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc1_ch3a: IOMUXC_GPIO_AD_12_ADC1_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc2_ch3a: IOMUXC_GPIO_AD_12_ADC2_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_enet_tdata03: IOMUXC_GPIO_AD_12_ENET_TDATA03 { + pinmux = <0x400e813c 6 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_ewm_ewm_out_b: IOMUXC_GPIO_AD_12_EWM_EWM_OUT_B { + pinmux = <0x400e813c 9 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexio2_flexio12: IOMUXC_GPIO_AD_12_FLEXIO2_FLEXIO12 { + pinmux = <0x400e813c 8 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexpwm2_pwm2_x: IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X { + pinmux = <0x400e813c 11 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexspi1_b_data03: IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 { + pinmux = <0x400e813c 3 0x400e8570 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio9_io11: IOMUXC_GPIO_AD_12_GPIO9_IO11 { + pinmux = <0x400e813c 10 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11_cm7: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11_CM7 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpt1_capture1: IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 { + pinmux = <0x400e813c 2 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_lpi2c1_hreq: IOMUXC_GPIO_AD_12_LPI2C1_HREQ { + pinmux = <0x400e813c 1 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_spdif_lock: IOMUXC_GPIO_AD_12_SPDIF_LOCK { + pinmux = <0x400e813c 0 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_video_mux_csi_pixclk: IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK { + pinmux = <0x400e813c 4 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc1_ch3b: IOMUXC_GPIO_AD_13_ADC1_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc2_ch3b: IOMUXC_GPIO_AD_13_ADC2_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_enet_tdata02: IOMUXC_GPIO_AD_13_ENET_TDATA02 { + pinmux = <0x400e8140 6 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexio2_flexio13: IOMUXC_GPIO_AD_13_FLEXIO2_FLEXIO13 { + pinmux = <0x400e8140 8 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexpwm2_pwm3_x: IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X { + pinmux = <0x400e8140 11 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexspi1_b_data02: IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 { + pinmux = <0x400e8140 3 0x400e856c 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio9_io12: IOMUXC_GPIO_AD_13_GPIO9_IO12 { + pinmux = <0x400e8140 10 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12_cm7: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12_CM7 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpt1_capture2: IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 { + pinmux = <0x400e8140 2 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_pit1_trigger00: IOMUXC_GPIO_AD_13_PIT1_TRIGGER00 { + pinmux = <0x400e8140 1 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_spdif_sr_clk: IOMUXC_GPIO_AD_13_SPDIF_SR_CLK { + pinmux = <0x400e8140 0 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_video_mux_csi_mclk: IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK { + pinmux = <0x400e8140 4 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc1_ch4a: IOMUXC_GPIO_AD_14_ADC1_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc2_ch4a: IOMUXC_GPIO_AD_14_ADC2_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_ccm_enet_ref_clk_25m: IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8144 9 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_enet_rx_clk: IOMUXC_GPIO_AD_14_ENET_RX_CLK { + pinmux = <0x400e8144 6 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexio2_flexio14: IOMUXC_GPIO_AD_14_FLEXIO2_FLEXIO14 { + pinmux = <0x400e8144 8 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexpwm3_pwm0_x: IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X { + pinmux = <0x400e8144 11 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexspi1_b_data01: IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 { + pinmux = <0x400e8144 3 0x400e8568 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio9_io13: IOMUXC_GPIO_AD_14_GPIO9_IO13 { + pinmux = <0x400e8144 10 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13_cm7: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13_CM7 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpt1_compare1: IOMUXC_GPIO_AD_14_GPT1_COMPARE1 { + pinmux = <0x400e8144 2 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_spdif_ext_clk: IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK { + pinmux = <0x400e8144 0 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_video_mux_csi_vsync: IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC { + pinmux = <0x400e8144 4 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc1_ch4b: IOMUXC_GPIO_AD_15_ADC1_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc2_ch4b: IOMUXC_GPIO_AD_15_ADC2_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_enet_tx_er: IOMUXC_GPIO_AD_15_ENET_TX_ER { + pinmux = <0x400e8148 6 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexio2_flexio15: IOMUXC_GPIO_AD_15_FLEXIO2_FLEXIO15 { + pinmux = <0x400e8148 8 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexpwm3_pwm1_x: IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X { + pinmux = <0x400e8148 11 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexspi1_b_data00: IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 { + pinmux = <0x400e8148 3 0x400e8564 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio9_io14: IOMUXC_GPIO_AD_15_GPIO9_IO14 { + pinmux = <0x400e8148 10 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14_cm7: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14_CM7 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpt1_compare2: IOMUXC_GPIO_AD_15_GPT1_COMPARE2 { + pinmux = <0x400e8148 2 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_lpuart10_tx: IOMUXC_GPIO_AD_15_LPUART10_TX { + pinmux = <0x400e8148 1 0x400e8628 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_spdif_in: IOMUXC_GPIO_AD_15_SPDIF_IN { + pinmux = <0x400e8148 0 0x400e86b4 1 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_video_mux_csi_hsync: IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC { + pinmux = <0x400e8148 4 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc1_ch5a: IOMUXC_GPIO_AD_16_ADC1_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc2_ch5a: IOMUXC_GPIO_AD_16_ADC2_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_1g_mdc: IOMUXC_GPIO_AD_16_ENET_1G_MDC { + pinmux = <0x400e814c 9 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_rdata03: IOMUXC_GPIO_AD_16_ENET_RDATA03 { + pinmux = <0x400e814c 6 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexio2_flexio16: IOMUXC_GPIO_AD_16_FLEXIO2_FLEXIO16 { + pinmux = <0x400e814c 8 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexpwm3_pwm2_x: IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X { + pinmux = <0x400e814c 11 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexspi1_b_sclk: IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK { + pinmux = <0x400e814c 3 0x400e8578 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio9_io15: IOMUXC_GPIO_AD_16_GPIO9_IO15 { + pinmux = <0x400e814c 10 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15_cm7: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15_CM7 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpt1_compare3: IOMUXC_GPIO_AD_16_GPT1_COMPARE3 { + pinmux = <0x400e814c 2 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_lpuart10_rx: IOMUXC_GPIO_AD_16_LPUART10_RX { + pinmux = <0x400e814c 1 0x400e8624 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_spdif_out: IOMUXC_GPIO_AD_16_SPDIF_OUT { + pinmux = <0x400e814c 0 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_video_mux_csi_data09: IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 { + pinmux = <0x400e814c 4 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_acmp1_cmpo: IOMUXC_GPIO_AD_17_ACMP1_CMPO { + pinmux = <0x400e8150 1 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc1_ch5b: IOMUXC_GPIO_AD_17_ADC1_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc2_ch5b: IOMUXC_GPIO_AD_17_ADC2_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_1g_mdio: IOMUXC_GPIO_AD_17_ENET_1G_MDIO { + pinmux = <0x400e8150 9 0x400e84c8 2 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_rdata02: IOMUXC_GPIO_AD_17_ENET_RDATA02 { + pinmux = <0x400e8150 6 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexio2_flexio17: IOMUXC_GPIO_AD_17_FLEXIO2_FLEXIO17 { + pinmux = <0x400e8150 8 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexpwm3_pwm3_x: IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X { + pinmux = <0x400e8150 11 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexspi1_a_dqs: IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS { + pinmux = <0x400e8150 3 0x400e8550 1 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio9_io16: IOMUXC_GPIO_AD_17_GPIO9_IO16 { + pinmux = <0x400e8150 10 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16_cm7: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16_CM7 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpt1_clk: IOMUXC_GPIO_AD_17_GPT1_CLK { + pinmux = <0x400e8150 2 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_sai1_mclk: IOMUXC_GPIO_AD_17_SAI1_MCLK { + pinmux = <0x400e8150 0 0x400e866c 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_video_mux_csi_data08: IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 { + pinmux = <0x400e8150 4 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_acmp2_cmpo: IOMUXC_GPIO_AD_18_ACMP2_CMPO { + pinmux = <0x400e8154 1 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_adc2_ch0a: IOMUXC_GPIO_AD_18_ADC2_CH0A { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_enet_crs: IOMUXC_GPIO_AD_18_ENET_CRS { + pinmux = <0x400e8154 6 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexio2_flexio18: IOMUXC_GPIO_AD_18_FLEXIO2_FLEXIO18 { + pinmux = <0x400e8154 8 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexpwm4_pwm0_x: IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X { + pinmux = <0x400e8154 11 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexspi1_a_ss0_b: IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B { + pinmux = <0x400e8154 3 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio9_io17: IOMUXC_GPIO_AD_18_GPIO9_IO17 { + pinmux = <0x400e8154 10 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17_cm7: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17_CM7 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpi2c2_scl: IOMUXC_GPIO_AD_18_LPI2C2_SCL { + pinmux = <0x400e8154 9 0x400e85b4 1 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpspi1_pcs1: IOMUXC_GPIO_AD_18_LPSPI1_PCS1 { + pinmux = <0x400e8154 2 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_sai1_rx_sync: IOMUXC_GPIO_AD_18_SAI1_RX_SYNC { + pinmux = <0x400e8154 0 0x400e8678 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_video_mux_csi_data07: IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 { + pinmux = <0x400e8154 4 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_acmp3_cmpo: IOMUXC_GPIO_AD_19_ACMP3_CMPO { + pinmux = <0x400e8158 1 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_adc2_ch0b: IOMUXC_GPIO_AD_19_ADC2_CH0B { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_enet_col: IOMUXC_GPIO_AD_19_ENET_COL { + pinmux = <0x400e8158 6 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexio2_flexio19: IOMUXC_GPIO_AD_19_FLEXIO2_FLEXIO19 { + pinmux = <0x400e8158 8 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexpwm4_pwm1_x: IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X { + pinmux = <0x400e8158 11 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexspi1_a_sclk: IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK { + pinmux = <0x400e8158 3 0x400e8574 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio9_io18: IOMUXC_GPIO_AD_19_GPIO9_IO18 { + pinmux = <0x400e8158 10 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18_cm7: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18_CM7 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpi2c2_sda: IOMUXC_GPIO_AD_19_LPI2C2_SDA { + pinmux = <0x400e8158 9 0x400e85b8 1 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpspi1_pcs2: IOMUXC_GPIO_AD_19_LPSPI1_PCS2 { + pinmux = <0x400e8158 2 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_sai1_rx_bclk: IOMUXC_GPIO_AD_19_SAI1_RX_BCLK { + pinmux = <0x400e8158 0 0x400e8670 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_video_mux_csi_data06: IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 { + pinmux = <0x400e8158 4 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_acmp4_cmpo: IOMUXC_GPIO_AD_20_ACMP4_CMPO { + pinmux = <0x400e815c 1 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_adc2_ch1a: IOMUXC_GPIO_AD_20_ADC2_CH1A { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexio2_flexio20: IOMUXC_GPIO_AD_20_FLEXIO2_FLEXIO20 { + pinmux = <0x400e815c 8 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexpwm4_pwm2_x: IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X { + pinmux = <0x400e815c 11 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexspi1_a_data00: IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 { + pinmux = <0x400e815c 3 0x400e8554 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio9_io19: IOMUXC_GPIO_AD_20_GPIO9_IO19 { + pinmux = <0x400e815c 10 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19_cm7: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19_CM7 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_kpp_row07: IOMUXC_GPIO_AD_20_KPP_ROW07 { + pinmux = <0x400e815c 6 0x400e85a8 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_lpspi1_pcs3: IOMUXC_GPIO_AD_20_LPSPI1_PCS3 { + pinmux = <0x400e815c 2 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_sai1_rx_data00: IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 { + pinmux = <0x400e815c 0 0x400e8674 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_video_mux_csi_data05: IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 { + pinmux = <0x400e815c 4 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_adc2_ch1b: IOMUXC_GPIO_AD_21_ADC2_CH1B { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexio2_flexio21: IOMUXC_GPIO_AD_21_FLEXIO2_FLEXIO21 { + pinmux = <0x400e8160 8 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexpwm4_pwm3_x: IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X { + pinmux = <0x400e8160 11 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexspi1_a_data01: IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 { + pinmux = <0x400e8160 3 0x400e8558 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio9_io20: IOMUXC_GPIO_AD_21_GPIO9_IO20 { + pinmux = <0x400e8160 10 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20_cm7: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20_CM7 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_kpp_col07: IOMUXC_GPIO_AD_21_KPP_COL07 { + pinmux = <0x400e8160 6 0x400e85a0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_lpspi2_pcs1: IOMUXC_GPIO_AD_21_LPSPI2_PCS1 { + pinmux = <0x400e8160 2 0x400e85e0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_sai1_tx_data00: IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 { + pinmux = <0x400e8160 0 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_video_mux_csi_data04: IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 { + pinmux = <0x400e8160 4 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_adc2_ch2a: IOMUXC_GPIO_AD_22_ADC2_CH2A { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexio2_flexio22: IOMUXC_GPIO_AD_22_FLEXIO2_FLEXIO22 { + pinmux = <0x400e8164 8 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexspi1_a_data02: IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 { + pinmux = <0x400e8164 3 0x400e855c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio9_io21: IOMUXC_GPIO_AD_22_GPIO9_IO21 { + pinmux = <0x400e8164 10 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21_cm7: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21_CM7 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_kpp_row06: IOMUXC_GPIO_AD_22_KPP_ROW06 { + pinmux = <0x400e8164 6 0x400e85a4 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_lpspi2_pcs2: IOMUXC_GPIO_AD_22_LPSPI2_PCS2 { + pinmux = <0x400e8164 2 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_sai1_tx_bclk: IOMUXC_GPIO_AD_22_SAI1_TX_BCLK { + pinmux = <0x400e8164 0 0x400e867c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_video_mux_csi_data03: IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 { + pinmux = <0x400e8164 4 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_adc2_ch2b: IOMUXC_GPIO_AD_23_ADC2_CH2B { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexio2_flexio23: IOMUXC_GPIO_AD_23_FLEXIO2_FLEXIO23 { + pinmux = <0x400e8168 8 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexspi1_a_data03: IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 { + pinmux = <0x400e8168 3 0x400e8560 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio9_io22: IOMUXC_GPIO_AD_23_GPIO9_IO22 { + pinmux = <0x400e8168 10 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22_cm7: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22_CM7 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_kpp_col06: IOMUXC_GPIO_AD_23_KPP_COL06 { + pinmux = <0x400e8168 6 0x400e859c 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_lpspi2_pcs3: IOMUXC_GPIO_AD_23_LPSPI2_PCS3 { + pinmux = <0x400e8168 2 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_sai1_tx_sync: IOMUXC_GPIO_AD_23_SAI1_TX_SYNC { + pinmux = <0x400e8168 0 0x400e8680 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_video_mux_csi_data02: IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 { + pinmux = <0x400e8168 4 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_adc2_ch6a: IOMUXC_GPIO_AD_24_ADC2_CH6A { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_enet_rx_en: IOMUXC_GPIO_AD_24_ENET_RX_EN { + pinmux = <0x400e816c 3 0x400e84b8 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexio2_flexio24: IOMUXC_GPIO_AD_24_FLEXIO2_FLEXIO24 { + pinmux = <0x400e816c 8 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexpwm2_pwm0_a: IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A { + pinmux = <0x400e816c 4 0x400e8518 1 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio9_io23: IOMUXC_GPIO_AD_24_GPIO9_IO23 { + pinmux = <0x400e816c 10 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23_cm7: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23_CM7 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_kpp_row05: IOMUXC_GPIO_AD_24_KPP_ROW05 { + pinmux = <0x400e816c 6 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpi2c4_scl: IOMUXC_GPIO_AD_24_LPI2C4_SCL { + pinmux = <0x400e816c 9 0x400e85c4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpspi2_sck: IOMUXC_GPIO_AD_24_LPSPI2_SCK { + pinmux = <0x400e816c 1 0x400e85e4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpuart1_tx: IOMUXC_GPIO_AD_24_LPUART1_TX { + pinmux = <0x400e816c 0 0x400e8620 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_video_mux_csi_data00: IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 { + pinmux = <0x400e816c 2 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_adc2_ch6b: IOMUXC_GPIO_AD_25_ADC2_CH6B { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_enet_rx_er: IOMUXC_GPIO_AD_25_ENET_RX_ER { + pinmux = <0x400e8170 3 0x400e84bc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexio2_flexio25: IOMUXC_GPIO_AD_25_FLEXIO2_FLEXIO25 { + pinmux = <0x400e8170 8 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexpwm2_pwm0_b: IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B { + pinmux = <0x400e8170 4 0x400e8524 1 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio9_io24: IOMUXC_GPIO_AD_25_GPIO9_IO24 { + pinmux = <0x400e8170 10 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24_cm7: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24_CM7 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_kpp_col05: IOMUXC_GPIO_AD_25_KPP_COL05 { + pinmux = <0x400e8170 6 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpi2c4_sda: IOMUXC_GPIO_AD_25_LPI2C4_SDA { + pinmux = <0x400e8170 9 0x400e85c8 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpspi2_pcs0: IOMUXC_GPIO_AD_25_LPSPI2_PCS0 { + pinmux = <0x400e8170 1 0x400e85dc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpuart1_rx: IOMUXC_GPIO_AD_25_LPUART1_RX { + pinmux = <0x400e8170 0 0x400e861c 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_video_mux_csi_data01: IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 { + pinmux = <0x400e8170 2 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_acmp2_in3: IOMUXC_GPIO_AD_26_ACMP2_IN3 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_enet_rdata00: IOMUXC_GPIO_AD_26_ENET_RDATA00 { + pinmux = <0x400e8174 3 0x400e84b0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexio2_flexio26: IOMUXC_GPIO_AD_26_FLEXIO2_FLEXIO26 { + pinmux = <0x400e8174 8 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexpwm2_pwm1_a: IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A { + pinmux = <0x400e8174 4 0x400e851c 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio9_io25: IOMUXC_GPIO_AD_26_GPIO9_IO25 { + pinmux = <0x400e8174 10 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25_cm7: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25_CM7 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_kpp_row04: IOMUXC_GPIO_AD_26_KPP_ROW04 { + pinmux = <0x400e8174 6 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpspi2_sdo: IOMUXC_GPIO_AD_26_LPSPI2_SDO { + pinmux = <0x400e8174 1 0x400e85ec 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpuart1_cts_b: IOMUXC_GPIO_AD_26_LPUART1_CTS_B { + pinmux = <0x400e8174 0 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_semc_csx01: IOMUXC_GPIO_AD_26_SEMC_CSX01 { + pinmux = <0x400e8174 2 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_usdhc2_cd_b: IOMUXC_GPIO_AD_26_USDHC2_CD_B { + pinmux = <0x400e8174 11 0x400e86d0 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_acmp2_in4: IOMUXC_GPIO_AD_27_ACMP2_IN4 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_enet_rdata01: IOMUXC_GPIO_AD_27_ENET_RDATA01 { + pinmux = <0x400e8178 3 0x400e84b4 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexio2_flexio27: IOMUXC_GPIO_AD_27_FLEXIO2_FLEXIO27 { + pinmux = <0x400e8178 8 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexpwm2_pwm1_b: IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B { + pinmux = <0x400e8178 4 0x400e8528 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio9_io26: IOMUXC_GPIO_AD_27_GPIO9_IO26 { + pinmux = <0x400e8178 10 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26_cm7: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26_CM7 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_kpp_col04: IOMUXC_GPIO_AD_27_KPP_COL04 { + pinmux = <0x400e8178 6 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpspi2_sdi: IOMUXC_GPIO_AD_27_LPSPI2_SDI { + pinmux = <0x400e8178 1 0x400e85e8 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpuart1_rts_b: IOMUXC_GPIO_AD_27_LPUART1_RTS_B { + pinmux = <0x400e8178 0 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_semc_csx02: IOMUXC_GPIO_AD_27_SEMC_CSX02 { + pinmux = <0x400e8178 2 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_usdhc2_wp: IOMUXC_GPIO_AD_27_USDHC2_WP { + pinmux = <0x400e8178 11 0x400e86d4 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_acmp3_in1: IOMUXC_GPIO_AD_28_ACMP3_IN1 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_enet_tx_en: IOMUXC_GPIO_AD_28_ENET_TX_EN { + pinmux = <0x400e817c 3 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexio2_flexio28: IOMUXC_GPIO_AD_28_FLEXIO2_FLEXIO28 { + pinmux = <0x400e817c 8 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexpwm2_pwm2_a: IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A { + pinmux = <0x400e817c 4 0x400e8520 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio9_io27: IOMUXC_GPIO_AD_28_GPIO9_IO27 { + pinmux = <0x400e817c 10 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27_cm7: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27_CM7 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_kpp_row03: IOMUXC_GPIO_AD_28_KPP_ROW03 { + pinmux = <0x400e817c 6 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpspi1_sck: IOMUXC_GPIO_AD_28_LPSPI1_SCK { + pinmux = <0x400e817c 0 0x400e85d0 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpuart5_tx: IOMUXC_GPIO_AD_28_LPUART5_TX { + pinmux = <0x400e817c 1 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_semc_csx03: IOMUXC_GPIO_AD_28_SEMC_CSX03 { + pinmux = <0x400e817c 2 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_usdhc2_vselect: IOMUXC_GPIO_AD_28_USDHC2_VSELECT { + pinmux = <0x400e817c 11 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_video_mux_ext_dcic1: IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e817c 9 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_acmp3_in2: IOMUXC_GPIO_AD_29_ACMP3_IN2 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_ref_clk: IOMUXC_GPIO_AD_29_ENET_REF_CLK { + pinmux = <0x400e8180 2 0x400e84a8 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_tx_clk: IOMUXC_GPIO_AD_29_ENET_TX_CLK { + pinmux = <0x400e8180 3 0x400e84c0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexio2_flexio29: IOMUXC_GPIO_AD_29_FLEXIO2_FLEXIO29 { + pinmux = <0x400e8180 8 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexpwm2_pwm2_b: IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B { + pinmux = <0x400e8180 4 0x400e852c 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio9_io28: IOMUXC_GPIO_AD_29_GPIO9_IO28 { + pinmux = <0x400e8180 10 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28_cm7: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28_CM7 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_kpp_col03: IOMUXC_GPIO_AD_29_KPP_COL03 { + pinmux = <0x400e8180 6 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpspi1_pcs0: IOMUXC_GPIO_AD_29_LPSPI1_PCS0 { + pinmux = <0x400e8180 0 0x400e85cc 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpuart5_rx: IOMUXC_GPIO_AD_29_LPUART5_RX { + pinmux = <0x400e8180 1 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_usdhc2_reset_b: IOMUXC_GPIO_AD_29_USDHC2_RESET_B { + pinmux = <0x400e8180 11 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_video_mux_ext_dcic2: IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8180 9 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_acmp3_in3: IOMUXC_GPIO_AD_30_ACMP3_IN3 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_can2_tx: IOMUXC_GPIO_AD_30_CAN2_TX { + pinmux = <0x400e8184 2 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_enet_tdata00: IOMUXC_GPIO_AD_30_ENET_TDATA00 { + pinmux = <0x400e8184 3 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_flexio2_flexio30: IOMUXC_GPIO_AD_30_FLEXIO2_FLEXIO30 { + pinmux = <0x400e8184 8 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio9_io29: IOMUXC_GPIO_AD_30_GPIO9_IO29 { + pinmux = <0x400e8184 10 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29_cm7: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29_CM7 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_kpp_row02: IOMUXC_GPIO_AD_30_KPP_ROW02 { + pinmux = <0x400e8184 6 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpspi1_sdo: IOMUXC_GPIO_AD_30_LPSPI1_SDO { + pinmux = <0x400e8184 0 0x400e85d8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpuart3_tx: IOMUXC_GPIO_AD_30_LPUART3_TX { + pinmux = <0x400e8184 4 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_usb_otg2_oc: IOMUXC_GPIO_AD_30_USB_OTG2_OC { + pinmux = <0x400e8184 1 0x400e86b8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_AD_30_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e8184 9 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_acmp3_in4: IOMUXC_GPIO_AD_31_ACMP3_IN4 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_can2_rx: IOMUXC_GPIO_AD_31_CAN2_RX { + pinmux = <0x400e8188 2 0x400e849c 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_enet_tdata01: IOMUXC_GPIO_AD_31_ENET_TDATA01 { + pinmux = <0x400e8188 3 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_flexio2_flexio31: IOMUXC_GPIO_AD_31_FLEXIO2_FLEXIO31 { + pinmux = <0x400e8188 8 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio9_io30: IOMUXC_GPIO_AD_31_GPIO9_IO30 { + pinmux = <0x400e8188 10 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30_cm7: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30_CM7 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_kpp_col02: IOMUXC_GPIO_AD_31_KPP_COL02 { + pinmux = <0x400e8188 6 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpspi1_sdi: IOMUXC_GPIO_AD_31_LPSPI1_SDI { + pinmux = <0x400e8188 0 0x400e85d4 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpuart3_rx: IOMUXC_GPIO_AD_31_LPUART3_RX { + pinmux = <0x400e8188 4 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_usb_otg2_pwr: IOMUXC_GPIO_AD_31_USB_OTG2_PWR { + pinmux = <0x400e8188 1 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_AD_31_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8188 9 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_acmp4_in1: IOMUXC_GPIO_AD_32_ACMP4_IN1 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_1g_mdc: IOMUXC_GPIO_AD_32_ENET_1G_MDC { + pinmux = <0x400e818c 9 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_mdc: IOMUXC_GPIO_AD_32_ENET_MDC { + pinmux = <0x400e818c 3 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio9_io31: IOMUXC_GPIO_AD_32_GPIO9_IO31 { + pinmux = <0x400e818c 10 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31_cm7: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31_CM7 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_kpp_row01: IOMUXC_GPIO_AD_32_KPP_ROW01 { + pinmux = <0x400e818c 6 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpi2c1_scl: IOMUXC_GPIO_AD_32_LPI2C1_SCL { + pinmux = <0x400e818c 0 0x400e85ac 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpuart10_tx: IOMUXC_GPIO_AD_32_LPUART10_TX { + pinmux = <0x400e818c 8 0x400e8628 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_pgmc_pmic_ready: IOMUXC_GPIO_AD_32_PGMC_PMIC_READY { + pinmux = <0x400e818c 2 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usbphy2_otg_id: IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID { + pinmux = <0x400e818c 1 0x400e86c4 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usdhc1_cd_b: IOMUXC_GPIO_AD_32_USDHC1_CD_B { + pinmux = <0x400e818c 4 0x400e86c8 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_acmp4_in2: IOMUXC_GPIO_AD_33_ACMP4_IN2 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_1g_mdio: IOMUXC_GPIO_AD_33_ENET_1G_MDIO { + pinmux = <0x400e8190 9 0x400e84c8 3 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_mdio: IOMUXC_GPIO_AD_33_ENET_MDIO { + pinmux = <0x400e8190 3 0x400e84ac 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio10_io00: IOMUXC_GPIO_AD_33_GPIO10_IO00 { + pinmux = <0x400e8190 10 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio_mux4_io00: IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_kpp_col01: IOMUXC_GPIO_AD_33_KPP_COL01 { + pinmux = <0x400e8190 6 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpi2c1_sda: IOMUXC_GPIO_AD_33_LPI2C1_SDA { + pinmux = <0x400e8190 0 0x400e85b0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpuart10_rx: IOMUXC_GPIO_AD_33_LPUART10_RX { + pinmux = <0x400e8190 8 0x400e8624 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usbphy1_otg_id: IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID { + pinmux = <0x400e8190 1 0x400e86c0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usdhc1_wp: IOMUXC_GPIO_AD_33_USDHC1_WP { + pinmux = <0x400e8190 4 0x400e86cc 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_in17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_IN17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_inout17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_acmp4_in3: IOMUXC_GPIO_AD_34_ACMP4_IN3 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN { + pinmux = <0x400e8194 3 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1g_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN { + pinmux = <0x400e8194 0 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio10_io01: IOMUXC_GPIO_AD_34_GPIO10_IO01 { + pinmux = <0x400e8194 10 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio_mux4_io01: IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_kpp_row00: IOMUXC_GPIO_AD_34_KPP_ROW00 { + pinmux = <0x400e8194 6 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_lpuart10_cts_b: IOMUXC_GPIO_AD_34_LPUART10_CTS_B { + pinmux = <0x400e8194 8 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usb_otg1_pwr: IOMUXC_GPIO_AD_34_USB_OTG1_PWR { + pinmux = <0x400e8194 1 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usdhc1_vselect: IOMUXC_GPIO_AD_34_USDHC1_VSELECT { + pinmux = <0x400e8194 4 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_wdog1_wdog_any: IOMUXC_GPIO_AD_34_WDOG1_WDOG_ANY { + pinmux = <0x400e8194 9 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_in18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_IN18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_inout18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_acmp4_in4: IOMUXC_GPIO_AD_35_ACMP4_IN4 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT { + pinmux = <0x400e8198 3 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1g_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT { + pinmux = <0x400e8198 0 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_flexspi1_b_ss1_b: IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B { + pinmux = <0x400e8198 9 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio10_io02: IOMUXC_GPIO_AD_35_GPIO10_IO02 { + pinmux = <0x400e8198 10 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio_mux4_io02: IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_kpp_col00: IOMUXC_GPIO_AD_35_KPP_COL00 { + pinmux = <0x400e8198 6 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_lpuart10_rts_b: IOMUXC_GPIO_AD_35_LPUART10_RTS_B { + pinmux = <0x400e8198 8 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usb_otg1_oc: IOMUXC_GPIO_AD_35_USB_OTG1_OC { + pinmux = <0x400e8198 1 0x400e86bc 1 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usdhc1_reset_b: IOMUXC_GPIO_AD_35_USDHC1_RESET_B { + pinmux = <0x400e8198 4 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_in19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_IN19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_inout19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_INOUT19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_enet_1g_rx_en: IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN { + pinmux = <0x400e81e4 1 0x400e84e0 2 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio10_io21: IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 { + pinmux = <0x400e81e4 10 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio_mux4_io21: IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 { + pinmux = <0x400e81e4 5 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_qtimer1_timer0: IOMUXC_GPIO_DISP_B1_00_QTIMER1_TIMER0 { + pinmux = <0x400e81e4 3 0x400e863c 2 0x400e8428>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_video_mux_lcdif_clk: IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK { + pinmux = <0x400e81e4 0 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_in26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_IN26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_inout26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_clk: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK { + pinmux = <0x400e81e8 1 0x400e84cc 2 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_er: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER { + pinmux = <0x400e81e8 2 0x400e84e4 1 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio10_io22: IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 { + pinmux = <0x400e81e8 10 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio_mux4_io22: IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 { + pinmux = <0x400e81e8 5 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_qtimer1_timer1: IOMUXC_GPIO_DISP_B1_01_QTIMER1_TIMER1 { + pinmux = <0x400e81e8 3 0x400e8640 2 0x400e842c>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_video_mux_lcdif_enable: IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE { + pinmux = <0x400e81e8 0 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_in27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_IN27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_inout27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_enet_1g_rdata00: IOMUXC_GPIO_DISP_B1_02_ENET_1G_RDATA00 { + pinmux = <0x400e81ec 1 0x400e84d0 2 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio10_io23: IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 { + pinmux = <0x400e81ec 10 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio_mux4_io23: IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 { + pinmux = <0x400e81ec 5 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpi2c3_scl: IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL { + pinmux = <0x400e81ec 2 0x400e85bc 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpuart1_tx: IOMUXC_GPIO_DISP_B1_02_LPUART1_TX { + pinmux = <0x400e81ec 9 0x400e8620 1 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_qtimer1_timer2: IOMUXC_GPIO_DISP_B1_02_QTIMER1_TIMER2 { + pinmux = <0x400e81ec 3 0x400e8644 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_video_mux_lcdif_hsync: IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC { + pinmux = <0x400e81ec 0 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_in28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_IN28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_inout28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_enet_1g_rdata01: IOMUXC_GPIO_DISP_B1_03_ENET_1G_RDATA01 { + pinmux = <0x400e81f0 1 0x400e84d4 2 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio10_io24: IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 { + pinmux = <0x400e81f0 10 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio_mux4_io24: IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 { + pinmux = <0x400e81f0 5 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpi2c3_sda: IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA { + pinmux = <0x400e81f0 2 0x400e85c0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpuart1_rx: IOMUXC_GPIO_DISP_B1_03_LPUART1_RX { + pinmux = <0x400e81f0 9 0x400e861c 1 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_qtimer2_timer0: IOMUXC_GPIO_DISP_B1_03_QTIMER2_TIMER0 { + pinmux = <0x400e81f0 3 0x400e8648 2 0x400e8434>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_video_mux_lcdif_vsync: IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC { + pinmux = <0x400e81f0 0 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_in29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_IN29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_inout29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_enet_1g_rdata02: IOMUXC_GPIO_DISP_B1_04_ENET_1G_RDATA02 { + pinmux = <0x400e81f4 1 0x400e84d8 2 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio10_io25: IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 { + pinmux = <0x400e81f4 10 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio_mux4_io25: IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 { + pinmux = <0x400e81f4 5 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpspi3_sck: IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK { + pinmux = <0x400e81f4 9 0x400e8600 1 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpuart4_rx: IOMUXC_GPIO_DISP_B1_04_LPUART4_RX { + pinmux = <0x400e81f4 2 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_qtimer2_timer1: IOMUXC_GPIO_DISP_B1_04_QTIMER2_TIMER1 { + pinmux = <0x400e81f4 3 0x400e864c 2 0x400e8438>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_video_mux_lcdif_data00: IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 { + pinmux = <0x400e81f4 0 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_in30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_IN30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_inout30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_enet_1g_rdata03: IOMUXC_GPIO_DISP_B1_05_ENET_1G_RDATA03 { + pinmux = <0x400e81f8 1 0x400e84dc 2 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio10_io26: IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 { + pinmux = <0x400e81f8 10 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio_mux4_io26: IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 { + pinmux = <0x400e81f8 5 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpspi3_sdi: IOMUXC_GPIO_DISP_B1_05_LPSPI3_SDI { + pinmux = <0x400e81f8 9 0x400e8604 1 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpuart4_cts_b: IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B { + pinmux = <0x400e81f8 2 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_qtimer2_timer2: IOMUXC_GPIO_DISP_B1_05_QTIMER2_TIMER2 { + pinmux = <0x400e81f8 3 0x400e8650 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_video_mux_lcdif_data01: IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 { + pinmux = <0x400e81f8 0 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_in31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_IN31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_inout31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_enet_1g_tdata03: IOMUXC_GPIO_DISP_B1_06_ENET_1G_TDATA03 { + pinmux = <0x400e81fc 1 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio10_io27: IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 { + pinmux = <0x400e81fc 10 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio_mux4_io27: IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 { + pinmux = <0x400e81fc 5 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpspi3_sdo: IOMUXC_GPIO_DISP_B1_06_LPSPI3_SDO { + pinmux = <0x400e81fc 9 0x400e8608 1 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpuart4_tx: IOMUXC_GPIO_DISP_B1_06_LPUART4_TX { + pinmux = <0x400e81fc 2 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_qtimer3_timer0: IOMUXC_GPIO_DISP_B1_06_QTIMER3_TIMER0 { + pinmux = <0x400e81fc 3 0x400e8654 2 0x400e8440>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_src_bt_cfg00: IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 { + pinmux = <0x400e81fc 6 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_video_mux_lcdif_data02: IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 { + pinmux = <0x400e81fc 0 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_in32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_IN32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_inout32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_enet_1g_tdata02: IOMUXC_GPIO_DISP_B1_07_ENET_1G_TDATA02 { + pinmux = <0x400e8200 1 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio10_io28: IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 { + pinmux = <0x400e8200 10 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio_mux4_io28: IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 { + pinmux = <0x400e8200 5 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpspi3_pcs0: IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 { + pinmux = <0x400e8200 9 0x400e85f0 1 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpuart4_rts_b: IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B { + pinmux = <0x400e8200 2 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_qtimer3_timer1: IOMUXC_GPIO_DISP_B1_07_QTIMER3_TIMER1 { + pinmux = <0x400e8200 3 0x400e8658 2 0x400e8444>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_src_bt_cfg01: IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 { + pinmux = <0x400e8200 6 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_video_mux_lcdif_data03: IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 { + pinmux = <0x400e8200 0 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_in33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_IN33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_inout33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_enet_1g_tdata01: IOMUXC_GPIO_DISP_B1_08_ENET_1G_TDATA01 { + pinmux = <0x400e8204 1 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio10_io29: IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 { + pinmux = <0x400e8204 10 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio_mux4_io29: IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 { + pinmux = <0x400e8204 5 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_lpspi3_pcs1: IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 { + pinmux = <0x400e8204 9 0x400e85f4 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_qtimer3_timer2: IOMUXC_GPIO_DISP_B1_08_QTIMER3_TIMER2 { + pinmux = <0x400e8204 3 0x400e865c 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_src_bt_cfg02: IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 { + pinmux = <0x400e8204 6 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_usdhc1_cd_b: IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B { + pinmux = <0x400e8204 2 0x400e86c8 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_video_mux_lcdif_data04: IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 { + pinmux = <0x400e8204 0 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_in34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_IN34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_inout34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_enet_1g_tdata00: IOMUXC_GPIO_DISP_B1_09_ENET_1G_TDATA00 { + pinmux = <0x400e8208 1 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio10_io30: IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 { + pinmux = <0x400e8208 10 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio_mux4_io30: IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 { + pinmux = <0x400e8208 5 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_lpspi3_pcs2: IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 { + pinmux = <0x400e8208 9 0x400e85f8 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_qtimer4_timer0: IOMUXC_GPIO_DISP_B1_09_QTIMER4_TIMER0 { + pinmux = <0x400e8208 3 0x400e8660 2 0x400e844c>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_src_bt_cfg03: IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 { + pinmux = <0x400e8208 6 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_usdhc1_wp: IOMUXC_GPIO_DISP_B1_09_USDHC1_WP { + pinmux = <0x400e8208 2 0x400e86cc 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_video_mux_lcdif_data05: IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 { + pinmux = <0x400e8208 0 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_in35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_IN35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_inout35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_enet_1g_tx_en: IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN { + pinmux = <0x400e820c 1 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio10_io31: IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 { + pinmux = <0x400e820c 10 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio_mux4_io31: IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 { + pinmux = <0x400e820c 5 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_lpspi3_pcs3: IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 { + pinmux = <0x400e820c 9 0x400e85fc 1 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_qtimer4_timer1: IOMUXC_GPIO_DISP_B1_10_QTIMER4_TIMER1 { + pinmux = <0x400e820c 3 0x400e8664 2 0x400e8450>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_src_bt_cfg04: IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 { + pinmux = <0x400e820c 6 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_usdhc1_reset_b: IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B { + pinmux = <0x400e820c 2 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_video_mux_lcdif_data06: IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 { + pinmux = <0x400e820c 0 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_in36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_IN36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_inout36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_INOUT36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e8210 2 0x400e84c4 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_tx_clk_io: IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e8210 1 0x400e84e8 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio11_io00: IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 { + pinmux = <0x400e8210 10 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio_mux5_io00: IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 { + pinmux = <0x400e8210 5 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_qtimer4_timer2: IOMUXC_GPIO_DISP_B1_11_QTIMER4_TIMER2 { + pinmux = <0x400e8210 3 0x400e8668 1 0x400e8454>; + pin-pdrv; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_src_bt_cfg05: IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 { + pinmux = <0x400e8210 6 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_video_mux_lcdif_data07: IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 { + pinmux = <0x400e8210 0 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_in37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_IN37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_inout37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_INOUT37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_enet_1g_tx_er: IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER { + pinmux = <0x400e8214 3 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio11_io01: IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 { + pinmux = <0x400e8214 10 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio_mux5_io01: IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 { + pinmux = <0x400e8214 5 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_mqs_right: IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT { + pinmux = <0x400e8214 2 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_rx_data01: IOMUXC_GPIO_DISP_B2_00_SAI1_RX_DATA01 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_tx_data03: IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_src_bt_cfg06: IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 { + pinmux = <0x400e8214 6 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_video_mux_lcdif_data08: IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 { + pinmux = <0x400e8214 0 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_00_WDOG1_WDOG_B { + pinmux = <0x400e8214 1 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ccm_enet_ref_clk_25m: IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8218 9 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ewm_ewm_out_b: IOMUXC_GPIO_DISP_B2_01_EWM_EWM_OUT_B { + pinmux = <0x400e8218 8 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio11_io02: IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 { + pinmux = <0x400e8218 10 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio_mux5_io02: IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 { + pinmux = <0x400e8218 5 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_mqs_left: IOMUXC_GPIO_DISP_B2_01_MQS_LEFT { + pinmux = <0x400e8218 2 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_rx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_RX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_tx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_src_bt_cfg07: IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 { + pinmux = <0x400e8218 6 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_usdhc1_vselect: IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT { + pinmux = <0x400e8218 1 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_video_mux_lcdif_data09: IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 { + pinmux = <0x400e8218 0 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_01_WDOG2_WDOG_B { + pinmux = <0x400e8218 3 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_arm_trace00: IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 { + pinmux = <0x400e821c 3 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_enet_tdata00: IOMUXC_GPIO_DISP_B2_02_ENET_TDATA00 { + pinmux = <0x400e821c 1 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio11_io03: IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 { + pinmux = <0x400e821c 10 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio_mux5_io03: IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 { + pinmux = <0x400e821c 5 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_pit1_trigger03: IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER03 { + pinmux = <0x400e821c 2 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_rx_data03: IOMUXC_GPIO_DISP_B2_02_SAI1_RX_DATA03 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_tx_data01: IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_src_bt_cfg08: IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 { + pinmux = <0x400e821c 6 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_video_mux_lcdif_data10: IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 { + pinmux = <0x400e821c 0 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_arm_trace01: IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 { + pinmux = <0x400e8220 3 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_enet_tdata01: IOMUXC_GPIO_DISP_B2_03_ENET_TDATA01 { + pinmux = <0x400e8220 1 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio11_io04: IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 { + pinmux = <0x400e8220 10 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio_mux5_io04: IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 { + pinmux = <0x400e8220 5 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_pit1_trigger02: IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER02 { + pinmux = <0x400e8220 2 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_sai1_mclk: IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK { + pinmux = <0x400e8220 4 0x400e866c 1 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_src_bt_cfg09: IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 { + pinmux = <0x400e8220 6 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_video_mux_lcdif_data11: IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 { + pinmux = <0x400e8220 0 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_arm_trace02: IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 { + pinmux = <0x400e8224 3 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_enet_tx_en: IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN { + pinmux = <0x400e8224 1 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio11_io05: IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 { + pinmux = <0x400e8224 10 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio_mux5_io05: IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 { + pinmux = <0x400e8224 5 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_pit1_trigger01: IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER01 { + pinmux = <0x400e8224 2 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_sai1_rx_sync: IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC { + pinmux = <0x400e8224 4 0x400e8678 1 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_src_bt_cfg10: IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 { + pinmux = <0x400e8224 6 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_video_mux_lcdif_data12: IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 { + pinmux = <0x400e8224 0 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_arm_trace03: IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 { + pinmux = <0x400e8228 3 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_ref_clk: IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK { + pinmux = <0x400e8228 2 0x400e84a8 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_tx_clk: IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK { + pinmux = <0x400e8228 1 0x400e84c0 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio11_io06: IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 { + pinmux = <0x400e8228 10 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio_mux5_io06: IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 { + pinmux = <0x400e8228 5 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_sai1_rx_bclk: IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK { + pinmux = <0x400e8228 4 0x400e8670 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_src_bt_cfg11: IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 { + pinmux = <0x400e8228 6 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_video_mux_lcdif_data13: IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 { + pinmux = <0x400e8228 0 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_arm_trace_clk: IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK { + pinmux = <0x400e822c 3 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_enet_rdata00: IOMUXC_GPIO_DISP_B2_06_ENET_RDATA00 { + pinmux = <0x400e822c 1 0x400e84b0 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio11_io07: IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 { + pinmux = <0x400e822c 10 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio_mux5_io07: IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 { + pinmux = <0x400e822c 5 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_lpuart7_tx: IOMUXC_GPIO_DISP_B2_06_LPUART7_TX { + pinmux = <0x400e822c 2 0x400e8630 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_sai1_rx_data00: IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 { + pinmux = <0x400e822c 4 0x400e8674 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_video_mux_lcdif_data14: IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 { + pinmux = <0x400e822c 0 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_arm_trace_swo: IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO { + pinmux = <0x400e8230 3 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_enet_rdata01: IOMUXC_GPIO_DISP_B2_07_ENET_RDATA01 { + pinmux = <0x400e8230 1 0x400e84b4 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio11_io08: IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 { + pinmux = <0x400e8230 10 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio_mux5_io08: IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 { + pinmux = <0x400e8230 5 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_lpuart7_rx: IOMUXC_GPIO_DISP_B2_07_LPUART7_RX { + pinmux = <0x400e8230 2 0x400e862c 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_sai1_tx_data00: IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 { + pinmux = <0x400e8230 4 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_video_mux_lcdif_data15: IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 { + pinmux = <0x400e8230 0 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_cm7_imxrt_txev: IOMUXC_GPIO_DISP_B2_08_CM7_IMXRT_TXEV { + pinmux = <0x400e8234 3 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_enet_rx_en: IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN { + pinmux = <0x400e8234 1 0x400e84b8 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio11_io09: IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 { + pinmux = <0x400e8234 10 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio_mux5_io09: IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 { + pinmux = <0x400e8234 5 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart1_tx: IOMUXC_GPIO_DISP_B2_08_LPUART1_TX { + pinmux = <0x400e8234 9 0x400e8620 2 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart8_tx: IOMUXC_GPIO_DISP_B2_08_LPUART8_TX { + pinmux = <0x400e8234 2 0x400e8638 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_sai1_tx_bclk: IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK { + pinmux = <0x400e8234 4 0x400e867c 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_video_mux_lcdif_data16: IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 { + pinmux = <0x400e8234 0 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_cm7_imxrt_rxev: IOMUXC_GPIO_DISP_B2_09_CM7_IMXRT_RXEV { + pinmux = <0x400e8238 3 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_enet_rx_er: IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER { + pinmux = <0x400e8238 1 0x400e84bc 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio11_io10: IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 { + pinmux = <0x400e8238 10 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio_mux5_io10: IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 { + pinmux = <0x400e8238 5 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart1_rx: IOMUXC_GPIO_DISP_B2_09_LPUART1_RX { + pinmux = <0x400e8238 9 0x400e861c 2 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart8_rx: IOMUXC_GPIO_DISP_B2_09_LPUART8_RX { + pinmux = <0x400e8238 2 0x400e8634 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_sai1_tx_sync: IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC { + pinmux = <0x400e8238 4 0x400e8680 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_video_mux_lcdif_data17: IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 { + pinmux = <0x400e8238 0 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio11_io11: IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 { + pinmux = <0x400e823c 10 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio_mux5_io11: IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 { + pinmux = <0x400e823c 5 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpi2c3_scl: IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL { + pinmux = <0x400e823c 6 0x400e85bc 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpuart2_tx: IOMUXC_GPIO_DISP_B2_10_LPUART2_TX { + pinmux = <0x400e823c 2 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_sim2_trxd: IOMUXC_GPIO_DISP_B2_10_SIM2_TRXD { + pinmux = <0x400e823c 1 0x400e86a8 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_spdif_in: IOMUXC_GPIO_DISP_B2_10_SPDIF_IN { + pinmux = <0x400e823c 9 0x400e86b4 2 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_video_mux_lcdif_data18: IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 { + pinmux = <0x400e823c 0 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_10_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e823c 3 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_in38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_IN38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_inout38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_INOUT38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio11_io12: IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 { + pinmux = <0x400e8240 10 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio_mux5_io12: IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 { + pinmux = <0x400e8240 5 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpi2c3_sda: IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA { + pinmux = <0x400e8240 6 0x400e85c0 1 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpuart2_rx: IOMUXC_GPIO_DISP_B2_11_LPUART2_RX { + pinmux = <0x400e8240 2 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_sim2_clk: IOMUXC_GPIO_DISP_B2_11_SIM2_CLK { + pinmux = <0x400e8240 1 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_spdif_out: IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT { + pinmux = <0x400e8240 9 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_video_mux_lcdif_data19: IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 { + pinmux = <0x400e8240 0 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_11_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8240 3 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_in39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_IN39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_inout39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_INOUT39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_can1_tx: IOMUXC_GPIO_DISP_B2_12_CAN1_TX { + pinmux = <0x400e8244 2 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio11_io13: IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 { + pinmux = <0x400e8244 10 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio_mux5_io13: IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 { + pinmux = <0x400e8244 5 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpi2c4_scl: IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL { + pinmux = <0x400e8244 6 0x400e85c4 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpspi4_sck: IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK { + pinmux = <0x400e8244 9 0x400e8610 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpuart2_cts_b: IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B { + pinmux = <0x400e8244 3 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_sim2_rst_b: IOMUXC_GPIO_DISP_B2_12_SIM2_RST_B { + pinmux = <0x400e8244 1 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_video_mux_lcdif_data20: IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 { + pinmux = <0x400e8244 0 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_in40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_IN40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_inout40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_INOUT40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_can1_rx: IOMUXC_GPIO_DISP_B2_13_CAN1_RX { + pinmux = <0x400e8248 2 0x400e8498 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_enet_ref_clk: IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK { + pinmux = <0x400e8248 4 0x400e84a8 2 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio11_io14: IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 { + pinmux = <0x400e8248 10 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio_mux5_io14: IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 { + pinmux = <0x400e8248 5 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpi2c4_sda: IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA { + pinmux = <0x400e8248 6 0x400e85c8 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpspi4_sdi: IOMUXC_GPIO_DISP_B2_13_LPSPI4_SDI { + pinmux = <0x400e8248 9 0x400e8614 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpuart2_rts_b: IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B { + pinmux = <0x400e8248 3 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_sim2_sven: IOMUXC_GPIO_DISP_B2_13_SIM2_SVEN { + pinmux = <0x400e8248 1 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_video_mux_lcdif_data21: IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 { + pinmux = <0x400e8248 0 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_can1_tx: IOMUXC_GPIO_DISP_B2_14_CAN1_TX { + pinmux = <0x400e824c 6 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK1 { + pinmux = <0x400e824c 4 0x400e84c4 3 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio11_io15: IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 { + pinmux = <0x400e824c 10 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio_mux5_io15: IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 { + pinmux = <0x400e824c 5 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_lpspi4_sdo: IOMUXC_GPIO_DISP_B2_14_LPSPI4_SDO { + pinmux = <0x400e824c 9 0x400e8618 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_sim2_pd: IOMUXC_GPIO_DISP_B2_14_SIM2_PD { + pinmux = <0x400e824c 1 0x400e86ac 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_ext_dcic1: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e824c 3 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_lcdif_data22: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 { + pinmux = <0x400e824c 0 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_14_WDOG2_WDOG_B { + pinmux = <0x400e824c 2 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_can1_rx: IOMUXC_GPIO_DISP_B2_15_CAN1_RX { + pinmux = <0x400e8250 6 0x400e8498 2 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio11_io16: IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 { + pinmux = <0x400e8250 10 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio_mux5_io16: IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 { + pinmux = <0x400e8250 5 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_lpspi4_pcs0: IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 { + pinmux = <0x400e8250 9 0x400e860c 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_pit1_trigger00: IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER00 { + pinmux = <0x400e8250 4 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_sim2_power_fail: IOMUXC_GPIO_DISP_B2_15_SIM2_POWER_FAIL { + pinmux = <0x400e8250 1 0x400e86b0 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_ext_dcic2: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8250 3 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_lcdif_data23: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 { + pinmux = <0x400e8250 0 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_15_WDOG1_WDOG_B { + pinmux = <0x400e8250 2 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexio1_flexio00: IOMUXC_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00 { + pinmux = <0x400e8010 8 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexpwm4_pwm0_a: IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A { + pinmux = <0x400e8010 1 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio7_io00: IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 { + pinmux = <0x400e8010 10 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio_mux1_io00: IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 { + pinmux = <0x400e8010 5 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_semc_data00: IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 { + pinmux = <0x400e8010 0 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexio1_flexio01: IOMUXC_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01 { + pinmux = <0x400e8014 8 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexpwm4_pwm0_b: IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B { + pinmux = <0x400e8014 1 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio7_io01: IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 { + pinmux = <0x400e8014 10 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio_mux1_io01: IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 { + pinmux = <0x400e8014 5 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_semc_data01: IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 { + pinmux = <0x400e8014 0 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexio1_flexio02: IOMUXC_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02 { + pinmux = <0x400e8018 8 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexpwm4_pwm1_a: IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A { + pinmux = <0x400e8018 1 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio7_io02: IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 { + pinmux = <0x400e8018 10 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio_mux1_io02: IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 { + pinmux = <0x400e8018 5 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_semc_data02: IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 { + pinmux = <0x400e8018 0 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexio1_flexio03: IOMUXC_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03 { + pinmux = <0x400e801c 8 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexpwm4_pwm1_b: IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B { + pinmux = <0x400e801c 1 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio7_io03: IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 { + pinmux = <0x400e801c 10 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio_mux1_io03: IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 { + pinmux = <0x400e801c 5 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_semc_data03: IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 { + pinmux = <0x400e801c 0 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexio1_flexio04: IOMUXC_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04 { + pinmux = <0x400e8020 8 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexpwm4_pwm2_a: IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A { + pinmux = <0x400e8020 1 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio7_io04: IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 { + pinmux = <0x400e8020 10 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio_mux1_io04: IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 { + pinmux = <0x400e8020 5 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_semc_data04: IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 { + pinmux = <0x400e8020 0 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexio1_flexio05: IOMUXC_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05 { + pinmux = <0x400e8024 8 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexpwm4_pwm2_b: IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B { + pinmux = <0x400e8024 1 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio7_io05: IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 { + pinmux = <0x400e8024 10 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio_mux1_io05: IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 { + pinmux = <0x400e8024 5 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_semc_data05: IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 { + pinmux = <0x400e8024 0 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexio1_flexio06: IOMUXC_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06 { + pinmux = <0x400e8028 8 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexpwm2_pwm0_a: IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A { + pinmux = <0x400e8028 1 0x400e8518 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio7_io06: IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 { + pinmux = <0x400e8028 10 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio_mux1_io06: IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 { + pinmux = <0x400e8028 5 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_semc_data06: IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 { + pinmux = <0x400e8028 0 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexio1_flexio07: IOMUXC_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07 { + pinmux = <0x400e802c 8 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexpwm2_pwm0_b: IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B { + pinmux = <0x400e802c 1 0x400e8524 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio7_io07: IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 { + pinmux = <0x400e802c 10 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio_mux1_io07: IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 { + pinmux = <0x400e802c 5 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_semc_data07: IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 { + pinmux = <0x400e802c 0 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexio1_flexio08: IOMUXC_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08 { + pinmux = <0x400e8030 8 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexpwm2_pwm1_a: IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A { + pinmux = <0x400e8030 1 0x400e851c 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio7_io08: IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 { + pinmux = <0x400e8030 10 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio_mux1_io08: IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 { + pinmux = <0x400e8030 5 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_semc_dm00: IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 { + pinmux = <0x400e8030 0 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexio1_flexio09: IOMUXC_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09 { + pinmux = <0x400e8034 8 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexpwm2_pwm1_b: IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B { + pinmux = <0x400e8034 1 0x400e8528 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio7_io09: IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 { + pinmux = <0x400e8034 10 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio_mux1_io09: IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 { + pinmux = <0x400e8034 5 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpt5_capture1: IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 { + pinmux = <0x400e8034 2 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_semc_addr00: IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 { + pinmux = <0x400e8034 0 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexio1_flexio10: IOMUXC_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10 { + pinmux = <0x400e8038 8 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexpwm2_pwm2_a: IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A { + pinmux = <0x400e8038 1 0x400e8520 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio7_io10: IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 { + pinmux = <0x400e8038 10 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio_mux1_io10: IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 { + pinmux = <0x400e8038 5 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpt5_capture2: IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 { + pinmux = <0x400e8038 2 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_semc_addr01: IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 { + pinmux = <0x400e8038 0 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexio1_flexio11: IOMUXC_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11 { + pinmux = <0x400e803c 8 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexpwm2_pwm2_b: IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B { + pinmux = <0x400e803c 1 0x400e852c 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio7_io11: IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 { + pinmux = <0x400e803c 10 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio_mux1_io11: IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 { + pinmux = <0x400e803c 5 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpt5_compare1: IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 { + pinmux = <0x400e803c 2 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_semc_addr02: IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 { + pinmux = <0x400e803c 0 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_flexio1_flexio12: IOMUXC_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12 { + pinmux = <0x400e8040 8 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio7_io12: IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 { + pinmux = <0x400e8040 10 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio_mux1_io12: IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 { + pinmux = <0x400e8040 5 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpt5_compare2: IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 { + pinmux = <0x400e8040 2 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_semc_addr03: IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 { + pinmux = <0x400e8040 0 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_in04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_IN04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_INOUT04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_flexio1_flexio13: IOMUXC_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13 { + pinmux = <0x400e8044 8 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio7_io13: IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 { + pinmux = <0x400e8044 10 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio_mux1_io13: IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 { + pinmux = <0x400e8044 5 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpt5_compare3: IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 { + pinmux = <0x400e8044 2 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_semc_addr04: IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 { + pinmux = <0x400e8044 0 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_in05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_IN05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_INOUT05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_flexio1_flexio14: IOMUXC_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14 { + pinmux = <0x400e8048 8 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio7_io14: IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 { + pinmux = <0x400e8048 10 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio_mux1_io14: IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 { + pinmux = <0x400e8048 5 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpt5_clk: IOMUXC_GPIO_EMC_B1_14_GPT5_CLK { + pinmux = <0x400e8048 2 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_semc_addr05: IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 { + pinmux = <0x400e8048 0 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_in06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_IN06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_INOUT06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_flexio1_flexio15: IOMUXC_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15 { + pinmux = <0x400e804c 8 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio7_io15: IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 { + pinmux = <0x400e804c 10 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio_mux1_io15: IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 { + pinmux = <0x400e804c 5 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_semc_addr06: IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 { + pinmux = <0x400e804c 0 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_in07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_IN07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_INOUT07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_flexio1_flexio16: IOMUXC_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16 { + pinmux = <0x400e8050 8 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio7_io16: IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 { + pinmux = <0x400e8050 10 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio_mux1_io16: IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 { + pinmux = <0x400e8050 5 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_semc_addr07: IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 { + pinmux = <0x400e8050 0 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_in08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_IN08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_INOUT08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexio1_flexio17: IOMUXC_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17 { + pinmux = <0x400e8054 8 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexpwm4_pwm3_a: IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A { + pinmux = <0x400e8054 1 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio7_io17: IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 { + pinmux = <0x400e8054 10 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio_mux1_io17: IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 { + pinmux = <0x400e8054 5 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_qtimer1_timer0: IOMUXC_GPIO_EMC_B1_17_QTIMER1_TIMER0 { + pinmux = <0x400e8054 2 0x400e863c 0 0x400e8298>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_semc_addr08: IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 { + pinmux = <0x400e8054 0 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexio1_flexio18: IOMUXC_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18 { + pinmux = <0x400e8058 8 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexpwm4_pwm3_b: IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B { + pinmux = <0x400e8058 1 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio7_io18: IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 { + pinmux = <0x400e8058 10 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio_mux1_io18: IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 { + pinmux = <0x400e8058 5 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_qtimer2_timer0: IOMUXC_GPIO_EMC_B1_18_QTIMER2_TIMER0 { + pinmux = <0x400e8058 2 0x400e8648 0 0x400e829c>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_semc_addr09: IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 { + pinmux = <0x400e8058 0 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexio1_flexio19: IOMUXC_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19 { + pinmux = <0x400e805c 8 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexpwm2_pwm3_a: IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A { + pinmux = <0x400e805c 1 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio7_io19: IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 { + pinmux = <0x400e805c 10 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio_mux1_io19: IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 { + pinmux = <0x400e805c 5 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_qtimer3_timer0: IOMUXC_GPIO_EMC_B1_19_QTIMER3_TIMER0 { + pinmux = <0x400e805c 2 0x400e8654 0 0x400e82a0>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_semc_addr11: IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 { + pinmux = <0x400e805c 0 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexio1_flexio20: IOMUXC_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20 { + pinmux = <0x400e8060 8 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexpwm2_pwm3_b: IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B { + pinmux = <0x400e8060 1 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio7_io20: IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 { + pinmux = <0x400e8060 10 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio_mux1_io20: IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 { + pinmux = <0x400e8060 5 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_qtimer4_timer0: IOMUXC_GPIO_EMC_B1_20_QTIMER4_TIMER0 { + pinmux = <0x400e8060 2 0x400e8660 0 0x400e82a4>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_semc_addr12: IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 { + pinmux = <0x400e8060 0 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexio1_flexio21: IOMUXC_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21 { + pinmux = <0x400e8064 8 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A { + pinmux = <0x400e8064 1 0x400e853c 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio7_io21: IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 { + pinmux = <0x400e8064 10 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio_mux1_io21: IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 { + pinmux = <0x400e8064 5 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_semc_ba0: IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 { + pinmux = <0x400e8064 0 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexio1_flexio22: IOMUXC_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22 { + pinmux = <0x400e8068 8 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B { + pinmux = <0x400e8068 1 0x400e854c 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio7_io22: IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 { + pinmux = <0x400e8068 10 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio_mux1_io22: IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 { + pinmux = <0x400e8068 5 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_semc_ba1: IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 { + pinmux = <0x400e8068 0 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexio1_flexio23: IOMUXC_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23 { + pinmux = <0x400e806c 8 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexpwm1_pwm0_a: IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A { + pinmux = <0x400e806c 1 0x400e8500 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio7_io23: IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 { + pinmux = <0x400e806c 10 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio_mux1_io23: IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 { + pinmux = <0x400e806c 5 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_semc_addr10: IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 { + pinmux = <0x400e806c 0 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexio1_flexio24: IOMUXC_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24 { + pinmux = <0x400e8070 8 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexpwm1_pwm0_b: IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B { + pinmux = <0x400e8070 1 0x400e850c 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio7_io24: IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 { + pinmux = <0x400e8070 10 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio_mux1_io24: IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 { + pinmux = <0x400e8070 5 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_semc_cas: IOMUXC_GPIO_EMC_B1_24_SEMC_CAS { + pinmux = <0x400e8070 0 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexio1_flexio25: IOMUXC_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25 { + pinmux = <0x400e8074 8 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexpwm1_pwm1_a: IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A { + pinmux = <0x400e8074 1 0x400e8504 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio7_io25: IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 { + pinmux = <0x400e8074 10 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio_mux1_io25: IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 { + pinmux = <0x400e8074 5 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_semc_ras: IOMUXC_GPIO_EMC_B1_25_SEMC_RAS { + pinmux = <0x400e8074 0 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexio1_flexio26: IOMUXC_GPIO_EMC_B1_26_FLEXIO1_FLEXIO26 { + pinmux = <0x400e8078 8 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexpwm1_pwm1_b: IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B { + pinmux = <0x400e8078 1 0x400e8510 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio7_io26: IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 { + pinmux = <0x400e8078 10 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio_mux1_io26: IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 { + pinmux = <0x400e8078 5 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_semc_clk: IOMUXC_GPIO_EMC_B1_26_SEMC_CLK { + pinmux = <0x400e8078 0 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexio1_flexio27: IOMUXC_GPIO_EMC_B1_27_FLEXIO1_FLEXIO27 { + pinmux = <0x400e807c 8 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexpwm1_pwm2_a: IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A { + pinmux = <0x400e807c 1 0x400e8508 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio7_io27: IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 { + pinmux = <0x400e807c 10 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio_mux1_io27: IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 { + pinmux = <0x400e807c 5 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_semc_cke: IOMUXC_GPIO_EMC_B1_27_SEMC_CKE { + pinmux = <0x400e807c 0 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexio1_flexio28: IOMUXC_GPIO_EMC_B1_28_FLEXIO1_FLEXIO28 { + pinmux = <0x400e8080 8 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexpwm1_pwm2_b: IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B { + pinmux = <0x400e8080 1 0x400e8514 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio7_io28: IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 { + pinmux = <0x400e8080 10 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio_mux1_io28: IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 { + pinmux = <0x400e8080 5 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_semc_we: IOMUXC_GPIO_EMC_B1_28_SEMC_WE { + pinmux = <0x400e8080 0 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexio1_flexio29: IOMUXC_GPIO_EMC_B1_29_FLEXIO1_FLEXIO29 { + pinmux = <0x400e8084 8 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A { + pinmux = <0x400e8084 1 0x400e8530 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio7_io29: IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 { + pinmux = <0x400e8084 10 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio_mux1_io29: IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 { + pinmux = <0x400e8084 5 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_semc_cs0: IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 { + pinmux = <0x400e8084 0 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexio1_flexio30: IOMUXC_GPIO_EMC_B1_30_FLEXIO1_FLEXIO30 { + pinmux = <0x400e8088 8 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B { + pinmux = <0x400e8088 1 0x400e8540 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio7_io30: IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 { + pinmux = <0x400e8088 10 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio_mux1_io30: IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 { + pinmux = <0x400e8088 5 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_semc_data08: IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 { + pinmux = <0x400e8088 0 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexio1_flexio31: IOMUXC_GPIO_EMC_B1_31_FLEXIO1_FLEXIO31 { + pinmux = <0x400e808c 8 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A { + pinmux = <0x400e808c 1 0x400e8534 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio7_io31: IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 { + pinmux = <0x400e808c 10 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio_mux1_io31: IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 { + pinmux = <0x400e808c 5 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_semc_data09: IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 { + pinmux = <0x400e808c 0 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B { + pinmux = <0x400e8090 1 0x400e8544 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio8_io00: IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 { + pinmux = <0x400e8090 10 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00_cm7: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00_CM7 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_semc_data10: IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 { + pinmux = <0x400e8090 0 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A { + pinmux = <0x400e8094 1 0x400e8538 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio8_io01: IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 { + pinmux = <0x400e8094 10 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01_cm7: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01_CM7 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_semc_data11: IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 { + pinmux = <0x400e8094 0 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B { + pinmux = <0x400e8098 1 0x400e8548 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio8_io02: IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 { + pinmux = <0x400e8098 10 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02_cm7: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02_CM7 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_semc_data12: IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 { + pinmux = <0x400e8098 0 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio8_io03: IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 { + pinmux = <0x400e809c 10 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03_cm7: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03_CM7 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_semc_data13: IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 { + pinmux = <0x400e809c 0 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_in09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_IN09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_INOUT09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio8_io04: IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 { + pinmux = <0x400e80a0 10 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04_cm7: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04_CM7 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_semc_data14: IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 { + pinmux = <0x400e80a0 0 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_in10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_IN10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_INOUT10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio8_io05: IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 { + pinmux = <0x400e80a4 10 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05_cm7: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05_CM7 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_semc_data15: IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 { + pinmux = <0x400e80a4 0 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_in11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_IN11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_INOUT11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_flexpwm1_pwm3_a: IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A { + pinmux = <0x400e80a8 1 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio8_io06: IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 { + pinmux = <0x400e80a8 10 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06_cm7: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06_CM7 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_qtimer1_timer1: IOMUXC_GPIO_EMC_B1_38_QTIMER1_TIMER1 { + pinmux = <0x400e80a8 2 0x400e8640 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_semc_dm01: IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 { + pinmux = <0x400e80a8 0 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_flexpwm1_pwm3_b: IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B { + pinmux = <0x400e80ac 1 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio8_io07: IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 { + pinmux = <0x400e80ac 10 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07_cm7: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07_CM7 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_qtimer2_timer1: IOMUXC_GPIO_EMC_B1_39_QTIMER2_TIMER1 { + pinmux = <0x400e80ac 2 0x400e864c 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_semc_dqs: IOMUXC_GPIO_EMC_B1_39_SEMC_DQS { + pinmux = <0x400e80ac 0 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_ccm_clko1: IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 { + pinmux = <0x400e80b0 9 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_enet_1g_mdc: IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC { + pinmux = <0x400e80b0 7 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio8_io08: IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 { + pinmux = <0x400e80b0 10 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08_cm7: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08_CM7 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_lpuart6_tx: IOMUXC_GPIO_EMC_B1_40_LPUART6_TX { + pinmux = <0x400e80b0 3 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_mqs_right: IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT { + pinmux = <0x400e80b0 2 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_semc_rdy: IOMUXC_GPIO_EMC_B1_40_SEMC_RDY { + pinmux = <0x400e80b0 0 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_in12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_IN12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_INOUT12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_ccm_clko2: IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 { + pinmux = <0x400e80b4 9 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_enet_1g_mdio: IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO { + pinmux = <0x400e80b4 7 0x400e84c8 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_flexspi2_b_data07: IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 { + pinmux = <0x400e80b4 4 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio8_io09: IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 { + pinmux = <0x400e80b4 10 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09_cm7: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09_CM7 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_lpuart6_rx: IOMUXC_GPIO_EMC_B1_41_LPUART6_RX { + pinmux = <0x400e80b4 3 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_mqs_left: IOMUXC_GPIO_EMC_B1_41_MQS_LEFT { + pinmux = <0x400e80b4 2 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_semc_csx00: IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 { + pinmux = <0x400e80b4 0 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_in13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_IN13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_INOUT13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_ccm_enet_ref_clk_25m: IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e80b8 1 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A { + pinmux = <0x400e80b8 11 0x400e8530 1 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexspi2_b_data06: IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 { + pinmux = <0x400e80b8 4 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio8_io10: IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 { + pinmux = <0x400e80b8 10 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10_cm7: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10_CM7 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpi2c2_scl: IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL { + pinmux = <0x400e80b8 9 0x400e85b4 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpspi1_sck: IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK { + pinmux = <0x400e80b8 8 0x400e85d0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpuart6_cts_b: IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B { + pinmux = <0x400e80b8 3 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_00_QTIMER3_TIMER1 { + pinmux = <0x400e80b8 2 0x400e8658 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_semc_data16: IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 { + pinmux = <0x400e80b8 0 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_in20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_inout20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B { + pinmux = <0x400e80bc 11 0x400e8540 1 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexspi2_b_data05: IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 { + pinmux = <0x400e80bc 4 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio8_io11: IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 { + pinmux = <0x400e80bc 10 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11_cm7: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11_CM7 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpi2c2_sda: IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA { + pinmux = <0x400e80bc 9 0x400e85b8 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpspi1_pcs0: IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 { + pinmux = <0x400e80bc 8 0x400e85cc 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpuart6_rts_b: IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B { + pinmux = <0x400e80bc 3 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_qtimer4_timer1: IOMUXC_GPIO_EMC_B2_01_QTIMER4_TIMER1 { + pinmux = <0x400e80bc 2 0x400e8664 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_semc_data17: IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 { + pinmux = <0x400e80bc 0 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_usdhc2_cd_b: IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B { + pinmux = <0x400e80bc 1 0x400e86d0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_in21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_inout21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A { + pinmux = <0x400e80c0 11 0x400e8534 1 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexspi2_b_data04: IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 { + pinmux = <0x400e80c0 4 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio8_io12: IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 { + pinmux = <0x400e80c0 10 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12_cm7: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12_CM7 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_lpspi1_sdo: IOMUXC_GPIO_EMC_B2_02_LPSPI1_SDO { + pinmux = <0x400e80c0 8 0x400e85d8 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_semc_data18: IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 { + pinmux = <0x400e80c0 0 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_usdhc2_wp: IOMUXC_GPIO_EMC_B2_02_USDHC2_WP { + pinmux = <0x400e80c0 1 0x400e86d4 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_video_mux_csi_data23: IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 { + pinmux = <0x400e80c0 3 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_in22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_inout22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_enet_1g_tdata03: IOMUXC_GPIO_EMC_B2_03_ENET_1G_TDATA03 { + pinmux = <0x400e80c4 7 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B { + pinmux = <0x400e80c4 11 0x400e8544 1 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexspi2_b_data03: IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 { + pinmux = <0x400e80c4 4 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio8_io13: IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 { + pinmux = <0x400e80c4 10 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13_cm7: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13_CM7 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_lpspi1_sdi: IOMUXC_GPIO_EMC_B2_03_LPSPI1_SDI { + pinmux = <0x400e80c4 8 0x400e85d4 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_semc_data19: IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 { + pinmux = <0x400e80c4 0 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_usdhc2_vselect: IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT { + pinmux = <0x400e80c4 1 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_video_mux_csi_data22: IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 { + pinmux = <0x400e80c4 3 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_in23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_inout23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_enet_1g_tdata02: IOMUXC_GPIO_EMC_B2_04_ENET_1G_TDATA02 { + pinmux = <0x400e80c8 7 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A { + pinmux = <0x400e80c8 11 0x400e8538 1 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexspi2_b_data02: IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 { + pinmux = <0x400e80c8 4 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio8_io14: IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 { + pinmux = <0x400e80c8 10 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14_cm7: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14_CM7 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_lpspi3_sck: IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK { + pinmux = <0x400e80c8 8 0x400e8600 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_sai2_mclk: IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK { + pinmux = <0x400e80c8 2 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_semc_data20: IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 { + pinmux = <0x400e80c8 0 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_usdhc2_reset_b: IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B { + pinmux = <0x400e80c8 1 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_video_mux_csi_data21: IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 { + pinmux = <0x400e80c8 3 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_in24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_inout24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_enet_1g_rx_clk: IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK { + pinmux = <0x400e80cc 7 0x400e84cc 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B { + pinmux = <0x400e80cc 11 0x400e8548 1 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexspi2_b_data01: IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 { + pinmux = <0x400e80cc 4 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio8_io15: IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 { + pinmux = <0x400e80cc 10 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15_cm7: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15_CM7 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpt3_clk: IOMUXC_GPIO_EMC_B2_05_GPT3_CLK { + pinmux = <0x400e80cc 1 0x400e8598 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_lpspi3_pcs0: IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 { + pinmux = <0x400e80cc 8 0x400e85f0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_pit1_trigger00: IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER00 { + pinmux = <0x400e80cc 9 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_sai2_rx_sync: IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC { + pinmux = <0x400e80cc 2 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_semc_data21: IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 { + pinmux = <0x400e80cc 0 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_video_mux_csi_data20: IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 { + pinmux = <0x400e80cc 3 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_in25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_inout25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_enet_1g_tx_er: IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER { + pinmux = <0x400e80d0 7 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A { + pinmux = <0x400e80d0 11 0x400e853c 1 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexspi2_b_data00: IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 { + pinmux = <0x400e80d0 4 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio8_io16: IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 { + pinmux = <0x400e80d0 10 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16_cm7: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16_CM7 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpt3_capture1: IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 { + pinmux = <0x400e80d0 1 0x400e8590 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_lpspi3_sdo: IOMUXC_GPIO_EMC_B2_06_LPSPI3_SDO { + pinmux = <0x400e80d0 8 0x400e8608 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_pit1_trigger01: IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER01 { + pinmux = <0x400e80d0 9 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_sai2_rx_bclk: IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK { + pinmux = <0x400e80d0 2 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_semc_data22: IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 { + pinmux = <0x400e80d0 0 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_video_mux_csi_data19: IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 { + pinmux = <0x400e80d0 3 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_in26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_IN26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_inout26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_enet_1g_rdata03: IOMUXC_GPIO_EMC_B2_07_ENET_1G_RDATA03 { + pinmux = <0x400e80d4 7 0x400e84dc 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B { + pinmux = <0x400e80d4 11 0x400e854c 1 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexspi2_b_dqs: IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS { + pinmux = <0x400e80d4 4 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio8_io17: IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 { + pinmux = <0x400e80d4 10 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17_cm7: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17_CM7 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpt3_capture2: IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 { + pinmux = <0x400e80d4 1 0x400e8594 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_lpspi3_sdi: IOMUXC_GPIO_EMC_B2_07_LPSPI3_SDI { + pinmux = <0x400e80d4 8 0x400e8604 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_pit1_trigger02: IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER02 { + pinmux = <0x400e80d4 9 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_sai2_rx_data: IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA { + pinmux = <0x400e80d4 2 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_semc_data23: IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 { + pinmux = <0x400e80d4 0 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_video_mux_csi_data18: IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 { + pinmux = <0x400e80d4 3 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_in27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_IN27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_inout27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_enet_1g_rdata02: IOMUXC_GPIO_EMC_B2_08_ENET_1G_RDATA02 { + pinmux = <0x400e80d8 7 0x400e84d8 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B { + pinmux = <0x400e80d8 4 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio8_io18: IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 { + pinmux = <0x400e80d8 10 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18_cm7: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18_CM7 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpt3_compare1: IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 { + pinmux = <0x400e80d8 1 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_lpspi3_pcs1: IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 { + pinmux = <0x400e80d8 8 0x400e85f4 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_pit1_trigger03: IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER03 { + pinmux = <0x400e80d8 9 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_sai2_tx_data: IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA { + pinmux = <0x400e80d8 2 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_semc_dm02: IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 { + pinmux = <0x400e80d8 0 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_video_mux_csi_data17: IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 { + pinmux = <0x400e80d8 3 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_in28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_IN28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_inout28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_enet_1g_crs: IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS { + pinmux = <0x400e80dc 7 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_flexspi2_b_sclk: IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK { + pinmux = <0x400e80dc 4 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio8_io19: IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 { + pinmux = <0x400e80dc 10 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19_cm7: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19_CM7 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpt3_compare2: IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 { + pinmux = <0x400e80dc 1 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_lpspi3_pcs2: IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 { + pinmux = <0x400e80dc 8 0x400e85f8 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_qtimer1_timer0: IOMUXC_GPIO_EMC_B2_09_QTIMER1_TIMER0 { + pinmux = <0x400e80dc 9 0x400e863c 1 0x400e8320>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_sai2_tx_bclk: IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK { + pinmux = <0x400e80dc 2 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_semc_data24: IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 { + pinmux = <0x400e80dc 0 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_video_mux_csi_data16: IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 { + pinmux = <0x400e80dc 3 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_in29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_IN29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_inout29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_enet_1g_col: IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL { + pinmux = <0x400e80e0 7 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_flexspi2_a_sclk: IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK { + pinmux = <0x400e80e0 4 0x400e858c 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio8_io20: IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 { + pinmux = <0x400e80e0 10 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20_cm7: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20_CM7 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpt3_compare3: IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 { + pinmux = <0x400e80e0 1 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_lpspi3_pcs3: IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 { + pinmux = <0x400e80e0 8 0x400e85fc 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_qtimer1_timer1: IOMUXC_GPIO_EMC_B2_10_QTIMER1_TIMER1 { + pinmux = <0x400e80e0 9 0x400e8640 1 0x400e8324>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_sai2_tx_sync: IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC { + pinmux = <0x400e80e0 2 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_semc_data25: IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 { + pinmux = <0x400e80e0 0 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_video_mux_csi_field: IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD { + pinmux = <0x400e80e0 3 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_in30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_IN30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_inout30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_enet_1g_tdata00: IOMUXC_GPIO_EMC_B2_11_ENET_1G_TDATA00 { + pinmux = <0x400e80e4 2 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B { + pinmux = <0x400e80e4 4 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio8_io21: IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 { + pinmux = <0x400e80e4 10 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21_cm7: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21_CM7 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_qtimer1_timer2: IOMUXC_GPIO_EMC_B2_11_QTIMER1_TIMER2 { + pinmux = <0x400e80e4 9 0x400e8644 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sai3_rx_sync: IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC { + pinmux = <0x400e80e4 3 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_semc_data26: IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 { + pinmux = <0x400e80e4 0 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sim1_trxd: IOMUXC_GPIO_EMC_B2_11_SIM1_TRXD { + pinmux = <0x400e80e4 8 0x400e869c 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_spdif_in: IOMUXC_GPIO_EMC_B2_11_SPDIF_IN { + pinmux = <0x400e80e4 1 0x400e86b4 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_in31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_IN31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_inout31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_enet_1g_tdata01: IOMUXC_GPIO_EMC_B2_12_ENET_1G_TDATA01 { + pinmux = <0x400e80e8 2 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_flexspi2_a_dqs: IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS { + pinmux = <0x400e80e8 4 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio8_io22: IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 { + pinmux = <0x400e80e8 10 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22_cm7: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22_CM7 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_qtimer1_timer3: IOMUXC_GPIO_EMC_B2_12_QTIMER1_TIMER3 { + pinmux = <0x400e80e8 9 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4030 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sai3_rx_bclk: IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK { + pinmux = <0x400e80e8 3 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_semc_data27: IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 { + pinmux = <0x400e80e8 0 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sim1_clk: IOMUXC_GPIO_EMC_B2_12_SIM1_CLK { + pinmux = <0x400e80e8 8 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_spdif_out: IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT { + pinmux = <0x400e80e8 1 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_in32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_IN32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_inout32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_enet_1g_tx_en: IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN { + pinmux = <0x400e80ec 2 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_flexspi2_a_data00: IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 { + pinmux = <0x400e80ec 4 0x400e857c 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio8_io23: IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 { + pinmux = <0x400e80ec 10 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23_cm7: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23_CM7 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_qtimer2_timer0: IOMUXC_GPIO_EMC_B2_13_QTIMER2_TIMER0 { + pinmux = <0x400e80ec 9 0x400e8648 1 0x400e8330>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sai3_rx_data: IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA { + pinmux = <0x400e80ec 3 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_semc_data28: IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 { + pinmux = <0x400e80ec 0 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sim1_rst_b: IOMUXC_GPIO_EMC_B2_13_SIM1_RST_B { + pinmux = <0x400e80ec 8 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_in33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_IN33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_inout33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_enet_1g_tx_clk_io: IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO { + pinmux = <0x400e80f0 2 0x400e84e8 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_flexspi2_a_data01: IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 { + pinmux = <0x400e80f0 4 0x400e8580 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio8_io24: IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 { + pinmux = <0x400e80f0 10 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24_cm7: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24_CM7 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_qtimer2_timer1: IOMUXC_GPIO_EMC_B2_14_QTIMER2_TIMER1 { + pinmux = <0x400e80f0 9 0x400e864c 1 0x400e8334>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sai3_tx_data: IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA { + pinmux = <0x400e80f0 3 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_semc_data29: IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 { + pinmux = <0x400e80f0 0 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sim1_sven: IOMUXC_GPIO_EMC_B2_14_SIM1_SVEN { + pinmux = <0x400e80f0 8 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_in34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_IN34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_inout34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_enet_1g_rdata00: IOMUXC_GPIO_EMC_B2_15_ENET_1G_RDATA00 { + pinmux = <0x400e80f4 2 0x400e84d0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_flexspi2_a_data02: IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 { + pinmux = <0x400e80f4 4 0x400e8584 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio8_io25: IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 { + pinmux = <0x400e80f4 10 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25_cm7: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25_CM7 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_qtimer2_timer2: IOMUXC_GPIO_EMC_B2_15_QTIMER2_TIMER2 { + pinmux = <0x400e80f4 9 0x400e8650 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sai3_tx_bclk: IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK { + pinmux = <0x400e80f4 3 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_semc_data30: IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 { + pinmux = <0x400e80f4 0 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sim1_pd: IOMUXC_GPIO_EMC_B2_15_SIM1_PD { + pinmux = <0x400e80f4 8 0x400e86a0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_in35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_IN35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_inout35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_enet_1g_rdata01: IOMUXC_GPIO_EMC_B2_16_ENET_1G_RDATA01 { + pinmux = <0x400e80f8 2 0x400e84d4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_flexspi2_a_data03: IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 { + pinmux = <0x400e80f8 4 0x400e8588 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio8_io26: IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 { + pinmux = <0x400e80f8 10 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26_cm7: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26_CM7 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_qtimer2_timer3: IOMUXC_GPIO_EMC_B2_16_QTIMER2_TIMER3 { + pinmux = <0x400e80f8 9 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4034 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sai3_tx_sync: IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC { + pinmux = <0x400e80f8 3 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_semc_data31: IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 { + pinmux = <0x400e80f8 0 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sim1_power_fail: IOMUXC_GPIO_EMC_B2_16_SIM1_POWER_FAIL { + pinmux = <0x400e80f8 8 0x400e86a4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_in14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_IN14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_enet_1g_rx_en: IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN { + pinmux = <0x400e80fc 2 0x400e84e0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_flexspi2_a_data04: IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 { + pinmux = <0x400e80fc 4 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio8_io27: IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 { + pinmux = <0x400e80fc 10 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27_cm7: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27_CM7 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_qtimer3_timer0: IOMUXC_GPIO_EMC_B2_17_QTIMER3_TIMER0 { + pinmux = <0x400e80fc 9 0x400e8654 1 0x400e8340>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_sai3_mclk: IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK { + pinmux = <0x400e80fc 3 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_semc_dm03: IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 { + pinmux = <0x400e80fc 0 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_wdog1_wdog_any: IOMUXC_GPIO_EMC_B2_17_WDOG1_WDOG_ANY { + pinmux = <0x400e80fc 8 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_in15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_IN15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_enet_1g_rx_er: IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER { + pinmux = <0x400e8100 2 0x400e84e4 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_ewm_ewm_out_b: IOMUXC_GPIO_EMC_B2_18_EWM_EWM_OUT_B { + pinmux = <0x400e8100 3 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi1_a_dqs: IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS { + pinmux = <0x400e8100 6 0x400e8550 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi2_a_data05: IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 { + pinmux = <0x400e8100 4 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio8_io28: IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 { + pinmux = <0x400e8100 10 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28_cm7: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28_CM7 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_18_QTIMER3_TIMER1 { + pinmux = <0x400e8100 9 0x400e8658 1 0x400e8344>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_semc_dqs4: IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 { + pinmux = <0x400e8100 0 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_wdog1_wdog_b: IOMUXC_GPIO_EMC_B2_18_WDOG1_WDOG_B { + pinmux = <0x400e8100 8 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_IN16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC { + pinmux = <0x400e8104 2 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_ref_clk1: IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK1 { + pinmux = <0x400e8104 3 0x400e84c4 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_MDC { + pinmux = <0x400e8104 1 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_flexspi2_a_data06: IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 { + pinmux = <0x400e8104 4 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio8_io29: IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 { + pinmux = <0x400e8104 10 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29_cm7: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29_CM7 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_qtimer3_timer2: IOMUXC_GPIO_EMC_B2_19_QTIMER3_TIMER2 { + pinmux = <0x400e8104 9 0x400e865c 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_semc_clkx00: IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 { + pinmux = <0x400e8104 0 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_1g_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO { + pinmux = <0x400e8108 2 0x400e84c8 1 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_MDIO { + pinmux = <0x400e8108 1 0x400e84ac 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_flexspi2_a_data07: IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 { + pinmux = <0x400e8108 4 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio8_io30: IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 { + pinmux = <0x400e8108 10 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30_cm7: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30_CM7 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_qtimer3_timer3: IOMUXC_GPIO_EMC_B2_20_QTIMER3_TIMER3 { + pinmux = <0x400e8108 9 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e4038 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_semc_clkx01: IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 { + pinmux = <0x400e8108 0 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_can3_tx: IOMUXC_LPSR_GPIO_LPSR_00_CAN3_TX { + pinmux = <0x40c08000 0 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_cm4_imxrt_txev: IOMUXC_LPSR_GPIO_LPSR_00_CM4_IMXRT_TXEV { + pinmux = <0x40c08000 3 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio12_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO12_IO00 { + pinmux = <0x40c08000 10 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio_mux6_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO_MUX6_IO00 { + pinmux = <0x40c08000 5 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_00_LPUART12_TX { + pinmux = <0x40c08000 6 0x40c080b0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mic_clk: IOMUXC_LPSR_GPIO_LPSR_00_MIC_CLK { + pinmux = <0x40c08000 1 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mqs_right: IOMUXC_LPSR_GPIO_LPSR_00_MQS_RIGHT { + pinmux = <0x40c08000 2 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_00_SAI4_MCLK { + pinmux = <0x40c08000 7 0x40c080c8 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_can3_rx: IOMUXC_LPSR_GPIO_LPSR_01_CAN3_RX { + pinmux = <0x40c08004 0 0x40c08080 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_cm4_imxrt_rxev: IOMUXC_LPSR_GPIO_LPSR_01_CM4_IMXRT_RXEV { + pinmux = <0x40c08004 3 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio12_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO12_IO01 { + pinmux = <0x40c08004 10 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO_MUX6_IO01 { + pinmux = <0x40c08004 5 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_01_LPUART12_RX { + pinmux = <0x40c08004 6 0x40c080ac 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_01_MIC_BITSTREAM00 { + pinmux = <0x40c08004 1 0x40c080b4 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mqs_left: IOMUXC_LPSR_GPIO_LPSR_01_MQS_LEFT { + pinmux = <0x40c08004 2 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio12_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO12_IO02 { + pinmux = <0x40c08008 10 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO_MUX6_IO02 { + pinmux = <0x40c08008 5 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_02_LPSPI5_SCK { + pinmux = <0x40c08008 1 0x40c08098 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_mqs_right: IOMUXC_LPSR_GPIO_LPSR_02_MQS_RIGHT { + pinmux = <0x40c08008 3 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_02_SAI4_TX_DATA { + pinmux = <0x40c08008 2 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_src_boot_mode00: IOMUXC_LPSR_GPIO_LPSR_02_SRC_BOOT_MODE00 { + pinmux = <0x40c08008 0 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio12_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO12_IO03 { + pinmux = <0x40c0800c 10 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO_MUX6_IO03 { + pinmux = <0x40c0800c 5 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_03_LPSPI5_PCS0 { + pinmux = <0x40c0800c 1 0x40c08094 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_mqs_left: IOMUXC_LPSR_GPIO_LPSR_03_MQS_LEFT { + pinmux = <0x40c0800c 3 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_03_SAI4_TX_SYNC { + pinmux = <0x40c0800c 2 0x40c080dc 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_src_boot_mode01: IOMUXC_LPSR_GPIO_LPSR_03_SRC_BOOT_MODE01 { + pinmux = <0x40c0800c 0 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio12_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO12_IO04 { + pinmux = <0x40c08010 10 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO_MUX6_IO04 { + pinmux = <0x40c08010 5 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_04_LPI2C5_SDA { + pinmux = <0x40c08010 0 0x40c08088 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_04_LPSPI5_SDO { + pinmux = <0x40c08010 1 0x40c080a0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_04_LPUART11_TX { + pinmux = <0x40c08010 6 0x40c080a8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart12_rts_b: IOMUXC_LPSR_GPIO_LPSR_04_LPUART12_RTS_B { + pinmux = <0x40c08010 3 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_04_SAI4_TX_BCLK { + pinmux = <0x40c08010 2 0x40c080d8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio12_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO12_IO05 { + pinmux = <0x40c08014 10 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO_MUX6_IO05 { + pinmux = <0x40c08014 5 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_05_LPI2C5_SCL { + pinmux = <0x40c08014 0 0x40c08084 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_05_LPSPI5_SDI { + pinmux = <0x40c08014 1 0x40c0809c 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_05_LPUART11_RX { + pinmux = <0x40c08014 6 0x40c080a4 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart12_cts_b: IOMUXC_LPSR_GPIO_LPSR_05_LPUART12_CTS_B { + pinmux = <0x40c08014 3 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_05_SAI4_MCLK { + pinmux = <0x40c08014 2 0x40c080c8 1 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_can3_tx: IOMUXC_LPSR_GPIO_LPSR_06_CAN3_TX { + pinmux = <0x40c08018 6 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio12_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO12_IO06 { + pinmux = <0x40c08018 10 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO_MUX6_IO06 { + pinmux = <0x40c08018 5 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_06_LPI2C6_SDA { + pinmux = <0x40c08018 0 0x40c08090 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi5_pcs1: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI5_PCS1 { + pinmux = <0x40c08018 8 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi6_pcs3: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI6_PCS3 { + pinmux = <0x40c08018 4 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_06_LPUART12_TX { + pinmux = <0x40c08018 3 0x40c080b0 1 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_06_PIT2_TRIGGER03 { + pinmux = <0x40c08018 7 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_06_SAI4_RX_DATA { + pinmux = <0x40c08018 2 0x40c080d0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_can3_rx: IOMUXC_LPSR_GPIO_LPSR_07_CAN3_RX { + pinmux = <0x40c0801c 6 0x40c08080 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio12_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO12_IO07 { + pinmux = <0x40c0801c 10 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO_MUX6_IO07 { + pinmux = <0x40c0801c 5 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_07_LPI2C6_SCL { + pinmux = <0x40c0801c 0 0x40c0808c 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi5_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI5_PCS2 { + pinmux = <0x40c0801c 8 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi6_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI6_PCS2 { + pinmux = <0x40c0801c 4 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_07_LPUART12_RX { + pinmux = <0x40c0801c 3 0x40c080ac 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_07_PIT2_TRIGGER02 { + pinmux = <0x40c0801c 7 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_07_SAI4_RX_BCLK { + pinmux = <0x40c0801c 2 0x40c080cc 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_can3_tx: IOMUXC_LPSR_GPIO_LPSR_08_CAN3_TX { + pinmux = <0x40c08020 1 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio12_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO12_IO08 { + pinmux = <0x40c08020 10 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO_MUX6_IO08 { + pinmux = <0x40c08020 5 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_08_LPI2C5_SDA { + pinmux = <0x40c08020 6 0x40c08088 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi5_pcs3: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI5_PCS3 { + pinmux = <0x40c08020 8 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi6_pcs1: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI6_PCS1 { + pinmux = <0x40c08020 4 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_08_LPUART11_TX { + pinmux = <0x40c08020 0 0x40c080a8 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_mic_clk: IOMUXC_LPSR_GPIO_LPSR_08_MIC_CLK { + pinmux = <0x40c08020 3 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_08_PIT2_TRIGGER01 { + pinmux = <0x40c08020 7 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_08_SAI4_RX_SYNC { + pinmux = <0x40c08020 2 0x40c080d4 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_can3_rx: IOMUXC_LPSR_GPIO_LPSR_09_CAN3_RX { + pinmux = <0x40c08024 1 0x40c08080 2 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio12_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO12_IO09 { + pinmux = <0x40c08024 10 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO_MUX6_IO09 { + pinmux = <0x40c08024 5 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_09_LPI2C5_SCL { + pinmux = <0x40c08024 6 0x40c08084 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpspi6_pcs0: IOMUXC_LPSR_GPIO_LPSR_09_LPSPI6_PCS0 { + pinmux = <0x40c08024 4 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_09_LPUART11_RX { + pinmux = <0x40c08024 0 0x40c080a4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_09_MIC_BITSTREAM00 { + pinmux = <0x40c08024 3 0x40c080b4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_09_PIT2_TRIGGER00 { + pinmux = <0x40c08024 2 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_09_SAI4_TX_DATA { + pinmux = <0x40c08024 7 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio12_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO12_IO10 { + pinmux = <0x40c08028 10 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO_MUX6_IO10 { + pinmux = <0x40c08028 5 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_jtag_mux_trstb: IOMUXC_LPSR_GPIO_LPSR_10_JTAG_MUX_TRSTB { + pinmux = <0x40c08028 0 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c5_scls: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C5_SCLS { + pinmux = <0x40c08028 6 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C6_SDA { + pinmux = <0x40c08028 2 0x40c08090 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpspi6_sck: IOMUXC_LPSR_GPIO_LPSR_10_LPSPI6_SCK { + pinmux = <0x40c08028 4 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart11_cts_b: IOMUXC_LPSR_GPIO_LPSR_10_LPUART11_CTS_B { + pinmux = <0x40c08028 1 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_10_LPUART12_TX { + pinmux = <0x40c08028 8 0x40c080b0 2 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_10_MIC_BITSTREAM01 { + pinmux = <0x40c08028 3 0x40c080b8 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_10_SAI4_TX_SYNC { + pinmux = <0x40c08028 7 0x40c080dc 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_arm_trace_swo: IOMUXC_LPSR_GPIO_LPSR_11_ARM_TRACE_SWO { + pinmux = <0x40c0802c 7 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio12_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO12_IO11 { + pinmux = <0x40c0802c 10 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO_MUX6_IO11 { + pinmux = <0x40c0802c 5 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_jtag_mux_tdo: IOMUXC_LPSR_GPIO_LPSR_11_JTAG_MUX_TDO { + pinmux = <0x40c0802c 0 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c5_sdas: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C5_SDAS { + pinmux = <0x40c0802c 6 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C6_SCL { + pinmux = <0x40c0802c 2 0x40c0808c 1 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpspi6_sdo: IOMUXC_LPSR_GPIO_LPSR_11_LPSPI6_SDO { + pinmux = <0x40c0802c 4 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart11_rts_b: IOMUXC_LPSR_GPIO_LPSR_11_LPUART11_RTS_B { + pinmux = <0x40c0802c 1 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_11_LPUART12_RX { + pinmux = <0x40c0802c 8 0x40c080ac 2 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_11_MIC_BITSTREAM02 { + pinmux = <0x40c0802c 3 0x40c080bc 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio12_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO12_IO12 { + pinmux = <0x40c08030 10 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO_MUX6_IO12 { + pinmux = <0x40c08030 5 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_jtag_mux_tdi: IOMUXC_LPSR_GPIO_LPSR_12_JTAG_MUX_TDI { + pinmux = <0x40c08030 0 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpi2c5_hreq: IOMUXC_LPSR_GPIO_LPSR_12_LPI2C5_HREQ { + pinmux = <0x40c08030 6 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI5_SCK { + pinmux = <0x40c08030 8 0x40c08098 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi6_sdi: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI6_SDI { + pinmux = <0x40c08030 4 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_12_MIC_BITSTREAM03 { + pinmux = <0x40c08030 3 0x40c080c0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_12_PIT2_TRIGGER00 { + pinmux = <0x40c08030 1 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_12_SAI4_TX_BCLK { + pinmux = <0x40c08030 7 0x40c080d8 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio12_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO12_IO13 { + pinmux = <0x40c08034 10 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO_MUX6_IO13 { + pinmux = <0x40c08034 5 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_jtag_mux_mod: IOMUXC_LPSR_GPIO_LPSR_13_JTAG_MUX_MOD { + pinmux = <0x40c08034 0 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_13_LPSPI5_PCS0 { + pinmux = <0x40c08034 8 0x40c08094 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_13_MIC_BITSTREAM01 { + pinmux = <0x40c08034 1 0x40c080b8 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_13_PIT2_TRIGGER01 { + pinmux = <0x40c08034 2 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_13_SAI4_RX_DATA { + pinmux = <0x40c08034 7 0x40c080d0 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio12_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO12_IO14 { + pinmux = <0x40c08038 10 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO_MUX6_IO14 { + pinmux = <0x40c08038 5 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_jtag_mux_tck: IOMUXC_LPSR_GPIO_LPSR_14_JTAG_MUX_TCK { + pinmux = <0x40c08038 0 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_14_LPSPI5_SDO { + pinmux = <0x40c08038 8 0x40c080a0 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_14_MIC_BITSTREAM02 { + pinmux = <0x40c08038 1 0x40c080bc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_14_PIT2_TRIGGER02 { + pinmux = <0x40c08038 2 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_14_SAI4_RX_BCLK { + pinmux = <0x40c08038 7 0x40c080cc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio12_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO12_IO15 { + pinmux = <0x40c0803c 10 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO_MUX6_IO15 { + pinmux = <0x40c0803c 5 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_jtag_mux_tms: IOMUXC_LPSR_GPIO_LPSR_15_JTAG_MUX_TMS { + pinmux = <0x40c0803c 0 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_15_LPSPI5_SDI { + pinmux = <0x40c0803c 8 0x40c0809c 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_15_MIC_BITSTREAM03 { + pinmux = <0x40c0803c 1 0x40c080c0 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_15_PIT2_TRIGGER03 { + pinmux = <0x40c0803c 2 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_15_SAI4_RX_SYNC { + pinmux = <0x40c0803c 7 0x40c080d4 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi2_a_ss0_b: IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B { + pinmux = <0x400e819c 6 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio10_io03: IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 { + pinmux = <0x400e819c 10 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio_mux4_io03: IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 { + pinmux = <0x400e819c 5 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpt4_capture1: IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 { + pinmux = <0x400e819c 3 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_kpp_row07: IOMUXC_GPIO_SD_B1_00_KPP_ROW07 { + pinmux = <0x400e819c 8 0x400e85a8 1 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc1_cmd: IOMUXC_GPIO_SD_B1_00_USDHC1_CMD { + pinmux = <0x400e819c 0 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi2_a_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK { + pinmux = <0x400e81a0 6 0x400e858c 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio10_io04: IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 { + pinmux = <0x400e81a0 10 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio_mux4_io04: IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 { + pinmux = <0x400e81a0 5 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpt4_capture2: IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 { + pinmux = <0x400e81a0 3 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_kpp_col07: IOMUXC_GPIO_SD_B1_01_KPP_COL07 { + pinmux = <0x400e81a0 8 0x400e85a0 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc1_clk: IOMUXC_GPIO_SD_B1_01_USDHC1_CLK { + pinmux = <0x400e81a0 0 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_in21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_inout21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81a4 9 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi2_a_data00: IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 { + pinmux = <0x400e81a4 6 0x400e857c 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio10_io05: IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 { + pinmux = <0x400e81a4 10 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio_mux4_io05: IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 { + pinmux = <0x400e81a4 5 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpt4_compare1: IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 { + pinmux = <0x400e81a4 3 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_kpp_row06: IOMUXC_GPIO_SD_B1_02_KPP_ROW06 { + pinmux = <0x400e81a4 8 0x400e85a4 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc1_data0: IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 { + pinmux = <0x400e81a4 0 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_in22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_inout22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi1_b_ss1_b: IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B { + pinmux = <0x400e81a8 9 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi2_a_data01: IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 { + pinmux = <0x400e81a8 6 0x400e8580 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio10_io06: IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 { + pinmux = <0x400e81a8 10 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio_mux4_io06: IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 { + pinmux = <0x400e81a8 5 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpt4_compare2: IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 { + pinmux = <0x400e81a8 3 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_kpp_col06: IOMUXC_GPIO_SD_B1_03_KPP_COL06 { + pinmux = <0x400e81a8 8 0x400e859c 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc1_data1: IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 { + pinmux = <0x400e81a8 0 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_in23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_inout23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81ac 8 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi2_a_data02: IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 { + pinmux = <0x400e81ac 6 0x400e8584 1 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio10_io07: IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 { + pinmux = <0x400e81ac 10 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio_mux4_io07: IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 { + pinmux = <0x400e81ac 5 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpt4_compare3: IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 { + pinmux = <0x400e81ac 3 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc1_data2: IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 { + pinmux = <0x400e81ac 0 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_in24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_inout24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi1_b_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS { + pinmux = <0x400e81b0 8 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi2_a_data03: IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 { + pinmux = <0x400e81b0 6 0x400e8588 1 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio10_io08: IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 { + pinmux = <0x400e81b0 10 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio_mux4_io08: IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 { + pinmux = <0x400e81b0 5 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpt4_clk: IOMUXC_GPIO_SD_B1_05_GPT4_CLK { + pinmux = <0x400e81b0 3 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc1_data3: IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 { + pinmux = <0x400e81b0 0 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_in25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_inout25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_enet_1g_rx_en: IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN { + pinmux = <0x400e81b4 2 0x400e84e0 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_flexspi1_b_data03: IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 { + pinmux = <0x400e81b4 1 0x400e8570 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio10_io09: IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 { + pinmux = <0x400e81b4 10 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio_mux4_io09: IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 { + pinmux = <0x400e81b4 5 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpspi4_sck: IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK { + pinmux = <0x400e81b4 4 0x400e8610 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpuart9_tx: IOMUXC_GPIO_SD_B2_00_LPUART9_TX { + pinmux = <0x400e81b4 3 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_usdhc2_data3: IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 { + pinmux = <0x400e81b4 0 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_enet_1g_rx_clk: IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK { + pinmux = <0x400e81b8 2 0x400e84cc 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_flexspi1_b_data02: IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 { + pinmux = <0x400e81b8 1 0x400e856c 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio10_io10: IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 { + pinmux = <0x400e81b8 10 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio_mux4_io10: IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 { + pinmux = <0x400e81b8 5 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpspi4_pcs0: IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 { + pinmux = <0x400e81b8 4 0x400e860c 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpuart9_rx: IOMUXC_GPIO_SD_B2_01_LPUART9_RX { + pinmux = <0x400e81b8 3 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_usdhc2_data2: IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 { + pinmux = <0x400e81b8 0 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_enet_1g_rdata00: IOMUXC_GPIO_SD_B2_02_ENET_1G_RDATA00 { + pinmux = <0x400e81bc 2 0x400e84d0 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_flexspi1_b_data01: IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 { + pinmux = <0x400e81bc 1 0x400e8568 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio10_io11: IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 { + pinmux = <0x400e81bc 10 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio_mux4_io11: IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 { + pinmux = <0x400e81bc 5 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpspi4_sdo: IOMUXC_GPIO_SD_B2_02_LPSPI4_SDO { + pinmux = <0x400e81bc 4 0x400e8618 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpuart9_cts_b: IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B { + pinmux = <0x400e81bc 3 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_usdhc2_data1: IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 { + pinmux = <0x400e81bc 0 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_enet_1g_rdata01: IOMUXC_GPIO_SD_B2_03_ENET_1G_RDATA01 { + pinmux = <0x400e81c0 2 0x400e84d4 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_flexspi1_b_data00: IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 { + pinmux = <0x400e81c0 1 0x400e8564 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio10_io12: IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 { + pinmux = <0x400e81c0 10 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio_mux4_io12: IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 { + pinmux = <0x400e81c0 5 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpspi4_sdi: IOMUXC_GPIO_SD_B2_03_LPSPI4_SDI { + pinmux = <0x400e81c0 4 0x400e8614 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpuart9_rts_b: IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B { + pinmux = <0x400e81c0 3 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_usdhc2_data0: IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 { + pinmux = <0x400e81c0 0 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_enet_1g_rdata02: IOMUXC_GPIO_SD_B2_04_ENET_1G_RDATA02 { + pinmux = <0x400e81c4 2 0x400e84d8 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81c4 3 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_b_sclk: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK { + pinmux = <0x400e81c4 1 0x400e8578 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio10_io13: IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 { + pinmux = <0x400e81c4 10 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio_mux4_io13: IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 { + pinmux = <0x400e81c4 5 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_lpspi4_pcs1: IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 { + pinmux = <0x400e81c4 4 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_usdhc2_clk: IOMUXC_GPIO_SD_B2_04_USDHC2_CLK { + pinmux = <0x400e81c4 0 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_enet_1g_rdata03: IOMUXC_GPIO_SD_B2_05_ENET_1G_RDATA03 { + pinmux = <0x400e81c8 2 0x400e84dc 1 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_a_dqs: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS { + pinmux = <0x400e81c8 1 0x400e8550 2 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81c8 3 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio10_io14: IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 { + pinmux = <0x400e81c8 10 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio_mux4_io14: IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 { + pinmux = <0x400e81c8 5 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_lpspi4_pcs2: IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 { + pinmux = <0x400e81c8 4 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_usdhc2_cmd: IOMUXC_GPIO_SD_B2_05_USDHC2_CMD { + pinmux = <0x400e81c8 0 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_enet_1g_tdata03: IOMUXC_GPIO_SD_B2_06_ENET_1G_TDATA03 { + pinmux = <0x400e81cc 2 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_flexspi1_a_ss0_b: IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B { + pinmux = <0x400e81cc 1 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio10_io15: IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 { + pinmux = <0x400e81cc 10 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio_mux4_io15: IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 { + pinmux = <0x400e81cc 5 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpt6_capture1: IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 { + pinmux = <0x400e81cc 4 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_lpspi4_pcs3: IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 { + pinmux = <0x400e81cc 3 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B { + pinmux = <0x400e81cc 0 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_1g_tdata02: IOMUXC_GPIO_SD_B2_07_ENET_1G_TDATA02 { + pinmux = <0x400e81d0 2 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_tx_er: IOMUXC_GPIO_SD_B2_07_ENET_TX_ER { + pinmux = <0x400e81d0 8 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_flexspi1_a_sclk: IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK { + pinmux = <0x400e81d0 1 0x400e8574 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio10_io16: IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 { + pinmux = <0x400e81d0 10 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio_mux4_io16: IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 { + pinmux = <0x400e81d0 5 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpt6_capture2: IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 { + pinmux = <0x400e81d0 4 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpspi2_sck: IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK { + pinmux = <0x400e81d0 6 0x400e85e4 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpuart3_cts_b: IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B { + pinmux = <0x400e81d0 3 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_usdhc2_strobe: IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE { + pinmux = <0x400e81d0 0 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_enet_1g_tdata01: IOMUXC_GPIO_SD_B2_08_ENET_1G_TDATA01 { + pinmux = <0x400e81d4 2 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_flexspi1_a_data00: IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 { + pinmux = <0x400e81d4 1 0x400e8554 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio10_io17: IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 { + pinmux = <0x400e81d4 10 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio_mux4_io17: IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 { + pinmux = <0x400e81d4 5 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpt6_compare1: IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 { + pinmux = <0x400e81d4 4 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpspi2_pcs0: IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 { + pinmux = <0x400e81d4 6 0x400e85dc 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpuart3_rts_b: IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B { + pinmux = <0x400e81d4 3 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_usdhc2_data4: IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 { + pinmux = <0x400e81d4 0 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_enet_1g_tdata00: IOMUXC_GPIO_SD_B2_09_ENET_1G_TDATA00 { + pinmux = <0x400e81d8 2 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_flexspi1_a_data01: IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 { + pinmux = <0x400e81d8 1 0x400e8558 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio10_io18: IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 { + pinmux = <0x400e81d8 10 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio_mux4_io18: IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 { + pinmux = <0x400e81d8 5 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpt6_compare2: IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 { + pinmux = <0x400e81d8 4 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpspi2_sdo: IOMUXC_GPIO_SD_B2_09_LPSPI2_SDO { + pinmux = <0x400e81d8 6 0x400e85ec 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpuart5_cts_b: IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B { + pinmux = <0x400e81d8 3 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_usdhc2_data5: IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 { + pinmux = <0x400e81d8 0 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_enet_1g_tx_en: IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN { + pinmux = <0x400e81dc 2 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_flexspi1_a_data02: IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 { + pinmux = <0x400e81dc 1 0x400e855c 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio10_io19: IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 { + pinmux = <0x400e81dc 10 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio_mux4_io19: IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 { + pinmux = <0x400e81dc 5 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpt6_compare3: IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 { + pinmux = <0x400e81dc 4 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpspi2_sdi: IOMUXC_GPIO_SD_B2_10_LPSPI2_SDI { + pinmux = <0x400e81dc 6 0x400e85e8 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpuart5_rts_b: IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B { + pinmux = <0x400e81dc 3 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_usdhc2_data6: IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 { + pinmux = <0x400e81dc 0 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_ref_clk1: IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e81e0 3 0x400e84c4 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_tx_clk_io: IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e81e0 2 0x400e84e8 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_flexspi1_a_data03: IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 { + pinmux = <0x400e81e0 1 0x400e8560 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio10_io20: IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 { + pinmux = <0x400e81e0 10 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio_mux4_io20: IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 { + pinmux = <0x400e81e0 5 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpt6_clk: IOMUXC_GPIO_SD_B2_11_GPT6_CLK { + pinmux = <0x400e81e0 4 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_lpspi2_pcs1: IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 { + pinmux = <0x400e81e0 6 0x400e85e0 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_usdhc2_data7: IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 { + pinmux = <0x400e81e0 0 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03: IOMUXC_SNVS_GPIO_SNVS_00_DIG_GPIO13_IO03 { + pinmux = <0x40c9400c 5 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_snvs_lp_tamper00: IOMUXC_SNVS_GPIO_SNVS_00_DIG_SNVS_LP_TAMPER00 { + pinmux = <0x40c9400c 0 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04: IOMUXC_SNVS_GPIO_SNVS_01_DIG_GPIO13_IO04 { + pinmux = <0x40c94010 5 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_snvs_lp_tamper01: IOMUXC_SNVS_GPIO_SNVS_01_DIG_SNVS_LP_TAMPER01 { + pinmux = <0x40c94010 0 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05: IOMUXC_SNVS_GPIO_SNVS_02_DIG_GPIO13_IO05 { + pinmux = <0x40c94014 5 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_snvs_lp_tamper02: IOMUXC_SNVS_GPIO_SNVS_02_DIG_SNVS_LP_TAMPER02 { + pinmux = <0x40c94014 0 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06: IOMUXC_SNVS_GPIO_SNVS_03_DIG_GPIO13_IO06 { + pinmux = <0x40c94018 5 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_snvs_lp_tamper03: IOMUXC_SNVS_GPIO_SNVS_03_DIG_SNVS_LP_TAMPER03 { + pinmux = <0x40c94018 0 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07: IOMUXC_SNVS_GPIO_SNVS_04_DIG_GPIO13_IO07 { + pinmux = <0x40c9401c 5 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_snvs_lp_tamper04: IOMUXC_SNVS_GPIO_SNVS_04_DIG_SNVS_LP_TAMPER04 { + pinmux = <0x40c9401c 0 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08: IOMUXC_SNVS_GPIO_SNVS_05_DIG_GPIO13_IO08 { + pinmux = <0x40c94020 5 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_snvs_lp_tamper05: IOMUXC_SNVS_GPIO_SNVS_05_DIG_SNVS_LP_TAMPER05 { + pinmux = <0x40c94020 0 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09: IOMUXC_SNVS_GPIO_SNVS_06_DIG_GPIO13_IO09 { + pinmux = <0x40c94024 5 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_snvs_lp_tamper06: IOMUXC_SNVS_GPIO_SNVS_06_DIG_SNVS_LP_TAMPER06 { + pinmux = <0x40c94024 0 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10: IOMUXC_SNVS_GPIO_SNVS_07_DIG_GPIO13_IO10 { + pinmux = <0x40c94028 5 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_snvs_lp_tamper07: IOMUXC_SNVS_GPIO_SNVS_07_DIG_SNVS_LP_TAMPER07 { + pinmux = <0x40c94028 0 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11: IOMUXC_SNVS_GPIO_SNVS_08_DIG_GPIO13_IO11 { + pinmux = <0x40c9402c 5 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_snvs_lp_tamper08: IOMUXC_SNVS_GPIO_SNVS_08_DIG_SNVS_LP_TAMPER08 { + pinmux = <0x40c9402c 0 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12: IOMUXC_SNVS_GPIO_SNVS_09_DIG_GPIO13_IO12 { + pinmux = <0x40c94030 5 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_snvs_lp_tamper09: IOMUXC_SNVS_GPIO_SNVS_09_DIG_SNVS_LP_TAMPER09 { + pinmux = <0x40c94030 0 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_dig_src_reset_b: IOMUXC_SNVS_ONOFF_DIG_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x40c9403c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_gpio13_io01: IOMUXC_SNVS_PMIC_ON_REQ_DIG_GPIO13_IO01 { + pinmux = <0x40c94004 5 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_snvs_lp_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ { + pinmux = <0x40c94004 0 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_gpio13_io02: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_GPIO13_IO02 { + pinmux = <0x40c94008 5 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_pgmc_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_PGMC_PMIC_VSTBY_REQ { + pinmux = <0x40c94008 0 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_dig_src_por_b: IOMUXC_SNVS_POR_B_DIG_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x40c94038>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_dig_test_mode: IOMUXC_SNVS_TEST_MODE_DIG_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x40c94034>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_dig_gpio13_io00: IOMUXC_SNVS_WAKEUP_DIG_GPIO13_IO00 { + pinmux = <0x40c94000 5 0x0 0 0x40c94040>; + pin-snvs; + }; +}; + diff --git a/dts/nxp/nxp_imx/rt/mimxrt1173cvm8a-pinctrl.dtsi b/dts/nxp/nxp_imx/rt/mimxrt1173cvm8a-pinctrl.dtsi new file mode 100644 index 000000000..a15c2b93a --- /dev/null +++ b/dts/nxp/nxp_imx/rt/mimxrt1173cvm8a-pinctrl.dtsi @@ -0,0 +1,6212 @@ +/* + * Copyright 2024, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Note: File generated by gen_soc_headers.py + * from configuration data for MIMXRT1173CVM8A + */ + +/* + * SOC level pinctrl defintions + * These definitions define SOC level defaults for each pin, + * and select the pinmux for the pin. Pinmux entries are a tuple of: + * + * the mux_register and input_daisy reside in the IOMUXC peripheral, and + * the pinctrl driver will write the mux_mode and input_daisy values into + * each register, respectively. The config_register is used to configure + * the pin based on the devicetree properties set + */ + +&iomuxc { + /omit-if-no-ref/ iomuxc_gpio_ad_00_acmp1_in1: IOMUXC_GPIO_AD_00_ACMP1_IN1 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_can2_tx: IOMUXC_GPIO_AD_00_CAN2_TX { + pinmux = <0x400e810c 1 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_enet_1g_1588_event1_in: IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN { + pinmux = <0x400e810c 2 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexio2_flexio00: IOMUXC_GPIO_AD_00_FLEXIO2_FLEXIO00 { + pinmux = <0x400e810c 8 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexpwm1_pwm0_a: IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A { + pinmux = <0x400e810c 4 0x400e8500 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_flexspi2_b_ss1_b: IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B { + pinmux = <0x400e810c 9 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio8_io31: IOMUXC_GPIO_AD_00_GPIO8_IO31 { + pinmux = <0x400e810c 10 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpio_mux2_io31_cm7: IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31_CM7 { + pinmux = <0x400e810c 5 0x0 0 0x400e8350>; + pin-pue; + gpr = <0x400e40a4 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_gpt2_capture1: IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 { + pinmux = <0x400e810c 3 0x0 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_lpuart7_tx: IOMUXC_GPIO_AD_00_LPUART7_TX { + pinmux = <0x400e810c 6 0x400e8630 0 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_00_sim1_trxd: IOMUXC_GPIO_AD_00_SIM1_TRXD { + pinmux = <0x400e810c 0 0x400e869c 1 0x400e8350>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_acmp1_in2: IOMUXC_GPIO_AD_01_ACMP1_IN2 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_can2_rx: IOMUXC_GPIO_AD_01_CAN2_RX { + pinmux = <0x400e8110 1 0x400e849c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_enet_1g_1588_event1_out: IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT { + pinmux = <0x400e8110 2 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexio2_flexio01: IOMUXC_GPIO_AD_01_FLEXIO2_FLEXIO01 { + pinmux = <0x400e8110 8 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexpwm1_pwm0_b: IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B { + pinmux = <0x400e8110 4 0x400e850c 1 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_flexspi2_a_ss1_b: IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B { + pinmux = <0x400e8110 9 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio9_io00: IOMUXC_GPIO_AD_01_GPIO9_IO00 { + pinmux = <0x400e8110 10 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpio_mux3_io00_cm7: IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00_CM7 { + pinmux = <0x400e8110 5 0x0 0 0x400e8354>; + pin-pue; + gpr = <0x400e40a8 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_gpt2_capture2: IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 { + pinmux = <0x400e8110 3 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_lpuart7_rx: IOMUXC_GPIO_AD_01_LPUART7_RX { + pinmux = <0x400e8110 6 0x400e862c 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_01_sim1_clk: IOMUXC_GPIO_AD_01_SIM1_CLK { + pinmux = <0x400e8110 0 0x0 0 0x400e8354>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_acmp1_in3: IOMUXC_GPIO_AD_02_ACMP1_IN3 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_enet_1g_1588_event2_in: IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN { + pinmux = <0x400e8114 2 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexio2_flexio02: IOMUXC_GPIO_AD_02_FLEXIO2_FLEXIO02 { + pinmux = <0x400e8114 8 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_flexpwm1_pwm1_a: IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A { + pinmux = <0x400e8114 4 0x400e8504 1 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio9_io01: IOMUXC_GPIO_AD_02_GPIO9_IO01 { + pinmux = <0x400e8114 10 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpio_mux3_io01_cm7: IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01_CM7 { + pinmux = <0x400e8114 5 0x0 0 0x400e8358>; + pin-pue; + gpr = <0x400e40a8 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_gpt2_compare1: IOMUXC_GPIO_AD_02_GPT2_COMPARE1 { + pinmux = <0x400e8114 3 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart7_cts_b: IOMUXC_GPIO_AD_02_LPUART7_CTS_B { + pinmux = <0x400e8114 1 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_lpuart8_tx: IOMUXC_GPIO_AD_02_LPUART8_TX { + pinmux = <0x400e8114 6 0x400e8638 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_sim1_rst_b: IOMUXC_GPIO_AD_02_SIM1_RST_B { + pinmux = <0x400e8114 0 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_02_video_mux_ext_dcic1: IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e8114 9 0x0 0 0x400e8358>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_acmp1_in4: IOMUXC_GPIO_AD_03_ACMP1_IN4 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_enet_1g_1588_event2_out: IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT { + pinmux = <0x400e8118 2 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexio2_flexio03: IOMUXC_GPIO_AD_03_FLEXIO2_FLEXIO03 { + pinmux = <0x400e8118 8 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_flexpwm1_pwm1_b: IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B { + pinmux = <0x400e8118 4 0x400e8510 1 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio9_io02: IOMUXC_GPIO_AD_03_GPIO9_IO02 { + pinmux = <0x400e8118 10 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpio_mux3_io02_cm7: IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02_CM7 { + pinmux = <0x400e8118 5 0x0 0 0x400e835c>; + pin-pue; + gpr = <0x400e40a8 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_gpt2_compare2: IOMUXC_GPIO_AD_03_GPT2_COMPARE2 { + pinmux = <0x400e8118 3 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart7_rts_b: IOMUXC_GPIO_AD_03_LPUART7_RTS_B { + pinmux = <0x400e8118 1 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_lpuart8_rx: IOMUXC_GPIO_AD_03_LPUART8_RX { + pinmux = <0x400e8118 6 0x400e8634 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_sim1_sven: IOMUXC_GPIO_AD_03_SIM1_SVEN { + pinmux = <0x400e8118 0 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_03_video_mux_ext_dcic2: IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8118 9 0x0 0 0x400e835c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_acmp2_in1: IOMUXC_GPIO_AD_04_ACMP2_IN1 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_enet_1g_1588_event3_in: IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN { + pinmux = <0x400e811c 2 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexio2_flexio04: IOMUXC_GPIO_AD_04_FLEXIO2_FLEXIO04 { + pinmux = <0x400e811c 8 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_flexpwm1_pwm2_a: IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A { + pinmux = <0x400e811c 4 0x400e8508 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio9_io03: IOMUXC_GPIO_AD_04_GPIO9_IO03 { + pinmux = <0x400e811c 10 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpio_mux3_io03_cm7: IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03_CM7 { + pinmux = <0x400e811c 5 0x0 0 0x400e8360>; + pin-pue; + gpr = <0x400e40a8 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_gpt2_compare3: IOMUXC_GPIO_AD_04_GPT2_COMPARE3 { + pinmux = <0x400e811c 3 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_lpuart8_cts_b: IOMUXC_GPIO_AD_04_LPUART8_CTS_B { + pinmux = <0x400e811c 1 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_qtimer4_timer0: IOMUXC_GPIO_AD_04_QTIMER4_TIMER0 { + pinmux = <0x400e811c 9 0x400e8660 1 0x400e8360>; + pin-pue; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_sim1_pd: IOMUXC_GPIO_AD_04_SIM1_PD { + pinmux = <0x400e811c 0 0x400e86a0 1 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_04_wdog1_wdog_b: IOMUXC_GPIO_AD_04_WDOG1_WDOG_B { + pinmux = <0x400e811c 6 0x0 0 0x400e8360>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_acmp2_in2: IOMUXC_GPIO_AD_05_ACMP2_IN2 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_enet_1g_1588_event3_out: IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT { + pinmux = <0x400e8120 2 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexio2_flexio05: IOMUXC_GPIO_AD_05_FLEXIO2_FLEXIO05 { + pinmux = <0x400e8120 8 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_flexpwm1_pwm2_b: IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B { + pinmux = <0x400e8120 4 0x400e8514 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio9_io04: IOMUXC_GPIO_AD_05_GPIO9_IO04 { + pinmux = <0x400e8120 10 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpio_mux3_io04_cm7: IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04_CM7 { + pinmux = <0x400e8120 5 0x0 0 0x400e8364>; + pin-pue; + gpr = <0x400e40a8 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_gpt2_clk: IOMUXC_GPIO_AD_05_GPT2_CLK { + pinmux = <0x400e8120 3 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_lpuart8_rts_b: IOMUXC_GPIO_AD_05_LPUART8_RTS_B { + pinmux = <0x400e8120 1 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_qtimer4_timer1: IOMUXC_GPIO_AD_05_QTIMER4_TIMER1 { + pinmux = <0x400e8120 9 0x400e8664 1 0x400e8364>; + pin-pue; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_sim1_power_fail: IOMUXC_GPIO_AD_05_SIM1_POWER_FAIL { + pinmux = <0x400e8120 0 0x400e86a4 1 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_05_wdog2_wdog_b: IOMUXC_GPIO_AD_05_WDOG2_WDOG_B { + pinmux = <0x400e8120 6 0x0 0 0x400e8364>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_adc1_ch0a: IOMUXC_GPIO_AD_06_ADC1_CH0A { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_can1_tx: IOMUXC_GPIO_AD_06_CAN1_TX { + pinmux = <0x400e8124 1 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_enet_1588_event1_in: IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN { + pinmux = <0x400e8124 6 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexio2_flexio06: IOMUXC_GPIO_AD_06_FLEXIO2_FLEXIO06 { + pinmux = <0x400e8124 8 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_flexpwm1_pwm0_x: IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X { + pinmux = <0x400e8124 11 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio9_io05: IOMUXC_GPIO_AD_06_GPIO9_IO05 { + pinmux = <0x400e8124 10 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpio_mux3_io05_cm7: IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05_CM7 { + pinmux = <0x400e8124 5 0x0 0 0x400e8368>; + pin-pue; + gpr = <0x400e40a8 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_gpt3_capture1: IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 { + pinmux = <0x400e8124 3 0x400e8590 1 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_qtimer4_timer2: IOMUXC_GPIO_AD_06_QTIMER4_TIMER2 { + pinmux = <0x400e8124 9 0x400e8668 0 0x400e8368>; + pin-pue; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_sim2_trxd: IOMUXC_GPIO_AD_06_SIM2_TRXD { + pinmux = <0x400e8124 2 0x400e86a8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_usb_otg2_oc: IOMUXC_GPIO_AD_06_USB_OTG2_OC { + pinmux = <0x400e8124 0 0x400e86b8 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_06_video_mux_csi_data15: IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 { + pinmux = <0x400e8124 4 0x0 0 0x400e8368>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_adc1_ch0b: IOMUXC_GPIO_AD_07_ADC1_CH0B { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_can1_rx: IOMUXC_GPIO_AD_07_CAN1_RX { + pinmux = <0x400e8128 1 0x400e8498 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_enet_1588_event1_out: IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT { + pinmux = <0x400e8128 6 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexio2_flexio07: IOMUXC_GPIO_AD_07_FLEXIO2_FLEXIO07 { + pinmux = <0x400e8128 8 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_flexpwm1_pwm1_x: IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X { + pinmux = <0x400e8128 11 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio9_io06: IOMUXC_GPIO_AD_07_GPIO9_IO06 { + pinmux = <0x400e8128 10 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpio_mux3_io06_cm7: IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06_CM7 { + pinmux = <0x400e8128 5 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e40a8 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_gpt3_capture2: IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 { + pinmux = <0x400e8128 3 0x400e8594 1 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_qtimer4_timer3: IOMUXC_GPIO_AD_07_QTIMER4_TIMER3 { + pinmux = <0x400e8128 9 0x0 0 0x400e836c>; + pin-pue; + gpr = <0x400e403c 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_sim2_clk: IOMUXC_GPIO_AD_07_SIM2_CLK { + pinmux = <0x400e8128 2 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_usb_otg2_pwr: IOMUXC_GPIO_AD_07_USB_OTG2_PWR { + pinmux = <0x400e8128 0 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_07_video_mux_csi_data14: IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 { + pinmux = <0x400e8128 4 0x0 0 0x400e836c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_adc1_ch1a: IOMUXC_GPIO_AD_08_ADC1_CH1A { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_enet_1588_event2_in: IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN { + pinmux = <0x400e812c 6 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexio2_flexio08: IOMUXC_GPIO_AD_08_FLEXIO2_FLEXIO08 { + pinmux = <0x400e812c 8 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_flexpwm1_pwm2_x: IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X { + pinmux = <0x400e812c 11 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio9_io07: IOMUXC_GPIO_AD_08_GPIO9_IO07 { + pinmux = <0x400e812c 10 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpio_mux3_io07_cm7: IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07_CM7 { + pinmux = <0x400e812c 5 0x0 0 0x400e8370>; + pin-pue; + gpr = <0x400e40a8 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_gpt3_compare1: IOMUXC_GPIO_AD_08_GPT3_COMPARE1 { + pinmux = <0x400e812c 3 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_lpi2c1_scl: IOMUXC_GPIO_AD_08_LPI2C1_SCL { + pinmux = <0x400e812c 1 0x400e85ac 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_sim2_rst_b: IOMUXC_GPIO_AD_08_SIM2_RST_B { + pinmux = <0x400e812c 2 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_usbphy2_otg_id: IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID { + pinmux = <0x400e812c 0 0x400e86c4 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_08_video_mux_csi_data13: IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 { + pinmux = <0x400e812c 4 0x0 0 0x400e8370>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_adc1_ch1b: IOMUXC_GPIO_AD_09_ADC1_CH1B { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_enet_1588_event2_out: IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT { + pinmux = <0x400e8130 6 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexio2_flexio09: IOMUXC_GPIO_AD_09_FLEXIO2_FLEXIO09 { + pinmux = <0x400e8130 8 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_flexpwm1_pwm3_x: IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X { + pinmux = <0x400e8130 11 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio9_io08: IOMUXC_GPIO_AD_09_GPIO9_IO08 { + pinmux = <0x400e8130 10 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpio_mux3_io08_cm7: IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08_CM7 { + pinmux = <0x400e8130 5 0x0 0 0x400e8374>; + pin-pue; + gpr = <0x400e40a8 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_gpt3_compare2: IOMUXC_GPIO_AD_09_GPT3_COMPARE2 { + pinmux = <0x400e8130 3 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_lpi2c1_sda: IOMUXC_GPIO_AD_09_LPI2C1_SDA { + pinmux = <0x400e8130 1 0x400e85b0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_sim2_sven: IOMUXC_GPIO_AD_09_SIM2_SVEN { + pinmux = <0x400e8130 2 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_usbphy1_otg_id: IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID { + pinmux = <0x400e8130 0 0x400e86c0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_09_video_mux_csi_data12: IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 { + pinmux = <0x400e8130 4 0x0 0 0x400e8374>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_adc1_ch2a: IOMUXC_GPIO_AD_10_ADC1_CH2A { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_enet_1588_event3_in: IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN { + pinmux = <0x400e8134 6 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexio2_flexio10: IOMUXC_GPIO_AD_10_FLEXIO2_FLEXIO10 { + pinmux = <0x400e8134 8 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_flexpwm2_pwm0_x: IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X { + pinmux = <0x400e8134 11 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio9_io09: IOMUXC_GPIO_AD_10_GPIO9_IO09 { + pinmux = <0x400e8134 10 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpio_mux3_io09_cm7: IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09_CM7 { + pinmux = <0x400e8134 5 0x0 0 0x400e8378>; + pin-pue; + gpr = <0x400e40a8 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_gpt3_compare3: IOMUXC_GPIO_AD_10_GPT3_COMPARE3 { + pinmux = <0x400e8134 3 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_lpi2c1_scls: IOMUXC_GPIO_AD_10_LPI2C1_SCLS { + pinmux = <0x400e8134 1 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_sim2_pd: IOMUXC_GPIO_AD_10_SIM2_PD { + pinmux = <0x400e8134 2 0x400e86ac 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_usb_otg1_pwr: IOMUXC_GPIO_AD_10_USB_OTG1_PWR { + pinmux = <0x400e8134 0 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_10_video_mux_csi_data11: IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 { + pinmux = <0x400e8134 4 0x0 0 0x400e8378>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_adc1_ch2b: IOMUXC_GPIO_AD_11_ADC1_CH2B { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_enet_1588_event3_out: IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT { + pinmux = <0x400e8138 6 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexio2_flexio11: IOMUXC_GPIO_AD_11_FLEXIO2_FLEXIO11 { + pinmux = <0x400e8138 8 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_flexpwm2_pwm1_x: IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X { + pinmux = <0x400e8138 11 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio9_io10: IOMUXC_GPIO_AD_11_GPIO9_IO10 { + pinmux = <0x400e8138 10 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpio_mux3_io10_cm7: IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10_CM7 { + pinmux = <0x400e8138 5 0x0 0 0x400e837c>; + pin-pue; + gpr = <0x400e40a8 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_gpt3_clk: IOMUXC_GPIO_AD_11_GPT3_CLK { + pinmux = <0x400e8138 3 0x400e8598 1 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_lpi2c1_sdas: IOMUXC_GPIO_AD_11_LPI2C1_SDAS { + pinmux = <0x400e8138 1 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_sim2_power_fail: IOMUXC_GPIO_AD_11_SIM2_POWER_FAIL { + pinmux = <0x400e8138 2 0x400e86b0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_usb_otg1_oc: IOMUXC_GPIO_AD_11_USB_OTG1_OC { + pinmux = <0x400e8138 0 0x400e86bc 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_11_video_mux_csi_data10: IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 { + pinmux = <0x400e8138 4 0x0 0 0x400e837c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc1_ch3a: IOMUXC_GPIO_AD_12_ADC1_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_adc2_ch3a: IOMUXC_GPIO_AD_12_ADC2_CH3A { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_enet_tdata03: IOMUXC_GPIO_AD_12_ENET_TDATA03 { + pinmux = <0x400e813c 6 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_ewm_ewm_out_b: IOMUXC_GPIO_AD_12_EWM_EWM_OUT_B { + pinmux = <0x400e813c 9 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexio2_flexio12: IOMUXC_GPIO_AD_12_FLEXIO2_FLEXIO12 { + pinmux = <0x400e813c 8 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexpwm2_pwm2_x: IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X { + pinmux = <0x400e813c 11 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_flexspi1_b_data03: IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 { + pinmux = <0x400e813c 3 0x400e8570 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio9_io11: IOMUXC_GPIO_AD_12_GPIO9_IO11 { + pinmux = <0x400e813c 10 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpio_mux3_io11_cm7: IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11_CM7 { + pinmux = <0x400e813c 5 0x0 0 0x400e8380>; + pin-pue; + gpr = <0x400e40a8 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_gpt1_capture1: IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 { + pinmux = <0x400e813c 2 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_lpi2c1_hreq: IOMUXC_GPIO_AD_12_LPI2C1_HREQ { + pinmux = <0x400e813c 1 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_spdif_lock: IOMUXC_GPIO_AD_12_SPDIF_LOCK { + pinmux = <0x400e813c 0 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_12_video_mux_csi_pixclk: IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK { + pinmux = <0x400e813c 4 0x0 0 0x400e8380>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc1_ch3b: IOMUXC_GPIO_AD_13_ADC1_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_adc2_ch3b: IOMUXC_GPIO_AD_13_ADC2_CH3B { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_enet_tdata02: IOMUXC_GPIO_AD_13_ENET_TDATA02 { + pinmux = <0x400e8140 6 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexio2_flexio13: IOMUXC_GPIO_AD_13_FLEXIO2_FLEXIO13 { + pinmux = <0x400e8140 8 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexpwm2_pwm3_x: IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X { + pinmux = <0x400e8140 11 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_flexspi1_b_data02: IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 { + pinmux = <0x400e8140 3 0x400e856c 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio9_io12: IOMUXC_GPIO_AD_13_GPIO9_IO12 { + pinmux = <0x400e8140 10 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpio_mux3_io12_cm7: IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12_CM7 { + pinmux = <0x400e8140 5 0x0 0 0x400e8384>; + pin-pue; + gpr = <0x400e40a8 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_gpt1_capture2: IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 { + pinmux = <0x400e8140 2 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_pit1_trigger00: IOMUXC_GPIO_AD_13_PIT1_TRIGGER00 { + pinmux = <0x400e8140 1 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_spdif_sr_clk: IOMUXC_GPIO_AD_13_SPDIF_SR_CLK { + pinmux = <0x400e8140 0 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_13_video_mux_csi_mclk: IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK { + pinmux = <0x400e8140 4 0x0 0 0x400e8384>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc1_ch4a: IOMUXC_GPIO_AD_14_ADC1_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_adc2_ch4a: IOMUXC_GPIO_AD_14_ADC2_CH4A { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_ccm_enet_ref_clk_25m: IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8144 9 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_enet_rx_clk: IOMUXC_GPIO_AD_14_ENET_RX_CLK { + pinmux = <0x400e8144 6 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexio2_flexio14: IOMUXC_GPIO_AD_14_FLEXIO2_FLEXIO14 { + pinmux = <0x400e8144 8 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexpwm3_pwm0_x: IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X { + pinmux = <0x400e8144 11 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_flexspi1_b_data01: IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 { + pinmux = <0x400e8144 3 0x400e8568 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio9_io13: IOMUXC_GPIO_AD_14_GPIO9_IO13 { + pinmux = <0x400e8144 10 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpio_mux3_io13_cm7: IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13_CM7 { + pinmux = <0x400e8144 5 0x0 0 0x400e8388>; + pin-pue; + gpr = <0x400e40a8 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_gpt1_compare1: IOMUXC_GPIO_AD_14_GPT1_COMPARE1 { + pinmux = <0x400e8144 2 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_spdif_ext_clk: IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK { + pinmux = <0x400e8144 0 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_14_video_mux_csi_vsync: IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC { + pinmux = <0x400e8144 4 0x0 0 0x400e8388>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc1_ch4b: IOMUXC_GPIO_AD_15_ADC1_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_adc2_ch4b: IOMUXC_GPIO_AD_15_ADC2_CH4B { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_enet_tx_er: IOMUXC_GPIO_AD_15_ENET_TX_ER { + pinmux = <0x400e8148 6 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexio2_flexio15: IOMUXC_GPIO_AD_15_FLEXIO2_FLEXIO15 { + pinmux = <0x400e8148 8 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexpwm3_pwm1_x: IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X { + pinmux = <0x400e8148 11 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_flexspi1_b_data00: IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 { + pinmux = <0x400e8148 3 0x400e8564 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio9_io14: IOMUXC_GPIO_AD_15_GPIO9_IO14 { + pinmux = <0x400e8148 10 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpio_mux3_io14_cm7: IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14_CM7 { + pinmux = <0x400e8148 5 0x0 0 0x400e838c>; + pin-pue; + gpr = <0x400e40a8 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_gpt1_compare2: IOMUXC_GPIO_AD_15_GPT1_COMPARE2 { + pinmux = <0x400e8148 2 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_lpuart10_tx: IOMUXC_GPIO_AD_15_LPUART10_TX { + pinmux = <0x400e8148 1 0x400e8628 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_spdif_in: IOMUXC_GPIO_AD_15_SPDIF_IN { + pinmux = <0x400e8148 0 0x400e86b4 1 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_15_video_mux_csi_hsync: IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC { + pinmux = <0x400e8148 4 0x0 0 0x400e838c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc1_ch5a: IOMUXC_GPIO_AD_16_ADC1_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_adc2_ch5a: IOMUXC_GPIO_AD_16_ADC2_CH5A { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_1g_mdc: IOMUXC_GPIO_AD_16_ENET_1G_MDC { + pinmux = <0x400e814c 9 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_enet_rdata03: IOMUXC_GPIO_AD_16_ENET_RDATA03 { + pinmux = <0x400e814c 6 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexio2_flexio16: IOMUXC_GPIO_AD_16_FLEXIO2_FLEXIO16 { + pinmux = <0x400e814c 8 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexpwm3_pwm2_x: IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X { + pinmux = <0x400e814c 11 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_flexspi1_b_sclk: IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK { + pinmux = <0x400e814c 3 0x400e8578 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio9_io15: IOMUXC_GPIO_AD_16_GPIO9_IO15 { + pinmux = <0x400e814c 10 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpio_mux3_io15_cm7: IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15_CM7 { + pinmux = <0x400e814c 5 0x0 0 0x400e8390>; + pin-pue; + gpr = <0x400e40a8 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_gpt1_compare3: IOMUXC_GPIO_AD_16_GPT1_COMPARE3 { + pinmux = <0x400e814c 2 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_lpuart10_rx: IOMUXC_GPIO_AD_16_LPUART10_RX { + pinmux = <0x400e814c 1 0x400e8624 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_spdif_out: IOMUXC_GPIO_AD_16_SPDIF_OUT { + pinmux = <0x400e814c 0 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_16_video_mux_csi_data09: IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 { + pinmux = <0x400e814c 4 0x0 0 0x400e8390>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_acmp1_cmpo: IOMUXC_GPIO_AD_17_ACMP1_CMPO { + pinmux = <0x400e8150 1 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc1_ch5b: IOMUXC_GPIO_AD_17_ADC1_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_adc2_ch5b: IOMUXC_GPIO_AD_17_ADC2_CH5B { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_1g_mdio: IOMUXC_GPIO_AD_17_ENET_1G_MDIO { + pinmux = <0x400e8150 9 0x400e84c8 2 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_enet_rdata02: IOMUXC_GPIO_AD_17_ENET_RDATA02 { + pinmux = <0x400e8150 6 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexio2_flexio17: IOMUXC_GPIO_AD_17_FLEXIO2_FLEXIO17 { + pinmux = <0x400e8150 8 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexpwm3_pwm3_x: IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X { + pinmux = <0x400e8150 11 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_flexspi1_a_dqs: IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS { + pinmux = <0x400e8150 3 0x400e8550 1 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio9_io16: IOMUXC_GPIO_AD_17_GPIO9_IO16 { + pinmux = <0x400e8150 10 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpio_mux3_io16_cm7: IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16_CM7 { + pinmux = <0x400e8150 5 0x0 0 0x400e8394>; + pin-pue; + gpr = <0x400e40ac 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_gpt1_clk: IOMUXC_GPIO_AD_17_GPT1_CLK { + pinmux = <0x400e8150 2 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_sai1_mclk: IOMUXC_GPIO_AD_17_SAI1_MCLK { + pinmux = <0x400e8150 0 0x400e866c 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_17_video_mux_csi_data08: IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 { + pinmux = <0x400e8150 4 0x0 0 0x400e8394>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_acmp2_cmpo: IOMUXC_GPIO_AD_18_ACMP2_CMPO { + pinmux = <0x400e8154 1 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_adc2_ch0a: IOMUXC_GPIO_AD_18_ADC2_CH0A { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_enet_crs: IOMUXC_GPIO_AD_18_ENET_CRS { + pinmux = <0x400e8154 6 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexio2_flexio18: IOMUXC_GPIO_AD_18_FLEXIO2_FLEXIO18 { + pinmux = <0x400e8154 8 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexpwm4_pwm0_x: IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X { + pinmux = <0x400e8154 11 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_flexspi1_a_ss0_b: IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B { + pinmux = <0x400e8154 3 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio9_io17: IOMUXC_GPIO_AD_18_GPIO9_IO17 { + pinmux = <0x400e8154 10 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_gpio_mux3_io17_cm7: IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17_CM7 { + pinmux = <0x400e8154 5 0x0 0 0x400e8398>; + pin-pue; + gpr = <0x400e40ac 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpi2c2_scl: IOMUXC_GPIO_AD_18_LPI2C2_SCL { + pinmux = <0x400e8154 9 0x400e85b4 1 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_lpspi1_pcs1: IOMUXC_GPIO_AD_18_LPSPI1_PCS1 { + pinmux = <0x400e8154 2 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_sai1_rx_sync: IOMUXC_GPIO_AD_18_SAI1_RX_SYNC { + pinmux = <0x400e8154 0 0x400e8678 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_18_video_mux_csi_data07: IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 { + pinmux = <0x400e8154 4 0x0 0 0x400e8398>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_acmp3_cmpo: IOMUXC_GPIO_AD_19_ACMP3_CMPO { + pinmux = <0x400e8158 1 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_adc2_ch0b: IOMUXC_GPIO_AD_19_ADC2_CH0B { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_enet_col: IOMUXC_GPIO_AD_19_ENET_COL { + pinmux = <0x400e8158 6 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexio2_flexio19: IOMUXC_GPIO_AD_19_FLEXIO2_FLEXIO19 { + pinmux = <0x400e8158 8 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexpwm4_pwm1_x: IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X { + pinmux = <0x400e8158 11 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_flexspi1_a_sclk: IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK { + pinmux = <0x400e8158 3 0x400e8574 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio9_io18: IOMUXC_GPIO_AD_19_GPIO9_IO18 { + pinmux = <0x400e8158 10 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_gpio_mux3_io18_cm7: IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18_CM7 { + pinmux = <0x400e8158 5 0x0 0 0x400e839c>; + pin-pue; + gpr = <0x400e40ac 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpi2c2_sda: IOMUXC_GPIO_AD_19_LPI2C2_SDA { + pinmux = <0x400e8158 9 0x400e85b8 1 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_lpspi1_pcs2: IOMUXC_GPIO_AD_19_LPSPI1_PCS2 { + pinmux = <0x400e8158 2 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_sai1_rx_bclk: IOMUXC_GPIO_AD_19_SAI1_RX_BCLK { + pinmux = <0x400e8158 0 0x400e8670 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_19_video_mux_csi_data06: IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 { + pinmux = <0x400e8158 4 0x0 0 0x400e839c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_acmp4_cmpo: IOMUXC_GPIO_AD_20_ACMP4_CMPO { + pinmux = <0x400e815c 1 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_adc2_ch1a: IOMUXC_GPIO_AD_20_ADC2_CH1A { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexio2_flexio20: IOMUXC_GPIO_AD_20_FLEXIO2_FLEXIO20 { + pinmux = <0x400e815c 8 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexpwm4_pwm2_x: IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X { + pinmux = <0x400e815c 11 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_flexspi1_a_data00: IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 { + pinmux = <0x400e815c 3 0x400e8554 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio9_io19: IOMUXC_GPIO_AD_20_GPIO9_IO19 { + pinmux = <0x400e815c 10 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_gpio_mux3_io19_cm7: IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19_CM7 { + pinmux = <0x400e815c 5 0x0 0 0x400e83a0>; + pin-pue; + gpr = <0x400e40ac 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_kpp_row07: IOMUXC_GPIO_AD_20_KPP_ROW07 { + pinmux = <0x400e815c 6 0x400e85a8 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_lpspi1_pcs3: IOMUXC_GPIO_AD_20_LPSPI1_PCS3 { + pinmux = <0x400e815c 2 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_sai1_rx_data00: IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 { + pinmux = <0x400e815c 0 0x400e8674 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_20_video_mux_csi_data05: IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 { + pinmux = <0x400e815c 4 0x0 0 0x400e83a0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_adc2_ch1b: IOMUXC_GPIO_AD_21_ADC2_CH1B { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexio2_flexio21: IOMUXC_GPIO_AD_21_FLEXIO2_FLEXIO21 { + pinmux = <0x400e8160 8 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexpwm4_pwm3_x: IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X { + pinmux = <0x400e8160 11 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_flexspi1_a_data01: IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 { + pinmux = <0x400e8160 3 0x400e8558 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio9_io20: IOMUXC_GPIO_AD_21_GPIO9_IO20 { + pinmux = <0x400e8160 10 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_gpio_mux3_io20_cm7: IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20_CM7 { + pinmux = <0x400e8160 5 0x0 0 0x400e83a4>; + pin-pue; + gpr = <0x400e40ac 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_kpp_col07: IOMUXC_GPIO_AD_21_KPP_COL07 { + pinmux = <0x400e8160 6 0x400e85a0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_lpspi2_pcs1: IOMUXC_GPIO_AD_21_LPSPI2_PCS1 { + pinmux = <0x400e8160 2 0x400e85e0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_sai1_tx_data00: IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 { + pinmux = <0x400e8160 0 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_21_video_mux_csi_data04: IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 { + pinmux = <0x400e8160 4 0x0 0 0x400e83a4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_adc2_ch2a: IOMUXC_GPIO_AD_22_ADC2_CH2A { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexio2_flexio22: IOMUXC_GPIO_AD_22_FLEXIO2_FLEXIO22 { + pinmux = <0x400e8164 8 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_flexspi1_a_data02: IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 { + pinmux = <0x400e8164 3 0x400e855c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio9_io21: IOMUXC_GPIO_AD_22_GPIO9_IO21 { + pinmux = <0x400e8164 10 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_gpio_mux3_io21_cm7: IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21_CM7 { + pinmux = <0x400e8164 5 0x0 0 0x400e83a8>; + pin-pue; + gpr = <0x400e40ac 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_kpp_row06: IOMUXC_GPIO_AD_22_KPP_ROW06 { + pinmux = <0x400e8164 6 0x400e85a4 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_lpspi2_pcs2: IOMUXC_GPIO_AD_22_LPSPI2_PCS2 { + pinmux = <0x400e8164 2 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_sai1_tx_bclk: IOMUXC_GPIO_AD_22_SAI1_TX_BCLK { + pinmux = <0x400e8164 0 0x400e867c 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_22_video_mux_csi_data03: IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 { + pinmux = <0x400e8164 4 0x0 0 0x400e83a8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_adc2_ch2b: IOMUXC_GPIO_AD_23_ADC2_CH2B { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexio2_flexio23: IOMUXC_GPIO_AD_23_FLEXIO2_FLEXIO23 { + pinmux = <0x400e8168 8 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_flexspi1_a_data03: IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 { + pinmux = <0x400e8168 3 0x400e8560 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio9_io22: IOMUXC_GPIO_AD_23_GPIO9_IO22 { + pinmux = <0x400e8168 10 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_gpio_mux3_io22_cm7: IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22_CM7 { + pinmux = <0x400e8168 5 0x0 0 0x400e83ac>; + pin-pue; + gpr = <0x400e40ac 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_kpp_col06: IOMUXC_GPIO_AD_23_KPP_COL06 { + pinmux = <0x400e8168 6 0x400e859c 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_lpspi2_pcs3: IOMUXC_GPIO_AD_23_LPSPI2_PCS3 { + pinmux = <0x400e8168 2 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_sai1_tx_sync: IOMUXC_GPIO_AD_23_SAI1_TX_SYNC { + pinmux = <0x400e8168 0 0x400e8680 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_23_video_mux_csi_data02: IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 { + pinmux = <0x400e8168 4 0x0 0 0x400e83ac>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_adc2_ch6a: IOMUXC_GPIO_AD_24_ADC2_CH6A { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_enet_rx_en: IOMUXC_GPIO_AD_24_ENET_RX_EN { + pinmux = <0x400e816c 3 0x400e84b8 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexio2_flexio24: IOMUXC_GPIO_AD_24_FLEXIO2_FLEXIO24 { + pinmux = <0x400e816c 8 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_flexpwm2_pwm0_a: IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A { + pinmux = <0x400e816c 4 0x400e8518 1 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio9_io23: IOMUXC_GPIO_AD_24_GPIO9_IO23 { + pinmux = <0x400e816c 10 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_gpio_mux3_io23_cm7: IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23_CM7 { + pinmux = <0x400e816c 5 0x0 0 0x400e83b0>; + pin-pue; + gpr = <0x400e40ac 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_kpp_row05: IOMUXC_GPIO_AD_24_KPP_ROW05 { + pinmux = <0x400e816c 6 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpi2c4_scl: IOMUXC_GPIO_AD_24_LPI2C4_SCL { + pinmux = <0x400e816c 9 0x400e85c4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpspi2_sck: IOMUXC_GPIO_AD_24_LPSPI2_SCK { + pinmux = <0x400e816c 1 0x400e85e4 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_lpuart1_tx: IOMUXC_GPIO_AD_24_LPUART1_TX { + pinmux = <0x400e816c 0 0x400e8620 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_24_video_mux_csi_data00: IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 { + pinmux = <0x400e816c 2 0x0 0 0x400e83b0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_adc2_ch6b: IOMUXC_GPIO_AD_25_ADC2_CH6B { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_enet_rx_er: IOMUXC_GPIO_AD_25_ENET_RX_ER { + pinmux = <0x400e8170 3 0x400e84bc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexio2_flexio25: IOMUXC_GPIO_AD_25_FLEXIO2_FLEXIO25 { + pinmux = <0x400e8170 8 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_flexpwm2_pwm0_b: IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B { + pinmux = <0x400e8170 4 0x400e8524 1 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio9_io24: IOMUXC_GPIO_AD_25_GPIO9_IO24 { + pinmux = <0x400e8170 10 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_gpio_mux3_io24_cm7: IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24_CM7 { + pinmux = <0x400e8170 5 0x0 0 0x400e83b4>; + pin-pue; + gpr = <0x400e40ac 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_kpp_col05: IOMUXC_GPIO_AD_25_KPP_COL05 { + pinmux = <0x400e8170 6 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpi2c4_sda: IOMUXC_GPIO_AD_25_LPI2C4_SDA { + pinmux = <0x400e8170 9 0x400e85c8 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpspi2_pcs0: IOMUXC_GPIO_AD_25_LPSPI2_PCS0 { + pinmux = <0x400e8170 1 0x400e85dc 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_lpuart1_rx: IOMUXC_GPIO_AD_25_LPUART1_RX { + pinmux = <0x400e8170 0 0x400e861c 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_25_video_mux_csi_data01: IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 { + pinmux = <0x400e8170 2 0x0 0 0x400e83b4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_acmp2_in3: IOMUXC_GPIO_AD_26_ACMP2_IN3 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_enet_rdata00: IOMUXC_GPIO_AD_26_ENET_RDATA00 { + pinmux = <0x400e8174 3 0x400e84b0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexio2_flexio26: IOMUXC_GPIO_AD_26_FLEXIO2_FLEXIO26 { + pinmux = <0x400e8174 8 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_flexpwm2_pwm1_a: IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A { + pinmux = <0x400e8174 4 0x400e851c 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio9_io25: IOMUXC_GPIO_AD_26_GPIO9_IO25 { + pinmux = <0x400e8174 10 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_gpio_mux3_io25_cm7: IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25_CM7 { + pinmux = <0x400e8174 5 0x0 0 0x400e83b8>; + pin-pue; + gpr = <0x400e40ac 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_kpp_row04: IOMUXC_GPIO_AD_26_KPP_ROW04 { + pinmux = <0x400e8174 6 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpspi2_sdo: IOMUXC_GPIO_AD_26_LPSPI2_SDO { + pinmux = <0x400e8174 1 0x400e85ec 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_lpuart1_cts_b: IOMUXC_GPIO_AD_26_LPUART1_CTS_B { + pinmux = <0x400e8174 0 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_semc_csx01: IOMUXC_GPIO_AD_26_SEMC_CSX01 { + pinmux = <0x400e8174 2 0x0 0 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_26_usdhc2_cd_b: IOMUXC_GPIO_AD_26_USDHC2_CD_B { + pinmux = <0x400e8174 11 0x400e86d0 1 0x400e83b8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_acmp2_in4: IOMUXC_GPIO_AD_27_ACMP2_IN4 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_enet_rdata01: IOMUXC_GPIO_AD_27_ENET_RDATA01 { + pinmux = <0x400e8178 3 0x400e84b4 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexio2_flexio27: IOMUXC_GPIO_AD_27_FLEXIO2_FLEXIO27 { + pinmux = <0x400e8178 8 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_flexpwm2_pwm1_b: IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B { + pinmux = <0x400e8178 4 0x400e8528 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio9_io26: IOMUXC_GPIO_AD_27_GPIO9_IO26 { + pinmux = <0x400e8178 10 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_gpio_mux3_io26_cm7: IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26_CM7 { + pinmux = <0x400e8178 5 0x0 0 0x400e83bc>; + pin-pue; + gpr = <0x400e40ac 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_kpp_col04: IOMUXC_GPIO_AD_27_KPP_COL04 { + pinmux = <0x400e8178 6 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpspi2_sdi: IOMUXC_GPIO_AD_27_LPSPI2_SDI { + pinmux = <0x400e8178 1 0x400e85e8 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_lpuart1_rts_b: IOMUXC_GPIO_AD_27_LPUART1_RTS_B { + pinmux = <0x400e8178 0 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_semc_csx02: IOMUXC_GPIO_AD_27_SEMC_CSX02 { + pinmux = <0x400e8178 2 0x0 0 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_27_usdhc2_wp: IOMUXC_GPIO_AD_27_USDHC2_WP { + pinmux = <0x400e8178 11 0x400e86d4 1 0x400e83bc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_acmp3_in1: IOMUXC_GPIO_AD_28_ACMP3_IN1 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_enet_tx_en: IOMUXC_GPIO_AD_28_ENET_TX_EN { + pinmux = <0x400e817c 3 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexio2_flexio28: IOMUXC_GPIO_AD_28_FLEXIO2_FLEXIO28 { + pinmux = <0x400e817c 8 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_flexpwm2_pwm2_a: IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A { + pinmux = <0x400e817c 4 0x400e8520 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio9_io27: IOMUXC_GPIO_AD_28_GPIO9_IO27 { + pinmux = <0x400e817c 10 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_gpio_mux3_io27_cm7: IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27_CM7 { + pinmux = <0x400e817c 5 0x0 0 0x400e83c0>; + pin-pue; + gpr = <0x400e40ac 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_kpp_row03: IOMUXC_GPIO_AD_28_KPP_ROW03 { + pinmux = <0x400e817c 6 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpspi1_sck: IOMUXC_GPIO_AD_28_LPSPI1_SCK { + pinmux = <0x400e817c 0 0x400e85d0 1 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_lpuart5_tx: IOMUXC_GPIO_AD_28_LPUART5_TX { + pinmux = <0x400e817c 1 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_semc_csx03: IOMUXC_GPIO_AD_28_SEMC_CSX03 { + pinmux = <0x400e817c 2 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_usdhc2_vselect: IOMUXC_GPIO_AD_28_USDHC2_VSELECT { + pinmux = <0x400e817c 11 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_28_video_mux_ext_dcic1: IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e817c 9 0x0 0 0x400e83c0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_acmp3_in2: IOMUXC_GPIO_AD_29_ACMP3_IN2 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_ref_clk: IOMUXC_GPIO_AD_29_ENET_REF_CLK { + pinmux = <0x400e8180 2 0x400e84a8 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_enet_tx_clk: IOMUXC_GPIO_AD_29_ENET_TX_CLK { + pinmux = <0x400e8180 3 0x400e84c0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexio2_flexio29: IOMUXC_GPIO_AD_29_FLEXIO2_FLEXIO29 { + pinmux = <0x400e8180 8 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_flexpwm2_pwm2_b: IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B { + pinmux = <0x400e8180 4 0x400e852c 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio9_io28: IOMUXC_GPIO_AD_29_GPIO9_IO28 { + pinmux = <0x400e8180 10 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_gpio_mux3_io28_cm7: IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28_CM7 { + pinmux = <0x400e8180 5 0x0 0 0x400e83c4>; + pin-pue; + gpr = <0x400e40ac 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_kpp_col03: IOMUXC_GPIO_AD_29_KPP_COL03 { + pinmux = <0x400e8180 6 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpspi1_pcs0: IOMUXC_GPIO_AD_29_LPSPI1_PCS0 { + pinmux = <0x400e8180 0 0x400e85cc 1 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_lpuart5_rx: IOMUXC_GPIO_AD_29_LPUART5_RX { + pinmux = <0x400e8180 1 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_usdhc2_reset_b: IOMUXC_GPIO_AD_29_USDHC2_RESET_B { + pinmux = <0x400e8180 11 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_29_video_mux_ext_dcic2: IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8180 9 0x0 0 0x400e83c4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_acmp3_in3: IOMUXC_GPIO_AD_30_ACMP3_IN3 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_can2_tx: IOMUXC_GPIO_AD_30_CAN2_TX { + pinmux = <0x400e8184 2 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_enet_tdata00: IOMUXC_GPIO_AD_30_ENET_TDATA00 { + pinmux = <0x400e8184 3 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_flexio2_flexio30: IOMUXC_GPIO_AD_30_FLEXIO2_FLEXIO30 { + pinmux = <0x400e8184 8 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio9_io29: IOMUXC_GPIO_AD_30_GPIO9_IO29 { + pinmux = <0x400e8184 10 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_gpio_mux3_io29_cm7: IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29_CM7 { + pinmux = <0x400e8184 5 0x0 0 0x400e83c8>; + pin-pue; + gpr = <0x400e40ac 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_kpp_row02: IOMUXC_GPIO_AD_30_KPP_ROW02 { + pinmux = <0x400e8184 6 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpspi1_sdo: IOMUXC_GPIO_AD_30_LPSPI1_SDO { + pinmux = <0x400e8184 0 0x400e85d8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_lpuart3_tx: IOMUXC_GPIO_AD_30_LPUART3_TX { + pinmux = <0x400e8184 4 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_usb_otg2_oc: IOMUXC_GPIO_AD_30_USB_OTG2_OC { + pinmux = <0x400e8184 1 0x400e86b8 1 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_30_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_AD_30_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e8184 9 0x0 0 0x400e83c8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_acmp3_in4: IOMUXC_GPIO_AD_31_ACMP3_IN4 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_can2_rx: IOMUXC_GPIO_AD_31_CAN2_RX { + pinmux = <0x400e8188 2 0x400e849c 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_enet_tdata01: IOMUXC_GPIO_AD_31_ENET_TDATA01 { + pinmux = <0x400e8188 3 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_flexio2_flexio31: IOMUXC_GPIO_AD_31_FLEXIO2_FLEXIO31 { + pinmux = <0x400e8188 8 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio9_io30: IOMUXC_GPIO_AD_31_GPIO9_IO30 { + pinmux = <0x400e8188 10 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_gpio_mux3_io30_cm7: IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30_CM7 { + pinmux = <0x400e8188 5 0x0 0 0x400e83cc>; + pin-pue; + gpr = <0x400e40ac 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_kpp_col02: IOMUXC_GPIO_AD_31_KPP_COL02 { + pinmux = <0x400e8188 6 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpspi1_sdi: IOMUXC_GPIO_AD_31_LPSPI1_SDI { + pinmux = <0x400e8188 0 0x400e85d4 1 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_lpuart3_rx: IOMUXC_GPIO_AD_31_LPUART3_RX { + pinmux = <0x400e8188 4 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_usb_otg2_pwr: IOMUXC_GPIO_AD_31_USB_OTG2_PWR { + pinmux = <0x400e8188 1 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_31_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_AD_31_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8188 9 0x0 0 0x400e83cc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_acmp4_in1: IOMUXC_GPIO_AD_32_ACMP4_IN1 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_1g_mdc: IOMUXC_GPIO_AD_32_ENET_1G_MDC { + pinmux = <0x400e818c 9 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_enet_mdc: IOMUXC_GPIO_AD_32_ENET_MDC { + pinmux = <0x400e818c 3 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio9_io31: IOMUXC_GPIO_AD_32_GPIO9_IO31 { + pinmux = <0x400e818c 10 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_gpio_mux3_io31_cm7: IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31_CM7 { + pinmux = <0x400e818c 5 0x0 0 0x400e83d0>; + pin-pue; + gpr = <0x400e40ac 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_kpp_row01: IOMUXC_GPIO_AD_32_KPP_ROW01 { + pinmux = <0x400e818c 6 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpi2c1_scl: IOMUXC_GPIO_AD_32_LPI2C1_SCL { + pinmux = <0x400e818c 0 0x400e85ac 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_lpuart10_tx: IOMUXC_GPIO_AD_32_LPUART10_TX { + pinmux = <0x400e818c 8 0x400e8628 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_pgmc_pmic_ready: IOMUXC_GPIO_AD_32_PGMC_PMIC_READY { + pinmux = <0x400e818c 2 0x0 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usbphy2_otg_id: IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID { + pinmux = <0x400e818c 1 0x400e86c4 1 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_32_usdhc1_cd_b: IOMUXC_GPIO_AD_32_USDHC1_CD_B { + pinmux = <0x400e818c 4 0x400e86c8 0 0x400e83d0>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_acmp4_in2: IOMUXC_GPIO_AD_33_ACMP4_IN2 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_1g_mdio: IOMUXC_GPIO_AD_33_ENET_1G_MDIO { + pinmux = <0x400e8190 9 0x400e84c8 3 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_enet_mdio: IOMUXC_GPIO_AD_33_ENET_MDIO { + pinmux = <0x400e8190 3 0x400e84ac 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio10_io00: IOMUXC_GPIO_AD_33_GPIO10_IO00 { + pinmux = <0x400e8190 10 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_gpio_mux4_io00: IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 { + pinmux = <0x400e8190 5 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_kpp_col01: IOMUXC_GPIO_AD_33_KPP_COL01 { + pinmux = <0x400e8190 6 0x0 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpi2c1_sda: IOMUXC_GPIO_AD_33_LPI2C1_SDA { + pinmux = <0x400e8190 0 0x400e85b0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_lpuart10_rx: IOMUXC_GPIO_AD_33_LPUART10_RX { + pinmux = <0x400e8190 8 0x400e8624 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usbphy1_otg_id: IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID { + pinmux = <0x400e8190 1 0x400e86c0 1 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_usdhc1_wp: IOMUXC_GPIO_AD_33_USDHC1_WP { + pinmux = <0x400e8190 4 0x400e86cc 0 0x400e83d4>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_in17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_IN17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_33_xbar1_xbar_inout17: IOMUXC_GPIO_AD_33_XBAR1_XBAR_INOUT17 { + pinmux = <0x400e8190 2 0x0 0 0x400e83d4>; + pin-pue; + gpr = <0x400e4050 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_acmp4_in3: IOMUXC_GPIO_AD_34_ACMP4_IN3 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN { + pinmux = <0x400e8194 3 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_enet_1g_1588_event0_in: IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN { + pinmux = <0x400e8194 0 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio10_io01: IOMUXC_GPIO_AD_34_GPIO10_IO01 { + pinmux = <0x400e8194 10 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_gpio_mux4_io01: IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 { + pinmux = <0x400e8194 5 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_kpp_row00: IOMUXC_GPIO_AD_34_KPP_ROW00 { + pinmux = <0x400e8194 6 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_lpuart10_cts_b: IOMUXC_GPIO_AD_34_LPUART10_CTS_B { + pinmux = <0x400e8194 8 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usb_otg1_pwr: IOMUXC_GPIO_AD_34_USB_OTG1_PWR { + pinmux = <0x400e8194 1 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_usdhc1_vselect: IOMUXC_GPIO_AD_34_USDHC1_VSELECT { + pinmux = <0x400e8194 4 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_wdog1_wdog_any: IOMUXC_GPIO_AD_34_WDOG1_WDOG_ANY { + pinmux = <0x400e8194 9 0x0 0 0x400e83d8>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_in18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_IN18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_34_xbar1_xbar_inout18: IOMUXC_GPIO_AD_34_XBAR1_XBAR_INOUT18 { + pinmux = <0x400e8194 2 0x0 0 0x400e83d8>; + pin-pue; + gpr = <0x400e4050 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_acmp4_in4: IOMUXC_GPIO_AD_35_ACMP4_IN4 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT { + pinmux = <0x400e8198 3 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_enet_1g_1588_event0_out: IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT { + pinmux = <0x400e8198 0 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_flexspi1_b_ss1_b: IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B { + pinmux = <0x400e8198 9 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio10_io02: IOMUXC_GPIO_AD_35_GPIO10_IO02 { + pinmux = <0x400e8198 10 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_gpio_mux4_io02: IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 { + pinmux = <0x400e8198 5 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_kpp_col00: IOMUXC_GPIO_AD_35_KPP_COL00 { + pinmux = <0x400e8198 6 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_lpuart10_rts_b: IOMUXC_GPIO_AD_35_LPUART10_RTS_B { + pinmux = <0x400e8198 8 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usb_otg1_oc: IOMUXC_GPIO_AD_35_USB_OTG1_OC { + pinmux = <0x400e8198 1 0x400e86bc 1 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_usdhc1_reset_b: IOMUXC_GPIO_AD_35_USDHC1_RESET_B { + pinmux = <0x400e8198 4 0x0 0 0x400e83dc>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_in19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_IN19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_ad_35_xbar1_xbar_inout19: IOMUXC_GPIO_AD_35_XBAR1_XBAR_INOUT19 { + pinmux = <0x400e8198 2 0x0 0 0x400e83dc>; + pin-pue; + gpr = <0x400e4050 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_enet_1g_rx_en: IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN { + pinmux = <0x400e81e4 1 0x400e84e0 2 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio10_io21: IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 { + pinmux = <0x400e81e4 10 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_gpio_mux4_io21: IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 { + pinmux = <0x400e81e4 5 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_qtimer1_timer0: IOMUXC_GPIO_DISP_B1_00_QTIMER1_TIMER0 { + pinmux = <0x400e81e4 3 0x400e863c 2 0x400e8428>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_video_mux_lcdif_clk: IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK { + pinmux = <0x400e81e4 0 0x0 0 0x400e8428>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_in26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_IN26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_00_xbar1_xbar_inout26: IOMUXC_GPIO_DISP_B1_00_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e81e4 4 0x400e86f0 1 0x400e8428>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_clk: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK { + pinmux = <0x400e81e8 1 0x400e84cc 2 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_enet_1g_rx_er: IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER { + pinmux = <0x400e81e8 2 0x400e84e4 1 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio10_io22: IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 { + pinmux = <0x400e81e8 10 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_gpio_mux4_io22: IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 { + pinmux = <0x400e81e8 5 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_qtimer1_timer1: IOMUXC_GPIO_DISP_B1_01_QTIMER1_TIMER1 { + pinmux = <0x400e81e8 3 0x400e8640 2 0x400e842c>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_video_mux_lcdif_enable: IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE { + pinmux = <0x400e81e8 0 0x0 0 0x400e842c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_in27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_IN27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_01_xbar1_xbar_inout27: IOMUXC_GPIO_DISP_B1_01_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e81e8 4 0x400e86f4 1 0x400e842c>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_enet_1g_rdata00: IOMUXC_GPIO_DISP_B1_02_ENET_1G_RDATA00 { + pinmux = <0x400e81ec 1 0x400e84d0 2 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio10_io23: IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 { + pinmux = <0x400e81ec 10 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_gpio_mux4_io23: IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 { + pinmux = <0x400e81ec 5 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpi2c3_scl: IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL { + pinmux = <0x400e81ec 2 0x400e85bc 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_lpuart1_tx: IOMUXC_GPIO_DISP_B1_02_LPUART1_TX { + pinmux = <0x400e81ec 9 0x400e8620 1 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_qtimer1_timer2: IOMUXC_GPIO_DISP_B1_02_QTIMER1_TIMER2 { + pinmux = <0x400e81ec 3 0x400e8644 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_video_mux_lcdif_hsync: IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC { + pinmux = <0x400e81ec 0 0x0 0 0x400e8430>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_in28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_IN28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_02_xbar1_xbar_inout28: IOMUXC_GPIO_DISP_B1_02_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e81ec 4 0x400e86f8 1 0x400e8430>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_enet_1g_rdata01: IOMUXC_GPIO_DISP_B1_03_ENET_1G_RDATA01 { + pinmux = <0x400e81f0 1 0x400e84d4 2 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio10_io24: IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 { + pinmux = <0x400e81f0 10 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_gpio_mux4_io24: IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 { + pinmux = <0x400e81f0 5 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpi2c3_sda: IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA { + pinmux = <0x400e81f0 2 0x400e85c0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_lpuart1_rx: IOMUXC_GPIO_DISP_B1_03_LPUART1_RX { + pinmux = <0x400e81f0 9 0x400e861c 1 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_qtimer2_timer0: IOMUXC_GPIO_DISP_B1_03_QTIMER2_TIMER0 { + pinmux = <0x400e81f0 3 0x400e8648 2 0x400e8434>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_video_mux_lcdif_vsync: IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC { + pinmux = <0x400e81f0 0 0x0 0 0x400e8434>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_in29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_IN29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_03_xbar1_xbar_inout29: IOMUXC_GPIO_DISP_B1_03_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e81f0 4 0x400e86fc 1 0x400e8434>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_enet_1g_rdata02: IOMUXC_GPIO_DISP_B1_04_ENET_1G_RDATA02 { + pinmux = <0x400e81f4 1 0x400e84d8 2 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio10_io25: IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 { + pinmux = <0x400e81f4 10 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_gpio_mux4_io25: IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 { + pinmux = <0x400e81f4 5 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpspi3_sck: IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK { + pinmux = <0x400e81f4 9 0x400e8600 1 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_lpuart4_rx: IOMUXC_GPIO_DISP_B1_04_LPUART4_RX { + pinmux = <0x400e81f4 2 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_qtimer2_timer1: IOMUXC_GPIO_DISP_B1_04_QTIMER2_TIMER1 { + pinmux = <0x400e81f4 3 0x400e864c 2 0x400e8438>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_video_mux_lcdif_data00: IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 { + pinmux = <0x400e81f4 0 0x0 0 0x400e8438>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_in30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_IN30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_04_xbar1_xbar_inout30: IOMUXC_GPIO_DISP_B1_04_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e81f4 4 0x400e8700 1 0x400e8438>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_enet_1g_rdata03: IOMUXC_GPIO_DISP_B1_05_ENET_1G_RDATA03 { + pinmux = <0x400e81f8 1 0x400e84dc 2 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio10_io26: IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 { + pinmux = <0x400e81f8 10 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_gpio_mux4_io26: IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 { + pinmux = <0x400e81f8 5 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpspi3_sdi: IOMUXC_GPIO_DISP_B1_05_LPSPI3_SDI { + pinmux = <0x400e81f8 9 0x400e8604 1 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_lpuart4_cts_b: IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B { + pinmux = <0x400e81f8 2 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_qtimer2_timer2: IOMUXC_GPIO_DISP_B1_05_QTIMER2_TIMER2 { + pinmux = <0x400e81f8 3 0x400e8650 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_video_mux_lcdif_data01: IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 { + pinmux = <0x400e81f8 0 0x0 0 0x400e843c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_in31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_IN31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_05_xbar1_xbar_inout31: IOMUXC_GPIO_DISP_B1_05_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e81f8 4 0x400e8704 1 0x400e843c>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_enet_1g_tdata03: IOMUXC_GPIO_DISP_B1_06_ENET_1G_TDATA03 { + pinmux = <0x400e81fc 1 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio10_io27: IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 { + pinmux = <0x400e81fc 10 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_gpio_mux4_io27: IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 { + pinmux = <0x400e81fc 5 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpspi3_sdo: IOMUXC_GPIO_DISP_B1_06_LPSPI3_SDO { + pinmux = <0x400e81fc 9 0x400e8608 1 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_lpuart4_tx: IOMUXC_GPIO_DISP_B1_06_LPUART4_TX { + pinmux = <0x400e81fc 2 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_qtimer3_timer0: IOMUXC_GPIO_DISP_B1_06_QTIMER3_TIMER0 { + pinmux = <0x400e81fc 3 0x400e8654 2 0x400e8440>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_src_bt_cfg00: IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 { + pinmux = <0x400e81fc 6 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_video_mux_lcdif_data02: IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 { + pinmux = <0x400e81fc 0 0x0 0 0x400e8440>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_in32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_IN32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_06_xbar1_xbar_inout32: IOMUXC_GPIO_DISP_B1_06_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e81fc 4 0x400e8708 1 0x400e8440>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_enet_1g_tdata02: IOMUXC_GPIO_DISP_B1_07_ENET_1G_TDATA02 { + pinmux = <0x400e8200 1 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio10_io28: IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 { + pinmux = <0x400e8200 10 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_gpio_mux4_io28: IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 { + pinmux = <0x400e8200 5 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpspi3_pcs0: IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 { + pinmux = <0x400e8200 9 0x400e85f0 1 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_lpuart4_rts_b: IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B { + pinmux = <0x400e8200 2 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_qtimer3_timer1: IOMUXC_GPIO_DISP_B1_07_QTIMER3_TIMER1 { + pinmux = <0x400e8200 3 0x400e8658 2 0x400e8444>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_src_bt_cfg01: IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 { + pinmux = <0x400e8200 6 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_video_mux_lcdif_data03: IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 { + pinmux = <0x400e8200 0 0x0 0 0x400e8444>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_in33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_IN33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_07_xbar1_xbar_inout33: IOMUXC_GPIO_DISP_B1_07_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e8200 4 0x400e870c 1 0x400e8444>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_enet_1g_tdata01: IOMUXC_GPIO_DISP_B1_08_ENET_1G_TDATA01 { + pinmux = <0x400e8204 1 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio10_io29: IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 { + pinmux = <0x400e8204 10 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_gpio_mux4_io29: IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 { + pinmux = <0x400e8204 5 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_lpspi3_pcs1: IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 { + pinmux = <0x400e8204 9 0x400e85f4 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_qtimer3_timer2: IOMUXC_GPIO_DISP_B1_08_QTIMER3_TIMER2 { + pinmux = <0x400e8204 3 0x400e865c 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_src_bt_cfg02: IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 { + pinmux = <0x400e8204 6 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_usdhc1_cd_b: IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B { + pinmux = <0x400e8204 2 0x400e86c8 1 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_video_mux_lcdif_data04: IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 { + pinmux = <0x400e8204 0 0x0 0 0x400e8448>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_in34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_IN34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_08_xbar1_xbar_inout34: IOMUXC_GPIO_DISP_B1_08_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e8204 4 0x400e8710 1 0x400e8448>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_enet_1g_tdata00: IOMUXC_GPIO_DISP_B1_09_ENET_1G_TDATA00 { + pinmux = <0x400e8208 1 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio10_io30: IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 { + pinmux = <0x400e8208 10 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_gpio_mux4_io30: IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 { + pinmux = <0x400e8208 5 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_lpspi3_pcs2: IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 { + pinmux = <0x400e8208 9 0x400e85f8 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_qtimer4_timer0: IOMUXC_GPIO_DISP_B1_09_QTIMER4_TIMER0 { + pinmux = <0x400e8208 3 0x400e8660 2 0x400e844c>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_src_bt_cfg03: IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 { + pinmux = <0x400e8208 6 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_usdhc1_wp: IOMUXC_GPIO_DISP_B1_09_USDHC1_WP { + pinmux = <0x400e8208 2 0x400e86cc 1 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_video_mux_lcdif_data05: IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 { + pinmux = <0x400e8208 0 0x0 0 0x400e844c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_in35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_IN35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_09_xbar1_xbar_inout35: IOMUXC_GPIO_DISP_B1_09_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e8208 4 0x400e8714 1 0x400e844c>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_enet_1g_tx_en: IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN { + pinmux = <0x400e820c 1 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio10_io31: IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 { + pinmux = <0x400e820c 10 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_gpio_mux4_io31: IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 { + pinmux = <0x400e820c 5 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_lpspi3_pcs3: IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 { + pinmux = <0x400e820c 9 0x400e85fc 1 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_qtimer4_timer1: IOMUXC_GPIO_DISP_B1_10_QTIMER4_TIMER1 { + pinmux = <0x400e820c 3 0x400e8664 2 0x400e8450>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_src_bt_cfg04: IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 { + pinmux = <0x400e820c 6 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_usdhc1_reset_b: IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B { + pinmux = <0x400e820c 2 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_video_mux_lcdif_data06: IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 { + pinmux = <0x400e820c 0 0x0 0 0x400e8450>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_in36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_IN36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_10_xbar1_xbar_inout36: IOMUXC_GPIO_DISP_B1_10_XBAR1_XBAR_INOUT36 { + pinmux = <0x400e820c 4 0x0 0 0x400e8450>; + pin-pdrv; + gpr = <0x400e4054 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e8210 2 0x400e84c4 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_enet_1g_tx_clk_io: IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e8210 1 0x400e84e8 2 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio11_io00: IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 { + pinmux = <0x400e8210 10 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_gpio_mux5_io00: IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 { + pinmux = <0x400e8210 5 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_qtimer4_timer2: IOMUXC_GPIO_DISP_B1_11_QTIMER4_TIMER2 { + pinmux = <0x400e8210 3 0x400e8668 1 0x400e8454>; + pin-pdrv; + gpr = <0x400e403c 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_src_bt_cfg05: IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 { + pinmux = <0x400e8210 6 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_video_mux_lcdif_data07: IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 { + pinmux = <0x400e8210 0 0x0 0 0x400e8454>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_in37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_IN37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b1_11_xbar1_xbar_inout37: IOMUXC_GPIO_DISP_B1_11_XBAR1_XBAR_INOUT37 { + pinmux = <0x400e8210 4 0x0 0 0x400e8454>; + pin-pdrv; + gpr = <0x400e4054 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_enet_1g_tx_er: IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER { + pinmux = <0x400e8214 3 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio11_io01: IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 { + pinmux = <0x400e8214 10 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_gpio_mux5_io01: IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 { + pinmux = <0x400e8214 5 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_mqs_right: IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT { + pinmux = <0x400e8214 2 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_rx_data01: IOMUXC_GPIO_DISP_B2_00_SAI1_RX_DATA01 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_sai1_tx_data03: IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 { + pinmux = <0x400e8214 4 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_src_bt_cfg06: IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 { + pinmux = <0x400e8214 6 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_video_mux_lcdif_data08: IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 { + pinmux = <0x400e8214 0 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_00_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_00_WDOG1_WDOG_B { + pinmux = <0x400e8214 1 0x0 0 0x400e8458>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ccm_enet_ref_clk_25m: IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e8218 9 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_ewm_ewm_out_b: IOMUXC_GPIO_DISP_B2_01_EWM_EWM_OUT_B { + pinmux = <0x400e8218 8 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio11_io02: IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 { + pinmux = <0x400e8218 10 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_gpio_mux5_io02: IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 { + pinmux = <0x400e8218 5 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_mqs_left: IOMUXC_GPIO_DISP_B2_01_MQS_LEFT { + pinmux = <0x400e8218 2 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_rx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_RX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_sai1_tx_data02: IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 { + pinmux = <0x400e8218 4 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_src_bt_cfg07: IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 { + pinmux = <0x400e8218 6 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_usdhc1_vselect: IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT { + pinmux = <0x400e8218 1 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_video_mux_lcdif_data09: IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 { + pinmux = <0x400e8218 0 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_01_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_01_WDOG2_WDOG_B { + pinmux = <0x400e8218 3 0x0 0 0x400e845c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_arm_trace00: IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 { + pinmux = <0x400e821c 3 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_enet_tdata00: IOMUXC_GPIO_DISP_B2_02_ENET_TDATA00 { + pinmux = <0x400e821c 1 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio11_io03: IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 { + pinmux = <0x400e821c 10 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_gpio_mux5_io03: IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 { + pinmux = <0x400e821c 5 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_pit1_trigger03: IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER03 { + pinmux = <0x400e821c 2 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_rx_data03: IOMUXC_GPIO_DISP_B2_02_SAI1_RX_DATA03 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_sai1_tx_data01: IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 { + pinmux = <0x400e821c 4 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_src_bt_cfg08: IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 { + pinmux = <0x400e821c 6 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_02_video_mux_lcdif_data10: IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 { + pinmux = <0x400e821c 0 0x0 0 0x400e8460>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_arm_trace01: IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 { + pinmux = <0x400e8220 3 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_enet_tdata01: IOMUXC_GPIO_DISP_B2_03_ENET_TDATA01 { + pinmux = <0x400e8220 1 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio11_io04: IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 { + pinmux = <0x400e8220 10 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_gpio_mux5_io04: IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 { + pinmux = <0x400e8220 5 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_pit1_trigger02: IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER02 { + pinmux = <0x400e8220 2 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_sai1_mclk: IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK { + pinmux = <0x400e8220 4 0x400e866c 1 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_src_bt_cfg09: IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 { + pinmux = <0x400e8220 6 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_03_video_mux_lcdif_data11: IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 { + pinmux = <0x400e8220 0 0x0 0 0x400e8464>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_arm_trace02: IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 { + pinmux = <0x400e8224 3 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_enet_tx_en: IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN { + pinmux = <0x400e8224 1 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio11_io05: IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 { + pinmux = <0x400e8224 10 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_gpio_mux5_io05: IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 { + pinmux = <0x400e8224 5 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_pit1_trigger01: IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER01 { + pinmux = <0x400e8224 2 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_sai1_rx_sync: IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC { + pinmux = <0x400e8224 4 0x400e8678 1 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_src_bt_cfg10: IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 { + pinmux = <0x400e8224 6 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_04_video_mux_lcdif_data12: IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 { + pinmux = <0x400e8224 0 0x0 0 0x400e8468>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_arm_trace03: IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 { + pinmux = <0x400e8228 3 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_ref_clk: IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK { + pinmux = <0x400e8228 2 0x400e84a8 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_enet_tx_clk: IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK { + pinmux = <0x400e8228 1 0x400e84c0 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio11_io06: IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 { + pinmux = <0x400e8228 10 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_gpio_mux5_io06: IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 { + pinmux = <0x400e8228 5 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_sai1_rx_bclk: IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK { + pinmux = <0x400e8228 4 0x400e8670 1 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_src_bt_cfg11: IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 { + pinmux = <0x400e8228 6 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_05_video_mux_lcdif_data13: IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 { + pinmux = <0x400e8228 0 0x0 0 0x400e846c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_arm_trace_clk: IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK { + pinmux = <0x400e822c 3 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_enet_rdata00: IOMUXC_GPIO_DISP_B2_06_ENET_RDATA00 { + pinmux = <0x400e822c 1 0x400e84b0 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio11_io07: IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 { + pinmux = <0x400e822c 10 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_gpio_mux5_io07: IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 { + pinmux = <0x400e822c 5 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_lpuart7_tx: IOMUXC_GPIO_DISP_B2_06_LPUART7_TX { + pinmux = <0x400e822c 2 0x400e8630 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_sai1_rx_data00: IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 { + pinmux = <0x400e822c 4 0x400e8674 1 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_06_video_mux_lcdif_data14: IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 { + pinmux = <0x400e822c 0 0x0 0 0x400e8470>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_arm_trace_swo: IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO { + pinmux = <0x400e8230 3 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_enet_rdata01: IOMUXC_GPIO_DISP_B2_07_ENET_RDATA01 { + pinmux = <0x400e8230 1 0x400e84b4 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio11_io08: IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 { + pinmux = <0x400e8230 10 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_gpio_mux5_io08: IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 { + pinmux = <0x400e8230 5 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_lpuart7_rx: IOMUXC_GPIO_DISP_B2_07_LPUART7_RX { + pinmux = <0x400e8230 2 0x400e862c 1 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_sai1_tx_data00: IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 { + pinmux = <0x400e8230 4 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_07_video_mux_lcdif_data15: IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 { + pinmux = <0x400e8230 0 0x0 0 0x400e8474>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_cm7_imxrt_txev: IOMUXC_GPIO_DISP_B2_08_CM7_IMXRT_TXEV { + pinmux = <0x400e8234 3 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_enet_rx_en: IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN { + pinmux = <0x400e8234 1 0x400e84b8 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio11_io09: IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 { + pinmux = <0x400e8234 10 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_gpio_mux5_io09: IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 { + pinmux = <0x400e8234 5 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart1_tx: IOMUXC_GPIO_DISP_B2_08_LPUART1_TX { + pinmux = <0x400e8234 9 0x400e8620 2 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_lpuart8_tx: IOMUXC_GPIO_DISP_B2_08_LPUART8_TX { + pinmux = <0x400e8234 2 0x400e8638 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_sai1_tx_bclk: IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK { + pinmux = <0x400e8234 4 0x400e867c 1 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_08_video_mux_lcdif_data16: IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 { + pinmux = <0x400e8234 0 0x0 0 0x400e8478>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_cm7_imxrt_rxev: IOMUXC_GPIO_DISP_B2_09_CM7_IMXRT_RXEV { + pinmux = <0x400e8238 3 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_enet_rx_er: IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER { + pinmux = <0x400e8238 1 0x400e84bc 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio11_io10: IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 { + pinmux = <0x400e8238 10 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_gpio_mux5_io10: IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 { + pinmux = <0x400e8238 5 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart1_rx: IOMUXC_GPIO_DISP_B2_09_LPUART1_RX { + pinmux = <0x400e8238 9 0x400e861c 2 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_lpuart8_rx: IOMUXC_GPIO_DISP_B2_09_LPUART8_RX { + pinmux = <0x400e8238 2 0x400e8634 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_sai1_tx_sync: IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC { + pinmux = <0x400e8238 4 0x400e8680 1 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_09_video_mux_lcdif_data17: IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 { + pinmux = <0x400e8238 0 0x0 0 0x400e847c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio11_io11: IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 { + pinmux = <0x400e823c 10 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_gpio_mux5_io11: IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 { + pinmux = <0x400e823c 5 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpi2c3_scl: IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL { + pinmux = <0x400e823c 6 0x400e85bc 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_lpuart2_tx: IOMUXC_GPIO_DISP_B2_10_LPUART2_TX { + pinmux = <0x400e823c 2 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_sim2_trxd: IOMUXC_GPIO_DISP_B2_10_SIM2_TRXD { + pinmux = <0x400e823c 1 0x400e86a8 1 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_spdif_in: IOMUXC_GPIO_DISP_B2_10_SPDIF_IN { + pinmux = <0x400e823c 9 0x400e86b4 2 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_video_mux_lcdif_data18: IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 { + pinmux = <0x400e823c 0 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_wdog2_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_10_WDOG2_WDOG_RST_B_DEB { + pinmux = <0x400e823c 3 0x0 0 0x400e8480>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_in38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_IN38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_10_xbar1_xbar_inout38: IOMUXC_GPIO_DISP_B2_10_XBAR1_XBAR_INOUT38 { + pinmux = <0x400e823c 4 0x0 0 0x400e8480>; + pin-pue; + gpr = <0x400e4054 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio11_io12: IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 { + pinmux = <0x400e8240 10 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_gpio_mux5_io12: IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 { + pinmux = <0x400e8240 5 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpi2c3_sda: IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA { + pinmux = <0x400e8240 6 0x400e85c0 1 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_lpuart2_rx: IOMUXC_GPIO_DISP_B2_11_LPUART2_RX { + pinmux = <0x400e8240 2 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_sim2_clk: IOMUXC_GPIO_DISP_B2_11_SIM2_CLK { + pinmux = <0x400e8240 1 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_spdif_out: IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT { + pinmux = <0x400e8240 9 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_video_mux_lcdif_data19: IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 { + pinmux = <0x400e8240 0 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_wdog1_wdog_rst_b_deb: IOMUXC_GPIO_DISP_B2_11_WDOG1_WDOG_RST_B_DEB { + pinmux = <0x400e8240 3 0x0 0 0x400e8484>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_in39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_IN39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_11_xbar1_xbar_inout39: IOMUXC_GPIO_DISP_B2_11_XBAR1_XBAR_INOUT39 { + pinmux = <0x400e8240 4 0x0 0 0x400e8484>; + pin-pue; + gpr = <0x400e4054 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_can1_tx: IOMUXC_GPIO_DISP_B2_12_CAN1_TX { + pinmux = <0x400e8244 2 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio11_io13: IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 { + pinmux = <0x400e8244 10 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_gpio_mux5_io13: IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 { + pinmux = <0x400e8244 5 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpi2c4_scl: IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL { + pinmux = <0x400e8244 6 0x400e85c4 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpspi4_sck: IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK { + pinmux = <0x400e8244 9 0x400e8610 1 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_lpuart2_cts_b: IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B { + pinmux = <0x400e8244 3 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_sim2_rst_b: IOMUXC_GPIO_DISP_B2_12_SIM2_RST_B { + pinmux = <0x400e8244 1 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_video_mux_lcdif_data20: IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 { + pinmux = <0x400e8244 0 0x0 0 0x400e8488>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_in40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_IN40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_12_xbar1_xbar_inout40: IOMUXC_GPIO_DISP_B2_12_XBAR1_XBAR_INOUT40 { + pinmux = <0x400e8244 4 0x0 0 0x400e8488>; + pin-pue; + gpr = <0x400e4054 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_can1_rx: IOMUXC_GPIO_DISP_B2_13_CAN1_RX { + pinmux = <0x400e8248 2 0x400e8498 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_enet_ref_clk: IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK { + pinmux = <0x400e8248 4 0x400e84a8 2 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio11_io14: IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 { + pinmux = <0x400e8248 10 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_gpio_mux5_io14: IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 { + pinmux = <0x400e8248 5 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpi2c4_sda: IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA { + pinmux = <0x400e8248 6 0x400e85c8 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpspi4_sdi: IOMUXC_GPIO_DISP_B2_13_LPSPI4_SDI { + pinmux = <0x400e8248 9 0x400e8614 1 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_lpuart2_rts_b: IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B { + pinmux = <0x400e8248 3 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_sim2_sven: IOMUXC_GPIO_DISP_B2_13_SIM2_SVEN { + pinmux = <0x400e8248 1 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_13_video_mux_lcdif_data21: IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 { + pinmux = <0x400e8248 0 0x0 0 0x400e848c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_can1_tx: IOMUXC_GPIO_DISP_B2_14_CAN1_TX { + pinmux = <0x400e824c 6 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_enet_1g_ref_clk1: IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK1 { + pinmux = <0x400e824c 4 0x400e84c4 3 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio11_io15: IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 { + pinmux = <0x400e824c 10 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_gpio_mux5_io15: IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 { + pinmux = <0x400e824c 5 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_lpspi4_sdo: IOMUXC_GPIO_DISP_B2_14_LPSPI4_SDO { + pinmux = <0x400e824c 9 0x400e8618 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_sim2_pd: IOMUXC_GPIO_DISP_B2_14_SIM2_PD { + pinmux = <0x400e824c 1 0x400e86ac 1 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_ext_dcic1: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 { + pinmux = <0x400e824c 3 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_video_mux_lcdif_data22: IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 { + pinmux = <0x400e824c 0 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_14_wdog2_wdog_b: IOMUXC_GPIO_DISP_B2_14_WDOG2_WDOG_B { + pinmux = <0x400e824c 2 0x0 0 0x400e8490>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_can1_rx: IOMUXC_GPIO_DISP_B2_15_CAN1_RX { + pinmux = <0x400e8250 6 0x400e8498 2 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio11_io16: IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 { + pinmux = <0x400e8250 10 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_gpio_mux5_io16: IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 { + pinmux = <0x400e8250 5 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_lpspi4_pcs0: IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 { + pinmux = <0x400e8250 9 0x400e860c 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_pit1_trigger00: IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER00 { + pinmux = <0x400e8250 4 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_sim2_power_fail: IOMUXC_GPIO_DISP_B2_15_SIM2_POWER_FAIL { + pinmux = <0x400e8250 1 0x400e86b0 1 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_ext_dcic2: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 { + pinmux = <0x400e8250 3 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_video_mux_lcdif_data23: IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 { + pinmux = <0x400e8250 0 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_disp_b2_15_wdog1_wdog_b: IOMUXC_GPIO_DISP_B2_15_WDOG1_WDOG_B { + pinmux = <0x400e8250 2 0x0 0 0x400e8494>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexio1_flexio00: IOMUXC_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00 { + pinmux = <0x400e8010 8 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_flexpwm4_pwm0_a: IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A { + pinmux = <0x400e8010 1 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio7_io00: IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 { + pinmux = <0x400e8010 10 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_gpio_mux1_io00: IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 { + pinmux = <0x400e8010 5 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_00_semc_data00: IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 { + pinmux = <0x400e8010 0 0x0 0 0x400e8254>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexio1_flexio01: IOMUXC_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01 { + pinmux = <0x400e8014 8 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_flexpwm4_pwm0_b: IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B { + pinmux = <0x400e8014 1 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio7_io01: IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 { + pinmux = <0x400e8014 10 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_gpio_mux1_io01: IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 { + pinmux = <0x400e8014 5 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_01_semc_data01: IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 { + pinmux = <0x400e8014 0 0x0 0 0x400e8258>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexio1_flexio02: IOMUXC_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02 { + pinmux = <0x400e8018 8 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_flexpwm4_pwm1_a: IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A { + pinmux = <0x400e8018 1 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio7_io02: IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 { + pinmux = <0x400e8018 10 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_gpio_mux1_io02: IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 { + pinmux = <0x400e8018 5 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_02_semc_data02: IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 { + pinmux = <0x400e8018 0 0x0 0 0x400e825c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexio1_flexio03: IOMUXC_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03 { + pinmux = <0x400e801c 8 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_flexpwm4_pwm1_b: IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B { + pinmux = <0x400e801c 1 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio7_io03: IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 { + pinmux = <0x400e801c 10 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_gpio_mux1_io03: IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 { + pinmux = <0x400e801c 5 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_03_semc_data03: IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 { + pinmux = <0x400e801c 0 0x0 0 0x400e8260>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexio1_flexio04: IOMUXC_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04 { + pinmux = <0x400e8020 8 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_flexpwm4_pwm2_a: IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A { + pinmux = <0x400e8020 1 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio7_io04: IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 { + pinmux = <0x400e8020 10 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_gpio_mux1_io04: IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 { + pinmux = <0x400e8020 5 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_04_semc_data04: IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 { + pinmux = <0x400e8020 0 0x0 0 0x400e8264>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexio1_flexio05: IOMUXC_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05 { + pinmux = <0x400e8024 8 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_flexpwm4_pwm2_b: IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B { + pinmux = <0x400e8024 1 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio7_io05: IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 { + pinmux = <0x400e8024 10 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_gpio_mux1_io05: IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 { + pinmux = <0x400e8024 5 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_05_semc_data05: IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 { + pinmux = <0x400e8024 0 0x0 0 0x400e8268>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexio1_flexio06: IOMUXC_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06 { + pinmux = <0x400e8028 8 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_flexpwm2_pwm0_a: IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A { + pinmux = <0x400e8028 1 0x400e8518 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio7_io06: IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 { + pinmux = <0x400e8028 10 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_gpio_mux1_io06: IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 { + pinmux = <0x400e8028 5 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_06_semc_data06: IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 { + pinmux = <0x400e8028 0 0x0 0 0x400e826c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexio1_flexio07: IOMUXC_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07 { + pinmux = <0x400e802c 8 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_flexpwm2_pwm0_b: IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B { + pinmux = <0x400e802c 1 0x400e8524 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio7_io07: IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 { + pinmux = <0x400e802c 10 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_gpio_mux1_io07: IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 { + pinmux = <0x400e802c 5 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_07_semc_data07: IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 { + pinmux = <0x400e802c 0 0x0 0 0x400e8270>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexio1_flexio08: IOMUXC_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08 { + pinmux = <0x400e8030 8 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_flexpwm2_pwm1_a: IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A { + pinmux = <0x400e8030 1 0x400e851c 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio7_io08: IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 { + pinmux = <0x400e8030 10 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_gpio_mux1_io08: IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 { + pinmux = <0x400e8030 5 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_08_semc_dm00: IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 { + pinmux = <0x400e8030 0 0x0 0 0x400e8274>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexio1_flexio09: IOMUXC_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09 { + pinmux = <0x400e8034 8 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_flexpwm2_pwm1_b: IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B { + pinmux = <0x400e8034 1 0x400e8528 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio7_io09: IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 { + pinmux = <0x400e8034 10 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpio_mux1_io09: IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 { + pinmux = <0x400e8034 5 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_gpt5_capture1: IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 { + pinmux = <0x400e8034 2 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_09_semc_addr00: IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 { + pinmux = <0x400e8034 0 0x0 0 0x400e8278>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexio1_flexio10: IOMUXC_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10 { + pinmux = <0x400e8038 8 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_flexpwm2_pwm2_a: IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A { + pinmux = <0x400e8038 1 0x400e8520 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio7_io10: IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 { + pinmux = <0x400e8038 10 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpio_mux1_io10: IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 { + pinmux = <0x400e8038 5 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_gpt5_capture2: IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 { + pinmux = <0x400e8038 2 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_10_semc_addr01: IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 { + pinmux = <0x400e8038 0 0x0 0 0x400e827c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexio1_flexio11: IOMUXC_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11 { + pinmux = <0x400e803c 8 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_flexpwm2_pwm2_b: IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B { + pinmux = <0x400e803c 1 0x400e852c 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio7_io11: IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 { + pinmux = <0x400e803c 10 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpio_mux1_io11: IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 { + pinmux = <0x400e803c 5 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_gpt5_compare1: IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 { + pinmux = <0x400e803c 2 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_11_semc_addr02: IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 { + pinmux = <0x400e803c 0 0x0 0 0x400e8280>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_flexio1_flexio12: IOMUXC_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12 { + pinmux = <0x400e8040 8 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio7_io12: IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 { + pinmux = <0x400e8040 10 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpio_mux1_io12: IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 { + pinmux = <0x400e8040 5 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_gpt5_compare2: IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 { + pinmux = <0x400e8040 2 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_semc_addr03: IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 { + pinmux = <0x400e8040 0 0x0 0 0x400e8284>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_in04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_IN04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_12_xbar1_xbar_inout04: IOMUXC_GPIO_EMC_B1_12_XBAR1_XBAR_INOUT04 { + pinmux = <0x400e8040 1 0x0 0 0x400e8284>; + pin-pdrv; + gpr = <0x400e4050 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_flexio1_flexio13: IOMUXC_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13 { + pinmux = <0x400e8044 8 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio7_io13: IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 { + pinmux = <0x400e8044 10 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpio_mux1_io13: IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 { + pinmux = <0x400e8044 5 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_gpt5_compare3: IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 { + pinmux = <0x400e8044 2 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_semc_addr04: IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 { + pinmux = <0x400e8044 0 0x0 0 0x400e8288>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_in05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_IN05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_13_xbar1_xbar_inout05: IOMUXC_GPIO_EMC_B1_13_XBAR1_XBAR_INOUT05 { + pinmux = <0x400e8044 1 0x0 0 0x400e8288>; + pin-pdrv; + gpr = <0x400e4050 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_flexio1_flexio14: IOMUXC_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14 { + pinmux = <0x400e8048 8 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio7_io14: IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 { + pinmux = <0x400e8048 10 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpio_mux1_io14: IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 { + pinmux = <0x400e8048 5 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_gpt5_clk: IOMUXC_GPIO_EMC_B1_14_GPT5_CLK { + pinmux = <0x400e8048 2 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_semc_addr05: IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 { + pinmux = <0x400e8048 0 0x0 0 0x400e828c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_in06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_IN06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_14_xbar1_xbar_inout06: IOMUXC_GPIO_EMC_B1_14_XBAR1_XBAR_INOUT06 { + pinmux = <0x400e8048 1 0x0 0 0x400e828c>; + pin-pdrv; + gpr = <0x400e4050 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_flexio1_flexio15: IOMUXC_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15 { + pinmux = <0x400e804c 8 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio7_io15: IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 { + pinmux = <0x400e804c 10 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_gpio_mux1_io15: IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 { + pinmux = <0x400e804c 5 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_semc_addr06: IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 { + pinmux = <0x400e804c 0 0x0 0 0x400e8290>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_in07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_IN07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_15_xbar1_xbar_inout07: IOMUXC_GPIO_EMC_B1_15_XBAR1_XBAR_INOUT07 { + pinmux = <0x400e804c 1 0x0 0 0x400e8290>; + pin-pdrv; + gpr = <0x400e4050 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_flexio1_flexio16: IOMUXC_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16 { + pinmux = <0x400e8050 8 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio7_io16: IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 { + pinmux = <0x400e8050 10 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_gpio_mux1_io16: IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 { + pinmux = <0x400e8050 5 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_semc_addr07: IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 { + pinmux = <0x400e8050 0 0x0 0 0x400e8294>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_in08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_IN08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_16_xbar1_xbar_inout08: IOMUXC_GPIO_EMC_B1_16_XBAR1_XBAR_INOUT08 { + pinmux = <0x400e8050 1 0x0 0 0x400e8294>; + pin-pdrv; + gpr = <0x400e4050 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexio1_flexio17: IOMUXC_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17 { + pinmux = <0x400e8054 8 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_flexpwm4_pwm3_a: IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A { + pinmux = <0x400e8054 1 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio7_io17: IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 { + pinmux = <0x400e8054 10 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_gpio_mux1_io17: IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 { + pinmux = <0x400e8054 5 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_qtimer1_timer0: IOMUXC_GPIO_EMC_B1_17_QTIMER1_TIMER0 { + pinmux = <0x400e8054 2 0x400e863c 0 0x400e8298>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_17_semc_addr08: IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 { + pinmux = <0x400e8054 0 0x0 0 0x400e8298>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexio1_flexio18: IOMUXC_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18 { + pinmux = <0x400e8058 8 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_flexpwm4_pwm3_b: IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B { + pinmux = <0x400e8058 1 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio7_io18: IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 { + pinmux = <0x400e8058 10 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_gpio_mux1_io18: IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 { + pinmux = <0x400e8058 5 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_qtimer2_timer0: IOMUXC_GPIO_EMC_B1_18_QTIMER2_TIMER0 { + pinmux = <0x400e8058 2 0x400e8648 0 0x400e829c>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_18_semc_addr09: IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 { + pinmux = <0x400e8058 0 0x0 0 0x400e829c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexio1_flexio19: IOMUXC_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19 { + pinmux = <0x400e805c 8 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_flexpwm2_pwm3_a: IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A { + pinmux = <0x400e805c 1 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio7_io19: IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 { + pinmux = <0x400e805c 10 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_gpio_mux1_io19: IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 { + pinmux = <0x400e805c 5 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_qtimer3_timer0: IOMUXC_GPIO_EMC_B1_19_QTIMER3_TIMER0 { + pinmux = <0x400e805c 2 0x400e8654 0 0x400e82a0>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_19_semc_addr11: IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 { + pinmux = <0x400e805c 0 0x0 0 0x400e82a0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexio1_flexio20: IOMUXC_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20 { + pinmux = <0x400e8060 8 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_flexpwm2_pwm3_b: IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B { + pinmux = <0x400e8060 1 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio7_io20: IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 { + pinmux = <0x400e8060 10 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_gpio_mux1_io20: IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 { + pinmux = <0x400e8060 5 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_qtimer4_timer0: IOMUXC_GPIO_EMC_B1_20_QTIMER4_TIMER0 { + pinmux = <0x400e8060 2 0x400e8660 0 0x400e82a4>; + pin-pdrv; + gpr = <0x400e403c 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_20_semc_addr12: IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 { + pinmux = <0x400e8060 0 0x0 0 0x400e82a4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexio1_flexio21: IOMUXC_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21 { + pinmux = <0x400e8064 8 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A { + pinmux = <0x400e8064 1 0x400e853c 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio7_io21: IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 { + pinmux = <0x400e8064 10 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_gpio_mux1_io21: IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 { + pinmux = <0x400e8064 5 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_21_semc_ba0: IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 { + pinmux = <0x400e8064 0 0x0 0 0x400e82a8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexio1_flexio22: IOMUXC_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22 { + pinmux = <0x400e8068 8 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B { + pinmux = <0x400e8068 1 0x400e854c 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio7_io22: IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 { + pinmux = <0x400e8068 10 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_gpio_mux1_io22: IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 { + pinmux = <0x400e8068 5 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_22_semc_ba1: IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 { + pinmux = <0x400e8068 0 0x0 0 0x400e82ac>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexio1_flexio23: IOMUXC_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23 { + pinmux = <0x400e806c 8 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_flexpwm1_pwm0_a: IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A { + pinmux = <0x400e806c 1 0x400e8500 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio7_io23: IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 { + pinmux = <0x400e806c 10 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_gpio_mux1_io23: IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 { + pinmux = <0x400e806c 5 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_23_semc_addr10: IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 { + pinmux = <0x400e806c 0 0x0 0 0x400e82b0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexio1_flexio24: IOMUXC_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24 { + pinmux = <0x400e8070 8 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_flexpwm1_pwm0_b: IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B { + pinmux = <0x400e8070 1 0x400e850c 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio7_io24: IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 { + pinmux = <0x400e8070 10 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_gpio_mux1_io24: IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 { + pinmux = <0x400e8070 5 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_24_semc_cas: IOMUXC_GPIO_EMC_B1_24_SEMC_CAS { + pinmux = <0x400e8070 0 0x0 0 0x400e82b4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexio1_flexio25: IOMUXC_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25 { + pinmux = <0x400e8074 8 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_flexpwm1_pwm1_a: IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A { + pinmux = <0x400e8074 1 0x400e8504 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio7_io25: IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 { + pinmux = <0x400e8074 10 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_gpio_mux1_io25: IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 { + pinmux = <0x400e8074 5 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_25_semc_ras: IOMUXC_GPIO_EMC_B1_25_SEMC_RAS { + pinmux = <0x400e8074 0 0x0 0 0x400e82b8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexio1_flexio26: IOMUXC_GPIO_EMC_B1_26_FLEXIO1_FLEXIO26 { + pinmux = <0x400e8078 8 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_flexpwm1_pwm1_b: IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B { + pinmux = <0x400e8078 1 0x400e8510 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio7_io26: IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 { + pinmux = <0x400e8078 10 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_gpio_mux1_io26: IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 { + pinmux = <0x400e8078 5 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_26_semc_clk: IOMUXC_GPIO_EMC_B1_26_SEMC_CLK { + pinmux = <0x400e8078 0 0x0 0 0x400e82bc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexio1_flexio27: IOMUXC_GPIO_EMC_B1_27_FLEXIO1_FLEXIO27 { + pinmux = <0x400e807c 8 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_flexpwm1_pwm2_a: IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A { + pinmux = <0x400e807c 1 0x400e8508 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio7_io27: IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 { + pinmux = <0x400e807c 10 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_gpio_mux1_io27: IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 { + pinmux = <0x400e807c 5 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_27_semc_cke: IOMUXC_GPIO_EMC_B1_27_SEMC_CKE { + pinmux = <0x400e807c 0 0x0 0 0x400e82c0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexio1_flexio28: IOMUXC_GPIO_EMC_B1_28_FLEXIO1_FLEXIO28 { + pinmux = <0x400e8080 8 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_flexpwm1_pwm2_b: IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B { + pinmux = <0x400e8080 1 0x400e8514 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio7_io28: IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 { + pinmux = <0x400e8080 10 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_gpio_mux1_io28: IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 { + pinmux = <0x400e8080 5 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_28_semc_we: IOMUXC_GPIO_EMC_B1_28_SEMC_WE { + pinmux = <0x400e8080 0 0x0 0 0x400e82c4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexio1_flexio29: IOMUXC_GPIO_EMC_B1_29_FLEXIO1_FLEXIO29 { + pinmux = <0x400e8084 8 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A { + pinmux = <0x400e8084 1 0x400e8530 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio7_io29: IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 { + pinmux = <0x400e8084 10 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_gpio_mux1_io29: IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 { + pinmux = <0x400e8084 5 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_29_semc_cs0: IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 { + pinmux = <0x400e8084 0 0x0 0 0x400e82c8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexio1_flexio30: IOMUXC_GPIO_EMC_B1_30_FLEXIO1_FLEXIO30 { + pinmux = <0x400e8088 8 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B { + pinmux = <0x400e8088 1 0x400e8540 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio7_io30: IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 { + pinmux = <0x400e8088 10 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_gpio_mux1_io30: IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 { + pinmux = <0x400e8088 5 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_30_semc_data08: IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 { + pinmux = <0x400e8088 0 0x0 0 0x400e82cc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexio1_flexio31: IOMUXC_GPIO_EMC_B1_31_FLEXIO1_FLEXIO31 { + pinmux = <0x400e808c 8 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A { + pinmux = <0x400e808c 1 0x400e8534 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio7_io31: IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 { + pinmux = <0x400e808c 10 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_gpio_mux1_io31: IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 { + pinmux = <0x400e808c 5 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_31_semc_data09: IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 { + pinmux = <0x400e808c 0 0x0 0 0x400e82d0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B { + pinmux = <0x400e8090 1 0x400e8544 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio8_io00: IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 { + pinmux = <0x400e8090 10 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_gpio_mux2_io00_cm7: IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00_CM7 { + pinmux = <0x400e8090 5 0x0 0 0x400e82d4>; + pin-pdrv; + gpr = <0x400e40a0 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_32_semc_data10: IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 { + pinmux = <0x400e8090 0 0x0 0 0x400e82d4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A { + pinmux = <0x400e8094 1 0x400e8538 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio8_io01: IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 { + pinmux = <0x400e8094 10 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_gpio_mux2_io01_cm7: IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01_CM7 { + pinmux = <0x400e8094 5 0x0 0 0x400e82d8>; + pin-pdrv; + gpr = <0x400e40a0 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_33_semc_data11: IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 { + pinmux = <0x400e8094 0 0x0 0 0x400e82d8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B { + pinmux = <0x400e8098 1 0x400e8548 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio8_io02: IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 { + pinmux = <0x400e8098 10 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_gpio_mux2_io02_cm7: IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02_CM7 { + pinmux = <0x400e8098 5 0x0 0 0x400e82dc>; + pin-pdrv; + gpr = <0x400e40a0 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_34_semc_data12: IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 { + pinmux = <0x400e8098 0 0x0 0 0x400e82dc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio8_io03: IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 { + pinmux = <0x400e809c 10 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_gpio_mux2_io03_cm7: IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03_CM7 { + pinmux = <0x400e809c 5 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e40a0 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_semc_data13: IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 { + pinmux = <0x400e809c 0 0x0 0 0x400e82e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_in09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_IN09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_35_xbar1_xbar_inout09: IOMUXC_GPIO_EMC_B1_35_XBAR1_XBAR_INOUT09 { + pinmux = <0x400e809c 1 0x0 0 0x400e82e0>; + pin-pdrv; + gpr = <0x400e4050 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio8_io04: IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 { + pinmux = <0x400e80a0 10 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_gpio_mux2_io04_cm7: IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04_CM7 { + pinmux = <0x400e80a0 5 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e40a0 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_semc_data14: IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 { + pinmux = <0x400e80a0 0 0x0 0 0x400e82e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_in10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_IN10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_36_xbar1_xbar_inout10: IOMUXC_GPIO_EMC_B1_36_XBAR1_XBAR_INOUT10 { + pinmux = <0x400e80a0 1 0x0 0 0x400e82e4>; + pin-pdrv; + gpr = <0x400e4050 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio8_io05: IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 { + pinmux = <0x400e80a4 10 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_gpio_mux2_io05_cm7: IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05_CM7 { + pinmux = <0x400e80a4 5 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e40a0 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_semc_data15: IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 { + pinmux = <0x400e80a4 0 0x0 0 0x400e82e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_in11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_IN11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_37_xbar1_xbar_inout11: IOMUXC_GPIO_EMC_B1_37_XBAR1_XBAR_INOUT11 { + pinmux = <0x400e80a4 1 0x0 0 0x400e82e8>; + pin-pdrv; + gpr = <0x400e4050 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_flexpwm1_pwm3_a: IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A { + pinmux = <0x400e80a8 1 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio8_io06: IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 { + pinmux = <0x400e80a8 10 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_gpio_mux2_io06_cm7: IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06_CM7 { + pinmux = <0x400e80a8 5 0x0 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e40a0 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_qtimer1_timer1: IOMUXC_GPIO_EMC_B1_38_QTIMER1_TIMER1 { + pinmux = <0x400e80a8 2 0x400e8640 0 0x400e82ec>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_38_semc_dm01: IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 { + pinmux = <0x400e80a8 0 0x0 0 0x400e82ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_flexpwm1_pwm3_b: IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B { + pinmux = <0x400e80ac 1 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio8_io07: IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 { + pinmux = <0x400e80ac 10 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_gpio_mux2_io07_cm7: IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07_CM7 { + pinmux = <0x400e80ac 5 0x0 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e40a0 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_qtimer2_timer1: IOMUXC_GPIO_EMC_B1_39_QTIMER2_TIMER1 { + pinmux = <0x400e80ac 2 0x400e864c 0 0x400e82f0>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_39_semc_dqs: IOMUXC_GPIO_EMC_B1_39_SEMC_DQS { + pinmux = <0x400e80ac 0 0x0 0 0x400e82f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_ccm_clko1: IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 { + pinmux = <0x400e80b0 9 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_enet_1g_mdc: IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC { + pinmux = <0x400e80b0 7 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio8_io08: IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 { + pinmux = <0x400e80b0 10 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_gpio_mux2_io08_cm7: IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08_CM7 { + pinmux = <0x400e80b0 5 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e40a0 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_lpuart6_tx: IOMUXC_GPIO_EMC_B1_40_LPUART6_TX { + pinmux = <0x400e80b0 3 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_mqs_right: IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT { + pinmux = <0x400e80b0 2 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_semc_rdy: IOMUXC_GPIO_EMC_B1_40_SEMC_RDY { + pinmux = <0x400e80b0 0 0x0 0 0x400e82f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_in12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_IN12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_40_xbar1_xbar_inout12: IOMUXC_GPIO_EMC_B1_40_XBAR1_XBAR_INOUT12 { + pinmux = <0x400e80b0 1 0x0 0 0x400e82f4>; + pin-pdrv; + gpr = <0x400e4050 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_ccm_clko2: IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 { + pinmux = <0x400e80b4 9 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_enet_1g_mdio: IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO { + pinmux = <0x400e80b4 7 0x400e84c8 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_flexspi2_b_data07: IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 { + pinmux = <0x400e80b4 4 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio8_io09: IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 { + pinmux = <0x400e80b4 10 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_gpio_mux2_io09_cm7: IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09_CM7 { + pinmux = <0x400e80b4 5 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e40a0 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_lpuart6_rx: IOMUXC_GPIO_EMC_B1_41_LPUART6_RX { + pinmux = <0x400e80b4 3 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_mqs_left: IOMUXC_GPIO_EMC_B1_41_MQS_LEFT { + pinmux = <0x400e80b4 2 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_semc_csx00: IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 { + pinmux = <0x400e80b4 0 0x0 0 0x400e82f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_in13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_IN13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b1_41_xbar1_xbar_inout13: IOMUXC_GPIO_EMC_B1_41_XBAR1_XBAR_INOUT13 { + pinmux = <0x400e80b4 1 0x0 0 0x400e82f8>; + pin-pdrv; + gpr = <0x400e4050 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_ccm_enet_ref_clk_25m: IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M { + pinmux = <0x400e80b8 1 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexpwm3_pwm0_a: IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A { + pinmux = <0x400e80b8 11 0x400e8530 1 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_flexspi2_b_data06: IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 { + pinmux = <0x400e80b8 4 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio8_io10: IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 { + pinmux = <0x400e80b8 10 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_gpio_mux2_io10_cm7: IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10_CM7 { + pinmux = <0x400e80b8 5 0x0 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e40a0 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpi2c2_scl: IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL { + pinmux = <0x400e80b8 9 0x400e85b4 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpspi1_sck: IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK { + pinmux = <0x400e80b8 8 0x400e85d0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_lpuart6_cts_b: IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B { + pinmux = <0x400e80b8 3 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_00_QTIMER3_TIMER1 { + pinmux = <0x400e80b8 2 0x400e8658 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_semc_data16: IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 { + pinmux = <0x400e80b8 0 0x0 0 0x400e82fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_in20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_00_xbar1_xbar_inout20: IOMUXC_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e80b8 6 0x400e86d8 0 0x400e82fc>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexpwm3_pwm0_b: IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B { + pinmux = <0x400e80bc 11 0x400e8540 1 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_flexspi2_b_data05: IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 { + pinmux = <0x400e80bc 4 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio8_io11: IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 { + pinmux = <0x400e80bc 10 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_gpio_mux2_io11_cm7: IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11_CM7 { + pinmux = <0x400e80bc 5 0x0 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e40a0 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpi2c2_sda: IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA { + pinmux = <0x400e80bc 9 0x400e85b8 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpspi1_pcs0: IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 { + pinmux = <0x400e80bc 8 0x400e85cc 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_lpuart6_rts_b: IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B { + pinmux = <0x400e80bc 3 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_qtimer4_timer1: IOMUXC_GPIO_EMC_B2_01_QTIMER4_TIMER1 { + pinmux = <0x400e80bc 2 0x400e8664 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e403c 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_semc_data17: IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 { + pinmux = <0x400e80bc 0 0x0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_usdhc2_cd_b: IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B { + pinmux = <0x400e80bc 1 0x400e86d0 0 0x400e8300>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_in21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_01_xbar1_xbar_inout21: IOMUXC_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e80bc 6 0x400e86dc 0 0x400e8300>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexpwm3_pwm1_a: IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A { + pinmux = <0x400e80c0 11 0x400e8534 1 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_flexspi2_b_data04: IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 { + pinmux = <0x400e80c0 4 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio8_io12: IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 { + pinmux = <0x400e80c0 10 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_gpio_mux2_io12_cm7: IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12_CM7 { + pinmux = <0x400e80c0 5 0x0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e40a0 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_lpspi1_sdo: IOMUXC_GPIO_EMC_B2_02_LPSPI1_SDO { + pinmux = <0x400e80c0 8 0x400e85d8 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_semc_data18: IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 { + pinmux = <0x400e80c0 0 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_usdhc2_wp: IOMUXC_GPIO_EMC_B2_02_USDHC2_WP { + pinmux = <0x400e80c0 1 0x400e86d4 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_video_mux_csi_data23: IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 { + pinmux = <0x400e80c0 3 0x0 0 0x400e8304>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_in22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_02_xbar1_xbar_inout22: IOMUXC_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e80c0 6 0x400e86e0 0 0x400e8304>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_enet_1g_tdata03: IOMUXC_GPIO_EMC_B2_03_ENET_1G_TDATA03 { + pinmux = <0x400e80c4 7 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexpwm3_pwm1_b: IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B { + pinmux = <0x400e80c4 11 0x400e8544 1 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_flexspi2_b_data03: IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 { + pinmux = <0x400e80c4 4 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio8_io13: IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 { + pinmux = <0x400e80c4 10 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_gpio_mux2_io13_cm7: IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13_CM7 { + pinmux = <0x400e80c4 5 0x0 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e40a0 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_lpspi1_sdi: IOMUXC_GPIO_EMC_B2_03_LPSPI1_SDI { + pinmux = <0x400e80c4 8 0x400e85d4 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_semc_data19: IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 { + pinmux = <0x400e80c4 0 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_usdhc2_vselect: IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT { + pinmux = <0x400e80c4 1 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_video_mux_csi_data22: IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 { + pinmux = <0x400e80c4 3 0x0 0 0x400e8308>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_in23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_03_xbar1_xbar_inout23: IOMUXC_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e80c4 6 0x400e86e4 0 0x400e8308>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_enet_1g_tdata02: IOMUXC_GPIO_EMC_B2_04_ENET_1G_TDATA02 { + pinmux = <0x400e80c8 7 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexpwm3_pwm2_a: IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A { + pinmux = <0x400e80c8 11 0x400e8538 1 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_flexspi2_b_data02: IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 { + pinmux = <0x400e80c8 4 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio8_io14: IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 { + pinmux = <0x400e80c8 10 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_gpio_mux2_io14_cm7: IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14_CM7 { + pinmux = <0x400e80c8 5 0x0 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e40a0 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_lpspi3_sck: IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK { + pinmux = <0x400e80c8 8 0x400e8600 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_sai2_mclk: IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK { + pinmux = <0x400e80c8 2 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_semc_data20: IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 { + pinmux = <0x400e80c8 0 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_usdhc2_reset_b: IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B { + pinmux = <0x400e80c8 1 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_video_mux_csi_data21: IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 { + pinmux = <0x400e80c8 3 0x0 0 0x400e830c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_in24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_04_xbar1_xbar_inout24: IOMUXC_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e80c8 6 0x400e86e8 0 0x400e830c>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_enet_1g_rx_clk: IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK { + pinmux = <0x400e80cc 7 0x400e84cc 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexpwm3_pwm2_b: IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B { + pinmux = <0x400e80cc 11 0x400e8548 1 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_flexspi2_b_data01: IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 { + pinmux = <0x400e80cc 4 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio8_io15: IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 { + pinmux = <0x400e80cc 10 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpio_mux2_io15_cm7: IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15_CM7 { + pinmux = <0x400e80cc 5 0x0 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e40a0 0xf 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_gpt3_clk: IOMUXC_GPIO_EMC_B2_05_GPT3_CLK { + pinmux = <0x400e80cc 1 0x400e8598 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_lpspi3_pcs0: IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 { + pinmux = <0x400e80cc 8 0x400e85f0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_pit1_trigger00: IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER00 { + pinmux = <0x400e80cc 9 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_sai2_rx_sync: IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC { + pinmux = <0x400e80cc 2 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_semc_data21: IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 { + pinmux = <0x400e80cc 0 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_video_mux_csi_data20: IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 { + pinmux = <0x400e80cc 3 0x0 0 0x400e8310>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_in25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_05_xbar1_xbar_inout25: IOMUXC_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e80cc 6 0x400e86ec 0 0x400e8310>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_enet_1g_tx_er: IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER { + pinmux = <0x400e80d0 7 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexpwm3_pwm3_a: IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A { + pinmux = <0x400e80d0 11 0x400e853c 1 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_flexspi2_b_data00: IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 { + pinmux = <0x400e80d0 4 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio8_io16: IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 { + pinmux = <0x400e80d0 10 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpio_mux2_io16_cm7: IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16_CM7 { + pinmux = <0x400e80d0 5 0x0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e40a4 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_gpt3_capture1: IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 { + pinmux = <0x400e80d0 1 0x400e8590 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_lpspi3_sdo: IOMUXC_GPIO_EMC_B2_06_LPSPI3_SDO { + pinmux = <0x400e80d0 8 0x400e8608 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_pit1_trigger01: IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER01 { + pinmux = <0x400e80d0 9 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_sai2_rx_bclk: IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK { + pinmux = <0x400e80d0 2 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_semc_data22: IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 { + pinmux = <0x400e80d0 0 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_video_mux_csi_data19: IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 { + pinmux = <0x400e80d0 3 0x0 0 0x400e8314>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_in26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_IN26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_06_xbar1_xbar_inout26: IOMUXC_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26 { + pinmux = <0x400e80d0 6 0x400e86f0 0 0x400e8314>; + pin-pdrv; + gpr = <0x400e4050 0x16 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_enet_1g_rdata03: IOMUXC_GPIO_EMC_B2_07_ENET_1G_RDATA03 { + pinmux = <0x400e80d4 7 0x400e84dc 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexpwm3_pwm3_b: IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B { + pinmux = <0x400e80d4 11 0x400e854c 1 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_flexspi2_b_dqs: IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS { + pinmux = <0x400e80d4 4 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio8_io17: IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 { + pinmux = <0x400e80d4 10 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpio_mux2_io17_cm7: IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17_CM7 { + pinmux = <0x400e80d4 5 0x0 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e40a4 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_gpt3_capture2: IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 { + pinmux = <0x400e80d4 1 0x400e8594 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_lpspi3_sdi: IOMUXC_GPIO_EMC_B2_07_LPSPI3_SDI { + pinmux = <0x400e80d4 8 0x400e8604 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_pit1_trigger02: IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER02 { + pinmux = <0x400e80d4 9 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_sai2_rx_data: IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA { + pinmux = <0x400e80d4 2 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_semc_data23: IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 { + pinmux = <0x400e80d4 0 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_video_mux_csi_data18: IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 { + pinmux = <0x400e80d4 3 0x0 0 0x400e8318>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_in27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_IN27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_07_xbar1_xbar_inout27: IOMUXC_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27 { + pinmux = <0x400e80d4 6 0x400e86f4 0 0x400e8318>; + pin-pdrv; + gpr = <0x400e4050 0x17 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_enet_1g_rdata02: IOMUXC_GPIO_EMC_B2_08_ENET_1G_RDATA02 { + pinmux = <0x400e80d8 7 0x400e84d8 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_flexspi2_b_ss0_b: IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B { + pinmux = <0x400e80d8 4 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio8_io18: IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 { + pinmux = <0x400e80d8 10 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpio_mux2_io18_cm7: IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18_CM7 { + pinmux = <0x400e80d8 5 0x0 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e40a4 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_gpt3_compare1: IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 { + pinmux = <0x400e80d8 1 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_lpspi3_pcs1: IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 { + pinmux = <0x400e80d8 8 0x400e85f4 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_pit1_trigger03: IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER03 { + pinmux = <0x400e80d8 9 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_sai2_tx_data: IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA { + pinmux = <0x400e80d8 2 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_semc_dm02: IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 { + pinmux = <0x400e80d8 0 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_video_mux_csi_data17: IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 { + pinmux = <0x400e80d8 3 0x0 0 0x400e831c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_in28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_IN28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_08_xbar1_xbar_inout28: IOMUXC_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28 { + pinmux = <0x400e80d8 6 0x400e86f8 0 0x400e831c>; + pin-pdrv; + gpr = <0x400e4050 0x18 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_enet_1g_crs: IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS { + pinmux = <0x400e80dc 7 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_flexspi2_b_sclk: IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK { + pinmux = <0x400e80dc 4 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio8_io19: IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 { + pinmux = <0x400e80dc 10 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpio_mux2_io19_cm7: IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19_CM7 { + pinmux = <0x400e80dc 5 0x0 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e40a4 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_gpt3_compare2: IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 { + pinmux = <0x400e80dc 1 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_lpspi3_pcs2: IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 { + pinmux = <0x400e80dc 8 0x400e85f8 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_qtimer1_timer0: IOMUXC_GPIO_EMC_B2_09_QTIMER1_TIMER0 { + pinmux = <0x400e80dc 9 0x400e863c 1 0x400e8320>; + pin-pdrv; + gpr = <0x400e4030 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_sai2_tx_bclk: IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK { + pinmux = <0x400e80dc 2 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_semc_data24: IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 { + pinmux = <0x400e80dc 0 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_video_mux_csi_data16: IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 { + pinmux = <0x400e80dc 3 0x0 0 0x400e8320>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_in29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_IN29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_09_xbar1_xbar_inout29: IOMUXC_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29 { + pinmux = <0x400e80dc 6 0x400e86fc 0 0x400e8320>; + pin-pdrv; + gpr = <0x400e4050 0x19 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_enet_1g_col: IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL { + pinmux = <0x400e80e0 7 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_flexspi2_a_sclk: IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK { + pinmux = <0x400e80e0 4 0x400e858c 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio8_io20: IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 { + pinmux = <0x400e80e0 10 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpio_mux2_io20_cm7: IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20_CM7 { + pinmux = <0x400e80e0 5 0x0 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e40a4 0x4 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_gpt3_compare3: IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 { + pinmux = <0x400e80e0 1 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_lpspi3_pcs3: IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 { + pinmux = <0x400e80e0 8 0x400e85fc 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_qtimer1_timer1: IOMUXC_GPIO_EMC_B2_10_QTIMER1_TIMER1 { + pinmux = <0x400e80e0 9 0x400e8640 1 0x400e8324>; + pin-pdrv; + gpr = <0x400e4030 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_sai2_tx_sync: IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC { + pinmux = <0x400e80e0 2 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_semc_data25: IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 { + pinmux = <0x400e80e0 0 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_video_mux_csi_field: IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD { + pinmux = <0x400e80e0 3 0x0 0 0x400e8324>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_in30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_IN30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_10_xbar1_xbar_inout30: IOMUXC_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30 { + pinmux = <0x400e80e0 6 0x400e8700 0 0x400e8324>; + pin-pdrv; + gpr = <0x400e4050 0x1a 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_enet_1g_tdata00: IOMUXC_GPIO_EMC_B2_11_ENET_1G_TDATA00 { + pinmux = <0x400e80e4 2 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_flexspi2_a_ss0_b: IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B { + pinmux = <0x400e80e4 4 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio8_io21: IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 { + pinmux = <0x400e80e4 10 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_gpio_mux2_io21_cm7: IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21_CM7 { + pinmux = <0x400e80e4 5 0x0 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e40a4 0x5 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_qtimer1_timer2: IOMUXC_GPIO_EMC_B2_11_QTIMER1_TIMER2 { + pinmux = <0x400e80e4 9 0x400e8644 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4030 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sai3_rx_sync: IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC { + pinmux = <0x400e80e4 3 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_semc_data26: IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 { + pinmux = <0x400e80e4 0 0x0 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_sim1_trxd: IOMUXC_GPIO_EMC_B2_11_SIM1_TRXD { + pinmux = <0x400e80e4 8 0x400e869c 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_spdif_in: IOMUXC_GPIO_EMC_B2_11_SPDIF_IN { + pinmux = <0x400e80e4 1 0x400e86b4 0 0x400e8328>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_in31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_IN31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_11_xbar1_xbar_inout31: IOMUXC_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31 { + pinmux = <0x400e80e4 6 0x400e8704 0 0x400e8328>; + pin-pdrv; + gpr = <0x400e4050 0x1b 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_enet_1g_tdata01: IOMUXC_GPIO_EMC_B2_12_ENET_1G_TDATA01 { + pinmux = <0x400e80e8 2 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_flexspi2_a_dqs: IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS { + pinmux = <0x400e80e8 4 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio8_io22: IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 { + pinmux = <0x400e80e8 10 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_gpio_mux2_io22_cm7: IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22_CM7 { + pinmux = <0x400e80e8 5 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e40a4 0x6 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_qtimer1_timer3: IOMUXC_GPIO_EMC_B2_12_QTIMER1_TIMER3 { + pinmux = <0x400e80e8 9 0x0 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4030 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sai3_rx_bclk: IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK { + pinmux = <0x400e80e8 3 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_semc_data27: IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 { + pinmux = <0x400e80e8 0 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_sim1_clk: IOMUXC_GPIO_EMC_B2_12_SIM1_CLK { + pinmux = <0x400e80e8 8 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_spdif_out: IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT { + pinmux = <0x400e80e8 1 0x0 0 0x400e832c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_in32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_IN32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_12_xbar1_xbar_inout32: IOMUXC_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32 { + pinmux = <0x400e80e8 6 0x400e8708 0 0x400e832c>; + pin-pdrv; + gpr = <0x400e4054 0x0 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_enet_1g_tx_en: IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN { + pinmux = <0x400e80ec 2 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_flexspi2_a_data00: IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 { + pinmux = <0x400e80ec 4 0x400e857c 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio8_io23: IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 { + pinmux = <0x400e80ec 10 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_gpio_mux2_io23_cm7: IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23_CM7 { + pinmux = <0x400e80ec 5 0x0 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e40a4 0x7 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_qtimer2_timer0: IOMUXC_GPIO_EMC_B2_13_QTIMER2_TIMER0 { + pinmux = <0x400e80ec 9 0x400e8648 1 0x400e8330>; + pin-pdrv; + gpr = <0x400e4034 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sai3_rx_data: IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA { + pinmux = <0x400e80ec 3 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_semc_data28: IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 { + pinmux = <0x400e80ec 0 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_sim1_rst_b: IOMUXC_GPIO_EMC_B2_13_SIM1_RST_B { + pinmux = <0x400e80ec 8 0x0 0 0x400e8330>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_in33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_IN33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_13_xbar1_xbar_inout33: IOMUXC_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33 { + pinmux = <0x400e80ec 6 0x400e870c 0 0x400e8330>; + pin-pdrv; + gpr = <0x400e4054 0x1 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_enet_1g_tx_clk_io: IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO { + pinmux = <0x400e80f0 2 0x400e84e8 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_flexspi2_a_data01: IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 { + pinmux = <0x400e80f0 4 0x400e8580 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio8_io24: IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 { + pinmux = <0x400e80f0 10 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_gpio_mux2_io24_cm7: IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24_CM7 { + pinmux = <0x400e80f0 5 0x0 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e40a4 0x8 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_qtimer2_timer1: IOMUXC_GPIO_EMC_B2_14_QTIMER2_TIMER1 { + pinmux = <0x400e80f0 9 0x400e864c 1 0x400e8334>; + pin-pdrv; + gpr = <0x400e4034 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sai3_tx_data: IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA { + pinmux = <0x400e80f0 3 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_semc_data29: IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 { + pinmux = <0x400e80f0 0 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_sim1_sven: IOMUXC_GPIO_EMC_B2_14_SIM1_SVEN { + pinmux = <0x400e80f0 8 0x0 0 0x400e8334>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_in34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_IN34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_14_xbar1_xbar_inout34: IOMUXC_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34 { + pinmux = <0x400e80f0 6 0x400e8710 0 0x400e8334>; + pin-pdrv; + gpr = <0x400e4054 0x2 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_enet_1g_rdata00: IOMUXC_GPIO_EMC_B2_15_ENET_1G_RDATA00 { + pinmux = <0x400e80f4 2 0x400e84d0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_flexspi2_a_data02: IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 { + pinmux = <0x400e80f4 4 0x400e8584 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio8_io25: IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 { + pinmux = <0x400e80f4 10 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_gpio_mux2_io25_cm7: IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25_CM7 { + pinmux = <0x400e80f4 5 0x0 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e40a4 0x9 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_qtimer2_timer2: IOMUXC_GPIO_EMC_B2_15_QTIMER2_TIMER2 { + pinmux = <0x400e80f4 9 0x400e8650 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4034 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sai3_tx_bclk: IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK { + pinmux = <0x400e80f4 3 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_semc_data30: IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 { + pinmux = <0x400e80f4 0 0x0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_sim1_pd: IOMUXC_GPIO_EMC_B2_15_SIM1_PD { + pinmux = <0x400e80f4 8 0x400e86a0 0 0x400e8338>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_in35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_IN35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_15_xbar1_xbar_inout35: IOMUXC_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35 { + pinmux = <0x400e80f4 6 0x400e8714 0 0x400e8338>; + pin-pdrv; + gpr = <0x400e4054 0x3 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_enet_1g_rdata01: IOMUXC_GPIO_EMC_B2_16_ENET_1G_RDATA01 { + pinmux = <0x400e80f8 2 0x400e84d4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_flexspi2_a_data03: IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 { + pinmux = <0x400e80f8 4 0x400e8588 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio8_io26: IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 { + pinmux = <0x400e80f8 10 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_gpio_mux2_io26_cm7: IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26_CM7 { + pinmux = <0x400e80f8 5 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e40a4 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_qtimer2_timer3: IOMUXC_GPIO_EMC_B2_16_QTIMER2_TIMER3 { + pinmux = <0x400e80f8 9 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4034 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sai3_tx_sync: IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC { + pinmux = <0x400e80f8 3 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_semc_data31: IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 { + pinmux = <0x400e80f8 0 0x0 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_sim1_power_fail: IOMUXC_GPIO_EMC_B2_16_SIM1_POWER_FAIL { + pinmux = <0x400e80f8 8 0x400e86a4 0 0x400e833c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_in14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_IN14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_16_xbar1_xbar_inout14: IOMUXC_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14 { + pinmux = <0x400e80f8 1 0x0 0 0x400e833c>; + pin-pdrv; + gpr = <0x400e4050 0xa 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_enet_1g_rx_en: IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN { + pinmux = <0x400e80fc 2 0x400e84e0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_flexspi2_a_data04: IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 { + pinmux = <0x400e80fc 4 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio8_io27: IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 { + pinmux = <0x400e80fc 10 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_gpio_mux2_io27_cm7: IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27_CM7 { + pinmux = <0x400e80fc 5 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e40a4 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_qtimer3_timer0: IOMUXC_GPIO_EMC_B2_17_QTIMER3_TIMER0 { + pinmux = <0x400e80fc 9 0x400e8654 1 0x400e8340>; + pin-pdrv; + gpr = <0x400e4038 0x8 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_sai3_mclk: IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK { + pinmux = <0x400e80fc 3 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_semc_dm03: IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 { + pinmux = <0x400e80fc 0 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_wdog1_wdog_any: IOMUXC_GPIO_EMC_B2_17_WDOG1_WDOG_ANY { + pinmux = <0x400e80fc 8 0x0 0 0x400e8340>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_in15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_IN15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_17_xbar1_xbar_inout15: IOMUXC_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15 { + pinmux = <0x400e80fc 1 0x0 0 0x400e8340>; + pin-pdrv; + gpr = <0x400e4050 0xb 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_enet_1g_rx_er: IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER { + pinmux = <0x400e8100 2 0x400e84e4 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_ewm_ewm_out_b: IOMUXC_GPIO_EMC_B2_18_EWM_EWM_OUT_B { + pinmux = <0x400e8100 3 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi1_a_dqs: IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS { + pinmux = <0x400e8100 6 0x400e8550 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_flexspi2_a_data05: IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 { + pinmux = <0x400e8100 4 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio8_io28: IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 { + pinmux = <0x400e8100 10 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_gpio_mux2_io28_cm7: IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28_CM7 { + pinmux = <0x400e8100 5 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e40a4 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_qtimer3_timer1: IOMUXC_GPIO_EMC_B2_18_QTIMER3_TIMER1 { + pinmux = <0x400e8100 9 0x400e8658 1 0x400e8344>; + pin-pdrv; + gpr = <0x400e4038 0x9 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_semc_dqs4: IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 { + pinmux = <0x400e8100 0 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_wdog1_wdog_b: IOMUXC_GPIO_EMC_B2_18_WDOG1_WDOG_B { + pinmux = <0x400e8100 8 0x0 0 0x400e8344>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_in16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_IN16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_18_xbar1_xbar_inout16: IOMUXC_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16 { + pinmux = <0x400e8100 1 0x0 0 0x400e8344>; + pin-pdrv; + gpr = <0x400e4050 0xc 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC { + pinmux = <0x400e8104 2 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_1g_ref_clk1: IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK1 { + pinmux = <0x400e8104 3 0x400e84c4 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_enet_mdc: IOMUXC_GPIO_EMC_B2_19_ENET_MDC { + pinmux = <0x400e8104 1 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_flexspi2_a_data06: IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 { + pinmux = <0x400e8104 4 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio8_io29: IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 { + pinmux = <0x400e8104 10 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_gpio_mux2_io29_cm7: IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29_CM7 { + pinmux = <0x400e8104 5 0x0 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e40a4 0xd 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_qtimer3_timer2: IOMUXC_GPIO_EMC_B2_19_QTIMER3_TIMER2 { + pinmux = <0x400e8104 9 0x400e865c 0 0x400e8348>; + pin-pdrv; + gpr = <0x400e4038 0xa 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_19_semc_clkx00: IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 { + pinmux = <0x400e8104 0 0x0 0 0x400e8348>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_1g_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO { + pinmux = <0x400e8108 2 0x400e84c8 1 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_enet_mdio: IOMUXC_GPIO_EMC_B2_20_ENET_MDIO { + pinmux = <0x400e8108 1 0x400e84ac 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_flexspi2_a_data07: IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 { + pinmux = <0x400e8108 4 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio8_io30: IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 { + pinmux = <0x400e8108 10 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_gpio_mux2_io30_cm7: IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30_CM7 { + pinmux = <0x400e8108 5 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e40a4 0xe 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_qtimer3_timer3: IOMUXC_GPIO_EMC_B2_20_QTIMER3_TIMER3 { + pinmux = <0x400e8108 9 0x0 0 0x400e834c>; + pin-pdrv; + gpr = <0x400e4038 0xb 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_emc_b2_20_semc_clkx01: IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 { + pinmux = <0x400e8108 0 0x0 0 0x400e834c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_can3_tx: IOMUXC_LPSR_GPIO_LPSR_00_CAN3_TX { + pinmux = <0x40c08000 0 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_cm4_imxrt_txev: IOMUXC_LPSR_GPIO_LPSR_00_CM4_IMXRT_TXEV { + pinmux = <0x40c08000 3 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio12_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO12_IO00 { + pinmux = <0x40c08000 10 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_gpio_mux6_io00: IOMUXC_LPSR_GPIO_LPSR_00_GPIO_MUX6_IO00 { + pinmux = <0x40c08000 5 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_00_LPUART12_TX { + pinmux = <0x40c08000 6 0x40c080b0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mic_clk: IOMUXC_LPSR_GPIO_LPSR_00_MIC_CLK { + pinmux = <0x40c08000 1 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_mqs_right: IOMUXC_LPSR_GPIO_LPSR_00_MQS_RIGHT { + pinmux = <0x40c08000 2 0x0 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_00_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_00_SAI4_MCLK { + pinmux = <0x40c08000 7 0x40c080c8 0 0x40c08040>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_can3_rx: IOMUXC_LPSR_GPIO_LPSR_01_CAN3_RX { + pinmux = <0x40c08004 0 0x40c08080 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_cm4_imxrt_rxev: IOMUXC_LPSR_GPIO_LPSR_01_CM4_IMXRT_RXEV { + pinmux = <0x40c08004 3 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio12_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO12_IO01 { + pinmux = <0x40c08004 10 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01: IOMUXC_LPSR_GPIO_LPSR_01_GPIO_MUX6_IO01 { + pinmux = <0x40c08004 5 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_01_LPUART12_RX { + pinmux = <0x40c08004 6 0x40c080ac 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_01_MIC_BITSTREAM00 { + pinmux = <0x40c08004 1 0x40c080b4 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_01_mqs_left: IOMUXC_LPSR_GPIO_LPSR_01_MQS_LEFT { + pinmux = <0x40c08004 2 0x0 0 0x40c08044>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio12_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO12_IO02 { + pinmux = <0x40c08008 10 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02: IOMUXC_LPSR_GPIO_LPSR_02_GPIO_MUX6_IO02 { + pinmux = <0x40c08008 5 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_02_LPSPI5_SCK { + pinmux = <0x40c08008 1 0x40c08098 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_mqs_right: IOMUXC_LPSR_GPIO_LPSR_02_MQS_RIGHT { + pinmux = <0x40c08008 3 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_02_SAI4_TX_DATA { + pinmux = <0x40c08008 2 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_02_src_boot_mode00: IOMUXC_LPSR_GPIO_LPSR_02_SRC_BOOT_MODE00 { + pinmux = <0x40c08008 0 0x0 0 0x40c08048>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio12_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO12_IO03 { + pinmux = <0x40c0800c 10 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03: IOMUXC_LPSR_GPIO_LPSR_03_GPIO_MUX6_IO03 { + pinmux = <0x40c0800c 5 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_03_LPSPI5_PCS0 { + pinmux = <0x40c0800c 1 0x40c08094 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_mqs_left: IOMUXC_LPSR_GPIO_LPSR_03_MQS_LEFT { + pinmux = <0x40c0800c 3 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_03_SAI4_TX_SYNC { + pinmux = <0x40c0800c 2 0x40c080dc 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_03_src_boot_mode01: IOMUXC_LPSR_GPIO_LPSR_03_SRC_BOOT_MODE01 { + pinmux = <0x40c0800c 0 0x0 0 0x40c0804c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio12_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO12_IO04 { + pinmux = <0x40c08010 10 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04: IOMUXC_LPSR_GPIO_LPSR_04_GPIO_MUX6_IO04 { + pinmux = <0x40c08010 5 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_04_LPI2C5_SDA { + pinmux = <0x40c08010 0 0x40c08088 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_04_LPSPI5_SDO { + pinmux = <0x40c08010 1 0x40c080a0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_04_LPUART11_TX { + pinmux = <0x40c08010 6 0x40c080a8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_lpuart12_rts_b: IOMUXC_LPSR_GPIO_LPSR_04_LPUART12_RTS_B { + pinmux = <0x40c08010 3 0x0 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_04_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_04_SAI4_TX_BCLK { + pinmux = <0x40c08010 2 0x40c080d8 0 0x40c08050>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio12_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO12_IO05 { + pinmux = <0x40c08014 10 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05: IOMUXC_LPSR_GPIO_LPSR_05_GPIO_MUX6_IO05 { + pinmux = <0x40c08014 5 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_05_LPI2C5_SCL { + pinmux = <0x40c08014 0 0x40c08084 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_05_LPSPI5_SDI { + pinmux = <0x40c08014 1 0x40c0809c 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_05_LPUART11_RX { + pinmux = <0x40c08014 6 0x40c080a4 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_lpuart12_cts_b: IOMUXC_LPSR_GPIO_LPSR_05_LPUART12_CTS_B { + pinmux = <0x40c08014 3 0x0 0 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_05_sai4_mclk: IOMUXC_LPSR_GPIO_LPSR_05_SAI4_MCLK { + pinmux = <0x40c08014 2 0x40c080c8 1 0x40c08054>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_can3_tx: IOMUXC_LPSR_GPIO_LPSR_06_CAN3_TX { + pinmux = <0x40c08018 6 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio12_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO12_IO06 { + pinmux = <0x40c08018 10 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06: IOMUXC_LPSR_GPIO_LPSR_06_GPIO_MUX6_IO06 { + pinmux = <0x40c08018 5 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_06_LPI2C6_SDA { + pinmux = <0x40c08018 0 0x40c08090 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi5_pcs1: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI5_PCS1 { + pinmux = <0x40c08018 8 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpspi6_pcs3: IOMUXC_LPSR_GPIO_LPSR_06_LPSPI6_PCS3 { + pinmux = <0x40c08018 4 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_06_LPUART12_TX { + pinmux = <0x40c08018 3 0x40c080b0 1 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_06_PIT2_TRIGGER03 { + pinmux = <0x40c08018 7 0x0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_06_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_06_SAI4_RX_DATA { + pinmux = <0x40c08018 2 0x40c080d0 0 0x40c08058>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_can3_rx: IOMUXC_LPSR_GPIO_LPSR_07_CAN3_RX { + pinmux = <0x40c0801c 6 0x40c08080 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio12_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO12_IO07 { + pinmux = <0x40c0801c 10 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07: IOMUXC_LPSR_GPIO_LPSR_07_GPIO_MUX6_IO07 { + pinmux = <0x40c0801c 5 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_07_LPI2C6_SCL { + pinmux = <0x40c0801c 0 0x40c0808c 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi5_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI5_PCS2 { + pinmux = <0x40c0801c 8 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpspi6_pcs2: IOMUXC_LPSR_GPIO_LPSR_07_LPSPI6_PCS2 { + pinmux = <0x40c0801c 4 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_07_LPUART12_RX { + pinmux = <0x40c0801c 3 0x40c080ac 1 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_07_PIT2_TRIGGER02 { + pinmux = <0x40c0801c 7 0x0 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_07_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_07_SAI4_RX_BCLK { + pinmux = <0x40c0801c 2 0x40c080cc 0 0x40c0805c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_can3_tx: IOMUXC_LPSR_GPIO_LPSR_08_CAN3_TX { + pinmux = <0x40c08020 1 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio12_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO12_IO08 { + pinmux = <0x40c08020 10 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08: IOMUXC_LPSR_GPIO_LPSR_08_GPIO_MUX6_IO08 { + pinmux = <0x40c08020 5 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpi2c5_sda: IOMUXC_LPSR_GPIO_LPSR_08_LPI2C5_SDA { + pinmux = <0x40c08020 6 0x40c08088 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi5_pcs3: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI5_PCS3 { + pinmux = <0x40c08020 8 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpspi6_pcs1: IOMUXC_LPSR_GPIO_LPSR_08_LPSPI6_PCS1 { + pinmux = <0x40c08020 4 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_lpuart11_tx: IOMUXC_LPSR_GPIO_LPSR_08_LPUART11_TX { + pinmux = <0x40c08020 0 0x40c080a8 1 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_mic_clk: IOMUXC_LPSR_GPIO_LPSR_08_MIC_CLK { + pinmux = <0x40c08020 3 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_08_PIT2_TRIGGER01 { + pinmux = <0x40c08020 7 0x0 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_08_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_08_SAI4_RX_SYNC { + pinmux = <0x40c08020 2 0x40c080d4 0 0x40c08060>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_can3_rx: IOMUXC_LPSR_GPIO_LPSR_09_CAN3_RX { + pinmux = <0x40c08024 1 0x40c08080 2 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio12_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO12_IO09 { + pinmux = <0x40c08024 10 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09: IOMUXC_LPSR_GPIO_LPSR_09_GPIO_MUX6_IO09 { + pinmux = <0x40c08024 5 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpi2c5_scl: IOMUXC_LPSR_GPIO_LPSR_09_LPI2C5_SCL { + pinmux = <0x40c08024 6 0x40c08084 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpspi6_pcs0: IOMUXC_LPSR_GPIO_LPSR_09_LPSPI6_PCS0 { + pinmux = <0x40c08024 4 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_lpuart11_rx: IOMUXC_LPSR_GPIO_LPSR_09_LPUART11_RX { + pinmux = <0x40c08024 0 0x40c080a4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_mic_bitstream00: IOMUXC_LPSR_GPIO_LPSR_09_MIC_BITSTREAM00 { + pinmux = <0x40c08024 3 0x40c080b4 1 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_09_PIT2_TRIGGER00 { + pinmux = <0x40c08024 2 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_09_sai4_tx_data: IOMUXC_LPSR_GPIO_LPSR_09_SAI4_TX_DATA { + pinmux = <0x40c08024 7 0x0 0 0x40c08064>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio12_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO12_IO10 { + pinmux = <0x40c08028 10 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10: IOMUXC_LPSR_GPIO_LPSR_10_GPIO_MUX6_IO10 { + pinmux = <0x40c08028 5 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_jtag_mux_trstb: IOMUXC_LPSR_GPIO_LPSR_10_JTAG_MUX_TRSTB { + pinmux = <0x40c08028 0 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c5_scls: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C5_SCLS { + pinmux = <0x40c08028 6 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpi2c6_sda: IOMUXC_LPSR_GPIO_LPSR_10_LPI2C6_SDA { + pinmux = <0x40c08028 2 0x40c08090 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpspi6_sck: IOMUXC_LPSR_GPIO_LPSR_10_LPSPI6_SCK { + pinmux = <0x40c08028 4 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart11_cts_b: IOMUXC_LPSR_GPIO_LPSR_10_LPUART11_CTS_B { + pinmux = <0x40c08028 1 0x0 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_lpuart12_tx: IOMUXC_LPSR_GPIO_LPSR_10_LPUART12_TX { + pinmux = <0x40c08028 8 0x40c080b0 2 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_10_MIC_BITSTREAM01 { + pinmux = <0x40c08028 3 0x40c080b8 0 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_10_sai4_tx_sync: IOMUXC_LPSR_GPIO_LPSR_10_SAI4_TX_SYNC { + pinmux = <0x40c08028 7 0x40c080dc 1 0x40c08068>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_arm_trace_swo: IOMUXC_LPSR_GPIO_LPSR_11_ARM_TRACE_SWO { + pinmux = <0x40c0802c 7 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio12_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO12_IO11 { + pinmux = <0x40c0802c 10 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11: IOMUXC_LPSR_GPIO_LPSR_11_GPIO_MUX6_IO11 { + pinmux = <0x40c0802c 5 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_jtag_mux_tdo: IOMUXC_LPSR_GPIO_LPSR_11_JTAG_MUX_TDO { + pinmux = <0x40c0802c 0 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c5_sdas: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C5_SDAS { + pinmux = <0x40c0802c 6 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpi2c6_scl: IOMUXC_LPSR_GPIO_LPSR_11_LPI2C6_SCL { + pinmux = <0x40c0802c 2 0x40c0808c 1 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpspi6_sdo: IOMUXC_LPSR_GPIO_LPSR_11_LPSPI6_SDO { + pinmux = <0x40c0802c 4 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart11_rts_b: IOMUXC_LPSR_GPIO_LPSR_11_LPUART11_RTS_B { + pinmux = <0x40c0802c 1 0x0 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_lpuart12_rx: IOMUXC_LPSR_GPIO_LPSR_11_LPUART12_RX { + pinmux = <0x40c0802c 8 0x40c080ac 2 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_11_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_11_MIC_BITSTREAM02 { + pinmux = <0x40c0802c 3 0x40c080bc 0 0x40c0806c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio12_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO12_IO12 { + pinmux = <0x40c08030 10 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12: IOMUXC_LPSR_GPIO_LPSR_12_GPIO_MUX6_IO12 { + pinmux = <0x40c08030 5 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_jtag_mux_tdi: IOMUXC_LPSR_GPIO_LPSR_12_JTAG_MUX_TDI { + pinmux = <0x40c08030 0 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpi2c5_hreq: IOMUXC_LPSR_GPIO_LPSR_12_LPI2C5_HREQ { + pinmux = <0x40c08030 6 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi5_sck: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI5_SCK { + pinmux = <0x40c08030 8 0x40c08098 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_lpspi6_sdi: IOMUXC_LPSR_GPIO_LPSR_12_LPSPI6_SDI { + pinmux = <0x40c08030 4 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_12_MIC_BITSTREAM03 { + pinmux = <0x40c08030 3 0x40c080c0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_pit2_trigger00: IOMUXC_LPSR_GPIO_LPSR_12_PIT2_TRIGGER00 { + pinmux = <0x40c08030 1 0x0 0 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_12_sai4_tx_bclk: IOMUXC_LPSR_GPIO_LPSR_12_SAI4_TX_BCLK { + pinmux = <0x40c08030 7 0x40c080d8 1 0x40c08070>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio12_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO12_IO13 { + pinmux = <0x40c08034 10 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13: IOMUXC_LPSR_GPIO_LPSR_13_GPIO_MUX6_IO13 { + pinmux = <0x40c08034 5 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_jtag_mux_mod: IOMUXC_LPSR_GPIO_LPSR_13_JTAG_MUX_MOD { + pinmux = <0x40c08034 0 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_lpspi5_pcs0: IOMUXC_LPSR_GPIO_LPSR_13_LPSPI5_PCS0 { + pinmux = <0x40c08034 8 0x40c08094 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_mic_bitstream01: IOMUXC_LPSR_GPIO_LPSR_13_MIC_BITSTREAM01 { + pinmux = <0x40c08034 1 0x40c080b8 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_pit2_trigger01: IOMUXC_LPSR_GPIO_LPSR_13_PIT2_TRIGGER01 { + pinmux = <0x40c08034 2 0x0 0 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_13_sai4_rx_data: IOMUXC_LPSR_GPIO_LPSR_13_SAI4_RX_DATA { + pinmux = <0x40c08034 7 0x40c080d0 1 0x40c08074>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio12_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO12_IO14 { + pinmux = <0x40c08038 10 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14: IOMUXC_LPSR_GPIO_LPSR_14_GPIO_MUX6_IO14 { + pinmux = <0x40c08038 5 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_jtag_mux_tck: IOMUXC_LPSR_GPIO_LPSR_14_JTAG_MUX_TCK { + pinmux = <0x40c08038 0 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_lpspi5_sdo: IOMUXC_LPSR_GPIO_LPSR_14_LPSPI5_SDO { + pinmux = <0x40c08038 8 0x40c080a0 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_mic_bitstream02: IOMUXC_LPSR_GPIO_LPSR_14_MIC_BITSTREAM02 { + pinmux = <0x40c08038 1 0x40c080bc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_pit2_trigger02: IOMUXC_LPSR_GPIO_LPSR_14_PIT2_TRIGGER02 { + pinmux = <0x40c08038 2 0x0 0 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_14_sai4_rx_bclk: IOMUXC_LPSR_GPIO_LPSR_14_SAI4_RX_BCLK { + pinmux = <0x40c08038 7 0x40c080cc 1 0x40c08078>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio12_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO12_IO15 { + pinmux = <0x40c0803c 10 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15: IOMUXC_LPSR_GPIO_LPSR_15_GPIO_MUX6_IO15 { + pinmux = <0x40c0803c 5 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_jtag_mux_tms: IOMUXC_LPSR_GPIO_LPSR_15_JTAG_MUX_TMS { + pinmux = <0x40c0803c 0 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_lpspi5_sdi: IOMUXC_LPSR_GPIO_LPSR_15_LPSPI5_SDI { + pinmux = <0x40c0803c 8 0x40c0809c 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_mic_bitstream03: IOMUXC_LPSR_GPIO_LPSR_15_MIC_BITSTREAM03 { + pinmux = <0x40c0803c 1 0x40c080c0 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_pit2_trigger03: IOMUXC_LPSR_GPIO_LPSR_15_PIT2_TRIGGER03 { + pinmux = <0x40c0803c 2 0x0 0 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_lpsr_gpio_lpsr_15_sai4_rx_sync: IOMUXC_LPSR_GPIO_LPSR_15_SAI4_RX_SYNC { + pinmux = <0x40c0803c 7 0x40c080d4 1 0x40c0807c>; + pin-lpsr; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_flexspi2_a_ss0_b: IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B { + pinmux = <0x400e819c 6 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio10_io03: IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 { + pinmux = <0x400e819c 10 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpio_mux4_io03: IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 { + pinmux = <0x400e819c 5 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_gpt4_capture1: IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 { + pinmux = <0x400e819c 3 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_kpp_row07: IOMUXC_GPIO_SD_B1_00_KPP_ROW07 { + pinmux = <0x400e819c 8 0x400e85a8 1 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_usdhc1_cmd: IOMUXC_GPIO_SD_B1_00_USDHC1_CMD { + pinmux = <0x400e819c 0 0x0 0 0x400e83e0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_in20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_IN20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_00_xbar1_xbar_inout20: IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20 { + pinmux = <0x400e819c 2 0x400e86d8 1 0x400e83e0>; + pin-pdrv; + gpr = <0x400e4050 0x10 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_flexspi2_a_sclk: IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK { + pinmux = <0x400e81a0 6 0x400e858c 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio10_io04: IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 { + pinmux = <0x400e81a0 10 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpio_mux4_io04: IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 { + pinmux = <0x400e81a0 5 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_gpt4_capture2: IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 { + pinmux = <0x400e81a0 3 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_kpp_col07: IOMUXC_GPIO_SD_B1_01_KPP_COL07 { + pinmux = <0x400e81a0 8 0x400e85a0 1 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_usdhc1_clk: IOMUXC_GPIO_SD_B1_01_USDHC1_CLK { + pinmux = <0x400e81a0 0 0x0 0 0x400e83e4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_in21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_IN21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_01_xbar1_xbar_inout21: IOMUXC_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21 { + pinmux = <0x400e81a0 2 0x400e86dc 1 0x400e83e4>; + pin-pdrv; + gpr = <0x400e4050 0x11 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81a4 9 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_flexspi2_a_data00: IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 { + pinmux = <0x400e81a4 6 0x400e857c 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio10_io05: IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 { + pinmux = <0x400e81a4 10 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpio_mux4_io05: IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 { + pinmux = <0x400e81a4 5 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_gpt4_compare1: IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 { + pinmux = <0x400e81a4 3 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_kpp_row06: IOMUXC_GPIO_SD_B1_02_KPP_ROW06 { + pinmux = <0x400e81a4 8 0x400e85a4 1 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_usdhc1_data0: IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 { + pinmux = <0x400e81a4 0 0x0 0 0x400e83e8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_in22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_IN22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_02_xbar1_xbar_inout22: IOMUXC_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22 { + pinmux = <0x400e81a4 2 0x400e86e0 1 0x400e83e8>; + pin-pdrv; + gpr = <0x400e4050 0x12 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi1_b_ss1_b: IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B { + pinmux = <0x400e81a8 9 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_flexspi2_a_data01: IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 { + pinmux = <0x400e81a8 6 0x400e8580 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio10_io06: IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 { + pinmux = <0x400e81a8 10 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpio_mux4_io06: IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 { + pinmux = <0x400e81a8 5 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_gpt4_compare2: IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 { + pinmux = <0x400e81a8 3 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_kpp_col06: IOMUXC_GPIO_SD_B1_03_KPP_COL06 { + pinmux = <0x400e81a8 8 0x400e859c 1 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_usdhc1_data1: IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 { + pinmux = <0x400e81a8 0 0x0 0 0x400e83ec>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_in23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_IN23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_03_xbar1_xbar_inout23: IOMUXC_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23 { + pinmux = <0x400e81a8 2 0x400e86e4 1 0x400e83ec>; + pin-pdrv; + gpr = <0x400e4050 0x13 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81ac 8 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_flexspi2_a_data02: IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 { + pinmux = <0x400e81ac 6 0x400e8584 1 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio10_io07: IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 { + pinmux = <0x400e81ac 10 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpio_mux4_io07: IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 { + pinmux = <0x400e81ac 5 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_gpt4_compare3: IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 { + pinmux = <0x400e81ac 3 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_usdhc1_data2: IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 { + pinmux = <0x400e81ac 0 0x0 0 0x400e83f0>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_in24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_IN24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_04_xbar1_xbar_inout24: IOMUXC_GPIO_SD_B1_04_XBAR1_XBAR_INOUT24 { + pinmux = <0x400e81ac 2 0x400e86e8 1 0x400e83f0>; + pin-pdrv; + gpr = <0x400e4050 0x14 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi1_b_dqs: IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS { + pinmux = <0x400e81b0 8 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_flexspi2_a_data03: IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 { + pinmux = <0x400e81b0 6 0x400e8588 1 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio10_io08: IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 { + pinmux = <0x400e81b0 10 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpio_mux4_io08: IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 { + pinmux = <0x400e81b0 5 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_gpt4_clk: IOMUXC_GPIO_SD_B1_05_GPT4_CLK { + pinmux = <0x400e81b0 3 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_usdhc1_data3: IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 { + pinmux = <0x400e81b0 0 0x0 0 0x400e83f4>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_in25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_IN25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x0>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b1_05_xbar1_xbar_inout25: IOMUXC_GPIO_SD_B1_05_XBAR1_XBAR_INOUT25 { + pinmux = <0x400e81b0 2 0x400e86ec 1 0x400e83f4>; + pin-pdrv; + gpr = <0x400e4050 0x15 0x1>; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_enet_1g_rx_en: IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN { + pinmux = <0x400e81b4 2 0x400e84e0 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_flexspi1_b_data03: IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 { + pinmux = <0x400e81b4 1 0x400e8570 1 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio10_io09: IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 { + pinmux = <0x400e81b4 10 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_gpio_mux4_io09: IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 { + pinmux = <0x400e81b4 5 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpspi4_sck: IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK { + pinmux = <0x400e81b4 4 0x400e8610 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_lpuart9_tx: IOMUXC_GPIO_SD_B2_00_LPUART9_TX { + pinmux = <0x400e81b4 3 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_00_usdhc2_data3: IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 { + pinmux = <0x400e81b4 0 0x0 0 0x400e83f8>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_enet_1g_rx_clk: IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK { + pinmux = <0x400e81b8 2 0x400e84cc 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_flexspi1_b_data02: IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 { + pinmux = <0x400e81b8 1 0x400e856c 1 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio10_io10: IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 { + pinmux = <0x400e81b8 10 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_gpio_mux4_io10: IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 { + pinmux = <0x400e81b8 5 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpspi4_pcs0: IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 { + pinmux = <0x400e81b8 4 0x400e860c 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_lpuart9_rx: IOMUXC_GPIO_SD_B2_01_LPUART9_RX { + pinmux = <0x400e81b8 3 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_01_usdhc2_data2: IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 { + pinmux = <0x400e81b8 0 0x0 0 0x400e83fc>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_enet_1g_rdata00: IOMUXC_GPIO_SD_B2_02_ENET_1G_RDATA00 { + pinmux = <0x400e81bc 2 0x400e84d0 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_flexspi1_b_data01: IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 { + pinmux = <0x400e81bc 1 0x400e8568 1 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio10_io11: IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 { + pinmux = <0x400e81bc 10 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_gpio_mux4_io11: IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 { + pinmux = <0x400e81bc 5 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpspi4_sdo: IOMUXC_GPIO_SD_B2_02_LPSPI4_SDO { + pinmux = <0x400e81bc 4 0x400e8618 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_lpuart9_cts_b: IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B { + pinmux = <0x400e81bc 3 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_02_usdhc2_data1: IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 { + pinmux = <0x400e81bc 0 0x0 0 0x400e8400>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_enet_1g_rdata01: IOMUXC_GPIO_SD_B2_03_ENET_1G_RDATA01 { + pinmux = <0x400e81c0 2 0x400e84d4 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_flexspi1_b_data00: IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 { + pinmux = <0x400e81c0 1 0x400e8564 1 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio10_io12: IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 { + pinmux = <0x400e81c0 10 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_gpio_mux4_io12: IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 { + pinmux = <0x400e81c0 5 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpspi4_sdi: IOMUXC_GPIO_SD_B2_03_LPSPI4_SDI { + pinmux = <0x400e81c0 4 0x400e8614 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_lpuart9_rts_b: IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B { + pinmux = <0x400e81c0 3 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_03_usdhc2_data0: IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 { + pinmux = <0x400e81c0 0 0x0 0 0x400e8404>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_enet_1g_rdata02: IOMUXC_GPIO_SD_B2_04_ENET_1G_RDATA02 { + pinmux = <0x400e81c4 2 0x400e84d8 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_a_ss1_b: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B { + pinmux = <0x400e81c4 3 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_flexspi1_b_sclk: IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK { + pinmux = <0x400e81c4 1 0x400e8578 1 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio10_io13: IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 { + pinmux = <0x400e81c4 10 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_gpio_mux4_io13: IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 { + pinmux = <0x400e81c4 5 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_lpspi4_pcs1: IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 { + pinmux = <0x400e81c4 4 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_04_usdhc2_clk: IOMUXC_GPIO_SD_B2_04_USDHC2_CLK { + pinmux = <0x400e81c4 0 0x0 0 0x400e8408>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_enet_1g_rdata03: IOMUXC_GPIO_SD_B2_05_ENET_1G_RDATA03 { + pinmux = <0x400e81c8 2 0x400e84dc 1 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_a_dqs: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS { + pinmux = <0x400e81c8 1 0x400e8550 2 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_flexspi1_b_ss0_b: IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B { + pinmux = <0x400e81c8 3 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio10_io14: IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 { + pinmux = <0x400e81c8 10 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_gpio_mux4_io14: IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 { + pinmux = <0x400e81c8 5 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_lpspi4_pcs2: IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 { + pinmux = <0x400e81c8 4 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_05_usdhc2_cmd: IOMUXC_GPIO_SD_B2_05_USDHC2_CMD { + pinmux = <0x400e81c8 0 0x0 0 0x400e840c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_enet_1g_tdata03: IOMUXC_GPIO_SD_B2_06_ENET_1G_TDATA03 { + pinmux = <0x400e81cc 2 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_flexspi1_a_ss0_b: IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B { + pinmux = <0x400e81cc 1 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio10_io15: IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 { + pinmux = <0x400e81cc 10 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpio_mux4_io15: IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 { + pinmux = <0x400e81cc 5 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_gpt6_capture1: IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 { + pinmux = <0x400e81cc 4 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_lpspi4_pcs3: IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 { + pinmux = <0x400e81cc 3 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_06_usdhc2_reset_b: IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B { + pinmux = <0x400e81cc 0 0x0 0 0x400e8410>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_1g_tdata02: IOMUXC_GPIO_SD_B2_07_ENET_1G_TDATA02 { + pinmux = <0x400e81d0 2 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_enet_tx_er: IOMUXC_GPIO_SD_B2_07_ENET_TX_ER { + pinmux = <0x400e81d0 8 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_flexspi1_a_sclk: IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK { + pinmux = <0x400e81d0 1 0x400e8574 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio10_io16: IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 { + pinmux = <0x400e81d0 10 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpio_mux4_io16: IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 { + pinmux = <0x400e81d0 5 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_gpt6_capture2: IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 { + pinmux = <0x400e81d0 4 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpspi2_sck: IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK { + pinmux = <0x400e81d0 6 0x400e85e4 1 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_lpuart3_cts_b: IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B { + pinmux = <0x400e81d0 3 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_07_usdhc2_strobe: IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE { + pinmux = <0x400e81d0 0 0x0 0 0x400e8414>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_enet_1g_tdata01: IOMUXC_GPIO_SD_B2_08_ENET_1G_TDATA01 { + pinmux = <0x400e81d4 2 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_flexspi1_a_data00: IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 { + pinmux = <0x400e81d4 1 0x400e8554 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio10_io17: IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 { + pinmux = <0x400e81d4 10 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpio_mux4_io17: IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 { + pinmux = <0x400e81d4 5 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_gpt6_compare1: IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 { + pinmux = <0x400e81d4 4 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpspi2_pcs0: IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 { + pinmux = <0x400e81d4 6 0x400e85dc 1 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_lpuart3_rts_b: IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B { + pinmux = <0x400e81d4 3 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_08_usdhc2_data4: IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 { + pinmux = <0x400e81d4 0 0x0 0 0x400e8418>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_enet_1g_tdata00: IOMUXC_GPIO_SD_B2_09_ENET_1G_TDATA00 { + pinmux = <0x400e81d8 2 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_flexspi1_a_data01: IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 { + pinmux = <0x400e81d8 1 0x400e8558 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio10_io18: IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 { + pinmux = <0x400e81d8 10 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpio_mux4_io18: IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 { + pinmux = <0x400e81d8 5 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_gpt6_compare2: IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 { + pinmux = <0x400e81d8 4 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpspi2_sdo: IOMUXC_GPIO_SD_B2_09_LPSPI2_SDO { + pinmux = <0x400e81d8 6 0x400e85ec 1 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_lpuart5_cts_b: IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B { + pinmux = <0x400e81d8 3 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_09_usdhc2_data5: IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 { + pinmux = <0x400e81d8 0 0x0 0 0x400e841c>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_enet_1g_tx_en: IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN { + pinmux = <0x400e81dc 2 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_flexspi1_a_data02: IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 { + pinmux = <0x400e81dc 1 0x400e855c 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio10_io19: IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 { + pinmux = <0x400e81dc 10 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpio_mux4_io19: IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 { + pinmux = <0x400e81dc 5 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_gpt6_compare3: IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 { + pinmux = <0x400e81dc 4 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpspi2_sdi: IOMUXC_GPIO_SD_B2_10_LPSPI2_SDI { + pinmux = <0x400e81dc 6 0x400e85e8 1 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_lpuart5_rts_b: IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B { + pinmux = <0x400e81dc 3 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_10_usdhc2_data6: IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 { + pinmux = <0x400e81dc 0 0x0 0 0x400e8420>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_ref_clk1: IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK1 { + pinmux = <0x400e81e0 3 0x400e84c4 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_enet_1g_tx_clk_io: IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO { + pinmux = <0x400e81e0 2 0x400e84e8 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_flexspi1_a_data03: IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 { + pinmux = <0x400e81e0 1 0x400e8560 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio10_io20: IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 { + pinmux = <0x400e81e0 10 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpio_mux4_io20: IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 { + pinmux = <0x400e81e0 5 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_gpt6_clk: IOMUXC_GPIO_SD_B2_11_GPT6_CLK { + pinmux = <0x400e81e0 4 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_lpspi2_pcs1: IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 { + pinmux = <0x400e81e0 6 0x400e85e0 1 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_gpio_sd_b2_11_usdhc2_data7: IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 { + pinmux = <0x400e81e0 0 0x0 0 0x400e8424>; + pin-pdrv; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03: IOMUXC_SNVS_GPIO_SNVS_00_DIG_GPIO13_IO03 { + pinmux = <0x40c9400c 5 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_00_dig_snvs_lp_tamper00: IOMUXC_SNVS_GPIO_SNVS_00_DIG_SNVS_LP_TAMPER00 { + pinmux = <0x40c9400c 0 0x0 0 0x40c9404c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04: IOMUXC_SNVS_GPIO_SNVS_01_DIG_GPIO13_IO04 { + pinmux = <0x40c94010 5 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_01_dig_snvs_lp_tamper01: IOMUXC_SNVS_GPIO_SNVS_01_DIG_SNVS_LP_TAMPER01 { + pinmux = <0x40c94010 0 0x0 0 0x40c94050>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05: IOMUXC_SNVS_GPIO_SNVS_02_DIG_GPIO13_IO05 { + pinmux = <0x40c94014 5 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_02_dig_snvs_lp_tamper02: IOMUXC_SNVS_GPIO_SNVS_02_DIG_SNVS_LP_TAMPER02 { + pinmux = <0x40c94014 0 0x0 0 0x40c94054>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06: IOMUXC_SNVS_GPIO_SNVS_03_DIG_GPIO13_IO06 { + pinmux = <0x40c94018 5 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_03_dig_snvs_lp_tamper03: IOMUXC_SNVS_GPIO_SNVS_03_DIG_SNVS_LP_TAMPER03 { + pinmux = <0x40c94018 0 0x0 0 0x40c94058>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07: IOMUXC_SNVS_GPIO_SNVS_04_DIG_GPIO13_IO07 { + pinmux = <0x40c9401c 5 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_04_dig_snvs_lp_tamper04: IOMUXC_SNVS_GPIO_SNVS_04_DIG_SNVS_LP_TAMPER04 { + pinmux = <0x40c9401c 0 0x0 0 0x40c9405c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08: IOMUXC_SNVS_GPIO_SNVS_05_DIG_GPIO13_IO08 { + pinmux = <0x40c94020 5 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_05_dig_snvs_lp_tamper05: IOMUXC_SNVS_GPIO_SNVS_05_DIG_SNVS_LP_TAMPER05 { + pinmux = <0x40c94020 0 0x0 0 0x40c94060>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09: IOMUXC_SNVS_GPIO_SNVS_06_DIG_GPIO13_IO09 { + pinmux = <0x40c94024 5 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_06_dig_snvs_lp_tamper06: IOMUXC_SNVS_GPIO_SNVS_06_DIG_SNVS_LP_TAMPER06 { + pinmux = <0x40c94024 0 0x0 0 0x40c94064>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10: IOMUXC_SNVS_GPIO_SNVS_07_DIG_GPIO13_IO10 { + pinmux = <0x40c94028 5 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_07_dig_snvs_lp_tamper07: IOMUXC_SNVS_GPIO_SNVS_07_DIG_SNVS_LP_TAMPER07 { + pinmux = <0x40c94028 0 0x0 0 0x40c94068>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11: IOMUXC_SNVS_GPIO_SNVS_08_DIG_GPIO13_IO11 { + pinmux = <0x40c9402c 5 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_08_dig_snvs_lp_tamper08: IOMUXC_SNVS_GPIO_SNVS_08_DIG_SNVS_LP_TAMPER08 { + pinmux = <0x40c9402c 0 0x0 0 0x40c9406c>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12: IOMUXC_SNVS_GPIO_SNVS_09_DIG_GPIO13_IO12 { + pinmux = <0x40c94030 5 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_gpio_snvs_09_dig_snvs_lp_tamper09: IOMUXC_SNVS_GPIO_SNVS_09_DIG_SNVS_LP_TAMPER09 { + pinmux = <0x40c94030 0 0x0 0 0x40c94070>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_onoff_dig_src_reset_b: IOMUXC_SNVS_ONOFF_DIG_SRC_RESET_B { + pinmux = <0x0 0 0x0 0 0x40c9403c>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_gpio13_io01: IOMUXC_SNVS_PMIC_ON_REQ_DIG_GPIO13_IO01 { + pinmux = <0x40c94004 5 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_on_req_dig_snvs_lp_pmic_on_req: IOMUXC_SNVS_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ { + pinmux = <0x40c94004 0 0x0 0 0x40c94044>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_gpio13_io02: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_GPIO13_IO02 { + pinmux = <0x40c94008 5 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_pmic_stby_req_dig_pgmc_pmic_vstby_req: IOMUXC_SNVS_PMIC_STBY_REQ_DIG_PGMC_PMIC_VSTBY_REQ { + pinmux = <0x40c94008 0 0x0 0 0x40c94048>; + pin-snvs; + }; + /omit-if-no-ref/ iomuxc_snvs_por_b_dig_src_por_b: IOMUXC_SNVS_POR_B_DIG_SRC_POR_B { + pinmux = <0x0 0 0x0 0 0x40c94038>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_test_mode_dig_test_mode: IOMUXC_SNVS_TEST_MODE_DIG_TEST_MODE { + pinmux = <0x0 0 0x0 0 0x40c94034>; + pin-pue; + }; + /omit-if-no-ref/ iomuxc_snvs_wakeup_dig_gpio13_io00: IOMUXC_SNVS_WAKEUP_DIG_GPIO13_IO00 { + pinmux = <0x40c94000 5 0x0 0 0x40c94040>; + pin-snvs; + }; +}; +